IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 1Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Power MOSFET
FEATURES
• Dynamic dV/dt rating
• Repetitive avalanche rated
• Fast switching
• Ease of paralleling
• Simple drive requirements
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220AB package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220AB contribute to its
wide acceptance throughout the industry.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 14 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).
c. ISD 8.0 A, dI/dt 100 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) 500
RDS(on) ()V
GS = 10 V 0.85
Qg max. (nC) 63
Qgs (nC) 9.3
Qgd (nC) 32
Configuration Single
N-Channel MOSFET
G
D
S
TO-220AB
GD
S
Available
Available
ORDERING INFORMATION
Package TO-220AB
Lead (Pb)-free IRF840PbF
SiHF840-E3
SnPb IRF840
SiHF840
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS ± 20 V
Continuous Drain Current VGS at 10 V TC = 25 °C ID
8.0
ATC = 100 °C 5.1
Pulsed Drain Current a IDM 32
Linear Derating Factor 1.0 W/°C
Single Pulse Avalanche Energy bEAS 510 mJ
Repetitive Avalanche Current aIAR 8.0 A
Repetitive Avalanche Energy a EAR 13 mJ
Maximum Power Dissipation TC = 25 °C PD125 W
Peak Diode Recovery dV/dt cdV/dt 3.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C
Soldering Recommendations (Peak temperature) dfor 10 s 300
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 2Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -62
°C/WCase-to-Sink, Flat, Greased Surface RthCS 0.50 -
Maximum Junction-to-Case (Drain) RthJC -1.0
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.78 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 500 V, VGS = 0 V - - 25 μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 4.8 A b - - 0.85
Forward Transconductance gfs VDS = 50 V, ID = 4.8 A b 4.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 1300 -
pFOutput Capacitance Coss -310-
Reverse Transfer Capacitance Crss -120-
Total Gate Charge Qg
VGS = 10 V ID = 8 A, VDS = 400 V,
see fig. 6 and 13 b
--63
nC Gate-Source Charge Qgs --9.3
Gate-Drain Charge Qgd --32
Turn-On Delay Time td(on)
VDD = 250 V, ID = 8 A
Rg = 9.1 , RD = 31, see fig. 10 b
-14-
ns
Rise Time tr -23-
Turn-Off Delay Time td(off) -49-
Fall Time tf -20-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Gate Input Resistance Rgf = 1 MHz, open drain 0.6 - 2.8
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--8.0
A
Pulsed Diode Forward Current a ISM --32
Body Diode Voltage VSD TJ = 25 °C, IS = 8 A, VGS = 0 V b --2.0V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 8 A, dI/dt = 100 A/μs b - 460 970 ns
Body Diode Reverse Recovery Charge Qrr -4.28.9μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 3Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage
91070_01 VDS, Drain-to-Source Voltage (V)
ID, Drain Current (A)
101
100
100101
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TC = 25 °C
4.5 V
91070_02
101
100
100101
I
D
, Drain Current (A)
4.5 V
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TC = 150 °C
V
DS,
Drain-to-Source Voltage (V)
91070_03
25 °C
150 °C
20 µs Pulse Width
VDS = 50 V
101
100
I
D
, Drain Current (A)
V
GS,
Gate-to-Source Voltage (V)
5678910
4
91070_04
3.0
0.0
0.5
1.0
1.5
2.0
2.5
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
RDS(on), Drain-to-Source On Resistance
(Normalized)
ID = 8.0 A
VGS = 10 V
91070_05
2500
2000
1500
1000
0
500
100101
Capacitance (pF)
V
DS,
Drain-to-Source Voltage (V)
Ciss
Crss
Coss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
91070_06 QG, Total Gate Charge (nC)
VGS, Gate-to-Source Voltage (V)
20
16
12
8
0
4
015 75
6045
30
I
D
= 8.0 A
For test circuit
see figure 13
V
DS
= 250 V
V
DS
= 100 V
V
DS
= 400 V
IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 4Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
91070_07
101
100
VSD, Source-to-Drain Voltage (V)
ISD, Reverse Drain Current (A)
0.4 1.00.80.6
25 °C
150 °C
V
GS
= 0 V
1.4
1.2
91070_09
I
D
, Drain Current (A)
T
C
, Case Temperature (°C)
0.0
2.0
4.0
6.0
8.0
25 1501251007550
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
0 - 0.5
0.2
0.1
0.05
0.02
0.01 Single Pulse
(Thermal Response)
PDM
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Thermal Response (ZthJC)
10-5 10-4 10-3 10-2 0.1 1 10 102
10
1
0.1
10-3
10-2
IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 5Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
R
G
I
AS
0.01 Ω
t
p
D.U.T.
L
VDS
+
-V
DD
10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
91070_12c
Bottom
To p
ID
3.6 A
5.1 A
8.0 A
VDD = 50 V
1200
0
200
400
600
800
1000
25 150
125
10075
50
Starting T
J
, Junction Temperature (°C)
E
AS
, Single Pulse Energy (mJ)
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRF840, SiHF840
www.vishay.com Vishay Siliconix
S16-0754-Rev. D, 02-May-16 6Document Number: 91070
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91070.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 V a
VDD
ISD
Driver gate drive
D.U.T. ISD waveform
D.U.T. VDSwaveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Note
a. VGS = 5 V for logic level devices
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Package Information
www.vishay.com Vishay Siliconix
Revison: 14-Dec-15 1Document Number: 66542
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-220-1
Note
• M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM
M
*
3
2
1
L
L(1)
D
H(1)
Q
Ø P
A
F
J(1)
b(1)
e(1)
e
E
b
C
DIM. MILLIMETERS INCHES
MIN. MAX. MIN. MAX.
A 4.24 4.65 0.167 0.183
b 0.69 1.02 0.027 0.040
b(1) 1.14 1.78 0.045 0.070
c 0.36 0.61 0.014 0.024
D 14.33 15.85 0.564 0.624
E 9.96 10.52 0.392 0.414
e 2.41 2.67 0.095 0.105
e(1) 4.88 5.28 0.192 0.208
F 1.14 1.40 0.045 0.055
H(1) 6.10 6.71 0.240 0.264
J(1) 2.41 2.92 0.095 0.115
L 13.36 14.40 0.526 0.567
L(1) 3.33 4.04 0.131 0.159
Ø P 3.53 3.94 0.139 0.155
Q2.54 3.00 0.100 0.118
ECN: X15-0364-Rev. C, 14-Dec-15
DWG: 6031
Package Picture
ASE Xi’an
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
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