LOGIC DEVICES INC cbE D 2K x 8 Static RAM (Low Se Mm 5565905 0001008 2 72 $6-2 3-72 L6116/L6116L Q 2K x8 Static RAM with Chip Select Powerdown, Output Enable 4 Auto-Powerdown Design 4 Advanced CMOS Technology O High Speed to 10 ns maximum 2 Low Power Operation Active: 250 mW (L6116) typical at 35 ns Standby (typical): 100 wW (L6116) 50 pW (L6116L) { Data Retention at 2 V for Battery Backup Operation Q Plug Compatible with IDT6116, Cypress CY7C128/CY6116 Package Styles Available: * 24-pin Plastic DIP * 24-pin Sidebraze, Hermetic DIP * 24-pin CerDIP * 24-pin Plastic SOIC * 24-pin Plastic SOJ 28-pin Ceramic LCC * 32-pin Ceramic LCC The L6116 and L6116L are high- performance, low-power CMOS static RAM. The storage circuitry is organ- ized as 2048 words by 8 bits per word. The 8 Data In and Data Out signals. share I/O pins, These devices are available in six speeds with maximum access times from 10 ns to 35 ns, Inputs and output are TTL compat- ible. Operation is from a single +5 V power supply. Power cotisumption for the L6116 is 250 mW (typical) at 35 ns. Dissipation drops to 75 mW (typical) for the L6116 and 60 mW (typical) for the L6116L when the memory is deselected (Enable is high). Two standby modes are available. Proprietary Auto-Powerdown circuitry reduces power consuniption automatically during read or write accesses which are longer than the minimum access time, or when the memory is deselected. In addition, data may be retained in inactive e eo W 128x 16x 8 7 wl SY F > MEMORY ROW 3 ARRAY ADDRESS fi 4 ce>} WE ~>] CONTROL ->) 6e> COLUMN SELECT 8 & COLUMN SENSE DATA vo W COLUMN ADDRESS storage with a supply voltage as low as2V. The L6116 and L6116L con: sume only 15 .W and 6 pW (typical) respectively at 3 V, allowing effective battery backup operation. The L6116 and L6116L provide asynchronous (unclocked) operation with matching access and cycle times. An active-low Chip Enable and a three-state I/O bus with a separate Output Enable control simplify the connection of several chips for increased storage capacity. Memory locations are specified on address pins Ao through A10. Reading from a designated location is accomplished by presenting an address and driving CE low while WE remains high. The data in the addressed memory location will then appear on the Data Out pins within one access time. The output pins stay in a high-impedance state when CE or OE is high, or WE is low. Writing to an addressed location is accomplished when the active-low CE and WE inputs are both low. Either signal may be used to terminate the write operation. Data In and Data Out signals have the same polarity. Latchup and static discharge pro- tection are provided on-chip. The L6116 and L6116L can withstand an injection current of up to 200 mA on any pin without damage. Memory Products | DEVIGES INCORPORATED 2-33 LDS.6116-8LOGIC DEVICES INC ebe Dd 2K x 8 Static RAM (Low Power) Me 5565905 0001009 4 L6116/L6116L. T-46-23-12 Storage temperature .... stececvasens 65G to +150C Output current inte low outputs Operating ambient temperature... Vcc supply voltage with respect to ground....... Input signal with respect to ground .. Signa! applied to high impedance output seeeesaereceesconseres 56C to +125C we -0.5 V to +7.0 V nueans esueeue eves -3.0 V to +7.0 V 3.0 V to +7.0V Latchup current vee OPERATING CONDITIONS -To meet spe Mode Active Operation, Commercial Active Operation, Military Data Retention, Commercial Data Retention, Military Temperature Range (Ambient) 0C to +70C 45V<sVocs5.5V -55C to +125C 45V<sVeco<5.5V 0C to +70C 20VsVecs5.5V 20VsVeos5.5V 55C ta +125C Supply Voltage L6i16 L6116L, Symbol Parameter Test Condition Min | Typ| Max | Min | Typ} Max |Unit VoH | Output High Voltage loH = 4.0 mA, Vcc = 4.5 V 2.4 2.4 Vv VoL | Output Low Voltage lot = 8.0 mA 0.4 04/V VIH Input High Voltage 2.0 Voc | 2.0 Veco | V +0.3 +0.3 Vi. | Input Low Voltage (Note 3) ~3.0 0.8 F3.0 081 Vv IIx Input Leakage Current GND s< Vins Vcc =10 +10 |10 +10 | pA toz | Output Leakage Current GND < Vout < Veo, GE = Veco -10 +10 1-10 +10 | pA los Output Short Current VouT = GND, Vcc = Max (Note 4) 350 -350| mA Icc2 Vcc Current, TTL Inactive (Note 7) 15; 30 12] 20 |mA Icos_ | Vcc Current, GMOS Standby | (Note 8) 20| 100 10| 30 | pA Ioc4 Vcc Current, Data Retention | Voc =3.0V (Note 9) 5 | 50 2 |.10 | pA CiN | Input Capacitance Ambient Temp = 25C, Voc = 5.0 V 5 5 pF Cout | Output Capacitance: Test Frequency = 1 MHz (Note 10) 7 7 | pF L6116- Symbol Parameter Test Conditlon 35 25 20 15 12 10 Unit oct | Voc Current, Active | (Note 6) 75 | 100| 125| 160| 200} 220 mA {jen (a fi) (qi) Memory Products OEVICES INCORPORATED 2-34 LDS.6116-Boem pen LOGIC DEVICES INC 2K x 8 Static RAM (Low Power) bE D MM 5565905 0001010 0 my L6116/L6116L T-46~23~12 L6116/1.6116L- 35 25 20 | #15 | 12 10 Symbol Parameter Min] Max{ Min] Max{ Min] Max! Min] Mex| Min] Max! Min] Max] Min) Max tAVAV Read Cycle Time 35 25 20 15 12 10 tavav | Address Valid to Output Valid (13, 14) 35 26 20 16 12 10 taxox | Address Change to Output Change 3 3 3 3 3 3 tclav | Chip Enable Low to Output Valid (13, 15) 35| | 25 20 15 12 10 tcLaz_ | Chip Enable Low to Output Low Z (20, 21) 3 3 3 3 3| 3 tcHaz | Chip Enable High to Output High Z (20, 21) 18 10. 8 8 5 4 toLav | Output Enable Low to Output Valid 15 12 10 8 6 toLaz | Output Enable Low to Output Low Z (20, 21) 0 0 0 0 0 0 toHoz | Output Enable High to Output High Z (20, 21) 12 10 8] 5 5 4 tPu Input Transition to Power Up (10, 19) 0 0 0 0 0 0 fep Power Up to Power Down (10, 19) 35 256 20 20 20 18 tcHvL | Chip Enable High to Data Retention (10) 0 i) 0 0 0 0 ADDRESS DATA VALIO DATA OUT tcraz toa toraz HIGH IMPEDANCE tpy leo HIGH IMPEDANCE DATA RETENTION MODE Veco " 45V 48V 4 sav _. tow. I hi tAVAV CE Viet Vin FesEiz= DEVICES INCORPORATED Memory Products 2-35 LOS.61 16-5LOGIC DEVICES INC GebE D MM 5565905 0001011 2 m@ 2K x 8 Static RAM (Low Power) _ L6116/L6116L L6116/L6116L- Symbol Parameter tAVAV Time tcLew | Chip Enable Low to End of tavVBw to tavew | Address Valid to End of Write Cycle tEWAX to {WLEW | Write Enable Low to End of Write Cycle tOVEW to tewox i End of Write Cycle to Data Change tWHOZ Enable to Low Z (20, 21) to Output High Z (20, 21) - o Oo] |=] a eo] Of @| oO} @ WE DATA IN DATA OUT toew WE ts DATAIN VALIO HIGH IMPEDANCE DATA OUT : lec Memory Products 2-36 LOS.6116-8 DEVICES INCORPORATEDee LOGIC DEVICES INC ebE D 2K x 8 Static RAM (Low Power) M@ 5565905 g00101lc 4 L6116/L6116L T-46-23-12. [NOTES 1, Maximum Ratings indicate stress specifi- cations only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied, Exposure to maximum rating con- ditions for extended periods may affect re- liability of the tested device, 2, The products described by this specifica- tion include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive elec- trical stress values, 3. This product provides hard clamping of transient undershoot. Input levels below ground willbe clamped beginning at-0.6 V. Acurrent in excess of 100 mA is required to reach-2 V. The device can withstand indefi- nite operation with inputs as low as -3 V subject only to power dissipation and bond wire fusing constraints, 4. Duration of the output short circuit should not exceed 30 seconds. 5. A series of normalized curves on pages 2-8 through 2-11 of this data booksupply the designer with typical DC and AC paramet- ric information for Logic Devices Static RAMs. These curves may be used to deter- mine device characteristics at various tem- peratures and voltage levels, 6. Tested with all address and data inputs changing at the maximum cycle rate. The device is continuously enabled for writing, ie., CEs VIL, WE S VIL. Input pulse levels are 0 103.0 V. 7. Tested with outputs open and alladdress and data inputs changing at the maximum read cycle rate, The device is continuously disabled, i.e., CE > VIH. 8, Tested with outputs open and alladdress and data inputs stable. The device is con- tinuously disabled, ie. CE = Vcc, Input levels are within 0.2 V of VCC or ground. 9. Data retention operation requires that VCC never drop below 2.0 V, CE must be 2 Vcc-0.2V. For all other inputs VIN 2 VCC - 0.2 V or VIN $0.2 V is required to ensure full powerdown. 10. These parameters are guaranteed but not 100% tested. 11. Test conditions assume input transition times of less than 3 ns, reference levels of 1.5 V, output loading for specified IOL and IOH plus 30 pF (Fig. 1a), and input pulse levels of 0 to 3.0 V (Fig. 2). 12. Each parameter is shown asa minimum or maximum value. Input requirements are specified from the point of view of the exter- nal system driving the chip. For example, tavew ig specified as a minimum since the external system must supply at least that much time to meet the worst-case require- ments of all parts. Responses from the inter- nal circuitry are specified from the point of view of the device. Access time, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 13, WE is high for the read cycle. 14, The chip is continuously selected (CE low), 18. All address lines are valid prior-to or coincident-with the CE transition to low. 16. The internal write cycle of the memo is defined by the overlap of CE low and low. Both signals must be low to initiate a write, Either signal can terminate a write by going high. The address, data, and control input setup and hold times should be refer- enced fo the signal that falls last or rises first. 17. If WE goes low before or concurrent with CE going low, the output remains ina high impedance state, 18. If CE goes high before or concurrent with WE going high, the output remains in a high impedance state. 19. Powerup from ICC2 to ICCi occurs as a result of any of the following conditions: a. Falling edge of CE. b. Falling edge of WE (CE active). . Transition onany addressline (CE active). d. Transition on any data line (CE and WE active). The device automatically powers down from ICC2 to ICC1 after tev has elapsed from any of the prior conditions. This means that power dissipation is dependent on only cycle rate, and is not on Chip Select pulse width. 20. At any given temperature and voltage condition, output disable time is less than output enable time for any given device, 21. Transition is measured +200 mV from steady state voltage with specified loading in Fig. 1b. This parameter issampled and not 100% tested. 22, Alladdress timings are referenced from the last valid address line to the first transi- tioning address line. 23. CE or WE must be high during address transitions. 24, This productisa very high speed device and care must be taken during testing in order to realize valid test_information. In- adequate attention to setups and proce- dures can cause a good part to be rejected as faulty. Long high inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes di- rectly up to the contactor fingers. A 0.01 pF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper terminations must be used. Ri 4802 +5 V OO OUTPUT , | Ra INCLUDING == 30 pF ee JIG AND SCOPE Ri 4802 BV O-$ wr OUTPUT TT > INCLUDING 5 pF Ra JIG AND 1 in a SCOPE Fiquae 1b. 90% 10 10% <3ns Memory Products 2-37 LDS.6116-BLOGIC DEVICES INC ebE D 2K x 8 Static RAM (Low Power) Me 5565905 0001013 &b L6116/L6116L 24-pin iw (0.3" wide) arti ~~ 24q) veo As({j2 231] As As3 221] Ao As(}4 =. 21f] WE A3G5 20,) OE a2Qe6 = 19[] Ato AiQ]7 16f0 CE Aotja 170) vor vooQs 16[1 "0s vorl}10 18 [) Vos voeTii 14/1) vos eno Ci2 13f) vos 24-pin (0.6" wide) T~46-23-12 arg Ae C As] Age] aac Ag > oS 1. OBNAHPRON vOo C] vor vo2 GND (] 42 _ an 12 ABBE S COST SEaeseq gSegor Plastic DIP (P2) 25ns}] L6116PC- 25 L6116DC or 20 or 18ns| L6116LPC 115 | LtieLDC 25 ns L6116DM 20 ns or 18s L6116LDM L61 16M L61 16L0M a5 25 ns L1 16DME 35 | L6116CME 20 ns 20 or 15ns Let {6LDME 15 | L6116LCME 12 MIL-STO-683. Cone 35 26 ns L6116DMB + 85 | Leti6CMs 20 ns or 20 or 15ns L6116LDMB / 15 | L6116L.CMB 12ns 12 10ns 8ns L6i 16NC ol L6116LNG Letiec L6176LHG L61 16HM L6116LHM L6116HME L6116LHME L61 16HMB L6116LHMB Sidebraze tie DIP (D L6t 161C Lett 16LIC L6116LIM L61 16IME L6116LIME L6116IM f 25 or Lt 1GIMB L6116LIMB DEVICES INCORPORATED Memory Products 1D8.6116-8LOGIC DEVICES INC 2K x 8 Static RAM (Low Power) 2ebE D 24-pin ORDERING INFORMATION CONam han ~o 205 > Donn Onno nh _~ nN 241 Veo 23 3 As 229 Ag 2a WE 209 OE 19 {2 Ato 18 SE 17 [3 WO7 16 vos 3 =) vos Me 5565905 0001014 4 L6116/L6116L T-46~23-12 300" Plastic SO L6116LUG = L6116UC ~- 25 or 20 15 L641 4 ewe L116eLWo Ceramic Leadiess Chip Carrier (K1) L6116KC - or L6116LKC L61 16KM L6116LKM Ceramic Leadless Chip Carrier (K7) Let 1 6TC L6116LTC L1 1eT L6116LTM =fe$5C to4125C: L6116KME or L6116LKME L61 16KMB L6116LKMB L6116TME L6116LTME Lt 16TMB O1 L6116LTMB DEVICES INCORPORATED Memory Products