KSZ8081MNX/KSZ8081RNB
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.4
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August
19, 2015
Revision 1.4
General Description
The KSZ8081 is a single-supply 10Base-T/100Base-TX
Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted
pair (UTP) cable.
The KSZ8081 is a highly-integrated PHY solution. It
reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs and
by integrating a low-noise regulator to supply the 1.2V
core.
The KSZ808 1MNX offer s the Media Inde pendent Inte rface
(MII) and the KSZ8081RNB offers the Reduced Media
Independent Interface (RMII) for direct connection with
MII/RMII-compliant Ethernet MAC processors and
switches.
A 25MHz crystal is used to generate all required clocks,
including the 50MHz RMII reference clock output for the
KSZ8081RNB.
The KSZ8081 provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ8081 I/Os and the
board. Micrel LinkMD® TDR-based cable diagnostics
identify faulty copper cabling.
The KSZ8081MNX and KSZ8081RNB are available in 32-
pin, lead-free QFN packages (see “Ordering Inform ation”).
Datasheets and support documentation are available on
website at: www.micrel.com.
Features
• Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• MII interface support (KSZ8081MNX)
• RMII v1.2 Interface support with a 50MHz reference
clock output to MAC, and an option to input a 50MHz
reference clock (KSZ8081RNB)
• Back-to-back mode support for a 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and en able opt ion
• Auto-negotiation to automatically select the highest link-
up speed (10/100Mbps) and duplex (half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty
copper cabling
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• HBM ESD rating (6kV)
Functional Diagram
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 2 Revision 1.4
Features (Continued)
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for
1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5mm × 5mm) QFN package
Applications
• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer
Ordering Information
Part Number Temperature
Range Package Lead
Finish Description
KSZ8081MNXCA 0°C to +70°C 32-Pin QFN Pb-Free MII, Commercial Temperature.
KSZ8081MNXIA(1) −40°C to +85°C 32-P in QFN Pb-Free MII, Industrial Temperature.
KSZ8081RNBCA 0°C to +70°C 32-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output (power-up default),
Commercial Tem perature.
KSZ8081RNBIA(1) −40°C to +85°C 32-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz
RMII REF_CLK output (power-up default),
Industrial Temperature.
KSZ8081MNX-EVAL KSZ8081MNX Evaluation Board
(Mount ed with KSZ8081MNX device in commercial
temperature)
KSZ8081RNB-EVAL KSZ8081RNB Evaluation Board
(Mount ed with KSZ8081R NB dev ice in commer cia l
temperature)
Note:
1. Contact factory for lead time.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 3 Revision 1.4
Revision History
Revision Date Summary of Changes
1.0 11/5/12 Initial release of datasheet.
1.1 2/6/14
Removed copper wire bonding part numbers from Ordering Information.
Added note for TXC (Pin 22) and Register 16h, Bit [15] regarding a Reserved Factory Mode for
KSZ8081MNX device.
Corrected TXC (Pin 22) pin type for KSZ8081MNX device.
Removed TXC and RXC clock connections for MII Back-to-Back mode. This is a datasheet correction.
There is no change to the silicon.
Added series resistance and load capacitance for the crystal selection criteria.
1.2 12/18/14 Added silver wire bondi ng part numbers to Ordering Information.
Updated Ordering Information to include Ordering Part Number and Device Marking.
1.3
04/14/15
Updated Table 7, add a note for Table 7.
Updated Table 8, updated NAND tree I/O testing descriptions.
Add Max frequency for MDC in MII Management (MIIM) Interface section.
Updated Table 23, add a note for Table 23.
Updated Fig ure 22 and Figure 22 descriptions.
Updated descriptions under Figure 23 for LED strap pins, add a note for F i gure 23.
Fixed the missing value for maximum junction and thermal resistance (θJC).
1.4 08/19/15
Updated descriptions in local loopback section for data loopback path.
Updated Table 17 and Table 21.
Updated Ordering Inform ati on Table.
Updated pin 22 TXC and register 16h bit [15] description for MNX part.
Updated description and add a n equation in LinkMD section.
Add HBM ESD rating in Features.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 4 Revision 1.4
Table of Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration – KSZ8081MNX ......................................................................................................................................... 8
Pin Description – KSZ8081MNX ............................................................................................................................................. 9
Strapping Options – KSZ8081MNX ...................................................................................................................................... 12
Pin Configuration – KSZ8081RNB ........................................................................................................................................ 14
Pin Description – KSZ8081RNB ........................................................................................................................................... 15
Strapping Options – KSZ8081RNB ....................................................................................................................................... 18
Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 19
100Base-TX Transmit ........................................................................................................................................................ 19
100Base-TX Receive ......................................................................................................................................................... 19
Scrambler/De-Scrambler (100Base-TX Only) ................................................................................................................... 19
10Base-T Transmit ............................................................................................................................................................ 19
10Base-T Receive ............................................................................................................................................................. 20
SQE and Jabber Function (10Base-T Only) ...................................................................................................................... 20
PLL Clock Synthesizer ...................................................................................................................................................... 20
Auto-Negotiation ................................................................................................................................................................ 20
MII Interface (KSZ8081MNX Only) ....................................................................................................................................... 22
MII Signal Definition ........................................................................................................................................................... 22
Transmit Clock (TXC) ........................................................................................................................................................ 22
Transmit Enable (TXEN) ................................................................................................................................................... 22
Transmit Data[3:0] (TXD[3:0]) ........................................................................................................................................... 23
Receive Clock (RXC) ......................................................................................................................................................... 23
Receive Data Valid (RXDV) ............................................................................................................................................... 23
Receive Data[3:0] (RXD[3:0]) ............................................................................................................................................ 23
Receive Error (RXER) ....................................................................................................................................................... 23
Carrier Sense (CRS) ......................................................................................................................................................... 23
Collision (COL) .................................................................................................................................................................. 23
MII Signal Diagram ............................................................................................................................................................ 23
RMII Data Interface (KSZ8081RNB Only) ............................................................................................................................ 25
RMII – 25MHz Clock Mode ................................................................................................................................................ 25
RMII – 50MHz Clock Mode ................................................................................................................................................ 25
RMII Signal Definition ........................................................................................................................................................ 25
Reference Clock (REF_CLK) ............................................................................................................................................ 25
Transmit Enable (TXEN) ................................................................................................................................................... 26
Transmit Data[1:0] (TXD[1:0]) ........................................................................................................................................... 26
Carrier Sense/Receive Data Valid (CRS_DV) ................................................................................................................... 26
Receive Data[1:0] (RXD[1:0]) ............................................................................................................................................ 26
Receive Error (RXER) ....................................................................................................................................................... 26
Collision Detection (COL) .................................................................................................................................................. 26
RMII Signal Diagram ......................................................................................................................................................... 26
Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 28
MII Back -to-Back Mode (KSZ8081MNX Only) .................................................................................................................. 28
RMII Back -to-Back Mode (KSZ8081RNB Only) ................................................................................................................ 29
MII Management (MIIM) Interface ......................................................................................................................................... 29
Interrupt (INTRP) ................................................................................................................................................................... 30
HP Auto MDI/MDI-X .............................................................................................................................................................. 30
Straight Cab le .................................................................................................................................................................... 31
Crossover Cable ................................................................................................................................................................ 31
Loopback Mode ..................................................................................................................................................................... 32
Local (Digital) Loopback .................................................................................................................................................... 32
Remote (Analog) Loopback ............................................................................................................................................... 33
LinkMD® Cab le Dia gnos t ic .................................................................................................................................................... 34
Usage ............................................................................................................................................................................. 34
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 5 Revision 1.4
NAND Tree Support .............................................................................................................................................................. 35
NAND Tree I/O Testing ..................................................................................................................................................... 36
Power Management .............................................................................................................................................................. 37
Power-Saving Mode .......................................................................................................................................................... 37
Energy-Detect Power-Down Mode .................................................................................................................................... 37
Power-Down Mode ............................................................................................................................................................ 37
Slow-Oscillator Mode ......................................................................................................................................................... 37
Reference Circuit for Power and Ground Connections ......................................................................................................... 38
Typical Current/Power Consumption .................................................................................................................................... 39
Transceiver (3.3V), Digital I/Os (3.3V) .............................................................................................................................. 39
Transceiver (3.3V), Digital I/Os (2.5V) .............................................................................................................................. 39
Transceiver (3.3V), Digital I/Os (1.8V) .............................................................................................................................. 40
Register Map ......................................................................................................................................................................... 41
Register Description .............................................................................................................................................................. 42
Absolute Maximum Ratings .................................................................................................................................................. 52
Operating Ratings ................................................................................................................................................................. 52
Electrical Characteristics ....................................................................................................................................................... 52
Timing Diagrams ................................................................................................................................................................... 54
MII SQE Timing (10Base-T) .............................................................................................................................................. 54
MII Transmit Timing (10Base-T) ........................................................................................................................................ 55
MII Receive Timing (10Base-T) ......................................................................................................................................... 56
MII Transmit Timing (100Base-TX) ................................................................................................................................... 57
MII Receive Timing (100Base-TX) .................................................................................................................................... 58
RMII Timing ....................................................................................................................................................................... 59
Auto-Negotiation Timing .................................................................................................................................................... 60
MDC/MDIO Timing ............................................................................................................................................................ 61
Power-up/Reset Timing ..................................................................................................................................................... 62
Reset Circuit .......................................................................................................................................................................... 63
Reference Circuits – LED S tr ap -In Pins ................................................................................................................................ 64
Reference Clock – Connection and Selection ...................................................................................................................... 65
Magnetic – Connection and Selection .................................................................................................................................. 66
Package Information and Recommended Land Pattern ....................................................................................................... 68
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 6 Revision 1.4
List of Figures
Figure 1. Auto-Negotiation Flow Chart .................................................................................................................................. 21
Figure 2. KSZ8081MNX MII Interface ................................................................................................................................... 24
Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode) .............................................................................................. 27
Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode) .............................................................................................. 27
Figure 5. KSZ8081 MN X /R NB to KSZ80 81M N X /RNB Bac k-to-Back Copper Repeater ....................................................... 28
Figure 6. T ypical Strai ght C abl e Connec tion ........................................................................................................................ 31
Figure 7. Typical Crossover Cable Connection .................................................................................................................... 31
Figure 8. Local (Digital) Loopback ........................................................................................................................................ 32
Figure 9. Remote (Analog) Loopback ................................................................................................................................... 33
Figure 10. KSZ808 1MN X /R NB Po wer and Gro und Connec tio ns ......................................................................................... 38
Figure 11. MII SQE Tim ing (10Bas e-T) ................................................................................................................................ 54
Figure 12. MII Transmit Timing (10Base-T) .......................................................................................................................... 55
Figure 13. MII Receive Timing (10Base-T) ........................................................................................................................... 56
Figure 14. MII Transmit Timing (100Base-TX) ...................................................................................................................... 57
Figure 15. MII Receive Timing (100Base-TX) ....................................................................................................................... 58
Figure 16. RMII Timing – Data Received from RMII ............................................................................................................. 59
Figure 17. RMII Timing – Data Input to RMII ........................................................................................................................ 59
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 60
Figure 19. MDC/ MDIO Timing ............................................................................................................................................... 61
Figure 20. Power -up/R es et Timing ....................................................................................................................................... 62
Figure 21. Recom mended Res et Circ uit ............................................................................................................................... 63
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 63
Figure 23. Reference Circuits for LED Strapping Pins ......................................................................................................... 64
Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 65
Figure 25. 50MHz Oscillator Reference Clock Connection .................................................................................................. 65
Figure 26. Typical Magnetic Interface Circuit ........................................................................................................................ 66
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 7 Revision 1.4
List of Tables
Table 1. MII Signal Definition ................................................................................................................................................ 22
Table 2. RMII Signal Defintion .............................................................................................................................................. 25
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) ............................................. 28
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ....................................... 29
Table 5. MII Management Frame Format for the KSZ8081MNX/RNB ................................................................................. 30
Table 6. MDI/MDI-X Pin Definition ........................................................................................................................................ 30
Table 7. NAND Tree Test Pin Order for KSZ8081MNX ........................................................................................................ 35
Table 8. NAND Tree Test Pin Order for KSZ8081RNB ........................................................................................................ 36
Table 9. KSZ8081MNX/RNB Power Pin Descriptions .......................................................................................................... 38
Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) ........................................................... 39
Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) ........................................................... 39
Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) ........................................................... 40
Table 13. MII SQE Timing (10Base-T) Parameters .............................................................................................................. 54
Table 14. MII Transmit Timing (10Base-T) Parameters........................................................................................................ 55
Table 15. MII Receive Timing (10Base-T) Parameters......................................................................................................... 56
Table 16. MII Transmit Timing (100Base-TX) Parameters ................................................................................................... 57
Table 17. MII Receive Timing (100Base-TX) Parameters .................................................................................................... 58
Table 18. RMII Timing Parameters – KSZ8081RNB (25MHz input to XI pin, 50MHz output from REF_CLK pin) .............. 59
Table 19. RMII Timing Parameters – KSZ8081RNB (50MHz input to XI pin) ...................................................................... 59
Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 60
Table 21. MDC/MDIO Timing Parameters ............................................................................................................................ 61
Table 22. Power-up/Reset Timing Parameters ..................................................................................................................... 62
Table 23. 25MHz Crystal/Reference Clock Selection Criteria .............................................................................................. 65
Table 24. 50MHz Oscillator/Reference Clock Selection Criteria .......................................................................................... 65
Table 25. Magnetics Selection Criteria ................................................................................................................................. 67
Table 26. Compatible Single-Port 10/100 Magnetics............................................................................................................ 67
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 8 Revision 1.4
Pin Configuration – KSZ8081MNX
32-Pin 5mm × 5mm QFN
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 9 Revision 1.4
Pin Description – KSZ8081MNX
Pin Number Pin Name Type
(2)
Pin Function
1 GND GND Ground
2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8081MNX). Decouple wi th 2.2µF and 0.1µF
capacitors to gr ound .
3 VDDA_3.3 P 3.3V analog VDD.
4 RXM I/O Physical receive or transmit signal (− differential).
5 RXP I/O Physical receive or transmit signal (+ differential).
6 TXM I/O Physical transmit or receive signal (− differential).
7 TXP I/O Physical transmit or receive signal (+ differential).
8 XO O Crystal feedback for 25MHz crystal.
This pin is a no connect if an oscillator or external clock source is used.
9 XI I Crystal / Oscillator / External Clock Input. 25MHz ±50ppm.
10 REXT I Set PHY transmit output current. Connect a 6.49kΩ resistor to ground on this pin.
11 MDIO Ipu/Opu Management Interface (MII) Data I/O This pin has a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resistor.
12 MDC Ipu Management Inter f ac e (M I I) Clock Input. This clock pin is synchronous to the MDIO
data pin.
13 RXD3/
PHYAD0 Ipu/O
MII Mode: MII Receive Data Output[3]
(
3
)
.
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
14 RXD2/
PHYAD1 Ipd/O
MII Mode: MII Receive Data Output[2](3).
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
15 RXD1/
PHYAD2 Ipd/O
MII Mode: MII Receive Data Output[1](3).
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Charact eristics for value).
Ipu/O = Input with internal pull-up (see Electri cal Characteristics for value) during power-up/reset; out put pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Charact erist ic s for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ics for
value).
3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] pres ents valid dat a to the MAC. RXD[3:0] is invali d
data from the PHY when RXDV is de-asserted.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 10 Revision 1.4
Pin Description – KSZ8081MNX (Continued)
Pin Number Pin Name Type
(2)
Pin Function
16 RXD0/
DUPLEX Ipu/O
MII Mode: MII Receive Data Output[0]
(
3
)
.
Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD
18 RXDV/
CONFIG2 Ipd/O
MII Mode: MII Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
19 RXC/
B-CAST_OFF Ipd/O
MII Mode: MII Receive Clock Output.
Config Mode: The pull-up/pull-down value is latche d as B-CAST_OFF at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
20 RXER/
ISO Ipd/O
MII mode: MII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
21
INTRP/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up
resistor.
Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s
22 TXC Ipd/O
MII Mode: MII Transmit Clock Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for normal
operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It is
better having an ex ternal pull-down resistor to avoid MAC side pulls this pin high.
23 TXEN I MII Mode: MII Transmit Enable input.
24 TXD0 I MII Mode: MII Transmit Data Input[0]
(4)
.
25 TXD1 I MII Mode: MII Transmit Data Input[1]
(4)
.
26 TXD2 I MII Mode: MII Transmit Data Input[2](4).
27 TXD3 I MII Mode: MII Transmit Data Input[3](4).
28 COL/
CONFIG0 Ipd/O
MII Mode: MII Collision Dete ct output .
Config Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
29 CRS/
CONFIG1 Ipd/O
MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
Note:
4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents vali d data from the MAC. TXD[3:0] has no
effect on the PHY when TXEN is de-asserted.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 11 Revision 1.4
Pin Description – KSZ8081MNX (Continued)
Pin Number Pin Name Type
(2)
Pin Function
30 LED0/
NWAYEN Ipu/O
LED Output: Programmable LED0 output.
Config Mode: Latched as auto -negot iation enable (Register 0h, Bit [12]) at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4 ], and is defined as
follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED Mode = [10], [11] Reserved
31 LED1/
SPEED Ipu/O
LED Output: Programmable LED1 Output.
Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset.
See the Strapping Options – KSZ8081MNX section for detai l s.
The LED1 pin is programmable using Register 1Fh bits [5:4 ], and is defined as
follows:
LED Mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity
Pin State
LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11] Reserved
32 RST# Ipu Chip Reset (active low).
PADDLE GND GND Ground
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 12 Revision 1.4
Strapping Options – KSZ8081MNX
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure that the intended values are strapped-in correctly.
Pin Number Pin Name Type(5) Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0
to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high
or writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset:
CONFIG[2:0] Mode
000 MII (default)
110 MII back-to-back
001 – 101, 111 Reserved – not used
20 ISO Ipd/O
Isolate Mode:
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
31 SPEED Ipu/O
Speed Mode:
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the
speed select, and also is latched into Register 4h (auto-negotiation advertisement) as
the speed capability support.
16 DUPLEX Ipu/O
Duplex Mode:
Pull-up (default ) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
Note:
5. Ipu/O = Input with internal pull -up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ics for
value).
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 13 Revision 1.4
Strapping Options – KSZ8081MNX (Continued)
Pin Number Pin Name Type
(
5
)
Pin Function
30 NWAYEN Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
19 B-CAST_OFF Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21 NAND_Tree# Ipu/Opu
NAND Tree Mode:
Pull-up (default ) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 14 Revision 1.4
Pin Configuration – KSZ8081RNB
32-Pin 5mm × 5mm QFN
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 15 Revision 1.4
Pin Description – KSZ8081RNB
Pin Number Pin Name Type
(6)
Pin Function
1 GND GND Ground
2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8081RNB). Decouple with 2.2µF and 0.1µF
capacitors to gr ound .
3 VDDA_3.3 P 3.3V analog VDD.
4 RXM I/O Physical receive or transmit signal (− differential).
5 RXP I/O Physical receive or transmit signal (+ differential).
6 TXM I/O Physical transmit or receive signal (− differential).
7 TXP I/O Physical transmit or receive signal (+ differential).
8 XO O Crystal feedback for 25MHz crystal. This pin is a no connect if an oscillator or external
clock source is used.
9 XI I 25MHz Mode: 25MHz ±50ppm Crystal / Oscillator / External Clock Input
50MHz Mode: 50MHz ±50ppm Oscillator / External Clock Input
10 REXT I Set PHY transmit output current. Connect a 6.49kΩ resistor to ground on this pin.
11 MDIO Ipu/Opu Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resistor.
12 MDC Ipu Management Interface (MII) Clock Input. This cl o ck pin is synchronous to the MDIO
data pin.
13 PHYAD0 Ipu/O The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
14 PHYAD1 Ipd/O The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
15 RXD1/
PHYAD2 Ipd/O
RMII Mode: RMII Receive Data Output[1](7).
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
16 RXD0/
DUPLEX Ipu/O
RMII Mode: RMII Receive Data Output[0]
(
7
)
.
Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion
of reset.
See the Strapping Options – KSZ8081RNB section for deta il s.
Notes:
6. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electric al Characteristics for value).
Ipu/O = Input with internal pull-up (see Electri cal Characteristics for value) during power-up/reset; out put pi n otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characterist ics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ics for
value).
NC = Pin is not bonded to the die.
7. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two
bits of rec overed dat a are sent by the PHY to the MAC.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 16 Revision 1.4
Pin Description – KSZ8081RNB (Continued)
Pin Number Pin Name Type
(6)
Pin Function
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD.
18 CRS_DV/
CONFIG2 Ipd/O
RMII Mode: RMI I Ca rrier Sense/Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
19
REF_CLK/
B-CAST_OFF
Ipd/O
RMII Mode: 25MHz Mode. This pin provides the 50MHz RMII reference clock output
to the MAC. See also XI (Pin 9).
50MHz mode: This pin is a no connect. See also XI (Pin 9).
Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
20 RXER/
ISO Ipd/O
RMII Mode: RMII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
21
INTRP/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up
resistor.
Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for detail s.
22 NC - No Connect. This pin is not bonded and can be left floating.
23 TXEN I RMII Transmit Enable input.
24 TXD0 I RMII Transmit Data Input[0](8).
25 TXD1 I RMII Transmit Data Input[1](8).
26 NC - No Connect. This pin is not bonded and can be left floating.
27 NC - No Connect. This pin is not bonded and can be left floating.
28 CONFIG0 Ipd/O The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See
the Strapping Options – KSZ8081RNB section for details.
29 CONFIG1 Ipd/O The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See
the Strapping Options – KSZ8081RNB section for details.
Note:
8. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits
of data are received by the PHY from the MAC.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 17 Revision 1.4
Pin Description – KSZ8081RNB (Continued)
Pin Number Pin Name Type
(6)
Pin Function
30 LED0/
NWAYEN Ipu/O
LED Output: Programmable LED0 Output.
Config Mode: Latched as auto -negot iation enable (Register 0h, Bit [12]) at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB section for deta il s.
The LED0 pin is programmable using Register 1Fh bits [5:4 ], and is defined as
follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED Mode = [10], [11] Reserved
31 LED1/
SPEED Ipu/O
LED Output: Programmable LED1 Output.
Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset.
See the Strapping Options – KSZ8081RNB sectio n for details.
The LED1 pin is programmable using Register 1Fh bits [5:4 ], and is defined as
follows:
LED Mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity
Pin State
LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11] Reserved
32 RST# Ipu Chip Reset (active low).
PADDLE GND GND Ground.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 18 Revision 1.4
Strapping Options – KSZ8081RNB
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure that the intended values are strapped-in correctly.
Pin Number Pin Name Type(9) Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0
to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high
or writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
001 RMII
101 RMII back-to-back
000, 010 – 100, 110, 111 Reserved – not used
20 ISO Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
31 SPEED Ipu/O
Speed mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the
speed select, and also is latched into Register 4h (auto-negotiation advertisement) as
the speed capability support.
16 DUPLEX Ipu/O
Duplex mode
Pull-up (default ) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
30 NWAYEN Ipu/O
Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
19 B-CAST_OFF Ipd/O
Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21 NAND_Tree# Ipu/Opu
NAND tree m ode
Pull-up (default ) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
9. Ipu/O = Input with internal pull -up (see Electrical Characterist ics f or value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteri st ic s for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ics for
value).
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 19 Revision 1.4
Functional Description: 10Base-T/100Base-TX Trans cei ver
The KSZ8081 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the co pper m edia s ide, the KSZ8 081 s uppor ts 10B ase-T and 100 Base-T X f or transm iss ion and rece ption of data over
a standard C AT -5 uns hie ld ed t wist ed pa ir (UTP) cable , and HP Auto MDI /MDI -X f or r elia ble detectio n of and c orr ect ion for
straight-through and crossover cables.
On the MAC proces sor s ide, the KSZ80 81MN X of fers the M edia In depen dent I nterf ace ( MII) and the KSZ8 081RN B off ers
the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC
processors and switches, respectively.
The MII m anagem ent bus opti on gives t he MAC pr ocess or com plete access to the KSZ8 081 contr ol and status reg isters.
Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
The KSZ8081MNX/RNB is used to refer to both KSZ8081MNX and KSZ8081RNB versions in this datasheet.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The c ircuitry starts with a p arallel-to-serial convers ion, whic h converts the MII data from the MAC into a 125MH z serial bit
stream. The data and c ontr ol s tream is then c onverted into 4 B/5 B coding and f ollo w ed by a scram bler. The seriali zed dat a
is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by
an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side s tarts with the equal ization filter to c ompens ate for inter-s ym bol interfer ence (ISI) over the twisted p air
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
compar isons of incom ing si gnal str ength a gains t som e k nown cable charac ter istic s, then tunes its elf for optim ization. T his
is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert t he NRZI signal to NRZ format. This signal is sent t hrough the de-scram bler, then the 4B/5B dec oder. Finally,
the NRZ serial data is converted to MII format and provided as the input data to the MAC.
Scrambler/De-Scramble r (100B a se-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of
2.5V peak . The 10Bas e-T signals ha ve harm onic contents that are at least 27dB belo w the fun damental f requency wh en
driven by an all-ones Manchester -encoded signal.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 20 Revision 1.4
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch c ircuit rejec ts signals with levels less than 4 00mV, or with s hort pulse widths, to prevent
noise at t he RXP and RX M inputs fr om f alsely triggeri ng the decoder. W hen the input exceeds t he squelch li mit, the PLL
locks onto the incom ing signal and th e KSZ8081 MNX/R NB decodes a d ata fram e. The rec eive clock is kept active dur ing
idle periods between data receptions.
SQE and Jabber Fu nction (10Base-T Only)
In 10Base-T operat ion , a short pu ls e is put o ut o n th e CO L pi n af ter each frame is transmitted. T his SQE tes t is ne ede d t o
test the 10Base-T transmit/receive path. If transm it enable (TXEN) is high for m ore than 20ms (jabbering), the 10Base-T
transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T
transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8081MNX/RNB generates all internal clocks and all external clocks for system timing from an external 25MHz
cr ysta l, oscillator, or reference clock . For the KSZ808 1RNB in RMII 50 MHz clock mode, these c locks are gener ated from
an external 50MHz oscillator or system clock.
Auto-Negotiation
The KSZ8081MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-n egoti ation, l ink par tners advert ise c apabilit ies ac ross t he UTP link to each other an d then c om pare their own
capabil ities with those the y received from their link partners . The highest speed a nd duplex setting th at is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priority 1: 100Base-TX, full-duplex
• Priority 2: 100Base-TX, half-duplex
• Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8081MNX/RNB link partner is forced to bypass auto-negotiation, then the
KSZ8081MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which all ows the KSZ8081 MNX/RNB to es tablish a link by listening for a f ixed signal protoc ol in the absenc e of the auto-
negotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, Bit [12]. If au to-ne got iat ion is dis ab led , th e s pee d is s et b y Register 0h, Bit [13] , an d the dup lex is
set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 1.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 21 Revision 1.4
Figure 1. Auto-Negotiation Flow Chart
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 22 Revision 1.4
MII Interface (KSZ8081MNX Only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8081MNX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
Table 1. MII Signal Definition
MII Signal Name Direction
(with respect to PHY,
KSZ8081MNX signal)
Direction
(with respect to MAC) Description
TXC Output Input Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmi t Data[3:0]
RXC Output Input Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data[3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Ca rrier Sense
COL Output Input Collision Detection
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXC is
2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indic ates th at th e M AC is pr esen tin g ni bb les on TX D[ 3:0] f or transmission. It is as ser ted synchronously wit h the f irs t
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated
before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 23 Revision 1.4
Transmit Data[3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, T XD[3:0] are accepted by the PHY for
transm ission. T XD[3:0] is 00 to i ndicate idle wh en TXEN is de-ass erted. Values other tha n 00 on TX D[3:0] while TXEN is
de-asserted ar e ignor ed b y the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
• In 10Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle or the link is down.
• In 100Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can
detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-
asserted wh en an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if
IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with
respect to TXC and RXC.
MII Signal Diagram
The KSZ8081MNX MII pin connections to the MAC are shown in Figure 2.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 24 Revision 1.4
Figure 2. KSZ8081MNX MII Interface
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 25 Revision 1.4
RMII Data Interface (KSZ808 1RNB Only)
The Reduc ed Medi a Indep endent Int erf ace (RMI I) spec ifies a lo w pin count M edia Inde pen dent Inter face ( MII). It prov ides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
RMII – 25MHz Clock Mode
The KSZ8081RNB is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 0 (default value) to select 25MHz clock mode.
RMII – 50MHz Clock Mode
The KSZ8081RNB is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:
• An external 50MHz clock source (oscillator) connected to XI (Pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 1 to select 50MHz clock mode.
RMII Signal Definition
Table 2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
Table 2. RMII Signal Defintion
RMII Signal Name Direction
(with respect to PHY,
KSZ8081RNB signal)
Direction
(with respect to MAC) Description
REF_CLK Output (25MHz clock mode) /
<no connect> (50MHz clock mode)
Input/
Input or <no connect> Synchronous 50MHz reference clock for
receive, tran sm it, and contr ol interfa ce
TXEN Input Output Transmit Enable
TXD[1:0] Input Output Transmi t Data[1:0]
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data[1:0]
RXER Output Input, or (not required) Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
For 25MHz clock mode, the KSZ8081RNB generates and outputs the 50MHz RMII REF_CLK to the MAC at REF_CLK
(Pin 19).
For 50MH z cloc k mode, the KSZ808 1RNB takes in the 50MHz RMII R EF_CLK from the MAC or system board at XI ( Pin
9) and leaves the REF_CLK (Pin 19) as a no connect.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 26 Revision 1.4
Transmit Enable (TXEN)
TXEN indicates that the MAC is present ing dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data[1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for
transmission.
TXD[1:0] is 0 0 to ind icate id le when TXEN is de-ass er t ed. The PHY i gnores va lue s other tha n 00 on TXD[1:0] while T X EN
is de-asserted.
Carrier Sen se/Receive Data Valid (CRS_DV)
The PH Y asser ts CRS_ DV when the recei ve medium is non-id le. It is as ser ted asynchron ous ly when a carr ie r is detec ted.
This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
W hile carr ier detect ion crit eria are m et, CRS_D V rem ai ns ass erted con tinuo usl y from the f irst r ecovered dibit of the fr ame
through the f ina l rec ov ered dibit. It is ne gated befor e th e f irs t REF _CLK th at f ollo w s the f inal dibit . The data on R X D[1:0] is
considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to
REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
Receive Data[1:0] (RXD[1:0])
RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,
RXD[1:0] transfers two bits of recovered data from the PHY.
RXD[1:0] is 00 to indic ate i dle whe n CRS_D V is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while
CRS_DV is de-asserted.
Receive Error (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a
PHY can d etect that m ay otherwise be undetectable b y the M AC sub-la yer ) was detecte d somewher e in the fr ame being
transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. . While CRS_DV is de-asserted, RXER has no effect on the
MAC.
Collision Detection (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
RMII Signal Diagram
The KSZ8081RNB RMII pin connections to the MAC for 25MHz clock mode are shown in Figure 3. The connections for
50MHz clock mode are shown in Figure 4.
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Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode)
Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode)
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KSZ8081MNX/KSZ8081RNB
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Back-to-Back Mode – 100Mbps Copper Repeater
Two KSZ8081MNX/RNB devices can be connected back-to-back to form a 100Base-TX copper repeater.
Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Bac k-to-Back Copper Repeater
MII Back-to-Back Mode (KSZ8081MNX Only)
In MII back -to-bac k mode, a K SZ8081M NX int erf aces with another KSZ 8081MNX to pr ovide a com plete 100Mbps cop per
repeater solution.
The KSZ8081MNX devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 110
• A common 25MHz reference clock connected to XI (Pin 9) of both KSZ8081MNX devices
• MII signals connected as shown in Table 3.
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8081MNX (100Base-TX copper)
[Device 1] KSZ8081MNX (100Base-TX copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
RXDV 18 Output TXEN 23 Input
RXD3 13 Output TXD3 27 Input
RXD2 14 Output TXD2 26 Input
RXD1 15 Output TXD1 25 Input
RXD0 16 Output TXD0 24 Input
TXEN 23 Input RXDV 18 Output
TXD3 27 Input RXD3 13 Output
TXD2 26 Input RXD2 14 Output
TXD1 25 Input RXD1 15 Output
TXD0 24 Input RXD0 16 Output
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RMII Back-to-Back Mode (KSZ8081RNB Only)
In RMII back-to-back mode, a KSZ8081RNB interfaces with another KSZ8081RNB to provide a complete 100Mbps
copper repeater solution.
The KSZ8081RNB devices are configured to RMII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 101
• A common 50MHz reference clock connected to XI (Pin 9) of both KSZ8081RNB devices
• RMII signa ls conn ec ted as s ho wn in Table 4.
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8081RNB (100Base-TX copper)
[Device 1] KSZ8081RNB (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
CRSDV 18 Output TXEN 23 Input
RXD1 15 Output TXD1 25 Input
RXD0 16 Output TXD0 24 Input
TXEN 23 Input CRSDV 18 Output
TXD1 25 Input RXD1 15 Output
TXD0 24 Input RXD0 16 Output
MII Management (MIIM) Interface
The KSZ8081MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control th e state of the KSZ 8081MNX /RN B. An exter nal de vice with MI IM capa bilit y is used to r ead the PHY s tatus and/ or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller
to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE 802.3
Specification. The additional registers are provided for expanded functionality. See the “Register Map” section for
details.
As the def ault, the KSZ808 1MNX/RNB supp orts unique PH Y addr esses 1 to 7, and broa dcast PHY addr ess 0. The latter
is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ808 1MNX/RNB device, or write
to multiple KSZ8081MNX/RNB devices simultaneously.
PHY addr ess 0 can opt ionall y be disab led as the br oadcast ad dress b y either har dware pin str apping ( B-CAST_OFF, Pin
19) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MNX/RNB
device.
The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock.
Table 5 shows the MII management frame format for the KSZ8081MNX/RNB.
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Table 5. MII Management Frame Format for the KSZ8081MNX/RNB
Preamble Start of
Frame Read/Write
OP Code PHY Address
Bits [4:0] REG Address
Bits [4:0] TA Data
Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Interrupt (INTRP)
INTRP (Pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8081MNX/RNB PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII m anagem ent bus option gi ves the MAC pr oc essor com plete acc ess to t he KSZ 808 1MNX/RN B co ntr ol and st atus
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8081MNX/RNB and its link partner. This feature allows the KSZ8081MNX/RNB to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8081MNX/RNB accordingly.
HP Auto MD I/MDI-X is ena bled b y def ault. It is d isable d by writin g a ‘1’ to Register 1Fh, Bit [13]. MDI and M DI-X m ode is
selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 6 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
Table 6. MDI/MDI-X Pin Definition
MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2 TX− 2 RX−
3 RX+ 3 TX+
6 RX− 6 TX−
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Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 shows a
typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
Figure 6. Typical Straight Cable Connection
Crossover C able
A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 7
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
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KSZ8081MNX/KSZ8081RNB
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Loopback Mode
The KSZ8081MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
Local (Di gital) Loopback
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8081MNX/RNB and the
external MAC, and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data path is shown in Figure 8.
1. The MII/RMII MAC transmits frames to the KSZ8081MNX/RNB.
2. Frames are wrapped around inside the KSZ8081MNX/RNB.
3. The KSZ8081MNX/RNB transmits frames back to the MII/RMII MAC.
4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
Figure 8. Local (Digital) Loopback
The following programming action and register settings are used for local loopback mode.
For 10/100Mbps loopbac k,
• Set Register 0h,
Bit [14] = 1 // Enable local loopback mode
Bit [13] = 0/1 // Select 10Mbps/1 00Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
If don’t want the frames go out from the copper port in the local loopback, please follow the steps as below.
1. Set register 1Fh bit [3] to ‘1’ to disable the transmitter.
2. Run local loopback test as above.
3. Set register 1Fh bit [3] to ‘0’ to enable the transmitter.
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Remote (Ana log) Loopback
This loopb ack m ode checks the li ne (diff erenti al pairs , tr ansform er , RJ-45 c onnector, Eth ernet c able) tr ansmit and rece ive
data paths between the KSZ8081MNX/RNB and its link partner, and is supported for 100Base-TX full-duplex mode only.
The loopback data path is shown in Figure 9.
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081MNX/RNB.
2. Frames are wrapped around inside the KSZ8081MNX/RNB.
3. The KSZ8081MNX/RNB transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.
Figure 9. Remote (Analog) Loopback
The following programming steps and register settings are used for remote loopback mode.
1. Set Register 0h,
Bits [13] = 1 // Select 100Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner.
2. Set Register 1Fh,
Bit [2] = 1 // Enable remote loopback mode
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the
PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
Usage
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
3. Disable auto MDI/MDI-X by writing a ‘1’ to Regis t er 1Fh, bit [13].
4. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The
distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Register s 1Dh bits [8:0] sh ou ld be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
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NAND Tree Support
The KSZ8081MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8081MNX/RNB digital I/O (NAND tree input) pin is an
input to on e NAND gat e along the ch ain. At the end of the c hain, the TXD1 pin pr ovides the outp ut for the n ested NAND
gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAN D tree in put pin lo w, sequ ent ia ll y, accor ding to the NAND tree pi n order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven lo w
Table 7 and Table 8 list the NAND tree pin orders for KSZ8081MNX and KSZ8081RNB, respectively.
Table 7. NAND Tree Test Pin Order for KSZ8081MNX
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
21 INTRP Input
23 TXEN Input
30 LED0 Input
24 TXD0 Input
25 TXD1 Output
Note: KS8081MNX supports partial NAND tree test pins. Table 7 lists partial NAND tree test pins. If full NAND tree testing
is required, please use KSZ8091MNX device that supports all the required pins.
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Table 8. NAND Tree Test Pin Order for KSZ8081RNB
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
21 INTRP Input
23 TXEN Input
31 LED1 Input
30 LED0 Input
24 TXD0 Input
25 TXD1 Output
NAND Tree I/O Testing
Use the following procedure to check for faults on the KSZ8081MNX/RNB digital I/O pin connections to the board:
1. Enable NAND tree mode using either hardware (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]).
2. Use board logic to drive all KSZ8081MNX/RNB NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MNX/RNB NAND tree pin order, as follows:
a. Toggle the f irs t pin (MD IO) f r om high to low , and ver ify that the TXD1 pin s witc hes from high to low to ind icate that
the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the s econd p in (MDC) from high to low, a nd verif y that the TXD1 pin s witches f rom low to hi gh to ind icate
that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Continue with this sequence until all KSZ8081MNX/RNB NAND tree input pins have been toggled.
Each KSZ8081MNX/RNB NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a g ood connect ion. If the TXD1 pin fails to tog gle wh en th e K SZ80 81M NX/RNB in put p in to gg les f rom high to lo w,
the input pin has a fault.
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Power Management
The KSZ8081MNX/RNB incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consum ption when the cable is unplugged. It is enabled by
writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected
(no link).
In this m ode, the KSZ8081 MNX /R NB sh ut s do wn all tr ans cei ver bl oc ks, except f or the tr ans mitter, energy detect, and PL L
circuits.
By default, power-saving mode is disabled after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD m ode works with th e PLL off (set by writing a ‘1’ to Regist er 10h, Bit [4] to autom atically turn t he PLL off in EDPD
mode) to turn off all KSZ8081MNX/RNB transceiver blocks except the transmitter and energy-detect circuit s.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8081MNX/RNB and its
link partner , whe n op er ati n g in t he s ame low-po wer st at e a nd with Aut o MDI/MDI-X dis able d, can wak e up when t he c ab le
is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
Power-Down Mode
Power-down mode is used to power down the KSZ8081MNX/RNB device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8081MNX/RNB disables all internal functions except the MII management interface. The
KSZ8081MNX/RNB exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow
oscillator when th e KSZ8081MNX/RNB device is not in use after power-up. It is enabled b y writing a ‘1’ to Register 11h,
Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081MNX/RNB device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-do wn m ode b y writing a ‘0’ to Register 0h, Bit [11].
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
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Reference Circuit for Power and Ground Connections
The KSZ8081MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Fi gure 10 and Table 9 for 3.3V VDDIO.
Figure 10. KSZ8081MNX/RNB Power and Ground Connections
Table 9. KSZ8081MNX/RNB Pow er Pin Descriptions
Power Pin Pin Number Description
VDD_1.2 2 Decouple with 2.2µF and 0.1µF capacitors to ground.
VDDA_3.3 3 Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22µF and 0.1µF capacitors to ground.
VDDIO 17 Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22µF and 0.1µF capacitors to ground.
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Typical Current/Power Consumption
Table 1 0, Table 1 1, and Table 12 show t yp ical valu es for c urrent consum ption by the trans ceiver (VDD A_3.3) an d digital
I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081MNX/RNB device for the indicated
nominal op erating voltag es. These cur rent and power consum ption values inc lud e the transmit driver c urrent and on-chip
regulator current for the 1.2V core.
Transceiver (3.3V), Digital I/Os (3.3V)
Table 10. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition 3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffi c ) 34 12 152
100Base-TX Full-duplex @ 100% utilization 34 13 155
10Base-T Link-up (no traffic) 14 11 82.5
10Base-T Ful l-duplex @ 100% utilization 30 11 135
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 14 10 79.2
EDPD mode (Reg. 18h, Bit [11] = 0) 10 10 66.0
EDPD mode (Reg. 18h, Bit [11] = 0 ) and PLL off (Reg. 10h,
Bit [4] = 1) 3.77 1.54 17.5
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.59 1.51 13.5
Software power-down m ode (Reg. 0h, Bit [11] =1) and slow-
oscillator mode (Reg. 11h, Bit [5] =1) 1.36 0.45 5.97
Transceiver (3.3V), Digital I/Os (2.5V)
Table 11. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Condition 3.3V Transceiver
(VDDA_3.3) 2.5V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffi c ) 34 11 140
100Base-TX Full-duplex @ 100% utilization 34 12 142
10Base-T Link-up (no traffic) 15 10 74.5
10Base-T Ful l-duplex @ 100% utilization 27 10 114
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 10 74.5
EDPD mode (Reg. 18h, Bit [11] = 0) 11 10 61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 3.55 1.35 15.1
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.29 1.34 10.9
Software power-down m ode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 0.29 4.52
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Transceiver (3.3V), Digital I/Os (1.8V)
Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffi c ) 34 11 132
100Base-TX Full-duplex @ 100% utilization 34 12 134
10Base-T Link-up (no traffic) 15 9.0 65.7
10Base-T Ful l-duplex @ 100% utilization 27 9.0 105
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 9.0 65.7
EDPD mode (Reg. 18h, Bit [11] = 0) 11 9.0 52.5
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 4.05 1.21 15.5
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.79 1.21 11.4
Software power-down m ode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 0.19 5.79
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Register Map
Registe r Number (Hex) Description
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Link Partner Ability
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Link Partner Next Page Ability
9h Reserved
10h Digital Reserved Control
11h AFE Control 1
12h – 14h Reserved
15h RXER Counter
16h Operation Mode Strap Override
17h Operation Mode Strap Status
18h Expanded Control
19h – 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD Control/Status
1Eh PHY Control 1
1Fh PHY Control 2
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 42 Revision 1.4
Register Description
Address Name Description Mode
(10)
Default
Register 0h – Basic Control
0.15 Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation RW 0
0.13 Speed Select
1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(Register 0. 12 = 1).
RW Set by the SPEED strapping pin.
See the Strapping Options –
KSZ8081MNX section for details.
0.12 Auto-
Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, the auto-negotiati o n result ov err ide s
the settings in registers 0.13 and 0.8.
RW
Set by the NWAYEN strapping
pin.
See the Strapping Options –
KSZ8081MNX section for details.
0.11 Power-Down
1 = Power-down mode
0 = Normal opera tion
If software reset (Register 0.15) is used to exit
power-down m ode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and re-
latches the pin strapping pin values.
RW 0
0.10 Isolate 1 = Electrical isolation of PHY fro m MII/RMII
0 = Normal operation RW Set by the ISO strapping pin.
See the Strapping Options –
KSZ8081MNX section for details.
0.9 Restart Auto-
Negotiation
1 = Restart auto-nego tiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW
The inverse of the DUPLEX
strapping pin value.
See the Strapping Options –
KSZ8081MNX section for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0
0.6:0 Reserved Reserved RO 000_0000
Note:
10. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 43 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100Base-TX
Full-Duplex 1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex RO 1
1.13 100Base-TX
Half-Duplex 1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex RO 1
1.12 10Base-T
Full-Duplex 1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex RO 1
1.11 10Base-T
Half-Duplex 1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex RO 1
1.10:7 Reserved Reserved RO 000_0
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble RO 1
1.5 Auto-
Negotiation
Complete
1 = Auto-neg oti at io n proce ss c omplet e d
0 = Auto-negot iation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-
Negotiation
Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports extended capability registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0022h
Register 3h – PHY Identifier 2
3.15:10 PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0001_01
3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision
Number Four-bit manufacturer’s revision number RO Indicates silicon revision
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 44 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability RW 0
4.14 Reserved Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
4.8 100Base-TX
Full-Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options –
KSZ8081MNX section for details.
4.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options –
KSZ8081MNX section for details.
4.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RW 1
4.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RW 1
4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
5.8 100Base-TX
Full-Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RO 0
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 45 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 5h – Auto-Negotiation Link Partner Ability
5.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RO 0
5.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RO 0
5.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RO 0
5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4 Parallel
Detection Fault 1 = Fault detected by parallel detection
0 = No fault detected by parallel detection RO/LH 0
6.3 Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability RO 0
6.2 Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet RO/LH 0
6.0
Link Partner
Auto-
Negotiation
Able
1 = Link partner has auto-neg otiation capabi lity
0 = Link partner does not have auto-negotiation
capability RO 0
Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page RW 0
7.14 Reserved Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unformatted page RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with m essage RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0 RO 0
7.10:0 Mes sage Field 11-bit wide field to encode 2048 messages RW 000_0000_0001
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 46 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 8h – Link Partner Next Page Ability
8.15 Next Page 1 = Additional next pages will follow
0 = Last page RO 0
8.14 Acknowledge 1 = Successful rec eipt of link word
0 = No suc cessful receipt of link word RO 0
8.13 Message Page 1 = Message page
0 = Unformatted page RO 0
8.12 Acknowledge2 1 = Can act on the information
0 = Cannot act on the information RO 0
8.11 Toggle
1 = Previous value of transmitted link code word
equal to logic 0
0 = Previous value of transmitted link code word
equal to logic 1
RO 0
8.10:0 Mes sage Field 11-bit wide field to encode 2048 messages RO 000_0000_0000
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off 1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
11.5 Slow-Oscillator
Mode Enable
Slow-oscillator mode is used to dis connect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8081MNX/RNB device is not in use after
power-up.
1 = Enable
0 = Disable
This bit automatically sets software power-down
to the analog side when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h
Register 16h – Operation Mode Strap Override
16.15 Reserved
Factory Mode
0 = Normal operation
1 = Fact ory t est mode
If TXC (Pin 22) latches in a pull-up value at the
de-assertion of reset, write a ‘0’ to this bit to
clear Reserved Factory Mode.
This bit applies only to KSZ8081MNX.
RW 0
Set by the pull-up/pull-down value
of TXC (Pin 22).
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9 B-CAST_OFF
Override 1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 47 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 16h – Operation Mode Strap Override
16.8 Reserved Reserved RW 0
16.7 MII B-to-B
Override
1 = Override strap-in for MII back-to-back mode
(also set Bit 0 of this register to ‘1’)
This bit appl ies only to KSZ8081MNX. RW 0
16.6 RMII B-to-B
Override
1 = Override strap-in for RMII Back-to-Back
mode (also set Bit 1 of this register to ‘1’)
This bit appl ies only to KSZ8081RNB. RW 0
16.5 NAND Tree
Override 1 = Override strap-in for NAND tree mode RW 0
16.4:2 Reserved Reserved RW 0_00
16.1 RMII Override 1 = Override strap-in for RMII mode
This bit appl ies only to KSZ8081RNB. RW 0
16.0 MII Override 1 = Override strap-in for MII mode
This bit appl ies only to KSZ8081MNX. RW 1
Register 17h – Operation Mode Strap Status
17.15:13 PHYAD[2:0]
Strap-In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
RO
17.12:10 Reserved Reserved RO
17.9 B-CAST_OFF
Strap-In Status 1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RO
17.8 Reserved Reserved RO
17.7 MII B-to-B
Strap-In Status 1 = Strap to MII back-to-back mode
This bit appl ies only to KSZ8081MNX. RO
17.6 RMII B-to-B
Strap-In Status 1 = Strap to RMII Back-to-Back mode
This bit appl ies only to KSZ8081RNB. RO
17.5 NAND Tree
Strap-In Status 1 = Strap to NAND tree mode RO
17.4:2 Reserved Reserved RO
17.1 RMII Strap-In
Status 1 = Strap to RMII mode
This bit appl ies only to KSZ8081RNB. RO
17.0 MII Strap-In
Status 1 = Strap to MII mode
This bit applies only to KSZ8081MNX. RO
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 48 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW 1
18.10 100Base-TX
Latency
1 = MII output is random latency
0 = MII output is fixed latency
For both settings, all bytes of received preamble
are passed to the MII output.
This bit appl ies only to KSZ8081MNX.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6 10Base-T
Preamble
Restore
1 = Restore rec eived preamble to MII output
0 = Remove all seven bytes of preamble before
sending frame (starting with SFD) to MII output
This bit applies only to KSZ8081MNX,
RW 0
18.5:0 Reserved Reserved RW 00_0000
Register 1Bh – Interrupt Control/Status
1B.15 Jabber
Interrupt
Enable
1 = Enable jabber interr upt
0 = Disable jabber interrupt RW 0
1B.14 Receive Error
Interrupt
Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt RW 0
1B.13 Page Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt RW 0
1B.12 Parallel Detect
Fault Interr upt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt RW 0
1B.11
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt RW 0
1B.10 Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt RW 0
1B.9 Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt RW 0
1B.8 Link-Up
Interrupt
Enable
1 = Enable link-up int errupt
0 = Disable link-up interrupt RW 0
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 49 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 1Bh – Interrupt Control/Status
1B.7 Jabber
Interrupt 1 = Jabber occurred
0 = Jabber did not occur RO/SC 0
1B.6 Receive Error
Interrupt 1 = Receive error occurred
0 = Receive error did not occur RO/SC 0
1B.5 Page Receive
Interrupt 1 = Page receive occurred
0 = Page receive did not occur RO/SC 0
1B.4 Parallel Detect
Fault Interr upt 1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur RO/SC 0
1B.3 Link Partner
Acknowledge
Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur RO/SC 0
1B.2 Link-Down
Interrupt 1 = Link-down occurred
0 = Link-down did not occur RO/SC 0
1B.1 Remote Fault
Interrupt 1 = Remote fault occurred
0 = Remote fault did not occur RO/SC 0
1B.0 Link-Up
Interrupt 1 = Link-up occurred
0 = Link-up did not occur RO/SC 0
Register 1Dh – LinkMD Control/Status
1D.15 Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the stat us i nfor m atio n is
valid for read.
RW/SC 0
1D.14:13 Cable
Diagnostic
Test Result
[00] = Normal condition
[01] = Open c ondition has been detected in
cable
[10] = Short condition has been detected in
cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Indicator 1 = Short cable (<10 meter) has been detected
by LinkMD RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter D istan ce to fault RO 0_0000_0000
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 50 Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 1Eh – PHY Control 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9 Enable Pause
(Flow Control) 1 = Flow control capable
0 = No flow c ontrol capability RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down RO 0
1E.7 Polari t y Status 1 = Polarity is reversed
0 = Polarity is not reversed RO
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X
State 1 = MDI-X
0 = MDI RO
1E.4 Energy Detect
1 = Signal present on receive differential
pair
0 = No signal detected on receive differential
pair
RO 0
1E.3 PHY Isolate 1 = PHY in isolate mode
0 = PHY in normal operation RW 0
1E.2:0 Operation
Mode
Indication
[000] = Still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = Reserved
RO 000
Register 1Fh – PHY Control 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode RW 1
1F.14 MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM (pins 5, 4) and
Receive on TXP,TXM (pins 7, 6)
0 = MDI mode
Transmit on TXP,TXM (pins 7, 6) and
Receive on RXP,RXM (pins 5, 4)
RW 0
1F.13 Pair Swap
Disable 1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X RW 0
1F.12 Reserved Reserved RW 0
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 51 Revision 1.4
Register Description (Continued)
Address Name Description Mode(10) Default
Register 1Fh – PHY Control 2
1F.11 Force Lin k
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving 1 = Enable power saving
0 = Disable power saving RW 0
1F.9 Interrupt Level 1 = Interrupt pin active high
0 = Interrupt pin active low RW 0
1F.8 Enable Jabber 1 = Enable jabber cou nter
0 = Disable jabber counter RW 1
1F.7 RMII
Reference
Clock Select
1 = RMII 50MHz clock mode; clock input to XI
(Pin 9) is 50MHz
0 = RMII 25MHz clock mode; clock input to XI
(Pin 9) is 25MHz
This bit appl ies only to KSZ8081RNB.
RW 0
1F.6 Reserved Reserved RW 0
1F.5:4 LED Mode
[00] = LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
[10], [11] = Reserved
RW 00
1F.3 Disable
Transmitter 1 = Disable transmitter
0 = Enable transmitter RW 0
1F.2 Remote
Loopback 1 = Remote (analog) loopback is enabled
0 = Normal mode RW 0
1F.1 Enable SQE
Test 1 = Enable SQE test
0 = Disable SQE test RW 0
1F.0 Disable Data
Scrambling 1 = Disable scrambler
0 = Enable scrambler RW 0
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 52 Revision 1.4
Absolute Maximum Ratings(11)
Supply Voltage (VIN)
(VDD_1.2) .................................................. –0.5V to +1.8V
(VDDIO, VDDA_3.3) ...................................... –0.5V to +5.0V
Input Voltage (all inputs) .............................. –0.5V to +5.0V
Output Volta ge (a ll outputs ) ......................... –0.5V to +5.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (TS) ......................... –55°C to +150°C
Operating Ratings(12)
Suppl y Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
(VDDIO_2.5) ........................................ +2.375V to +2.625V
(VDDIO_1.8) ........................................ +1.710V to +1.890V
Ambient Temperature
(TA, Commercial) ...................................... 0°C to +70°C
(TA, Industrial) ....................................... –40°C to +85°C
Maximum Junction Temperature (TJ(MAX)) .................. 125°C
Thermal Resistance (θJA) ................................... 34°C/W
Thermal Resistance (θJC) .................................... 6°C/W
Electrical Characteristics(13)
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)
(14)
IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA
IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA
IDD3_3.3V EDPD Mode Ethernet cable disconnected (reg. 18h.11 = 0) 20 mA
IDD4_3.3V Power-Do wn Mode Software power-down (reg. 0h.11 = 1) 4 mA
CMOS Level Inputs
VIH Input High Voltage
VDDIO = 3.3V 2.0
V VDDIO = 2.5V 1.8
VDDIO = 1.8V 1.3
VIL Input Low Voltag e
VDDIO = 3.3V 0.8
V VDDIO = 2.5V 0.7
VDDIO = 1.8V 0.5
|IIN| Input Current VIN = GND ~ VDDIO 10 µA
CMOS Level Outputs
VOH Output High Voltage
VDDIO = 3.3V 2.4
V VDDIO = 2.5V 2.0
VDDIO = 1.8V 1.5
VOL Output Low Voltage
VDDIO = 3.3V 0.4
V VDDIO = 2.5V 0.4
VDDIO = 1.8V 0.3
|Ioz| Output Tri-State Leakage 10 µA
LED Output
ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA
Notes:
11. Exceeding the absolute maximum ratings can damage the device. Stresses greater than the absolute maximum rating can cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified i n the operating secti ons of thi s s pecifi cation is
not implied. Maximum condit i ons for extended periods may affect reliabil i t y.
12. The device is not guaranteed to funct i on outside its operati ng ratings.
13. TA = 25°C. Specification for packaged product only.
14. Current consumption is for the single 3.3V supply KSZ8081MNX/RNB device only, and includes the transmit driver current and the 1.2V supply
voltage (VDD_1.2) that are supplied by the KSZ8081MNX/RNB.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 53 Revision 1.4
Electrical Characteristics(13) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
pu Internal Pull-Up Resistance
VDDIO = 3.3V 30 45 73
kΩ VDDIO = 2.5V 39 61 102
VDDIO = 1.8V 48 99 178
pd Internal Pull-Down Resistance
VDDIO = 3.3V 26 43 79
kΩ VDDIO = 2.5V 34 59 113
VDDIO = 1.8V 53 99 200
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO Peak Differential Output Voltage 100Ω termination across differential output 0.95 1.05 V
VIMB Output Voltage Imbalance 100Ω termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall Time Imbalance 0 0.5 ns
Duty Cycle Distortion ±0.25 ns
Overshoot 5 %
Output Jitter Peak-to-peak 0.7 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output Vol tage 100Ω termination across differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5 ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
Transmitter – Drive Setting
VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V
REF_CLK Output
50MHz RMII Clock Output Jitter Peak-to-peak. (Applies only to KS Z8081RN B
in RMII – 25MHz clock mode) 300 ps
100Mbps Mode – Industr ial Applications Parameters
Clock Phase Delay – XI Input to
MII TXC Output
XI (25MHz clock input) to MII TXC (25MHz
clock output) delay, referenced to rising edges
of both clocks. (Applies only to KSZ8081MNX
in MII mode)
15 20 25 ns
tllr Link Loss Reac tion (Indication)
Time
Link loss detected at receive differential inputs
to PHY signal indication time for each of the
following:
1. For LED mode 00, Speed LED output
changes from low (100Mbps) to high (10Mbps,
default state for link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status
change.
4.4 µs
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 54 Revision 1.4
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 11. MII SQE Timing (10Base-T)
Table 13. MII SQE Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Units
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs
tSQEP COL (SQE) pulse duration 1.0 µs
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KSZ8081MNX/KSZ8081RNB
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MII Transmit Timing (10Base-T)
Figure 12. MII Transmit Timing (10Base-T)
Table 14. MII Transmit Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Units
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSU1 TXD[3:0] setup to rising edge of TXC 120 ns
tSU2 TXEN setup to rising edge of TXC 120 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 600 ns
tCRS2 TXEN low to CRS de-asserted latency 1.0 µs
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MII Receive Timing (10Base-T)
Figure 13. MII Receive Timing (10Base-T)
Table 15. MII Receive Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Units
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising
edge of RXC 205 ns
tRLAT CRS to (RXDV, RXD[3:0]) latency 7.2 µs
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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MII Transmit Timing (100Base-TX)
Figure 14. MII Transmit Timing (100Base-TX)
Table 16. MII Transmit Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Units
tP TXC period 40 ns
tWL TXC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edg e of T X C 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 72 ns
tCRS2 TXEN low to CRS de-asserted latency 72 ns
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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MII Receive Timing (100Base-TX)
Figure 15. MII Receive Timing (100Base-TX)
Table 17. MII Receive Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Units
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising
edge of RXC 16 21 25 ns
tRLAT CRS to (RXDV, RXD[3:0] latency 170 ns
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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RMII Timing
Figure 16. RMII Timing – Data Received from RMII
Figure 17. RMII Timing – Data Input to RMII
Table 18. RMII Timing Parameters – KSZ8081RNB (25MHz input to XI pin, 50MHz output from REF_CLK pin)
Timing Parameter Description Min. Typ. Max. Units
tCYC Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tOD Output delay 7 10 13 ns
Table 19. RMII Timing Parameters – KSZ8081RNB (50MHz input to XI pin)
Timing Parameter Description Min. Typ. Max. Units
tCYC Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tOD Output delay 8 11 13 ns
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KSZ8081MNX/KSZ8081RNB
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Auto-Negotiation Timin g
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Timing Parameter
Description
Min.
Typ.
Max.
Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/Dat a pul se width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pul se to clo ck p ul se 111 128 139 µs
Number of clock/data pulses per FLP burst 17 33
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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MDC/MDIO Timing
Figure 19. MDC/MDIO Ti ming
Table 21. MDC/MDIO Timing Parameters
Timing Parameter Description Min. Typ. Max. Units
fc MDC Clock Frequency 2.5 10 MHz
tP MDC period 400 ns
tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 ns
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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Power-up/Rese t Timing
The KSZ8081MNX/RNB reset timing requirement is summarized in Fi gure 20 and Table 22.
Figure 20. Power-up/Reset Timing
Table 22. Power-up/Reset Timing Para meter s
Parameter Description Min. Max. Units
tVR Supply voltage (VDDIO, VDDA_3.3) rise tim e 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms
tCS Configurat i on setu p time 5 ns
tCH Configuration hold time 5 ns
tRC Reset to strap-in pin output 6 ns
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
Micrel, Inc.
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Reset Circuit
Figure 21 shows a reset circuit recomm ended for powering up the KSZ8081MNX/RNB if reset is triggered by the power
supply.
Figure 21. Recommended Reset Circuit
Figure 22 Shows a reset circuit recomm ended for applications where reset is driven by another device (for example, the
CPU or a n FPG A). T he res et out R ST _OUT _n fr om CPU/FPG A provi des th e war m res et after power up reset. D 2 is us ed
if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If
different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 c an be remove d to connect both de vices directl y. Usually, Eth ernet device and CP U/FPGA sho uld use same
VDDIO voltag e.
CPU/FPGA
VDDIO
C 10uF
R 10K
RST RST_OUT_n
D1
D2
KSZ8081MNX/RNB
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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Reference Circuits – LED Strap-In Pins
The pull-up, float, and pull-do wn reference c ircuits f or the LED1/SPEE D and LED0/NWAYEN strapping pi ns are sho wn in
Figure 23 for 3.3V and 2.5V VDDIO.
Figure 23. Reference Circuits for LED Strapping Pins
For using 1.8V VDDIO, should select parts with low 1.8V operation voltage and forwarding current IF about 2mA LED
indicator. It is ok using internal pull-up or external pull-up resistor for the LED pin pull-up strap function, and use an
external 0.75K to 1K pull-down resistor for the LED pin pull-down strap function.
Note: If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For
example, use a bipolar transistor or a level shift device.
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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Reference Clock – Connection and Selection
A crystal or ex ternal cloc k source, such as an os c illat or , is used to pr o vide t h e ref er enc e c lock for the KSZ80 8 1MNX /R N B.
For the KSZ 8 081 MNX in al l oper at in g modes and f or the K SZ80 81RNB in R MII – 25MHz Clock Mode, t he ref er enc e c lock
is 25MHz. The reference clock connections to XI (Pin 9) and XO (Pin 8), and the reference clock selection criteria, are
provided in Figure 24 and Table 23.
Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection
Table 23. 25MHz Crystal/Reference Clock Selection Criteria
Characteristics Value Units
Frequency 25 MHz
Frequency to lera nce (max)(15) ±50 ppm
Crystal series resistance (typ) 40 Ω
Crystal load cap aci tan ce (typ) 22 pF
Note:
15. ±60ppm for overtemperature crystal.
For the K SZ808 1RNB in RMII – 50MH z clock mode, t he ref erence c loc k is 50MHz. T he ref erence c lock c onnections to XI
(Pin 9), and the reference clock selection criteria are provided in Figure 25 and Table 24.
Figure 25. 50MHz Oscillator Reference Clock Connection
Table 24. 50MHz Oscillator/Reference Clock Selection Criteria
Characteristics Value Units
Frequency 50 MHz
Frequency to lera nce (maximum) ±50 ppm
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
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Magnetic – Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8081MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8081MNX/RNB side should not be connected to any
power supply source on the board; instead, the center tap pins should be separated from one another and connected
through separate 0.1µF common-mode capacitors to ground. Separ ation is required because the common-mode voltage
is different between transmitting and receiving differential pairs.
Figure 26 shows the typical magnetic interface circuit for the KSZ8081MNX/RNB.
Figure 26. Typical Magnetic Interface Circuit
Micrel, Inc.
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Table 25 lists recommended magnetic characteristics.
Table 25. Magnetics Selection Criteria
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (minimum) 350µH 100mV, 100kHz, 8mA
Inser tion loss (typical) –1.1dB 100kHz to 100M Hz
HIPOT (minimum) 1500Vrms
Table 26 is a l is t of c om pati ble s i ng le-port magnet ics with s ep arated transf or mer center ta p p ins on t he PHY chip sid e th at
can be used with the KSZ8081MNX/RNB.
Table 26. Compatible Single-Port 10/100 Magnetics
Manufacturer Part Number Temperature Range Magnetic + RJ-45
Bel Fus e S558-5999-U7 0°C to 70°C No
Bel Fus e SI-46001-F 0°C to 70°C Yes
Bel Fus e SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70°C No
Pulse H1260 0°C to 70°C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C to 70°C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70°C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
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