PIC32MX110F016B-I/SS - Microchip Technology

PIC32MX1XX/2XX

Operating Conditions

• 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz

Core: 40 MHz MIPS32® M4K®

• MIPS16e® mode for up to 40% smaller code size

• 1.56 DMIPS/MHz (Dhrystone 2.1) performance

• Code-efficient (C and Assembly) architecture

• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

Clock Management

• 0.9% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer

• Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep, Idle)

• Integrated Power-on Reset and Brown-out Reset

• 0.5 mA/MHz dynamic current (typical)

•20 μA IPD current (typical)

Audio Interface Features

• Data communication: I2S, LJ, RJ, DSP modes

• Control interface: SPI and I2C™

• Master clock:

- Generation of fractional clock frequencies

- Can be synchronized with USB clock

- Can be tuned in run-time

Advanced Analog Features

• ADC Module:

- 10-bit 1.1 Msps rate with one S&H

- Up to 10 analog inputs on 28-pin devices and 13

analog inputs on 44-pin devices

• Flexible and independent ADC trigger sources

• Charge Time Measurement Unit (CTMU):

- Supports mTouch™ capacitive touch sensing

- Provides high-resolution time measurement (1 ns)

- On-chip temperature measurement capability

• Comparators:

- Up to three Analog Comparator modules

- Programmable references with 32 voltage points

Timers/Output Compare/Input Capture

• Five General Purpose Timers:

- Five 16-bit and up to two 32-bit Timers/Counters

• Five Output Compare (OC) modules

• Five Input Capture (IC) modules

• Peripheral Pin Select (PPS) to allow function remap

• Real-Time Clock and Calendar (RTCC) module

Communication Interfaces

• USB 2.0-compliant Full-speed OTG controller

• Two UART modules (10 Mbps)

- Supports LIN 2.0 protocols and IrDA® support

• Two 4-wire SPI modules (20 Mbps)

•Two I

2C modules (up to 1 Mbaud) with SMBus support

• Peripheral Pin Select (PPS) to allow function remap

• Parallel Master Port (PMP)

Direct Memory Access (DMA)

• Four channels of hardware DMA with automatic data

size detection

• Two additional channels dedicated for USB

• Programmable Cyclic Redundancy Check (CRC)

Input/Output

• 15 mA source/sink on all I/O pins

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• External interrupts on all I/O pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

•4-wire MIPS

® Enhanced JTAG interface

• Unlimited program and six complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

Packages

Type SOIC SSOP SPDIP QFN VTLA TQFP

Pin Count 28 28 28 28 44 36 44 44

I/O Pins (up to) 21 21 21 21 34 25 34 34

Contact/Lead Pitch 1.27 0.65 0.100'' 0.65 0.65 0.50 0.50 0.80

Dimensions 17.90x7.50x2.65 10.2x5.3x2 1.365x.285x.135'' 6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1

Note: All dimensions are in millimeters (mm) unless specified.

32-bit Micr ocontr ollers (up to 128 KB Flash and 32 KB SRAM) with

Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX

TABLE 1: PIC32MX1XX GENERAL PURPOSE FAMILY FEATURES

Device

Pins

Program Memory (KB)(1)

Data Memory (KB)

Remappable Peripherals

Analog Comparators

USB On-The-Go (OTG)

I2C™

PMP

DMA Channels

(Programmable/Dedicated)

CTMU

10-bit 1 Msps ADC (Channels)

RTCC

I/O Pins

JTAG

Packages

Remappable Pins

Timers(2)/Capture/Compare

UART

SPI/I2S

External Interrupts(3)

PIC32MX110F016B 28 16+3 4 20 5/5/5 2253N2Y4/2Y10Y21Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX110F016C 36 16+3 4 24 5/5/5 2253N2Y4/2Y12Y25YVTLA

PIC32MX110F016D 44 16+3 4 32 5/5/5 2253N2Y4/2Y13Y34Y

VTLA,

TQFP,

QFN

PIC32MX120F032B 28 32+3 8 20 5/5/5 2253N2Y4/2Y10Y21Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX120F032C 36 32+3 8 24 5/5/5 2253N2Y4/2Y12Y25YVTLA

PIC32MX120F032D 44 32+3 8 32 5/5/5 2253N2Y4/2Y13Y34Y

VTLA,

TQFP,

QFN

PIC32MX130F064B 28 64+3 16 20 5/5/5 2253N2Y4/2Y10Y21Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX130F064C 36 64+3 16 24 5/5/5 2253N2Y4/2Y12Y25YVTLA

PIC32MX130F064D 44 64+3 16 32 5/5/5 2253N2Y4/2Y13Y34Y

VTLA,

TQFP,

QFN

PIC32MX150F128B 28 128+3 32 20 5/5/5 2253N2Y4/2Y10Y21Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX150F128C 36 128+3 32 24 5/5/5 2253N2Y4/2Y12Y25YVTLA

PIC32MX150F128D 44 128+3 32 32 5/5/5 2253N2Y4/2Y13Y34Y

VTLA,

TQFP,

QFN

Note 1: This device features 3 KB of boot Flash memory.

2: Four out of five timers are remappable.

3: Four out of five external interrupts are remappable.

PIC32MX1XX/2XX

TABLE 2: PIC32MX2XX USB FAMILY FEATURES

Device

Pins

Program Memory (KB)(1)

Data Memory (KB)

Remappable Peripherals

Analog Comparators

USB On-The-Go (OTG)

I2C™

PMP

DMA Channels

(Programmable/Dedicated)

CTMU

10-bit 1 Msps ADC (Channels)

RTCC

I/O Pins

JTAG

Packages

Remappable Pins

Timers(2)/Capture/Compare

UART

SPI/I2S

External Interrupts(3)

PIC32MX210F016B 28 16+3 4 19 5/5/5 2253Y2Y4/2Y9Y19Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX210F016C 36 16+3 4 23 5/5/5 2253Y2Y4/2Y12Y23YVTLA

PIC32MX210F016D 44 16+3 4 31 5/5/5 2253Y2Y4/2Y13Y33Y

VTLA,

TQFP,

QFN

PIC32MX220F032B 28 32+3 8 19 5/5/5 2253Y2Y4/2Y9Y19Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX220F032C 36 32+3 8 23 5/5/5 2253Y2Y4/2Y12Y23YVTLA

PIC32MX220F032D 44 32+3 8 31 5/5/5 2253Y2Y4/2Y13Y33Y

VTLA,

TQFP,

QFN

PIC32MX230F064B 28 64+3 16 19 5/5/52253Y2Y4/2Y9Y19Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX230F064C 36 64+3 16 23 5/5/52253Y2Y4/2Y12Y23YVTLA

PIC32MX230F064D 44 64+3 16 31 5/5/52253Y2Y4/2Y13Y33Y

VTLA,

TQFP,

QFN

PIC32MX250F128B 28 128+3 32 19 5/5/52253Y2Y4/2Y9Y19Y

SOIC,

SSOP,

SPDIP,

QFN

PIC32MX250F128C 36 128+3 32 23 5/5/52253Y2Y4/2Y12Y23YVTLA

PIC32MX250F128D 44 128+3 32 31 5/5/52253Y2Y4/2Y13Y33Y

VTLA,

TQFP,

QFN

Note 1: This device features 3 KB of boot Flash memory.

2: Four out of five timers are remappable.

3: Four out of five external interrupts are remappable.

PIC32MX1XX/2XX

Pin Diagrams

Note 1: The RPn pins can be used by remappable peripherals. See Tabl e 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

MCLR

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

VREF-/CVREF-/AN1/RPA1/CTED2/RA1 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN11/RPB13/CTPLS/PMRD/RB13

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN12/PMD0/RB12

PGEC2/TMS/RPB11/PMD1/RB11

VSS PGED2/RPB10/CTED11/PMD2/RB10

OSC1/CLKI/RPA2/RA2

OSC2/CLKO/RPA3/PMA0/RA3 VSS

SOSCI/RPB4/RB4 TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 TCK/RPB8/SCL1/CTED10/PMD4/RB8

VDD TDI/RPB7/CTED3/PMD5/INT0/RB7

PGEC3/RPB6/PMD6/RB6

MCLR AVDD

AVSS

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3

VSS

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

VDD

MCLR

VSS

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

VDD

28-Pin SOIC, SPDIP, SSOP(1,2) = Pins are up to 5V tolerant

MCLR

VSS

VCAP

VSS

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

VDD

PGED3/RPB5/PMD7/RB5

MCLR 128AVDD

PGED3/V

REF

+/CV

REF

+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

227AVSS

PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 3 26 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 4 25 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 5 24 AN11/RPB13/CTPLS/PMRD/RB13

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 6 23 VUSB

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 7 22 PGEC2/RPB11/D-/RB11

VSS 8 21 PGED2/RPB10/D+/CTED11/RB10

OSC1/CLKI/RPA2/RA2 9 20 VCAP

OSC2/CLKO/RPA3/PMA0/RA3 10 19 VSS

SOSCI/RPB4/RB4 11 18 TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 12 17 TCK/RPB8/SCL1/CTED10/PMD4/RB8

VDD 13 16 TDI/RPB7/CTED3/PMD5/INT0/RB7

TMS/RPB5/USBID/RB5 14 15 VBUS

PIC32MX220F032B

PIC32MX220F016B

128

227

326

425

524

623

722

821

920

10 19

11 18

12 17

13 16

14 15

PIC32MX120F032B

PIC32MX120F016B

PIC32MX130F064B

PIC32MX150F128B PIC32MX230F064B

PIC32MX250F128B

PIC32MX1XX/2XX

Pin Diagrams (Continued)

28-Pin QFN(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

VREF-/CVREF-/AN1/RPA1/CTED2/RA1

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

MCLR

AVDD

AVSS

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 121AN11/RPB13/CTPLS/PMRD/RB13

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 220AN12/PMD0/RB12

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 319PGEC2/TMS/RPB11/PMD1/RB11

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 4

PIC32MX120F032B

18 PGED2/RPB10/CTED11/PMD2/RB10

VSS 517VCAP

OSC1/CLKI/RPA2/RA2 616VSS

OSC2/CLKO/RPA3/PMA0/RA3 715TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCI/RPB4/RB4

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

VDD

PGED3/RPB5/PMD7/RB5

PGEC3/RPB6/PMD6/RB6

TDI/RPB7/CTED3/PMD5/INT0/RB7

TCK/RPB8/SCL1/CTED10/PMD4/RB8

PIC32MX120F016B

PIC32MX130F064B

PIC32MX150F128B

PIC32MX1XX/2XX

Pin Diagrams (Continued)

28-Pin QFN(1,2,3) = Pins are up to 5V tolerant

PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1

PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

MCLR

AVDD

AVSS

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 121AN11/RPB13/CTPLS/PMRD/RB13

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 220VUSB

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 319PGEC2/RPB11/D-/RB11

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 4PIC32MX220F032B 18 PGED2/RPB10/D+/CTED11/RB10

VSS 517VCAP

OSC1/CLKI/RPA2/RA2 616VSS

OSC2/CLKO/RPA3/PMA0/RA3 715TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCI/RPB4/RB4

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

VDD

TMS/RPB5/USBID/RB5

VBUS

TDI/RPB7/CTED3/PMD5/INT0/RB7

TCK/RPB8/SCL1/CTED10/PMD4/RB8

PIC32MX220F016B

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

PIC32MX230F064B

PIC32MX250F128B

PIC32MX1XX/2XX

Pin Diagrams (Continued)

36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 1 1.3 “Peripheral Pin

Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX130F064C and PIC32MX150F128C devices only.

PIC32MX120F016C

PIC32MX120F032C

33 32 31 30 29 28

11 12 13 14 15

16 17 18

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0

VREF-/CVREF-/AN1/RPA1/CTED2/RA1

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

MCLR

AVDD

AVSS

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2

AN11/RPB13/CTPLS/PMRD/RB13

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3

AN12/PMD0/RB12

PGED(4)/AN6/RPC0/RC0

PGEC2/TMS/RPB11/PMD1/RB11

PGEC(4)/AN7/RPC1/RC1

PGED2/RPB10/CTED11/PMD2/RB10

VDD

VSS

VCAP

OSC1/CLKI/RPA2/RA2

VSS

OSC2/CLKO/RPA3/PMA0/RA3

RPC9/CTED7/RC9

SOSCI/RPB4/RB4

TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

RPC3/RC3

VSS

VDD

PGED3/RPB5/PMD7/RB5

PGEC3/RPB6/PMD6/RB6

TDI/RPB7/CTED3/PMD5/INT0/RB7

TCK/RPB8/SCL1/CTED10/PMD4/RB8

PIC32MX130F064C

PIC32MX150F128C

PIC32MX1XX/2XX

Pin Diagrams (Continued)

36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX230F064C and PIC32MX250F128C devices only.

PIC32MX220F016C

PIC32MX220F032C

33 32 31 30 29 28

11 12 13 14 15

16 17 18

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0

PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1

PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

MCLR

AVDD

AVSS

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2

AN11/RPB13/CTPLS/PMRD/RB13

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3

VUSB

PGED4(4)/AN6/RPC0/RC0

PGEC2/RPB11/D-/RB11

PGEC4(4)/AN7/RPC1/RC1

PGED2/RPB10/D+/CTED11/RB10

VDD

VCAP

OSC1/CLKI/RPA2/RA2

VSS

OSC2/CLKO/RPA3/PMA0/RA3

RPC9/CTED7/RC9

SOSCI/RPB4/RB4

TDO/RPB9/SDA1/CTED4/PMD3/RB9

SOSCO/RPA4/T1CK/CTED9/PMA1/RA4

AN12/RPC3/RC3

VSS

VDD

TMS/RPB5/USBID/RB5

VBUS

TDI/RPB7/CTED3/PMD5/INT0/RB7

TCK/RPB8/SCL1/CTED10/PMD4/RB8

VDD

VSS

PIC32MX230F064C

PIC32MX250F128C

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin QFN(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

PGEC3/RPB6/PMD6/RB6

PGED3/RPB5/PMD7/RB5

VDD

VSS

RPC5/PMA3/RC5

RPC4/PMA4/RC4

RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4

RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9 5 29 VSS

VSS 6

PIC32MX120F032D

28 VDD

VCAP 7 27 AN8/RPC2/PMA2/RC2

PGED2/RPB10/CTED11/PMD2/RB10 8 26 AN7/RPC1/RC1

PGEC2/RPB11/PMD1/RB11 9 25 AN6/RPC0/RC0

AN12/PMD0/RB12 10 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3

AN11/RPB13/CTPLS/PMRD/RB13 11 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2

PGED4(4)/TMS/PMA10/RA10

PGEC(4)/TCK/CTED8/PMA7/RA7

CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

AVSS

AVDD

MCLR

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

VREF-/CVREF-/AN1/RPA1/CTED2/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1

PIC32MX120F016D

PIC32MX130F064D

PIC32MX150F128D

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin QFN(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

VBUS

RPB5/USBID/RB5

VDD

VSS

RPC5/PMA3/RC5

RPC4/PMA4/RC4

AN12/RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

1 33 SOSCI/RPB4/RB4

RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9 5 29 VSS

VSS 6

PIC32MX220F032D

28 VDD

VCAP 7 27 AN8/RPC2/PMA2/RC2

8 26 AN7/RPC1/RC1

PGEC2/RPB11/D-/RB11 9 25 AN6/RPC0/RC0

VUSB 10 24

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3

AN11/RPB13/CTPLS/PMRD/RB13 11 23

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2

PGED(4)/TMS/PMA10/RA10

PGEC(4)/TCK/CTED8/PMA7/RA7

CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

AVSS

AVDD

MCLR

PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1

PGED2/RPB10/D+/CTED11/RB10

RPB9/SDA1/CTED4/PMD3/RB9

PIC32MX220F016D

PIC32MX230F064D

PIC32MX250F128D

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin TQFP(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

PGEC3/RPB6/PMD6/RB6

PGED3/RPB5/PMD7/RB5

VDD

VSS

RPC5/PMA3/RC5

RPC4/PMA4/RC4

RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

RPB9/SDA1/CTED4/PMD3/RB9 1 33 SOSCI/RPB4/RB4

RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9 5 29 VSS

VSS 6

PIC32MX120F032D

28 VDD

VCAP 7 27 AN8/RPC2/PMA2/RC2

PGED2/RPB10/CTED11/PMD2/RB10 8 26 AN7/RPC1/RC1

PGEC2/RPB11/PMD1/RB11 9 25 AN6/RPC0/RC0

AN12/PMD0/RB12 10 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3

AN11/RPB13/CTPLS/PMRD/RB13 11 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2

PGED(4)/TMS/PMA10/RA10

PGEC(4)/TCK/CTED8/PMA7/RA7

CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

AVSS

AVDD

MCLR

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

VREF-/CVREF-/AN1/RPA1/CTED2/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1

PIC32MX120F016D

PIC32MX130F064D

PIC32MX150F128D

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

PGEC3/RPB6/PMD6/RB6

PGED3/RPB5/PMD7/RB5

VDD

VSS

RPC5/PMA3/RC5

RPC4/PMA4/RC4

RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

RPB9/SDA1/CTED4/PMD3/RB9

SOSCI/RPB4/RB4

RPC6/PMA1/RC6

TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7

OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8

OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9

VSS

PIC32MX120F032D VDD

VCAP

AN8/RPC2/PMA2/RC2

PGED2/RPB10/CTED11/PMD2/RB10

AN7/RPC1/RC1

PGEC2/RPB11/PMD1/RB11

AN6/RPC0/RC0

AN12/PMD0/RB12

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2

PGEC(4)/TCK/CTED8/PMA7/RA7

CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

AVSS

AVDD

MCLR

VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0

VREF-/CVREF-/AN1/RPA1/CTED2/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0

PIC32MX120F016D

2221201911 12 13 14 15

343536

16 17 18

3738394041424344

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1

AN11/RPB13/CTPLS/PMRD/RB13

PIC32MX130F064D

PIC32MX150F128D

PGED(4)/TMS/PMA10/RA10

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin TQFP(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

VBUS

RPB5/USBID/RB5

VDD

VSS

RPC5/PMA3/RC5

RPC4/PMA4/RC4

AN12/RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

1 33 SOSCI/RPB4/RB4

RPC6/PMA1/RC6 2 32 TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7 3 31 OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8 4 30 OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9 5 29 VSS

VSS 6

PIC32MX220F032D

28 VDD

VCAP 7 27 AN8/RPC2/PMA2/RC2

8 26 AN7/RPC1/RC1

PGEC2/RPB11/D-/RB11 9 25 AN6/RPC0/RC0

VUSB 10 24

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3

AN11/RPB13/CTPLS/PMRD/RB13 11 23

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2

PGED(4)/TMS/PMA10/RA10

PGEC(4)/TCK/CTED8/PMA7/RA7

CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

AVSS

AVDD

MCLR

PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1

PGED2/RPB10/D+/CTED11/RB10

RPB9/SDA1/CTED4/PMD3/RB9

PIC32MX220F016D

PIC32MX230F064D

PIC32MX250F128D

PIC32MX1XX/2XX

Pin Diagrams (Continued)

44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral

Pin Select” for restrictions.

2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more

information.

3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

4: This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only.

RPB8/SCL1/CTED10/PMD4/RB8

RPB7/CTED3/PMD5/INT0/RB7

BUS

RPB5/USBID/RB5

RPC5/PMA3/RC5

RPC4/PMA4/RC4

AN12/RPC3/RC3

TDI/RPA9/PMA9/RA9

SOSCO/RPA4/T1CK/CTED9/RA4

SOSCI/RPB4/RB4

RPC6/PMA1/RC6

TDO/RPA8/PMA8/RA8

RPC7/PMA0/RC7

OSC2/CLKO/RPA3/RA3

RPC8/PMA5/RC8

OSC1/CLKI/RPA2/RA2

RPC9/CTED7/PMA6/RC9

CAP

AN8/RPC2/PMA2/RC2

AN7/RPC1/RC1

PGEC2/RPB11/D-/RB11

AN6/RPC0/RC0

USB

AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3

AN11/RPB13/CTPLS/PMRD/RB13

AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2

PGED

(4)

/TMS/PMA10/RA10

PGEC

(4)

/TCK/CTED8/PMA7/RA7

REF

/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14

AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15

MCLR

PGED3/V

REF

+/CV

REF

+/AN0/C3INC/RPA0/CTED1/PMD7/RA0

PGEC3/V

REF

-/CV

REF

-/AN1/RPA1/CTED2/PMD6/RA1

PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0

PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1

PGED2/RPB10/D+/CTED11/RB10

RPB9/SDA1/CTED4/PMD3/RB9

PIC32MX220F032D

PIC32MX220F016D

2221201911 12 13 14 15

343536

16 17 18

3738394041424344

PIC32MX230F064D

PIC32MX250F128D

© 2011 Microchip Technology Inc. Preliminary DS61168C-page 15
PIC32MX1XX/2XX
Table of Contents
0 Device Overview ........................................................................................................................................................................ 19
0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 27
0 CPU............................................................................................................................................................................................ 33
0 Memory Organization ................................................................................................................................................................. 37
0 Flash Program Memory.............................................................................................................................................................. 79
0 Resets ........................................................................................................................................................................................ 83
0 Interrupt Controller ..................................................................................................................................................................... 87
0 Oscillator Configuration .............................................................................................................................................................. 95
0 Direct Memory Access (DMA) Controller ................................................................................................................................. 105
0 USB On-The-Go (OTG)............................................................................................................................................................ 121
0 I/O Ports ................................................................................................................................................................................... 143
0 Timer1 ...................................................................................................................................................................................... 151
0 Timer2/3, Timer4/5 ................................................................................................................................................................... 155
0 Input Capture............................................................................................................................................................................ 159
0 Output Compare....................................................................................................................................................................... 163
0 Serial Peripheral Interface (SPI)............................................................................................................................................... 165
0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 173
0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 179
0 Parallel Master Port (PMP)....................................................................................................................................................... 185
0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 193
0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 203
0 Comparator .............................................................................................................................................................................. 211
0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 215
0 Charge Time Measurement Unit (CTMU)  ............................................................................................................................... 217
0 Power-Saving Features ........................................................................................................................................................... 221
0 Special Features ...................................................................................................................................................................... 225
0 Instruction Set .......................................................................................................................................................................... 239
0 Development Support............................................................................................................................................................... 241
0 Electrical Characteristics .......................................................................................................................................................... 245
0 DC and AC Device Characteristics Graphs.............................................................................................................................. 285
0 Packaging Information.............................................................................................................................................................. 289
The Microchip Web Site ..................................................................................................................................................................... 315
Customer Change Notification Service .............................................................................................................................................. 315
Customer Support.............................................................................................................................................................................. 315
Reader Response .............................................................................................................................................................................. 316
Product Identification System ............................................................................................................................................................ 317

PIC32MX1XX/2XX

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department

via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notific at ion Syst em

PIC32MX1XX/2XX

Referenced Sources

This device data sheet is based on the following

individual chapters of the “PIC32 Family Reference

Manual”. These documents should be considered as

the general reference for the operation of a particular

module or device feature.

•Section 1. “Introduction” (DS61127)

•Section 2. “CPU” (DS61113)

•Section 3. “Memory Organization” (DS61115)

•Section 5. “Flash Program Memory” (DS61121)

•Section 6. “Oscillator Configuration” (DS61112)

•Section 7. “Resets” (DS61118)

•Section 8. “Interrupt Controller” (DS61108)

•Section 9. “Watchdog Timer and Power-up Timer” (DS61114)

•Section 10. “Power-Saving Features” (DS61130)

•Section 12. “I/O Ports” (DS61120)

•Section 13. “Parallel Master Port (PMP)” (DS61128)

•Section 14. “Timers” (DS61105)

•Section 15. “Input Capture” (DS61122)

•Section 16. “Output Compare” (DS61111)

•Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104)

•Se c t i o n 1 9 . “Comparator” (DS61110)

•Section 20. “Comparator Voltage Reference (CVREF)” (DS61109)

•Section 21. “Universal Asynchronous Rece iver Transmitter (UART)” (DS61107)

•Section 23. “Serial Peripheral Interface (SPI)” (DS61106)

•Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS61116)

•Section 27. “USB On-The-Go (OTG)” (DS61126)

•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125)

•Section 31. “Direct Memory Access (DMA) Controller” (DS61117)

•Section 32. “Configuration” (DS61124)

•Section 33. “Programming and Diagnostics” (DS61129)

•Section 37. “Charge Time Measurement Unit (CTMU)” (DS61167)

Note: To access the documents listed below,

browse to the documentation section of

the Microchip web site

(www.microchip.com).

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

1.0 DEVICE OVERVIEW This document contains device-specific information for

PIC32MX1XX/2XX devices.

Figure 1-1 illustrates a general block diagram of the

core and peripheral modules in the PIC32MX1XX/2XX

family of devices.

Table 1-1 lists the functions of the various pins shown

in the pinout diagrams.

FIGURE 1-1: BLOCK DIAGRAM(1)

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section of the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note 1: Some features are not available on all device variants.

UART1-2

Comparators 1-3

PORTA

Remappable

PORTB

CTMU

JTAG Priority

DMAC

ICD

MIPS32® M4K®

IS DS

EJTAG INT

Bus Matrix

Data RAM Peripheral Bridge

128

128-bit Wide

Flash

32 32

Peripheral Bus Clocked by PBCLK

Program Flash Memory

Controller

32 32

Interrupt

Controller

BSCAN

PORTC

PMP

I2C1-2

SPI1-2

IC1-5

PWM

OC1-5

OSC1/CLKI

OSC2/CLKO

VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators Regulator

Voltage

VCAP

OSC/SOSC

Oscillators

PLL

Dividers

SYSCLK

PBCLK

Peripheral Bus Clocked by SYSCLK

USB

PLL-USB USBCLK

RTCC

10-bit ADC

Timer1-5

CPU Core

Pins

PIC32MX1XX/2XX

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

AN0 27 2 33 19 I Analog Analog input channels.

AN1 28 3 34 20 I Analog

AN2 1 4 35 21 I Analog

AN3 2 5 36 22 I Analog

AN4 3 6 1 23 I Analog

AN5 4 7 2 24 I Analog

AN6 — — 3 25 I Analog

AN7 — — 4 26 I Analog

AN8 — — — 27 I Analog

AN9 23262915IAnalog

AN10 22 25 28 14 I Analog

AN11 21 24 27 11 I Analog

AN12 20(2) 23(2) 26(2) 10(2)

IAnalog

11(3) 36(3)

CLKI 6 9 7 30 I ST/CMOS External clock source input. Always

associated with OSC1 pin function.

CLKO 7 10 8 31 O — Oscillator crystal output. Connects to

crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in

RC and EC modes. Always associated

with OSC2 pin function.

OSC1 6 9 7 30 I ST/CMOS Oscillator crystal input. ST buffer when

configured in RC mode; CMOS

otherwise.

OSC2 7 10 8 31 I/O — Oscillator crystal output. Connects to

crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in

RC and EC modes.

SOSCI 8 11 9 33 I ST/CMOS 32.768 kHz low-power oscillator crystal

input; CMOS otherwise.

SOSCO 9 12 10 34 O — 32.768 kHz low-power oscillator crystal

output.

REFCLKI PPS PPS PPS PPS I ST Reference Input Clock

REFCLKO PPS PPS PPS PPS O — Reference Output Clock

IC1 PPS PPS PPS PPS I ST Capture Inputs 1-5

IC2 PPS PPS PPS PPS I ST

IC3 PPS PPS PPS PPS I ST

IC4 PPS PPS PPS PPS I ST

IC5 PPS PPS PPS PPS I ST

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

OC1 PPS PPS PPS PPS O — Output Compare Output 1

OC2 PPS PPS PPS PPS O — Output Compare Output 2

OC3 PPS PPS PPS PPS O — Output Compare Output 3

OC4 PPS PPS PPS PPS O — Output Compare Output 4

OC5 PPS PPS PPS PPS O — Output Compare Output 5

OCFA PPS PPS PPS PPS I ST Output Compare Fault A Input

OCFB PPS PPS PPS PPS I ST Output Compare Fault B Input

INT0 13 16 17 43 I ST External Interrupt 0

INT1 PPS PPS PPS PPS I ST External Interrupt 1

INT2 PPS PPS PPS PPS I ST External Interrupt 2

INT3 PPS PPS PPS PPS I ST External Interrupt 3

INT4 PPS PPS PPS PPS I ST External Interrupt 4

RA0 27 2 33 19 I/O ST PORTA is a bidirectional I/O port

RA1 28 3 34 20 I/O ST

RA2 6 9 7 30 I/O ST

RA3 7 10 8 31 I/O ST

RA4 9 12 10 34 I/O ST

RA7 — — — 13 I/O ST

RA8 — — — 32 I/O ST

RA9 — — — 35 I/O ST

RA10 — — — 12 I/O ST

RB0 1 4 35 21 I/O ST PORTB is a bidirectional I/O port

RB1 2 5 36 22 I/O ST

RB2 3 6 1 23 I/O ST

RB3 4 7 2 24 I/O ST

RB4 8 11 9 33 I/O ST

RB5 11141541I/OST

RB6 12(2) 15(2) 16(2) 42(2) I/O ST

RB7 13161743I/OST

RB8 14171844I/OST

RB9 15 18 19 1 I/O ST

RB10 18 21 24 8 I/O ST

RB11 19 22 25 9 I/O ST

RB12 20(2) 23(2) 26(2) 10(2) I/O ST

RB13 21 24 27 11 I/O ST

RB14 22 25 28 14 I/O ST

RB15 23 26 29 15 I/O ST

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

RC0 — — 3 25 I/O ST PORTC is a bidirectional I/O port

RC1 — — 4 26 I/O ST

RC2 — — — 27 I/O ST

RC3 — — 11 36 I/O ST

RC4 — — — 37 I/O ST

RC5 — — — 38 I/O ST

RC6 — — — 2 I/O ST

RC7 — — — 3 I/O ST

RC8 — — — 4 I/O ST

RC9 — — 20 5 I/O ST

T1CK 9 12 10 34 I ST Timer1 external clock input

T2CK PPS PPS PPS PPS I ST Timer2 external clock input

T3CK PPS PPS PPS PPS I ST Timer3 external clock input

T4CK PPS PPS PPS PPS I ST Timer4 external clock input

T5CK PPS PPS PPS PPS I ST Timer5 external clock input

U1CTS PPS PPS PPS PPS I ST UART1 clear to send

U1RTS PPS PPS PPS PPS O — UART1 ready to send

U1RX PPS PPS PPS PPS I ST UART1 receive

U1TX PPS PPS PPS PPS O — UART1 transmit

U2CTS PPS PPS PPS PPS I ST UART2 clear to send

U2RTS PPS PPS PPS PPS O — UART2 ready to send

U2RX PPS PPS PPS PPS IST

UART2 receive

U2TX PPS PPS PPS PPS O—

UART2 transmit

SCK1 22 25 28 14 I/O ST Synchronous serial clock input/output for

SPI1

SDI1 PPS PPS PPS PPS IST

SPI1 data in

SDO1 PPS PPS PPS PPS O—

SPI1 data out

SS1 PPS PPS PPS PPS I/O ST SPI1 slave synchronization or frame

pulse I/O

SCK2 23 26 29 15 I/O ST Synchronous serial clock input/output for

SPI2

SDI2 PPS PPS PPS PPS IST

SPI2 data in

SDO2 PPS PPS PPS PPS O—

SPI2 data out

SS2 PPS PPS PPS PPS I/O ST SPI2 slave synchronization or frame

pulse I/O

SCL1 28 3 34 20 I/O ST Synchronous serial clock input/output for

I2C1

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

SDA1 27 2 33 19 I/O ST Synchronous serial data input/output for

I2C1

SCL2 12(2) 15(2) 16(2) 42(2) I/O ST Synchronous serial clock input/output for

I2C2

SDA2 11(2) 14(2) 15(2) 41(2) I/O ST Synchronous serial data input/output for

I2C2

TMS 19(2) 22(2) 25(2)

12 I ST JTAG Test mode select pin

11(3) 14(3) 15(3)

TCK 14 17 18 13 I ST JTAG test clock input pin

TDI 13 16 17 35 O — JTAG test data input pin

TDO 15 18 19 32 O — JTAG test data output pin

RTCC 4 7 2 24 I ST Real-Time Clock alarm output

CVREF- 28 3 34 20 I Analog Comparator Voltage Reference (low)

CVREF+ 27 2 33 19 I Analog Comparator Voltage Reference (high)

CVREFOUT 22 25 28 14 O Analog Comparator Voltage Reference output

C1INA 4 7 2 24 I Analog Comparator Inputs

C1INB 3 6 1 23 I Analog

C1INC 2 5 36 22 I Analog

C1IND 1 4 35 21 I Analog

C2INA 2 5 36 22 I Analog

C2INB 1 4 35 21 I Analog

C2INC 4 7 2 24 I Analog

C2IND 3 6 1 23 I Analog

C3INA 23262915IAnalog

C3INB 22252814IAnalog

C3INC 27 2 33 19 I Analog

C3IND 1 4 35 21 I Analog

C1OUT PPS PPS PPS PPS O — Comparator Outputs

C2OUT PPS PPS PPS PPS O —

C3OUT PPS PPS PPS PPS O —

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

PMA0 7 10 8 3 I/O TTL/ST Parallel Master Port Address bit 0 input

(Buffered Slave modes) and output

(Master modes)

PMA1 9 12 10 2 I/O TTL/ST Parallel Master Port Address bit 1 input

(Buffered Slave modes) and output

(Master modes)

PMA2 — — 27 O — Parallel Master Port address

(Demultiplexed Master modes)

PMA3 — — 38 O —

PMA4 — — 37 O —

PMA5 — — 4 O —

PMA6 — — 5 O —

PMA7 — — 13 O —

PMA8 — — 32 O —

PMA9 — — 35 O —

PMA10 — — 12 O —

PMCS1 23 26 29 15 O — Parallel Master Port Chip Select 1 strobe

PMD0 20(2) 23(2) 26(2) 10(2)

I/O TTL/ST Parallel Master Port data (Demultiplexed

Master mode) or address/data

(Multiplexed Master modes)

1(3) 4(3) 35(3) 21(3)

PMD1 19(2) 22(2) 25(2) 9(2)

I/O TTL/ST

2(3) 5(3) 36(3) 22(3)

PMD2 18(2) 21(2) 24(2) 8(2)

I/O TTL/ST

3(3) 6(3) 1(3) 23(3)

PMD3 15 18 19 1 I/O TTL/ST

PMD4 14 17 18 44 I/O TTL/ST

PMD5 13 16 17 43 I/O TTL/ST

PMD6 12(2) 15(2) 16(2) 42(2)

I/O TTL/ST

28(3) 3(3) 34(3) 20(3)

PMD7 11(2) 14(2) 15(2) 41(2)

I/O TTL/ST

27(3) 2(3) 33(3) 19(3)

PMRD 21 24 27 11 O — Parallel Master Port read strobe

PMWR 22(2) 25(2) 28(2) 14(2)

O — Parallel Master Port write strobe

4(3) 7(3) 2(3) 24(3)

VBUS 12 15 16 42 I Analog USB bus power monitor

VUSB 20 23 26 10 P — USB internal transceiver supply. If the

USB module is not used, this pin must be

connected to VDD.

VBUSON 22 25 28 14 O — USB Host and OTG bus power control

output

D+ 18 21 24 8 I/O Analog USB D+

D- 19 22 25 9 I/O Analog USB D-

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

USBID 11 14 15 41 I ST USB OTG ID detect

CTED1 27 2 33 19 I ST CTMU External Edge Input

CTED2 28 3 34 20 I ST

CTED313161743IST

CTED4 15 18 19 1 I ST

CTED522252814IST

CTED623262915IST

CTED7 — — 20 5 I ST

CTED8 — — — 13 I ST

CTED9 9 12 10 34 I ST

CTED10 14 17 18 44 I ST

CTED11 18 21 24 8 I ST

CTED12 2 5 36 22 I ST

CTED13 3 6 1 23 I ST

CTPLS 21 24 27 11 O — CTMU Pulse Output

PGED1 1 4 35 21 I/O ST Data I/O pin for Programming/Debugging

Communication Channel 1

PGEC1 2 5 36 22 I ST Clock input pin for

Programming/Debugging

Communication Channel 1

PGED2 18 21 24 8 I/O ST Data I/O pin for Programming/Debugging

Communication Channel 2

PGEC2 19 22 25 9 I ST Clock input pin for

Programming/Debugging

Communication Channel 2

PGED3 11(2) 14(2) 15(2) 41(2)

I/O ST Data I/O pin for Programming/Debugging

Communication Channel 3

27(3) 2(3) 33(3) 19(3)

PGEC3 12(2) 15(2) 16(2) 42(2)

IST

Clock input pin for Programming/

Debugging Communication Channel 3

28(3) 3(3) 34(3) 20(3)

PGED4 — — 3 12 I/O ST Data I/O pin for Programming/Debugging

Communication Channel 4

PGEC4 — — 4 13 IST

Clock input pin for Programming/

Debugging Communication Channel 4

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

MCLR 26 1 32 18 I/P ST Master Clear (Reset) input. This pin is an

active-low Reset to the device.

AVDD 25 28 31 17 P — Positive supply for analog modules. This

pin must be connected at all times.

AVSS 24 27 30 16 P — Ground reference for analog modules

VDD 10 13 5, 13, 14,

28, 40 P — Positive supply for peripheral logic and

I/O pins

VCAP 17 20 22 7 P — CPU logic filter capacitor connection

VSS 5, 16 8, 19 6, 12, 21 6, 29, 39 P — Ground reference for logic and I/O pins.

This pin must be connected at all times.

VREF+ 27 2 33 19 I Analog Analog voltage reference (high) input

VREF- 28 3 34 20 I Analog Analog voltage reference (low) input

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number(1)

Type Buffer

Type Description

28-pin

QFN

28-pin

SSOP/

SPDIP/

SOIC

36-pin

VTLA 44-pin

QFN

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A

Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.

2: Pin number for PIC32MX1XX devices only.

3: Pin number for PIC32MX2XX devices only.

PIC32MX1XX/2XX

2.0 GUIDELINES FOR GETTING

STARTED WITH 32-BIT

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC32MX1XX/2XX family of

32-bit Microcontrollers (MCUs) requires attention to a

minimal set of device pin connections before proceed-

ing with development. The following is a list of pin

names, which must always be connected:

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins, even if the ADC module

is not used

(see Section 2.2 “Decoupling Capacitors”)

•V

CAP pin

(see Section 2.3 “Capacitor on Internal

Voltage Regulator (VCAP)”)

•MCLR

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins, used for In-Circuit Serial

Programming (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins, when external oscillator

source is used

(see Section 2.7 “External Oscillator Pins”)

The following pin may be required, as well:

VREF+/VREF- pins, used when external voltage

reference for the ADC module is implemented.

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply

pins, such as VDD, VSS, AVDD and AVSS is required.

See Figure 2-1.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A value of 0.1 µF

(100 nF), 10-20V is recommended. The capacitor

should be a low Equivalent Series Resistance (low-

ESR) capacitor and have resonance frequency in

the range of 20 MHz and higher. It is further

recommended that ceramic capacitors be used.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close to

the pins as possible. It is recommended that the

capacitors be placed on the same side of the board

as the device. If space is constricted, the capacitor

can be placed on another layer on the PCB using a

via; however, ensure that the trace length from the

pin to the capacitor is within one-quarter inch

(6 mm) in length.

•Handling high freque nc y nois e : If the board is

experiencing high frequency noise, upward of tens

of MHz, add a second ceramic-type capacitor in par-

allel to the above described decoupling capacitor.

The value of the second capacitor can be in the

range of 0.01 µF to 0.001 µF. Place this second

capacitor next to the primary decoupling capacitor.

In high-speed circuit designs, consider implement-

ing a decade pair of capacitances as close to the

power and ground pins as possible. For example,

0.1 µF in parallel with 0.001 µF.

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first, and

then to the device pins. This ensures that the decou-

pling capacitors are first in the power chain. Equally

important is to keep the trace length between the

capacitor and the power pins to a minimum thereby

reducing PCB track inductance.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section of the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: The AVDD and AVSS pins must be

connected, regardless of ADC use and

the ADC voltage reference source.

PIC32

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

0.1 µF

Ceramic

VCAP

10Ω

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

0.1 µF

Ceramic

CBP

CEFC

VUSB(1)

Note 1: If the USB module is not used, this pin

must be connected to VDD.

PIC32MX1XX/2XX

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve

power supply stability. Typical values range from 4.7 µF

to 47 µF. This capacitor should be located as close to

the device as possible.

2.3 Capacitor on Internal Voltage

Regulator (VCAP)

2.3.1 INTERNAL REGULATOR MODE

A low-ESR (1 ohm) capacitor is required on the VCAP

pin, which is used to stabilize the internal voltage regu-

lator output. The VCAP pin must not be connected to

VDD, and must have a CEFC capacitor, with at least a

6V rating, connected to ground. The type can be

ceramic or tantalum. Refer to Section 29.0 “Electr ical

Characteristics” for additional information on CEFC

specifications.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device

functions:

• Device Reset

• Device programming and debugging

Pulling The MCLR pin low generates a device Reset.

Figure 2-2 illustrates a typical MCLR circuit. During

device programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R and C will need to be adjusted based on the

application and PCB requirements.

For example, as illustrated in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Place the components illustrated in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS(1,2,3)

Note 1: R≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

3: The capacitor can be sized to prevent uninten-

tional Resets from brief glitches or to extend

the device Reset period during POR.

VDD

MCLR

PIC32

PIC32MX1XX/2XX

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging pur-

poses. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e.,

PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB® ICD 3 or MPLAB REAL ICE™.

For more information on ICD 3 and REAL ICE

connection requirements, refer to the following

documents that are available on the Microchip web

site.

•“Using MPLAB® ICD 3” (poster) DS51765

•“MPLAB® ICD 3 Design Advisory” DS51764

•“MPLAB® REAL ICE™ In-Circuit Debugger

User’s Guide” DS51616

•“Using MPLAB® REAL ICE™ Emulator” (poster)

DS51749

2.6 JTAG

The TMS, TDO, TDI and TCK pins are used for testing

and debugging according to the Joint Test Action

Group (JTAG) standard. It is recommended to keep the

trace length between the JTAG connector and the

JTAG pins on the device as short as possible. If the

JTAG connector is expected to experience an ESD

event, a series resistor is recommended, with the value

in the range of a few tens of Ohms, not to exceed 100

Ohms.

Pull-up resistors, series diodes and capacitors on the

TMS, TDO, TDI and TCK pins are not recommended

as they will interfere with the programmer/debugger

communications to the device. If such discrete compo-

nents are an application requirement, they should be

removed from the circuit during programming and

debugging. Alternatively, refer to the AC/DC character-

istics and timing requirements information in the

respective device Flash programming specification for

information on capacitive loading limits and pin input

voltage high (VIH) and input low (VIL) requirements.

PIC32MX1XX/2XX

2.7 External Oscillator Pins

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 8.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same side

of the board as the device. Also, place the oscillator cir-

cuit close to the respective oscillator pins, not exceed-

ing one-half inch (12 mm) distance between them. The

load capacitors should be placed next to the oscillator

itself, on the same side of the board. Use a grounded

copper pour around the oscillator circuit to isolate them

from surrounding circuits. The grounded copper pour

should be routed directly to the MCU ground. Do not

run any signal traces or power traces inside the ground

pour. Also, if using a two-sided board, avoid any traces

on the other side of the board where the crystal is

placed. A suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED OSCILLATOR

CIRCUIT PLACEMENT

2.8 Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a

debugger, it automatically initializes all of the analog-to-

digital input pins (ANx) as “digital” pins by setting all bits

in the ADPCFG register.

The bits in this register that correspond to the analog-

to-digital pins that are initialized by MPLAB ICD 2, ICD

3 or REAL ICE, must not be cleared by the user

application firmware; otherwise, communication errors

will result between the debugger and the device.

If your application needs to use certain analog-to-digital

pins as analog input pins during the debug session, the

user application must clear the corresponding bits in

the ADPCFG register during initialization of the ADC

module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used as a

programmer, the user application firmware must cor-

rectly configure the ADPCFG register. Automatic initial-

ization of this register is only done during debugger

operation. Failure to correctly configure the register(s)

will result in all analog-to-digital pins being recognized

as analog input pins, resulting in the port value being

read as a logic ‘0’, which may affect user application

functionality.

2.9 Unused I/Os

Unused I/O pins should not be allowed to float as

inputs. They can be configured as outputs and driven

to a logic-low state.

Alternatively, inputs can be reserved by connecting the

pin to VSS through a 1k to 10k resistor and configuring

the pin as an input.

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC32MX1XX/2XX

2.10 Typical Application Connection

Examples

Examples of typical application connections are shown

in Figure 2-4 and Figure 2-5.

FIGURE 2-4: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION

FIGURE 2-5: AUDIO PLAYBACK APPLICATION

CTMU

Current Source

ADC

Microchip

mTouch™

Library

User

Application

Microchip

Graphics

Library

Read the Touch Sensors

Process Samples

Display Data

Parallel

Master

Port

LCD Controller

Frame

Buffer

Display

Controller

PMPD<7:0>

LCD

Panel

PIC32MX120F032D

To AN6 To AN7 To AN8 To AN11

R1 R1 R1

AN0

AN1

AN11

To AN 0

To AN 1

To A N5

AN9

PMPWR

To AN 9

Audio

Codec

Display

PMP

I2S

SPI

USB

PMPD<7:0>

Stereo Headphones

Speaker

PIC32MX220F032D

Host

PMPWR

MMC SD

SDI

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

3.0 CPU

The the MIPS32® M4K® Processor Core is the heart of

the PIC32MX1XX/2XX family processor. The CPU

fetches instructions, decodes each instruction, fetches

source operands, executes each instruction and writes

the results of instruction execution to the proper

destinations.

3.1 Features

• 5-stage pipeline

• 32-bit address and data paths

• MIPS32 Enhanced Architecture (Release 2)

- Multiply-accumulate and multiply-subtract

instructions

- Targeted multiply instruction

- Zero/One detect instructions

-WAIT instruction

- Conditional move instructions (MOVN, MOVZ)

- Vectored interrupts

- Programmable exception vector base

- Atomic interrupt enable/disable

- GPR shadow registers to minimize latency

for interrupt handlers

- Bit field manipulation instructions

• MIPS16e® code compression

- 16-bit encoding of 32-bit instructions to

improve code density

- Special PC-relative instructions for efficient

loading of addresses and constants

-SAVE and RESTORE macro instructions for

setting up and tearing down stack frames

within subroutines

- Improved support for handling 8 and 16-bit

data types

• Simple Fixed Mapping Translation (FMT)

mechanism

• Simple dual bus interface

- Independent 32-bit address and data busses

- Transactions can be aborted to improve

interrupt latency

• Autonomous multiply/divide unit

- Maximum issue rate of one 32x16 multiply

per clock

- Maximum issue rate of one 32x32 multiply

every other clock

- Early-in iterative divide. Minimum 11 and

maximum 33 clock latency (dividend (rs) sign

extension-dependent)

• Power control

- Minimum frequency: 0 MHz

- Low-Power mode (triggered by WAIT

instruction)

- Extensive use of local gated clocks

• EJTAG debug and instruction trace

- Support for single stepping

- Virtual instruction and data address/value

- Breakpoints

FIGURE 3-1: MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS61113) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32). Resources

for the MIPS32® M4K® Processor Core

are available at http://www.mips.com.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Dual Bus I/F

System

Coprocessor

MDU

FMT

TAP

EJTAG

Power

Management

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

Bus Matrix

Bus Interface

CPU

PIC32MX1XX/2XX

3.2 Architecture Overview

The MIPS32® M4K® processor core contains several

logic blocks working together in parallel, providing an

efficient high-performance computing engine. The

following blocks are included with the core:

• Execution Unit

• Multiply/Divide Unit (MDU)

• System Control Coprocessor (CP0)

• Fixed Mapping Translation (FMT)

• Dual Internal Bus interfaces

• Power Management

• MIPS16e Support

• Enhanced JTAG (EJTAG) Controller

3.2.1 EXECUTION UNIT

The MIPS32® M4K® processor core execution unit

implements a load/store architecture with single-cycle

ALU operations (logical, shift, add, subtract) and an

autonomous multiply/divide unit. The core contains

thirty-two 32-bit General Purpose Registers (GPRs)

used for integer operations and address calculation.

One additional register file shadow set (containing

thirty-two registers) is added to minimize context

switching overhead during interrupt/exception process-

ing. The register file consists of two read ports and one

write port and is fully bypassed to minimize operation

latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address

• Address unit for calculating the next instruction

address

• Logic for branch determination and branch target

address calculation

• Load aligner

• Bypass multiplexers used to avoid stalls when

executing instruction streams where data

producing instructions are followed closely by

consumers of their results

• Leading Zero/One detect unit for implementing

the CLZ and CLO instructions

• Arithmetic Logic Unit (ALU) for performing bitwise

logical operations

• Shifter and store aligner

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The MIPS32® M4K® processor core includes a Multi-

ply/Divide Unit (MDU) that contains a separate pipeline

for multiply and divide operations. This pipeline oper-

ates in parallel with the Integer Unit (IU) pipeline and

does not stall when the IU pipeline stalls. This allows

MDU operations to be partially masked by system stalls

and/or other integer unit instructions.

The high-performance MDU consists of a 32x16 booth

recoded multiplier, result/accumulation registers (HI

and LO), a divide state machine, and the necessary

multiplexers and control logic. The first number shown

(‘32’ of 32x16) represents the rs operand. The second

number (‘16’ of 32x16) represents the rt operand. The

PIC32 core only checks the value of the latter (rt) oper-

and to determine how many times the operation must

pass through the multiplier. The 16x16 and 32x16

operations pass through the multiplier once. A 32x32

operation passes through the multiplier twice.

The MDU supports execution of one 16x16 or 32x16

multiply operation every clock cycle; 32x32 multiply

operations can be issued every other clock cycle.

Appropriate interlocks are implemented to stall the

issuance of back-to-back 32x32 multiply operations.

The multiply operand size is automatically determined

by logic built into the MDU.

Divide operations are implemented with a simple 1 bit

per clock iterative algorithm. An early-in detection

checks the sign extension of the dividend (rs) operand.

If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit

wide rs, 15 iterations are skipped and for a 24-bit wide

rs, 7 iterations are skipped. Any attempt to issue a sub-

sequent MDU instruction while a divide is still active

causes an IU pipeline stall until the divide operation is

completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles

until the operation can be reissued) and latency (num-

ber of cycles until a result is available) for the PIC32

core multiply and divide instructions. The approximate

latency and repeat rates are listed in terms of pipeline

clocks.

TABLE 3-1: MIPS32® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode Operand Size (mul rt) (div rs) Latency Repeat Ra te

MULT/MULTU, MADD/MADDU,

MSUB/MSUBU 16 bits 1 1

32 bits 2 2

MUL 16 bits 2 1

32 bits 3 2

DIV/DIVU 8 bits 12 11

16 bits 19 18

24 bits 26 25

32 bits 33 32

PIC32MX1XX/2XX

The MIPS architecture defines that the result of a

multiply or divide operation be placed in the HI and LO

registers. Using the Move-From-HI (MFHI) and Move-

From-LO (MFLO) instructions, these values can be

transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the

MIPS32 architecture also defines a multiply instruction,

MUL, which places the least significant results in the pri-

mary register file instead of the HI/LO register pair. By

avoiding the explicit MFLO instruction required when

using the LO register, and by supporting multiple desti-

nation registers, the throughput of multiply-intensive

operations is increased.

Two other instructions, Multiply-Add (MADD) and

Multiply-Subtract (MSUB), are used to perform the

multiply-accumulate and multiply-subtract operations.

The MADD instruction multiplies two numbers and then

adds the product to the current contents of the HI and

LO registers. Similarly, the MSUB instruction multiplies

two operands and then subtracts the product from the

HI and LO registers. The MADD and MSUB operations

are commonly used in DSP algorithms.

3.2.3 SYSTEM CONTROL

COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the

virtual-to-physical address translation, the exception

control system, the processor’s diagnostics capability,

the operating modes (Kernel, User and Debug) and

whether interrupts are enabled or disabled. Configura-

tion information, such as presence of options like

MIPS16e, is also available by accessing the CP0

registers, listed in Tab l e 3 - 2.

TABLE 3-2: COPROCESSOR 0 REGISTERS

Number Register

Name Function

0-6 Reserved Reserved in the PIC32MX1XX/2XX family core.

7 HWREna Enables access via the RDHWR instruction to selected hardware registers.

8 BadVAddr(1) Reports the address for the most recent address-related exception.

9 Count(1) Processor cycle count.

10 Reserved Reserved in the PIC32MX1XX/2XX family core.

11 Compare(1) Timer interrupt control.

12 Status(1) Processor status and control.

12 IntCtl(1) Interrupt system status and control.

12 SRSCtl(1) Shadow register set status and control.

12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set.

13 Cause(1) Cause of last general exception.

14 EPC(1) Program counter at last exception.

15 PRId Processor identification and revision.

15 EBASE Exception vector base register.

16 Config Configuration register.

16 Config1 Configuration Register 1.

16 Config2 Configuration Register 2.

16 Config3 Configuration Register 3.

17-22 Reserved Reserved in the PIC32MX1XX/2XX family core.

23 Debug(2) Debug control and exception status.

24 DEPC(2) Program counter at last debug exception.

25-29 Reserved Reserved in the PIC32MX1XX/2XX family core.

30 ErrorEPC(1) Program counter at last error.

31 DESAVE(2) Debug handler scratchpad register.

Note 1: Registers used in exception processing.

2: Registers used during debug.

PIC32MX1XX/2XX

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Table 3-3 lists

the exception types in order of priority.

TABLE 3-3: MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES

3.3 Power Management

The MIPS® M4K® processor core offers a number of

power management features, including low-power

design, active power management and power-down

modes of operation. The core is a static design that

supports slowing or Halting the clocks, which reduces

system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED

POWER MANAGEMENT

The mechanism for invoking Power-Down mode is

through execution of the WAIT instruction. For more

information on power management, see Section 25.0

“Power-Saving Features”.

3.4 EJTAG Debug Support

The MIPS® M4K® processor core provides for an

Enhanced JTAG (EJTAG) interface for use in the soft-

ware debug of application and kernel code. In addition

to standard User mode and Kernel modes of operation,

the M4K core provides a Debug mode that is entered

after a debug exception (derived from a hardware

breakpoint, single-step exception, etc.) is taken and

continues until a Debug Exception Return (DERET)

instruction is executed. During this time, the processor

executes the debug exception handler routine.

The EJTAG interface operates through the Test Access

Port (TAP), a serial communication port used for trans-

ferring test data in and out of the core. In addition to the

standard JTAG instructions, special instructions

defined in the EJTAG specification define which

registers are selected and how they are used.

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.

DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register.

NMI Assertion of NMI signal.

Interrupt Assertion of unmasked hardware or software interrupt signal.

DIB EJTAG debug hardware instruction break matched.

AdEL Fetch address alignment error.

Fetch reference to protected address.

IBE Instruction fetch bus error.

DBp EJTAG breakpoint (execution of SDBBP instruction).

Sys Execution of SYSCALL instruction.

Bp Execution of BREAK instruction.

RI Execution of a reserved instruction.

CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.

CEU Execution of a CorExtend instruction when CorExtend is not enabled.

Ov Execution of an arithmetic instruction that overflowed.

Tr Execution of a trap (when trap condition is true).

DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

AdEL Load address alignment error.

Load reference to protected address.

AdES Store address alignment error.

Store to protected address.

DBE Load or store bus error.

DDBL EJTAG data hardware breakpoint matched in load data compare.

PIC32MX1XX/2XX

4.0 MEMORY ORGANIZATION

PIC32MX1XX/2XX microcontrollers provide 4 GB of

unified virtual memory address space. All memory

regions, including program, data memory, SFRs and

Configuration registers, reside in this address space at

their respective unique addresses. The program and

data memories can be optionally partitioned into user

and kernel memories. In addition, the data memory can

be made executable, allowing PIC32MX1XX/2XX

devices to execute from data memory.

Key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel

(KSEG0/KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept

runaway code

• Simple memory mapping with Fixed Mapping

Translation (FMT) unit

• Cacheable (KSEG0) and non-cacheable (KSEG1)

address regions

4.1 PIC32MX1XX/2XX Memory Layout

PIC32MX1XX/2XX microcontrollers implement two

address schemes: virtual and physical. All hardware

resources, such as program memory, data memory

and peripherals, are located at their respective physical

addresses. Virtual addresses are exclusively used by

the CPU to fetch and execute instructions as well as

access peripherals. Physical addresses are used by

bus master peripherals, such as DMA and the Flash

controller, that access memory independently of the

CPU.

The memory maps for the PIC32MX1XX/2XX devices

are illustrated in Figure 4-1 and Figure 4-2.

Note: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source.For

detailed information, refer to Section 3.

“Memory Organization” (DS61115) in

the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

PIC32MX1XX/2XX

FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX11X/21X DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD004000

0xBD003FFF

Program Flash(2)

0xBD000000

Reserved

0xA0001000

0xA0000FFF

RAM(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D004000 0x1F800000

0x9D003FFF

Program Flash(2) Reserved

0x9D000000 0x1D004000

Reserved Program Flash(2) 0x1D003FFF

0x80001000

0x80000FFF

RAM(2) 0x1D000000

Reserved

0x80000000 0x00001000

Reserved RAM(2) 0x00000FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization

code provided by end user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

PIC32MX1XX/2XX

FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX12X/22X DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD008000

0xBD007FFF

Program Flash(2)

0xBD000000

Reserved

0xA0002000

0xA0001FFF

RAM(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D008000 0x1F800000

0x9D007FFF

Program Flash(2) Reserved

0x9D000000 0x1D008000

Reserved Program Flash(2) 0x1D007FFF

0x80002000

0x80001FFF

RAM(2) 0x1D000000

Reserved

0x80000000 0x00002000

Reserved RAM(2) 0x00001FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization

code provided by end user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

PIC32MX1XX/2XX

FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX13X/23X DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD010000

0xBD00FFFF

Program Flash(2)

0xBD000000

Reserved

0xA0004000

0xA0003FFF

RAM(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D010000 0x1F800000

0x9D00FFFF

Program Flash(2) Reserved

0x9D000000 0x1D010000

Reserved Program Flash(2) 0x1D00FFFF

0x80004000

0x80003FFF

RAM(2) 0x1D000000

Reserved

0x80000000 0x00004000

Reserved RAM(2) 0x00003FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization

code provided by end user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

PIC32MX1XX/2XX

FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX15X/25X DEVICES(1)

Virtual

Memory Map Physical

Memory Map

0xFFFFFFFF Reserved

Reserved

0xFFFFFFFF

0xBFC00C00

0xBFC00BFF Device

Configuration

Registers

0xBFC00BF0

0xBFC00BEF

Boot Flash

0xBFC00000

Reserved

0xBF900000

0xBF8FFFFF

SFRs

0xBF800000

Reserved

0xBD020000

0xBD01FFFF

Program Flash(2)

0xBD000000

Reserved

0xA0008000

0xA0007FFF

RAM(2)

0xA0000000 0x1FC00C00

Reserved Device

Configuration

Registers

0x1FC00BFF

0x9FC00C00

0x9FC00BFF Device

Configuration

Registers

0x1FC00BF0

Boot Flash

0x1FC00BEF

0x9FC00BF0

0x9FC00BEF

Boot Flash

0x1FC00000

Reserved

0x9FC00000 0x1F900000

Reserved SFRs

0x1F8FFFFF

0x9D020000 0x1F800000

0x9D01FFFF

Program Flash(2) Reserved

0x9D000000 0x1D020000

Reserved Program Flash(2) 0x1D01FFFF

0x80008000

0x80007FFF

RAM(2) 0x1D000000

Reserved

0x80000000 0x00008000

Reserved RAM(2) 0x00007FFF

0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”

(DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization

code provided by end user development tools (refer to the specific development tool

documentation for information).

KSEG1KSEG0

PIC32MX1XX/2XX

4.1.1 PERIPHERAL REGISTERS LOCATIONS

Table 4-1 through Tab le 4-2 7 contain the peripheral address maps for the PIC32MX1XX/2XX devices.

TABLE 4-1: BUS MATRIX REGISTER MAP

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 BMXCON(1) 31:16 — — — — — — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0 — — — — — — — — —BMXWSDRM — — — BMXARB<2:0> 0041

2010 BMXDKPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDKPBA<15:0> 0000

2020 BMXDUDBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUDBA<15:0> 0000

2030 BMXDUPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 BMXDUPBA<15:0> 0000

2040 BMXDRMSZ 31:16 BMXDRMSZ<31:0> xxxx

15:0 xxxx

2050 BMXPUPBA(1) 31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000

15:0 BMXPUPBA<15:0> 0000

2060 BMXPFMSZ 31:16 BMXPFMSZ<31:0> xxxx

15:0 xxxx

2070 BMXBOOTSZ 31:16 BMXBOOTSZ<31:0> 0000

15:0 3000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, S ET and INV Registers ” for more information.

PIC32MX1XX/2XX

TABLE 4-2: INTERRUPT REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Rang e

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1000 INTCON 31:16 — — — — — — — — — — — — — — — SS0 0000

15:0 — — — MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

1010 INTSTAT(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — —SRIPL<2:0>—— VEC<5:0> 0000

1020 IPTMR 31:16 IPTMR<31:0> 0000

15:0 0000

1030 IFS0 31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000

15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000

1040 IFS1 31:16 DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF 0000

15:0 CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF(2) CMP3IF CMP2IF CMP1IF 0000

1060 IEC0 31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000

15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000

1070 IEC1 31:16 DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE 0000

15:0 CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP3IE CMP2IE CMP1IE 0000

1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000

10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000

10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000

10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000

15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000

10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000

10E0 IPC5 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000

15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000

10F0 IPC6 31:16 — — — CMP1IP<2:0> CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000

15:0 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000

1100 IPC7 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — USBIP<2:0>(2) USBIS<1:0>(2) 0000

15:0 — — — CMP3IP<2:0> CMP3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 1 1.2 “CLR,

SET and INV Registers” for more information.

2: These bits are not available on PIC32MX1XX devices.

3: This register does not have associated CLR, SET, INV registers.

PIC32MX1XX/2XX

1110 IPC8 31:16 — — — PMPIP<2:0> PMPIS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000

15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000

1120 IPC9 31:16 — — — CTMUIP<2:0> CTMUIS<1:0> — — — I2C2IP<2:0> I2C2IS<1:0> 0000

15:0 — — — U2IP<2:0> U2IS<1:0> — — — SPI2IP<2:0> SPI2IS<1:0> 0000

1130 IPC10 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

TABLE 4-2: INTERRUPT REGISTER MAP(1) (CONTINUED)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SET and INV Registers” for more information.

2: These bits are not available on PIC32MX1XX devices.

3: This register does not have associated CLR, SET, INV registers.

PIC32MX1XX/2XX

TABLE 4-3: TIMER1-TIMER5 REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0600 T1CON 31:16 ————————————————0000

15:0 ON — SIDL TWDIS TWIP — — —TGATE—TCKPS<1:0>—TSYNCTCS —0000

0610 TMR1 31:16 ————————————————0000

15:0 TMR1<15:0> 0000

0620 PR1 31:16 ————————————————0000

15:0 PR1<15:0> FFFF

0800 T2CON 31:16 ————————————————0000

15:0 ON —SIDL— — — — — TGATE TCKPS<2:0> T32 —TCS—0000

0810 TMR2 31:16 ————————————————0000

15:0 TMR2<15:0> 0000

0820 PR2 31:16 ————————————————0000

15:0 PR2<15:0> FFFF

0A00 T3CON 31:16 ————————————————0000

15:0 ON —SIDL— — — — — TGATE TCKPS<2:0> ——TCS—0000

0A10 TMR3 31:16 ————————————————0000

15:0 TMR3<15:0> 0000

0A20 PR3 31:16 ————————————————0000

15:0 PR3<15:0> FFFF

0C00 T4CON 31:16 ————————————————0000

15:0 ON —SIDL— — — — — TGATE TCKPS<2:0> T32 —TCS—0000

0C10 TMR4 31:16 ————————————————0000

15:0 TMR4<15:0> 0000

0C20 PR4 31:16 ————————————————0000

15:0 PR4<15:0> FFFF

0E00 T5CON 31:16 ————————————————0000

15:0 ON —SIDL— — — — — TGATE TCKPS<2:0> ——TCS—0000

0E10 TMR5 31:16 ————————————————0000

15:0 TMR5<15:0> 0000

0E20 PR5 31:16 ————————————————0000

15:0 PR5<15:0> FFFF

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for

more information.

PIC32MX1XX/2XX

TABLE 4-4: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2000 IC1CON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2010 IC1BUF 31:16 IC1BUF<31:0> xxxx

15:0 xxxx

2200 IC2CON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2210 IC2BUF 31:16 IC2BUF<31:0> xxxx

15:0 xxxx

2400 IC3CON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2410 IC3BUF 31:16 IC3BUF<31:0> xxxx

15:0 xxxx

2600 IC4CON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2610 IC4BUF 31:16 IC4BUF<31:0> xxxx

15:0 xxxx

2800 IC5CON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

2810 IC5BUF 31:16 IC5BUF<31:0> xxxx

15:0 xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC32MX1XX/2XX

TABLE 4-5: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3000 OC1CON 31:16 ————————————————0000

15:0 ON —SIDL——————— OC32 OCFLT OCTSEL OCM<2:0> 0000

3010 OC1R 31:16 OC1R<31:0> xxxx

15:0 xxxx

3020 OC1RS 31:16 OC1RS<31:0> xxxx

15:0 xxxx

3200 OC2CON 31:16 ————————————————0000

15:0 ON —SIDL——————— OC32 OCFLT OCTSEL OCM<2:0> 0000

3210 OC2R 31:16 OC2R<31:0> xxxx

15:0 xxxx

3220 OC2RS 31:16 OC2RS<31:0> xxxx

15:0 xxxx

3400 OC3CON 31:16 ————————————————0000

15:0 ON —SIDL——————— OC32 OCFLT OCTSEL OCM<2:0> 0000

3410 OC3R 31:16 OC3R<31:0> xxxx

15:0 xxxx

3420 OC3RS 31:16

15:0 OC3RS<31:0> xxxx

xxxx

3600 OC4CON 31:16 ————————————————0000

15:0 ON —SIDL——————— OC32 OCFLT OCTSEL OCM<2:0> 0000

3610 OC4R 31:16 OC4R<31:0> xxxx

15:0 xxxx

3620 OC4RS 31:16

15:0 OC4RS<31:0> xxxx

xxxx

3800 OC5CON 31:16 ————————————————0000

15:0 ON —SIDL——————— OC32 OCFLT OCTSEL OCM<2:0> 0000

3810 OC5R 31:16 OC5R<31:0> xxxx

15:0 xxxx

3820 OC5RS 31:16 OC5RS<31:0> xxxx

15:0 xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

TABLE 4-6: I2C1 AND I2C2 REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5000 I2C1CON 31:16 ————————————————0000

15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

5010 I2C1STAT 31:16 ————————————————0000

15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000

5020 I2C1ADD 31:16 ————————————————0000

15:0 —————— Address Register 0000

5030 I2C1MSK 31:16 ————————————————0000

15:0 —————— Address Mask Register 0000

5040 I2C1BRG 31:16 ————————————————0000

15:0 ———— Baud Rate Generator Register 0000

5050 I2C1TRN 31:16 ————————————————0000

15:0 ———————— Transmit Register 0000

5060 I2C1RCV 31:16 ————————————————0000

15:0 ———————— Receive Register 0000

5100 I2C2CON 31:16 ————————————————0000

15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

5110 I2C2STAT 31:16 ————————————————0000

15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000

5120 I2C2ADD 31:16 ————————————————0000

15:0 —————— Address Register 0000

5130 I2C2MSK 31:16 ————————————————0000

15:0 —————— Address Mask Register 0000

5140 I2C2BRG 31:16 ————————————————0000

15:0 ———— Baud Rate Generator Register 0000

5150 I2C2TRN 31:16 ————————————————0000

15:0 ———————— Transmit Register 0000

5160 I2C2RCV 31:16 ————————————————0000

15:0 ———————— Receive Register 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV

Registers” for more information.

PIC32MX1XX/2XX

TABLE 4-7: UART1 AND UART2 REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6000 U1MODE(1) 31:16 ————————————————0000

15:0 ON —SIDLIRENRTSMD— UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6010 U1STA(1) 31:16 ——————— ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110

6020 U1TXREG 31:16 ————————————————0000

15:0 ——————— TX8 Transmit Register 0000

6030 U1RXREG 31:16 ————————————————0000

15:0 ——————— RX8 Receive Register 0000

6040 U1BRG(1) 31:16 ————————————————0000

15:0 Baud Rate Generator Prescaler 0000

6200 U2MODE(1) 31:16

15:0

————————————————0000

ON —SIDLIRENRTSMD— UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000

6210 U2STA(1) 31:16 ——————— ADM_EN ADDR<7:0> 0000

15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110

6220 U2TXREG 31:16 ————————————————0000

15:0 ——————— TX8 Transmit Register 0000

6230 U2RXREG 31:16 ————————————————0000

15:0 ——————— RX8 Receive Register 0000

6240 U2BRG(1) 31:16 ————————————————0000

15:0 Baud Rate Generator Prescaler 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 1 1.2 “CLR, SET and INV Registers” for more information.

PIC32MX1XX/2XX

TABLE 4-8: SPI2 AND SPI2 REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5800 SPI1CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL ————— SPIFE ENHBUF 0000

15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5810 SPI1STAT 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY —— SPITUR SRMT SPIROV SPIRBE —SPITBE—SPITBFSPIRBF0008

5820 SPI1BUF 31:16 DATA<31:0> 0000

15:0 0000

5830 SPI1BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — —BRG<8:0>0000

5840 SPI1CON2

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD-

MONO — AUDMOD<1:0> 0000

5A00 SPI2CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL ————— SPIFE ENHBUF 0000

15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000

5A10 SPI2STAT 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000

15:0 — — — FRMERR SPIBUSY —— SPITUR SRMT SPIROV SPIRBE —SPITBE—SPITBFSPIRBF0008

5A20 SPI2BUF 31:16 DATA<31:0> 0000

15:0 0000

5A30 SPI2BRG 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — —BRG<8:0>0000

5A40 SPI2CON2

31:16 — — — — — — — — — — — — — — — — 0000

15:0 SPI

SGNEXT — — FRM

ERREN

SPI

ROVEN

SPI

TUREN IGNROV IGNTUR AUDEN ———AUD

MONO — AUDMOD<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 1 1.2 “CLR, SET and INV

Registers” for more information.

PIC32MX1XX/2XX

TABLE 4-9: ADC REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

9000 AD1CON1(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL—— FORM<2:0> SSRC<2:0> CLRASAM —ASAMSAMPDONE0000

9010 AD1CON2(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 VCFG<2:0> OFFCAL — CSCNA ——BUFS—SMPI<3:0>BUFMALTS0000

9020 AD1CON3(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ADRC —— SAMC<4:0> ADCS<7:0> 0000

9040 AD1CHS(1) 31:16 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000

15:0 — — — — — — — — — — — — — — — — 0000

9050 AD1CSSL(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000

9070 ADC1BUF0 31:16 ADC Result Word 0 (ADC1BUF0<31:0>) 0000

15:0 0000

9080 ADC1BUF1 31:16 ADC Result Word 1 (ADC1BUF1<31:0>) 0000

15:0 0000

9090 ADC1BUF2 31:16 ADC Result Word 2 (ADC1BUF2<31:0>) 0000

15:0 0000

90A0 ADC1BUF3 31:16 ADC Result Word 3 (ADC1BUF3<31:0>) 0000

15:0 0000

90B0 ADC1BUF4 31:16 ADC Result Word 4 (ADC1BUF4<31:0>) 0000

15:0 0000

90C0 ADC1BUF5 31:16 ADC Result Word 5 (ADC1BUF5<31:0>) 0000

15:0 0000

90D0 ADC1BUF6 31:16 ADC Result Word 6 (ADC1BUF6<31:0>) 0000

15:0 0000

90E0 ADC1BUF7 31:16 ADC Result Word 7 (ADC1BUF7<31:0>) 0000

15:0 0000

90F0 ADC1BUF8 31:16 ADC Result Word 8 (ADC1BUF8<31:0>) 0000

15:0 0000

9100 ADC1BUF9 31:16 ADC Result Word 9 (ADC1BUF9<31:0>) 0000

15:0 0000

9110 ADC1BUFA 31:16 ADC Result Word A (ADC1BUFA<31:0>) 0000

15:0 0000

9120 ADC1BUFB 31:16 ADC Result Word B (ADC1BUFB<31:0>) 0000

15:0 0000

9130 ADC1BUFC 31:16 ADC Result Word C (ADC1BUFC<31:0>) 0000

15:0 0000

9140 ADC1BUFD 31:16 ADC Result Word D (ADC1BUFD<31:0>) 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

details.

PIC32MX1XX/2XX

9150 ADC1BUFE 31:16 ADC Result Word E (ADC1BUFE<31:0>) 0000

15:0 0000

9160 ADC1BUFF 31:16 ADC Result Word F (ADC1BUFF<31:0>) 0000

15:0 0000

TABLE 4-9: ADC REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

details.

PIC32MX1XX/2XX

TABLE 4-10: DMA GLOBAL REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3000 DMACON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —— SUSPEND DMABUSY — — — — — — — — — — — 0000

3010 DMASTAT 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RDWR DMACH<2:0>(2) 0000

3020 DMAADDR 31:16 DMAADDR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more

information.

TABLE 4-11: DMA CRC REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3030 DCRCCON 31:16 —— BYTO<1:0> WBO ——BITO————————0000

15:0 ——— PLEN<4:0> CRCEN CRCAPP CRCTYP —— CRCCH<2:0> 0000

3040 DCRCDATA 31:16 DCRCDATA<31:0> 0000

15:0 0000

3050 DCRCXOR 31:16 DCRCXOR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

3060 DCH0CON 31:16 ————————————————0000

15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

3070 DCH0ECON 31:16 ———————— CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00

3080 DCH0INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3090 DCH0SSA 31:16 CHSSA<31:0> 0000

15:0 0000

30A0 DCH0DSA 31:16 CHDSA<31:0> 0000

15:0 0000

30B0 DCH0SSIZ 31:16 ————————————————0000

15:0 CHSSIZ<15:0> 0000

30C0 DCH0DSIZ 31:16 ————————————————0000

15:0 CHDSIZ<15:0> 0000

30D0 DCH0SPTR 31:16 ————————————————0000

15:0 CHSPTR<15:0> 0000

30E0 DCH0DPTR 31:16 ————————————————0000

15:0 CHDPTR<15:0> 0000

30F0 DCH0CSIZ 31:16 ————————————————0000

15:0 CHCSIZ<15:0> 0000

3100 DCH0CPTR 31:16 ————————————————0000

15:0 CHCPTR<15:0> 0000

3110 DCH0DAT 31:16 ————————————————0000

15:0 ———————— CHPDAT<7:0> 0000

3120 DCH1CON 31:16 ————————————————0000

15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

3130 DCH1ECON 31:16 ———————— CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00

3140 DCH1INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3150 DCH1SSA 31:16 CHSSA<31:0> 0000

15:0 0000

3160 DCH1DSA 31:16 CHDSA<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

3170 DCH1SSIZ 31:16 ————————————————0000

15:0 CHSSIZ<15:0> 0000

3180 DCH1DSIZ 31:16 ————————————————0000

15:0 CHDSIZ<15:0> 0000

3190 DCH1SPTR 31:16 ————————————————0000

15:0 CHSPTR<15:0> 0000

31A0 DCH1DPTR 31:16 ————————————————0000

15:0 CHDPTR<15:0> 0000

31B0 DCH1CSIZ 31:16 ————————————————0000

15:0 CHCSIZ<15:0> 0000

31C0 DCH1CPTR 31:16 ————————————————0000

15:0 CHCPTR<15:0> 0000

31D0 DCH1DAT 31:16 ————————————————0000

15:0 ———————— CHPDAT<7:0> 0000

31E0 DCH2CON 31:16 ————————————————0000

15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

31F0 DCH2ECON 31:16 ———————— CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00

3200 DCH2INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

3210 DCH2SSA 31:16 CHSSA<31:0> 0000

15:0 0000

3220 DCH2DSA 31:16 CHDSA<31:0> 0000

15:0 0000

3230 DCH2SSIZ 31:16 ————————————————0000

15:0 CHSSIZ<15:0> 0000

3240 DCH2DSIZ 31:16 ————————————————0000

15:0 CHDSIZ<15:0> 0000

3250 DCH2SPTR 31:16 ————————————————0000

15:0 CHSPTR<15:0> 0000

3260 DCH2DPTR 31:16 ————————————————0000

15:0 CHDPTR<15:0> 0000

3270 DCH2CSIZ 31:16 ————————————————0000

15:0 CHCSIZ<15:0> 0000

TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

3280 DCH2CPTR 31:16 ————————————————0000

15:0 CHCPTR<15:0> 0000

3290 DCH2DAT 31:16 ————————————————0000

15:0 ———————— CHPDAT<7:0> 0000

32A0 DCH3CON 31:16 ————————————————0000

15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000

32B0 DCH3ECON 31:16 ———————— CHAIRQ<7:0> 00FF

15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00

32C0 DCH3INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000

15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000

32D0 DCH3SSA 31:16 CHSSA<31:0> 0000

15:0 0000

32E0 DCH3DSA 31:16 CHDSA<31:0> 0000

15:0 0000

32F0 DCH3SSIZ 31:16 ————————————————0000

15:0 CHSSIZ<15:0> 0000

3300 DCH3DSIZ 31:16 ————————————————0000

15:0 CHDSIZ<15:0> 0000

3310 DCH3SPTR 31:16 ————————————————0000

15:0 CHSPTR<15:0> 0000

3320 DCH3DPTR 31:16 ————————————————0000

15:0 CHDPTR<15:0> 0000

3330 DCH3CSIZ 31:16 ————————————————0000

15:0 CHCSIZ<15:0> 0000

3340 DCH3CPTR 31:16 ————————————————0000

15:0 CHCPTR<15:0> 0000

3350 DCH3DAT 31:16 ————————————————0000

15:0 ———————— CHPDAT<7:0> 0000

TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

TABLE 4-13: COMPARATOR REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

A000 CM1CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUTEVPOL<1:0> — CREF —— CCH<1:0> 00C3

A010 CM2CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUTEVPOL<1:0> — CREF —— CCH<1:0> 00C3

A020 CM3CON 31:16 ————————————————0000

15:0 ON COE CPOL ————COUTEVPOL<1:0> — CREF —— CCH<1:0> 00C3

A060 CMSTAT 31:16 ————————————————0000

15:0 ——SIDL—————————— C3OUT C2OUT C1OUT 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

TABLE 4-14: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

9800 CVRCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

TABLE 4-15: FLASH CO NTROLLER REGISTER MA P

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F400 NVMCON(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 WR WREN WRERR LVDERR LVDSTAT ——————— NVMOP<3:0> 0000

F410 NVMKEY 31:16 NVMKEY<31:0> 0000

15:0 0000

F420

NVMADDR

(1) 31:16 NVMADDR<31:0> 0000

15:0 0000

F430 NVMDATA 31:16 NVMDATA<31:0> 0000

15:0 0000

F440 NVMSRC

ADDR

31:16 NVMSRCADDR<31:0> 0000

15:0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more

information.

PIC32MX1XX/2XX

TABLE 4-16: SYSTEM CONTROL REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F000 OSCCON 31:16 —— PLLODIV<2:0> FRCDIV<2:0> — SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0> x1xx(2)

15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK(4) SLOCK SLPEN CF UFRCEN(4) SOSCEN OSWEN xxxx(2)

F010 OSCTUN 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — —TUN<5:0>0000

F020 REFOCON 31:16 —RODIV<14:0> 0000

15:0 ON —SIDL OERSLP— DIVSWEN ACTIVE — — — — ROSEL<3:0> 0000

F030 REFOTRIM 31:16 ROTRIM<8:0> — — — — — — — 0000

15:0 — — — — — — — — —— — — — — — — 0000

0000 WDTCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON — — — — — — — — SWDTPS<4:0> WDTWINEN WDTCLR 0000

F600 RCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR xxxx(2)

F610 RSWRST 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — — —SWRST0000

F200 CFGCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——IOLOCKPMDLOCK— — — — — — — —JTAGEN — — TDOEN 000B

F230 SYSKEY(3) 31:16 SYSKEY<31:0> 0000

15:0 0000

F240 PMD1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — —CVRMD———CTMUMD— — — — — — —AD1MD0000

F250 PMD2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — CMP3MD CMP2MD CMP1MD 0000

F260 PMD3 31:16 — — — — — — — — — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000

15:0 — — — — — — — — — — — IC5MD IC4MD IC3MD IC2MD IC1MD 0000

F270 PMD4 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — T5MD T4MD T3MD T2MD T1MD 0000

F280 PMD5 31:16 — — — — — — — USB1MD — — — — — — I2C1MD I2C1MD 0000

15:0 — — — — — — SPI2MD SPI1MD — — — — — —U2MDU1MD0000

F290 PMD6 31:16 — — — — — — — — — — — — — — — PMPMD 0000

15:0 — — — — — — — — — — — — — —REFOMDRTCCMD0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2

“CLR, SET and INV Registers” for more information.

2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.

3: This register does not have associated CLR, SET, INV registers.

4: This bit is available on PIC32MX2XX devices only.

PIC32MX1XX/2XX

TABLE 4-17: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY

Virtual Address

(BFC0_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2FF0 DEVCFG3 31:16 FVBUSONID FUSBIDIO IOL1WAY PMDL1WAY —— — — — — — — — — — — xxxx

15:0 USERID<15:0> xxxx

2FF4 DEVCFG2 31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx

15:0

UPLLEN

(1)

— — — — UPLLIDIV<2:0>(1) —FPLLMUL<2:0>— FPLLIDIV<2:0> xxxx

2FF8 DEVCFG1 31:16 — — — — — — FWDTWINSZ<1:0> FWDTEN WINDIS —WDTPS<4:0>xxxx

15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN ——FNOSC<2:0>xxxx

2FFC DEVCFG0 31:16 — — —CP— — —BWP— — — — — — — — xxxx

15:0 PWP<5:0> — — — — — ICESEL<1:0> JTAGEN DEBUG<1:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: This bit is available on PIC32MX2XX devices only.

TABLE 4-18: DEVICE AND REVISION ID SUMMARY(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

F220 DEVID 31:16 VER<3:0> DEVID<27:16> xxxx

15:0 DEVID<15:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset values are dependent on the device variant.

PIC32MX1XX/2XX

TABLE 4-19: PORTA REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6000 ANSELA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — — ANSA1 ANSA0 0003

6010 TRISA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————TRISA10

(2) TRISA9(2) TRISA8(2) TRISA7(2) —— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F

6020 PORTA 31:16 — — — — — — — — — — — 0000

15:0 —————RA10

(2) RA9(2) RA8(2) RA7(2) —— RA4 RA3 RA2 RA1 RA0 xxxx

6030 LATA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————LATA10

(2) LATA9(2) LATA8(2) LATA7(2) —— LATA4 LATA3 LATA2 LATA1 LATA0 xxxx

6040 ODCA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————— ODCA10(2) ODCA9(2) ODCA8(2) ODCA7(2) — — — — — — — 0000

6050 CNPUA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————— CNPUA10(2) CNPUA9(2) CNPUA8(2) CNPUA7(2) —— CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000

6060 CNPDA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————— CNPDA10(2) CNPDA9(2) CNPDA8(2) CNPDA7(2) —— CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000

6070 CNCONA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — — — — — — — — — — — 0000

6080 CNENA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————— CNIEA10(2) CNIEA9(2) CNIEA8(2) CNIEA7(2) —— CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000

6090 CNSTATA 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ————— CNSTATA10(2) CNSTATA9(2) CNSTATA8(2) CNSTATA7(2) —— CNSTATA4 CNSTATA3 CNSTATA2 CNSTATA1 CNSTATA0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

2: This bit is available on 44-pin devices only.

PIC32MX1XX/2XX

TABLE 4-20: PORTB REGISTER MAP

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6100 ANSELB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ANSB15 ANSB14 ANSB13 ANSB12(2) — — — — — — — — ANSB3 ANSB2 ANSB1 ANSB0 E00F

6110 TRISB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 TRISB15 TRISB14 TRISB13 TRISB12(2) TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6(2) TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF

6120 PORTB 31:16 — — — — — — — — — — — 0000

15:0 RC15 RC14 RC13 RC12(2) RB11 RB10 RB9 RB8 RB7 RC6(2) RB5 RB4 RB3 RB2 RB1 RB0 xxxx

6130 LATB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 LATB15 LATB14 LATB13 LATB12(2) LATB11 LATB10 LATB9 LATB8 LATB7 LATB6(2) LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx

6140 ODCB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——— — ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 — — — — 0000

6150 CNPUB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000

6160 CNPDB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000

6170 CNCONB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL — — — — — — — — — — — — — 0000

6180 CNENB 31:16 — — — — — — — — — — — — — — — — 0000

15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB11(2) CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6(2) CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000

6190 CNSTATB

31:16 — — — — — — — — — — — — — — — — 0000

15:0 CN

STATB15

STATB14

STATB13

STATB12(2) CN

STATB11

STATB10

STATB9

STATB8

STATB7

STATB6(2) CN

STATB5

STATB4

STATB3

STATB2

STATB1

STATB0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

2: This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF.

PIC32MX1XX/2XX

TABLE 4-21: PORTC REGISTER MAP(1,2)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

6200 ANSELC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — ANSC3 ANSC2(3) ANSC1 ANSC0 000F

6210 TRISC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————TRISC9TRISC8

(3) TRISC7(3) TRISC6(3) TRISC5(3) TRISC4(3) TRISC3 TRISC2(3) TRISC1 TRISC0 03FF

6220 PORTC 31:16 — — — — — — — — — — — 0000

15:0 —————— RC9 RC8(3) RC7(3) RC6(3) RC5(3) RC4(3) RC3 RC2(3) RC1 RC0 xxxx

6230 LATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ——————LATC9LATC8

(3) LATC7(3) LATC6(3) LATC5(3) LATC4(3) LATC3 LATC2(3) LATC1 LATC0 xxxx

6240 ODCC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————— ODCC9 ODCC8(3) ODCC7(3) ODCC6(3) ODCC5(3) ODCC4(3) — — — — 0000

6250 CNPUC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————— CNPUC9 CNPUC8(3) CNPUC7(3) CNPUC6(3) CNPUC5(3) CNPUC4(3) CNPUC3 CNPUC2(3) CNPUC1 CNPUC0 0000

6260 CNPDC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————— CNPDC9 CNPDC8(3) CNPDC7(3) CNPDC6(3) CNPDC5(3) CNPDC4(3) CNPDC3 CNPDC2(3) CNPDC1 CNPDC0 0000

6270 CNCONC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ON —SIDL— — — — — — — — — — — — — 0000

6280 CNENC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————— CNIEC9 CNIEC8(3) CNIEC7(3) CNIEC6(3) CNIEC5(3) CNIEC4(3) CNIEC3 CNIEC2(3) CNIEC1 CNIEC0 0000

6290 CNSTATC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 —————— CNSTATC9 CNSTATC8(3) CNSTATC7(3) CNSTATC6(3) CNSTATC5(3) CNSTATC4(3) CNSTATC3 CNSTATC2(3) CNSTATC1 CNSTATC0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

2: PORTC is not available on 28-pin devices.

3: This bit is available on 44-pin devices only.

PIC32MX1XX/2XX

TABLE 4-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

FA04 INT1R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —INT1R<3:0>0000

FA08 INT2R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —INT2R<3:0>0000

FA0C INT3R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —INT3R<3:0>0000

FA10 INT4R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —INT4R<3:0>0000

FA18 T2CKR

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —T2CKR<3:0>0000

FA1C T3CKR

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —T3CKR<3:0>0000

FA20 T4CKR

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —T4CKR<3:0>0000

FA24 T5CKR

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —T5CKR<3:0>0000

FA28 IC1R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —IC1R<3:0>0000

FA2C IC2R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —IC2R<3:0>0000

FA30 IC3R

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —IC3R<3:0>0000

FA34 IC4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —IC4R<3:0>0000

FA38 IC5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —IC5R<3:0>0000

FA48 OCFAR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —OCFAR<3:0>0000

FA4C OCFBR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —OCFBR<3:0>0000

FA50 U1RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —U1RXR<3:0>0000

PIC32MX1XX/2XX

FA54 U1CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — U1CTSR<3:0> 0000

FA58 U2RXR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —U2RXR<3:0>0000

FA5C U2CTSR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — U2CTSR<3:0> 0000

FA84 SDI1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —SDI1R<3:0>0000

FA88 SS1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — SS1R<3:0> 0000

FA90 SDI2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —SDI2R<3:0>0000

FA94 SS2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — SS2R<3:0> 0000

FAB8 REFCLKIR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — REFCLKIR<3:0> 0000

TABLE 4-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

PIC32MX1XX/2XX

TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

FB00 RPA0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA0<3:0> 0000

FB04 RPA1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA1<3:0> 0000

FB08 RPA2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA2<3:0> 0000

FB0C RPA3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA3<3:0> 0000

FB10 RPA4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA4<3:0> 0000

FB20 RPA8R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA8<3:0> 0000

FB24 RPA9R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPA9<3:0> 0000

FB2C RPB0R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB0<3:0> 0000

FB30 RPB1R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB1<3:0> 0000

FB34 RPB2R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB2<3:0> 0000

FB38 RPB3R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB3<3:0> 0000

FB3C RPB4R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB4<3:0> 0000

FB40 RPB5R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB5<3:0> 0000

FB44 RPB6R(2) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB6<3:0> 0000

FB48 RPB7R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB7<3:0> 0000

FB4C RPB8R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB8<3:0> 0000

Note 1: This register is only available on 44-pin devices.

2: This register is only available on PIC32MX1XX devices.

3: This register is only available on 36-pin and 44-pin devices.

PIC32MX1XX/2XX

FB50 RPB9R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB9<3:0> 0000

FB54 RPB10R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB10<3:0> 0000

FB58 RPB11R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — —RPB11<3:0>0000

FB60 RPB13R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB13<3:0> 0000

FB64 RPB14R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB14<3:0> 0000

FB68 RPB15R 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPB15<3:0> 0000

FB6C RPC0R(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC0<3:0> 0000

FB70 RPC1R(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC1<3:0> 0000

FB74 RPC2R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC2<3:0> 0000

FB78 RPC3R(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC3<3:0> 0000

FB7C RPC4R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC4<3:0> 0000

FB80 RPC5R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC5<3:0> 0000

FB84 RPC6R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC6<3:0> 0000

FB88 RPC7R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC7<3:0> 0000

FB8C RPC8R(1) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC8<3:0> 0000

FB90 RPC9R(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — RPC9<3:0> 0000

TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Note 1: This register is only available on 44-pin devices.

2: This register is only available on PIC32MX1XX devices.

3: This register is only available on 36-pin and 44-pin devices.

PIC32MX1XX/2XX

TABLE 4-24: PARALLEL MASTER PORT REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

7000 PMCON 31:16 ————————————————0000

15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP —CS1P— WRSP RDSP 0000

7010 PMMODE 31:16 ————————————————0000

15:0 BUSY IRQM<1:0> INCM<1:0> — MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000

7020 PMADDR 31:16 ————————————————0000

15:0 —

CS1

— — — ADDR<10:0> 0000

7030 PMDOUT 31:16 DATAOUT<31:0> 0000

15:0 0000

7040 PMDIN 31:16 DATAIN<31:0> 0000

15:0 0000

7050 PMAEN 31:16 ————————————————0000

15:0 —

PTEN14

— — — PTEN<10:0> 0000

7060 PMSTAT 31:16 ————————————————0000

15:0 IBF IBOV —— IB3F IB2F IB1F IB0F OBE OBUF —— OB3EOB2EOB1EOB0E008F

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

more information.

PIC32MX1XX/2XX

TABLE 4-25: RTCC REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0200 RTCCON 31:16 — — — — — — CAL<9:0> 0000

15:0 ON —SIDL — — — — — RTSECSEL RTCCLKON —— RTCWREN RTCSYNC HALFSEC RTCOE 0000

0210 RTCALRM 31:16 — — — — — — — — — — — — — — — — 0000

15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000

0220 RTCTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx

15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00

0230 RTCDATE 31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx

15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx00

0240 ALRMTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx

15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00

0250 ALRMDATE 31:16 ——— — ———— MONTH10<3:0> MONTH01<3:0> 00xx

15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

TABLE 4-26: CTMU REGISTER MAP(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

A200 CTMUCON 31:16 EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000

15:0 ON — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

information.

PIC32MX1XX/2XX

TABLE 4-27: USB REGISTER MAP(1)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5040 U1OTGIR(2) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000

5050 U1OTGIE 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000

5060 U1OTGSTAT(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — —ID —LSTATE — SESVD SESEND — VBUSVD 0000

5070 U1OTGCON 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000

5080 U1PWRC 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — —UACTPND

(4) —— USLPGRD USBBUSY — USUSPEND USBPWR 0000

5200 U1IR(2) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000

DETACHIF 0000

5210 U1IE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000

DETACHIE 0000

5220 U1EIR(2) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000

EOFEF 0000

5230 U1EIE

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000

EOFEE 0000

5240 U1STAT(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — ENDPT<3:0> DIR PPBI — — 0000

5250 U1CON

31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN 0000

TOKBUSY SOFEN 0000

5260 U1ADDR 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — LSPDEN DEVADDR<6:0> 0000

5270 U1BDTP1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — BDTPTRL<7:1> —0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See

Section 11.2 “CLR, SET and INV Registers” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

PIC32MX1XX/2XX

5280 U1FRML(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — FRML<7:0> 0000

5290 U1FRMH(3) 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — — — FRMH<2:0> 0000

52A0 U1TOK 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — PID<3:0> EP<3:0> 0000

52B0 U1SOF 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — CNT<7:0> 0000

52C0 U1BDTP2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — BDTPTRH<7:0> 0000

52D0 U1BDTP3 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — BDTPTRU<7:0> 0000

52E0 U1CNFG1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — —UTEYEUOEMON— USBSIDL — — — UASUSPND 0001

5300 U1EP0 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5310 U1EP1 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5320 U1EP2 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5330 U1EP3 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5340 U1EP4 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5350 U1EP5 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5360 U1EP6 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5370 U1EP7 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

5380 U1EP8 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

TABLE 4-27: USB REGISTER MAP(1) (CONTINUED)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Section 11.2 “CLR, SET and INV Registers” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

PIC32MX1XX/2XX

5390 U1EP9 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53A0 U1EP10 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53B0 U1EP11 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53C0 U1EP12 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53D0 U1EP13 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53E0 U1EP14 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

53F0 U1EP15 31:16 — — — — — — — — — — — — — — — — 0000

15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000

TABLE 4-27: USB REGISTER MAP(1) (CONTINUED)

Virtual Address

(BF88_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Section 11.2 “CLR, SET and INV Registers” for more information.

2: This register does not have associated SET and INV registers.

3: This register does not have associated CLR, SET and INV registers.

4: Reset value for this bit is undefined.

PIC32MX1XX/2XX

4.2 Control Registers

the RAM and Flash memory partitions for data and

code.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — — BMX

ERRIXI

BMX

ERRICD

BMX

ERRDMA

BMX

ERRDS

BMX

ERRIS

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1

—BMX

WSDRM — — — BMXARB<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 31-21 Unimplemented: Read as ‘0’

bit 20 BMXERRIXI: Enable Bus Error from IXI bit

1= Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus

0= Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus

bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit

1= Enable bus error exceptions for unmapped address accesses initiated from ICD

0= Disable bus error exceptions for unmapped address accesses initiated from ICD

bit 18 BMXERRDMA: Bus Error from DMA bit

1= Enable bus error exceptions for unmapped address accesses initiated from DMA

0= Disable bus error exceptions for unmapped address accesses initiated from DMA

bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)

1= Enable bus error exceptions for unmapped address accesses initiated from CPU data access

0= Disable bus error exceptions for unmapped address accesses initiated from CPU data access

bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)

1= Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access

0= Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access

bit 15-7 Unimplemented: Read as ‘0’

bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit

1= Data RAM accesses from CPU have one wait state for address setup

0= Data RAM accesses from CPU have zero wait states for address setup

bit 5-3 Unimplemented: Read as ‘0’

bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits

111 = Reserved (using these Configuration modes will produce undefined behavior)

•

011 = Reserved (using these Configuration modes will produce undefined behavior)

010 = Arbitration Mode 2

001 = Arbitration Mode 1 (default)

000 = Arbitration Mode 0

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDKPBA<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDKPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-11 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits

When non-zero, this value selects the relative base address for kernel program space in RAM

bit 10-0 BMXDKPBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDUDBA<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUDBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-11 BMXDUDBA<15:10>: DRM User Data Base Address bits

When non-zero, the value selects the relative base address for User mode data space in RAM, the value

must be greater than BMXDKPBA.

bit 10-0 BMXDUDBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

BMXDUPBA<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-11 BMXDUPBA<15:10>: DRM User Program Base Address bits

When non-zero, the value selects the relative base address for User mode program space in RAM,

BMXDUPBA must be greater than BMXDUDBA.

bit 10-0 BMXDUPBA<9:0>: Read-Only bits

Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

2: The value in this register must be less than or equal to BMXDRMSZ.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 RRRRR R R R

BMXDRMSZ<31:24>

23:16 RRRRR R R R

BMXDRMSZ<23:16>

15:8 RRRRR R R R

BMXDRMSZ<15:8>

7:0 RRRRR R R R

BMXDRMSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits

Static value that indicates the size of the Data RAM in bytes:

0x00001000 = device has 4 KB RAM

0x00002000 = device has 8 KB RAM

0x00004000 = device has 16 KB RAM

0x00008000 = device has 32 KB RAM

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— BMXPUPBA<19:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXPUPBA<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXPUPBA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-20 Unimplemented: Read as ‘0’

bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits

bit 10-0 BMXPUPBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

2: The value in this register must be less than or equal to BMXPFMSZ.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 RRRRR R R R

BMXPFMSZ<31:24>

23:16 RRRRR R R R

BMXPFMSZ<23:16>

15:8 RRRRR R R R

BMXPFMSZ<15:8>

7:0 RRRRR R R R

BMXPFMSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits

Static value that indicates the size of the PFM in bytes:

0x00004000 = device has 16 KB Flash

0x00008000 = device has 32 KB Flash

0x00010000 = device has 64 KB Flash

0x00020000 = device has 128 KB Flash

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 RRRRR R R R

BMXBOOTSZ<31:24>

23:16 RRRRR R R R

BMXBOOTSZ<23:16>

15:8 RRRRR R R R

BMXBOOTSZ<15:8>

7:0 RRRRR R R R

BMXBOOTSZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits

Static value that indicates the size of the Boot PFM in bytes:

0x00000C00 = device has 3 KB boot Flash

PIC32MX1XX/2XX

5.0 FLASH PROGRAM MEMORY PIC32MX1XX/2XX devices contain an internal Flash

program memory for executing user code. There are

three methods by which the user can program this

memory:

1. Run-Time Self-Programming (RTSP)

2. EJTAG Programming

3. In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either

Flash or RAM memory. Information about RTSP

techniques is available in Section 5. “Flash Progr am

Memory” (DS61121) in the “PIC32 Family Reference

Manual”.

EJTAG is performed using the EJTAG port of the

device and an EJTAG capable programmer.

ICSP is performed using a serial data connection to the

device and allows much faster programming times than

RTSP.

The EJTAG and ICSP methods are described in the

“PIC32 Flash Programming Specification” (DS61145),

which can be downloaded from the Microchip web site.

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 5. “Flash

Program Memory” (DS61121) in the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0

WR WREN WRERR(1) LVDERR(1) LVDSTAT(1) — — —

7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

———— NVMOP<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 WR: Write Control bit

This bit is writable when WREN = 1 and the unlock sequence is followed.

1 = Initiate a Flash operation. Hardware clears this bit when the operation completes

0 = Flash operation complete or inactive

bit 14 WREN: Write Enable bit

1 = Enable writes to WR bit and enables LVD circuit

0 = Disable writes to WR bit and disables LVD circuit

This is the only bit in this register reset by a device Reset.

bit 13 WRERR: Write Error bit(1)

This bit is read-only and is automatically set by hardware.

1 = Program or erase sequence did not complete successfully

0 = Program or erase sequence completed normally

bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)

This bit is read-only and is automatically set by hardware.

1 = Low-voltage detected (possible data corruption, if WRERR is set)

0 = Voltage level is acceptable for programming

bit 11 LVDSTAT : Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)

This bit is read-only and is automatically set, and cleared, by hardware.

1 = Low-voltage event active

0 = Low-voltage event NOT active

bit 10-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation bits

These bits are writable when WREN = 0.

1111 = Reserved

•

0111 = Reserved

0110 = No operation

0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected

0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected

0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected

0010 = No operation

0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected

0000 = No operation

Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<31:24>

23:16 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<23:16>

15:8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<15:8>

7:0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as ‘0’ on any read

Note 1: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits

Bulk/Chip/PFM Erase: Address is ignored.

Page Erase: Address identifies the page to erase.

Row Program: Address identifies the row to program.

Word Program: Address identifies the word to program.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Programming Data bits

Note 1: The bits in this register are only reset by a Power-on Reset (POR).

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NVMSRCADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits

(NVMCON<3:0>) are set to perform row programming.

PIC32MX1XX/2XX

6.0 RESETS The Reset module combines all Reset sources and

controls the device Master Reset signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR

: Master Clear Reset pin

• SWR: Software Reset

• WDTR: Watchdog Timer Reset

• BOR: Brown-out Reset

• CMR: Configuration Mismatch Reset

A simplified block diagram of the Reset module is

illustrated in Figure 6-1.

FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 7. “Resets”

(DS61118) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

WDT

Time-out

Glitch Filter

BOR

Configuration

SYSRST

Software Reset

Power-up

Timer

Voltage

Enabled

Reset

WDTR

SWR

CMR

MCLR

Mismatch

Regulator

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0

— — — — — — CMR VREGS

7:0 R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS

EXTR SWR — WDTO SLEEP IDLE BOR(1) POR(1)

Legend: HS = Set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-10 Unimplemented: Read as ‘0’

bit 9 CMR: Configuration Mismatch Reset Flag bit

1 = Configuration mismatch Reset has occurred

0 = Configuration mismatch Reset has not occurred

bit 8 VREGS: Voltage Regulator Standby Enable bit

1 = Regulator is enabled and is on during Sleep mode

0 = Regulator is disabled and is off during Sleep mode

bit 7 EXTR: External Reset (MCLR) Pin Flag bit

1 = Master Clear (pin) Reset has occurred

0 = Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset Flag bit

1 = Software Reset was executed

0 = Software Reset as not executed

bit 5 Unimplemented: Read as ‘0’

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT Time-out has occurred

0 = WDT Time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device was in Sleep mode

0 = Device was not in Sleep mode

bit 2 IDLE: Wake From Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit(1)

1 = Brown-out Reset has occurred

0 = Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit(1)

1 = Power-on Reset has occurred

0 = Power-on Reset has not occurred

Note 1: User software must clear this bit to view next detection.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC

— — — — — — —SWRST

(1)

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’

bit 0 SWRST: Software Reset Trigger bit(1)

1 = Enable software Reset event

0 = No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section

6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details.

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

7.0 INTERRUPT CONTROLLER

PIC32MX1XX/2XX devices generate interrupt requests

in response to interrupt events from peripheral modules.

The interrupt control module exists externally to the CPU

logic and prioritizes the interrupt events before

presenting them to the CPU.

The PIC32MX1XX/2XX interrupt module includes the

following features:

• Up to 64 interrupt sources

• Up to 44 interrupt vectors

• Single and multi-vector mode operations

• Five external interrupts with edge polarity control

• Interrupt proximity timer

• Seven user-selectable priority levels for each

vector

• Four user-selectable subpriority levels within each

priority

• Dedicated shadow set for all priority levels(1)

• Software can generate any interrupt

• User-configurable interrupt vector table location

• User-configurable interrupt vector spacing

FIGURE 7-1: INTERRUPT CONTROLLER MODULE

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 8. “Interrupt

Controller” (DS61108) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information. Note 1: On PIC32MX1XX/2XX devices, the

dedicated shadow set is associated with

all priority levels.

Interrupt Controller

Interrupt Requests

Vector Number

CPU Core

Priority Level

Shadow Set Number

PIC32MX1XX/2XX

TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION

Interrupt Source(1) IRQ

#Vector

Interrupt Bit Location Persistent

Interrupt

Flag Enable Priority Sub-priority

Highest Natural Order Priority

CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No

CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No

CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No

INT0 – External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No

T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No

IC1E – Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes

IC1 – Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes

OC1 – Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No

INT1 – External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No

T2 – Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No

IC2E – Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes

IC2 – Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> Yes

OC2 – Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No

INT2 – External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No

T3 – Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No

IC3E – Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes

IC3 – Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> Yes

OC3 – Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No

INT3 – External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No

T4 – Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No

IC4E – Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes

IC4 – Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes

OC4 – Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No

INT4 – External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No

T5 – Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No

IC5E – Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes

IC5 – Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> Yes

OC5 – Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No

AD1 – ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes

FSCM – Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No

RTCC – Real-Time Clock and

Calendar

30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No

FCE – Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No

CMP1 – Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No

CMP2 – Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No

CMP3 – Comparator Interrupt 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> No

USB – USB Interrupts 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> Yes

SPI1E – SPI1 Fault 36 31 IFS1<4> IEC1<4> IPC7<28:26> IPC7<25:24> Yes

SPI1RX – SPI1 Receive Done 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> Yes

SPI1TX – SPI1 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> Yes

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX General Purpose

Family Features” and TABLE 2: “PIC32MX2XX US B Fa mily Features” for the lists of available

peripherals.

PIC32MX1XX/2XX

U1E – UART1 Fault 39 32 IFS1<7> IEC1<7> IPC8<4:2> IPC8<1:0> Yes

U1RX – UART1 Receive Done 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> Yes

U1TX – UART1 Transfer Done 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes

I2C1B – I2C1 Bus Collision Event 42 33 IFS1<10> IEC1<10> IPC8<12:10> IPC8<9:8> Yes

I2C1S – I2C1 Slave Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8> Yes

I2C1M – I2C1 Master Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes

CNA – PORTA Input Change

Interrupt

45 34 IFS1<13> IEC1<13> IPC8<20:18> IPC8<17:16> Yes

CNB – PORTB Input Change

Interrupt

46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16> Yes

CNC – PORTC Input Change

Interrupt

47 34 IFS1<15> IEC1<15> IPC8<20:18> IPC8<17:16> Yes

PMP – Parallel Master Port 48 35 IFS1<16> IEC1<16> IPC8<28:26> IPC8<25:24> Yes

PMPE – Parallel Master Port Error 49 35 IFS1<17> IEC1<17> IPC8<28:26> IPC8<25:24> Yes

SPI2E – SPI2 Fault 50 36 IFS1<18> IEC1<18> IPC9<4:2> IPC9<1:0> Yes

SPI2RX – SPI2 Receive Done 51 36 IFS1<19> IEC1<19> IPC9<4:2> IPC9<1:0> Yes

SPI2TX – SPI2 Transfer Done 52 36 IFS1<20> IEC1<20> IPC9<4:2> IPC9<1:0> Yes

U2E – UART2 Error 53 37 IFS1<21> IEC1<21> IPC9<12:10> IPC9<9:8> Yes

U2RX – UART2 Receiver 54 37 IFS1<22> IEC1<22> IPC9<12:10> IPC9<9:8> Yes

U2TX – UART2 Transmitter 55 37 IFS1<23> IEC1<23> IPC9<12:10> IPC9<9:8> Yes

I2C2B – I2C2 Bus Collision Event 56 38 IFS1<24> IEC1<24> IPC9<20:18> IPC9<17:16> Yes

I2C2S – I2C2 Slave Event 57 38 IFS1<25> IEC1<25> IPC9<20:18> IPC9<17:16> Yes

I2C2M – I2C2 Master Event 58 38 IFS1<26> IEC1<26> IPC9<20:18> IPC9<17:16> Yes

CTMU – CTMU Event 59 39 IFS1<27> IEC1<27> IPC9<28:26> IPC9<25:24> Yes

DMA0 – DMA Channel 0 60 40 IFS1<28> IEC1<28> IPC10<4:2> IPC10<1:0> No

DMA1 – DMA Channel 1 61 41 IFS1<29> IEC1<29> IPC10<12:10> IPC10<9:8> No

DMA2 – DMA Channel 2 62 42 IFS1<30> IEC1<30> IPC10<20:18> IPC10<17:16> No

DMA3 – DMA Channel 3 63 43 IFS1<31> IEC1<31> IPC10<28:26> IPC10<25:24> No

Lowest Natural Order Priority

TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1) IRQ

#Vector

Interrupt Bit Location Persistent

Interrupt

Flag Enable Priority Sub-priority

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX General Purpose

Family Features” and TABLE 2: “PIC32MX2XX USB Family Features” for the lists of available

peripherals.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SS0

15:8 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— — — MVEC —TPC<2:0>

7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-17 Unimplemented: Read as ‘0’

bit 16 SS0: Single Vector Shadow Register Set bit

1 = Single vector is presented with a shadow register set

0 = Single vector is not presented with a shadow register set

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MVEC: Multi Vector Configuration bit

1 = Interrupt controller configured for multi vectored mode

0 = Interrupt controller configured for single vectored mode

bit 11 Unimplemented: Read as ‘0’

bit 10-8 TPC<2:0>: Temporal Proximity Control bits

111 = Interrupts of group priority 7 or lower start the TP timer

•

010 = Interrupts of group priority 2 or lower start the TP timer

001 = Interrupts of group priority 1 start the IP timer

000 = Disables proximity timer

bit 7-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit

1 = Rising edge

0 = Falling edge

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — RIPL<2:0>(1)

7:0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— VEC<5:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as ‘0’

bit 10-8 RIPL<2:0>: Requested Priority Level bits(1)

000-111 = The priority level of the latest interrupt presented to the CPU

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 VEC<5:0>: Interrupt Vector bits(1)

00000-11111 = The interrupt vector that is presented to the CPU

Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TPTMR<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TPTMR<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TPTMR<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TPTMR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 TPTMR<31:0>: Temporal Proximity Timer Reload bits

Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by

an interrupt event.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 IFS08

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS00: Interrupt Flag Status bits

1 = Interrupt request has occurred

0 = No interrupt request has occurred

Note 1: This register represents a generic definition of the IFSx register. Refer to Ta b l e 7 - 1 for the exact bit

definitions.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC08

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC00: Interrupt Enable bits

1 = Interrupt is enabled

0 = Interrupt is disabled

Note 1: This register represents a generic definition of the IECx register. Refer to Tab l e 7 - 1 for the exact bit

definitions.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP03<2:0> IS03<1:0>

23:16 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP02<2:0> IS02<1:0>

15:8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP01<2:0> IS01<1:0>

7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — IP00<2:0> IS00<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-26 IP03<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 25-24 IS03<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpiority is 0

bit 23-21 Unimplemented: Read as ‘0’

bit 20-18 IP02<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 17-16 IS02<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 15-13 Unimplemented: Read as ‘0’

bit 12-10 IP01<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

Note 1: This register represents a generic definition of the IPCx register. Refer to Tab l e 7 - 1 for the exact bit

definitions.

PIC32MX1XX/2XX

bit 9-8 IS01<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-2 IP00<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 1-0 IS00<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

Note 1: This register represents a generic definition of the IPCx register. Refer to Tab l e 7 - 1 for the exact bit

definitions.

PIC32MX1XX/2XX

8.0 OSCILLATOR

CONFIGURATION

The PIC32MX1XX/2XX oscillator system has the

following modules and features:

• A Total of four external and internal oscillator

options as clock sources

• On-Chip PLL with user-selectable input divider,

multiplier and output divider to boost operating

frequency on select internal and external

oscillator sources

• On-Chip user-selectable divisor postscaler on

select oscillator sources

• Software-controllable switching between

various clock sources

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

• Dedicated On-Chip PLL for USB peripheral

A block diagram of the oscillator system is provided in

Figure 8-1.

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 6. “Oscillator

Configuration” (DS61112) in the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC32MX1XX/2XX

FIGURE 8-1: PIC32MX1XX/2XX FAMILY CLOCK DIAGRAM

Timer1, RTCC

Clock Control Logic

Fail-Safe

Clock

Monitor

FSCM INT

FSCM Event

COSC<2:0>

NOSC<2:0>

OSWEN

FSCMEN<1:0>

PLL

Secondary Oscill ator (SOSC)

SOSCEN and FSOSCEN

SOSCO

SOSCI

Primary Oscilla t or

POSC (XT, HS, EC)

CPU and Select Peripherals

Peripherals

FRCDIV<2:0>

WDT, PWRT

8 MHz typical

FRC

31.25 kHz typical

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

FRCDIV

TUN<5:0>

div 16

Postscaler

FPLLIDIV<2:0>

PBDIV<1:0>

FRC/16

Postscaler

COSC<2:0>

FIN

div x

div y

PLLODIV<2:0>

div x

32.768 kHz

PLLMULT<2:0>

PBCLK (TPB)

UFIN = 4 MHz

PLL x24

USB Clock (48 MHz)

div 2

UPLLEN

UFRCEN

div x

UPLLIDIV<2:0>

UFIN

4 MHz ≤ FIN ≤ 5 MHz

(3)

XTAL

(1)

Enable

Notes: 1. A series resistor, RS, may be required for AT strip cut crystals.

2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.

3. Refer to Section 6. “Oscillator Conf igu ra tion” (DS61112) in the “PIC32 Family Reference Manual” for help in determining the best

oscillator components.

4. PBCLK out is available on the OSC2 pin in certain clock modes.

5. USB PLL is available on PIC32MX2XX devices only.

OSC2(4)

OSC1

(2)

To Internal

Logic

USB PLL(5)

(POSC)

div 2

To AD C

SYSCLK

REFCLKI

div N

REFCLKO

RODIV<14:0> To SPI

ROSEL<3:0>

POSC

FRC

LPRC

SOSC

PBCLK

SYSCLK

XTPLL, HSPLL,

ECPLL, FRCPLL

System USB PLL

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1

—— PLLODIV<2:0> FRCDIV<2:0>

23:16 U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y

— SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0>

15:8 U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

— COSC<2:0> — NOSC<2:0>

7:0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0

CLKLOCK ULOCK(2) SLOCK SLPEN CF UFRCEN(2) SOSCEN OSWEN

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-27 PLLODIV<2:0>: Output Divider for PLL

111 = PLL output divided by 256

110 = PLL output divided by 64

101 = PLL output divided by 32

100 = PLL output divided by 16

011 = PLL output divided by 8

010 = PLL output divided by 4

001 = PLL output divided by 2

000 = PLL output divided by 1

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

111 = FRC divided by 256

110 = FRC divided by 64

101 = FRC divided by 32

100 = FRC divided by 16

011 = FRC divided by 8

010 = FRC divided by 4

001 = FRC divided by 2 (default setting)

000 = FRC divided by 1

bit 23 Unimplemented: Read as ‘0’

bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit

1 = Indicates that the Secondary Oscillator is running and is stable

0 = Secondary Oscillator is still warming up or is turned off

bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit

1 = PBDIV<1:0> bits can be written

0 = PBDIV<1:0> bits cannot be written

bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits

11 = PBCLK is SYSCLK divided by 8 (default)

10 = PBCLK is SYSCLK divided by 4

01 = PBCLK is SYSCLK divided by 2

00 = PBCLK is SYSCLK divided by 1

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the

“PIC32 Family Reference Manual” for details.

2: This bit is available on PIC32MX2XX devices only.

PIC32MX1XX/2XX

bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits

111 = Clock is multiplied by 24

110 = Clock is multiplied by 21

101 = Clock is multiplied by 20

100 = Clock is multiplied by 19

011 = Clock is multiplied by 18

010 = Clock is multiplied by 17

001 = Clock is multiplied by 16

000 = Clock is multiplied by 15

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits

110 = Internal Fast RC (FRC) Oscillator divided by 16

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)

010 = Primary Oscillator (POSC) (XT, HS or EC)

001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)

000 = Internal Fast RC (FRC) Oscillator

bit 11 Unimplemented: Read as ‘0’

bit 10-8 NOSC<2:0>: New Oscillator Selection bits

111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits

110 = Internal Fast RC Oscillator (FRC) divided by 16

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)

010 = Primary Oscillator (XT, HS or EC)

001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)

000 = Internal Fast Internal RC Oscillator (FRC)

On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified

If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):

Clock and PLL selections are never locked and may be modified.

bit 6 ULOCK: USB PLL Lock Status bit(2)

1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied

0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or

USB PLL is disabled

bit 5 SLOCK: PLL Lock Status bit

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4 SLPEN: Sleep Mode Enable bit

1 = Device will enter Sleep mode when a WAIT instruction is executed

0 = Device will enter Idle mode when a WAIT instruction is executed

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the

“PIC32 Family Reference Manual” for details.

2: This bit is available on PIC32MX2XX devices only.

PIC32MX1XX/2XX

bit 2 UFRCEN: USB FRC Clock Enable bit(2)

1 = Enable FRC as the clock source for the USB clock source

0 = Use the Primary Oscillator or USB PLL as the USB clock source

bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit

1 = Enable Secondary Oscillator

0 = Disable Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the

“PIC32 Family Reference Manual” for details.

2: This bit is available on PIC32MX2XX devices only.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN<5:0>(2)

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2)

100000 = Center frequency -12.5%

100001 =

•

111111 =

000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz)

000001 =

•

011110 =

011111 = Center frequency +12.5%

Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the

“PIC32 Family Reference Manual” for details.

2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither

characterized, nor tested.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—RODIV<14:8>(3)

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RODIV<7:0>(3)

15:8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC

ON —SIDLOE

RSLP(2) — DIVSWEN ACTIVE

7:0

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — ROSEL<3:0>(1)

Legend: HC = Hardware Clearable HS = Hardware Settable

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as ‘0’

bit 30-16 RODIV<14:0> Reference Clock Divider bits(1)

111111111111111 = Output clock is source clock frequency divided by 65,534

111111111111110 = Output clock is source clock frequency divided by 65,532

•

000000000000010 = Output clock is source clock frequency divided by 4

000000000000001 = Output clock is source clock frequency divided by 2

000000000000000 = Output clock is same frequency as source clock (no divider)

bit 15 ON: Output Enable bit

1 = Reference Oscillator Module enabled

0 = Reference Oscillator Module disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFCLKO pin

0 = Reference clock is not driven out on REFCLKO pin

bit 11 RSLP: Reference Oscillator Module Run in Sleep bit(2)

1 = Reference Oscillator Module output continues to run in Sleep

0 = Reference Oscillator Module output is disabled in Sleep

bit 10 Unimplemented: Read as ‘0’

bit 9 DIVSWEN: Divider Switch Enable bit

1 = Divider switch is in progress

0 = Divider switch is complete

bit 8 ACTIVE: Reference Clock Request Status bit

1 = Reference clock request is active

0 = Reference clock request is not active

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.

3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’.

PIC32MX1XX/2XX

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1)

1111 = Reserved; do not use

•

1001 = Reserved; do not use

1000 = REFCLKI

0111 = System PLL output

0110 = USB PLL output

0101 =S

OSC

0100 =LPRC

0011 =FRC

0010 =P

OSC

0001 = PBCLK

0000 = SYSCLK

Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may

result.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.

3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ROTRIM<8:1>

23:16 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ROTRIM<0> ———————

15:8 U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111 = 511/512 divisor added to RODIV value

111111110 = 510/512 divisor added to RODIV value

•

100000000 = 256/512 divisor added to RODIV value

•

000000010 = 2/512 divisor added to RODIV value

000000001 = 1/512 divisor added to RODIV value

000000000 = 0/512 divisor added to RODIV value

bit 22-0 Unimplemented: Read as ‘0’

Note 1: While the ON bit (REFOCON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is

also set to ‘1’.

2: This register is not available on all devices. Refer to the specific device data sheet for availability.

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

9.0 DIRECT MEMORY ACCESS

(DMA) CONTROLLER

The PIC32 Direct Memory Access (DMA) controller is a

bus master module useful for data transfers between

different devices without CPU intervention. The source

and destination of a DMA transfer can be any of the

memory mapped modules existent in the PIC32 (such

as Peripheral Bus (PBUS) devices: SPI, UART, PMP,

etc.) or memory itself.

Following are some of the key features of the DMA

controller module:

• Four identical channels, each featuring:

- Auto-increment source and destination

address registers

- Source and destination pointers

- Memory to memory and memory to

peripheral transfers

• Automatic word-size detection:

- Transfer granularity, down to byte level

- Bytes need not be word-aligned at source

and destination

• Fixed priority channel arbitration

• Flexible DMA channel operating modes:

- Manual (software) or automatic (interrupt)

DMA requests

- One-Shot or Auto-Repeat Block Transfer

modes

- Channel-to-channel chaining

• Flexible DMA requests:

- A DMA request can be selected from any of

the peripheral interrupt sources

- Each channel can select any (appropriate)

observable interrupt as its DMA request

source

- A DMA transfer abort can be selected from

any of the peripheral interrupt sources

- Pattern (data) match transfer termination

• Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external

event

- Invalid DMA address generated

• DMA debug support features:

- Most recent address accessed by a DMA

channel

- Most recent DMA channel to transfer data

• CRC Generation module:

- CRC module can be assigned to any of the

available channels

- CRC module is highly configurable

FIGURE 9-1: DMA BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 31. “Direct

Memory Access (DMA) Controller”

(DS61117) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Address Decoder Channel 0 Control

Channel 1 Control

Channel n Control

Global Control

(DMACON)

Bus Interface

Channel Priority

Arbitration

SEL

System IRQINT Controller

Device Bus + Bus Arbitration

Peripheral Bus

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0

ON(1) —— SUSPEND DMABUSY — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: DMA On bit(1)

1 = DMA module is enabled

0 = DMA module is disabled

bit 14-13 Unimplemented: Read as ‘0’

bit 12 SUSPEND: DMA Suspend bit

1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus

0 = DMA operates normally

bit 11 DMABUSY: DMA Module Busy bit(4)

1 = DMA module is active

0 = DMA module is disabled and not actively transferring data

bit 10-0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — RDWR DMACH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3 RDWR: Read/Write Status bit

1 = Last DMA bus access was a read

0 = Last DMA bus access was a write

bit 2-0 DMACH<2:0>: DMA Channel bits

These bits contain the value of the most recent active DMA channel.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<31:24>

23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<23:16>

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Module Address bits

These bits contain the address of the most recent DMA access.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0

——BYTO<1:0>WBO

(1) ——BITO

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — PLEN<4:0>

7:0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

CRCEN CRCAPP(1) CRCTYP —— CRCCH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits

11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order

per half-word)

10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per

half-word)

01 = Endian byte swap on word boundaries (i.e., reverse source byte order)

00 = No swapping (i.e., source byte order)

bit 27 WBO: CRC Write Byte Order Selection bit(1)

1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>

0 = Source data is written to the destination unaltered

bit 26-25 Unimplemented: Read as ‘0’

bit 24 BITO: CRC Bit Order Selection bit(4)

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)

0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)

0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)

bit 23-13 Unimplemented: Read as ‘0’

bit 12-8 PLEN<4:0>: Polynomial Length bits(1)

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

These bits are unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Denotes the length of the polynomial – 1.

bit 7 CRCEN: CRC Enable bit

1 = CRC module is enabled and channel transfers are routed through the CRC module

0 = CRC module is disabled and channel transfers proceed normally

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

PIC32MX1XX/2XX

bit 6 CRCAPP: CRC Append Mode bit(1)

1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer

completes the DMA writes the calculated CRC value to the location given by CHxDSA

0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the

destination

bit 5 CRCTYP: CRC Type Selection bit

1 = The CRC module will calculate an IP header checksum

0 = The CRC module will calculate a LFSR CRC

bit 4-3 Unimplemented: Read as ‘0’

bit 2-0 CRCCH<2:0>: CRC Channel Select bits

111 = CRC is assigned to Channel 7

110 = CRC is assigned to Channel 6

101 = CRC is assigned to Channel 5

100 = CRC is assigned to Channel 4

011 = CRC is assigned to Channel 3

010 = CRC is assigned to Channel 2

001 = CRC is assigned to Channel 1

000 = CRC is assigned to Channel 0

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Writing to this register will seed the CRC generator. Reading from this register will return the current value of

the CRC. Bits greater than PLEN will return ‘0’ on any read.

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written

to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Bits greater than PLEN will return ‘0’ on any read.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DCRCXOR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

This register is unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = Enable the XOR input to the Shift register

0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in

the register

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

CHBUSY — — — — — — CHCHNS(1)

7:0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0

CHEN(2) CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 CHBUSY: Channel Busy bit

1 = Channel is active or has been enabled

0 = Channel is inactive or has been disabled

bit 14-9 Unimplemented: Read as ‘0’

bit 8 CHCHNS: Chain Channel Selection bit(1)

1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)

0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)

bit 7 CHEN: Channel Enable bit(2)

1 = Channel is enabled

0 = Channel is disabled

bit 6 CHAED: Channel Allow Events If Disabled bit

1 = Channel start/abort events will be registered, even if the channel is disabled

0 = Channel start/abort events will be ignored if the channel is disabled

bit CHCHN: Channel Chain Enable bit

1 = Allow channel to be chained

0 = Do not allow channel to be chained

bit 4 CHAEN: Channel Automatic Enable bit

1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete

0 = Channel is disabled on block transfer complete

bit 3 Unimplemented: Read as ‘0’

bit 2 CHEDET: Channel Event Detected bit

1 = An event has been detected

0 = No events have been detected

bit 1-0 CHPRI<1:0>: Channel Priority bits

11 = Channel has priority 3 (highest)

10 = Channel has priority 2

01 = Channel has priority 1

00 = Channel has priority 0

Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).

2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if

available on the device variant) to see when the channel is suspended, as it may take some clock cycles

to complete a current transaction before the channel is suspended.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHAIRQ<7:0>(1)

15:8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CHSIRQ<7:0>(1)

7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CFORCE CABORT PATEN SIRQEN AIRQEN — — —

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)

11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag

•

00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag

00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag

bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)

11111111 = Interrupt 255 will initiate a DMA transfer

•

00000001 = Interrupt 1 will initiate a DMA transfer

00000000 = Interrupt 0 will initiate a DMA transfer

bit 7 CFORCE: DMA Forced Transfer bit

1 = A DMA transfer is forced to begin when this bit is written to a ‘1’

0 = This bit always reads ‘0’

bit 6 CABORT: DMA Abort Transfer bit

1 = A DMA transfer is aborted when this bit is written to a ‘1’

0 = This bit always reads ‘0’

bit 5 PATEN: Channel Pattern Match Abort Enable bit

1 = Abort transfer and clear CHEN on pattern match

0 = Pattern match is disabled

bit 4 SIRQEN: Channel Start IRQ Enable bit

1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs

0 = Interrupt number CHSIRQ is ignored and does not start a transfer

bit 3 AIRQEN: Channel Abort IRQ Enable bit

1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs

0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer

bit 2-0 Unimplemented: Read as ‘0’

Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 16 CHERIE: Channel Address Error Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 15-8 Unimplemented: Read as ‘0’

bit 7 CHSDIF: Channel Source Done Interrupt Flag bit

1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)

0 = No interrupt is pending

bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit

1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)

0 = No interrupt is pending

bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit

1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)

0 = No interrupt is pending

PIC32MX1XX/2XX

bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit

1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)

0 = No interrupt is pending

bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit

1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a

pattern match event occurs

0 = No interrupt is pending

bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit

1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)

0 = No interrupt is pending

bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit

1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted

0 = No interrupt is pending

bit 0 CHERIF: Channel Address Error Interrupt Flag bit

1 = A channel address error has been detected

Either the source or the destination address is invalid.

0 = No interrupt is pending

PIC32MX1XX/2XX

Bit Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.

Note: This must be the physical address of the source.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<23:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.

Note: This must be the physical address of the destination.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHSSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSSIZ<15:0>: Channel Source Size bits

1111111111111111 = 65,535 byte source size

•

0000000000000010 = 2 byte source size

0000000000000001 = 1 byte source size

0000000000000000 = 65,536 byte source size

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHDSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits

1111111111111111 = 65,535 byte destination size

•

0000000000000010 = 2 byte destination size

0000000000000001 = 1 byte destination size

0000000000000000 = 65,536 byte destination size

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits

1111111111111111 = Points to byte 65,535 of the source

•

0000000000000001 = Points to byte 1 of the source

0000000000000000 = Points to byte 0 of the source

Note 1: When in Pattern Detect mode, this register is reset on a pattern detect.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits

1111111111111111 = Points to byte 65,535 of the destination

•

0000000000000001 = Points to byte 1 of the destination

0000000000000000 = Points to byte 0 of the destination

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHCSIZ<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits

1111111111111111 = 65,535 bytes transferred on an event

•

0000000000000010 = 2 bytes transferred on an event

0000000000000001= 1 byte transferred on an event

0000000000000000 = 65,536 bytes transferred on an event

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<15:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits

1111111111111111 = 65,535 bytes have been transferred since the last event

•

0000000000000001 = 1 byte has been transferred since the last event

0000000000000000 = 0 bytes have been transferred since the last event

Note 1: When in Pattern Detect mode, this register is reset on a pattern detect.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CHPDAT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CHPDAT<7:0>: Channel Data Register bits

Pattern Terminate mode:

Data to be matched must be stored in this register to allow terminate on match.

All other modes:

Unused.

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

10.0 USB ON-THE-GO (OTG)

The Universal Serial Bus (USB) module contains

analog and digital components to provide a USB 2.0

full-speed and low-speed embedded host, full-speed

device or OTG implementation with a minimum of

external components. This module in Host mode is

intended for use as an embedded host and therefore

does not implement a UHCI or OHCI controller.

The USB module consists of the clock generator, the

USB voltage comparators, the transceiver, the Serial

Interface Engine (SIE), a dedicated USB DMA control-

ler, pull-up and pull-down resistors, and the register

interface. A block diagram of the PIC32 USB OTG

module is presented in Figure 10-1.

The clock generator provides the 48 MHz clock

required for USB full-speed and low-speed communi-

cation. The voltage comparators monitor the voltage on

the VBUS pin to determine the state of the bus. The

transceiver provides the analog translation between

the USB bus and the digital logic. The SIE is a state

machine that transfers data to and from the endpoint

buffers and generates the hardware protocol for data

transfers. The USB DMA controller transfers data

between the data buffers in RAM and the SIE. The inte-

grated pull-up and pull-down resistors eliminate the

need for external signaling components. The register

interface allows the CPU to configure and

communicate with the module.

The PIC32 USB module includes the following

features:

• USB Full-speed support for host and device

• Low-speed host support

• USB OTG support

• Integrated signaling resistors

• Integrated analog comparators for VBUS

monitoring

• Integrated USB transceiver

• Transaction handshaking performed by hardware

• Endpoint buffering anywhere in system RAM

• Integrated DMA to access system RAM and Flash

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 27. “USB On-

The-Go (OTG)” (DS61126) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: The implementation and use of the USB

specifications, as well as other third party

specifications or technologies, may

require licensing; including, but not limited

to, USB Implementers Forum, Inc. (also

referred to as USB-IF). The user is fully

responsible for investigating and

satisfying any applicable licensing

obligations.

PIC32MX1XX/2XX

FIGURE 10-1: PIC32MX1XX/2XX FAMILY USB INTERFACE DIAGRAM

OSC1

OSC2

Primary Oscillator

8MHzTypical

FRC

Oscillator

TUN<5:0>(3)

PLL

48 MHz USB Clock(6)

Div x

UPLLEN(5) UFRCEN(2)

(POSC)

UPLLIDIV(5)

UFIN(4)

Div 2

VUSB

D+(1)

D-(1)

ID(7)

Bus

Transceiver

SIE

VBUSON(7)

Comparators

USB

SRP Charge

SRP Discharge

Registers

and

Control

Interface

Transceiver Power 3.3V

USB Module

Voltage

System

RAM

Full Speed Pull-up

Host Pull-down

Low Speed Pull-up

Host Pull-down

ID Pull-up

DMA

Note 1: Pins can be used as digital inputs when USB is not enabled.

2: This bit field is contained in the OSCCON register.

3: This bit field is contained in the OSCTRM register.

4: USB PLL UFIN requirements: 4 MHz.

5: This bit field is contained in the DEVCFG2 register.

6: A 48 MHz clock is required for proper USB operation.

7: Pins can be used as GPIO when the USB module is disabled.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIF: ID State Change Indicator bit

1 = Change in ID state detected

0 = No change in ID state detected

bit 6 T1MSECIF: 1 Millisecond Timer bit

1 = 1 millisecond timer has expired

0 = 1 millisecond timer has not expired

bit 5 LSTATEIF: Line State Stable Indicator bit

1 = USB line state has been stable for 1 ms, but different from last time

0 = USB line state has not been stable for 1 ms

bit 4 ACTVIF: Bus Activity Indicator bit

1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up

0 = Activity has not been detected

bit 3 SESVDIF: Session Valid Change Indicator bit

1 =V

BUS voltage has dropped below the session end level

0 =V

BUS voltage has not dropped below the session end level

bit 2 SESENDIF: B-Device VBUS Change Indicator bit

1 = A change on the session end input was detected

0 = No change on the session end input was detected

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit

1 = Change on the session valid input detected

0 = No change on the session valid input detected

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIE: ID Interrupt Enable bit

1 = ID interrupt enabled

0 = ID interrupt disabled

bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit

1 = 1 millisecond timer interrupt enabled

0 = 1 millisecond timer interrupt disabled

bit 5 LSTATEIE: Line State Interrupt Enable bit

1 = Line state interrupt enabled

0 = Line state interrupt disabled

bit 4 ACTVIE: Bus Activity Interrupt Enable bit

1 = ACTIVITY interrupt enabled

0 = ACTIVITY interrupt disabled

bit 3 SESVDIE: Session Valid Interrupt Enable bit

1 = Session valid interrupt enabled

0 = Session valid interrupt disabled

bit 2 SESENDIE: B-Session End Interrupt Enable bit

1 = B-session end interrupt enabled

0 = B-session end interrupt disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit

1 =A-VBUS valid interrupt enabled

0 =A-V

BUS valid interrupt disabled

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0

ID —LSTATE— SESVD SESEND — VBUSVD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 ID: ID Pin State Indicator bit

1 = No cable is attached or a type B cable has been plugged into the USB receptacle

0 = A “type A” OTG cable has been plugged into the USB receptacle

bit 6 Unimplemented: Read as ‘0’

bit 5 LSTATE: Line State Stable Indicator bit

1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms

0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms

bit 4 Unimplemented: Read as ‘0’

bit 3 SESVD: Session Valid Indicator bit

1 =V

BUS voltage is above Session Valid on the A or B device

0 =VBUS voltage is below Session Valid on the A or B device

bit 2 SESEND: B-Session End Indicator bit

1 =VBUS voltage is below Session Valid on the B device

0 =VBUS voltage is above Session Valid on the B device

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVD: A-VBUS Valid Indicator bit

1 =V

BUS voltage is above Session Valid on the A device

0 =V

BUS voltage is below Session Valid on the A device

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 DPPULUP: D+ Pull-Up Enable bit

1 = D+ data line pull-up resistor is enabled

0 = D+ data line pull-up resistor is disabled

bit 6 DMPULUP: D- Pull-Up Enable bit

1 = D- data line pull-up resistor is enabled

0 = D- data line pull-up resistor is disabled

bit 5 DPPULDWN: D+ Pull-Down Enable bit

1 = D+ data line pull-down resistor is enabled

0 = D+ data line pull-down resistor is disabled

bit 4 DMPULDWN: D- Pull-Down Enable bit

1 = D- data line pull-down resistor is enabled

0 = D- data line pull-down resistor is disabled

bit 3 VBUSON: VBUS Power-on bit

1 =V

BUS line is powered

0 =V

BUS line is not powered

bit 2 OTGEN: OTG Functionality Enable bit

1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control

0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control

bit 1 VBUSCHG: VBUS Charge Enable bit

1 =VBUS line is charged through a pull-up resistor

0 =V

BUS line is not charged through a resistor

bit 0 VBUSDIS: VBUS Discharge Enable bit

1 =VBUS line is discharged through a pull-down resistor

0 =V

BUS line is not discharged through a resistor

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

UACTPND —— USLPGRD USBBUSY — USUSPEND USBPWR

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UACTPND: USB Activity Pending bit

1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet

0 = An interrupt is not pending

bit 6-5 Unimplemented: Read as ‘0’

bit 4 USLPGRD: USB Sleep Entry Guard bit

1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending

0 = USB module does not block Sleep entry

bit 3 USBBUSY: USB Module Busy bit(1)

1 = USB module is active or disabled, but not ready to be enabled

0 = USB module is not active and is ready to be enabled

Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all

USB module registers produce undefined results.

bit 2 Unimplemented: Read as ‘0’

bit 1 USUSPEND: USB Suspend Mode bit

1 = USB module is placed in Suspend mode

(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)

0 = USB module operates normally

bit 0 USBPWR: USB Operation Enable bit

1 = USB module is turned on

0 = USB module is disabled

(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power

consumption.)

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS

STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) URSTIF(5)

DETACHIF(6)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIF: STALL Handshake Interrupt bit

1 = In Host mode a STALL handshake was received during the handshake phase of the transaction

In Device mode a STALL handshake was transmitted during the handshake phase of the transaction

0 = STALL handshake has not been sent

bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)

1 = Peripheral attachment was detected by the USB module

0 = Peripheral attachment was not detected

bit 5 RESUMEIF: Resume Interrupt bit(2)

1 = K-State is observed on the D+ or D- pin for 2.5 µs

0 = K-State is not observed

bit 4 IDLEIF: Idle Detect Interrupt bit

1 = Idle condition detected (constant Idle state of 3 ms or more)

0 = No Idle condition detected

bit 3 TRNIF: Token Processing Complete Interrupt bit(3)

1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information

0 = Processing of current token not complete

bit 2 SOFIF: SOF Token Interrupt bit

1 = SOF token received by the peripheral or the SOF threshold reached by the host

0 = SOF token was not received nor threshold reached

bit 1 UERRIF: USB Error Condition Interrupt bit(4)

1 = Unmasked error condition has occurred

0 = Unmasked error condition has not occurred

Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for

2.5 µs, and the current bus state is not SE0.

2: When not in Suspend mode, this interrupt should be disabled.

3: Clearing this bit will cause the STAT FIFO to advance.

4: Only error conditions enabled through the U1EIE register will set this bit.

5: Device mode.

6: Host mode.

PIC32MX1XX/2XX

bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5)

1 = Valid USB Reset has occurred

0 = No USB Reset has occurred

DETACHIF: USB Detach Interrupt bit (Host mode)(6)

1 = Peripheral detachment was detected by the USB module

0 = Peripheral detachment was not detected

Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for

2.5 µs, and the current bus state is not SE0.

2: When not in Suspend mode, this interrupt should be disabled.

3: Clearing this bit will cause the STAT FIFO to advance.

4: Only error conditions enabled through the U1EIE register will set this bit.

5: Device mode.

6: Host mode.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) URSTIE(2)

DETACHIE(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIE: STALL Handshake Interrupt Enable bit

1 = STALL interrupt enabled

0 = STALL interrupt disabled

bit 6 ATTACHIE: ATTACH Interrupt Enable bit

1 = ATTACH interrupt enabled

0 = ATTACH interrupt disabled

bit 5 RESUMEIE: RESUME Interrupt Enable bit

1 = RESUME interrupt enabled

0 = RESUME interrupt disabled

bit 4 IDLEIE: Idle Detect Interrupt Enable bit

1 = Idle interrupt enabled

0 = Idle interrupt disabled

bit 3 TRNIE: Token Processing Complete Interrupt Enable bit

1 = TRNIF interrupt enabled

0 = TRNIF interrupt disabled

bit 2 SOFIE: SOF Token Interrupt Enable bit

1 = SOFIF interrupt enabled

0 = SOFIF interrupt disabled

bit 1 UERRIE: USB Error Interrupt Enable bit(1)

1 = USB Error interrupt enabled

0 = USB Error interrupt disabled

bit 0 URSTIE: USB Reset Interrupt Enable bit(2)

1 = URSTIF interrupt enabled

0 = URSTIF interrupt disabled

DETACHIE: USB Detach Interrupt Enable bit(3)

1 = DATTCHIF interrupt enabled

0 = DATTCHIF interrupt disabled

Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

—————— ——

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

—————— ——

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

—————— ——

7:0

R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS

BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF

CRC5EF(3,4)

PIDEF

EOFEF(5)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEF: Bit Stuff Error Flag bit

1 = Packet rejected due to bit stuff error

0 = Packet accepted

bit 6 BMXEF: Bus Matrix Error Flag bit

1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid.

0 = No address error

bit 5 DMAEF: DMA Error Flag bit(1)

1 = USB DMA error condition detected

0 =No DMA error

bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2)

1 = Bus turnaround time-out has occurred

0 = No bus turnaround time-out

bit 3 DFN8EF: Data Field Size Error Flag bit

1 = Data field received is not an integral number of bytes

0 = Data field received is an integral number of bytes

bit 2 CRC16EF: CRC16 Failure Flag bit

1 = Data packet rejected due to CRC16 error

0 = Data packet accepted

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

PIC32MX1XX/2XX

bit 1 CRC5EF: CRC5 Host Error Flag bit(3,4)

1 = Token packet rejected due to CRC5 error

0 = Token packet accepted

EOFEF: EOF Error Flag bit(5)

1 = EOF error condition detected

0 = No EOF error condition

bit 0 PIDEF: PID Check Failure Flag bit

1 = PID check failed

0 = PID check passed

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(2)

PIDEE

EOFEE(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = BTSEF interrupt enabled

0 = BTSEF interrupt disabled

bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit

1 = BMXEF interrupt enabled

0 = BMXEF interrupt disabled

bit 5 DMAEE: DMA Error Interrupt Enable bit

1 = DMAEF interrupt enabled

0 = DMAEF interrupt disabled

bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1 = BTOEF interrupt enabled

0 = BTOEF interrupt disabled

bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit

1 = DFN8EF interrupt enabled

0 = DFN8EF interrupt disabled

bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit

1 = CRC16EF interrupt enabled

0 = CRC16EF interrupt disabled

bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(2)

1 = CRC5EF interrupt enabled

0 = CRC5EF interrupt disabled

EOFEE: EOF Error Interrupt Enable bit(3)

1 = EOF interrupt enabled

0 = EOF interrupt disabled

bit 0 PIDEE: PID Check Failure Interrupt Enable bit

1 = PIDEF interrupt enabled

0 = PIDEF interrupt disabled

Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0U-0U-0U-0U-0U-0U-0U-0

————————

23:16 U-0U-0U-0U-0U-0U-0U-0U-0

————————

15:8 U-0U-0U-0U-0U-0U-0U-0U-0

————————

7:0 R-x R-x R-x R-x R-x R-x U-0 U-0

ENDPT<3:0> DIR PPBI — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits

(Represents the number of the BDT, updated by the last USB transfer.)

1111 = Endpoint 15

1110 = Endpoint 14

•

0001 =Endpoint 1

0000 =Endpoint 0

bit 3 DIR: Last BD Direction Indicator bit

1 = Last transaction was a transmit transfer (TX)

0 = Last transaction was a receive transfer (RX)

bit 2 PPBI: Ping-Pong BD Pointer Indicator bit

1 = The last transaction was to the ODD BD bank

0 = The last transaction was to the EVEN BD bank

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is

only valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0

R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

JSTATE SE0 PKTDIS(4)

USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4)

TOKBUSY(1,5) SOFEN(5)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 JSTATE: Live Differential Receiver JSTATE flag bit

1 = JSTATE detected on the USB

0 = No JSTATE detected

bit 6 SE0: Live Single-Ended Zero flag bit

1 = Single Ended Zero detected on the USB

0 = No Single Ended Zero detected

bit 5 PKTDIS: Packet Transfer Disable bit(4)

1 = Token and packet processing disabled (set upon SETUP token received)

0 = Token and packet processing enabled

TOKBUSY: Token Busy Indicator bit(1,5)

1 = Token being executed by the USB module

0 = No token being executed

bit 4 USBRST: Module Reset bit(5)

1 = USB reset generated

0 = USB reset terminated

bit 3 HOSTEN: Host Mode Enable bit(2)

1 = USB host capability enabled

0 = USB host capability disabled

bit 2 RESUME: RESUME Signaling Enable bit(3)

1 = RESUME signaling activated

0 = RESUME signaling disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then

clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the

RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

PIC32MX1XX/2XX

bit 1 PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Even/Odd buffer pointers to the EVEN BD banks

0 = Even/Odd buffer pointers not being Reset

bit 0 USBEN: USB Module Enable bit(4)

1 = USB module and supporting circuitry enabled

0 = USB module and supporting circuitry disabled

SOFEN: SOF Enable bit(5)

1 = SOF token sent every 1 ms

0 = SOF token disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then

clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the

RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPDEN DEVADDR<6:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPDEN: Low Speed Enable Indicator bit

1 = Next token command to be executed at Low Speed

0 = Next token command to be executed at Full Speed

bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FRML<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — FRMH<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PID<3:0>(1) EP<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 PID<3:0>: Token Type Indicator bits(1)

0001 = OUT (TX) token type transaction

1001 = IN (RX) token type transaction

1101 = SETUP (TX) token type transaction

Note: All other values are reserved and must not be used.

bit 3-0 EP<3:0>: Token Command Endpoint Address bits

The four bit value must specify a valid endpoint.

Note 1: All other values are reserved and must not be used.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CNT<7:0>: SOF Threshold Value bits

Typical values of the threshold are:

01001010 = 64-byte packet

00101010 = 32-byte packet

00011010 = 16-byte packet

00010010 = 8-byte packet

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

BDTPTRL<15:9> —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-1 BDTPTRL<15:9>: BDT Base Address bits

This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting

location of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

bit 0 Unimplemented: Read as ‘0’

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRH<23:16>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRH<23:16>: BDT Base Address bits

This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting

location of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRU<31:24>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRU<31:24>: BDT Base Address bits

This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location

of the BDT in system memory.

The 32-bit BDT base address is 512-byte aligned.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

——————— —

7:0

R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0

UTEYE UOEMON —USBSIDL ——— UASUSPND

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UTEYE: USB Eye-Pattern Test Enable bit

1 = Eye-Pattern Test enabled

0 = Eye-Pattern Test disabled

bit 6 UOEMON: USB OE Monitor Enable bit

1 = OE signal active; it indicates intervals during which the D+/D- lines are driving

0 = OE signal inactive

bit 5 Unimplemented: Read as ‘0’

bit 4 USBSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 3-1 Unimplemented: Read as ‘0’

bit 0 UASUSPND: Automatic Suspend Enable bit

1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit

(U1PWRC<1>) in Register 10-5.

0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the

USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

7:0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)

1 = Direct connection to a low-speed device enabled

0 = Direct connection to a low-speed device disabled; hub required with PRE_PID

bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)

1 = Retry NAK’d transactions disabled

0 = Retry NAK’d transactions enabled; retry done in hardware

bit 5 Unimplemented: Read as ‘0’

bit 4 EPCONDIS: Bidirectional Endpoint Control bit

If EPTXEN = 1 and EPRXEN = 1:

1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed

0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed

Otherwise, this bit is ignored.

bit 3 EPRXEN: Endpoint Receive Enable bit

1 = Endpoint n receive enabled

0 = Endpoint n receive disabled

bit 2 EPTXEN: Endpoint Transmit Enable bit

1 = Endpoint n transmit enabled

0 = Endpoint n transmit disabled

bit 1 EPSTALL: Endpoint Stall Status bit

1 = Endpoint n was stalled

0 = Endpoint n was not stalled

bit 0 EPHSHK: Endpoint Handshake Enable bit

1 = Endpoint Handshake enabled

0 = Endpoint Handshake disabled (typically used for isochronous endpoints)

PIC32MX1XX/2XX

11.0 I/O PORTS General purpose I/O pins are the simplest of peripher-

als. They allow the PIC® MCU to monitor and control

other devices. To add flexibility and functionality, some

pins are multiplexed with alternate function(s). These

functions depend on which peripheral features are on

the device. In general, when a peripheral is functioning,

that pin may not be used as a general purpose I/O pin.

Following are some of the key features of this module:

• Individual output pin open-drain enable/disable

• Individual input pin weak pull-up and pull-down

• Monitor selective inputs and generate interrupt

when change in pin state is detected

• Operation during CPU Sleep and Idle modes

• Fast bit manipulation using CLR, SET and INV

registers

Figure 11-1 illustrates a block diagram of a typical

multiplexed I/O port.

FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports”

(DS61120) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Peripheral Output Data

Peripheral Module

Peripheral Output Enable

PIO Module

Peripheral Module Enable

WR LAT

I/O Pin

WR PORT

Data Bus

RD LAT

RD PORT

RD TRIS

WR TRIS

RD ODC

SYSCLK

EN Q

SYSCLK

WR ODC

ODC

TRIS

LAT

Sleep

Output Multiplexers

I/O Cell

Synchronization

Peripheral Input

Legend: R = Peripheral input buffer types may vary. Refer to Ta bl e 1 -1 for peripheral details.

Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure

for any specific port/peripheral combination may be different than it is shown here.

Peripheral Input Buffer

PIC32MX1XX/2XX

11.1 Parallel I/O (PIO) Ports

All port pins have ten registers directly associated with

their operation as digital I/O. The data direction register

(TRISx) determines whether the pin is an input or an

output. If the data direction bit is a ‘1’, then the pin is an

input. All port pins are defined as inputs after a Reset.

Reads from the latch (LATx) read the latch. Writes to

the latch write the latch. Reads from the port (PORTx)

read the port pins, while writes to the port pins write the

latch.

11.1.1 OPEN-DRAIN CONFIGURATION

In addition to the PORTx, LATx, and TRISx registers for

data control, some port pins can also be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The open-drain feature allows the generation of out-

puts higher than VDD (e.g., 5V) on any desired 5V-tol-

erant pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

See the “Pin Diagrams” section for the available pins

and their functionality.

11.1.2 CONFIGURING ANALOG AND

DIGITAL PORT PINS

The ANSELx register controls the operation of the

analog port pins. The port pins that are to function as

analog inputs must have their corresponding ANSEL

and TRIS bits set. In order to use port pins for I/O

functionality with digital modules, such as Timers,

UARTs, etc., the corresponding ANSELx bit must be

cleared.

The ANSELx register has a default value of 0xFFFF;

therefore, all pins that share analog functions are

analog (not digital) by default.

If the TRIS bit is cleared (output) while the ANSELx bit

is set, the digital output level (VOH or VOL) is converted

by an analog peripheral, such as the ADC module or

Comparator module.

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level).

Pins configured as digital inputs do not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

11.1.3 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be an NOP.

11.1.4 INPUT CHANGE NOTIFICATION

The input change notification function of the I/O ports

allows the PIC32MX1XX/2XX devices to generate

interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature can

detect input change-of-states even in Sleep mode,

when the clocks are disabled. Every I/O port pin can be

selected (enabled) for generating an interrupt request

on a change-of-state.

Five control registers are associated with the CN func-

tionality of each I/O port. The CNENx registers contain

the CN interrupt enable control bits for each of the input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

The CNSTATx register indicates whether a change

occurred on the corresponding pin since the last read

of the PORTx bit.

Each I/O pin also has a weak pull-up and a weak

pull-down connected to it. The pull-ups act as a

current source or sink source connected to the pin,

and eliminate the need for external resistors when

push-button or keypad devices are connected. The

pull-ups and pull-downs are enabled separately using

the CNPUx and the CNPDx registers, which contain

the control bits for each of the pins. Setting any of

the control bits enables the weak pull-ups and/or

pull-downs for the corresponding pins.

An additional control register (CNCONx) is shown in

11.2 CLR, SET and INV Registers

Every I/O module register has a corresponding CLR

(clear), SET (set) and INV (invert) register designed to

provide fast atomic bit manipulations. As the name of

the register implies, a value written to a SET, CLR or

INV register effectively performs the implied operation,

but only on the corresponding base register and only

bits specified as ‘1’ are modified. Bits specified as ‘0’

are not modified.

Reading SET, CLR and INV registers returns undefined

values. To see the affects of a write operation to a SET,

CLR or INV register, the base register must be read.

Note: Pull-ups and pull-downs on change notifi-

cation pins should always be disabled

when the port pin is configured as a digital

output.

PIC32MX1XX/2XX

11.3 Peripheral Pin Select

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. The chal-

lenge is even greater on low pin-count devices. In an

application where more than one peripheral needs to

be assigned to a single pin, inconvenient workarounds

in application code or a complete redesign may be the

only option.

Peripheral pin select configuration provides an

alternative to these choices by enabling peripheral set

selection and their placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, users can better tailor the device to

their entire application, rather than trimming the

application to fit the device.

The peripheral pin select configuration feature oper-

ates over a fixed subset of digital I/O pins. Users may

independently map the input and/or output of most dig-

ital peripherals to these I/O pins. Peripheral pin select

is performed in software and generally does not require

the device to be reprogrammed. Hardware safeguards

are included that prevent accidental or spurious

changes to the peripheral mapping once it has been

established.

11.3.1 AVAILABLE PINS

The number of available pins is dependent on the

particular device and its pin count. Pins that support the

peripheral pin select feature include the designation

“RPn” in their full pin designation, where “RP”

designates a remappable peripheral and “n” is the

remappable port number.

11.3.2 AVAILABLE PERIPHERALS

The peripherals managed by the peripheral pin select

are all digital-only peripherals. These include general

serial communications (UART and SPI), general pur-

pose timer clock inputs, timer-related peripherals (input

capture and output compare) and interrupt-on-change

inputs.

In comparison, some digital-only peripheral modules

are never included in the peripheral pin select feature.

This is because the peripheral’s function requires spe-

cial I/O circuitry on a specific port and cannot be easily

connected to multiple pins. These modules include I2C

among others. A similar requirement excludes all mod-

ules with analog inputs, such as the Analog-to-Digital

Converter (ADC).

A key difference between remappable and non-remap-

pable peripherals is that remappable peripherals are

not associated with a default I/O pin. The peripheral

must always be assigned to a specific I/O pin before it

can be used. In contrast, non-remappable peripherals

are always available on a default pin, assuming that the

peripheral is active and not conflicting with another

peripheral.

When a remappable peripheral is active on a given I/O

pin, it takes priority over all other digital I/O and digital

communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Remappable peripherals never take priority

over any analog functions associated with the pin.

11.3.3 CONTROLLING PERIPHERAL PIN

SELECT

Peripheral pin select features are controlled through

two sets of SFRs: one to map peripheral inputs, and

one to map outputs. Because they are separately con-

trolled, a particular peripheral’s input and output (if the

peripheral has both) can be placed on any selectable

function pin without constraint.

The association of a peripheral to a peripheral-select-

able pin is handled in two different ways, depending on

whether an input or output is being mapped.

11.3.4 INPUT MAPPING

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. That is, a control

will be mapped to. The [pin name]R registers, where [pin

name] refers to the peripheral pins listed in Table 11-1,

are used to configure peripheral input mapping (see

fields. Programming these bit fields with an appropriate

value maps the RPn pin with the corresponding value to

that peripheral. For any given device, the valid range of

values for any bit field is shown in Table 11-1.

For example, Figure 11-2 illustrates the remappable

pin selection for the U1RX input.

FIGURE 11-2: REMAPPABLE INPUT

EXAMPLE FOR U1RX

RPA2

RPB6

RPA4

2U1RX input

U1RXR<3:0>

to peripheral

RPn

Note: For input only, peripheral pin select functionality

does not have priority over TRISx settings.

Therefore, when configuring RPn pin for input,

the corresponding bit in the TRISx register must

also be configured for input (set to ‘1’).

PIC32MX1XX/2XX

TABLE 11-1: INPUT PIN SELECTION

Peripheral Pin [pin name]R SFR [pin name]R bits [pin name]R Value to

RPn Pin Selection

INT4 INT4R INT4R<3:0> 0000 = RPA0

0001 = RPB3

0010 = RPB4

0011 = RPB15

0100 = RPB7

0101 = RPC7

0110 = RPC0

0111 = RPC5

1000 = Reserved

•

1111 = Reserved

T2CK T2CKR T2CKR<3:0>

IC4 IC4R IC4R<3:0>

SS1 SS1R SS1R<3:0>

REFCLKI REFCLKIR REFCLKIR<3:0>

INT3 INT3R INT3R<3:0> 0000 = RPA1

0001 = RPB5

0010 = RPB1

0011 = RPB11

0100 = RPB8

0101 = RPA8

0110 = RPC8

0111 = RPA9

1000 = Reserved

•

1111 = Reserved

T3CK T3CKR T3CKR<3:0>

IC3 IC3R IC3R<3:0>

U1CTS U1CTSR U1CTSR<3:0>

U2RX U2RXR U2RXR<3:0>

SDI1 SDI1R SDI1R<3:0>

INT2 INT2R INT2R<3:0> 0000 = RPA2

0001 = RPB6

0010 = RPA4

0011 = RPB13

0100 = RPB2

0101 = RPC6

0110 = RPC1

0111 = RPC3

1000 = Reserved

•

1111 = Reserved

T4CK T4CKR T4CKR<3:0>

IC1 IC1R IC1R<3:0>

IC5 IC5R IC5R<3:0>

U1RX U1RXR U1RXR<3:0>

U2CTS U2CTSR U2CTSR<3:0>

SDI2 SDI2R SDI2R<3:0>

OCFB OCFBR OCFBR<3:0>

INT1 INT1R INT1R<3:0> 0000 = RPA3

0001 = RPB14

0010 = RPB0

0011 = RPB10

0100 = RPB9

0101 = RPC9

0110 = RPC2

0111 = RPC4

1000 = Reserved

•

1111 = Reserved

T5CK T5CKR T5CKR<3:0>

IC2 IC2R IC2R<3:0>

SS2 SS2R SS2R<3:0>

OCFA OCFAR OCFAR<3:0>

PIC32MX1XX/2XX

11.3.5 OUTPUT MAPPING

In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In

this case, a control register associated with a

particular pin dictates the peripheral output to be

mapped. The RPnR registers (Register 11-2) are

used to control output mapping. Like the [pin name]R

registers, each register contains sets of 4 bit fields.

The value of the bit field corresponds to one of the

peripherals, and that peripheral’s output is mapped

to the pin (see Table 11-2 and Figure 11-3).

A null output is associated with the output register reset

value of ‘0’. This is done to ensure that remappable

outputs remain disconnected from all output pins by

default.

FIGURE 11-3: EXAMPLE OF

MULTIPLEXING OF

REMAPPABLE OUTPUT

FOR RPA0

11.3.6 CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC32 devices include two features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Configuration bit select lock

11.3.6.1 Control Register Lock

Under normal operation, writes to the RPnR and [pin

name]R registers are not allowed. Attempted writes

appear to execute normally, but the contents of the

registers remain unchanged. To change these regis-

ters, they must be unlocked in hardware. The regis-

ter lock is controlled by the IOLOCK Configuration bit

(CFGCON<13>). Setting IOLOCK prevents writes to

the control registers; clearing IOLOCK allows writes.

To set or clear the IOLOCK bit, an unlock sequence

must be executed. Refer to Section 6. “Oscillator”

(DS61112) in the “PIC32 Family Reference Manual” for

details.

11.3.6.2 Configuration Bit Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPnR and [pin name]R registers. The IOL1WAY

Configuration bit (DEVCFG3<29>) blocks the IOLOCK

bit from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure

does not execute, and the peripheral pin select control

registers cannot be written to. The only way to clear the

bit and re-enable peripheral remapping is to perform a

device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session.

RPA0R<3:0>

Default

U1TX Output

U1RTS Output 2

Output Data

RPA0

PIC32MX1XX/2XX

TABLE 11-2: OUTPUT PIN SELECTION

RPn Port Pin RPnR SFR RPnR bits RPnR Value to Peripheral

Selection

RPA0 RPA0R RPA0R<3:0> 0000 = No Connect

0001 = U1TX

0010 = U2RTS

0011 = SS1

0100 = Reserved

0101 = OC1

0110 = Reserved

0111 = C2OUT

1000 = Reserved

•

1111 = Reserved

RPB3 RPB3R RPB3R<3:0>

RPB4 RPB4R RPB4R<3:0>

RPB15 RPB15R RPB15R<3:0>

RPB7 RPB7R RPB7R<3:0>

RPC7 RPC7R RPC7R<3:0>

RPC0 RPC0R RPC0R<3:0>

RPC5 RPC5R RPC5R<3:0>

RPA1 RPA1R RPA1R<3:0> 0000 = No Connect

0001 = Reserved

0010 = Reserved

0011 = SDO1

0100 = SDO2

0101 = OC2

0110 = Reserved

•

1111 = Reserved

RPB5 RPB5R RPB5R<3:0>

RPB1 RPB1R RPB1R<3:0>

RPB11 RPB11R RPB11R<3:0>

RPB8 RPB8R RPB8R<3:0>

RPA8 RPA8R RPA8R<3:0>

RPC8 RPC8R RPC8R<3:0>

RPA9 RPA9R RPA9R<3:0>

RPA2 RPA2R RPA2R<3:0> 0000 = No Connect

0001 = Reserved

0010 = Reserved

0011 = SDO1

0100 = SDO2

0101 = OC4

0110 = OC5

0111 = REFCLKO

1000 = Reserved

•

1111 = Reserved

RPB6 RPB6R RPB6R<3:0>

RPA4 RPA4R RPA4R<3:0>

RPB13 RPB13R RPB13R<3:0>

RPB2 RPB2R RPB2R<3:0>

RPC6 RPC6R RPC6R<3:0>

RPC1 RPC1R RPC1R<3:0>

RPC3 RPC3R RPC3R<3:0>

RPA3 RPA3R RPA3R<3:0> 0000 = No Connect

0001 = U1RTS

0010 = U2TX

0011 = Reserved

0100 = SS2

0101 = OC3

0110 = Reserved

0111 = C1OUT

1000 = Reserved

•

1111 = Reserved

RPB14 RPB14R RPB14R<3:0>

RPB0 RPB0R RPB0R<3:0>

RPB10 RPB10R RPB10R<3:0>

RPB9 RPB9R RPB9R<3:0>

RPC9 RPC9R RPC9R<3:0>

RPC2 RPC2R RPC2R<3:0>

RPC4 RPC4R RPC4R<3:0>

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

————[pin name]R<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits

Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 11-1 for

input pin selection values.

Note 1: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

————RPnR<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits

See Table 11 - 2 for output pin selection values.

Note 1: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 1.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

ON —SIDL— — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Change Notice (CN) Control ON bit

1 = CN is enabled

0 = CN is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Control bit

1 = CPU Idle Mode halts CN operation

0 = CPU Idle does not affect CN operation

bit 12-0 Unimplemented: Read as ‘0’

PIC32MX1XX/2XX

12.0 TIMER1 This family of PIC32 devices features one

synchronous/asynchronous 16-bit timer that can operate

as a free-running interval timer for various timing applica-

tions and counting external events. This timer can also

be used with the Low-Power Secondary Oscillator

(SOSC) for Real-Time Clock (RTC) applications. The

following modes are supported:

• Synchronous Internal Timer

• Synchronous Internal Gated Timer

• Synchronous External Timer

• Asynchronous External Timer

12.1 Additional Supported Features

• Selectable clock prescaler

• Timer operation during CPU Idle and Sleep mode

• Fast bit manipulation using CLR, SET and INV

registers

• Asynchronous mode can be used with the SOSC

to function as a Real-Time Clock (RTC)

FIGURE 12-1: TIMER 1 BLOCK DIAGRAM(1)

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS61105) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Sync

SOSCI

SOSCO/T1CK

PR1

T1IF

Equal 16-bit Comparator

TMR1

Reset

SOSCEN

Event Flag

TSYNC

TGATE

PBCLK

TCS

Gate

Sync

TCKPS<1:0>

Prescaler

1, 8, 64, 256

x 1

1 0

0 0

Note 1: The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the

FSOSCEN bit in Configuration Word, DEVCFG1.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0

ON(1) — SIDL TWDIS TWIP — — —

7:0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

TGATE — TCKPS<1:0> — TSYNC TCS —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit(1)

1 = Timer is enabled

0 = Timer is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode

0 = Continue operation even in Idle mode

bit 12 TWDIS: Asynchronous Timer Write Disable bit

1 = Writes to TMR1 are ignored until pending write operation completes

0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)

bit 11 TWIP: Asynchronous Timer Write in Progress bit

In Asynchronous Timer mode:

1 = Asynchronous write to TMR1 register in progress

0 = Asynchronous write to TMR1 register complete

In Synchronous Timer mode:

This bit is read as ‘0’.

bit 10-8 Unimplemented: Read as ‘0’

bit 7 TGATE: Timer Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits

11 = 1:256 prescale value

10 = 1:64 prescale value

01 = 1:8 prescale value

00 = 1:1 prescale value

Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

bit 3 Unimplemented: Read as ‘0’

bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit

When TCS = 1:

1 = External clock input is synchronized

0 = External clock input is not synchronized

When TCS = 0:

This bit is ignored.

bit 1 TCS: Timer Clock Source Select bit

1 = External clock from TxCKI pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

13.0 TIMER2/3, T I MER4/5

This family of PIC32 devices features four synchronous

16-bit timers (default) that can operate as a free-

running interval timer for various timing applications

and counting external events. The following modes are

supported:

• Synchronous internal 16-bit timer

• Synchronous internal 16-bit gated timer

• Synchronous external 16-bit timer

Two 32-bit synchronous timers are available by

combining Timer2 with Timer3 and Timer4 with Timer5.

The 32-bit timers can operate in three modes:

• Synchronous internal 32-bit timer

• Synchronous internal 32-bit gated timer

• Synchronous external 32-bit timer

13.1 Additional Supported Features

• Selectable clock prescaler

• Timers operational during CPU idle

• Time base for Input Capture and Output Compare

modules (Timer2 and Timer3 only)

• ADC event trigger (Timer3 only)

• Fast bit manipulation using CLR, SET and INV

registers

FIGURE 13-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 14. “Timers”

(DS61105) of the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: In this chapter, references to registers,

TxCON, TMRx and PRx, use ‘x’ to repre-

sent Timer2 through 5 in 16-bit modes. In

32-bit modes, ‘x’ represents Timer2 or 4;

‘y’ represents Timer3 or 5.

Sync

PRx

TxIF

Equal Comparator x 16

TMRx

Reset

Event Flag

TGATE

Gate

TxCK

Sync

TGATE

TCS

TCKPS

Prescaler

1, 2, 4, 8, 16,

32, 64, 256

x 1

1 0

0 0

PBCLK

Trigger(1)

ADC Event

Note 1: ADC event trigger is available on Timer3 only.

PIC32MX1XX/2XX

FIGURE 13-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)

TMRy TMRx

TyIF Event

Equal 32-bit Comparator

PRy PRx

Reset

LS Half Word

MS Half Word

Flag

Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or

Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.

2: ADC event trigger is available only on the Timer2/3 pair.

TGATE

PBCLK

Gate

TxCK

Sync

ADC Event

Trigger(2)

TGATE

TCS

TCKPS

Prescaler

1, 2, 4, 8, 16,

32, 64, 256

1 0

0 0

x 1

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

ON(1,3) —SIDL

(4) — — — — —

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

TGATE(3) TCKPS<2:0>(3) T32(2) —TCS

(3) —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit(1,3)

1 = Module is enabled

0 = Module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit(4)

1 = Discontinue operation when device enters Idle mode

0 = Continue operation even in Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3)

When TCS = 1:

This bit is ignored and is read as ‘0’.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3)

111 = 1:256 prescale value

110 = 1:64 prescale value

101 = 1:32 prescale value

100 = 1:16 prescale value

011 = 1:8 prescale value

010 = 1:4 prescale value

001 = 1:2 prescale value

000 = 1:1 prescale value

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is available only on even numbered timers (Timer2 and Timer4).

3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and

Timer5). All timer functions are set through the even numbered timers.

4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer

in Idle mode.

PIC32MX1XX/2XX

bit 3 T32: 32-Bit Timer Mode Select bit(2)

1 = Odd numbered and even numbered timers form a 32-bit timer

0 = Odd numbered and even numbered timers form a separate 16-bit timer

bit 2 Unimplemented: Read as ‘0’

bit 1 TCS: Timer Clock Source Select bit(3)

1 = External clock from TxCK pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as ‘0’

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is available only on even numbered timers (Timer2 and Timer4).

3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and

Timer5). All timer functions are set through the even numbered timers.

4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer

in Idle mode.

PIC32MX1XX/2XX

14.0 INPUT CAPTURE

The Input Capture module is useful in applications

requiring frequency (period) and pulse measurement.

The Input Capture module captures the 16-bit or 32-bit

value of the selected Time Base registers when an

event occurs at the ICx pin. The following events cause

capture events:

1. Simple capture event modes

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

2. Capture timer value on every edge (rising and

falling)

3. Capture timer value on every edge (rising and

falling), specified edge first.

4. Prescaler capture event modes

- Capture timer value on every 4th rising

edge of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select between one of

two 16-bit timers (Timer2 or Timer3) for the time base,

or two 16-bit timers (Timer2 and Timer3) together to

form a 32-bit timer. The selected timer can use either

an internal or external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

Interrupt optionally generated after 1, 2, 3 or 4

buffer locations are filled

• Input capture can also be used to provide

additional sources of external interrupts

FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 15. “Input

Capture” (DS61122) of the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

FIFO CONTROL

ICxBUF

TMR2 TMR3

CaptureEvent

FIFO

ICI<1:0>

ICM<2:0>

101

100

011

010

001

111

To CPU

Set Flag ICxIF

(In IFSx Register)

Rising Edge Mode

Prescaler Mode

(4th Rising Edge)

Falling Edge Mode

Edge Detection

Prescaler Mode

(16th Rising Edge)

Sleep/Idle

Wake-up Mode

C32/ICTMR

ICx pin

Mode

110

Specified/Every

Edge Mode

FEDGE

PIC32MX1XX/2XX

Bit Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ON(1) —SIDL— — —FEDGEC32

7:0 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit

-n = Bit Value at POR: (‘0’, ‘1’, x = unknown) P = Programmable bit r = Reserved bit

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Input Capture Module Enable bit(1)

1= Module enabled

0= Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Control bit

1= Halt in CPU Idle mode

0= Continue to operate in CPU Idle mode

bit 12-10 Unimplemented: Read as ‘0’

bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)

1= Capture rising edge first

0= Capture falling edge first

bit 8 C32: 32-bit Capture Select bit

1= 32-bit timer resource capture

0= 16-bit timer resource capture

bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)

0= Timer3 is the counter source for capture

1= Timer2 is the counter source for capture

bit 6-5 ICI<1:0>: Interrupt Control bits

11 = Interrupt on every fourth capture event

10 = Interrupt on every third capture event

01 = Interrupt on every second capture event

00 = Interrupt on every capture event

bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)

1= Input capture buffer is not empty; at least one more capture value can be read

0= Input capture buffer is empty

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

bit 2-0 ICM<2:0>: Input Capture Mode Select bits

111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)

110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter

101 = Prescaled Capture Event mode – every sixteenth rising edge

100 = Prescaled Capture Event mode – every fourth rising edge

011 = Simple Capture Event mode – every rising edge

010 = Simple Capture Event mode – every falling edge

001 = Edge Detect mode – every edge (rising and falling)

000 = Input Capture module is disabled

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

15.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to gen-

erate a single pulse or a train of pulses in response to

selected time base events. For all modes of operation,

the OCMP module compares the values stored in the

OCxR and/or the OCxRS registers to the value in the

selected timer. When a match occurs, the OCMP

module generates an event based on the selected

mode of operation.

The following are some of the key features:

• Multiple Output Compare Modules in a device

• Programmable interrupt generation on compare

event

• Single and Dual Compare modes

• Single and continuous output pulse generation

• Pulse-Width Modulation (PWM) mode

• Hardware-based PWM Fault detection and

automatic output disable

• Programmable selection of 16-bit or 32-bit time

bases

• Can operate from either of two available 16-bit

time bases or a single 32-bit time base

FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 16. “Output

Compare” (DS61111) in the “PIC32

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

OCxR(1)

Comparator

Output

Logic

OCM<2:0>

Output Enable

OCx(1)

Set Flag bit

OCxIF(1)

OCxRS(1)

Mode Select

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,

1 through 5.

2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.

OCTSEL 01

OCFA or OCFB(2)

Timer2 Timer2 Timer3

Logic

Output

Enable

Timer3

Rollover Rollover

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

ON(1) —SIDL— — — — —

7:0 U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

—— OC32 OCFLT(2) OCTSEL OCM<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Output Compare Peripheral On bit(1)

1 = Output Compare peripheral is enabled

0 = Output Compare peripheral is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters Idle mode

0 = Continue operation in Idle mode

bit 12-6 Unimplemented: Read as ‘0’

bit 5 OC32: 32-bit Compare Mode bit

1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source

0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source

bit 4 OCFLT: PWM Fault Condition Status bit(2)

1 = PWM Fault condition has occurred (cleared in HW only)

0 = No PWM Fault condition has occurred

bit 3 OCTSEL: Output Compare Timer Select bit

1 = Timer3 is the clock source for this OCMP module

0 = Timer2 is the clock source for this OCMP module

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx; Fault pin enabled

110 = PWM mode on OCx; Fault pin disabled

101 = Initialize OCx pin low; generate continuous output pulses on OCx pin

100 = Initialize OCx pin low; generate single output pulse on OCx pin

011 = Compare event toggles OCx pin

010 = Initialize OCx pin high; compare event forces OCx pin low

001 = Initialize OCx pin low; compare event forces OCx pin high

000 = Output compare peripheral is disabled but continues to draw current

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.

PIC32MX1XX/2XX

16.0 SERIAL PERIPHERAL

INTERFACE (SPI) The SPI module is a synchronous serial interface that

is useful for communicating with external peripherals

and other microcontroller devices. These peripheral

devices may be Serial EEPROMs, Shift registers, dis-

play drivers, Analog-to-Digital Converters (ADC), etc.

The PIC32 SPI module is compatible with Motorola®

SPI and SIOP interfaces.

Some of the key features of the SPI module are:

• Master and Slave modes support

• Four different clock formats

• Enhanced Framed SPI protocol support

• User-configurable 8-bit, 16-bit and 32-bit data width

• Separate SPI FIFO buffers for receive and transmit

- FIFO buffers act as 4/8/16-level deep FIFOs

based on 32/16/8-bit data width

• Programmable interrupt event on every 8-bit,

16-bit and 32-bit data transfer

• Operation during CPU Sleep and Idle mode

• Audio Codec Support:

-I

2S protocol

- Left-justified

- Right-justified

-PCM

FIGURE 16-1: SPI MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 23. “Serial

Peripheral Interface (SPI)” (DS61106) in

the “PIC32 Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Internal

Data Bus

SDIx

SDOx

SSx/FSYNC

SCKx

SPIxSR

bit 0

Shift

Control

Edge

Select

MSTEN

Baud Rate

Slave Select

Sync Control

Clock

Control

Transmit

Receive

and Frame

Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.

FIFOs Share Address SPIxBUF

SPIxBUF

Generator

PBCLK

WriteRead

SPIxTXB FIFO

SPIxRXB FIFO

REFCLK

MCLKSEL

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>

23:16 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

MCLKSEL(2) — — — — — SPIFE ENHBUF(2)

15:8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ON(1) — SIDL DISSDO MODE32 MODE16 SMP CKE(3)

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)

0 = Framed SPI support is disabled

bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)

1 = Frame sync pulse input (Slave mode)

0 = Frame sync pulse output (Master mode)

bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)

1 = Frame pulse is active-high

0 = Frame pulse is active-low

bit 28 MSSEN: Master Mode Slave Select Enable bit

1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in

Master mode. Polarity is determined by the FRMPOL bit.

0 = Slave select SPI support is disabled.

bit 27 FRMSYPW: Frame Sync Pulse Width bit

1 = Frame sync pulse is one character wide

0 = Frame sync pulse is one clock wide

bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per

pulse. This bit is only valid in FRAMED_SYNC mode.

111 = Reserved; do not use

110 = Reserved; do not use

101 = Generate a frame sync pulse on every 32 data characters

100 = Generate a frame sync pulse on every 16 data characters

011 = Generate a frame sync pulse on every 8 data characters

010 = Generate a frame sync pulse on every 4 data characters

001 = Generate a frame sync pulse on every 2 data characters

000 = Generate a frame sync pulse on every data character

bit 23 MCLKSEL: Master Clock Enable bit(2)

1 = REFCLK is used by the Baud Rate Generator

0 = PBCLK is used by the Baud Rate Generator

bit 22-18 Unimplemented: Read as ‘0’

bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)

1 = Frame synchronization pulse coincides with the first bit clock

0 = Frame synchronization pulse precedes the first bit clock

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in

the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

PIC32MX1XX/2XX

bit 16 ENHBUF: Enhanced Buffer Enable bit(2)

1 = Enhanced Buffer mode is enabled

0 = Enhanced Buffer mode is disabled

bit 15 ON: SPI Peripheral On bit(1)

1 = SPI Peripheral is enabled

0 = SPI Peripheral is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters in Idle mode

0 = Continue operation in Idle mode

bit 12 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register

0 = SDOx pin is controlled by the module

bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits

When AUDEN = 1:

MODE32 MODE16 Communication

1124-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame

1032-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame

0116-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame

0016-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame

When AUDEN = 0:

MODE32 MODE16 Communication

1x32-bit

0116-bit

008-bit

bit 9 SMP: SPI Data Input Sample Phase bit

Master mode (MSTEN = 1):

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

Slave mode (MSTEN = 0):

SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.

bit 8 CKE: SPI Clock Edge Select bit(3)

1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)

0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)

bit 7 SSEN: Slave Select Enable (Slave mode) bit

1 = SSx pin used for Slave mode

0 = SSx pin not used for Slave mode, pin controlled by port function.

bit 6 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level; active state is a low level

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 =Slave mode

bit 4 DISSDI: Disable SDI bit

1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)

0 = SDI pin is controlled by the SPI module

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in

the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

PIC32MX1XX/2XX

bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits

11 = Interrupt is generated when the buffer is not full (has one or more empty elements)

10 = Interrupt is generated when the buffer is empty by one-half or more

01 = Interrupt is generated when the buffer is completely empty

00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are

complete

bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits

11 = Interrupt is generated when the buffer is full

10 = Interrupt is generated when the buffer is full by one-half or more

01 = Interrupt is generated when the buffer is not empty

00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in

the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: This bit can only be written when the ON bit = 0.

3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI

mode (FRMEN = 1).

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SPISGNEXT —— FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR

7:0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0

AUDEN(1) — — — AUDMONO(1,2) — AUDMOD<1:0>(1,2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit

1 = Data from RX FIFO is sign extended

0 = Data from RX FIFO is not sign extened

bit 14-13 Unimplemented: Read as ‘0’

bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit

1 = Frame Error overflow generates error events

0 = Frame Error does not generate error events

bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit

1 = Receive overflow generates error events

0 = Receive overflow does not generate error events

bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit

1 = Transmit Underrun Generates Error Events

0 = Transmit Underrun Does Not Generates Error Events

bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)

1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data

0 = A ROV is a critical error which stop SPI operation

bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)

1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty

0 = A TUR is a critical error which stop SPI operation

bit 7 AUDEN: Enable Audio CODEC Support bit(1)

1 = Audio protocol enabled

0 = Audio protocol disabled

bit 6-5 Unimplemented: Read as ‘0’

bit 3 AUDMONO: Transmit Audio Data Format bit(1,2)

1 = Audio data is mono (Each data word is transmitted on both left and right channels)

0 = Audio data is stereo

bit 2 Unimplemented: Read as ‘0’

bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2)

11 = PCM/DSP mode

10 = Right Justified mode

01 = Left Justified mode

00 = I2S mode

Note 1: This bit can only be written when the ON bit = 0.

2: This bit is only valid for AUDEN = 1.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — RXBUFELM<4:0>

23:16 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — TXBUFELM<4:0>

15:8 U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0

— — — FRMERR SPIBUSY ——SPITUR

7:0 R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0

SRMT SPIROV SPIRBE —SPITBE— SPITBF SPIRBF

Legend: C = Clearable bit HS = Set in hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)

bit 23-21 Unimplemented: Read as ‘0’

bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)

bit 15-13 Unimplemented: Read as ‘0’

bit 12 FRMERR: SPI Frame Error status bit

1 = Frame error detected

0 = No Frame error detected

This bit is only valid when FRMEN = 1.

bit 11 SPIBUSY: SPI Activity Status bit

1 = SPI peripheral is currently busy with some transactions

0 = SPI peripheral is currently idle

bit 10-9 Unimplemented: Read as ‘0’

bit 8 SPITUR: Transmit Under Run bit

1 = Transmit buffer has encountered an underrun condition

0 = Transmit buffer has no underrun condition

This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling

the module.

bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)

1 = When SPI module shift register is empty

0 = When SPI module shift register is not empty

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new data is completely received and discarded. The user software has not read the previous data in

the SPIxBUF register.

0 = No overflow has occurred

This bit is set in hardware; can only be cleared (= 0) in software.

bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)

1 = RX FIFO is empty (CRPTR = SWPTR)

0 = RX FIFO is not empty (CRPTR ≠ SWPTR)

bit 4 Unimplemented: Read as ‘0’

PIC32MX1XX/2XX

bit 3 SPITBE: SPI Transmit Buffer Empty Status bit

1 = Transmit buffer, SPIxTXB is empty

0 = Transmit buffer, SPIxTXB is not empty

Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.

Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.

bit 2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPI Transmit Buffer Full Status bit

1 = Transmit not yet started, SPITXB is full

0 = Transmit buffer is not full

Standard Buffer Mode:

Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.

Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.

Enhanced Buffer Mode:

Set when CWPTR + 1 = SRPTR; cleared otherwise

bit 0 SPIRBF: SPI Receive Buffer Full Status bit

1 = Receive buffer, SPIxRXB is full

0 = Receive buffer, SPIxRXB is not full

Standard Buffer Mode:

Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.

Enhanced Buffer Mode:

Set when SWPTR + 1 = CRPTR; cleared otherwise

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

17.0 INTER-INTEGRATED

CIRCUIT™ (I2C™) The I2C module provides complete hardware support

for both Slave and Multi-Master modes of the I2C serial

communication standard. Figure 17-1 illustrates the

I2C module block diagram.

Each I2C module has a 2-pin interface: the SCLx pin is

clock and the SDAx pin is data.

Each I2C module offers the following key features:

•I

2C interface supporting both master and slave

operation

•I

2C Slave mode supports 7-bit and 10-bit addressing

•I

2C Master mode supports 7-bit and 10-bit

addressing

•I

2C port allows bidirectional transfers between

master and slaves

• Serial clock synchronization for the I2C port can

be used as a handshake mechanism to suspend

and resume serial transfer (SCLREL control)

•I

2C supports multi-master operation; detects bus

collision and arbitrates accordingly

• Provides support for address bit masking

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 24. “Inter-

Integrated Circuit™ (I2C™)” (DS61116)

in the “PIC32 Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC32MX1XX/2XX

FIGURE 17-1: I2C™ BLOCK DIAGRA M

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

I2CxADD

Start and Stop

Bit Detect

Clock

Address Match

Clock

Stretching

I2CxTRN

LSB

Shift Clock

BRG Down Counter

Reload

Control

PBCLK

Start and Stop

Bit Generation

Acknowledge

Generation

Collision

Detect

I2CxCON

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

I2CxMSK

I2CxRCV

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

ON(1) — SIDL SCLREL STRICT A10M DISSLW SMEN

7:0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

Legend: HC = Cleared in Hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: I2C Enable bit(1)

1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins

0 = Disables the I2C module; all I2C pins are controlled by PORT functions

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at

beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate

addresses in reserved address space.

0 = Strict I2C Reserved Address Rule not enabled

bit 10 A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

bit 7 GCEN: General Call Enable bit (when operating as I2C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0 = General call address disabled

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)

Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching

0 = Disable software or receive clock stretching

bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1 = Send NACK during Acknowledge

0 = Send ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(when operating as I2C master, applicable during master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence.

0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I2C master)

1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.

0 = Receive sequence not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence.

0 = Repeated Start condition not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I2C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0 = Start condition not in progress

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10

7:0

R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC

IWCOL I2COV D_A P S R_W RBF TBF

Legend: HS = Set in hardware HSC = Hardware set/cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ACKSTAT: Acknowledge Status bit

(when operating as I2C™ master, applicable to master transmit operation)

1 = NACK received from slave

0 = ACK received from slave

Hardware set or clear at end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation

0 = No collision

Hardware set at detection of bus collision.

bit 9 GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8 ADD10: 10-bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I2C module is busy

0 = No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5 D_A: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

PIC32MX1XX/2XX

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last

0 = Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 2 R_W: Read/Write Information bit (when operating as I2C slave)

1 = Read – indicates data transfer is output from slave

0 = Write – indicates data transfer is input to slave

Hardware set or clear after reception of I2C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full

0 = Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software

reads I2CxRCV.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full

0 = Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

PIC32MX1XX/2XX

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

The UART module is one of the serial I/O modules

available in PIC32MX1XX/2XX family devices. The

UART is a full-duplex, asynchronous communication

channel that communicates with peripheral devices

and personal computers through protocols, such as

RS-232, RS-485, LIN and IrDA®. The module also sup-

ports the hardware flow control option, with UxCTS and

UxRTS pins, and also includes an IrDA encoder and

decoder.

The primary features of the UART module are:

• Full-duplex, 8-bit or 9-bit data transmission

• Even, Odd or No Parity options (for 8-bit data)

• One or two Stop bits

• Hardware auto-baud feature

• Hardware flow control option

• Fully integrated Baud Rate Generator (BRG) with

16-bit prescaler

• Baud rates ranging from 38 bps to 10 Mbps at 40

MHz

• 8-level deep First-In-First-Out (FIFO) transmit

data buffer

• 8-level deep FIFO receive data buffer

• Parity, framing and buffer overrun error detection

• Support for interrupt-only on address detect

(9th bit = 1)

• Separate transmit and receive interrupts

• Loopback mode for diagnostic support

• LIN Protocol support

• IrDA encoder and decoder with 16x baud clock

output for external IrDA encoder/decoder support

Figure 18-1 illustrates a simplified block diagram of the

UART.

FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 21. “Universal

Asynchronous Receiver Transmitter

(UART)” (DS61107) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Baud Rate Generator

UxRX

Hardware Flow Control

UARTx Receiver

UARTx Transmitter UxTX

UxCTS

UxRTS/BCLKx

IrDA®

Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ON(1) —SIDLIRENRTSMD—UEN<1:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: UARTx Enable bit(1)

1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN

control bits

0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx

registers; UARTx power consumption is minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode

0 = Continue operation in Idle mode

bit 12 IREN: IrDA Encoder and Decoder Enable bit

1 = IrDA is enabled

0 = IrDA is disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 =UxRTS

pin is in Simplex mode

0 =UxRTS

pin is in Flow Control mode

bit 10 Unimplemented: Read as ‘0’

bit 9-8 UEN<1:0>: UARTx Enable bits

11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits

in the PORTx register

00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by

corresponding bits in the PORTx register

bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit

1 = Wake-up enabled

0 = Wake-up disabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Loopback mode is enabled

0 = Loopback mode is disabled

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);

cleared by hardware upon completion

0 = Baud rate measurement disabled or completed

bit 4 RXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is ‘0’

0 = UxRX Idle state is ‘1’

bit 3 BRGH: High Baud Rate Enable bit

1 = High-Speed mode – 4x baud clock enabled

0 = Standard Speed mode – 16x baud clock enabled

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, no parity

bit 0 STSEL: Stop Selection bit

1 = 2 Stop bits

0 = 1 Stop bit

Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —ADM_EN

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADDR<7:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1

UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT

7:0 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0 R-0

URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Read as ‘0’

bit 24 ADM_EN: Automatic Address Detect Mode Enable bit

1 = Automatic Address Detect mode is enabled

0 = Automatic Address Detect mode is disabled

bit 23-16 ADDR<7:0>: Automatic Address Mask bits

When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address

detection.

bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits

11 = Reserved, do not use

10 = Interrupt is generated and asserted while the transmit buffer is empty

01 = Interrupt is generated and asserted when all characters have been transmitted

00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space

bit 13 UTXINV: Transmit Polarity Inversion bit

If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):

1 = UxTX Idle state is ‘0’

0 = UxTX Idle state is ‘1’

If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):

1 = IrDA encoded UxTX Idle state is ‘1’

0 = IrDA encoded UxTX Idle state is ‘0’

bit 12 URXEN: Receiver Enable bit

1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)

0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.

bit 11 UTXBRK: Transmit Break bit

1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by

hardware upon completion

0 = Break transmission is disabled or completed

bit 10 UTXEN: Transmit Enable bit

1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)

0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is con-

trolled by port.

bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)

1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)

0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer

PIC32MX1XX/2XX

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit

11 = Reserved; do not use

10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)

01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)

00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect

0 = Address Detect mode is disabled

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Data is being received

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit.

This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit

resets the receiver buffer and RSR to empty state.

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

PIC32MX1XX/2XX

Figure 18-2 and Figure 18-3 illustrate typical receive

and transmit timing for the UART module.

FIGURE 18-2: UART RECEPTION

FIGURE 18-3: TRANSMISSION (8-BIT OR 9-BIT DATA)

Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13

Read to

UxRXREG

UxRX

RIDLE

OERR

UxRXIF

URXISEL = 00

UxRXIF

URXISEL = 01

UxRXIF

URXISEL = 10

Char 1 Char 2-4 Char 5-10 Char 11-13

Cleared by

Software

Cleared by

Software

Cleared by

Software

StartStart Bit 0 Bit 1 Stop

Write to

TSR

BCLK/16

(Shift Clock)

UxTX

UxTXIF

UTXISEL = 00

Bit 1

UxTXREG

UTXISEL = 01

UxTXIF

UTXISEL = 10

8 into TxBUF

Pull from Buffer

PIC32MX1XX/2XX

19.0 PARALLEL MASTER PORT

(PMP)

The PMP is a parallel 8-bit input/output module

specifically designed to communicate with a wide

variety of parallel devices, such as communications

peripherals, LCDs, external memory devices and

microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP module is

highly configurable.

Key features of the PMP module include:

• Fully multiplexed address/data mode

• Demultiplexed or partially multiplexed address/

data mode

- up to 11 address lines with single chip select

- up to 12 address lines without chip select

• One Chip Select Line

• Programmable Strobe Options

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support

- Address Support

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

FIGURE 19-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 13. “Parallel

Master Port (PMP)” (DS61128) in the

“PIC32 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PMA<0>

PMA<14>

PMRD

PMWR

PMENB

PMRD/PMWR

PMCS1

PMA<1>

PMA<10:2>

PMALL

PMALH Flash

Address Bus

Data Bus

Control Lines

PIC32MX1XX/2XX

LCD FIFO

Microcontroller

8-bit Data (with or without multiplexed addressing)

Up to 12-bit Address

Parallel

Buffer

PMD<7:0>

Master Port

EEPROM

SRAM

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ON(1) —SIDL

ADRMUX<1:0>

PMPTTL PTWREN PTRDEN

7:0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

CSF<1:0>(2) ALP(2) —CS1P

(2) — WRSP RDSP

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Parallel Master Port Enable bit(1)

1 = PMP enabled

0 = PMP disabled, no off-chip access performed

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used

10 = All 16 bits of address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and

PMA<14>

00 = Address and data appear on separate pins

bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt Trigger input buffer

bit 9 PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port enabled

0 = PMWR/PMENB port disabled

bit 8 PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port enabled

0 = PMRD/PMWR port disabled

bit 7-6 CSF<1:0>: Chip Select Function bits(2)

11 = Reserved

10 = PMCS1 function as Chip Select

01 = PMCS1 functions as address bit 14

00 = PMCS1 function as address bit 14

bit 5 ALP: Address Latch Polarity bit(2)

1 = Active-high (PMALL and PMALH)

0 = Active-low (PMALL and PMALH)

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when their corresponding pins are used as address lines.

PIC32MX1XX/2XX

bit 4 Unimplemented: Read as ‘0’

bit 3 CS1P: Chip Select 0 Polarity bit(2)

1 = Active-high (PMCS1)

0 = Active-low (PMCS1)

bit 2 Unimplemented: Read as ‘0’

bit 1 WRSP: Write Strobe Polarity bit

For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe active-high (PMWR)

0= Write strobe active-low (PMWR)

For Master mode 1 (PMMODE<9:8> = 11):

1= Enable strobe active-high (PMENB)

0= Enable strobe active-low (PMENB)

bit 0 RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Read Strobe active-high (PMRD)

0= Read Strobe active-low (PMRD)

For Master mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe active-high (PMRD/PMWR)

0= Read/write strobe active-low (PMRD/PMWR)

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when their corresponding pins are used as address lines.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

BUSY IRQM<1:0> INCM<1:0> — MODE<1:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAITB<1:0>(1) WAITM<3:0>(1) WAITE<1:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy

0 = Port is not busy

bit 14-13 IRQM<1:0>: Interrupt Request Mode bits

11 = Reserved, do not use

10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)

01 = Interrupt generated at the end of the read/write cycle

00 = No Interrupt generated

bit 12-11 INCM<1:0>: Increment Mode bits

11 = Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00 only)

10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)

01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)

00 = No increment or decrement of address

bit 10 Unimplemented: Read as ‘0’

bit 9-8 MODE<1:0>: Parallel Port Mode Select bits

11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>)

10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>)

01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)

00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)

11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB

10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB

01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB

00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a

write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.

2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.

PIC32MX1XX/2XX

bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)

1111 = Wait of 16 TPB

•

0001 = Wait of 2 TPB

0000 = Wait of 1 TPB (default)

bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)

11 = Wait of 4 TPB

10 = Wait of 3 TPB

01 = Wait of 2 TPB

00 = Wait of 1 TPB (default)

For Read operations:

11 = Wait of 3 TPB

10 = Wait of 2 TPB

01 = Wait of 1 TPB

00 = Wait of 0 TPB (default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a

write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.

2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

—CS1——— ADDR<10:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 CS1: Chip Select 1 bit

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (pin functions as PMA<14>)

bit 13-11 Unimplemented: Read as ‘0’

bit 10-0 ADDR<10:0>: Destination Address bits

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

—PTEN14———PTEN<10:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 15-14 PTEN14: PMCS1 Strobe Enable bits

1 = PMA14 functions as either PMA14 or PMCS1(1)

0 = PMA14 functions as port I/O

bit 13-11 Unimplemented: Read as ‘0’

bit 10-2 PTEN<10:2>: PMP Address Port Enable bits

1 = PMA<10:2> function as PMP address lines

0 = PMA<10:2> function as port I/O

bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)

0 = PMA1 and PMA0 pads functions as port I/O

Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.

2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode

selected by bits ADRMUX<1:0> in the PMCON register.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

15:8 R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0

IBF IBOV —— IB3FIB2FIB1FIB0F

7:0 R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF —— OB3E OB2E OB1E OB0E

Legend: HSC = Set by Hardware; Cleared by Software

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full

0 = Some or all of the writable input buffer registers are empty

bit 14 IBOV: Input Buffer Overflow Status bit

1 = A write attempt to a full input byte buffer occurred (must be cleared in software)

0 = No overflow occurred

bit 13-12 Unimplemented: Read as ‘0’

bit 11-8 IBxF: Input Buffer x Status Full bits

1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)

0 = Input Buffer does not contain any unread data

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable output buffer registers are empty

0 = Some or all of the readable output buffer registers are full

bit 6 OBUF: Output Buffer Underflow Status bit

1 = A read occurred from an empty output byte buffer (must be cleared in software)

0 = No underflow occurred

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 OBxE: Output Buffer x Status Empty bits

1 = Output buffer is empty (writing data to the buffer will clear this bit)

0 = Output buffer contains data that has not been transmitted

PIC32MX1XX/2XX

20.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

The PIC32 RTCC module is intended for applications in

which accurate time must be maintained for extended

periods of time with minimal or no CPU intervention.

Low-power optimization provides extended battery

lifetime while keeping track of time.

Following are some of the key features of this module:

• Time: hours, minutes and seconds

• 24-hour format (military time)

• Visibility of one-half second period

• Provides calendar: Weekday, date, month and

year

• Alarm intervals are configurable for half of a

second, one second, 10 seconds, one minute, 10

minutes, one hour, one day, one week, one month

and one year

• Alarm repeat with decrementing counter

• Alarm with indefinite repeat: Chime

• Year range: 2000 to 2099

• Leap year correction

• BCD format for smaller firmware overhead

• Optimized for long-term battery operation

• Fractional second synchronization

• User calibration of the clock crystal frequency with

auto-adjust

• Calibration range: ±0.66 seconds error per month

• Calibrates up to 260 ppm of crystal error

• Requirements: External 32.768 kHz clock crystal

• Alarm pulse or seconds clock output on

RTCC pin

FIGURE 20-1: RTCC BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 29. “Real-Time

Clock and Calendar (RTCC)”

(DS61125) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

RTCC Prescalers

RTCC Timer

Comparator

Compare Registers

Repeat Counter

ALRMTIME

HR, MIN, SEC

ALRMDATE

with Masks

RTCC Interrupt Logic

Alarm

Event

32.768 kHz Input

from Secondary

0.5s

Alarm Pulse

Set RTCC Flag

RTCVAL

ALRMVAL

RTCC

RTCOE

Oscillator (SOSC)

CAL<9:0>

MONTH, DAY, WDAY

RTCTIME

HR, MIN, SEC

RTCDATE

YEAR, MONTH, DAY, WDAY

Seconds Pulse

RTSECSEL

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —CAL<9:8>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL<7:0>

15:8 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

ON(2,3) —SIDL— — — — —

7:0 R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0

RTSECSEL(4) RTCCLKON ——RTCWREN

(5) RTCSYNC HALFSEC(6) RTCOE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-26 Unimplemented: Read as ‘0’

bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value

0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute

•

0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute

0000000000 = No adjustment

1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute

•

1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute

bit 15 ON: RTCC On bit(2,3)

1 = RTCC module is enabled

0 = RTCC module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode

0 = Continue normal operation in Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit(4)

1 = RTCC Seconds Clock is selected for the RTCC pin

0 = RTCC Alarm Pulse is selected for the RTCC pin

bit 6 RTCCLKON: RTCC Clock Enable Status bit

1 = RTCC Clock is actively running

0 = RTCC Clock is not running

bit 5-4 Unimplemented: Read as ‘0’

Note 1: This register is reset only on a Power-on Reset (POR).

2: The ON bit is only writable when RTCWREN = 1.

3: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

4: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

5: The RTCWREN bit can be set only when the write sequence is enabled.

6: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

PIC32MX1XX/2XX

bit 3 RTCWREN: RTC Value Registers Write Enable bit(5)

1 = RTC Value registers can be written to by the user

0 = RTC Value registers are locked out from being written to by the user

bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit

1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read

If the register is read twice and results in the same data, the data can be assumed to be valid

0 = RTC Value registers can be read without concern about a rollover ripple

bit 1 HALFSEC: Half-Second Status bit(6)

1 = Second half period of a second

0 = First half period of a second

bit 0 RTCOE: RTCC Output Enable bit

1 = RTCC clock output enabled – clock presented onto an I/O

0 = RTCC clock output disabled

Note 1: This register is reset only on a Power-on Reset (POR).

2: The ON bit is only writable when RTCWREN = 1.

3: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

4: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

5: The RTCWREN bit can be set only when the write sequence is enabled.

6: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN(2,3) CHIME(3) PIV(3) ALRMSYNC(4) AMASK<3:0>(3)

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ARPT<7:0>(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ALRMEN: Alarm Enable bit(2,3)

1 = Alarm is enabled

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit(3)

1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF

0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00

bit 13 PIV: Alarm Pulse Initial Value bit(3)

When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.

When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.

bit 12 ALRMSYNC: Alarm Sync bit(4)

1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.

The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple

bits may be changing, which are then synchronized to the PB clock domain

0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC

clocks away from a half-second rollover

bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3)

0000 = Every half-second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29, once every four years)

1010 = Reserved; do not use

1011 = Reserved; do not use

11xx = Reserved; do not use

Note 1: This register is reset only on a Power-on Reset (POR).

2: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and

CHIME = 0.

3: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.

4: This assumes a CPU read will execute in less than 32 PBCLKs.

PIC32MX1XX/2XX

bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(3)

11111111 = Alarm will trigger 256 times

•

00000000 = Alarm will trigger one time

The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.

Note 1: This register is reset only on a Power-on Reset (POR).

2: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and

CHIME = 0.

3: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.

4: This assumes a CPU read will execute in less than 32 PBCLKs.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

HR10<3:0> HR01<3:0>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MIN10<3:0> MIN01<3:0>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SEC10<3:0> SEC01<3:0>

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9

bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9

bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as ‘0’

Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>).

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YEAR10<3:0> YEAR01<3:0>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DAY10<3:0> DAY01<3:0>

7:0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits

bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit

bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1

bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9

bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6

Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>).

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

HR10<3:0> HR01<3:0>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MIN10<3:0> MIN01<3:0>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SEC10<3:0> SEC01<3:0>

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9

bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9

bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as ‘0’

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DAY10<1:0> DAY01<3:0>

7:0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1

bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9

bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6

PIC32MX1XX/2XX

NOTES:

PIC32MX1XX/2XX

21.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (ADC) The PIC32MX1XX/2XX 10-bit Analog-to-Digital

Converter (ADC) includes the following features:

• Successive Approximation Register (SAR)

conversion

• Up to 1 Msps conversion speed

• Up to 13 analog input pins

• External voltage reference input pins

• One unipolar, differential Sample and Hold

Amplifier (SHA)

• Automatic Channel Scan mode

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable buffer fill modes

• Eight conversion result format options

• Operation during CPU Sleep and Idle modes

A block diagram of the 10-bit ADC is illustrated in

Figure 21-1. The 10-bit ADC has up to 13 analog input

pins, designated AN0-AN12. In addition, there are two

analog input pins for external voltage reference

connections. These voltage reference inputs may be

shared with other analog input pins and may be

common to other analog module references.

FIGURE 21-1: ADC1 MODULE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC32MX1XX/2XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 17. “10-bit

Analog-to-Digital Converter (ADC)”

(DS61104) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

SAR ADC

S&H

ADC1BUF0

ADC1BUF1

ADC1BUF2

ADC1BUFF

ADC1BUFE

CTMUT(3)

IVREF(4)

AN1

VREFL

CH0SB<4:0>

CH0NA CH0NB

CH0SA<4:0>

Channel

Scan

CSCNA

Alternate

VREF+(1) AVDD AVSS

VREF-(1)

Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.

2: AN8 is only available on 44-pin devices. AN6 and AN7 are not available on 28-pin devices.

3: Connected to the CTMU module. See Section 24.0 “Charge Time Measurement Unit (CTMU)” for more

information.

4: See Section 23.0 “Comparator Voltage Reference (CVREF)” for more information.

5: This selection is only used with CTMU capacitive and time measurement.

Input Selection

VREFH VREFL

VCFG<2:0>

AN12(2)

AN0

Open(5)

CTMUI(3)

PIC32MX1XX/2XX

FIGURE 21-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

Div 2

TPB(2)

ADC Conversion

Clock Multiplier

2, 4,..., 512

ADRC

TAD

ADCS<7:0>

FRC(1)

Note 1: See Section 29.0 “Electrical Characteristics” for the exact FRC clock value.

2: Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information.

PIC32MX1XX/2XX

Bit

Range Bit

31/23/15/7 Bit

30/22/14/6 Bit

29/21/13/5 Bit

28/20/12/4 Bit

27/19/11/3 Bit

26/18/10/2 Bit

25/17/9/1 Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

ON(1) —SIDL—— FORM<2:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC

R/C-0, HSC

SSRC<2:0> CLRASAM — ASAM SAMP(2) DONE(3)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: ADC Operating Mode bit(1)

1 = ADC module is operating

0 = ADC module is not operating

bit 14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10-8 FORM<2:0>: Data Output Format bits

011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)

010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)

001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)

000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)

110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)

101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)

100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits

111 = Internal counter ends sampling and starts conversion (auto convert)

110 = Reserved

101 = Reserved

100 = Reserved

011 = CTMU ends sampling and starts conversion

010 = Timer 3 period match ends sampling and starts conversion

001 = Active transition on INT0 pin ends sampling and starts conversion

000 = Clearing SAMP bit ends sampling and starts conversion

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if

ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ≠ ‘0’, this

bit is automatically cleared by hardware to end sampling and start conversion.

3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can

write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation

already in progress. This bit is automatically cleared by hardware at the start of a new conversion.

PIC32MX1XX/2XX

bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)

1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the

ADC interrupt is generated.

0 = Normal operation, buffer contents will be overwritten by the next conversion sequence

bit 3 Unimplemented: Read as ‘0’

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set.

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit(2)

1 = The ADC sample and hold amplifier is sampling

0 = The ADC sample/hold amplifier is holding

When ASAM = 0, writing ‘1’ to this bit starts sampling.

When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.

bit 0 DONE: Analog-to-Digital Conversion Status bit(3)

1 = Analog-to-digital conversion is done

0 = Analog-to-digital conversion is not done or has not started

Clearing this bit will not affect any operation in progress.