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FEATURES
RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1OE
3Y V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN74AUC125QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
•Optimized for 1.8-V Operation and Is 3.6-V I/OTolerant to Support Mixed-Mode SignalOperation
•I
off
Supports Partial-Power-Down ModeOperation
•Sub-1-V Operable•Max t
pd
of 2.1 ns at 1.8 V•Low Power Consumption, 10- µA Max I
CC•±8-mA Output Drive at 1.8 V•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1500-V Charged-Device Model (C101)
This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V
CC
operation, but is designed specifically for 1.6-Vto 1.95-V V
CC
operation.
The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when theassociated output-enable ( OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C QFN – RGY Tape and reel SN74AUC125RGYR MS125
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
YOE A
L H HL L LH X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
1
1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
Absolute Maximum Ratings
(1)
SN74AUC125
QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 3.6 VV
I
Input voltage range
(2)
–0.5 3.6 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 3.6 VV
O
Output voltage range
(2)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±20 mAContinuous current through V
CC
or GND ±100 mAθ
JA
Package thermal impedance
(3)
47 °C/WT
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-5.
2
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Recommended Operating Conditions
(1)
SN74AUC125QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
MIN MAX UNIT
V
CC
Supply voltage 0.8 2.7 VV
CC
= 0.8 V V
CC
V
IH
High-level input voltage V
CC
= 1.1 V to 1.95 V 0.65 × V
CC
VV
CC
= 2.3 V to 2.7 V 1.7V
CC
= 0.8 V 0V
IL
Low-level input voltage V
CC
= 1.1 V to 1.95 V 0.35 × V
CC
VV
CC
= 2.3 V to 2.7 V 0.7V
I
Input voltage 0 3.6 VActive state 0 V
CCV
O
Output voltage V3-state 0 3.6V
CC
= 0.8 V –0.7V
CC
= 1.1 V –3I
OH
High-level output current V
CC
= 1.4 V –5 mAV
CC
= 1.65 V –8V
CC
= 2.3 V –9V
CC
= 0.8 V 0.7V
CC
= 1.1 V 3I
OL
Low-level output current V
CC
= 1.4 V 5 mAV
CC
= 1.65 V 8V
CC
= 2.3 V 9∆t/ ∆v Input transition rise or fall rate 20 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
Switching Characteristics
Switching Characteristics
SN74AUC125
QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 0.8 V to 2.7 V V
CC
– 0.1I
OH
= –0.7 mA 0.8 V 0.55I
OH
= –3 mA 1.1 V 0.8V
OH
VI
OH
= –5 mA 1.4 V 1I
OH
= –8 mA 1.65 V 1.2I
OH
= –9 mA 2.3 V 1.8I
OL
= 100 µA 0.8 V to 2.7 V 0.2I
OL
= 0.7 mA 0.8 V 0.25I
OL
= 3 mA 1.1 V 0.3V
OL
VI
OL
= 5 mA 1.4 V 0.4I
OL
= 8 mA 1.65 V 0.45I
OL
= 9 mA 2.3 V 0.6I
I
V
I
= V
CC
or GND 0 to 2.7 V ±5 µAI
off
V
I
or V
O
= 2.7 V 0 ±10 µAI
OZ
V
O
= V
CC
or GND 2.7 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 0.8 V to 2.7 V 10 µAC
i
V
I
= V
CC
or GND 2.5 V 2.5 pFC
o
V
O
= V
CC
or GND 2.5 V 5 pF
(1) All typical values are at T
A
= 25°C.
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 1 )
V
CC
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 VV
CC
= 0.8 VFROM TO
± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX
t
pd
A Y 5.8 0.7 3.7 0.6 2.6 0.5 1 2.1 0.5 1.3 nst
en
OE Y 7.5 0.9 4.1 0.7 2.9 0.6 1 2.2 0.6 1.4 nst
dis
OE Y 6.4 1.6 5.1 1.5 3.6 1.4 2.4 3.5 1 2.6 ns
over recommended operating free-air temperature range, C
L
= 30 pF (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 VFROM TO
± 0.15 V ± 0.2 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
t
pd
A Y 0.5 1.8 2.6 0.5 2.1 nst
en
OE Y 0.6 1.6 2.8 0.6 2.3 nst
dis
OE Y 1.2 2.4 3.4 0.8 2.3 ns
4
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Operating Characteristics
SN74AUC125QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
T
A
= 25°C
V
CC
= 0.8 V V
CC
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP TYP TYP
Outputs
15 15 15 16 17Power
enabledC
pd
dissipation f = 10 MHz pFOutputscapacitance
22234disabled
5
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PARAMETER MEASUREMENT INFORMATION
VCC/2
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
Data Input
Timing Input VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH − V∆
≈0 V
VCC
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
VCC RL0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V∆
CL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
SN74AUC125
QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES508A – NOVEMBER 2003 – REVISED MARCH 2005
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74AUC125RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74AUC125RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUC125RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUC125RGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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