DataSheeT - enpirion(R) power solutions EN5395QI 9A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION NOT RECOMMENDED FOR NEW DESIGN The EN5395QI is a Power System on a Chip (PowerSoC) DC-DC converter. It is specifically designed to meet the precise voltage and fast transient requirements of present and future highperformance, low-power processor, DSP, FPGA, ASIC, memory boards, and system level applications in distributed power architecture. Advanced circuit techniques, ultra-high switching frequency, and innovative, high-density, integrated circuit and proprietary inductor technology deliver high-quality, ultra-compact, non-isolated DC-DC conversion. Operating this converter requires as few as five external components that include small value input and output ceramic capacitors and a soft-start capacitor. Intel Enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. VIN 2 x 47F 1 PVIN VS0 AVIN VS1 VS2 POK VID Output Voltage Select VOUT AGND PGND 15nF 10mm 12mm * * * * * * * * * * * * * * Integrated Inductor Technology: Integrated Inductor, MOSFETS, Controller in a 10 x 12 x 1.85mm package Low Part Count: only 5 MLC Capacitors. Up to 30W continuous output power. Low output impedance optimized for 90 nm Master/slave configuration for paralleling. 5MHz operating frequency. High efficiency, up to 93%. Wide input voltage range of 2.375V to 5.5V. 3-Pin VID output voltage select to choose one of 7 pre-programmed output voltages. Output Enable pin and Power OK signal. Programmable soft-start time. Adjustable over-current protection. Thermal shutdown, short circuit, over-voltage and under-voltage protection. RoHS compliant, MSL level 3, 260C reflow. APPLICATIONS VSENSE SS FEATURES VOUT 2 x 47F Figure 1: Simplified Applications Circuit * * * Area constrained applications Noise sensitive applications Low voltage, distributed power architectures with 2.5V, 3.3V or 5V rails Computing Enterprise Storage Broadband, networking, LAN/WAN, optical * DSL, STB, DVR, DTV, Industrial PC * * * Page 1 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description EN5395QI EN5395QI -40C to +125C 56-pin (10mm x 12mm x 1.85mm) QFN EVB-EN5395QI EN5395QI QFN Evaluation Board Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html PIN FUNCTIONS Figure 2: Pin Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Page 2 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI PIN DESCRIPTIONS PIN 1-3 NAME NC TYPE FUNCTION - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 4-5 NC(SW) - NO CONNECT - These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. 6-13 NC - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 14-20 VOUT Power Regulated converter output. Connect these pins to the load and place output capacitor from these pins the PGND pins 24-26. 21-22 NC(SW) - NO CONNECT - These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. 23 NC - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 24-29 PGND Power Output power ground. Refer to layout guideline section. 30-35 PVIN Power Input power supply. Connect to input power supply. Decouple with input capacitor to PGND. 36-37 NC - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 38 ROCP Analog Optional Over Current Protection adjust pin. Place ROCP resistor between this pin and AGND (pin 40) to adjust the over current trip point. 39 AVIN Power Analog voltage input for the controller circuits. Connect this pin to the input power supply. 40 AGND Power Analog ground for the controller circuits. 41-42 NC - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 43 VS2 Analog Voltage select line 2 input. See Table 1. 44 VS1 Analog Voltage select line 1 input. See Table 1. 45 VS0 Analog Voltage select line 0 input. See Table 1. 46 POK Digital Power OK is an open drain transistor for power system state indication. POK is a logic high when VOUT is with -10% to +20% of VOUT nominal. Page 3 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI PIN NAME TYPE FUNCTION 47 VSENSE Analog Remote voltage sense input. Connect this pin to the load voltage at the point to be regulated. 48 SS Analog Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup timing. 49 EAIN Analog Optional Error Amplifier input. Allows for customization of the control loop. 50 EAOUT Analog Optional Error Amplifier output. Allows for customization of the control loop. 51 COMP Analog Output of the buffer leading to the error amplifier. Used for external modifications of the compensation network. 52 ENABLE Analog Input Enable. Applying a logic high, enables the output and initiates a soft-start. Applying a logic low disables the output. Analog PWM input/output. Used for optional master/slave configuration. When M/S pin is asserted "low", PWM will output the gate-drive PWM waveform. When the M/S pin is asserted "high", the PWM pin is configured as an input for PWM signal from the "master" device. PWM pin can drive up to 3 slave devices. - NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground. This pin may be connected internally. However, this pin must be soldered to the PCB. 53 54 PMW NC 55 M/S Analog Optional Master/Slave select pin. Asserting pin "low" places device in Master Mode for current sharing. PWM pin (53) will output PWM drive signal. Asserting pin "high" will place the device in Slave Mode. PWM pin (53) will be configured to input (receive) PWM drive signal from "Master" device. 56-58 NC - NO CONNECT - Do not electrically connect these pins to each other or to PCB. CAUTION! May be internally connected. Page 4 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Pin Ratings PARAMETER SYMBOL MIN MAX UNITS PVIN -0.5 7.0 V ENABLE, VSENSE, VS0-VS2, M/S -0.5 VIN V EAIN, EAOUT, COMP -0.5 2.5 V SS, PWM -0.5 3.0 V POK -0.5 VIN +0.3 V MIN MAX UNITS +150 C +150 C +260 C MAX UNITS Absolute Maximum Thermal Ratings PARAMETER CONDITION Maximum Operating Junction Temperature Storage Temperature Range Reflow Peak Body Temperature -65 (10 Sec) MSL3 JEDEC J-STD020A Absolute Maximum ESD Ratings PARAMETER CONDITION MIN HBM (Human Body Model) 2000 V CDM (Charged Device Model) 500 V RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS VIN 2.375 5.5 V Output Voltage Range VOUT 0.75 VIN - VDO (1) V Output Current Range IOUT 0 Operating Ambient Temperature Range TA Operating Junction Temperature TJ Input Voltage Range (2) 9 A -40 +85 C -40 +125 C Page 5 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI THERMAL CHARACTERISTICS PARAMETER SYMBOL TYPICAL UNITS TSD 150 C TSDHYS 20 C Thermal Resistance: Junction to Ambient (0 LFM) (3) JA 18 C/W Thermal Resistance: Junction to Case (0 LFM) JC 1.5 C/W Thermal Overload Trip Point Thermal Overload Trip Point Hysteresis (1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table. (2) Reference figures 5 and 6 fir the Output Current Derating Curves. (3) Based on four layer board and proper thermal design in line with JEDEC EIJ/JESD 51 standards. ELECTRICAL CHARACTERISTICS NOTE: VIN = 5.5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TA = 25C, 2.375V VIN 5.5V ILOAD = 1A; TA = 25C VOUT Initial Accuracy VOUT_INIT % VID Output Voltage Setting (V): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 -2 +2 0.8 -3 +3 2.4V VIN 5.5V -40C TA +85C Overall VOUT Accuracy (Line, Load, and Temperature combined) VOUT_ALL Transient Response Peak Deviation VOUT 0A ILOAD 9A % VID Output Voltage Setting (V): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 -3 +3 0.8 -4 +4 (IOUT = 0% to 100% or 100% to 0% or rated load) VIN = 5V, 1.2V VOUT 3.3V 5 % COUT = 2 x 47 F Under Voltage Lock out threshold VUVLO VIN Increasing 2.2 VIN Decreasing 2.1 V Page 6 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI PARAMETER Switching Frequency SYMBOL TEST CONDITIONS MIN FSWITCH TYP MAX 5 UNITS MHz 2.375V VIN 5.5V Continuous Output Current 0.603 <VOUT < VIN-0.5 IOUT TA = -40C to +60C 9 A NOTE: reference figures 5 and 6 for the output current derating curves Current Limit Threshold IOCP_TH Shut-Down Supply Current IS Disable Threshold VDISABLE Enable Threshold VENABLE Enable Pin Current IEN VS0-VS1, Enable Voltage Threshold VTH VS0-VS2 Pin Input Current IVSX ENABLE=0V 11 A 50 A Max voltage to ensure the converter is disabled 0.8 2.375V VIN 5.5V 1.8 5.5V < VIN 2.0 V 50 VIN = 5.5V V A Pin = Low 0.0 0.4 Pin = High 1.4 VIN VSX = GND 50 VSX = VIN 0 VSX = Open 0 A POK threshold High Percentage of VOUT Nominal 120 % POK threshold Low Percentage of VOUT Nominal 90 % POK Low Voltage IPOK = 4mA (Max Sink Current) POK High Voltage Dropout Resistance Current Balance IOUT With 2 - 4 converters in parallel, the difference between any 2 parts. VIN < 50mV; RTRACE < 10m. 0.4 V VIN V 50 m +/-10 % Page 7 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI TYPICAL PERFORMANCE CURVES Circuit of Figure 1, VIN = 5 V, VOUT = 1.2 V and TA = 25C, unless otherwise noted. Efficiency (VIN =3.3V) Efficiency (Vin = 5.0V) 95 85 Efficiency (%) Efficiency (%) 90 80 75 70 65 60 0 2 4 6 8 10 95 90 85 80 75 70 65 60 55 50 0 Load (Amperes) 2 4 6 8 10 Load (Amperes) Top to Bottom: VOUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V Page 8 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI TYPICAL PERFORMANCE CHARACTERISTICS Ripple Voltage, 5.5VIN/1.2VOUT, IOUT=9A, = 5x22F COUT Transient Response: 5VIN/1.2VOUT, 0-9A, 7A/S, COUT = 5x22F Ripple Voltage, 3.3VIN/1.2VOUT, IOUT=9A, COUT = 5x22F Transient Response: 5VIN/3.3VOUT, 0-9A, 7A/S, COUT = 5x22F Page 9 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Start up waveforms VIN=5.0V, VOUT=1.2V, CSS=15nF Start up waveforms VIN=5.0V, VOUT=3.3V, CSS=15nF Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK. Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK. Page 10 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI FUNCTIONAL BLOCK DIAGRAM POK PVIN UVLO Power Good Logic Thermal Limit Over Voltage VOUT Current Limit ROCP NC(SW) P-Drive VOUT (-) N-Drive PWM Comp (+) PGND Compensation Sawtooth Generator VSENSE Voltage Selector (-) Error Amp ENABLE SS VS0 VS1 VS2 (+) Reference Voltage selector Soft Start Bandgap Reference EAIN COMP EAOUT AVIN AGND Figure 3: Functional Block Diagram Page 11 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI FUNCTIONAL DESCRIPTION Synchronous DC-DC Step-Down PowerSoC The EN5395QI is a synchronous, pin programmable power supply with integrated power MOSFET switches and integrated inductor. The nominal input voltage range is 2.375-5.5V. The output can be set to common pre-set voltages by connecting appropriate combinations of 3 voltage selection pins to ground. The feedback control loop is a type III voltage-mode and the part uses a low-noise PWM topology. Up to 9A of output current can be drawn from this converter. The 5MHz operating frequency enables the use of small-size output capacitors. The power supply has the following protection features: * * * * Programmable over-current protection (to protect the IC from excessive load current) Thermal shutdown with hysteresis. Over-voltage protection Under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2V Additional features include: * * Soft-start circuit, limiting the in-rush current when the converter is powered up. Power good circuit indicating whether the output voltage is within 90%-120% of the programmed voltage. Output Voltage Programming The EN5395QI output voltage is programmed using a 3-pin voltage-ID or VID selector. Three binary VID pins allow the user to choose one of seven pre-set voltages. Refer to table 1 for the proper VID pin settings to program VOUT. The voltage select pins, VS0, VS1, and VS2, are pulled-up internally and so will default to a logic high, or "1", if left "open". Connecting the voltage select pin to ground will result in a logic "0". Table 1: Recommened Input Capacitos VS2* VS1* VS0* Output Voltage 0 0 0 3.3V 0 0 1 2.5V 0 1 0 1.8V 0 1 1 1.5V 1 0 0 1.25V 1 0 1 1.2V 1 1 0 0.8V 1 1 1 Reserved Page 12 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Input Capacitor Selection The EN5395QI requires between 40-80uF of input capacitance. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. Table 2. Recommended input capacitors Description MFG P/N 22uF, 10V, Murata GRM32ER71A226KE20L X7R, 1210 Taiyo Yuden LMK325B7226KM-T 47uF, 10V, Murata GRM32ER61A476KE20L X5R, 1210 Taiyo Yuden LMK325BJ476KM-T Output Capacitor Selection The EN5395QI has been optimized for use with approximately 100F of output capacitance. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these loose capacitance with frequency, temperature and bias voltage. Table 3. Recommended output capacitors Description 10uF, 10V, X7R, 1206 22uF, 6.3V, X5R, 1206 47uF, 6.3V, X5R, 1206 MFG P/N Murata GRM31CR71A106KA01L Taiyo Yuden LMK316B7106KL-T Murata GRM31CR60J226KE19L Taiyo Yuden LMK316BJ226KL-T Murata GRM31CR60J476ME19L Taiyo Yuden JMK316BJ476ML-T Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance, denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL. Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. Page 13 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI 1 Z Total = 1 1 1 + ... + + Zn Z1 Z 2 Typical ripple versus capacitor arrangement is given below (5.5VIN/1.2VOUT): Table 4. Typical Output Ripple Output Capacitor Configuration Typical Output Ripple (mVp-p) (as measured on EN5395QI Evaluation Board) 2 x 47F 20 5 x 22 F 12 Enable Operation The ENABLE pin provides a means to shut down the device, or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. When the ENABLE pin is asserted high, the device will undergo a normal soft start. Soft-Start Operation Soft start is a method to reduce in-rush current when the device is enabled. The output voltage is ramped up slowly upon start-up. The output rise time is controlled by choice of a soft-start capacitor, which is placed between the SS pin (pin 48) and the AGND pin (pin 40). Rise Time: TR = Css* 80K During start-up of the converter, the reference voltage to the error amplifier is gradually increased to its final level by an internal current source of typically 10uA. Typical soft-start rise time is 1mS to 3mS. Typical SS capacitor values are in the range of 15nF to 30 nF. Startup into Pre-Bias The EN5395QI supports startup into a pre-biased output of up to 1.5V. The output of the EN5395QI can be pre-biased with a voltage up to 1.5V when it is first enabled. POK Operation The POK signal is an open drain signal from the converter indicating the output voltage is within the specified range. The POK signal will be a logic high when the output voltage is within 90% - 120% of the programmed output voltage. If the output voltage goes outside of this range, the POK signal will be a logic low until the output voltage has returned to within this range. In the event of an over-voltage condition the POK signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. The internal POK FET is designed to tolerate up to 4mA. The pull-up resistor value should be chosen to limit the current from exceeding this value when POK is logic low. Page 14 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Over-Current Protection When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of 1.2 ms and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat. The OCP trip point is nominally set to 150% of maximum rated load. It is possible to increase the OCP trip point to 200% of the maximum rated load by connecting a 5k resistor between the ROCP pin (pin 38) and AGND (pin 40). This option is intended for startup into capacitive loads such as certain FPGAs and ASICs. Over-Voltage Protection When the output voltage exceeds 120% of the programmed output voltage, the PWM operation stops, the lower N-MOSFET is turned on and the POK signal goes low. When the output voltage drops below 95% of the programmed output voltage, normal PWM operation resumes and POK returns to its high state. Thermal Overload Protection Thermal shutdown will disable operation once the Junction temperature exceeds approximately 150C. Once the junction temperature drops by approx. 20C, the converter will re-start with a normal soft-start. Input Under-voltage Lock-out Circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter will not start-up. Circuits for hysteresis, input de-glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping. Compensation The EN5395QI is internally compensated through the use of a type 3 compensation network and is optimized for use with about 100F of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (See the section on Capacitor Selection for details on recommended capacitor types.) Voltage mode operation provides high noise immunity at light load. In some cases modifications to the compensation may be required. The EN5395QI provides access to the internal compensation network to allow for customization. For more information, contact Power Applications support. Parallel Device Operation In order to power a load that is higher than the rated 9A of the EN5395, from 2 to 4 devices can be placed in parallel for providing a single load with up to 36A of output current. Paralleling more than 1 device is accomplished by selecting a master device and tying that M/S pin to AGND. All slave devices should have their M/S pin tied to AVIN. The PWM pin from the master device is connected to all slave device PWM pins. The PWM signal is a 5 MHz drive signal and must be routed appropriately. 1. All master and slave devices should have identical placement and values of input, output and soft-start capacitors. 2. All master and slave devices should have their ENABLE pins tied together and should be operated simultaneously with a fast rising edge of 10 uSec or less, to ensure that devices start up at the same time. Startup imbalance could lead to OCP condition on first device to startup. 3. The maximum board trace resistance between any 2 devices VOUT pins should be less than 10m. 4. The maximum difference of PVIN between any 2 devices should be less than 50mV. Page 15 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Figure 4: Paralleling of two devices Figure 5: Output Current Derating Curve, VIN = 5.0V Page 16 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Figure 6: Output Current Derating Curve, VIN = 3.3V Page 17 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI LAYOUT RECOMMENDATIONS Figure 7. Layout of power and ground planes Figure 8. Use of vias connecting local and system ground. Recommendation 1: Input and output capacitors should be placed as close to the EN5395QI package as possible to reduce EMI from input and output loop currents. This reduces the physical area of the Input and Output AC current loops. Recommendation 2: Place a slit in the input/output capacitor ground plane just beyond the common connection point of the GND pins of the device as shown in figure 7. Recommendation 3: Multiple small (0.25mm) vias should be used to connect ground terminal of the Input capacitor and the output capacitor to the system ground plane as shown in figure 8. Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The diameter of the vias should be less than 0.3mm. This provides the quiet, or analog ground for the converter and also provides the path for heat dissipation from the converter. A later section of this note makes a recommendation on the PCB footprint. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. Recommendation 6: As with any switch-mode DC-DC converter, do not run sensitive signal or control lines underneath the converter package. Page 18 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES Exposed Metal on Bottom of Package Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, , and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN5395QI should be clear of any metal except for the large thermal pad. The "grayed-out" area in Figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. Figure 9 demonstrates the recommended PCB footprint for the EN5395QI. Figure 10 shows the shape and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad and the pins. Figure 9. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB Page 19 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI Figure 10. EN5395QI PCB Footprint (Top View) The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing specifications Page 20 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI PACKAGE DIMENSIONS Figure 11: EN5395QI Package Dimensions (Bottom View) Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html Page 21 02392 December 18, 2018 Rev H Data Sheet | Intel Enpirion Power Solutions: EN5395QI REVISION HISTORY Rev H Date Change(s) Nov, 2018 Changed datasheet into Intel format. WHERE TO GET MORE INFORMATION For more information about Intel(R) and Enpirion(R) PowerSoCs, visit: www.altera.com/enpirion (c) 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. Page 22 02392 December 18, 2018 Rev H