MOSEL VITELIC PRELIMINARY V8DJX232BLT/V8DJ232BLT 2M X 32 HIGH PERFORMANCE EDO/FPM MEMORY MODULE Features Description The V8DJX232BLT/V8DJ232BLT memory Module is organized as 2,097,152 x 32 bits in a 72lead single-in-line module. The 2M x 32 memory module uses 8 Mosel-Vitelic 1M x 8 DRAMs. The x32 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. 2M x 32-bit organization V8DJX232BLT EDO V8DJ232BLT FPM Utilizes High Performance 1M x 8 CMOS DRAMs Fast access times: 45, 50, 60 ns Low power dissipation CAS before RAS refresh, RAS only refresh, and Hidden refresh capability Standard 72-lead single-in-line module Single 5 V 10% Power Supply TTL Interface V8DJX232BLT/V8DJ232BLT Pin Configuration 1 36 37 72 Pin Names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS I/O1 I/O17 I/O2 I/O18 I/O3 I/O19 I/O4 I/O20 VCC NC A0 A1 A2 A3 A4 A5 A6 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC I/O5 I/O21 I/O6 I/O22 I/O7 I/O23 I/O8 I/O24 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC WE NC I/O9 I/O25 I/O10 I/O26 I/O11 I/O27 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 I/O12 I/O28 I/O13 I/O29 VCC I/O30 I/O14 I/O31 I/O15 I/O32 I/O16 NC PD1* PD2* PD3* PD4* NC VSS Name Description A0-A9 Addresses I/O1-I/O32 Data Inputs/Outputs RAS0-RAS3 Row Address Strobes CAS0-CAS3 Column Address Strobes WE Write Enable PD1-PD4 Presence Detect VCC Power Supply (5V) VSS Ground NC No Connection * Default Presence Detect is NC, Optional configurations are available. Device Usage Chart Operating Temperature Range Organization Module Type 2M x 32 SIMM 50 60 Std * * * * * 0C to 70C V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 1 Access Time (ns) Power V8DJX232BLT/V8DJ232BLT MOSEL VITELIC Part Number Information V MOSEL VITELIC MANUFACTURED 8 DJ NUMBER OF COMPONENTS MEM. FAMILY X 2 32 WIDTH DEPTH PWR. 8 BLANK = 5V B MEM. TYPE 32 LT PACKAGE CODE SPEED DEVICE FEATURES 8 50 ns 60 ns DRAM SOJ DM = 2-SIDED SIMM (TIN LEAD, LOW PROFILE) X = EDO PAGE MODE BLANK = FPM 1K REFRESH Edge Connector Pin Names Absolute Maximum Ratings* 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Ambient Temperature Under Bias................................ -10C to +80C Storage Temperature (plastic)..... -55C to +125C Voltage on any Pin Except VCC Relative to VSS .........................-1.0 V to +7.0 V Voltage on VCC Relative to VSS .....-1.0 V to +7.0 V Data Out Current .......................................... 50 mA Power Dissipation V8DJX232BLT............................................. 3.5 W V8DJ232BLT ............................................... 4.5 W VSS I/O17 I/O18 I/O19 I/O20 NC A1 A3 A5 NC I/O21 I/O22 I/O23 I/O24 NC A8 RAS3 NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 I/O1 I/O2 I/O3 I/O4 VCC A0 A2 A4 A6 I/O5 I/O6 I/O7 I/O8 A7 VCC A9 RAS2 NC *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. Capacitance* TA = 25C, f = 1.0MHz, VCC = 5 V 10%, VSS = 0 V Symbol 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 NC VSS CAS2 CAS1 RAS1 WE I/O9 I/O10 I/O11 I/O12 I/O13 VCC I/O14 I/O15 I/O16 PD1 PD3 NC 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 NC CAS0 CAS3 RAS0 NC NC I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 NC PD2 PD4 VSS V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 Parameter Min. Max. Unit CIN Input Capacitance, Address Inputs 111 pF CIN Input Capacitance, W 127 pF C(I/O) Input/Output Capacitance, I/O1-I/O32 17 pF CIN(RAS) Input Capacitance, RAS0, RAS2 32 pF CIN(CAS) Input Capacitance, CAS0-CAS3 32 pF *Note: Capacitance is samples and not 100% tested. 2 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC V8DJX232BLT/V8DJ232BLT Functional Diagram CAS0 RAS0 I/O1 I/O2 I/O3 I/O4 CAS RAS OE DQ0 DQ1 DQ2 DQ3 I/O1 I/O2 I/O3 I/O4 V53C808H WE CAS1 DQ4 DQ7 DQ6 DQ7 I/O1 I/O2 I/O3 I/O4 DQ9 DQ10 DQ11 DQ12 A0-A9 CAS2 RAS2 I/O1 I/O2 I/O3 I/O4 DQ18 DQ19 DQ20 DQ21 A0-A9 CAS3 I/O1 I/O2 I/O3 I/O4 DQ27 DQ28 DQ29 DQ30 V53C808H WE A0-A9 CAS RAS OE V53C808H DQ22 DQ23 DQ24 DQ25 A0-A9 CAS RAS OE A0-A9 WE I/O1 I/O2 I/O3 I/O4 CAS RAS OE V53C808H DQ31 DQ32 DQ33 DQ34 WE A0-A9 VCC A0-A9 VCC CX GND V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 WE I/O1 I/O2 I/O3 I/O4 V53C808H WE CAS RAS OE V53C808H DQ13 DQ14 DQ15 DQ16 A0-A9 CAS RAS OE WE I/O1 I/O2 I/O3 I/O4 V53C808H WE RAS1 V53C808H A0-A CAS RAS OE CAS RAS OE GND 3 WE RAS3 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC DC and Operating Characteristics TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified. Symbol Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) ICC1 VCC Supply Current, Operating ICC2 VCC Supply Current, TTL Standby ICC3 VCC Supply Current, RAS-Only Refresh ICC4 VCC Supply Current, EDO Page Mode Operation Access Time V8DJX232BLT Min. Typ. Max. Unit Test Conditions Notes -40 40 A VSS VIN VCC -40 40 A VSS VOUT VCC RAS, CAS at VIH 50 580 mA tRC = tRC (min.) 60 540 8 mA RAS, CAS at VIH other inputs VSS 50 580 mA tRC = tRC (min.) 2 60 540 50 340 mA Minimum cycle 1, 2 60 320 1, 2 ICC5 VCC Supply Current, Standby, Output Enabled 8 mA RAS = VIH, CAS = VIL other inputs VSS ICC6 VCC Supply Current, CMOS Standby 8 mA RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS ICC7 Self Refresh Current 1.6 mA CBR Cycle with tRAS tRASS (Min.) and CAS = VIL; WE = VCC-0.2V; A0-A8 and DIN = VCC-0.2V VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage -1 0.8 V 3 VIH Input High Voltage 2.4 VCC + 1 V 3 VOL Output Low Voltage 0.4 V IOL = 2 mA VOH Output High Voltage V IOH = -2 mA V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 5.0 2.4 4 1 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC DC and Operating Characteristics TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified. Symbol Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) ICC1 VCC Supply Current, Operating ICC2 VCC Supply Current, TTL Standby ICC3 VCC Supply Current, RAS-Only Refresh ICC4 VCC Supply Current, Fast Page Mode Operation Access Time V8DJ232BLT Min. Typ. Max. Unit Test Conditions Notes -40 40 A VSS VIN VCC -40 40 A VSS VOUT VCC RAS, CAS at VIH 50 840 mA tRC = tRC (min.) 60 800 16 mA RAS, CAS at VIH other inputs VSS 50 840 mA tRC = tRC (min.) 2 60 800 50 400 mA Minimum cycle 1, 2 60 360 1, 2 ICC5 VCC Supply Current, Standby, Output Enabled 8 mA RAS = VIH, CAS = VIL other inputs VSS ICC6 VCC Supply Current, CMOS Standby 8 mA RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage -1 0.8 V 3 VIH Input High Voltage 2.4 VCC + 1 V 3 VOL Output Low Voltage 0.4 V IOL = 4.2 mA VOH Output High Voltage V IOH = -5 mA V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 5.0 2.4 5 1 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC AC Characteristics TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V V8DJ232BLT 50 # Symbol Parameter 1 tRAS 2 60 Min. Max. Min. Max. Unit RAS Pulse Width 50 75K 60 75K ns tRC Read or Write Cycle Time 90 110 ns 3 tRP RAS Precharge Time 30 40 ns 4 tCSH CAS Hold Time 50 60 ns 5 tCAS CAS Pulse Width 14 15 ns 6 tRCD RAS to CAS Delay 19 7 tRCS Read Command Setup Time 0 0 ns 8 tASR Row Address Setup Time 0 0 ns 9 tRAH Row Address Hold Time 9 10 ns 10 tASC Column Address Setup Time 0 0 ns 11 tCAH Column Address Hold Time 7 10 ns 12 tRSH (R) RAS Hold Time (Read Cycle) 14 15 ns 13 tCRP CAS to RAS Precharge Time 5 5 ns 14 tRCH Read Command Hold Time Referenced to CAS 0 0 ns 5 15 tRRH Read Command Hold Time Referenced to RAS 0 0 ns 5 16 tROH RAS Hold Time Referenced to OE 10 10 ns 17 tOAC Access Time from OE 14 17 ns 18 tCAC Access Time from CAS 14 17 ns 6, 7 19 tRAC Access Time from RAS 50 60 ns 6, 8, 9 20 tCAA Access Time from Column Address 24 30 ns 6, 7, 10 21 tLZ CAS to Low-Z Output 0 ns 16 22 tHZ Output buffer turn-off delay time 0 ns 16 23 tAR Column Address Hold Time from RAS 40 24 tRAD RAS to Column Address 14 36 20 43 0 8 0 10 45 26 15 Notes ns 4 ns 30 ns 11 Delay Time 25 tRSH (W) RAS or CAS Hold Time in Write Cycle 14 15 ns 26 tCWL Write Command to CAS Lead Time 14 15 ns 27 tWCS Write Command Setup Time 0 0 ns 28 tWCH Write Command Hold Time 7 10 ns 29 tWP Write Pulse Width 7 10 ns V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 6 12, 13 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC AC Characteristics (cont.) V8DJ232BLT 50 # Symbol Parameter 30 tWCR Write Command Hold Time from RAS 40 45 ns 31 tRWL Write Command to RAS Lead Time 14 15 ns 32 tDS Data in Setup Time 0 0 ns 14 33 tDH Data in Hold Time 7 10 ns 14 34 tWOH Write to OE Hold Time 8 10 ns 14 35 tOED OE to Data Delay Time 8 10 ns 14 36 tRWC Read-Modify-Write Cycle Time 130 170 ns 37 tRRW Read-Modify-Write Cycle RAS Pulse Width 87 105 ns 38 tCWD CAS to WE Delay 34 40 ns 12 39 tRWD RAS to WE Delay in Read-Modify-Write Cycle 68 85 ns 12 40 tCRW CAS Pulse Width (RMW) 52 65 ns 41 tAWD Col. Address to WE Delay 42 58 ns 42 tPC Fast Page Mode Read or Write Cycle Time 28 40 ns 43 tCP CAS Precharge Time 7 8 ns 44 tCAR Column Address to RAS Setup Time 24 30 ns 45 tCAP Access Time from Column Precharge 46 tDHR Data in Hold Time Referenced to RAS 40 50 ns 47 tCSR CAS Setup Time CAS-before-RAS Refresh 10 10 ns 48 tRPC RAS to CAS Precharge Time 0 0 ns 49 tCHR CAS Hold Time CAS-before-RAS Refresh 12 15 ns 50 tPCM Fast Page Mode Read-Modify-Write Cycle Time 70 85 ns 51 tT Transition Time (Rise and Fall) 3 52 tREF Refresh Interval (1024 Cycles) V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 Min. 60 Max. Min. 27 50 16 7 Max. 34 3 Unit ns 50 ns 16 ms Notes 12 7 15 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC AC Characteristics TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V V8DJX232BLT 50 Parameter 60 # Symbol 1 tRAS RAS Pulse Width 50 2 tRC Read or Write Cycle Time 90 110 ns 3 tRP RAS Precharge Time 30 40 ns 4 tCSH CAS Hold Time 50 60 ns 5 tCAS CAS Pulse Width 9 15 ns 6 tRCD RAS to CAS Delay 19 7 tRCS Read Command Setup Time 0 0 ns 8 tASR Row Address Setup Time 0 0 ns 9 tRAH Row Address Hold Time 9 10 ns 10 tASC Column Address Setup Time 0 0 ns 11 tCAH Column Address Hold Time 7 10 ns 12 tRSH (R) RAS Hold Time (Read Cycle) 15 15 ns 13 tCRP CAS to RAS Precharge Time 5 5 ns 14 tRCH Read Command Hold Time Referenced to CAS 0 0 ns 5 15 tRRH Read Command Hold Time Referenced to RAS 0 0 ns 5 16 tCAC Access Time from CAS (EDO) 14 15 ns 6, 7, 14 17 tRAC Access Time from RAS 50 60 ns 6, 8, 9 18 tCAA Access Time from Column Address 24 30 ns 6, 7, 10 19 tLZ CAS to Low-Z Output 0 ns 16 20 tHZ CAS to High-Z Output 0 ns 16 21 tAR Column Address Hold Time from RAS 40 22 tRAD RAS to Column Address Delay Time 14 23 tRSH (W) RAS or CAS Hold Time in Write Cycle 14 15 ns 24 tCWL Write Command to CAS Lead Time 14 15 ns 25 tWCS Write Command Setup Time 0 0 ns 26 tWCH Write Command Hold Time 7 10 ns 27 tWP Write Pulse Width 7 10 ns 28 tWCR Write Command Hold Time from RAS 40 50 ns 29 tRWL Write Command to RAS Lead Time 14 15 ns 30 tDS Data in Setup Time 0 0 ns 14 31 tDH Data in Hold Time 7 10 ns 14 V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 Min. Max. Min. Max. 8 75K 36 60 20 75K 45 0 8 0 10 50 26 15 Unit Notes ns ns 4 ns 30 ns 11 12, 13 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC V8DJX232BLT 50 Parameter 60 # Symbol 32 tRWC (RMW) Read-Modify-Write Cycle Time 130 170 ns 33 tRRW (RMW) Read-Modify-Write Cycle RAS Pulse Width 87 105 ns 34 tCWD CAS to WE Delay 34 40 ns 12 35 tRWD RAS to WE Delay in Read-Modify-Write Cycle 68 85 ns 12 36 tCRW CAS Pulse Width (RMW) 52 65 ns 37 tAWD Col. Address to WE Delay 42 58 ns 38 tPC EDO Page Mode Read or Write Cycle Time 19 27 ns 39 tCP CAS Precharge Time 7 10 ns 40 tCAR Column Address to RAS Setup Time 24 30 ns 41 tCAP Access Time from Column Precharge 42 tDHR Data in Hold Time Referenced to RAS 40 50 ns 43 tCSR CAS Setup Time CAS-before-RAS Refresh 10 10 ns 44 tRPC RAS to CAS Precharge Time 0 0 ns 45 tCHR CAS Hold Time CAS-before-RAS Refresh 12 15 ns 46 tPCM EDO Page Mode Read-Modify-Write Cycle Time 70 85 ns 47 tCOH Output Hold After CAS Low 5 5 ns 48 tT Transition Time (Rise and Fall) 3 49 tREF Refresh Interval (1024 Cycles) V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 Min. Max. Min. Max. 27 50 16 9 34 3 Unit ns Notes 12 7 50 ns 15 16 ms 17 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL inputs and 100 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRCD will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 10 V8DJX232BLT/V8DJ232BLT MOSEL VITELIC Package Dimensions 1 36 37 0.050 72 4.25 [107.95] 0.33 4.25 [107.95] 3.98 [101.19] .13 [3.38] D = .12 [3.175] 0.86 [21.76] A .40 [10.16] R = .06 [1.57] .251 [6.375] .08 [2.03] .25 [6.35] 1.75 [44.45] .06 [1.57] 1.75 [44.45] Detail A Unit in inches [mm] .1 [2.54] .010 [0.25] .05 [1.27] .04 [1] Tolerances: 0.005 [0.13] V8DJX232BLT/V8DJ232BLT Rev. 0.3 May 1999 11 .25 [6.35] MOSEL VITELIC WORLDWIDE OFFICES V8DJX232BLT/V8DJ232BLT U.S.A. TAIWAN SINGAPORE IRELAND & UK 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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