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DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
219-0009; Rev 2; 4/11
General Description
The DS28E10 combines secure challenge-and-response
authentication functionality based on the FIPS 180-3
specified Secure Hash Algorithm (SHA-1) with 224 bits
of one-time programmable user EPROM in a single
chip. Once written, the memory is automatically write
protected. Additionally, each device has its own guaran-
teed unique 64-bit ROM identification number (ROM ID)
that is factory programmed into the chip. Memory writes
are performed 4 bytes at a time. A secure and low-cost
factory programming service is available to preprogram
device data, including the SHA-1 security data compo-
nents. The device communicates over the single-contact
1-Wire® bus. The communication follows the standard
1-Wire protocol with the ROM ID acting as node address
in the case of a multidevice 1-Wire network.
Applications
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Ordering Information
Features
S Dedicated Hardware-Accelerated SHA-1 Engine
for Generating SHA-1 MACs
S One Page of 28 Bytes User OTP EPROM
S Irreversible Write Protection
S Unique, Factory-Programmed 64-Bit Identification
Number
S 1-Wire Interface for Standard and Overdrive Speed
S Communicates with Host at Up to 15.4kbps at
Standard Speed or Up to 125kbps in Overdrive Mode
S Operating Range from 2.8V to 3.6V, -40NC to +85NC
S 3-Lead SOT23, 6-Lead TSOC Package
S ±6kV Human Body Model (HBM) ESD Protection
(typ) on 1-Wire and VCC Pin
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Typical Operating Circuit
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
EVALUATION KIT
AVAILABLE
IO
RPUP
3.3V
µC
Px.1 1-Wire
VCC VCC
GNDGND
DS28E10
PART TEMP RANGE PIN-PACKAGE
DS28E10R+T -40NC to +85NC3 SOT23
DS28E10P+ -40NC to +85NC6 TSOC
DS28E10P+T -40NC to +85NC6 TSOC
DS28E10
1-Wire SHA-1 Authenticator
2
ABRIDGED DATA SHEET
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
IO Voltage to GND .....................................................-0.5V, +7V
IO Sink Current ...................................................................20mA
VCC Voltage to GND ..................................................-0.5V, +7V
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(TA = -40NC to +85NC, see Note 1.)
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC PIN
Supply Voltage VCC During nonprogramming state (Note 2) 2.8 3.6 V
Standby Current ICCS VCC = 3.6V 0.5 4.0 FA
Operating Current ICCO VCC = 3.6V, reading (Note 3) 30 FA
IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Note 4) 2.8 3.6 V
1-Wire Pullup Resistance RPUP (Notes 4, 5) 0.3 2.2 kI
Input Capacitance CIO (Note 3) 50 pF
Input Load Current IL(IO pin at VPUP) (Note 3) 2 FA
Input Low Voltage VIL (Notes 4, 6, 7) 0.3 O VCC V
Input High Voltage VIH (Notes 3, 8) 0.7 O VCC V
Switching Hysteresis VHY (Notes 3, 9) 0.05 O VCC V
Output Low Voltage VOL At 4mA load (Note 10) 0.3 V
Recovery Time (Notes 4, 11) tREC Standard speed, RPUP = 2.2kI5Fs
Overdrive speed, RPUP = 2.2kI2
Rising-Edge Hold-Off Time
(Notes 3, 12) tREH Standard speed 0.5 5 Fs
Overdrive speed Not applicable (0)
Timeslot Duration (Notes 4, 13) tSLOT Standard speed 65 Fs
Overdrive speed 8
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time (Note 4) tRSTL Standard speed 480 640 Fs
Overdrive speed 48 80
Presence-Detect High Time tPDH Standard speed 15 60 Fs
Overdrive speed 2 6
Presence-Detect Low Time tPDL Standard speed 60 240 Fs
Overdrive speed 8 24
Presence-Detect Sample Time
(Notes 4, 14) tMSP Standard speed 60 75 Fs
Overdrive speed 6 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 4, 15) tW0L Standard speed 60 120 Fs
Overdrive Speed 6 16
Write-One Low Time
(Notes 4, 15) tW1L Standard speed 1 15 Fs
Overdrive speed 1 2
DS28E10
1-Wire SHA-1 Authenticator
3
ABRIDGED DATA SHEET
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40NC to +85NC, see Note 1.)
Note 1: Specifications at TA = -40NC are guaranteed by design only and not production tested.
Note 2: Refer to the full data sheet for this note.
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 4: System requirement.
Note 5: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 might be required.
Note 6: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 7: The voltage on IO needs to be less than or equal to VILMAX at all times while the master is driving IO to a logic 0 level.
Note 8: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 9: After VIH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic 0.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: Applies to a single DS28E10 attached to a 1-Wire line.
Note 12: The earliest recognition of a negative edge is possible at tREH after VIH has been reached on the preceding rising edge.
Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 14: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E10 present.
Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Note 15: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 16: d in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 17: Data retention is degraded as TA increases.
Note 18: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to
data sheet limit at operating temperature range is established by reliability testing.
Note 19: Refer to the full data sheet for this note.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: 1-Wire READ
Read Low Time
(Notes 4, 16) tRL Standard speed 5 15 - dFs
Overdrive speed 1 2 - d
Read Sample Time
(Notes 4, 16) tMSR Standard speed tRL + d15 Fs
Overdrive speed tRL + d2
EPROM
Programming Current IPROG VPP = VPP(MAX) (Note 3) Refer to the full data
sheet.
mA
Programming Time tPP ms
Programming Voltage VPP (Note 2) V
Data Retention tDR At +85NC (Notes 17, 18) 10 Years
SHA-1 Engine
SHA-1 Computation Current ICCSHA VCC = 3.6V Refer to the full data
sheet.
mA
SHA-1 Computation Time tCSHA (Note 19) ms
DS28E10
1-Wire SHA-1 Authenticator
4
ABRIDGED DATA SHEET
Detailed Description
The DS28E10 combines a 512-bit SHA-1 engine, security
data, 224 bits of one-time programmable (OTP) EPROM,
and a 64-bit ROM ID in a single chip. Data is transferred
serially through the 1-Wire protocol, which requires only
a single data lead and a ground return. In addition to its
important use as a unique data value in cryptographic
SHA-1 computations, the device’s 64-bit ROM ID can
be used to electronically identify the equipment in which
the DS28E10 is used. The ROM ID also serves as node
address in a multidrop 1-Wire network environment
where multiple devices reside on a common 1-Wire bus
and operate independently of each other.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
device. The device has six main data components: 64-bit
ROM ID, security data, challenge buffer, 28 bytes of OTP
user EPROM memory, special function registers, and a
512-bit SHA-1 engine. Figure 2 shows the hierarchical
structure of the 1-Wire protocol. The bus master must
first provide one of the seven ROM (network) function
commands: 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM, 5) Resume (communication), 6)
Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon
completion of an Overdrive-Skip ROM or Overdrive-
Match ROM command executed at standard speed,
the device enters overdrive mode where all subsequent
communication occurs at a higher speed. The protocol
required for these ROM function commands is described
in Figure 8. After a ROM function command is success-
fully executed, the memory and SHA-1 functions become
accessible and the master can provide any one of the
six available function commands. The protocol for these
commands is described in Figure 6. All data is read and
written least significant bit first.
Pin Configurations
Pin Description
VCC
IO
GND
N.C.
N.C.
N.C.
TSOC
+
5
4
6
2
3
1
DS28E10
VCC
1
3 GND
IO
DS28E10
SOT23-3
TOP VIEW
2
PIN NAME FUNCTION
SOT23 TSOC
1 2 IO 1-Wire Bus Interface. Open drain; requires external pullup resistor.
2 3 VCC Supply Pin for Operating Power
3 1 GND Ground Supply for the Device
— 4, 5, 6 N.C. Not Connected
DS28E10
1-Wire SHA-1 Authenticator
5
ABRIDGED DATA SHEET
Figure 1. Block Diagram
Figure 2. Hierarchical Structure for 1-Wire Protocol
Figure 3. 64-Bit ROM ID
Refer to the full data sheet.
DS28E10
1-Wire FUNCTION
CONTROL
IO (1-Wire)
VCC
CRC-16
GENERATOR
64-BIT
ROM ID
CHALLENGE BUFFER
512-BIT
SHA-1 ENGINE
GND
224 BITS USER
MEMORY
REGISTERS
SECURITY DATA
MEMORY AND
SHA-1 FUNCTION
CONTROL UNIT
POWER
DISTRIBUTION
AVAILABLE COMMANDS: DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM ID, RC-FLAG, OD-FLAG
1-Wire ROM
FUNCTION COMMANDS
DEVICE-SPECIFIC MEMORY
FUNCTION COMMANDS
COMMAND LEVEL:
DS28E10
MSB
8-BIT
CRC CODE 48-BIT SERIAL NUMBER
MSB MSBLSB
LSB
LSB
8-BIT FAMILY CODE
MSBLSB
DS28E10
1-Wire SHA-1 Authenticator
6
ABRIDGED DATA SHEET
64-Bit ROM ID
Each device contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a
cyclic redundancy check (CRC) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using
a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 +
X5 + X4 + 1. Additional information about the 1-Wire CRC
is available in Application Note 27: Understanding and
Using Cyclic Redundancy Checks with Maxim iButton®
Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After the
last bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the 8 bits of
the CRC returns the shift register to all 0s.
Memory
The device has three memory areas: user memory, secu-
rity data, and special function registers. User memory
and special function registers are located in a linear
address space, as shown in Figure 5. The user memory
begins at address 0000h and ends at address 0017h.
Refer to the full data sheet for additional information.
The user-writeable memory is implemented in EPROM
technology. The factory-default state of the memory is
00h. During programming, bits of the target 4-byte block
can be changed to a 1 or a 0. Once a block is written,
the entire 4-byte block becomes automatically write pro-
tected. This means it is not possible to program a block
multiple times, e.g., to change a few bits at a time.
Memory and SHA-1 Function
Commands
This section describes the commands and flowcharts
needed to use the memory and SHA-1 engine of the
device. Refer to the full data sheet for more informa-
tion.
Figure 4. 1-Wire CRC Generator
iButton is a registered trademark of Maxim Integrated
Products, Inc.
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGE
X0X1X2X3X4
POLYNOMIAL = X8 + X5 + X4 + 1
INPUT DATA
X5X6X7X8
DS28E10
1-Wire SHA-1 Authenticator
13
ABRIDGED DATA SHEET
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS28E10
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1-Wire signaling (signal types and
timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots, which
are initiated on the falling edge of sync pulses from the
bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS28E10
is open drain with an internal circuit equivalent to that
shown in Figure 7.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E10 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E10 requires a pullup resistor of
2.2kI (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction must be suspended, the bus must be left
in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16Fs
(overdrive speed) or more than 120Fs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E10 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory/SHA-1 Function Command
• Transaction/Data
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by a
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E10
is on the bus and is ready to operate. For more details,
see the 1-Wire Signaling section.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS28E10 supports. All ROM function commands are
8 bits long. A list of these commands follows (see the
flowchart in Figure 8). Under certain conditions, the ROM
function commands may not operate properly right after
power-up. See the Applications Information section for a
method to ensure proper operation.
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E10’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
Figure 7. Hardware Configuration
Rx
RPUP
IL
VPUP
BUS MASTER
OPEN-DRAIN
PORT PIN 100Ω MOSFET
Tx
Rx
Tx
DATA
DS28E10 1-Wire PORT
Rx = RECEIVE
Tx = TRANSMIT
DS28E10
1-Wire SHA-1 Authenticator
14
ABRIDGED DATA SHEET
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM ID,
allows the bus master to address a specific DS28E10 on
a multidrop bus. Only the DS28E10 that exactly matches
the 64-bit ROM ID responds to the following memory
or SHA-1 function command. All other slaves wait for a
reset pulse. This command can be used with a single or
multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their ROM ID numbers. By taking advantage of
the wired-AND property of the bus, the master can use
a process of elimination to identify the ID of all slave
devices. For each bit of the ID number, starting with the
least significant bit, the bus master issues a triplet of
time slots. On the first slot, each slave device participat-
ing in the search outputs the true value of its ID number
bit. On the second slot, each slave device participating
in the search outputs the complemented value of its ID
number bit. On the third slot, the master writes the true
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participat-
ing in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states of
the bit. By choosing which state to write, the bus master
branches in the search tree. After one complete pass,
the bus master knows the ROM ID number of a single
device. Additional passes identify the ID numbers of the
remaining devices. Refer to Application Note 187: 1-Wire
Search Algorithm for a detailed discussion, including an
example.
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
or SHA-1 functions without providing the 64-bit ROM
ID. If more than one slave is present on the bus and,
for example, a read command is issued following the
Skip ROM command, data collision occurs on the bus
as multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
Resume Command [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the memory and SHA-1 functions,
similar to a Skip ROM command. The only way to set
the RC bit is through successfully executing the Match
ROM, Search ROM, or Overdrive-Match ROM command.
Once the RC bit is set, the device can repeatedly be
accessed through the Resume command. Accessing
another device on the bus clears the RC bit, preventing
two or more devices from simultaneously responding to
the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM sets the
DS28E10 in the overdrive mode (OD = 1). All communi-
cation following this command must occur at overdrive
speed until a reset pulse of minimum 480Fs duration
resets all devices on the bus to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a
64-bit ROM ID transmitted at overdrive speed allows
the bus master to address a specific DS28E10 on a
multidrop bus and to simultaneously set it in overdrive
mode. Only the DS28E10 that exactly matches the 64-bit
number responds to the subsequent memory or SHA-1
function command. Slaves already in overdrive mode
from a previous Overdrive-Skip ROM or successful
Overdrive-Match ROM command remain in overdrive
mode. All overdrive-capable slaves return to standard
speed at the next reset pulse of minimum 480Fs dura-
tion. The Overdrive-Match ROM command can be used
with a single or multiple devices on the bus.
DS28E10
1-Wire SHA-1 Authenticator
15
ABRIDGED DATA SHEET
Figure 8a. ROM Functions Flowchart
DS28E10 Tx
PRESENCE PULSE
BUS MASTER Tx
RESET PULSE
BUS MASTER Tx ROM
FUNCTION COMMAND
DS28E10 Tx
CRC BYTE
DS28E10 Tx
FAMILY CODE
(1 BYTE)
DS28E10 Tx
SERIAL NUMBER
(6 BYTES)
RC = 0
MASTER Tx BIT 0
RC = 0 RC = 0 RC = 0
OD = 0
YY
Y
Y
Y
Y
Y
Y
33h
READ ROM
COMMAND?
N55h
MATCH ROM
COMMAND?
BIT 0 MATCH? BIT 0 MATCH?
N
N N
N N
N N
F0h
SEARCH ROM
COMMAND?
OD
RESET PULSE?
N
N
CCh
SKIP ROM
COMMAND?
N
RC = 1
MASTER Tx BIT 1
MASTER Tx BIT 63
BIT 1 MATCH?
BIT 63 MATCH?
Y
Y
RC = 1
FROM MEMORY AND SHA-1 FUNCTION
FLOWCHART (FIGURE 6)
TO MEMORY AND SHA-1 FUNCTION
FLOWCHART (FIGURE 6)
DS28E10 Tx BIT 0
DS28E10 Tx BIT 0
MASTER Tx BIT 0
BIT 1 MATCH?
BIT 63 MATCH?
DS28E10 Tx BIT 1
DS28E10 Tx BIT 1
MASTER Tx BIT 1
DS28E10 Tx BIT 63
DS28E10 Tx BIT 63
MASTER Tx BIT 63
Y
TO FIGURE 8b
TO FIGURE 8b
FROM FIGURE 8b
FROM FIGURE 8b
DS28E10
1-Wire SHA-1 Authenticator
16
ABRIDGED DATA SHEET
Figure 8b. ROM Functions Flowchart (continued)
MASTER Tx BIT 0
RC = 0; OD = 1 RC = 0; OD = 1
OD = 0
(SEE NOTE)
NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
(SEE NOTE)
(SEE NOTE)
RC = 1?
Y
Y
A5h
RESUME
COMMAND?
N
Y
3Ch
OVERDRIVE-
SKIP ROM?
N
Y
69h
OVERDRIVE-
MATCH ROM?
N
N
OD = 0
N
OD = 0
N
MASTER Tx BIT 1
MASTER Tx BIT 63
Y
Y
RC = 1
Y
BIT 0 MATCH?
MASTER Tx
RESET?
BIT 63 MATCH?
BIT 1 MATCH?
N
Y
N
Y
MASTER Tx
RESET?
N
TO FIGURE 8a
FROM FIGURE 8a
FROM FIGURE 8a
TO FIGURE 8a
DS28E10
1-Wire SHA-1 Authenticator
17
ABRIDGED DATA SHEET
1-Wire Signaling
The DS28E10 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and pres-
ence pulse, write-zero, write-one, and read-data. Except
for the presence pulse, the bus master initiates all falling
edges. The DS28E10 can communicate at two different
speeds: standard speed and overdrive speed. If not
explicitly set into the overdrive mode, the DS28E10 com-
municates at standard speed. While in overdrive mode
the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VIL. To get
from active to idle, the voltage needs to rise from 0V
past the threshold VIH. The time it takes for the voltage
to make this rise is seen in Figure 9 as ε, and its dura-
tion depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached.
Figure 9 shows the initialization sequence required to
begin any communication with the DS28E10. A reset
pulse followed by a presence pulse indicates that the
DS28E10 is ready to receive data, given the correct
ROM and memory function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for tRSTL + tF to compensate for the edge.
A tRSTL duration of 480Fs or longer exits the overdrive
mode, returning the device to standard speed. If the
DS28E10 is in overdrive mode and tRSTL is no longer
than 80Fs, the device remains in overdrive mode. If the
device is in overdrive mode and tRSTL is between 80Fs
and 480Fs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor, or in case of a DS2482-x00
driver, by active circuitry. When the threshold VIH is
crossed, the DS28E10 waits for tPDH and then transmits
a presence pulse by pulling the line low for tPDL. To
detect a presence pulse, the master must test the logical
state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of
tPDHMAX, tPDLMAX, and tRECMIN. Immediately after
tRSTH is expired, the DS28E10 is ready for data com-
munication. In a mixed population network, tRSTH should
be extended to minimum 480Fs at standard speed and
48Fs at overdrive speed to accommodate other 1-Wire
devices.
Read/Write Time Slots
Data communication with the DS28E10 takes place in
time slots, which carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 10 illustrates
the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls below
the threshold VIL, the DS28E10 starts its internal timing
generator that determines when the data line is sampled
Figure 9. Initialization Procedure: Reset and Presence Pulse
RESISTOR MASTER DS28E10
tRSTL
tRSTH
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"
VPUP
VIHMASTER
VIH
VIL
0V
ε
tF
tREC
tPDL
tPDH
tMSP
DS28E10
1-Wire SHA-1 Authenticator
18
ABRIDGED DATA SHEET
Figure 10. Read/Write Timing Diagrams
RESISTOR MASTER
RESISTOR MASTER
RESISTOR MASTER DS28E10
ε
ε
δ
VPUP
VIHMASTER
VIH
VIL
0V
tF
VPUP
VIHMASTER
VIH
VIL
0V
tF
VPUP
VIHMASTER
VIH
VIL
0V
tF
tSLOT
tW1L
tREC
tSLOT
tSLOT
tW0L
tREC
MASTER
SAMPLING
WINDOW
tRL
tMSR
WRITE-ONE TIME SLOT
WRITE-ZERO TIME SLOT
READ-DATA TIME SLOT
DS28E10
1-Wire SHA-1 Authenticator
19
ABRIDGED DATA SHEET
during a write time slot and how long data is valid during
a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VIH threshold before the write-
one low time tW1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
VIH threshold until the write-zero low time tW0LMIN is
expired. For the most reliable communication, the volt-
age on the data line should not exceed VILMAX during
the entire tW0L or tW1L window. After the VIH threshold
has been crossed, the DS28E10 needs a recovery time
tREC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below VIL until
the read low time tRL is expired. During the tRL window,
when responding with a 0, the DS28E10 starts pulling
the data line low; its internal timing generator determines
when this pulldown ends and the voltage starts rising
again. When responding with a 1, the DS28E10 does not
hold the data line low at all, and the voltage starts rising
as soon as tRL is over.
The sum of tRL + d (rise time) on one side and the internal
timing generator of the DS28E10 on the other side define
the master sampling window (tMSRMIN to tMSRMAX) in
which the master must perform a read from the data
line. For the most reliable communication, tRL should
be as short as permissible, and the master should read
close to but no later than tMSRMAX. After reading from
the data line, the master must wait until tSLOT is expired.
This guarantees sufficient recovery time tREC for the
DS28E10 to get ready for the next time slot. Note that
tREC specified herein applies only to a single DS28E10
attached to a 1-Wire line. For multidevice configurations,
tREC needs to be extended to accommodate the addi-
tional 1-Wire device input capacitance. Alternatively, an
interface that performs active pullup during the 1-Wire
recovery time, such as the DS2482-x00 1-Wire line driv-
ers, can be used.
Programming Pulse
Refer to the full data sheet for this information.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a
time slot can cause a slave device to lose synchroni-
zation with the master and, consequently, result in a
Figure 11. Programming Pulse Timing
Refer to the full data sheet for this information.
DS28E10
1-Wire SHA-1 Authenticator
20
ABRIDGED DATA SHEET
Search ROM command coming to a dead end or cause
a device-specific function command to abort. For bet-
ter performance there is a hysteresis at the low-to-high
switching threshold VIH. If a negative glitch crosses VIH
but does not go below VIH - VHY, it is not recognized
(Figure 13, Case A). The hysteresis is effective at any
1-Wire speed.
For standard speed communication only, there is a time
window specified by the rising-edge hold-off time tREH
during which glitches are ignored, even if they extend
below VIH - VHY threshold (Figure 13, Case B, tGL <
tREH). Deep voltage droops or glitches that appear late
after crossing the VIH threshold and extend beyond the
tREH window cannot be filtered out and are taken as the
beginning of a new time slot (Figure 13, Case C, tGL R
tREH). The rising-edge hold-off glitch filtering does not
apply at overdrive speed.
CRC Generation
The DS28E10 uses two different types of CRCs. One
CRC is an 8-bit type that is computed at the factory and
is stored in the most significant byte of the 64-bit ROM ID
number. The bus master can compute a CRC value from
the first 56 bits of the 64-bit ROM ID and compare it to
Figure 12. Typical Circuit for EPROM Programming
Figure 13. Noise Suppression Scheme
Refer to the full data sheet for this information.
V
PUP
V
IH
V
HY
0V
t
REH
t
GL
t
REH
t
GL
CASE A CASE CCASE B
DS28E10
1-Wire SHA-1 Authenticator
21
ABRIDGED DATA SHEET
the value read from the DS28E10 to determine if the ID
has been received error-free. The equivalent polynomial
function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC
is received in the true (noninverted) form.
The other CRC is a 16-bit type, which is used for error
detection with memory and SHA-1 commands. For
details, refer to the full data sheet.
Figure 14. CRC-16 Hardware Description and Polynomial
Refer to the full data sheet for this information.
DS28E10
1-Wire SHA-1 Authenticator
24
ABRIDGED DATA SHEET
Package Information
For the latest package outline information and land pat terns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suf fix character, but the drawing pertains to the
package regardless of RoHS status.
Applications Information
Power-Up Timing
The DS28E10 is sensitive to the power-on slew rate and
can inadvertently power up with incomplete initialization.
When this occurs, the Read ROM command does not
deliver a valid ROM ID and the memory/SHA-1 functions
do not work properly. Some production lots are more
affected than others.
For most reliable operation, it is recommended to per-
form the following steps after the VCC supply has rea-
ched its normal operating level:
1) Generate a reset/presence detect sequence (see
Figure 9).
2) Issue the Skip ROM command.
3) Issue the Write Memory command (code 55h) with
memory address 0000h.
4) Send 4 data bytes FFh.
5) Read the inverted CRC-16 and, without waiting for
tPP, send the 00h clocking byte. Do not apply the
programming pulse; instead, leave VCC at its normal
level (VCC = VPUP).
6) Generate a reset/presence detect sequence.
These steps force an internal power-on reset with com-
plete initialization. Now the device is ready to operate
and delivers a valid ROM ID and correctly executes all
ROM and memory/SHA-1 function commands. If there is
more than one DS28E10 on the 1-Wire bus, this proce-
dure initializes all of them at the same time.
Compatibility Considerations
The DS28E10 might not be the only device on the 1-Wire
bus. Therefore, one should be aware of unintended
consequences caused by issuing Skip ROM followed
by command code 55h. As it turns out, 1-Wire memories
understand command code 55h as Copy Scratchpad,
a command that is executed only if preceded by a
matching Write Scratchpad command; this precondition
is not met here. Logger iButtons of the DS1922 series
and the DS1923 understand command code 55h as
Forced Conversion. This command would definitely be
executed, but has no effect other than overwriting the
Latest Conversion Readout register with new values; this
occurs only if no mission is in progress.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
6 TSOC D6+1 21-0382 90-0321
3 SOT23 U3+2 21-0051 90-0179
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 25
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/10 Initial release —
1 10/10 Changed ESD specification from 8kV to 6kV in the Features section and added land
pattern information to the Package Information section 1, 23
2 4/11 Added the Applications Information section 24
