Pentium® III Processor for the PGA370
Socket at 500 MHz to 1 GHz
Datasheet
Product Features
The Pentium® III processor is designed for high-performance desktops and for workstations and
servers. It is binary compatible with previous Intel Architecture processors. The Pentium III processor
provides great perf orman ce for applications run ning on ad vanced oper atin g systems such as Windows*
98, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel processors—
the dynamic execution, Dual Independent Bus architecture plus Intel MMX™ technology and Internet
Streaming SIMD Extentions— bringing a new level of performance for systems buyers. The Pentium®
III processor is scaleable to two pro cessors in a multiprocessor system and extends the power of the
Pentium® II processor with performance headroom for business media, communication and internet
capabilities. Sy stems based on
Pentium® III processors also
include the latest features to
simplify system management and
lower the cost of ownership for
large and small business
environments. The Pentium® III
processor offers great performance
for today’s and tomorrow’s
applications.
FC-PGA370 Package
■A vailable in 1B GHz, 933, 866, 800EB, 733,
667, 600EB, and 533EB MHz for a
133 MHz sy st e m bu s
■Available in 900, 850, 800, 750, 700, 650,
600E, 550E, and 500E MHz for a 100 MHz
system bus
■System bus frequency at 100 MHz and
133 MHz ("E" denotes support for Advanced
Transfer Cache and Advanced system
buffering; "B" denotes support for a
133MHz system bus where both bus
frequencies are available for order per each
given core frequency; See Table 1 for a
summary of features for each line item.)
■Available in versions that incorporate
256 KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC))
■Dual Independent Bus (DIB) architecture:
Separate dedicated external System Bus and
dedicated internal high-speed cache bus
■Internet Streaming SIMD Extensions for
enhanced video, sound and 3D performance
■Binary compatible with applications running
on previous members of the Intel
microprocessor line
■Dynamic execution micro architecture
■Intel Processor Serial Number
■Power Management capabilities
■System Management mode
■Multiple low-power states
■Optimized for 32-bit applications running on
advanced 32-bit operating systems
■Flip Chip P in Grid Array (FC-PGA) packaging
techno lo gy; FC -P GA proce ss ors deliver high
performance wi th improved handling protection
and soc ketability
■Integrated high performance 16 KB instruction
and 16 KB data, nonblocking, level one cache
■256 KB Integrated Full Speed level two cache
allows for low latency on read/store operations
■Double Quad Word Wide(256bit) cache data
bus provides extremely high throughput on
read/store operations.
■8-way cache associativity provides improved
cache hit rate on reads/store operations.
■Error-correcting code for System Bus data
■Enables systems wh ich are scaleable for up to
two proces sors
October 2000
Order Number: 245264-007
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims an y express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may mak e changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatib ilities arising from future changes to them.
The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifcations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www .intel.com.
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.
Datasheet
3
Pentium
®
III Processor fo r the PGA370 Soc ket at 500 MHz to 1 GHz
Contents
1.0 Introduction.........................................................................................................................7
1.1 Terminology...........................................................................................................8
1.1.1 Package and Processor Terminology ......................................................8
1.1.2 Processor Naming Convention.................................................................9
1.2 Related Documents.............................................................................................10
2.0 Electrical Specifications....................................................................................................11
2.1 Processor System Bus and VREF........................................................................11
2.2 Clock Control and Low Power States..................................................................12
2.2.1 Normal State—State 1 ...........................................................................13
2.2.2 AutoHALT Powerdown State—State 2...................................................13
2.2.3 Stop-Grant State—State 3 .....................................................................13
2.2.4 HALT/Grant Snoop State—State 4 ........................................................14
2.2.5 Sleep State—State 5..............................................................................14
2.2.6 Deep Sleep State—State 6 ....................................................................14
2.2.7 Clock Control...................... ...... ...... ....... ...... ....... ................................ ....15
2.3 Power and Ground Pins......................................................................................15
2.3.1 Phase Lock Loop (PLL) Power...............................................................16
2.4 Decoupling Guidelines .......................................................................................16
2.4.1 Processor VCCCORE Decoupling............................................................16
2.4.2 Processor System Bus AGTL+ Decoupling............................................16
2.5 Processor System Bus Clock and Processor Clocking.......................................17
2.5.1 Mixing Processors of Differrent Frequencies .........................................17
2.6 Voltage Identification...........................................................................................17
2.7 Processor System Bus Unused Pins...................................................................19
2.8 Processor System Bus Signal Groups................................................................19
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................20
2.8.2 System Bus Frequency Select Signals (BSEL[1:0])...............................21
2.9 Test Access Port (TAP) Connection....................................................................22
2.10 Maximum Ratings................................................................................................22
2.11 Processor DC Specifications...............................................................................23
2.12 AGTL+ System Bus Specifications .....................................................................29
2.13 System Bus AC Specifications............................................................................29
2.13.1 I/O Buffer Model.....................................................................................30
3.0 Signal Quality Specifications............................................................................................38
3.1 BCLK and PICCLK Signal Quality Specifications and Measurement Guidelines38
3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................39
3.3 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................40
3.3.1 Overshoot/Undershoot Guidelines.........................................................40
3.3.2 Overshoot/Undershoot Magnitude .........................................................41
3.3.3 Overshoot/Undershoot Pulse Duration...................................................41
3.3.4 Activity Factor.........................................................................................41
3.3.5 Reading Overshoot/Undershoot Specification Tables............................42
3.3.6 Determining if a System meets the Overshoot/Undershoot
Specifications .........................................................................................43
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
4
Datasheet
3.4 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........45
3.4.1 Overshoo t/Und ersh oot Guide lines.... ....... ...... ....... ...... ...........................46
3.4.2 Ringback Specification...........................................................................46
3.4.3 Settling Limit Guideline ..........................................................................46
4.0 Thermal Specifications and Design Considerations.........................................................47
4.1 Thermal Specifications........................................................................................47
4.1.1 Thermal Diode........................................................................................48
5.0 Mecha nic al Spec ific ati ons.... ...... ....... ...... ................................ ....... ................................ .50
5.1 FC-PGA Mechanical Specifications ....................................................................50
5.2 Processo r Markings ....... ....... ...... ....... ...... ...... ................................. ...... ..............52
5.3 Processo r Signal Listin g........ ...... ....... ...... ...... ....... ................................ ....... .......52
6.0 Boxed Processor Specifications.......................................................................................64
6.1 Mechanical Specifications for the Boxed Intel® Pentium® III Processor..............64
6.1.1 Boxed Processor Thermal Cooling Solution Dimensions.......................64
6.1.2 Boxed Processor Heatsink Weight.........................................................67
6.1.3 Boxed Processor Thermal Cooling Solution Clip...................................67
6.2 Thermal Specifications........................................................................................68
6.2.1 Boxed Processor Cooling Requirements ...............................................68
6.3 Electrical Requirements for the Boxed Intel® Pentium® III Processor.................69
6.3.1 Fan Heatsink Power Supply...................................................................69
7.0 Pr oces sor Signal Desc ript ion................... ....... ...... ...... ....... ...... ....... ...... ...........................71
7.1 Alphabetical Signals Reference..........................................................................71
7.2 Signal Summaries...............................................................................................78
Datasheet
5
Pentium
®
III Processor fo r the PGA370 Soc ket at 500 MHz to 1 GHz
List of Figures
1 Second Level (L2) Cache Implementation ...........................................................7
2 AGTL+ Bus Topology in a Uniprocessor Configuration ......................................12
3 AGTL+ Bus Topology in a Dual-Processor Configuration...................................12
4 Stop Clock State Mac hine........ ................................ ....... ................................ ....12
5 Processor VccCMOS Package Routing..............................................................16
6 BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........21
7 BCLK, PICCLK, and TCK Generic Clock Waveform...........................................35
8 System Bus Valid Delay Timings ........................................................................35
9 System Bus Setup and Hold Timings..................................................................35
10 System Bus Reset and Configuration Timings....................................................36
11 Power-On Reset and Configuration Timings.......................................................36
12 Test Timings (TAP Connection) ..........................................................................37
13 Test Reset Timings .............................................................................................37
14 BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................39
15 Low to High AGTL+ Receiver Ringback Tolerance.............................................40
16 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform.......................45
17 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1 ..................45
18 Processor Functional Die Layout for CPUIDs up to and including 0683h...........48
19 Package Dimensions...........................................................................................50
20 Top Side Processor Markings.............................................................................52
21 Intel® Pentium® III Processor Pinout..................................................................53
22 Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket.........64
23 Space Requirements for the Boxed Processor to 850MHz.................................65
24 Space Requirements for the Boxed Processor from 866 to 933MHz..................65
25 Space Requirements for the Boxed Processor at 1 GHz....................................66
26 Dimensions of Mechanical Step Feature in Heatsink Base.................................66
27 Dimensions of Notches in Heatsink Base ..........................................................67
28 Clip Keepout Requirements for the PGA370 (Top View)....................................68
29 Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor
Fan Heatsinks in the PGA370 Socket.................................................................69
30 Boxed Processor Fan Heatsink Power Cable Connector Description.................70
31 Motherboard Power Header Placement Relative to the Boxed
Intel® Pentium® III Processor.............................................................................70
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6
Datasheet
List of Tables
1 Processo r Identifi catio n............................................... ....... ................................ ...9
2 Voltage Identification Definition ..........................................................................18
3 System Bus Signal Groups ................................................................................20
4 Frequency Select Truth Table for BSEL[1:0] ......................................................21
5 Absolute Maximum Ratings ................................................................................22
6 Voltage and Current Specifications.....................................................................24
7 AGTL+ Signal Groups DC Specifications ...........................................................28
8 Non-AGTL+ Signal Group DC Specifications .....................................................28
9 Processo r AGTL+ Bus Spe cific at ion s ..... ...... ....... ...... ....... ...... ....... ...... ..............29
10 System Bus AC Specifications (Clock) ...............................................................30
11 Valid System Bus to Core F requency Ratios .....................................................31
12 System Bus AC Specifications (AGTL+ Signal Group).......................................32
13 System Bus AC Specifications (CMOS Signal Group) .......................................32
14 System Bus AC Specifications (Reset Conditions) ............................................33
15 System Bus AC Specifications (APIC Clock and APIC I/O)................................33
16 System Bus AC Specifications (TAP Connection)..............................................34
17 BCLK/PICCLK Signal Quality Specifications for Simulation
at the Pr ocessor Pins..........................................................................................38
18 AGTL+ Signal Groups Ringback Tolerance Specifications
at the Pr ocessor Pins..........................................................................................39
19 Examp le Platfo rm Information.................. ................................ ....... ....................42
20 100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance
at Processor Pins................................................................................................43
21 133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance ....................44
22 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance
at Processor Pins................................................................................................44
23 Signal Ringback Specifications for Non-AGTL+ Signal Simulation
at the Pr ocessor Pins .........................................................................................46
24 Intel® Pentium® III Processor for the PGA370 Socket Thermal Design Power .47
25 Thermal Diode Parameters.................................................................................49
26 Thermal Diode Interface......................................................................................49
27 Intel® Pentium® III Processor Package Dimensions..........................................51
28 Proces so r Die Loadin g Parame ters ............... ....... ................................ ....... .......51
29 Signal Listing in Order by Signal Name ..............................................................54
30 Signal Listing in Order by Pin Number................................................................59
31 Boxed Processor Fan Heatsink Spatial Dimensions...........................................66
32 Fan Heatsi nk Power and Signal Specifications...................................................70
33 Signal Description...............................................................................................71
34 Output Signals.....................................................................................................78
35 Input Signals .......................................................................................................79
36 Input/Output Signals (Single Driver)....................................................................80
37 Input/Output Signals (Multiple Driver).................................................................80
Datasheet
7
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.0 Introduction
The Intel® Pentium® III processor for the PGA370 socket is the next member of the P6 family, in
the Intel IA-32 processor line and hereafter will be referred to as the “Pentium III processor”, or
simply “the processor”. The processor uses the same core and offers the same performance as the
Intel® Pentium® III processor for the SC2 42 connector, bu t utilizes a new package technology
called flip-chip pin grid array, or FC-PGA. This package utilizes the same 370-pin zero insertion
force socket (PGA370) used by the Intel®CeleronTM processor. Thermal solutions are attached
directly to the back of the processor core package without the use of a thermal plate or heat
spreader.
The Pentium III processor, like its predecessors in the P6 family of processors, implements a
Dynamic Execution microarchitecture—a unique combination of multip le branch prediction, data
flow analysis, and speculative execution. This enables these processors to deliver higher
performance than the Intel Pentium processor, while maintaining binary com patibility with all
previous Intel Architecture processors. The processor also executes Intel® MMXTM technology
instructions for enhanced media and communication performance just as it’s predecessor, the
Intel Pentium III processor. Additionally, Pentium III processor executes Streaming SIMD (single-
instruction, m ultiple data) Extensions for enhanced floating point and 3-D application
performance. The concept of processor identification, via CPUID, is extended in the processor
family with the addition of a processor serial num ber. Refer to the Intel® Processor Serial Number
application note for more detailed information. The processor utilizes multiple low-power states
such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times.
The processor includes an integrated on-die, 256 KB, 8-way set associative level-two (L2) cache.
The L2 cache implemen ts the new Advanced T ransfer Cache Architecture with a 256-bi t wide bus.
The processor also includes a 16 KB level one (L1) instruction cache and 16 KB L1 data cache.
These cache arrays run at the full speed of the processor core. As with the Intel Pentium III
processor for the SC242 connector, the Pentium III processor for the PGA370 socket has a
dedicated L2 cache b us, thus maintaining the dual ind epend ent b us architecture to d eliver h igh bus
bandwidth and performance (see Figure 1). Memory is cacheable for 64 GB of addressable
memory space, allowing significant headroom for desktop systems. Refer to the Specification
Update document for this processor to determine the cacheability and cache configuration options
for a specific processor. The Specification Update document can be requested at your nearest Intel
sales office.
The processor utilizes the same multiprocessing system bus technology as the Pentium II processor .
This allows for a higher level of performance for both uni-processor and two-way multiprocessor
systems. The system bus uses a variant of GTL+ signaling technology called Assisted Gunning
Transceiver Logic (AGTL+) signaling technology.
Figure 1. Second Level (L2) Cache Implementation
Processor
Core Tag L2 Processor
Core
L2
Intel
®
Pentium
®
III SECC2 Processor Intel
®
Pentium
®
III FC-PGA Processor
8
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.1 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low sign al. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a bin ary sequ ence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0] # = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
chipset components), and other bus agents.
1.1.1 Package and Processor Terminology
The following terms are used often in this document and are explained here for clarification:
•Pentium® III processo r - The entire product including all internal components.
•PGA370 socket - 370-pin Zero Insertion Force (ZIF) socket which a FC-PGA or PPGA
packaged processor plugs into.
•FC-PGA - Flip Chip Pin Grid Array. The package technology used on Pentium III processors
for the PGA370 socket.
•Advanced Transfer Cache (ATC) - New L2 cache architecture unique to the 0.18 micron
Pentium III processors. ATC consists of microarchitectural improv ements that provide a higher
data bandwidth interface into the processor core that is completely scaleable with the
processor core frequency.
•Keep-out zone - The area on or near a FC-PGA packaged processor that system designs can
not utilize.
•Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.
•OLGA - Organic Land Grid Array. The package technology for the core used in S.E.C.C. 2
processors that permits attachment of the heatsink directly to the die.
•PPGA - Plastic Pin Grid Array. The package technology used for Intel® CeleronTM
processors that utilize the PGA370 socket.
•Processor - For this document, the term processor is the generic form of the Pentium III
processor for the PGA370 socket in the FC-PGA package.
•Processor core - The processor’s execution engine.
•S.E.C.C. - The processor package technology called “Single Edge Contact Cartridge”. Used
with Intel® Pentium® II processors.
•S.E.C.C. 2 - The follow-on to S.E.C.C. processor package technology. This differs from its
predecessor in that it has no extended thermal plate, thus reducing thermal resistance. Used
with Intel® Pentium® III processors and latest versions of the Intel® Pentium® II processor.
•SC242 - The 242-contact slot connector (previously referred to as slot 1 connector) that the
S.E.C.C. and S.E.C.C. 2 plug into, just as the Intel® Pentium® Pro processor uses socket 8.
The cache and L2 cache are an industry designated names.
Datasheet
9
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.1.2 Processor Naming Convention
A letter(s) is added to certain processors (e.g., 600EB MHz) when the core freqnency alone may
not uniquely identify the processor. Below is a summary of what each letter means as well as a
table listing all the available Pentium III processors for the PGA370 socket.
“B” — 1 33 MHz System Bus Frequency
“E” — Processor with "Advanced Transfer Cache" (CPUID 068xh and greater)
NOTES:
1. Refer to the
Pentium
®
III Processor Specification Update
for the exact CPUID for each processor.
2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.
With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same
frequency as the processor core and has enhanced buffering.
Table 1. Processor Identification
Processor Core Frequency
(MHz)
System Bus
Frequency
(MHz)
L2 Cache Size
(Kbytes) L2 Cache
Type2CPUID1
500E 500 100 256 ATC 068xh
533EB 533 133 256 ATC 068xh
550E 550 100 256 ATC 068xh
600E 600 100 256 ATC 068xh
600EB 600 133 256 ATC 068xh
650 650 100 256 ATC 068xh
667 667 133 256 ATC 068xh
700 700 100 256 ATC 068xh
733 733 133 256 ATC 068xh
750 750 100 256 ATC 068xh
800 800 100 256 ATC 068xh
800EB 800 133 256 ATC 068xh
850 850 100 256 ATC 068xh
866 866 133 256 ATC 068xh
900 900 100 256 ATC 068xh
933 933 133 256 ATC 068xh
1B GHz 1000 133 256 ATC 068xh
10
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1.2 Related Documents
The reader of this specification should also be familiar with material and concepts presented in the
following documents 1,2:
1. Unless otherwise noted , this reference material can be found on the Intel Developer’s Website
located at http://developer.intel.com.
2. For a complete listing of Intel® Pentium® III processor reference material, please refer to the
Intel Developer’ s Website at http://developer.intel.com/design/PentiumIII/.
3. This material is available throu g h an Intel field sales representative.
Document Intel Order Number
AP-485,
Intel
®
Processor Identification and the CPUID Instruction
241618
AP-585,
Pentium
®
II Processor GTL+ Guidelines
243330
AP-589,
Design for EMI
243334
AP-905,
Pentium
®
III Processor Thermal Design Guidelines
245087
AP-907,
Pentium
®
III Processor Power Distribution Guidelines
245085
AP-909, Intel
®
Processor Serial Number
245125
Intel
®
Architecture Software Deve loper's Manual
243193
Volume I: Basic Architecture 243190
Volume II: Instruction Set Reference 243191
Volume III: System Programming Guide 243192
P6 Family of Processors Hardware Developer’s Manual
244001
IA-32 Processors and Related Products 1999 Databook 243565
Pentium
®
II Processor Developer’s Manual
243502
Pentium® III Processor Datasheet for SECC2 244452
Pentium® III Processor Datasheet for PGA370 245264
Pentium® III Processor Specification Update 244453
Intel
®
Celeron
TM
Processor Datasheet
243658
Intel
®
Celeron
TM
Processor Specificiation Update
243748
370-Pin Socket (PGA370) Design Guidelines
244410
PGA370 Heat Sink Cooling in MicroATX Chassis 245025
Intel® 810E Chipset Platform Design Guide 290675
Intel® 820 Chipset Platform Design Guide 290631
Intel® 840 Chipset Platform Design Guide 298021
CK98 Clock Synthesizer/Driver Design Guidelines 245338
Intel
®
810E Chipset Clock Synthesizer/Driver Specification
3
VRM 8.4 DC-DC Converter Design Guidelines
245335
Pentium III Processor for the PGA370 Socket I/O Buf fer Models, XTK/XNS*
Format 3
Pentium
®
Pro Pr ocessor BIOS Writer’s Guide 3
Extensions to the Pentium
®
Pro Processor BIOS Writer’s Guide 3
Pentium III Thermal/Mechanical Solution Functional Guidelines 245241
Datasheet
11
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.0 Electrical Specifications
2.1 Processor System Bus and VREF
The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Intel® Pentium® Pro pro cessor system bus sp ecificatio n is similar to the GTL specification, but
was enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Intel® Pentium® II
Processor Developer’s Manual.
Current P6 family processors vary from the Intel Pentium Pro processor in their output buffer
implementation. The buff ers that drive the system bus signals on the Intel®CeleronTM, Pentium II,
and Pentium III processors are actively driven to VCCCORE for one clock cycle after the low to high
transition to improve rise times. These signals should still be considered open-drain and require
termination to a supply that provides the high signal level. Because this specification is different
from the standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and
other documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both
be used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by
the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by the motherboard
to the PGA370 socket for the processor core. Local VREF copies should also be generated on the
motherboard for all other d evices on the AGTL+ system bus. T ermination (usually a r esisto r at each
end of the signal trace) is used to pull the bus up to the high vo ltage level and to control reflections
on the transmission line. The processor contains on-die termination resistors that provide
termination for one end of the AGTL+ bus, except for RESET#. These specifications assume
another resistor at the end of each signal trace to ensure adequate signal quality for the AGTL+
signals and provide backwards compatibility for the Intel Celeron processor; see Table 9 for the
bus termination vo ltage specifications for AGTL+. Refer to the Intel®Pentium®II Processor
Developer’s Manual for the AGTL+ bus specification. Solutions exist for single-ended termination
as well, though this implementation change s system design and eliminate backwards compatibility
for Intel Celeron processors in the PPGA package. Single-ended termination designs must still
provide an AGTL+ termination resistor on the motherboard for the RESET# signal. Figure 2 is a
schematic representation of the AGTL+ bus topology for the Pentium III processo rs in the PGA370
socket. Figure 3 is a schematic representation of the AGTL+ bus topoplogy in a dual-processor
configuration with Pentium III processors in the PGA370 socket.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus including trace len gths is highly recommended when d esigning a system with a heavily
loaded AGTL+ bus, especially for systems using a single set of termination resistors (i.e., those o n
the processor die). Such designs will not match the solution space allowed for by installation of
termination resis tors on the b a seboard.
12
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.2 Clock Control and Low Power States
Processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 4 for a visual representation of the processor low power states.
Figure 2. AGTL+ Bus Topology in a Uniprocesso r Configuration
Figure 3. AGTL+ Bus Topology in a Dual-Processor Conf iguration
Processor Chipset
Processor Chipset Processor
Figure 4. Stop Clock State Machine
PCB757a
2. Auto HALT Power Down S tate
BCLK running.
Snoops and interrupts allowed.
HALT
I
ns
t
ruc
ti
on an
d
HALT B us Cycle Generated
IN IT# , B IN IT# , INT R ,
SMI#, RESET#
1. No rmal State
Normal execution.
STPCLK#
Asserted STPCLK#
De-asserted
3. Stop G rant State
BCLK running.
Snoops and interrupts allowed.
SLP#
Asserted SLP#
De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK
Input
Stopped
BCLK
Input
Restarted
6. Deep S leep S tate
BCLK stopped.
No snoops or interrupts allowed.
4. HA LT/Grant Snoop State
BCLK running.
Service snoops to caches.
Snoop Event O ccurs
Snoop Event Serviced
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK# Asserted
STP CLK # De-asserted
and S top-Grant State
entered from
AutoHALT
, NMI
Datasheet
13
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide.
2.2.1 Normal State—State 1
This is the normal operating state for the processor.
2.2.2 AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor transitions to the Normal state upon the occurrence of SMI #, INIT#, or LINT[1:0] (NMI,
INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT
state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT
state.
2.2.3 Stop-Grant Sta te— Stat e 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for min im um po wer drawn by t he t erm ination resist o rs in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# and FLUSH# are not serviced during the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant
state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the
system bus (see S ect ion 2.2.4). A transition to the Sleep state (see Section 2.2.5) occurs with th e
assertion of the SLP# signal.
While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] are latched by the processor, and only
serviced when the processor returns to the Normal state. Only one occurrence of each event is
recognized and serviced upon return to the Normal state.
14
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.2.4 H ALT/Grant Snoop State—State 4
The processor responds to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The process or stays in this state until the snoop on the system bus has been serviced
(whether by the processor or another agent on the system bus). After the snoop is serviced, the
processor returns to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5 Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.
Snoop event s that occur w hile in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions o f signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has retu rned to Stop-Grant state will result in unp redictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin speci fication, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
While in the Sleep state, the pro cessor is capable of entering its lowest po wer state, the Deep Sleep
state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6 D eep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK inpu t be held low during the Deep Sleep S tate. Stopping
of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable b ehav ior.
Datasheet
15
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.2.7 Clock Control
BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states , the p rocessor will process a system bus snoop. The proces sor does
not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance
into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not st opped. During the
Deep Sleep state, the intern al clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be r emoved d urin g the Sleep or Deep Sleep states. When tran sitioning fro m th e Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3 Power and Ground Pins
The operating voltage of the Pentium III processor for the PGA370 socket is the same for the core
and the L2 cache; VCCCORE. There are four pins defined on the package for voltage identification
(VID). These pins specify the voltage required by the processor core. These have been added to
cleanly support voltage specification variations on current and future processors.
For clean on-chip power and voltage reference distribution, the Pentium III processors in the
FC-PGA package have 75 VCCCORE, 8 VREF, 15 VTT, and 77 VSS (ground) inputs. VCCCORE
inputs supply the processor core, including the on-die L2 cache. VTT inputs (1.5V) are used to
provide an AGTL+ termination voltage to the processor, and the VREF inputs are used as th e
AGTL+ reference voltage for the processor. Note that not all VTT inputs must be connected to the
VTT supply. Refer to Section 5.3 for more details.
On the motherboar d, all VCCCORE pins must be conn ected to a vol tage island (an isla nd is a porti on
of a power plane that has been divided, or an entire plane). In addition, the motherboard must
implement the VTT pins as a voltage island or large trace. Similarly, all GND pins must be
connected to a system ground plane.
Three additional power related pins exist on a processors utilizing the PGA370 socket. They are
VCC1.5, VCC2.5 and VCCCMOS.
The VCCCMOS pin provides the CMOS voltage for the pull-up resistors required on the system
platform. A 2.5V source must be provided to the VCC2.5 pin and a 1.5V source must be provided
to the VCC1.5 pin. The source for VCC1.5 mu st be the same as the one supplying VTT. Th e processor
routes the compatible CMOS voltage source (1.5V or 2.5V) through the package and out to the
VCCCMOS output pin. Processors based on 0.25 micron technology (e.g., the Intel Celeron
processor) u tilize 2.5V C M OS buffers. Processors based on 0.18 micron technology (e.g., the
Pentium III process or for the PGA370 socket) utilize 1.5V CMOS buffers. The signal VCOREDET
can be used by hardware on the motherboard to d etect which CMOS voltage the processor requires.
A VCOREDET connected to VSS within the processor indicates a 1.5V requirement on V CCCMOS.
Refer to Figure 5.
Each power signal must meet the specifications stated in Table 6 on page 24.
16
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.3.1 Phase Lock Loop (PLL) Power
It is highly critical that ph ase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source fo r the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform desi gn guide for the recommended filter specificatio ns.
2.4 Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remain s within the specifications listed in Table 6. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage oversho ot ). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoup ling capacitors on all power planes for the processor.
2.4.1 Processor VCCCORE Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 6) while maintaining the required tolerances (also defined in Table 6). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
2.4.2 Processor System Bus AGTL+ Decoupling
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ bus operation. See the AGTL+ buffer specification in the Intel®Pentium®II
Pr ocessor Developer's Manual for more information. Also, refer to the ap propriate platform de sign
guide for recommended capacitor component placement.
Figure 5. Processor VCCCMOS Package Routing
Intel
®
Pentium
®
III
Processor 0.1 uF
2.5V Supply
2.5V
1.5V Supply
1.5V
VCC
CMOS
*ICH or
Other Logic
CMOS
Pullups
CMOS Signals
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel
®
Pentium
®
III processor
for the PGA370 socket.
Datasheet
17
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.5 Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+
system bus timing parameters are specified with respect to the rising edge of the BCLK input. See
the P6 Family of P rocessors Hardware Developer's Manual for further details.
2.5.1 Mixing Processors of Differrent Frequencies
In two-way MP (multi-processor) systems, mixing processors of different internal clock
frequencies is not supported and has not been validated. Pentium III processors do not support a
variable multip lier ratio; therefore, adjusting the ratio setting to a common clock frequency is not
valid. However, mixing processors of the same frequency but of different steppings is supported.
Details on support for mixed steppings is provided in the Pentium®
III
Processor Specification
Update.
Note: Not all Pentium III processors for the PGA370 socket are validated for use in dual processor (DP)
systems. Refer to the Pentium®
III
Processor Specification Update to determine which processors
are DP capable.
2.6 Voltage Identification
There are four voltag e identification pins on the PGA370 socket. These p ins can b e used to suppo rt
automatic selection of VCCCORE voltages. These pins are not signals, but are either an open circuit
or a short circuit to VSS on the processor. The c ombi n ati o n of open s and sh orts de fines the vo ltag e
required by the processor core. The VID pins are needed to cleanly support voltage specification
variations on current and future processors. VID[3:0] are defined in Table 2. A ‘1’ in this table
refers to an open pin and a ‘0’ refers to a short to ground. The voltage regulator or VRM must
supply the voltage that is requested or disable itself.
To ensure a system is ready for current and futu re processors, the range of values in bold in Table 2
should be supp orted. A sm aller range will risk the ability of the system to migrate to a higher
performance processor and/o r maintain compatibility with current processo rs.
18
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on baseboard.
3. To ensure a system is ready for the Intel
®
Pentium
®
III and Intel
®
Celeron
TM
processors, the values in BOLD
in Table 2 should be supported.
Note that the ‘1111’ (all opens) ID can be used to detect the absence of a processor core in a given
socket as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see Section 7. 0).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[3:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-
DC converter, this can be accomplished by using the in put voltage to the converter f or the VID line
pull-ups. A resistor of greater than o r equal to 10 kΩ may be used to connect the VID sign als to the
converter input. Note that no changes have been made to the physical connector or pin definitions
between the Intel-enabled VRM 8.2 and VRM 8.4 specifications. Intel requires that designs
utilize VRM 8.4 specifications to meet the Pentium III processor requirements.
Table 2. Voltage Identification Definition 1, 2
VID3 VID2 VID1 VID0 VccCORE
1111 1.30
1110 1.35
1101 1.40
1100 1.45
1011 1.50
1010 1.55
1001 1.603
1000 1.653
0111 1.703
0110 1.753
0101 1.80 3
0100 1.85 3
0011 1.90 3
0010 1.95 3
0001 2.00 3
0000 2.05 3
1111 No Core
Datasheet
19
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.7 Processor System Bus Unused Pins
All RESERVED pins must remain unco nnected unl ess speci fically n oted. Con nection o f these pi ns
to VCCCORE, VREF, VSS, VTT, o r to any other sign al (including each other ) can result in component
malfunction or incompatibility with future processors. See Section 5.3 for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
VCCCMOS even when the APIC will not be used. A separate pull-up resistor must be p rovided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (VIH) and logic low (VIL) requirements are met. See Table 8 for DC
specifications of non-AGTL+ signals.
Unused AGTL+ inputs must be properly terminated to VTT on PGA370 socket motherboards
which supp ort the Intel C eleron and the Pentium III processors. For designs that intend to only
support the Pentium III processo r, unused AGTL+ inputs will be terminated by the processor’s on-
die termination resistors and thus do not need to be terminated on the motherboard. However,
RESET# must always be terminated on the motherboard as the Pentium III processor for the
PGA370 socket does not provide on-die termination of this AGTL+ input.
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
VCCCMOS and meet VIH requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. Wh en tying any signal to power or ground, a resistor will also allow for system testability.
2.8 Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Pentium III processor for the
PGA370 so cket includes on-die termination. Motherboard designs that also support
Intel Celeron processors in the PPGA package will need to provide AGTL + termination on
the system motherboard as well. Plat form designs that suppo rt dual processor configurations
will need to provide AGTL+ termination, via a termination package, in any socket not
populated with a processor.
AGTL+ input si gnals have di ff erenti al i nput buffers which u se V REF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this docum ent, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving . Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when drivin g.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) are only 1.5 V tolerant and must be pulled up to VCCCMOS. The CMOS, APIC, and
TAP outputs are open drain and must be pulled high to VCCCMOS. This ensures correct operation
for current Intel Pentium III and Intel Celeron processors.
The groups an d the sign als con tain ed within each gr oup are shown in Table 3. Refer to Section 7.0
for a description of these signals.
20
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for VccCMOS (1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V t olerant.
5. VCCCORE is the power supply for the processor core and is described in Section 2.6.
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the motherboard.
VSS is system ground.
VCC1.5, VCC2.5, VccCMOS are described in Section 2.3.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the
Pentium
®
III Processor Specification Update
for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pulldown resistor value.
2.8.1 Asynchrono us vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP
signals are synchronous to TCK.
Table 3. System Bus Signal Groups 1
Group Name Signals
AGTL+ Input BPRI#, BR1#7, DE F E R#, RESE T # 6, RS[2:0]#, RSP#, TRDY#
AGTL+ Output PRDY#
AGTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#2, D[63:0]#, DBSY #, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input3A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input4PWRGOOD
CMOS Output3FERR#, IERR#, THERMTRIP#
System Bus
Clock4BCLK
APIC Clock4PICCLK
APIC I/ O 3PICD[1:0]
TAP Input3TCK, TDI, TMS, TRST#
TAP O utput 3TDO
Power/Other5BSEL[1:0], CLKREF, CPUPRES #, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], V CC1.5, VCC2.5, VCCCMOS,
VCCCORE, VREF, VSS, VTT, Reserved
Datasheet
21
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.8.2 System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency. Table 2.9 defines the possible
combinations of the signals and the frequency associated with each co mbin ation. The frequency is
determined by the processor( s), chipset, and clock synthesizer. All system bus agents must operate
at the same frequency. The Pentium III processor for the PGA370 socket operates at 100 MHz
or 133 MHz system bus frequency; 66 MHz system bus operation is not supported. Individual
processors will only o perate at their specified front side bus (FSB) frequency, either 100 MHz o r
133 MHz, not both.
On motherboards th at support op eration at either 1 00 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the moth erbo ard i f on l y 1 33 MHz operatio n i s s upp ort ed (t hu s f orci n g t he RES ET# si g nal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in Fi gure 6. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. S ome chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implement ation details.
Figure 6. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
Processor
BSEL0 BSEL1
Chipset
Clock Driver
1 K
Ω
1 K
Ω
3.3V 3.3V
10 K
Ω
Note 1
10 K
Ω
Note 2
10 K
Ω
Note 2
Table 4. Frequency Select Truth Table for BSEL[1:0]
BSEL1 BSEL0 Frequency
0 0 66 MHz (unsupported)
0 1 100 MHz
1 0 Reserved
1 1 133 MHz
22
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.9 Test Access Port (TAP) Connect ion
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be the first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect the rest of the chain
unless one of the other components is capable of accepting a 1.5V input. Similar considerations
must be made for TCK, TMS, and TRST# signals.
In a two-way MP system design, be cautious when including an empty PGA370 socket in the scan
chain. All sockets in the scan chain must have a processor installed to complete the chain or the
system must support a method to bypass the empty socket; PGA370 termination packages should
not connect TDI to TDO in order to avoid placing the TDO pull-up resistor in parallel.
2.10 Maximum Ratings
Table 5 contains processor stress ratings only. Functional operation at the absolute maximum and
minimum is not implied nor guaranteed. The processor should not receive a clock while subjected
to these conditions. Functional operating conditions are given in the AC and DC tables in
Section 2 .11 through Section 2.13. Extended exposure to the maxim um ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist damage from
static electric discharge, on e should always take precautions to avoid high static voltag es or electric
fields.
NOTES:
1. Input voltage can never exceed VSS + 2.18 volts.
2. Input voltage can never go below VTT - 2.18 volts.
3. Par amet er applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups
only.
4. Par amet er applies to CMOS signals BCLK, PICCLK, and PWRGOOD only.
Table 5. Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
TSTORAGE Processor storage temperature –40 85 °C
VCCCORE and
VTT Processor core voltage and termination
supply voltage with respect to VSS –0.5 2.1 V
VinAGTL AGTL+ buffer input voltage VTT - 2. 18 2.18 V 1, 2
VinCMOS1.5 CMOS buffer DC input voltage with respect
to VSS VTT - 2.18 2.18 V 1, 2, 3
VinCMOS2.5 CMOS buffer DC input voltage with respect
to VSS -0.58 3.18 V 4
IVID Max VID pin current 5 mA
ICPUPRES# Max CPUPRES# pin current 5 mA
Datasheet
23
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.11 Processor DC Specifications
The processor DC specifications in this section are defined at the PGA370 socket pins (bottom side
of the motherboard). See Section 7.0 for the processor signal descriptions and Section 5. 3 for the
signal listings.
Most of the signals on the processor system bus are in the AGTL+ signal group. These signals are
specified to be terminated to 1.5V. The DC specifications for these signals are listed in Table 7 on
page 28.
To allow connection with other devices, the clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 8 on
page 28.
Table 6 through Table 9 li st the DC specifications for the Pentium III processor for the PGA370
socket. Specifications are valid only while meeting specifications for junction temperature, clock
frequency, and input voltages. Care should be taken to read all notes associated with each
parameter.
24
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 6. Voltage and Current Specifications 1, 2 (Sheet 1 of 3)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
VCCCORE VCC for Process or Core
500E
MHz
0x681 1.60
V
3,4
0x683 1.60 3,4
0x686 n/a
533EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 n/a
550E
MHz
0x681 1.60 3,4
0x683 1.65 3,4
0x686 1.70 3,4
600E
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
600EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
650
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
667
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
700
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
733
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
750
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
800
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
800EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
Datasheet
25
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
VCCCORE VCC for Processor Core
850
MHz
0x681 1.65
V
3,4
0x683 1.65 3,4
0x686 1.70 3,4
866
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
900
MHz 0x686 1.70 3,4
933
MHz 0x683 1.65 3,4
0x686 1.70 3,4
1B
GHz
0x683 1.70 3,4
0x686 1.70 3,4
0x686 1.76 3,4, 20
VTT, VCC1.5 Static AGTL+ bus
termination voltage 1.455 1.50 1.545 V 1.5 ±3%, 5, 16
VTT, VCC1.5 Tr ansient AGTL+ bus
termination voltage 1.365 1.50 1.635 V 1.5 ±9%, 5
VREF AGTL+ inp ut reference
voltage -2% 2/3
VTT +2% V ±2%, 7
VCLKREF CLK REF input
reference voltage 1.169 1.25 1.331 V ±6.5%, 15
Baseboard
VCCCORE
Tolerance,
Static
Processor core voltage
static tolerance level at
the PGA370 socket
pins
–0.080
0.001 0.040
0.100 V6
20, 21
Baseboard
VCCCORE
Tolerance,
Transient
Processor core voltage
transient tolerance level
at the PGA370 socket
pins
–0.130
–0.110
0.025
0.080
0.080
0.130 V6
19
20, 21
ICCCORE ICC for processor core
500E MHz
533EB MHz
550E MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
850 MHz
866 MHz
900 MHz
933 MHz
1B GHz
1B GHz
10.0
10.6
11.0
12.0
12.0
13.0
13.3
14.0
14.6
15.0
16.0
16.0
16.2
16.3
17.0
17.7
19.4
20.8
A
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9
3, 8, 9, 20
ICCCMOS ICC for VccCM OS 250 mA
Table 6. Voltage and Current Specifications 1, 2 (Sheet 2 of 3)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
26
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to all proc essor frequencies.
2. A ll specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
Intel
®
Celeron
TM
processor, see the
Intel
®
Celeron
TM
Processor Datasheet
.
3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. VTT and Vcc1.5 must be held to 1.5V ±9% while t he AGTL+ bus is active. It is required that VTT and Vcc1.5 be
held to 1.5V ±3% while the p rocessor system bus is static (idle condition). The ±3% range is the required
design target; ± 9% will come from the t ransient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the sold ered-side of the motherboard . VCCCORE must return to within the static
voltage specification within 100 µs after a transient event; see the
VRM 8.4 DC-DC Converter Design
Guidelines
for further details.
7. VREF should be generated from VTT by a voltage divider of 1% resistors or 1% mat ched resistors. Refer to the
Intel®
Pentium
®
II Processor Developer’s Manual
for more details on VREF.
8. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VccCORE
(VccCORE_TYP). In this case, the maximum current level for the regulator, IccCORE_REG, can be reduced from
the specified maximum current IccCORE _MAX and is calculated by the equation:
IccCORE_REG = IccCORE_MAX × (VccCORE_TYP - VccCORE_STATIC_TOLERANCE) / Vcc CORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see Section 2.1).
11.The curr ent specified is also for AutoHALT state.
12.Maximum values are specified by design/characterization at nominal VccCORE.
13.Based on simulati on and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5V or 3.3V supply. VTT should not be used due to risk of AGTL+ switching noise coupling to this analog
reference.
16.Static voltage regulatio n includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables ab ove.
17.FMB - Flexible Motherboard recommendation
18.These values are estimates based on preliminary simulation.
ICLKREF CLKRE F voltage
supply current 60 µA
IVTT Termination voltage
supply current 2.7 A 10
ISGnt ICC Stop-Grant for
processo r core 2.5 A 8, 11
ISLP ICC Sleep for processor
core 2.5 A 8
IDSLP ICC Deep Sleep for
processo r core 2.2 A
dICCCORE/dt Power supply current
slew rate 240 A/µs 12, 13, 14
dIvTT/dt Termination current
slew rate 8A/µs
12, 13, See
Table 9
Table 6. Voltage and Current Specifications 1, 2 (Sheet 3 of 3)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
Datasheet
27
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
19.This specification applies to PGA370 processors operating at frequencies of 933MHz or higher.
20.This specification only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70V, however
the processor should be supplied 1.76V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM.
21.This specification applies only to 1B GHz S-spec #: SL4WM. This value is 60mV offset from the standard
specification and more at the Minimum specification. These tolerances are measured from a 1.70V base,
while Vcc supplied is 1.76V.
28
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. A ll inputs, outputs, and I/O pins must comply with the signal quality specifications in Section 3.0.
3. Minimum and maximum VTT are given in Table 9 on page 29.
4. (0 ≤ VIN ≤ 1.5 V +3%) and (0 ≤VOUT≤1.5V+3%).
5. Refer to the processor I/O Buffer Models for I/V characteristics.
6. St eady state input voltage must not be above VSS + 1.65V or below VTT - 1.65V.
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to Pentum III processors at all frequencies.
2. Parameter measured at 9 mA (for use with TTL inputs).
3. (0 ≤ VIN ≤ 2.5V +5%).
4. ( 0 ≤ VOUT ≤ 2.5V +5%).
5. For BCLK specifications, refer to Table 17 on page 38.
6. (0 ≤ VIN ≤ 1.5V +3%).
7. ( 0 ≤ VOUT ≤ 1.5V +3%).
8. Applies to non-AGTL+ signal s BCLK, PICCLK, and PWRGOOD.
9. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD.
Table 7. AGTL+ Signal Groups DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.150 VREF - 0.200 V 6
VIH Input High Voltage VREF + 0.200 VTT V 2, 3, 6
Ron Buffer On Resistance 16.67 Ω 5
ILLeakage Current for inputs,
outputs, and I/O ±100 µA 4
Table 8. Non-AGTL+ Signal Group DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL1.5 Input Low Voltage –0.150 VREF - 0.200 V 9
VIL2.5 Input Low Voltage -0.58 0.700 V 5, 8
VIH1.5 Input High Voltage VREF + 0.200 VTT V6, 9
VIH2.5 Input High Voltage 2.000 3.18 V 5, 8
VOL Output Low Voltage 0.400 V 2
VOH Output High Voltage VTT V7, 9, All outputs are
open-drain
IOL Output Low Current 9 mA
ILI Input Leakage Current ±100 µA 3, 6
ILO Output Leakage Current ±100 µA 4, 7
Datasheet
29
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
2.12 AGTL+ Syst em Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT. These termination resistors are placed electrically between the ends of the signal
traces and the VTT voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called VREF. Refer to the appropriate platform design guide for more information
Table 9 below lists the nominal specification for the AGTL+ termination voltage (VTT). The
AGTL+ reference voltage (VREF) is generated on the system motherboard and should be set to 2/3
VTT for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the Intel®Pentium®II Processor Developer's Manual and AP-585,
Intel®Pentium®II Processor AGTL+ Guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Pent ium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. VTT and Vcc1.5 must be held to 1.5V ±9%. It is required that VTT and Vcc1.5 be held to 1.5V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. See
Section 7.0 for more details on the RTT CTRL signal. Refer to the recommendation guidelines for t he specific
chipset/processor combination.
5. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
2.13 System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 10 through Table 16 list the AC specifications associated with the processor system bus.
These specifications are broken into the following categories: Table 10 contains the system bus
clock specifications, Table 12 contains the AGTL+ specifications, Table 13 contains the CMOS
signal gr oup s pecifi cati ons , Table 14 contains timings for the r eset cond itions, Table 15 and covers
APIC bus timing, and Table 16 covers TAP timing.
All processor system bus AC specifications for the AGTL+ signal group are relative to the rising
edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’ logic
levels unless otherwise specified.
Table 9. Processor AGTL+ Bus Specifications 1, 2
Symbol Parameter Min Typ Max Units Notes
VTT Bus Term ination Voltage 1.50 V 3
On-die RTT Termination Resistor 40 130 Ω4
VREF Bus Refe rence Voltage 0.950 2/3 VTT 1.05 V 5
30
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
The timings specified in this section sh ould be used in conjun ction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) as the Pentium
III
Processor for the PGA37 0 Socket I/O Buffer
Models, XTK/XNS Format (Electronic Format).
AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be tak e n to read all notes associated with a particular timing parameter.
2.13.1 I/O Buffer Model
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s D eveloper’s Website (http://developer.inte l.com). The mo del is for use in single p rocessor
designs and assumes the presence of motherboard RTT values as described in Table 9 on page 29.
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings f or the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00V at the processor pins.
3. N/A
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 M Hz or 133 M Hz, not both. Table 11 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance f or clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recomm ended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the ri sing edg es of adjacent BCLKs crossi ng 1.25V at the processor pi n. The j itt er present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriat e clock synthesizer/driver specification for details
8. BCLK Rise time is measure bet ween 0.5V–2.0V. BCLK fall time is measured between 2.0V–0.5V.
9. BCLK high time is measured as the peri od of time above 2.0V. BCLK low t ime is measured as the period of
time below 0.5V
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 M Hz.
11.This spec ification applies to Pentium III processors operating at a system bus frequency of 133 M Hz.
12.Not 100% tested. Specified by design characterization as a clock driver requirement.
Table 10. System Bus AC Specifications (Clock)1, 2, 3
T# Parameter Min Nom Max Unit Figure Notes
System Bus Frequency 100.00
133.33 MHz 4
4
T1: BCLK Period 10.0
7.5 ns 74, 5, 10
4, 5, 11
T2: BCLK Period Stability ±250
±250 ps 6, 7, 10
6, 7, 11
T3: BCLK High Time 2.5
1.4 ns 79, 10
9, 11
T4: BCLK Low Time 2.4
1.4 ns 79, 10
9, 11
T5: BCLK Rise Time 0.4 1.6 ns 78, 12
T6: BCLK Fall Time 0.4 1.6 ns 78, 12
Datasheet
31
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the
Pentium III processor.
3. Individual processors will only operate at their specified system bus frequency. Either 100 MHz or 133 MHz,
not both.
Table 11. Valid System Bus to Core Frequency Ratios 1, 2, 3
Processor Core Frequency
(MHz) BCLK Frequency
(MHz) Frequency
Multiplier L2 Cache (MHz)
500E 500 100 5 500
533EB 533 133 4 533
550E 550 100 11/2 550
600E 600 100 6 600
600EB 600 133 9/2 600
650 650 100 13/2 650
667 667 133 5 667
700 700 100 7 700
733 733 133 11/2 733
750 750 100 15/2 750
800 800 100 8 800
800EB 800 133 6 800
850 850 100 17/2 850
866 866 133 13/2 866
900 900 100 9 900
933 933 133 7 933
1B GHz 1000 133 15/2 1000
32
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings f or the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. V alid delay timings for these signals are specified into 50 Ω to 1.5V, VREF at 1.0 V ±2% and with 56 Ω on-die
RTT.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchrounous.
7. S pecification is for a minimum 0.40 V swing from V REF - 200 mV to V REF + 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specifi cation is for a maximum 1. 0 V swing from VTT - 1V to VTT. This assumes an edge rate of 3V/ns.
9. This should be measured after VCCCORE, VTT, VccCMOS , and BCLK become stable.
10.This specification applies to the Pentium III processor running at 100 M Hz sy stem bus frequency.
11.This spec ification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 n s minimum setup time.
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. A ll CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK become stable .
Table 12. System Bus AC Specifications (AGTL+ Signal Group)1, 2, 3
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.40 3.25 ns 84, 10, 11
T8: AGTL+ Input Setup Time 1.20
0.95 ns
ns 9
95, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time 1.00 ns 98, 10
T10: RESET# Pulse Width 1.00 ms 10 6, 9, 10
Table 13. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T14: CMOS Input Pulse Width, except
PWRGOOD 2 BCLKs 8Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width 10 BCLKs 8, 11 5
Datasheet
33
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specificati ons are tested during manufacturing.
3. A ll AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
Table 14. System Bus AC Specifications (Reset Conditions) 1
T# Parameter M i n M ax Unit Figure Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time 4 BCLKs 10 Before deass ertion
of RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time 2 20 BCLKs 10 After clock that
deasserts RESET#
Table 15. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter Min Max Unit Figure Notes
T21: PICCLK Frequency 2.0 33.3 MHz
T22: PICCLK Period 30.0 500.0 ns 7
T23: PICCLK High Time 10.5 ns 7@ > 1.7V
T24: PICCLK Low Time 10.5 ns 7@ < 0.7V
T25: PICCLK Rise Time 0.25 3.0 ns 7(0.7V - 1.7V)
T26: PICCLK Fall Time 0.25 3.0 ns 7(1.7V - 0.7V)
T27: PICD[1:0] Setup Time 5.0 ns 94
T28: PICD[1:0] Hold Time 2.5 ns 94
T29a: PICD[1:0] Valid Delay (Rising Edge) 1.5 8.7 ns 7, 84, 5, 6
T29b: PICD[1:0] Valid Delay (Falling Edge) 1.5 12.0 ns 7, 84, 5, 6
34
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to all Pentium III processors fr equencies.
2. A ll AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All
TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fal l times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST #, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Note: For Figure 7 through Figure 13, the following apply:
1. Figure 7 through Figure 13 are to be used in conjunction with Table 10 through Table 16.
2. All AC timings for the AGTL+ signals at the processor p ins are referen ced to the B CLK rising
edge at 1.25 V. All AGTL+ si gnal timings (address bus, data bus, etc. ) are referenced at 1 .00 V
at the processor pins.
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
4. All AC timings for the TAP signals at the processor pins are ref erenced to the TCK rising edge
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
Table 16. System Bus AC Specifications (TAP Connection)1, 2, 3
T# Parameter Min Max Unit Figure Notes
T30: TCK Frequency 16.667 MHz
T31: TCK Period 60.0 ns 7
T32: TCK High Time 25.0 ns 7VREF + 0.200V, 10
T33: TCK Low Time 25.0 ns 7VREF - 0.200V, 10
T34: TCK Rise Time 5.0 ns 7(VREF - 0.200V) -
(VREF + 0.200V),
4, 10
T35: TCK Fall Time 5.0 ns 7(VREF + 0.200V) -
(VREF - 0.200V),
4, 10
T36: TRST# Pulse Width 40.0 ns 13 Asynchronous, 10
T37: TDI, TMS Setup Time 5.0 ns 12 5
T38: TDI, TMS Hold Time 14.0 ns 12 5
T39: TDO Valid Delay 1.0 10.0 ns 12 6, 7
T40: TDO Float Delay 25.0 ns 12 6, 7, 10
T41: All Non-Test Outputs Valid Delay 2.0 25.0 ns 12 6, 8, 9
T42: All Non-Test Inputs Set up Time 25.0 ns 12 6, 8, 9, 10
T43: All Non-Test Inputs Set up Time 5.0 ns 12 5, 8, 9
T44: All Non-Test Inputs Hol d Time 13.0 ns 12 5, 8, 9
Datasheet
35
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 7. BCLK, PICCLK, and TCK Generic Clock Waveform
Figure 8. System Bus Valid Delay Timings
Figure 9. System Bus Setup and Hold Timings
T
r
= T5, T25, T34, (Rise Time)
T
f
= T6, T26, T35, (Fall Time)
T
h
= T3, T23, T32, (High Time)
T
l
= T4, T24, T33, (Low Time)
T
p
= T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK is referenced to 0.5V. TCK is referenced to V
REF
- 200mV.
PICCLK is referenced to 0.7V.
V2 = BCLK is referenced to 2.0V. TCK is referenced to VREF - 200mV.
PICCLK is referenced to 1.7V.
V3 = BCLK and PICCLK are referenced to 1.25V. TCK is referenced to V
REF
.
V2 V3
V1
t
r
t
p
t
f
t
h
t
l
CLK
CLK
Signal Valid Valid
Tx
V
Tx
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group; 0.75V for CMOS, APIC and TAP signal groups
CLK
Signal Valid
Ts
V
Th
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = 1.0V for AGTL+ signal group; 0.75V for APIC and TAP signal groups
36
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 10. System Bus Reset and Configuration Ti mings
Figure 11. Power-On Reset and Configuration Timings
Ty
Safe Valid
Tz
Valid
Tv
Tw
Tx
Tu
Tt
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Tt= T9 (AGTL+ Input Hold Time)
Tu= T8 (AGTL+ Input Setup Time)
Tv= T10 (RESET# Pulse Width)
Tw= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
Tx= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
T
a
Valid Ratio
T
C
T
b
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
T
a
= T15 (PWRGOOD Inactive Pulse)
T
b
= T10 (RESET# Pulse Width)
T
c
= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
BCLK
V
IL, max
V
IH, min
Vcc
CORE
, V
TT
,
V
REF
Datasheet
37
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 12. Test Timings (TAP Connection)
Figure 13. Test Reset Timings
T
r
= T43 (All Non-Test Inputs Setup Time)
T
s
= T44 (All Non-Test Inputs Hold Time)
T
u
= T40 (TDO Float Delay)
T
v
= T37 (TDI, TMS Setup Time)
T
w
= T38 (TDI, TMS Hold TIme)
T
x
= T39 (TDO Valid Delay)
T
y
= T41 (All Non-Test Outputs Valid Delay)
T
z
= T42 (All Non-Test Outputs Float Time)
T
v
T
w
T
r
T
s
T
u
T
z
T
x
T
y
TCK
TDI, TMS
Input
Signal
TDO
Output
Signal
T
q
TRST#
T
q
= T36 (TRST# Pulse Width)
1.25V
38
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.0 Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 17, Table 18, and Table 23 ensures that
signal quality eff ects will not adversely affect processor operation.
3.1 BCLK and PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 17 describ e s the signal quality specifications at the process or pins for the p r ocessor system
bus clock (BCLK) and APIC clock (PICCLK) signals. Figure 14 describes the signal quality
waveform for the system bus clock at the processor pins.
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to all Pentium III processors fr equencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Table 17. BCLK/PICCLK Signal Quality Specifications for Simula tion at the Processor Pins 1
T# Parameter Min N om Max Unit Figure Notes
V1: BCLK VIL 0.500 V 14
V1: PICCLK VIL 0.700 V 14
V2: BCLK VIH 2.000 V 14
V2 PICCLK VIH 2.000 V 14
V3: VIN Absolute Voltage Range –0.58 3.18 V 14
V4: BCLK Rising Edge Ringback 2.000 V 14 2
V4: PICCLK Rising Edge Ringback 2.000 V 14 2
V5: BCLK Falling Edge Ringback 0.500 V 14 2
V5: PICCLK Falling Edge Ringback 0.700 V 14 2
Datasheet
39
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.2 AGTL+ Signal Quality Speci fications and Measurement
Guidelines
Many scenarios h a ve been simulated to generate a set of AGTL+ layout guid elines which are
available in the appropriate platform design guide. Refer to the Intel®Pentium®II Processor
Developer's Manual (Order Number 243502) for the AGTL+ buffer specification.
Table 18 provides the AGTL+ signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Pentium III processor for the PGA370 socket maximum allowable overshoot and undershoot
specifications for a given duration of time are detailed in Table 20 through Table 22. Figure 15
shows the AGTL+ ringback tolerance and Figure 16 shows the overshoot/undershoot waveform.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. S pecifications are for the edge rate of 0.3 - 0.8V/ns. See Figure 15 for the generic waveform.
3. A ll values specified by design characterization.
4. Please see Table 20 for maximum allowable overshoot.
5. Ringback between V REF + 100 mV and VREF + 200 mV or VREF - 200 mV and VREF - 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (
Intel
®
Pentium
®
II
Developers Manual
). Ringback below VREF + 100 m V or above VREF - 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
sources of syst em noise.
7. A negative value for ρ indicates that the ampl itude of ringback is above VREF. (i.e., φ = -100 mV specifies the
signal cannot ringback below VREF + 100 mV).
8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV.
Figure 14. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V2
V1
V3
V3
V4
V5
Table 18. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins 1, 2, 3
T# Parameter Min Unit Figure Notes
α: Overshoot 100 mV 15 4, 8
τ: Minimum Time at High 0.50 ns 15
ρ: Amplitude of Ringback ±200 mV 15 5, 6, 7, 8
φ: Final Settling Voltage 200 mV 15 8
δ: Duration of Squarewave Ringback N/A ns 15
40
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.3 AGTL+ Signal Quality Specifications and Measurement
Guidelines
3.3.1 Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or bel ow VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely resu lt of
excessive ov e rs hoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp unders hoo t or overshoot and will yield correct simulat i on resul ts . If ot h er I/O buffer models
are being used to characterize the Pentium III processor performance, care must be taken to ensure
that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will
impact results and may yield excessive overshoot/undershoot.
Figure 15. Low to High AGTL+ Receiver Ringback Tolera nce
ibk tl
0.7V Clk Ref
Clock
Time
V
start
V
REF
- 0.2
V
REF
V
REF
+ 0.2
Note: High to low case is analogous
τ
α
δ
ρφ
Datasheet
41
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.3.2 Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This could be acomplished by simultaneously measuring the VTT plane while measuring the
signal undersh oot. Today’s o scillo scopes can easily calculate the true undershoot waveform . The
true undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT - Signal_measured
Note: The converted undershoot waveform appears as a positive (overshoot) signal.
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determin ed independently.
After the true waveform conversion, the undershoot/overshoot specifications shown in Table 20
through Table 22 can be applied to the converted undershoot waveform using the same magnitude
and pulse duration specifications used with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in Table 20 through Table 22. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed puls e du rati ons. Prov ided that the magnitude of the overshoot/unde rshoot is within the
Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must
all be used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3 Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.635V). The total time could encompass several
oscillations above the reference voltag e. Multip le overshoot/undershoot pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
Note: Oscillations be low the reference voltag e can n ot be substracted from the total overshoot/
undershoot pulse duration.
Note: Multiple Overshoot/Undershoo t events occurring within th e same clock cycle must be considered
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individu al Pulse Duraitons to determine the total Oversho ot/Undershoot Pulse Duration for that
total event.
3.3.4 Ac t ivity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The specific at ions provided in Table 20 through Table 22 show the Maximum Pulse Duration
allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table
entry is independent of all others, meaning that the Pulse Duration reflects the existence of
overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot
42
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can
be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the
event occurs at all times and no other events can occur).
Note: Activity factor for AGTL+ signals is referenced to BCLK frequency.
Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
3.3.5 Reading Overshoot/Undershoot Specification Tables
The overshoot/undersho ot specifi cation for the Pentium III processor for the PGA370 socket is not
a simple single value. Instead, many factors are needed to determine what the over/undershoot
specification is. In addition to the magnitude of the overshoot, the following parameters must also
be known: the junction temperature the processor will be operating at, the width of the overshoot
(as measured above 1. 635V) and the Activity Factor (AF). To determine the allowed over shoot for
a particular overshoot event, the following must be done:
1. Determine the sig nal gr oup t hat particular signal falls into. If the signal is an AGTL+ signal
operating with a 100 MHz system bus, use Table 20 (100MHz AGTL+ signal group). If the
signal is an AGTL+ signal operating with a 133MHz system bus, use Table 21 (133 MHz
AGTL+ signal group). If the signal is a CMOS signal, use Table 22 (33 MHz CMOS signal
group).
2. Determine the maximum junction temperature (Tj) for the range of processors that the system
will sup po rt (80oC or 85oC).
3. Determine the M agn itude of the overshoot (relative to VSS)
4. Determine the A ctivity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Below is an example showing how the maximum pulse duration is determined for a given
waveform.
NOTES:
1. Corresponding Maximum Puse Duration Specification - 2.4 ns
2. P ulse Duration (measured) - 2.0 ns
Given the above parameters, and using Table 21 (85 oC/AF = 0.1 column) the maximum allowed
pulse dur ati o n i s 2. 4 ns. Since the measur e pul s e duration is 2 .0 ns, this par t icu l ar ov ersh oot ev ent
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
Table 19. Example Platform Information
Required Information Maximum Platform Support Notes
FSB Signal Group 133 MHz AG TL+
Max Tj 85 °C
Overshoot Magnitude 2.13V Measured Value
Activity Fact or (AF ) 0.1 Measured overshoot occurs on
average every 20 clocks
Datasheet
43
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.3.6 Determining if a System meets the Overshoot/Undershoot
Specifications
The overshoot/und ershoot specifications listed in the followin g tables speci fy th e allowable
overshoot/un dershoot for a single overshoot/undershoot event. Ho wever most systems will ha ve
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
you add the total impact of all overshoot events, the system may fail. A guideline to ensure a
system passes the overshoot and undershoot specifications is shown below. It is important to meet
these guidelines; otherwise, contact your Intrel field representative.
1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635V
OR
2. If only one ov ershoot /under shoot event mag nit ude occu rs, ens ure i t meets the ov er/un dershoot
specifications in the following tables
OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magn itude and co mpare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 20 through Table 22.
NOTES:
1. Overshoot/Undershoot Magnitude = 2.18V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to VSS.
3. Undershoot is measured relative to VTT
4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V.
5. Rinbacks below VTT can not be subtracted from Overshoots/Undershoots
6. Lesser Undershoot does not allocate longer or larger Overshoot
7. OEM's are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines
provided in the specific platform design guide.
8. All values specified by design character ization
1. BCLK period is 10 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 20. 100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins1,2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns) Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 20 2.53 0.25 18.6 1.86 0.18
2.13 V 20 4.93 0.49 20 3.2 0.32
2.08 V 20 9.1 0.91 20 6.1 0.6
2.03 V 20 16.6 1.67 20 11.4 1.1
1.98 V 20 20 3.0 20 20 2
1.93 V 20 20 5.5 20 20 6.6
1.88 V 202010202020
44
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
1. BCLK period is 7.5 ns.
2. Measurements taken at the processor socket pi ns on the solder-side of the motherboard.
NOTES:
1. P IC CLK period is 30 ns.
2. Measurements taken at the processor socket pi ns on the solder-side of the motherboard.
Table 21. 133 MHz AGTL+ Signal Group Overshoot/Undershoot Toleran ce 1, 2
Overshoot/Undershoo t
Magnitude
Maximum Pulse Duration at Tj = 80
°C (ns) Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 A F = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 15 1.9 0.19 14 1.4 0.14
2.13 V 15 3.7 0.37 15 2.4 0.24
2.08 V 15 6.8 0.68 15 4.6 0.46
2.03 V 15 12.5 1.25 15 8.6 0.84
1.9 8 V 15 15 2.28 1 5 15 1.5
1.93 V 15 15 4.1 15 15 5
1.88 V 15 15 7.5 15 15 15
Table 22. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins1, 2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns) Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 60 7.6 0.76 56 5.6 0.56
2.13 V 60 14.8 1.48 60 9.6 0.96
2.08 V 60 27.2 2.7 60 18.4 1.8
2.03 V 60 50 5 60 33 3.3
1.98 V 60 60 9.1 60 60 6
1.93 V 60 60 16.4 60 60 20
1.88 V 6060306060 60
Datasheet
45
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.4 Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settlin g lim it. All three sign al quality parameters are shown in Figure 17 for the non-
AGTL+ signal group.
NOTES:
1. VHI = 1.5V for all non-AGTL+ signals except for BCLK, PICCLK, and PW RGOOD. VHI = 2.5 V for BCLK,
PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.
Figure 16. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
Vss
Undershoot
Magnitude = V
TT
- Signal
Overshoot
Magnitude = Signal - Vss
V
TT
2.18V
2.08V
1.98V
1.88V
1.635V
Max
Overshoot
Magnitude
Time Dependent
Overshoot Converted Undershoot
Waveform
Undershoot
Magnitude
Time Dependent
Undershoot
Figure 17. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1
Undershoot
Overshoot Settling Limit
Settling Limi t
Rising-Edge
Ringback Falling-Edge
Ringback
VLO
VSS Time
VHI
46
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
3.4.1 Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or bel ow VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates (see Figure 17 for non-AGTL+ signals). The processor can be damaged by
repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if
the overshoot is great enough). Permanent damag e to the processor is the likely result of excessive
oversh oo t/undershoot. Violating the overshoot/unders hoot guideline will also ma ke satisfying the
ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the
absence of diodes on the input. These guidelines should be verified in simulations without the on-
chip ESD protection diodes present because the diodes will begin clamping the 1.5 V and 2.5 V
tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below
VSS. If signals are not reachin g the clamping voltage, this will not be an issue. A system should not
rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.
Note: The undersh oot guideline limits transitions exactly as described for the ATGL+ sign a ls. See
Figure 16.
3.4.2 R ingback Sp ecification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See Figure 17 for an illustration of ringback. Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 23 for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor pins .
NOTES:
1. Unl ess otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL+ signals except PWRGOOD.
3.4.3 Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total sign al swing (VHI –VLO) above
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwan ted
oscillatio ns which could jeopardize sign a l integrity. Simulation s to verify settling limit may be
done either with or without the in put protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amp litude o f
the ringing increasing in the subsequent transitions.
Table 23. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins 1
Input Signal Group Transition Maximum Ringback
(with Input Diodes Present) Unit Figure
Non-AGTL+ Signals 20 → 1 Vref + 0.200 V 17
Non-AGTL+ Signals 21 → 0 Vr ef - 0.200 V 17
PWRGOOD 0 → 1 2.00 V 17
Datasheet
47
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
4.0 Thermal Specifications and Design Considerations
This chapter provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design
Guidelines (Order Number 245087). The Pentium III processor uses flip chip pin grid array
packaging technology and has a junction temperature (Tjunction) specified.
4.1 Thermal Specifications
Table 24 provides the thermal design power dissipation and maximum temperatures for the
Pentium III processor for the PGA370 socket. Systems should design for the highest possible
processor power, even if a processor with a lower thermal dissipation is planned. A thermal
solution should be designed to ensure the junction temperature never exceeds these specifications.
NOTES:
1. These values are specified at nominal VCCCORE for the processor pins.
2. Therm a l Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tjunction specification.
3. TDP does not represent the power delivery and voltage regulation requirements for the processor . Refer to
Table 6 for voltage regulation and electrical specifications.
Table 24. Intel® Pentium® III Processor for the PGA370 Socket Thermal Design Power 1
Processor
Processor
Core
Frequency
(MHz)
L2 Cache
Size
(Kbytes)
Processor
Thermal
Design
Power 2,3
(W)
Power
Density5
(W/cm2)
CPUID
up to
0683h
Power
Density5
(W/cm2)
for
CPUID
0686h
Maximum
TJUNCTION
(°C)
TJUNCTION
Offset 4,6
(°C)
500E 500 256 13.2 18.2 20.8 85 1.9
533EB 533 256 14.0 19.3 22.0 85 2.0
550E 550 256 14.5 20.0 22.8 85 2.1
600E 600 256 15.8 21.8 24.8 82 2.3
600EB 600 256 15.8 21.8 24.8 82 2.3
650 650 256 17.0 23.4 26.7 82 2.5
667 667 256 17.5 24.1 27.5 82 2.5
700 700 256 18.3 25.2 28.7 80 2.7
733 733 256 19.1 26.3 30.0 80 2.8
750 750 256 19.5 26.9 30.6 80 2.8
800 800 256 20.8 28.7 32.6 80 3.0
800EB 800 256 20.8 28.7 32.6 80 3.0
850 850 256 22.5 31.0 35.2 80 3.3
866 866 256 22.9 31.5 35.9 80 3.3
900 900 256 23.2 N/A 37.1 75 3.6
933 933 256 24.5 33.8 38.4 75 3.6
1B GHz 1000 256 26.1 36.0 40.9 70 3.8
1B GHz7,8 1000 256 29.6 N/A 43.9 70 3.8
48
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
4. Tjunctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the
hottest location on the processor ’s core.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in Figure 18.
6. TJUNCTION offset values do not include any thermal di ode kit measurement error. Diode kit measurement
error must be added to the TJUNCTION offset value from the table, as outlined in the
Intel
®
Pentium
®
III
processor Thermal Metrology for CPUID-068h Family Processor s
(Order Number: 245301). Intel has
characterized the use of the Analog Devices AD1021 diode measurement kit and found its measurement
error to be 1 °C.
7. These values are estimates based on preliminary simulation.
8. This specificati on only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70V, however
the processor should be supplied 1.76V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM.
Figure 18 is a block diagram of the Pentium III processor die layout. The layout differentiates the
processor core from the cache d ie area. In effect, the thermal design power ind entified in Table 24
is dissipated entirely from the processor core area. Thermal solution designs should compensate
for this smaller heat flux area and not assume that the power is uniformly distributed across the
entire die area. The drawing below does not depict the 5% die shrink (CPUID=0686h) values as
follows: Die Area (0.900), Core Area (0.642), Cache Area (0.258) cm2.
4.1.1 Thermal Diode
The Pentium III processor for the PGA370 socket incorp orates an on-die diode that may be used to
monitor the die temperature (junction temperature). A thermal sensor located on the motherboard,
or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal
management or instrumentation purposes. Table 25 and Table 26 provide the diode parameter and
interface specifications.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-
die temperature gradients between the location of the thermal diode and the hottest location on the
die at a given point in time, and time based variations in the die temperature measurement. Time
based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is
slower than the rate at which the Tjunction temperature can change.
Figure 18. Processor Functional Die Layout for CPUIDs up to and including 0683h
Die Area ( 1. 0 46 cm2)
Core Area (0.7 26 cm2)
Cache Ar ea ( 0 .320 cm2)
Datasheet
49
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Charact eri zed at 100° C with a forward bias current of 5 - 300 µA.
3. The ideality factor , n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
Ifw=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the
diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4. Not 100% tested. Specified by design characterization.
Table 25. Thermal Diode Parameters1
Symbol Parameter Min Typ Max Unit Notes
Ifw Forward Bias Current 5 300 µ A 1
n Diode Ideality Factor 1.0057 1.0080 1.0125 2, 3, 4
Table 26. Thermal Dio de Interface
Pin Name PGA370 Socket pin # Pin Description
THERMDP AL31 diode anode (p_junction)
THERMDN AL29 diode cathode (n_junction)
50
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
5.0 Mechanical Specifications
The Pentium III processor uses a FC-PGA package technology. Mechanical specifications for the
processor are given in this section. See Section 1.1.1 for a complete terminology listing.
The processor utilizes a PGA370 socket for installation into the motherbo ard. Details on the sock et
are available in the 370-Pin Socket (PGA370) Design Guidelines.
Note: For Figure 19, the following apply:
1. Unless otherwis e specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production
product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational
purposes only. Reference dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference dimensions are
NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in
parentheses without tolerances are reference dimensions.
4. Drawings are not to scale.
5.1 F C-PGA Mechanical Specifications
The following fi gur e with pack age dimen sion s is prov i ded to aid i n the des ign of heatsink and clip
soluti ons as well as demonstrate where pin-side capacitors will be located on the processor.
Table 27 includes the measurements for these dimensio ns in both inches and millimeters.
Figure 19. Package Dimensions
Datasheet
51
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Capaci tors will be placed on the pin-side of the FC-PGA package in the area def ined by G1, G2, and G3. This
area is a keepout zone for motherboard designers.
The bare processor die has mechanical load limits that should not be exceeded during heat sink
assembly, mechanical stress testing , or stan dard drop and shipping conditio ns. The heat sink att ach
solution must not induce permanent stress into the processor substrate with the exception of a
uniform load to maintain the heatsink to the processor ther mal interface. The package dy namic and
static loading parame ters are li sted in Table 28.
For Table 28, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads
NOTES:
1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface
Table 27. Intel® Pentium® III Processor Package Dimensions
Symbol Millimeters Inches
Minimum Maximum Notes Minimum Maximum Notes
A1 0.787 0.889 0.031d 0.035
A2 1.000 1.200 0.039 0.047
B1 11.226 11.329 0.442 0.446
B2 9.296 9.398 0.366 0.370
C1 23.495 max 0.925 max
C2 21.590 max 0.850 max
D 49.428 49.632 1.946 1.954
D1 45.466 45.974 1.790 1.810
G1 0.000 17.780 0 0.700
G2 0.000 17.780 0 0.700
G3 0.000 0.889 0 0.035
H 2.540 Nominal 0.100 Nominal
L 3.048 3.302 0.120 0.130
ΦP 0.431 0. 483 Pin Diameter 0.017 0.019
Pin TP 0.508 Diameteric True Position (Pin-to-Pin) 0.020 Diameteric True Position (Pin-to-Pin)
Table 28. Processor Die Loading Parameters
Parameter Dynam ic (max)1Static (max)2Unit
Silicon Die Surface 200 50 lbf
Silicon Die Edge 100 12 lbf
52
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
5.2 Processor Markings
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium III processor for the PGA370 socket. Table 27 lists the measurements
for the package dimensions.
5.3 Processor Signal Listing
Table 29 and Table 30 provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 21 provides a pin-side view of the Pentium III processor pin-out.
The following notes apply to Table 29 and Table 30:
NOTES:
1. Thes e pins are required for backwards compatibility with other Intel processors. They are not used by the
Pentium III processor. Refer to the appropriate platform design guide and Section 7.1 for implementation
details.
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
platform design guide and Section 7.1 for implementation details. If backwards compatibility is not required,
then RESET2# (X4) should be connected to GND.
3. VCC1.5V must be supplied by the same voltage source supplying the VTT pins.
4. These V TT pins must be left unconnect ed (N/C) for backwards compatibility with Intel® Celeron™ processors
(CPUID 066xh). F or designs which do not support the Intel Celeron processors (CPUID 066xh), and for
compatibility with future processors, these VTT pins should be connected to the VTT plane. Refer to the
appropriate platform design guide and Section 7.1 for implementation details. For dual processor designs,
these pins must be connected to VTT.
5. This pin is required for backwards compatibilit y . If backwards compatibility is not required, this pin may be left
connected to VCCCORE. Refer to the appropriate platform design guide for implementation details.
6. P revious ly, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
(N/C).
7. P revious ly, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED. Refer to the
Peniutm
®
III
processor Specification Update
for a complete listing of processors that support DP operation.
Figure 20. Top Side Processor Markings
Dynamic
Production
Mark
Example
RB80526PY550266
FFFFFFFF-0001 SSSSS
FPO # - S/N S-spec#
pentium III logo
MALAY
intel ®
i (m) (c) ’99
Static Mark in k printed at
substrate supplier Country of Origin
Dynamic Laser Mark
Swatch
Product Code
Datasheet
53
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 21. Intel® Pentium® III Processor Pinout
VSS
VCC
VSSD35
D29
D33
D26
D28
D21 D23
D25
VSS
VCC
VSS
D31
VCC
D43
VCC VSS
D34
D38
VCCVSS
D39
D36
VCC
D37 D44
VCC VCC D32 D22 RSV D27
VSS
D42
D45 D49
VSS
VCC D63 VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS
VCC VSS VCC VSS RSV VTT D62 SLEW
CTRL DEP6 DEP4 VREF0 BPM1 BP3
D41 D52 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
D40 D59 D55 D54 D58 D50 D56 DEP5 DEP1 DEP0 BPM0 CPUPRES
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BINIT
D51 D47 D48 D57 D46 D53 D60 D61 DEP7
Dep7 DEP3 DEP2 PRDY VSS
BP2 VTT RSV
VCC VSS VCC
PICCLK PICD0 PREQ
VCC VCC VSS
RSV PICD1 LINT1
VCC VSS LINT0
RSV RSV RSV
VSS VCC VSS
RSV RSV RSV
VCC VSS VCC
VTT RTT
CTRL VTT
VSS VCC VSS
PLL2 VTT VTT
VCC VSS VCC
CLKREF VCC VSS
VCC VSS V_2.5
VTT VTT VCC
VSS VCC V_CMOS
VSS FERR RSP
VCC VSS V_1.5
A20M IERR FLUSH
VSS VCC VSS
INIT
VSS VCC VSS
PLL1 RSV BCLK
STPCLK IGNNE
VSS D16 D19
D7 D30 VCC
VCC VREF2 D24
D13 D20 VSS
VSS D11 D3
D2 D14 VCC
VCC D18 D9
D12 D10 VSS
RSV D17 VREF3
D8 D5 VCC
VCC D1 D6
D4 D15 VSS
VSS BERR VREF4
D0 A34 VCC
BR1 RESET2 A32
RSV A26 VSS
VSS A29 A18
A27 A30 VCC
VCC A24 A23
A33 A20 VSS
VSS A31 VREF5
A17 A22 VCC
VCC A35 A25
EDGCTRL A19 VSS
VSS RESET A10 A5 A8 A4 BNR REQ1 REQ2 VTT RS1 VCC RS0 THERM
TRIP
SLP VCC VSS VCC
A21 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BSEL1 BSEL0 SMI VID3
VCC VSS A28 A3 A11 VREF6 A14 VTT REQ0 LOCK VREF7 AERR PWRGD RS2 RSV TMS VCC VSS
VSS VSS A15 A13 A9 AP0 VTT A7 REQ4 REQ3 VTT HITM HIT DBSY THRMDN THRMDP TCK VID0 VID2
RSV VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1
VSS A12 A16 A6 VTT AP1 VTT BPRI DEFER VTT RP TRDY DRDY BR0 ADS TRST TDI TDO
Pin Side View
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
54
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 29. Signal Listing in Order by
Signal Name
Pin
No. Pin Name Signal Group
AK8 A 3# AGTL+ I/ O
AH12 A4# A GTL+ I/O
AH8 A5# AGTL+ I/O
AN9 A6# AGTL+ I/O
AL15 A7# AGTL+ I/O
AH10 A8# A GTL+ I/O
AL9 A9# A GTL+ I/ O
AH6 A10# A GTL+ I/O
AK10 A11# AGTL+ I/O
AN5 A12# A GTL+ I/O
AL7 A 13# AGTL+ I/O
AK14 A14# AGTL+ I/O
AL5 A 15# AGTL+ I/O
AN7 A16# A GTL+ I/O
AE1 A17# AGTL+ I/O
Z6 A18# AGTL+ I/O
AG3 A19# AGTL+ I/O
AC3 A20# A GTL+ I/O
AE33 A20M# CMOS Input
AJ1 A21# A GTL+ I/O
AE3 A22# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB4 A24# AGTL+ I/O
AF6 A25# AGTL+ I/O
Y3 A26# AGTL+ I/O
AA1 A27# AGTL+ I/O
AK6 A28# AGTL+ I/O
Z4 A29# AGTL+ I/O
AA3 A30# AGTL+ I/O
AD4 A31# A GTL+ I/O
X6 A32# AGTL+ I/O
AC1 A33# A GTL+ I/O
W3 A34# AGTL+ I/O
AF4 A35# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AK24 AERR# AGTL+ I/O
AL11 AP0# AGTL+ I/O
AN13 AP1# AGTL+ I/O
W37 BCLK System Bus Clock
V4 BERR# AGTL+ I/O
B36 B INIT# A GTL+ I/O
AH14 B NR# AGTL+ I/O
G33 BP2# AGTL+ I/O
E37 BP3# AGTL+ I/O
C35 BPM0# AGTL+ I/O
E35 BPM 1# AGTL+ I/ O
AN17 BPRI# AGTL+ Input
AN29 B R0# AGTL+ I/O
X2 BR1#8AG TL + In put
AJ33 BSEL0 Power/Other
AJ31 BSEL1 Power/Other
Y33 CLKRE F 7Power/Other
C37 CPUPRES# Power/Other
W1 D0# AGTL+ I/O
T4 D1# AGTL+ I/O
N1 D2# AGTL+ I/O
M6 D3# AGTL+ I/O
U1 D4# AGTL+ I/O
S3 D5# AGTL+ I/O
T6 D6# AGTL+ I/O
J1 D 7# AGTL+ I/O
S1 D8# AGTL+ I/O
P6 D9# AGTL+ I/O
Q3 D1 0 # AGTL + I/O
M4 D11# AGTL+ I/O
Q1 D1 2 # AGTL + I/O
L1 D13# AG TL+ I/O
N3 D14# AGTL+ I/O
U3 D15# AGTL+ I/O
H4 D16# AGTL+ I/O
R4 D17# AGTL+ I/O
P4 D 18 # AGTL+ I/O
H6 D19# AGTL+ I/O
L3 D20# AG TL+ I/O
G1 D2 1 # AGTL + I/O
F8 D22# A G TL + I/O
G3 D2 3 # AGTL + I/O
K6 D 24 # AGTL+ I/O
E3 D 25 # AGTL+ I/O
E1 D 26 # AGTL+ I/O
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet
55
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
F12 D27# AGTL+ I/O
A5 D28# AGTL+ I/O
A3 D29# AGTL+ I/O
J3 D30# AGTL + I/O
C5 D31# AGTL+ I/O
F6 D32# AGTL+ I/O
C1 D33# AGTL+ I/O
C7 D34# AGTL+ I/O
B2 D35# AGTL+ I/O
C9 D36# AGTL+ I/O
A9 D37# AGTL+ I/O
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
C15 D40# AGTL+ I/O
D14 D41# AGTL+ I/O
D12 D42# AGTL+ I/O
A7 D43# AGTL+ I/O
A11 D44# AG TL+ I/O
C11 D45# AGTL+ I/O
A21 D46# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
C13 D49# AGTL+ I/O
C25 D50# AGTL+ I/O
A13 D51# AGTL+ I/O
D16 D52# AGTL+ I/O
A23 D53# AGTL+ I/O
C21 D54# AGTL+ I/O
C19 D55# AGTL+ I/O
C27 D56# AGTL+ I/O
A19 D57# AGTL+ I/O
C23 D58# AGTL+ I/O
C17 D59# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
E25 D62# AGTL+ I/O
F16 D63# AGTL+ I/O
AL27 DBSY# AGTL+ I/O
AN19 DEFER# A G TL+ Input
C33 DEP0# AGTL+ I/O
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
C31 DEP1# AGTL+ I/O
A33 DEP2# AGTL+ I/O
A31 DEP3# AGTL+ I/O
E31 DEP4# AGTL+ I/O
C29 DEP5# AGTL+ I/O
E29 DEP6# AGTL+ I/O
A29 DEP7# AGTL+ I/O
AN27 DRDY# AGTL+ I/O
AG1 EDGCTRL 5Power/Other
AC35 FERR# CMOS Output
AE37 FLUSH# CMOS Input
AM22 GND Power/Other
AM26 GND Power/Other
AM30 GND Power/Other
AM34 GND Power/Other
AM6 GND Power/Other
AN3 GND Power/Other
B12 GND Power/Other
B16 GND Power/Other
B20 GND Power/Other
B24 GND Power/Other
B28 GND Power/Other
B32 GND Power/Other
B4 GND Power/Other
B8 GND Power/Other
D18 GND Power/Other
D2 GND Power/Other
D22 GND Power/Other
D26 GND Power/Other
D30 GND Power/Other
D34 GND Power/Other
D4 GND Power/Other
E11 GND Power/Other
E15 GND Power/Other
E19 GND Power/Other
E7 GND Power/Other
F20 GND Power/Other
F24 GND Power/Other
F28 GND Power/Other
F32 GND Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
56
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
F36 GND Power/Other
G5 GND Power/Other
H2 GND Power/Other
H34 GND Power/Other
K36 GND Power/Other
L5 GND Power/Other
M2 GND Power/Other
M34 GND Power/Other
P32 GND Power/Other
P36 GND Power/Other
A37 GND Power/Other
AB32 GND Power/Other
AC33 GND Power/Other
AC5 GND Power/Other
AD2 GND Power/Other
AD34 GND Power/Other
AF32 GND Power/Other
AF36 GND Power/Other
AG5 GND Power/Other
AH2 GND Power/Other
AH34 GND Power/Other
AJ11 GND Power/Other
AJ15 GND Power/Other
AJ19 GND Power/Other
AJ23 GND Power/Other
AJ27 GND Power/Other
AJ3 GND Power/Other
AJ7 GND Power/Other
AK36 GND Power/Other
AK4 GND Power/Other
AL1 GND Power/Other
AL3 GND Power/Other
AM10 GND Power/Other
AM14 GND Power/Other
AM18 GND Power/Other
Q5 GND Power/Other
R34 GND Power/Other
T32 GND Power/Other
T36 GND Power/Other
U5 GND Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
V2 GND Power/Other
V34 GND Power/Other
X32 GND Power/Other
X36 GND Power/Other
Y37 GND Power/Other
Y5 GND Power/Other
Z2 GND Power/Other
Z34 GND Power/Other
AL25 HIT# AGTL+ I/O
AL23 HITM# AGTL+ I/O
AE35 IERR# CMOS Output
AG37 IGNNE# CMOS Input
AG33 INIT# C MOS Input
M36 LINT0/INTR CMOS Input
L37 LINT1/NMI CMOS Input
AK20 LOCK# AGTL+ I/O
J33 PICCLK APIC Clock I nput
J35 PICD0 AP IC I/O
L35 PICD1 APIC I/O
W33 PLL1 Power/Other
U33 PLL2 Power/Other
A35 PRDY# AGTL+ Output
J37 PREQ# CMOS Input
AK26 P W RGOOD CMOS Input
AK18 R EQ0# A GTL+ I/O
AH16 REQ1# A GTL+ I/O
AH18 REQ2# A GTL+ I/O
AL19 R EQ3# A GTL+ I/O
AL17 R EQ4# A GTL+ I/O
G37 Reserved Reserved for future use
L33 Reserved Reserved for future use
N33 Reserved Reserved for future use
N35 Reserved Reserved for future use
N37 Reserved Reserved for future use
Q33 Reserved Reserved for future use
Q35 Reserved Reserved for future use
Q37 Reserved Reserved for future use
R2 Reserved Reserved for future use
W35 Reserved Reserved for future use
Y1 Reserved Reserved for future use
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet
57
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
AK30 Reserved Reserved for future use
AM2 6Reserved Reserved for future use
F10 Reserved Reserved for future use
X2 BR1#8AGTL+ Input
AH4 RES ET# 2AGTL+ Input
X4 RESET2# 2AGTL+ I/O
AN23 RP# A GTL+ I/O
AH26 RS0# AGTL + I nput
AH22 RS1# AGTL+ Input
AK28 RS2# AGTL + Input
AC37 RSP# AGTL+ Input
S35 RTTCTRL Power/Other
E27 SLEWCTRL Power/Other
AH30 SLP# CMOS Inp ut
AJ35 SMI# C MO S In put
AG35 STPCLK# CMOS Inpu t
AL33 TCK TAP Input
AN35 TDI TA P Input
AN37 TDO TAP Output
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AH28 THERMTRIP# CMOS Output
AK32 TMS TA P Input
AN25 TRDY# AGTL+ Input
AN33 TRST# TAP Input
AD36 VCC1.5 3Power/Other
Z36 VCC2.5 1Power/Other
AB36 VCCCMOS Power/Other
AA37 VCCCORE Power/Other
AA5 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB34 VCCCORE Power/Other
AD32 VCCCORE Power/Other
AE5 VCCCORE Power/Other
E5 VCCCORE Power/Other
E9 VCCCORE Power/Other
F14 VCCCORE Power/Other
F2 VCCCORE Power/Other
F22 VCCCORE Power/Other
F26 VCCCORE Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
F30 VCCCORE Power/Other
F34 VCCCORE Power/Other
F4 VCCCORE Power/Other
H32 VCCCORE Power/Other
H36 VCCCORE Power/Other
J5 VCCCORE Power/Other
K2 VCCCORE Power/Other
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
M32 VCCCORE Power/Other
N5 VCCCORE Power/Other
P2 VCCCORE Power/Other
P34 VCCCORE Power/Other
R32 VCCCORE Power/Other
R36 VCCCORE Power/Other
S5 VCCCORE Power/Other
T2 VCCCORE Power/Other
T34 VCCCORE Power/Other
V32 VCCCORE Power/Other
V36 VCCCORE Power/Other
W5 VCCCORE Power/Other
X34 VCCCORE Power/Other
Y35 VCCCORE Power/Other
Z32 VCCCORE Power/Other
AF2 VCCCORE Power/Other
AF34 VCCCORE Power/Other
AH24 VCCCORE Power/Other
AH32 VCCCORE Power/Other
AH36 VCCCORE Power/Other
AJ13 VCCCORE Power/Other
AJ17 VCCCORE Power/Other
AJ21 VCCCORE Power/Other
AJ25 VCCCORE Power/Other
AJ29 VCCCORE Power/Other
AJ5 VCCCORE Power/Other
AK2 VCCCORE Power/Other
AK34 VCCCORE Power/Other
AM12 VCCCORE Power/Other
AM16 VCCCORE Power/Other
AM20 VCCCORE Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
58
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
AM24 VCCCORE Power/Other
AM28 VCCCORE Power/Other
AM32 VCCCORE Power/Other
AM4 VCCCORE Power/Other
AM8 VCCCORE Power/Other
B10 VCCCORE Power/Other
B14 VCCCORE Power/Other
B18 VCCCORE Power/Other
B22 VCCCORE Power/Other
B26 VCCCORE Power/Other
B30 VCCCORE Power/Other
B34 VCCCORE Power/Other
B6 VCCCORE Power/Other
C3 VCCCORE Power/Other
D20 VCCCORE Power/Other
D24 VCCCORE Power/Other
D28 VCCCORE Power/Other
D32 VCCCORE Power/Other
D36 VCCCORE Power/Other
D6 VCCCORE Power/Other
E13 VCCCORE Power/Other
E17 VCCCORE Power/Other
AJ9 VCCCORE Power/Other
E21 RESERVE Power/Other
AL35 VID0 Power/Other
AM36 VID1 Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
AL37 VID2 Power/Other
AJ37 VID3 Power/Other
E33 VREF0 Power/Other
F18 VREF1 Power/Other
K4 VREF2 Power/Other
R6 VREF3 Power/Other
V6 VREF4 Power/Other
AD6 VREF5 Power/Other
AK12 VREF6 Power/Other
AK22 VREF7 Power/Other
AH20 VTT Power/Other
AK16 VTT Power/Other
AL13 VTT Power/Other
AL21 VTT Power/Other
AN11 VTT Power/Other
AN15 VTT Power/Other
G35 VTT Power/Other
AA33 VTT 4Power/Other
AA35 VTT 4Power/Other
AN21 VTT 4Power/Other
E23 VTT 4Power/Other
S33 VTT 4Power/Other
S37 VTT 4Power/Other
U35 VTT 4Power/Other
U37 VTT 4Power/Other
Table 29. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet
59
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 30. Signal Listing in Order by Pin
Number
Pin
No. Pin Name Signal Group
A3 D29# AGTL+ I/O
A5 D28# AGTL+ I/O
A7 D43# AGTL+ I/O
A9 D37# AGTL+ I/O
A11 D44# AG TL+ I/O
A13 D51# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
A19 D57# AGTL+ I/O
A21 D46# AGTL+ I/O
A23 D53# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
A29 DEP7# AGTL+ I/O
A31 DEP3# AGTL+ I/O
A33 DEP2# AGTL+ I/O
A35 PRDY# AGTL + Output
A37 GND Power/Other
AA1 A27# AGTL+ I/O
AA3 A30# AGTL+ I/O
AA5 VCCCORE Power/Other
AA33 VTT 4Power/Other
AA35 VTT 4Power/Other
AA37 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB4 A24# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB32 GND Power/Other
AB34 VCCCORE Power/Other
AB36 VCCCMOS Power/Other
AC1 A33# AGTL+ I/O
AC3 A20# AGTL+ I/O
AC5 GND Power/Other
AC33 GND Power/Other
AC35 FERR# CMOS Output
AC37 RSP# AGTL+ Input
AD2 GND Power/Other
AD4 A31# AGTL+ I/O
AD6 VREF5 Power/Other
AD32 VCCCORE Power/Other
AD34 GND Power/Other
AD36 VCC1.5 3Power/Other
AE1 A17# AGTL+ I/O
AE3 A22# AGTL+ I/O
AE5 VCCCORE Power/Other
AE33 A20M# CMOS Input
AE35 IERR# CMOS Output
AE37 FLUSH# CMOS Input
AF2 VCCCORE Power/Other
AF4 A35# AGTL+ I/O
AF6 A25# AGTL+ I/O
AF32 GND Power/Other
AF34 VCCCORE Power/Other
AF36 GND Power/Other
AG1 EDGCTRL 5Power/Other
AG3 A19# AGTL+ I/O
AG5 GND Power/Other
AG33 INIT# CMOS Input
AG35 STPCLK# CMOS Input
AG37 IGNNE# CMOS Input
AH2 GND Power/Other
AH4 RESET# 2AGTL+ Input
AH6 A10# AGTL+ I/O
AH8 A5# AGTL+ I/O
AH10 A8# AGTL+ I/O
AH12 A4# AGTL+ I/O
AH14 BNR# AGTL+ I/O
AH16 REQ1# AGTL+ I/O
AH18 REQ2# AGTL+ I/O
AH20 VTT Power/Other
AH22 RS1# AGTL+ Input
AH24 VCCCORE Power/Other
AH26 RS0# AGTL + Input
AH28 THERMTRIP# CMOS Output
AH30 SLP# CMOS Input
AH32 VCCCORE Power/Other
AH34 GND Power/Other
AH36 VCCCORE Power/Other
AJ1 A21# AGTL+ I/O
AJ3 GND Power/Other
Table 30. Signal List ing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
60
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
AJ5 VCCCORE Power/Other
AJ7 GND Power/Other
AJ9 VCCCORE Power/Other
AJ11 GND Power/Other
AJ13 VCCCORE Power/Other
AJ15 GND Power/Other
AJ17 VCCCORE Power/Other
AJ19 GND Power/Other
AJ21 VCCCORE Power/Other
AJ23 GND Power/Other
AJ25 VCCCORE Power/Other
AJ27 GND Power/Other
AJ29 VCCCORE Power/Other
AJ31 BSEL1 Power/Other
AJ33 BSEL0 Power/Other
AJ35 SMI# CMOS Input
AJ37 VID3 Power/Other
AK2 VCCCORE Power/Other
AK4 GND Power/Other
AK6 A28# AGTL+ I/O
AK8 A 3# AGTL+ I/ O
AK10 A11# AGTL+ I/O
AK12 VREF6 Power/Other
AK14 A14# AGTL+ I/O
AK16 VTT Power/Other
AK18 REQ0# AGTL+ I/O
AK20 LOCK# AGTL+ I/O
AK22 VREF7 Power/Other
AK24 AERR# AGTL+ I/O
AK26 PW RGOOD CM O S Input
AK28 RS2# AGTL+ Input
AK30 Reserved Reserved for future use
AK32 TMS TAP Input
AK34 VCCCORE Power/Other
AK36 GND Power/Other
AL1 GND Power/Other
AL3 GND Power/Other
AL5 A 15# AGTL+ I/O
AL7 A 13# AGTL+ I/O
AL9 A9# A GTL+ I/ O
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
AL11 AP0# AGTL+ I/O
AL13 VTT Power/Other
AL15 A 7# AGTL+ I/O
AL17 R EQ4# A GTL+ I/O
AL19 R EQ3# A GTL+ I/O
AL21 VTT Power/Other
AL23 HITM# AGTL+ I/O
AL25 HIT# AGTL+ I/O
AL27 DBSY # AGTL+ I/O
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AL33 TCK TAP Input
AL35 VID0 Power/Other
AL37 VID2 Power/Other
AM2 6Reserved Reserved for future use
AM4 VCCCORE Power/Other
AM6 GND Power/Other
AM8 VCCCORE Power/Other
AM10 GND Power/Other
AM12 VCCCORE Power/Other
AM14 GND Power/Other
AM16 VCCCORE Power/Other
AM18 GND Power/Other
AM20 VCCCORE Power/Other
AM22 GND Power/Other
AM24 VCCCORE Power/Other
AM26 GND Power/Other
AM28 VCCCORE Power/Other
AM30 GND Power/Other
AM32 VCCCORE Power/Other
AM34 GND Power/Other
AM36 VID1 Power/Other
AN3 GND Power/Other
AN5 A12# AGTL + I/ O
AN7 A16# AGTL + I/ O
AN9 A6# AGTL+ I/ O
AN11 VTT Power/Other
AN13 A P1# A G TL+ I/O
AN15 VTT Power/Other
AN17 BPRI# AGTL+ Input
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet
61
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
AN19 DEFER# A G TL+ Input
AN21 VTT 4Power/Other
AN23 RP# A GTL+ I/O
AN25 TRDY# AGTL+ Input
AN27 DRDY# AGTL+ I/O
AN29 BR0# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AN33 TRST# TAP Input
AN35 TDI TA P Input
AN37 TDO TAP Output
B2 D35# AGTL+ I/O
B4 GND Power/Other
B6 VCCCORE Power/Other
B8 GND Power/Other
B10 VCCCORE Power/Other
B12 GND Power/Other
B14 VCCCORE Power/Other
B16 GND Power/Other
B18 VCCCORE Power/Other
B20 GND Power/Other
B22 VCCCORE Power/Other
B24 GND Power/Other
B26 VCCCORE Power/Other
B28 GND Power/Other
B30 VCCCORE Power/Other
B32 GND Power/Other
B34 VCCCORE Power/Other
B36 BINIT# AGTL+ I/O
C1 D33# AGTL+ I/O
C3 VCCCORE Power/Other
C5 D31# AGTL+ I/O
C7 D34# AGTL+ I/O
C9 D36# AGTL+ I/O
C11 D45# AGTL+ I/O
C13 D49# AGTL+ I/O
C15 D40# AGTL+ I/O
C17 D59# AGTL+ I/O
C19 D55# AGTL+ I/O
C21 D54# AGTL+ I/O
C23 D58# AGTL+ I/O
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
C25 D50# AGTL+ I/O
C27 D56# AGTL+ I/O
C29 DEP5# AGTL+ I/O
C31 DEP1# AGTL+ I/O
C33 DEP0# AGTL+ I/O
C35 BPM0# AGTL+ I/O
C37 CPUPRES# Power/Other
D2 GND Power/Other
D4 GND Power/Other
D6 VCCCORE Power/Other
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
D12 D42# AGTL+ I/O
D14 D41# AGTL+ I/O
D16 D52# AGTL+ I/O
D18 GND Power/Other
D20 VCCCORE Power/Other
D22 GND Power/Other
D24 VCCCORE Power/Other
D26 GND Power/Other
D28 VCCCORE Power/Other
D30 GND Power/Other
D32 VCCCORE Power/Other
D34 GND Power/Other
D36 VCCCORE Power/Other
E1 D26# AGTL+ I/O
E3 D25# AGTL+ I/O
E5 VCCCORE Power/Other
E7 GND Power/Other
E9 VCCCORE Power/Other
E11 GND Power/Other
E13 VCCCORE Power/Other
E15 GND Power/Other
E17 VCCCORE Power/Other
E19 GND Power/Other
E21 RESERVE Power/Other
E23 VTT 4Power/Other
E25 D62# AGTL+ I/O
E27 SLEWCTRL Power/Other
E29 DEP6# AGTL+ I/O
Table 30. Signal List ing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
62
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
E31 DEP4# AGTL+ I/O
E33 VREF0 Power/Other
E35 BPM1# AGTL+ I/O
E37 BP3# AGT L+ I/ O
F2 VCCCORE Power/Other
F4 VCCCORE Power/Other
F6 D32# AGTL+ I/O
F8 D22# AGTL+ I/O
F10 Reserved Reserved for future use
F12 D27# AGTL+ I/O
F14 VCCCORE Power/Other
F16 D63# AGTL+ I/O
F18 VREF1 Power/Other
F20 GND Power/Other
F22 VCCCORE Power/Other
F24 GND Power/Other
F26 VCCCORE Power/Other
F28 GND Power/Other
F30 VCCCORE Power/Other
F32 GND Power/Other
F34 VCCCORE Power/Other
F36 GND Power/Other
G1 D21# AGTL+ I/O
G3 D23# AGTL+ I/O
G5 GND Power/Other
G33 BP2# AGTL+ I/O
G35 VTT Power/Other
G37 Reserved Reserved for future use
H2 GND Power/Other
H4 D16# AGTL+ I/O
H6 D19# AGTL+ I/O
H32 VCCCORE Power/Other
H34 GND Power/Other
H36 VCCCORE Power/Other
J1 D7# A GTL+ I/O
J3 D30# AGTL+ I/O
J5 VCCCORE Power/Other
J33 PI CCLK APIC Clock Input
J35 PICD0 AP IC I/O
J37 P REQ# CMOS Input
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
K2 VCCCORE Power/Other
K4 VREF2 Power/Other
K6 D24# AGTL+ I/O
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
K36 GND Power/Other
L1 D13# AGTL+ I/O
L3 D20# AGTL+ I/O
L5 GND Power/Other
L33 Reserved Res erved for future use
L35 PICD1 APIC I/O
L37 LINT1/NMI CMOS Input
M2 GND Power/Other
M4 D11# AGTL+ I/O
M6 D3# AGTL+ I/O
M32 VCCCORE Power/Other
M34 GND Power/Other
M36 LINT0/INTR CMOS Input
N1 D2# A GTL+ I/O
N3 D14# AGTL+ I/O
N5 VCCCORE Power/Other
N33 Reserved Res erved for future use
N35 Reserved Res erved for future use
N37 Reserved Res erved for future use
P2 VCCCORE Power/Other
P4 D18# AGTL+ I/O
P6 D9# A GTL+ I/O
P32 GND Power/Other
P34 VCCCORE Power/Other
P36 GND Power/Other
Q1 D12# AGTL+ I/O
Q3 D10# AGTL+ I/O
Q5 GND Power/Other
Q33 Reserved Reserved for future use
Q35 Reserved Reserved for future use
Q37 Reserved Reserved for future use
R2 Res erved Reserved for future use
R4 D17# AGTL+ I/O
R6 VREF3 Power/Other
R32 VCCCORE Power/Other
Table 30. Signal Listing in Order by Pin
Number (Continued)
Pin
No. P in Name Signal Group
Datasheet
63
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
R34 GND Power/Other
R36 VCCCORE Power/Other
S1 D8# AGTL+ I/O
S3 D5# AGTL+ I/O
S5 VCCCORE Power/Other
S33 VTT 4Power/Other
S35 RTTCTRL Power/Other
S37 VTT 4Power/Other
T2 VCCCORE Power/Other
T4 D1# AGTL+ I/O
T6 D6# AGTL+ I/O
T32 GND Power/Other
T34 VCCCORE Power/Other
T36 GND Power/Other
U1 D4# AGTL+ I/O
U3 D15# AGTL+ I/O
U5 GND Power/Other
U33 PLL2 Power/Other
U35 VTT 4Power/Other
U37 VTT 4Power/Other
V2 GND Power/Other
V4 BERR# AGTL+ I/O
V6 VREF4 Power/Other
V32 VCCCORE Power/Other
V34 GND Power/Other
Table 30. Signal Listing in Ord er by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
V36 VCCCORE Power/Other
W1 D0# AGTL+ I/O
W3 A34# AGTL+ I/O
W5 VCCCORE Power/Other
W33 PLL1 Power/Other
W35 Reserved Reserved for future use
W37 BCLK System Bus Clock
X2 BR1#8AGTL+ input
X4 RESET2# 2A GTL+ I/O
X6 A32# AGTL+ I/O
X32 GND Power/Other
X34 VCCCORE Power/Other
X36 GND Power/Other
Y1 Reser ved Reserv ed for future use
Y3 A26# AGTL+ I/O
Y5 GND Power/Other
Y33 CLKRE F 7Power/Other
Y35 VCCCORE Power/Other
Y37 GND Power/Other
Z2 GND Power/Other
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 VCCCORE Power/Other
Z34 GND Power/Other
Z36 VCC2.5 1Power/Other
Table 30. Signal List ing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
64
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.0 Boxed Processor Specifications
The Intel® Pentium® III processor for the PGA370 socket is also offered as an Intel boxed
processor. Intel boxed processors are intended for system integrators who build systems from
motherboards and standar d co mpo nents. The b oxed Pentium® III pr ocessor f or the PGA370 socket
will be supplied with an unattached fan heatsink. This section documents motherboard and system
requirements for the fan heatsink that will be supplied with the boxed Pentium III processor. This
section is particularly important for OEMs that manufacture motherboards for system integrators.
Unless otherwis e noted, all figures in this section are dimensi one d in inches. Figu re 22 shows a
mechanical representation of the box ed Intel Pentium ® III processor for the PGA370 socket in the
Flip Chip Pin Grid Array (FC-PGA) pack age.
Note: Drawings in this section reflect only the specifications on the Intel Boxed Processor product. These
dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system
designer’ s responsibility to consider their proprietary solution whe n designing to the required keep-
out zone on their system platform and chassis. Refer to the Intel® Pentium®
III
Processor Thermal/
Mechanical Functional Specifications for further guidance. Contact your local Intel Sales
Represent a tive for this doc ument.
6.1 M echanical Specifications for the Boxed Intel® Pentium® III
Processor
6.1.1 Boxed Processor Thermal Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed Intel Pentium processor fan
heatsink in the FC-PGA package. The boxed processor in the FC-PGA package ships with an un-
attached fan heatsink. Figure 22 shows a mechanical representation of the boxed Intel Pentium III
processor for the PGA370 socket in the Flip Chip Pin Grid Array (FC-PGA) package.
The dimensions for the boxed processor with integrated fan heatsink are shown in Figure 23,
Figure 24, and Figure 25. There are three versions of the fan heatsink. The smallest solution is
shown in Figure 23 for 500 to 850MHz. The larger cooling solution Figure 24 is required for
Pentium III processors at frequencies of 866 to 933MHz. Figure 25 is the largest boxed processor
fan heatsink and is used for 1 GHz Pentium® III processor. General spatial specifications are also
outlined in Table 31. All dimensions are in in ches unless otherwise noted.
Figure 22. Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket
Datasheet
65
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
The fan heatsink is designed t o allow visibility of the FC-PGA processor markings located on top
of the package. The FC-PGA processor markings are visible after installation of the fan heatsink
due to notched sides of the heatsink base (specified in Fi gure 2 7). The boxed p rocessor fan heatsink
is also asymmetrical in that the mechanical step feature (specified in Figure 26) must sit over t he
socket’s cam. The step allows the heatsink to securely interface with the processor in order to meet
thermal requirements.
Note: The heatsink airflow keepout zones found in Table 31 and Figure 29 refer specifically to the
boxed processor’s active fan heatsink. This does not reflect the worst-case dimensions that may
exist with other third party passive or active fan heatsinks.
Figure 23. Space Requirements for the Boxed Processor to 850MHz
Figure 24. Space Requirements for the Bo xed Processor from 866 to 933MHz
66
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 25. Space Requirements for the Boxed Processor at 1 GHz
Table 31. Boxed Processor Fan Heatsink Spatial Dimensionsa
a. Drawings re flect only the specifica tion of the Intel boxed processor product. These dimensions should not be used
as a universal keepout zone that covers all heatsinks. It is the system designer’s responsibility to consider their
own proprietary sol ution when designing the desir ed keepout zone in their system platform.
Dimensions (Inches) Min Typ Max
Fan Heatsink Length (see figure 23) 2.52
Fan Heatsink for 866 to 933 MHz Length (figure 24) 2.68
Fan Heatsink Length for 1 GHz (see figure 25) 3.17
Fan Heatsink Height (see figure 23) 1.75
Fan Heatsink for 866 to 933 MHz Height (figure 24) 1.78
Fan Heatsink Height for 1 GHz (see figure 25) 1.89
Fan Heatsink Width (see figure 23) 2.00
Fan Heatsink for 866 to 933 MHz Width (figure 24) 2.65
Fan Heatsink Width for 1 GHz (see figure 25) 2.65
Dimensions (Inches) Min Typ Max
Fan Heatsink height above motherboard for all
frequencies .30 .29 .33
Air Keepout Zones from end of Fan Heatsink for all
frequencies .20
Figure 26. Dimensions of Mechanical Step Feature in Heatsink Base
0.472
0.043
Datasheet
67
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.1.2 Boxed Processor Heatsink W eight
The boxed processor thermal cooling solution will not weigh more than 180 grams.
6.1.3 Boxed Processor Thermal Cooling Solution Clip
The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling s olution t o the processor after it is installed in the 370-pin socket ZIF socket.
Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach
tabs in a way that interferes with the installation of the boxed p rocessor thermal cooling solution
(see Figure 28 for specification).
Figure 27. Dimensions of Notches in Heatsink Base
68
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.2 Thermal Specifications
This section de scribes the cooling requirements of the thermal cooling solution utilized by th e
boxed processor.
6.2.1 Boxed Processor Cooling Requirements
The boxed processor is directly cooled with a fan heatsink. However, meeting the processor’s
temperature specif ication is also a function of the therm al design of the entire system, an ultimately
the responsibility of the system integrator. The processor temperature specification is found in
[Section 4.0] of this document. The boxed processor fan heatsink will keep the pro cessor core at
the recommended specifications (see Table 24) in chassis that provide good thermal management.
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of
the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink red uces the coo ling efficiency and
decreases fan life. Table 31 and Figure 29 illustrate an acceptable airspace clearance for the fan
heatsink. It is also recommended that the air temperature entering the fan be kept below 45ο C.
Meeting the pr ocessor’ s temperature specification is the responsibility of the system inte grator . The
processor temperature specification is found in [Section 4.0] of this d ocument.
Figure 28. Clip Keepout Requirements for the PGA370 (Top View)
Datasheet
69
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
6.3 Electrical Requirements for the Boxed Intel® Pentium® III
Processor
6.3.1 Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is attached
to the fan and will draw power from a power header on the motherboard. The power cable
connector and pinout are shown in Fig ure 30 . Moth erboards must provide a mat ched po wer h eader
to support the boxed processor. Table 32 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE (open-collector output) signal that
pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH to
match th e mo therboard-mou nt ed f a n s peed mon i to r r e quirements, if ap pli cabl e. Us e of t he S ENS E
signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard. Figure 31 shows the recommended location of the fan
power connector relative to the PGA370 socket. The motherboard power header should be
positioned within 4.00 inches (lateral) from the center of the PGA370 socket.
Figure 29. Thermal Airspace Requirement for all Boxed Intel® Pent ium® III Processor Fan
Heatsinks in the PGA370 Socket
Measure ambient temperature 0.3"
above center of fan inlet
0.20 Min
Air Space
0.20 Min
Air Space
Fan Heatsink
Processor
arsp1.vsd
70
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Figure 30. Boxed Processor Fan Heatsink Power Cable Connector Description
Table 32. Fan Heatsink Po wer and Signal Specifications
Description Min Typ Max
+12 V: 12 volt fan power supply 10.8 V 12 V 13.2 V
IC: Fan current draw 100 mA
SENSE: SENSE frequency (motherboard should pull this
pin up to appropriate VCC with resistor) 2 pulses per
fan revolution
Figure 31. Motherboard Power Header Placement Relative to the Boxed Intel® Pent ium® III
Processor
Pin Signal
Straight square pin, 3-pin terminal h ousing with
polarizing ribs and friction locking ramp.
0.100" pin pitch, 0.025" square pin width.
Waldom/Molex P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,
or equivalent.
1
2
3
GND
+12V
SENSE
123
0.10"
Socket 7
0.10"
R = 4.00”
PGA370
Datasheet
71
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
7.0 Processor Signal Description
This section provides an alphabetical listing of all the Intel® Pentium® III processor signals. The
tables at the end of this section summarize the signals by direction: output, input, and I/O.
7.1 Alphabetical Signals Reference
Table 33. Signal Description (Sheet 1 of 8)
Name Type Description
A[35:3]# I/O
The A[35:3]# (Address) signals define a 236-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
pins to determine their power-on configuration. See the Intel®
Pentium
®
II
Processor Developer’s Manual
for details.
A20M# I
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS# I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
AERR# I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
AP[1:0]# I/O
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the appropriate pins
of all processor system bus agents.
BCLK I
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
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Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
BERR# I/O
The BERR# (Bus Error) signal i s asserted to indicate an unrecoverable error without
a bus protocol violation. It may be driven by all processor sys tem bus agents, and
must connect the appropriate pins of all such agents, if used. However , Pentium III
processors do not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
• Enabled or di sa bl ed.
• Asserted optionally for int e rnal errors along with IE RR#.
• Asserted optionally by the request initiator of a bus transaction after it observes an error.
• Assert ed b y any bus agent w h e n it o bs erves an error in a bus transaction.
BINIT# I/O
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled assert ed, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not affected.
If BINIT# observation i s disabled during power-on configuration, a central agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of
the system.
BNR# I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same ti me, BNR# is a
wire-OR signal which must connect the appropriate pins of al l processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by mul tiple drivers, BNR# is act ivated on specific clock edges and
sampled on specif ic clock edges.
BP[3:2]# I/O The BP[3:2]# (Breakpoint) signals are outputs from t he processor that indicate the
status of breakpoints.
BPM[1:0]# I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are output s from the processor which indicat e the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPRI# I
The BPRI# (Bus Priority Request) signal is used to arbi trate for ownership of the
processor syst em bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
Table 33. Signal Description (Sheet 2 of 8)
Name Type Description
Datasheet
73
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
BR0#
BR1# I/O
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BSEL[1:0] I/O
These signals are used to select the system bus frequency. A BSEL[1:0] = “01”
selects a 100 MHz system bus frequency and a BSEL[1:0] = “1 1” selects a 133 MHz
system bus frequency. The f r equency is determined by the processor(s), chipset,
and frequency synthesi zer capabilities. All system bus agents must operate at the
same frequency. The Pentiu m III processor for the PGA370 socket operates at 100
MHz and 133 MHz system bus frequencies. Individual processors will only operate
at their specified front side bus (FSB) frequency. Either 100 MHz or 133 MHz, not
both.
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 Mhz system bus frequency. 66 MHz operation is
not support by the Pentium III pr ocessor for the PGA370 socket; therefore, BSEL0 is
ignored.
These signals must be pulled up to 2.5 V or 3.3V with 1 KΩ resistors and provided
as a frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operat ing at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See Section 2.8.2 for
implementation examples.
CLKREF I The CLKREF input is a filtered 1.25V supply voltage for the processor PLL. A
voltage divider and decoupling solution is provided by the motherboard. See the
design guide for implementation details.
Table 33. Signal Description (Sheet 3 of 8)
Name Type Description
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate
bus signal protocol, as shown below.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal Agent 0 Pins Agent 1 Pins
BREQ0# BR0# BR1#
BREQ1# BR1# BR0#
BR[1:0]# Signal Agent IDs
Pin Sampled Active in RESET# Agent ID
BR0# 0
BR1# 3
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Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
CPUPRES# O
The CPUPRES# signal is defined to allow a system design to detect the presence of
a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[3:0]= 1 111 (see Section 2.6), a syst em can determine if a socket
is occupied, and whether a processor core is present. See the t able below for states
and values for determining the presence of a device.
D[63:0]# I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY# I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
DEFER# I
The DEFER# si gnal is asserted by an agent to indicate that a transacti on cannot be
guaranteed in-order completion. Assert ion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEP[7:0]# I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor sy stem bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DRDY# I/O
The DRDY# (Dat a Ready) signal is asserted by the data dri ver on each data
transfer, indicating valid dat a on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
EDGCTRL O
The EDGCTRL input adjusts the edge rate of AGTL+ output buffers for previous
processors and should be pulled up to VCCCORE with a 51 Ω ±5% resistor. See the
platform design guide for implementation details. This signal is not used by the
Pentium III processor.
FERR# O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
Table 33. Signal Description (Sheet 4 of 8)
Name Type Description
PGA370 Socket Occupation Truth Table
Signal Value Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0] 0
1111 Term inator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[3:0] 1
Any va lue PGA370 soc ket not occupied.
Datasheet
75
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
FLUSH# I
When the FLUSH# input signal is asserte d, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new dat a while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to
determine its power-on configuration. See the
P6 Family of Processors Hardware
Developer ’s Manual
for details.
HIT#
HITM# I/O
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR# O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Asser tion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may opt ionally be
converted to an external error signal (e.g., NMI) by system core logic. The processor
will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IGNNE# I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floati ng-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
INIT# I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle snoop
requests during INIT# assert ion. INIT# is an asynchronous signal and must connect
the appropriate pins of all processor sy stem bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
LINT[1:0] I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all proc essors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Intel®Pentium
®
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI /INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it wil l wait until it observes LOCK# deasserted. This enables symmet ric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
Table 33. Signal Description (Sheet 5 of 8)
Name Type Description
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Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
PICCLK I The PICCLK (APIC Cl ock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICD[1:0] I/O The PICD[1:0] (APIC Data) signals are used for bidirectiona l serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PLL1, PLL2 I
All Pentium III processors have an internal analog PLL clock generator that requires
a quiet power supply. PLL1 and PLL2 are inputs to thi s PLL and must be connected
to VCCCORE through a low pass filter that minimizes jitter. See the platform design
guide for implementation details.
PRDY# O The PRDY (Probe Ready ) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ# I The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
PWRGOOD I
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (VCCCORE,
etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of si nking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high st ate. The figure bel ow illustr ates the
relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in Table 13, and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# I/O The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
RESET# I
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCCCORE and
CLK have reached their proper specifications. On observing active RESET#, all
processor syst em bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Deve loper’s Manual
for details.
The processor may have its outputs tristated via power-on confi guration. Otherwise,
if INIT# is sampled active during the act ive-to-inactive transi tion of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor
system bus agents.
RESET2# I The RESET2# pin is provided for compatibility with other Intel Architecture
processors. The Pentium III processor does not use the RESET2# pin. Refer to the
platform design guide for the proper connections of this signal.
RP# I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all
processor syst em bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
RS[2:0]# I The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
Table 33. Signal Description (Sheet 6 of 8)
Name Type Description
Datasheet
77
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
RSP# I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
RTTCTRL I The RTTCTRL input signal provides AGTL+ termination control. The Pentium III
processor samples this input to sense the presence of motherboard AGT L+
termination. See the platform design guide for implementation details.
SLEWCTRL I The SLEWCTRL input signal provides AGTL+ slew rate control. The Pentium I II
processor samples thi s input to determine the slew rate for AGTL+ signals when it is
the driving agent. See the platform design guide for implementation details.
SLP# I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or int errupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SMI# I
The SMI# (System Managem ent Interrupt) signal is asserted asy nchronous ly by
system logic. On accepting a System Management Interrupt, processors save the
current state and ent er System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK# I
The STPCLK# (St op Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The proce ssor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
TCK I The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI I The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO O The TDO (Test Data Out) signal transfers serial t est data out of the processor. TDO
provides the serial output needed f or JTAG specification support.
THERMDN O Thermal Diode Cathode. Used to calculate core (juncti on) temperature. See Section
4.1.
THERMDP I Thermal Diode Anode. Used to calculate core (junction) temperature. See Sec tion
4.1.
THERMTRIP# O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
Table 33. Signal Description (Sheet 7 of 8)
Name Type Description
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Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
7.2 Signal Summaries
Table 34 through Table 37 list attributes of the processo r output, input, and I/O signals.
TMS I The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY# I The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRST# I The TRST# (Test Reset) signal resets the Test Access Port (TAP ) logic. TRST#
must be driven low during power on Reset.
VID[3:0] O
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on process ors. See Table 2 for definitions of these
pins. The power suppl y must supply the voltage that is requested by t hese pins, or
disable itself.
VCOREDET OThe VCOREDET pin indicate the type of processor core present. This pin will float for
2.0 V V CCCORE based processor and will be shorted to VSS for the Pentium III
processor.
VCC1.5 I
The VCC1.5 V input pin provides the termination voltage for CMOS signals
interfacing to the processor . The Pentium II I processor reroutes the 1.5V input to the
VCCCMOS output via the package. The supply for VCC1.5 V must be the same one
used to supply VTT.
VCC2.5 I
The VCC2.5 V input pin provides the termination voltage for CMOS signals
interfacing to processors which require 2.5V termination on the CMOS signals. T his
signal is not used by the Pentium III processor.
VCCCMOS OThe VCCCMOS pin provides the CMOS voltage for use by the platform and is used for
terminating CMOS signals that interface to the processor.
VREF IThe VREF input pins supply the AGTL+ reference voltage, which is typically 2/3 of
VTT. VREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
logical 1.
Table 33. Signal Description (Sheet 8 of 8)
Name Type Description
Table 34. Output Signals
Name Active Level Clock Signal Group
CPUPRES# Low Asynch Power/Other
EDGCTRL N/A Asynch Power/Other
FERR# Low Asyn ch CMOS Output
IERR# Low Asynch CM OS Output
PRDY# Low BCLK AGTL+ Output
TDO High TCK TAP Output
THERMTRIP# Low Asynch CMOS Output
VCOREDET N/A Asynch Power/Other
VID[3:0] N/A Asynch Power/Other
Datasheet
79
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTE:
1. S ynchronous assertion with active TDRY# ensures synchronization.
Table 35. Input Signals
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Input Always1
BCLK High — System Bus Clock A lways
BPRI# Low BCLK AGTL+ Input Always
BR1# Low BCLK AG TL+ Input Always
DEFER# Low BCLK AG TL+ Input Always
FLUSH# Low Asynch CMOS Input Always1
IGNNE# Low Asynch CMOS Input Always1
INIT# Low Asynch CMOS Input Always1
INTR High As ynch CMOS Input AP IC disabled mode
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMO S Input Always
PWRGOOD High Asynch CMOS Input Always
RESET# Low B CLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RSP# Low B CLK AGTL+ Input Always
RTTCTRL N/A Asynch Power/Other
SLEWCTRL N/A Asynch Power/Other
SLP# Low Asynch CM OS Input During Sto p-Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High — TAP Input
TDI High TCK TAP Input
TMS High TCK TAP Input
TRST# Low Asynch TA P Input
TRDY# Low BCLK A GTL+ Input
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Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1 GHz
Table 36. Input/Output Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:3]# Low BCLK AGTL+ I/O ADS#, ADS#+1
ADS# Low B CLK AGTL+ I/O Always
AP[1:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
BP[3:2]# Lo w BC L K AGTL + I/O A lways
BPM[1:0]# Low BCLK AGTL+ I/O A lways
BR0# Low BCLK AGTL+ I/O A lways
BSEL[1:0] High Asynch Power/Other Always
D[63:0]# Low BCLK AGTL+ I/O DRDY#
DBSY# Low B CLK A G TL+ I/O Alw ays
DEP[7:0]# Low BCLK AGTL+ I/O DRDY#
DRDY# Low BCLK AGTL+ I/O Always
LOCK# Low BCLK AGTL+ I/O Always
REQ[4:0]# Low BCLK AGT L+ I/O ADS#, ADS#+1
RP# Low BCLK AGT L+ I/O ADS#, ADS#+1
Table 37. Input/Output Signals (Multiple Driver )
Name Active Level Clock Signal Group Qualified
AERR# Low BCLK AGTL+ I/O ADS#+3
BERR# Low BCLK AGTL+ I/O Alway s
BINIT# Low B CLK A GTL+ I/O Always
BNR# Low BCLK AGTL+ I/O Always
HIT# Low B CLK AG TL+ I/O Always
HITM# Low BCLK AGTL+ I/O Always
PICD[1:0] High PICCLK APIC I/O Always
