UC1525A/27A UC2525A/27A UC3525A/27A Regulating Pulse Width Modulators FEATURES DESCRIPTION * 8 to 35V Operation The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF. * 5.1V Reference Trimmed to 1% * 100Hz to 500kHz Oscillator Range * Separate Oscillator Sync Terminal * Adjustable Deadtime Control * Internal Soft-Start * Pulse-by-Pulse Shutdown * Input Undervoltage Lockout with Hysteresis * Latching PWM to Prevent Multiple Pulses * Dual Source/Sink Output Drivers BLOCK DIAGRAM OS C VREF OUT 16 GROUND 12 3 RT 6 5 DIS CHARGE 7 VC 11 OUTP UT A 14 OUTP UT B 13 VC 11 OUTP UT A 14 OUTP UT B To inte rna l circuitry Flip Flop OS C CT 13 NOR UVLO Lockout Re fe re nce Re gula tor +VIN 15 S YNC 4 NOR UC1525A Output S ta ge COMP COMP ENS ATION 9 INV INP UT 1 NI INP UT 2 S OFTS TART 8 Error Amp VREF S R P WM La tch OR S 50 A OR 3 k S HUTDOWN 10 5 k UC1527A Output S ta ge SLUS191A - February 1997 - Revised April 2004 UC1525A/27A UC2525A/27A UC3525A/27A RECOMMENDED OPERATING CONDITIONS (Note 3) ABSOLUTE MAXIMUM RATINGS(Note 1) Supply Voltage, (+VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA = +25C (Note 2). . . . . . . . . . 1000mW Power Dissipation at TC = +25C (Note 2) . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . -55C to +150C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . +300C Note 1: Values beyond which damage may occur. Note 2: Consult packaging Section of Databook for thermal limitations and considerations of package. Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V Collector Supply Voltage (VC). . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range. . . . . . . . . . . . . . 100Hz to 400kHz Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . 2k to 150k Oscillator Timing Capacitor . . . . . . . . . . . . . . . .001F to .01F Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 500 Operating Ambient Temperature Range UC1525A, UC1527A . . . . . . . . . . . . . . . . . . -55C to +125C UC2525A, UC2527A . . . . . . . . . . . . . . . . . . . -25C to +85C UC3525A, UC3527A . . . . . . . . . . . . . . . . . . . . . 0C to +70C Note 3: Range over which the device is functional and parameter limits are guaranteed. CONNECTION DIAGRAMS DIL-16 (TOP VIEW) J or N Package PLCC-20, LCC-20 (TOP VIEW) Q, L Package PACKAGE PIN FUNCTION FUNCTION PIN N/C 1 Inv. Input 2 N.I. Input 3 SYNC 4 OSC. output 5 N/C 6 CT 7 RT 8 Discharge 9 Softstart 10 N/C 11 Compensation 12 Shutdown 13 Output A 14 Ground 15 N/C 16 VC 17 Output B 18 +VIN 19 VREF 20 2 UC1525A/27A UC2525A/27A UC3525A/27A ELECTRICAL CHARACTERISTICS:+VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ. PARAMETER TEST CONDITIONS UC1525A/UC2525A UC1527A/UC2527A UC3525A UC3527A UNITS MIN TYP MAX MIN TYP MAX 5.05 5.00 Reference Section Output Voltage TJ = 25C 5.10 5.15 5.10 5.20 V Line Regulation VIN = 8 to 35V 10 20 10 20 mV mV Load Regulation IL = 0 to 20mA 20 50 20 50 Temperature Stability (Note 5) Over Operating Range 20 50 20 50 Total Output Variation (Note 5) Line, Load, and Temperature 5.25 V Shorter Circuit Current VREF = 0, TJ = 25C 80 100 80 100 mA Output Noise Voltage (Note 5) 10Hz 10kHz, TJ = 25 C 40 200 40 200 Vrms Long Term Stability (Note 5) TJ = 125C 20 50 20 50 mV 2 6 2 6 % 0.3 1 1 2 % 6 3 5.00 5.20 4.95 Oscillator Section(Note 6) Initial Accuracy (Notes 5 & 6) TJ = 25C Voltage Stability (Notes 5 & 6) VIN = 8 to 35V Temperature Stability (Note 5) Over Operating Range Minimum Frequency RT = 200k, CT = 0.1F Maximum Frequency RT = 2k, CT = 470pF Current Mirror IRT = 2mA 3 120 400 Clock Amplitude (Notes 5 & 6) Clock Width (Notes 5 & 6) TJ = 25C Sync Threshold Sync Input Current % Hz 400 1.7 2.0 3.0 3.5 0.3 0.5 1.2 2.0 1.0 Sync Voltage = 3.5V 6 120 2.2 kHz 1.7 2.0 3.0 3.5 2.2 mA 1.0 0.3 0.5 1.0 s 2.8 1.2 2.0 2.8 V 2.5 1.0 2.5 mA 0.5 5 2 10 mV 1 10 1 10 A 1 A V Error Amplifier Section (VCM = 5.1V) Input Offset Voltage Input Bias Current Input Offset Current 1 DC Open Loop Gain RL 10M 60 75 60 75 dB Gain-Bandwidth Product (Note 5) AV = 0dB, TJ = 25C 1 2 1 2 MHz DC Transconductance (Notes 5 & 7) TJ = 25C, 30k RL 1M 1.1 1.5 1.1 1.5 mS Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V 3.8 5.6 3.8 5.6 V Common Mode Rejection VCM = 1.5 to 5.2V 60 75 60 75 dB Supply Voltage Rejection VIN = 8 to 35V 50 60 50 60 dB Note 5: These parameters, although ensured over the recommended operating conditions, are not 100% tested in production. Note 6: Tested at fOSC = 40kHz (RT = 3.6kW, CT = 0.01mF, RD = 0W). Approximate oscillator frequency is defined by: 1 f = C T (0.7RT + 3R D ) Note 7: DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded. 3 UC1525A/27A UC2525A/27A UC3525A/27A ELECTRICAL CHARACTERISTICS:+VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ. PARAMETER TEST CONDITIONS UC1525A/UC2525A UC1527A/UC2527A MIN TYP 45 49 MAX UC3525A UC3527A MIN TYP 45 49 UNITS MAX PWM Comparator Minimum Duty-Cycle 0 Maximum Duty-Cycle (Note 6) Input Threshold (Note 6) Zero Duty-Cycle 0.7 Maximum Duty-Cycle 0.9 0 0.7 % % 0.9 V 3.3 3.6 3.3 3.6 V .05 1.0 .05 1.0 A 25 50 80 25 50 80 A 0.4 0.7 0.4 0.7 V 0.6 0.8 1.0 0.6 0.8 1.0 V Input Bias Current (Note 5) Shutdown Section Soft Start Current VSD = 0V, VSS = 0V Soft Start Low Level VSD = 2.5V Shutdown Threshold To outputs, VSS = 5.1V, TJ = 25C Shutdown Input Current VSD = 2.5V 0.4 1.0 0.4 1.0 mA Shutdown Delay (Note 5) VSD = 2.5V, TJ = 25C 0.2 0.5 0.2 0.5 s ISINK = 20mA 0.2 0.4 0.2 0.4 V ISINK = 100mA 1.0 2.0 1.0 2.0 V Output Drivers(Each Output) (VC = 20V) Output Low Level Output High Level ISOURCE = 20mA 18 19 18 19 V ISOURCE = 100mA 17 18 17 18 V Under-Voltage Lockout VCOMP and VSS = High 6 7 6 7 VC OFF Current (Note 7) VC = 35V Rise Time (Note 5) CL = 1nF, TJ = 25C 100 600 100 600 ns Fall Time (Note 5) CL = 1nF, TJ = 25C 50 300 50 300 ns VIN = 35V 14 20 14 20 mA 8 200 8 V 200 A Total Standby Current Supply Current Note 5: These parameters, although ensured over the recommended operating conditions, are not 100% tested in production. Note 6: Tested at fOSC = 40kHz (RT = 3.6kW, CT = 0.01mF, RD = 0W) Note 7: Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A. 4 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS UC1525A/27A UC2525A/27A UC3525A/27A UC1525A output circuit (1/2 circuit shown). UC1525A output saturation characteristics. For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. The low source impedance of the output drivers provides rapid charging of power FET Input capacitance while minimizing external components. Low power transformers can be driven by the UC1525A. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. 5 UC1525A/27A UC2525A/27A UC3525A/27A UC1525A oscillator schematic. PRINCIPLES OF OPERATION AND TYPICAL CHARAC- PWM latch is immediately set providing the fastest TERISTIC SHUTDOWN OPTIONS turn-off signal to the outputs; and a 150A-current sink (See Block Diagram) begins to discharge the external soft-start capacitor. If the Since both the compensation and soft-start terminals shutdown command is short, the PWM signal is termi(Pins 9 and 8) have current source pull-ups, either can nated without significant discharge of the soft-start careadily accept a pull-down signal which only has to sink a pacitor, thus, allowing, for example, a convenient maximum of 100A to turn off the outputs. This is subject implementation of pulse-by-pulse current limiting. Holding to the added requirement of discharging whatever exter- Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on nal capacitance may be attached to these pins. upon release. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the avail- Pin 10 should not be left floating as noise pickup could able shutdown options. Activating this circuit by applying conceivably interrupt normal operation. a positive signal on Pin 10 performs two functions; the Oscillator Charge Time vs RT and CT. Oscillator Discharge Time vs RD and CT. 6 UC1525A/27A UC2525A/27A UC3525A/27A RL is impedance from pin 9 to ground. Values below 30k will begin to limit the maximum duty cycle. Maximum value RD vs minimum value RT. Error amplifier voltage gain and phase vs frequency. Lab test fixture. 7 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-89511012A ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC 5962-89511032A ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC 5962-8951103EA ACTIVE CDIP J 16 1 None 5962-89511042A ACTIVE LCCC FK 20 1 None 5962-8951104EA ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC Lead/Ball Finish A42 SNPB MSL Peak Temp (3) Level-NC-NC-NC POST-PLATE Level-NC-NC-NC UC1525AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1525AJ883B ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1525AL ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC UC1525AL/81197 ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC UC1525AL883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC UC1527AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC A42 SNPB Level-NC-NC-NC UC1527AJ883B ACTIVE CDIP J 16 1 None UC1527AL883B ACTIVE LCCC FK 20 1 None UC2525ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2525ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC2525AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC2525AJ/81046 ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC2525AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA POST-PLATE Level-NC-NC-NC UC2525AQ ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UC2525AQTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR UC2525BDW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2525BJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC2525BN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA UC2527AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA UC3525ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC3525ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC3525AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC3525AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA UC3525AQ ACTIVE PLCC FN 20 46 None CU SNPB Level-2-220C-1 YEAR UC3525AQTR ACTIVE PLCC FN 20 1000 None CU SNPB Level-2-220C-1 YEAR UC3527AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC3527AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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