1 GSPS143.3 V CMOS AD9910 1 GSPS(400 MHz) 1 GSPS14DAC 0.23 Hz -125 dBc/Hz(1 kHz400 MHz) >80 dB SFDR /(I/O) (LO) // 8 FM Sin(X)/(X)() 1.8 V3.3 V / 100TQFP_EP 1024x32RAM PLL REFCLK AD9910 HIGH SPEED PARALLEL DATA INTERFACE LINEAR RAMP GENERATOR 1GSPS DDS CORE 14-BIT DAC 1024ELEMENT RAM TIMING AND CONTROL SERIAL CONTROL DATA PORT 06479-001 REFCLK MULTIPLIER 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2008 Analog Devices, Inc. All rights reserved. ADIADIADI AD9910 ................................................................................................... 1 ! ................................................................................................... 1 PLL ................................................................................. 27 ........................................................................................... 1 (OSK) .................................................................... 27 ........................................................................................... 4 ! OSK ................................................................................ 27 ................................................................................................... 5 ! OSK ................................................................................ 28 ........................................................................................... 6 (DRG) ............................................................... 28 .................................................................................. 6 DRG ................................................................................ 28 ............................................................................. 9 DRG ....................................................................... 30 .................................................................................. 9 DRG ....................................................................... 30 ESD ................................................................................... 9 DRG .................................................................. 30 PLL ................................................... 27 ................................................................... 10 ! ....................................................................... 30 ................................................................................ 13 ! ................................................................... 32 ........................................................................................ 16 DROVER ....................................................................... 32 ........................................................................................ 17 RAM ....................................................................................... 33 ! ....................................................................... 17 RAM ............................................................................... 33 RAM ...................................................................... 18 RAM/ ............................................................ 33 ! .............................................................. 19 RAM)* .................................................. 33 ! ...................................................... 20 RAM_SWP_OVR)RAM* ........................... 34 ! !!(PDCLK) ................................................... 20 RAM .............................................................. 34 ! !!(TxENABLE) .................................................... 21 RAM .............................................................. 34 ! ............................................................................ 22 ! RAM ................................................ 35 ................................................................................ 23 RAM .................................................................. 35 DDS ................................................................................ 23 RAMProfile ..................................... 36 14DAC ....................................................................... 23 ! Profile ...................................... 38 ! !!DAC ............................................................................ 24 RAM .............................................................. 38 ! sinc ......................................................................... 24 RAM ..................................................... 39 ! (REF_CLK/REF_CLK) ........................................ 24 RAM .............................................................. 41 REF_CLK/REF_CLK ............................................... 24 ........................................................................................ 42 ! !!REF_CLK/REF_CLK ....................................... 25 Profile ...................................................................................... 42 ! !!REF_CLK/REF_CLK ....................................... 25 I/O_UPDATESYNC_CLK ............... 42 ! !!(PLL) ......................................................... 25 ! PLL ......................................................................... 26 Rev. B | Page 2 of 64 I/O .......................................................................... 43 AD9910 ! ................................................................................ 43 ! !!/(I/O_RESET) .......................................... 49 .................................................................................... 44 ! !!/(I/O_UPDATE) ...................................... 49 ........................................................................................ 47 ! I/O ..................................................................... 49 3.3 V ................................................................................ 47 MSB/LSB ........................................................................ 49 DVDD_I/O (3.3V))11/15/21/28/45/56/66* ........... 47 .............................................................. 50 AVDD (3.3V))7477/83* ...................................... 47 ! .............................................................. 55 1.8 V ................................................................................ 47 ! !!1 (CFR1)--0x00 .......................... 55 DVDD (1.8V))17/23/30/47/57/64* ......................... 47 ! !!2 (CFR2)--0x01 .......................... 57 AVDD (1.8V))3* ........................................................ 47 ! !!3 (CFR3)--0x02 .......................... 58 AVDD (1.8V))6* ........................................................ 47 ! !!DAC--0x03 ................................. 58 AVDD (1.8V))89/92* ................................................ 47 ! !!I/O--0x04 .................................... 59 ........................................................................................ 48 ! !!(FTW)-- 0x07 ......................... 59 ! --I/O ............................................................. 48 ! !!(POW)--0x08 ......................... 59 ! I/O ................................................................. 48 ! !!(ASF)--0x09 ....................... 59 ! ................................................................................ 48 ! !!--0x0A ..................................... 60 ! !! ........................................................... 48 ! !!--0x0B ................................. 60 ! I/O ............................................... 48 ! !!--0x0C ................................. 60 ! !!(SCLK) ............................................................... 48 ! !!--0x0D ................................ 60 ! !!CS ................................................................... 48 ! !!Profile ..................................................................... 61 ! !!/(SDIO) ............................................ 48 ........................................................................................ 62 ! !!(SDO) ........................................................ 48 ! Rev. B | Page 3 of 64 ................................................................................ 73 AD9910 200812--AB 2 ............................................................................................ 5 1I/O_UPDATE Profile .................................................... 7 1XTAL_SEL .................................................. 8 3 ........................................................................................... 11 20 ......................................................................................... 16 22 ......................................................................................... 17 23 ......................................................................................... 18 24 ......................................................................................... 19 25 ......................................................................................... 20 "REF_CLK/REF_CLK" ....................................... 24 "REF_CLK/REF_CLK " ...................................... 25 "PLL" "(OSK)" ........................................................ 27 "DRG""" ............... 30 "DROVER" ........................................................... 32 43 ......................................................................................... 35 "45Profile" ................................................................................................. 38 47 ......................................................................................... 40 48 ......................................................................................... 41 "I/O_UPDATE" ................................................... 41 "Profile" ......................................................................... 42 "I/O_UPDATESYNC_CLK" ... 42 "49" ............................................................... 42 "" ............................................................... 44 "DVDD (1.8V)(17/23/30/47/57/64)" "AVDD (1.8V)(89/92)" ............................................... 47 "--I/O" ................................................ 48 17 ......................................................................................... 50 19 ......................................................................................... 57 2021 ................................................................................ 58 20082--0A "" .............................................................................. 1 1REFCLK .......................................... 5 SYNC_CLK .................................................... 6 I/O Update/Profile[2:0] ........................................ 6 TxENABLE/(PDCLK) TxENABLE/(PDCLK) ...................................... 6 ................................................................ 6 3 ........................................................................................... 10 91011121314 .......................... 12 307 .............................................................................. 24 "I/O" ............................................................. 41 16 ................................................................... 41 4953 ........................................................................... 43 "" ................................................................... 46 "I/O" .................................................... 47 17 ......................................................................................... 49 19 ......................................................................................... 56 20 ......................................................................................... 57 32 ......................................................................................... 60 20075--0 Rev. B | Page 4 of 64 AD9910 AD9910 14 DAC I/OAD9910 (DDS)1 GSPSAD9910DDS AD9910 AD9910 RAM/ DDS/DAC AD9910 400 MHz AD9910 DDS DDS32 1 GSPS AD9910( 0.23 HzDDS "") RAM_SWP_OVR CS RAM 2 DIGITAL RAMP GENERATOR DRHOLD DROVER 3 PROFILE[2:0] AMPLITUDE (A) AUX DAC 8-BIT A Acos ( t + ) DAC_RSET DATA ROUTE FREQUENCY ( ) Asin ( t + ) AND PARTITION CONTROL CLOCK 16 DAC FSC 2 IOUT INVERSE SINC FILTER REFCLK_OUT SYSCLK /2 8 PARALLEL INPUT IOUT DAC 14-BIT PHASE () PROGRAMMING REGISTERS I/O_UPDATE 8 DDS OUTPUT SHIFT KEYING OSK DRCTL DAC FSC CLOCK MODE SCLK I/O_RESET AD9910 SERIAL I/O PORT 2 SDIO INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION 2 2. Rev. B | Page 5 of 64 06479-002 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER SYNC_IN SYNC_OUT SYNC_CLK 2 SYNC_SMP_ERR PDCLK PARALLEL DATA TIMING AND CONTROL EXT_PWR_DWN TxENABLE AD9910 AVDD (1.8V)DVDD (1.8V) = 1.8 V 5%AVDD (3.3V) = 3.3 V 5%DVDD_I/O (3.3V) = 3.3 V 5%T = 25CRSET = 10 k IOUT = 20 mA(REFCLK) = 1000 MHz 1 REFCLK REFCLK REFCLK REFCLK REFCLK REFCLKVCO VCO(KV) @ REFCLK_OUT DAC REFCLK DAC SFDR SFDR 50.1 MHz 101.3 MHz 0 60 3.2 1500 REFCLK REFCLK 1000 60 1900 25 25 3 2.8 1.4 45 40 50 100 VCO0 VCO1 VCO2 VCO3 VCO4 VCO51 8.6 -10 35 55 60 1000 2000 429 500 555 750 789 850 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V 20 25 pF MHz 20 31.6 +10 2.3 0.8 1.5 5 1 kHz20 MHz AOUT 20x 100x MHz MHz MHz MHz MHz pF k k % % mV p-p mV p-p -152 -140 -140 -0.5 +0.5 mA % FS A LSB LSB pF dBc/Hz dBc/Hz dBc/Hz V 500 kHz 125 kHz 12.5 kHz 500 kHz 125 kHz 12.5 kHz Rev. B | Page 6 of 64 -87 -87 -96 -87 -87 -95 dBc dBc dBc dBc dBc dBc AD9910 201.1 MHz 301.1 MHz 401.3 MHz SCLK SCLK SCLK/ SCLK SCLK I/O_UPDATE/PROFILE[2:0] SYNC_CLK SYNC_CLK I/O_UPDATE Profile Tx_ENABLE16 PDCLK TxENABLE/)PDCLK* TxENABLE/)PDCLK* 2 )* )* Profile DAC DAC DAC RAM DAC DAC DAC DAC 16 DAC 0 500 kHz 125 kHz 12.5 kHz 500 kHz 125 kHz 12.5 kHz 500 kHz 125 kHz 12.5 kHz -87 dBc -87 dBc -91 dBc -86 dBc -86 dBc -88 dBc -84 dBc -84 dBc -85 dBc 4 4 70 2 5 0 11 ns ns SYNC_CLK SYNC_CLK 1.75 0 >1 2 Mbps ns ns ns ns ns ns 250 MHz ns ns 8 1 SYSCLK 3 ms 5 SYSCLK 3 OSK OSK 91 SYSCLK 3 79 SYSCLK 3 79 47 SYSCLK 3 SYSCLK 3 / 94 106 58 SYSCLK 3 SYSCLK 3 SYSCLK 3 / 91 91 47 SYSCLK 3 SYSCLK 3 SYSCLK 3 103 91 SYSCLK 3 SYSCLK 3 1.75 0 REFCLK REFCLK Rev. B | Page 7 of 64 AD9910 CMOS Logic 1 Logic 0 Logic 1 Logic 0 XTAL_SEL Logic 1 Logic 0 Logic 1 Logic 0 CMOS Logic 1 Logic 0 IAVDD (1.8 V) IAVDD (3.3 V) IDVDD (1.8 V) IDVDD (3.3 V) 0 2.0 90 38 2 0.8 120 50 V V A A pF 0.8 120 50 V V A A pF 2.0 90 38 2 1 mA 2.8 0.4 110 29 222 11 715 330 19 1 V V mA mA mA mA 850 400 25 mW mW mW VCO51000 MHz PLLPLLPLL 3 SYSCLKDDSSYSCLK SYSCLK 2 Rev. B | Page 8 of 64 AD9910 AVDD (1.8V)DVDD (1.8V) AVDD (3.3V)DVDD_I/O (3.3V) JA JC 10 DAC OUTPUTS 2V 4V -0.7 V to +4 V 5 mA -65C to +150C -40C to +85C 22C/W 2.8C/W 150C 300C AVDD IOUT IOUT MUST TERMINATE OUTPUTS TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. 06479-003 2 3. DIGITAL INPUTS DVDD_I/O AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. 06479-055 INPUT 4. ESD ESD)* ESD ESD Rev. B | Page 9 of 64 AD9910 76 AVDD (3.3V) 78 AGND 77 AVDD (3.3V) 79 AGND 81 IOUT 80 IOUT 82 AGND 83 AVDD (3.3V) 84 DAC_RSET 86 NC 85 AGND 87 NC 88 AGND 89 AVDD (1.8V) 91 REF_CLK 90 REF_CLK 92 AVDD (1.8V) 93 NC 94 REFCLK_OUT 96 AGND 95 XTAL_SEL 97 NC 99 NC 98 NC 100 NC 75 AVDD (3.3V) NC 1 PLL_LOOP_FILTER 2 AVDD (1.8V) 3 AGND 4 AGND 5 AVDD (1.8V) 6 71 I/O_RESET 70 CS SYNC_IN+ 7 69 SCLK SYNC_IN- 8 SYNC_OUT+ 9 68 SDO 67 SDIO PIN 1 INDICATOR 74 AVDD (3.3V) 73 AGND 72 NC 66 DVDD_I/O (3.3V) 65 DGND SYNC_OUT- 10 DVDD_I/O (3.3V) 11 AD9910 SYNC_SMP_ERR 12 64 DVDD (1.8V) TQFP-100 (E_PAD) TOP VIEW (Not to Scale) DGND 13 MASTER_RESET 14 63 DRHOLD 62 DRCTL DVDD_I/O (3.3V) 15 61 DROVER 60 OSK DGND 16 59 I/O_UPDATE DVDD (1.8V) 17 EXT_PWR_DWN 18 PLL_LOCK 19 58 DGND 57 DVDD (1.8V) 56 DVDD_I/O (3.3V) 55 SYNC_CLK NC 20 DVDD_I/O (3.3V) 21 DGND 22 54 PROFILE0 DVDD (1.8V) 23 RAM_SWP_OVR 24 53 PROFILE1 52 PROFILE2 51 DGND NOTES: 1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND. 2. NC = NO CONNECT. 5. Rev. B | Page 10 of 64 06479-004 F1 49 F0 50 D0 48 DGND 46 DVDD (1.8V) 47 D1 44 DVDD_I/O (3.3V) 45 D3 42 D2 43 TxENABLE 41 D4 39 PDCLK 40 D6 37 D5 38 D8 35 D7 36 D10 33 D9 34 D12 31 D11 32 DVDD (1.8V) 30 DVDD_I/O (3.3V) 28 DGND 29 D14 26 D13 27 D15 25 AD9910 3. NC I/O1 PLL_LOOP_FILTER I PLL"PLL" 3, 6, 89, 92 74 77, 83 17, 23, 30, 47, 57, 64 11, 15, 21, 28, 45, 56, 66 4, 5, 73, 78, 79, 82, 85, 88, 96 13, 16, 22, 29, 46, 51, 58, 65 7 AVDD (1.8V) AVDD (3.3V) DVDD (1.8V) I I I VDD1.8V DAC VDD3.3V VDD1.8V DVDD_I/O (3.3V) I /VDD3.3V AGND I DGND I SYNC_IN+ I (LVDS))* "" 8 SYNC_IN- I (LVDS) "" 9 SYNC_OUT+ O (LVDS))* "" 10 SYNC_OUT- O (LVDS) "" 12 SYNC_SMP_ERR O 14 MASTER_RESET I )*AD9910 SYNC_IN+/SYNC_IN- )*0 18 EXT_PWR_DWN I )* "" 19 PLL_LOCK O 24 RAM_SWP_OVR O PLL)*PLL RAM)*RAM 25 27, 31 39, 42 44, 48 49, 50 40 D[15:0] I RAM)*RAM F[1:0] PDCLK I O )* 41 TxENABLE I 52 54 PROFILE[2:0] I )* Profile)*DDS/profile )8*I/O SYNC_CLK 55 SYNC_CLK O 1, 20, 72, 86, 87, 93, 97 100 2 1/4)*AD9910I/O_UPDATE PROFILE[2:0] Rev. B | Page 11 of 64 AD9910 59 I/O_UPDATE I/O1 I/O 60 OSK I 61 DROVER O 62 DRCTL I 63 DRHOLD I 67 SDIO I/O 68 SDO O () 69 SCLK I () AD9910 70 CS I ()AD9910 AD9910/ AD9910 71 I/O_RESET I /()/ ("/(I/O_RESET)") 80 IOUT O DAC()50AGND 81 IOUT O DAC()50AGND 84 DAC_RSET O 90 REF_CLK I DACAGND10k "REF_CLK/REF_CLK " 91 REF_CLK I "REF_CLK/REF_CLK " 94 95 REFCLK_OUT XTAL_SEL O I "REF_CLK/REF_CLK " )1.8 V*)*XTAL_SEL AVDD(1.8V)AGND 96 (EPAD) (EPAD) 1 (LVDS)() "" ()OSK 0()() 0 ()/ 1 () "(DRG)" 0 () "(DRG)" 0 //() EPAD I = O = Rev. B | Page 12 of 64 AD9910 -50 0 -10 -55 -20 -30 -60 SFDR (dBc) SFDR (dBc) SFDR WITHOUT PLL SFDR WITH PLL -65 -40 -50 -60 1 -70 -70 0 50 100 150 200 250 300 350 -90 -100 400 06479-035 06479-034 -75 -80 50MHz/DIV START 0Hz STOP 500MHz OUTPUT FREQUENCY (MHz) 6. SFDR (PLL = 15.625 MHz64) 9. 10 MHzSFDRREFCLK = 1 GHz -45 0 LOW SUPPLY -10 -50 -20 HIGH SUPPLY -30 SFDR (dBc) SFDR (dBc) -55 -60 -40 -50 1 -60 -65 -70 06479-046 -75 0 50 100 150 200 250 300 350 400 -90 -100 450 06479-036 -80 -70 OUTPUT FREQUENCY (MHz) 7. SFDR (5%)REFCLK = 1 GHz START 0Hz 50MHz/DIV STOP 500MHz 10. 204 MHzSFDRREFCLK = 1 GHz 0 -50 -40C -10 +85C -55 -20 SFDR (dBc) -65 -40 -50 1 -60 -70 -75 0 50 100 150 200 250 300 350 400 06479-037 -80 -70 06479-047 SFDR (dBc) -30 -60 -90 -100 START 0Hz 450 50MHz/DIV STOP 500MHz OUTPUT FREQUENCY (MHz) 8. SFDR REFCLK = 1 GHz 11. 403 MHzSFDRREFCLK = 1 GHz Rev. B | Page 13 of 64 0 0 -12 -12 -24 -24 -36 -36 -48 -48 SFDR (dBc) -60 -72 -72 -84 -84 1 -120 2.5kHz/DIV 06479-040 -108 CENTER 10.32MHz 1 -96 06479-038 -96 -108 -120 CENTER 403.78MHz SPAN 25kHz 12. 10.32 MHzSFDRREFCLK = 1 GHz 0 -90 -12 -100 MAGNITUDE (dBc/Hz) -48 -60 -72 -84 -120 fOUT = 98.6MHz -130 -140 -160 fOUT = 20.1MHz 06479-039 -108 -120 2.5kHz/DIV fOUT = 201.1MHz -150 1 CENTER 204.36MHz SPAN 25kHz fOUT = 397.8MHz -110 -36 -96 2.5kHz/DIV 14. 403.78 MHzSFDRREFCLK = 1 GHz -24 SFDR (dBc) -60 -170 10 SPAN 25kHz 100 06479-042 SFDR (dBc) AD9910 1k 10k 100k 1M 10M FREQUENCY OFFSET (Hz) 13. 204.36 MHzSFDRREFCLK = 1 GHz 15. 1 GHzPLL Rev. B | Page 14 of 64 100M AD9910 -90 450 POWER DISSIPATION (mW) MAGNITUDE (dBc/ Hz) fOUT = 201.1MHz -110 -120 -130 -140 fOUT = 98.6MHz 100 1k 10k 100k 1M 10M 06479-043 fOUT = 20.1MHz -150 -160 10 100M FREQUENCY OFFSET (Hz) DVDD 1.8V 300 250 200 AVDD 1.8V 150 100 AVDD 3.3V 50 DVDD 3.3V 300 400 500 600 700 800 900 06479-044 POWER DISSIPATION (mW) 350 200 300 250 AVDD 1.8V 200 150 100 AVDD 3.3V 50 DVDD 3.3V 0 400 500 600 700 800 18. (PLL) 450 400 350 SYSTEM CLOCK FREQUENCY (MHz) 16. 1 GHz 50 MHz20x PLL 0 100 DVDD 1.8V 400 -100 1000 SYSTEM CLOCK FREQUENCY (MHz) 17. (PLL) Rev. B | Page 15 of 64 900 06479-045 fOUT = 397.8MHz 1000 AD9910 AD9510, AD9511, ADF4106 / CHARGE PUMP PHASE COMPARATOR LOOP FILTER VCO / 06479-056 REFERENCE REF_CLK AD9910 LPF 19. PLLDDS AD9510 CLOCK DISTRIBUTOR WITH DELAY EQUALIZATION CLOCK SOURCE REF_CLK AD9510 SYNCHRONIZATION DELAY EQUALIZATION FPGA SYNC_OUT C1 S1 DATA A1 AD9910 (MASTER) SYNC_CLK C2 S2 DATA (SLAVE 1) SYNC_CLK FPGA C3 S3 DATA A3 AD9910 (SLAVE 2) SYNC_CLK C4 S4 DATA A4 AD9910 FPGA (SLAVE 3) SYNC_CLK A_END 06479-058 CENTRAL CONTROL A2 AD9910 FPGA 20. AD9510 PROGRAMMABLE 1 TO 32 DIVIDER AND DELAY ADJUST CLOCK OUTPUT SELECTION(S) REFCLK CH 2 LPF AD9515 AD9514 AD9513 AD9512 n LVPECL LVDS CMOS 06479-057 AD9910 n = DEPENDENT ON PRODUCT SELECTION. 21. AD9512/AD9513/AD9514/AD9515 Rev. B | Page 16 of 64 $' AD9910 AD9910(OSK) t t t t DDS RAM OSKDDS OSK DDS DDS OSK / I/O DDSAD9910 DDSRAMDDS ""5 RAM ! DDS DDS DDS ProfileDDS AD99108Profile DDS Profile profile DDS (PROFILE[2:0])profileProfile SYNC_CLKProfile DDS DDS RAM_SWP_OVR CS RAM 2 DIGITAL RAMP GENERATOR DRHOLD DROVER 3 PROFILE[2:0] AUX DAC 8-BIT DAC_RSET AMPLITUDE (A) Acos ( t + ) A PHASE () DATA ROUTE FREQUENCY ( ) AND Asin ( t + ) PARTITION CONTROL CLOCK PROGRAMMING REGISTERS I/O_UPDATE 8 DDS OUTPUT SHIFT KEYING OSK DRCTL DAC FSC PARALLEL INPUT DAC FSC 2 IOUT INVERSE SINC FILTER REFCLK_OUT SYSCLK /2 8 16 IOUT DAC 14-BIT CLOCK MODE SCLK I/O_RESET AD9910 SERIAL I/O PORT 2 SDIO INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION 2 22. Rev. B | Page 17 of 64 06479-005 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER SYNC_IN SYNC_OUT SYNC_CLK 2 SYNC_SMP_ERR PDCLK PARALLEL DATA TIMING AND CONTROL EXT_PWR_DWN TxENABLE AD9910 RAM RAM ProfileProfile RAM(23)RAMI/O_UPDATE (PROFILE[2:0])ProfileProfile (Profile)DDS SYNC_CLKRAM RAM Profile RAM1024x32 RAM RAM DDS RAMDDS RAM DDS32 1614 DDS(RAM)8 RAM_SWP_OVR CS RAM 2 DIGITAL RAMP GENERATOR DRHOLD DROVER 3 PROFILE[2:0] AMPLITUDE (A) Acos ( t + ) A PHASE () DATA ROUTE FREQUENCY ( ) AND Asin ( t + ) PARTITION CONTROL CLOCK PROGRAMMING REGISTERS I/O_UPDATE AUX DAC 8-BIT 8 DDS OUTPUT SHIFT KEYING OSK DRCTL DAC FSC DAC_RSET PARALLEL INPUT DAC FSC 2 IOUT INVERSE SINC FILTER REFCLK_OUT SYSCLK /2 8 16 IOUT DAC 14-BIT CLOCK MODE SCLK I/O_RESET AD9910 SERIAL I/O PORT 2 SDIO INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION 2 23. RAM Rev. B | Page 18 of 64 06479-006 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER SYNC_IN SYNC_OUT SYNC_CLK 2 SYNC_SMP_ERR PDCLK PARALLEL DATA TIMING AND CONTROL EXT_PWR_DWN TxENABLE AD9910 32DRG32 (24)DDS (DRG) 321614 I/O MSB ()DRCTL DRHOLD / RAM_SWP_OVR CS RAM 2 DIGITAL RAMP GENERATOR DRHOLD DROVER 3 PROFILE[2:0] AMPLITUDE (A) A Acos ( t + ) DAC_RSET DATA ROUTE FREQUENCY ( ) AND Asin ( t + ) PARTITION CONTROL CLOCK 16 DAC FSC 2 IOUT INVERSE SINC FILTER REFCLK_OUT SYSCLK /2 8 PARALLEL INPUT IOUT DAC 14-BIT PHASE () PROGRAMMING REGISTERS I/O_UPDATE AUX DAC 8-BIT 8 DDS OUTPUT SHIFT KEYING OSK DRCTL DAC FSC CLOCK MODE SCLK I/O_RESET AD9910 SERIAL I/O PORT 2 SDIO INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION 2 24. Rev. B | Page 19 of 64 06479-007 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER SYNC_IN SYNC_OUT SYNC_CLK 2 SYNC_SMP_ERR PDCLK PARALLEL DATA TIMING AND CONTROL EXT_PWR_DWN TxENABLE AD9910 (0)16FTW32 (25)DDS LSBFM116 18 FTW32116 16MSB16(D[15:0] FTW2FM )LSB2(F[1:0]) 16DDS4 (PDCLK) 16(DDS AD9910PDCLK1/4 DAC )16 ()PDCLK PDCLK DDS16 18 FTW32 PDCLKPDCLK 16FTW32 PDCLK 4FM PDCLK FM16 PDCLK0 RAM_SWP_OVR CS RAM 2 DIGITAL RAMP GENERATOR DRHOLD DROVER 3 PROFILE[2:0] DAC_RSET AMPLITUDE (A) Acos ( t + ) A PHASE () DATA ROUTE FREQUENCY ( ) AND Asin ( t + ) PARTITION CONTROL CLOCK PROGRAMMING REGISTERS I/O_UPDATE AUX DAC 8-BIT 8 DDS OUTPUT SHIFT KEYING OSK DRCTL DAC FSC PARALLEL INPUT DAC FSC 2 IOUT INVERSE SINC FILTER REFCLK_OUT /2 SYSCLK 8 16 IOUT DAC 14-BIT CLOCK MODE SCLK I/O_RESET AD9910 SERIAL I/O PORT 2 SDIO INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION 2 25. Rev. B | Page 20 of 64 06479-008 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER SYNC_IN SYNC_OUT SYNC_SMP_ERR 2 SYNC_CLK PDCLK PARALLEL DATA TIMING AND CONTROL EXT_PWR_DWN TxENABLE AD9910 4. F[1:0] D[15:0] 00 D[15:2] 14 01 - 2-14D[1:0] 01 D[15:0] 16 02(1 - 2-16) 10 D[15:0] 32 16324FM 11 D[15:8] 8 MSBDDS 14MSBDDS6LSB ASF[5:0]1401 - 2-14 D[7:0] 8 MSBDDS 16MSBDDS8LSB POW[7:0]1602 (1 - 2-16) TxENABLE TxENABLE TxENABLE PDCLK26 TRUE TxENABLE (BURST) FALSE TxENABLE (CLOCK) tDH tDS PDCLK tDS PARALLEL DATA PORT tDH WORD1 WORD2 WORD3 WORD4 WORDN - 4 26. PDCLKTxENABLE Rev. A | Page 21 of 64 WORDN 06479-009 (TxENABLE) AD9910TxENABLE TxENABLE10TxENABLETxENABLE PDCLK) PDCLK*TxENABLEPDCLK TxENABLE18 TxENABLE ( ) AD9910 5DDS 5DDS RAM DDS RAM DDS /OSKDDS I/O DDSAD9910 5. RAM RAM RAM DDS RAM DRG DRG DRG FTW FTW RAM FTW profile DRG FTW profile FTW profile DRG OSK OSK () ASF OSK )* RAM RAM POWLSB DRG DRG POW RAM POW profile DRG ASFLSB POW profile ASFprofile profile (CFR2[24]) POW profile Rev. 0 | Page 22 of 64 AD9910 ! DDS (DDS)) DDSCFR1[16]* )*DDS 27 DDS16(POW) DDS () POW 2 16 (c) 2 = POW 360 16 (c) 2 DDS SIGNAL CONTROL PARAMETERS AMPLITUDE CONTROL 14 PHASE OFFSET CONTROL 16 POW )FTW* MSB ALIGNED 32 FREQUENCY 32 CONTROL DQ DDS_CLK 19 32 19 R 14 16 (MSBs) ACCUMULATOR RESET ANGLE-TOAMPLITUDE 14 14 CONVERSION (SINE OR COSINE) TO DAC DDS)*14 (ASF)DDS ASF 14 Amplitude Scale = 2 ASF * 20log 14 (c) 2 06479-010 32-BIT ACCUMULATOR 32 27. DDS AD9910(fOUT)DDS (FTW)fOUTFTWfSYSCLK f OUT = FTW * f SYSCLK 32 (c) 2 (1) FTW02,147,483,647 (231 - 1)32 32dc (1/2 fSYSCLK) fOUT1FTW2 ** FTW = 2 32 f OUT (c) (c) f SYSCLK (2) round(x))x* FTWfOUT = 41 MHzfSYSCLK = 122.88 MHzFTW = 1,433,053,867 (0x556AAAAB) (c) 2 (3) dB 3 ASF)FTW* AD9910DDS 1/4 fSYSCLK1/4 fSYSCLK 14DAC AD991014DAC DAC DAC_RSETAGND (RSET)DAC (IOUT))"DAC" *10 k(RSET) DAC FTW231 f OUT = 1 - FTW * f SYSCLK 32 * * (for FTW 231) Rev. A | Page 23 of 64 AD9910 Iout = CODE * 86.4 1 + 96 R SET (c) 5DDS 5DDS RAM DDS RAM 1 RSET RSET)*CODE DAC8)127*RSET = 10,000 CODE = 127IOUT = 20.07 mA -1 (dB) Sinc AD9910(DAC) DACDAC sin(x)/x)Sinc* Sinc DACSincSinc FIRSinc Sinc28)Sinc* SINC 0 -2 INVERSE SINC -3 -4 06479-011 DAC DAC(IOUT)8DAC 8IOUT 0 0.1 0.2 0.3 0.4 0.5 FREQUENCY RELATIVE TO DAC SAMPLE RATE SincCFR1[22]6 DACSinc 28. SincSinc -2.8 Sinc~3.0 dB 40% DACSinc -2.9 6. Sinc -35 +134 -562 +6 7 2 9 COMPENSATED RESPONSE (dB) -3.0 28Sinc (DAC1/2)4 dB SincDACSinc Sinc0.05 dB 29SincSinc -3.1 06479-012 1, 7 2, 6 3, 5 4 0 0.1 0.2 0.3 0.4 0.5 FREQUENCY RELATIVE TO DAC SAMPLE RATE 29.SincDAC (REF_CLK/REF_CLK ) REF_CLK/ REF_CLK REF_CLK/REF_CLKAD9910 SYSCLK)DAC* REF_CLK (PLL) REF_CLK 30 XTAL_SELCFR330 CFR3 Rev. 0 | Page 24 of 64 AD9910 PLL_LOOP_FILTER 95 2 DRV0 CFR3 [29:28] 2 91 REF_CLK 39pF ENABLE PLL_LOOP_FILTER IN REF_CLK 90 CHARGE PUMP DIVIDE REF_CLK 91 2 ICP CFR3 [21:19] 1 /2 0 OUT PLL VCO SELECT 7 N CFR3 [7:1] 1 0 SYSCLK 3 VCO SEL CFR3 [26:24] REFCLK INPUT DIVIDER BYPASS CFR3[15] 06479-013 1 0 REFCLK INPUT DIVIDER RESETB CFR3[14] 39pF 06479-014 REFCLK INPUT SELECT LOGIC REF_CLK XTAL PLL ENABLE CFR3 [8] REFCLK_OUT 94 90 30. REF_CLK PLLPLL REF_CLK/REF_CLK )*2 GHz1 GHz PLLREFCLK_OUT REF_CLK REFCLK_OUT 7 31. REF_CLK/REF_CLK REF_CLK/REF_CLK REF_CLK/REF_CLK 0.1 F REF_CLK 0.1 FREF_CLK/REF_CLK ~1.35 V 32 REF_CLK/REF_CLK ~2.5 k)*~1.2 k) *REF_CLK/REF_CLK 3250 0.1F DIFFERENTIAL SOURCE, DIFFERENTIAL INPUT 90 REF_CLK PECL, LVPECL, OR LVDS DRIVER TERMINATION 7. REFCLK_OUT DRV0(CFR3[29:28]) 00 01 10 11 0.1F REFCLK _ OUT )* BALUN (1:1) SINGLE-ENDED SOURCE, DIFFERENTIAL INPUT 0.1F 90 REF_CLK 50 0.1F REF_CLK/REF_CLK REF_CLK/REF_CLK 25 MHz31 XTAL_SEL1)1.8V * 91 REF_CLK 0.1F 90 REF_CLK SINGLE-ENDED SOURCE, SINGLE-ENDED INPUT 50 91 REF_CLK 0.1F 32. Rev. A | Page 25 of 64 91 REF_CLK 06479-015 XTAL_SEL AD9910 VCOPLL(fSYSCLK)420 MHz 1 GHzVCO fSYSCLK33 34VCO 33 VCO CFR3 [26:24] A-10C 900 MHzCFR3[26:24]100b B90C900 MHz CFR3[26:24]101b )33* CFR3[26:24] 34 VCO34 VCO CFR3[26:24] 33 VCO VCO fLOW = 920 fHIGH = 1030 VCO5 fLOW = 760 fHIGH = 875 VCO4 fLOW = 650 fHIGH = 790 VCO3 395 fLOW = 400 fHIGH = 460 495 595 695 (MHz) 795 895 fLOW = 500 fHIGH = 700 VCO2 fLOW = 420 fHIGH = 590 VCO1 fLOW = 370 fHIGH = 510 VCO0 335 435 535 635 735 835 (MHz) 935 1035 1135 34. VCO 8. VCO VCO(CFR3[26:24]) 000 001 010 011 100 101 110 111 VCO VCO0 VCO1 VCO2 VCO3 VCO4 VCO5 PLL PLL PLL (ICP)PLL 9 9. PLL ICP(CFR3[21:19]) 000 001 010 011 100 101 110 111 06479-059 VCO0 fLOW = 600 fHIGH = 880 VCO3 fLOW = 455 fHIGH = 530 VCO1 fLOW = 700 fHIGH = 950 VCO4 fLOW = 530 fHIGH = 615 VCO2 fLOW = 820 fHIGH = 1150 VCO5 06479-060 (PLL) (PLL) PLL ) 12x 127x*) PLL_LOOP_FILTER*PLL PLLPLL_LOCK 995 33. VCO Rev. 0 | Page 26 of 64 ICP (A) 212 237 262 287 312 337 363 387 AD9910 PLL PLL_LOOP_FILTER PLL35PLL PLLPLL_LOCKPLL REFCLKPLL_LOCKPLL 1PFD PLL_LOCKPFD0 (OSK) AVDD OSK(36)DDS DDS OSK OSK C1 C2 R1 PLL PLL_LOOP_FILTER 2 OSK REFCLK PLL PLL IN PFD CP 60 VCO PLL OUT OSK ENABLE AUTO OSK ENABLE 06479-016 MANUAL OSK EXTERNAL 35. REFCLK PLL LOAD ARR AT I/O_UPDATE IIPLL (N)(KD)VCO(KV)(KVVCO 1) (fOL)() R1= Nf OL K DK V 1 * 1 + sin( ) (c) C1= K D K V tan( ) 2 N (f OL ) 2 C2= K DK V N (2 f OL ) 2 1 - sin( ) * (c) cos( ) AMPLITUDE RAMP RATE (ASF[31:16]) 16 AMPLITUDE SCALE FACTOR (ASF[15:2]) 14 AMPLITUDE STEP SIZE (ASF[1:0]) OSK CONTROLLER 14 TO DDS AMPLITUDE CONTROL PARAMETER 2 DDS CLOCK 06479-017 /N (4) 47/!PTL (5) (6) KDICP KV1 46ICP 9uAKV / (Hz/V) 1 / (MHz/V) (fOL)(Hz)() PLLICP = 287 AKV = 625 MHz/V N = 2550 kHz 45R1 = 52.85 C1 = 145.4 nFC2 = 30.11 nF OSKCFR1)OSKOSK *OSKASF32 OSKOSKOSKOSK OSKOSK 0)* OSK ASF I/OOSK OSKOSK0 0 Rev. A | Page 27 of 64 AD9910 MASF(ARR)16 fSYSCLK = 750 MHzM = 23218 (0x5AB2) t 123.8293 s OSK14DDS) OSK1*OSK1OSK(0) OSK0OSK (0) 16 OSK01 I/OOSK ARR @ I/O 0I/O_UPDATE 1)profile* (DRG) DRG AD9910 DRG9 326432 )37* OSK0OSK 0 OSK1OSK(0) 61 63 DIGITAL RAMP ENABLE 2 DIGITAL RAMP DESTINATION 2 DIGITAL RAMP NO-DWELL OSKOSK0 OSK(0) OSKASF 1014OSKLSB OSKASF 62 DROVER PIN ACTIVE LOAD LRR AT I/O_UPDATE DIGITAL RAMP GENERATOR CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR DIGITAL RAMP LIMIT REGISTER DIGITAL RAMP STEP REGISTER DIGITAL RAMP RATE REGISTER TO DDS SIGNAL CONTROL PARAMETER 64 64 32 DDS CLOCK 37. Rev. 0 | Page 28 of 64 32 06479-018 4M fSYSCLK 1 2 4 8 DRHOLD t = (ASF[1:0]) 00 01 10 11 DROVER 1/4 f SYSCLK16 (t) 21/!PTL DRCTL OSK OSK )* 32ASFI/O ASF16 )[31:16]*ASF14 )[15:2]*ASF 2)[1:0]*)/ *OSK AD9910 DRGDRG DRG /DRG 38 DRG32DDS DRG2 11 323216 14MSB LSB DRCTL0DRG 1 DRGDRHOLD 1DRG DRG DRGDDSprofile 10. OSK (CFR2[21:20]) DDS DDS 00 01 1x1 31:16 31:18 x = 32 DECREMENT STEP SIZE 32 INCREMENT STEP SIZE DIGITAL RAMP ACCUMULATOR 0 32 32 1 32 DRCTL 62 16 POSITIVE SLOPE RATE LOAD LRR AT I/O_UPDATE 0 LIMIT CONTROL 32 32 UPPER LIMIT LOWER LIMIT 32 TO DDS SIGNAL CONTROL PARAMETER 16 1 LOAD CONTROL LOGIC DRHOLD 63 DDS CLOCK Q R 16 NEGATIVE SLOPE RATE D PRESET LOAD ACCUMULATOR RESET CONTROL LOGIC Q DIGITAL RAMP TIMER 38. Rev. A | Page 29 of 64 NO-DWELL CONTROL 2 NO DWELL CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP . ACC 06479-019 1 31:0 AD9910 DRG DRG32 DDS1/4 f SYSCLK (+t)(-t) +t= -t= 4p f SYSCLK 4N f SYSCLK PN3216 N P (STEPP)(STEPN)32 64 )STEPN* 32 STEPN STEPPM M * f SYSCLK 32 (c)2 !!!!= !!!!= !!!!= M 2 31 45 M 2 29 M * I 32 FS (c)2 !!!! = fSYSCLK)MHz* DACIFS )mA* 16 0 1 I/O DRCTLLRR @ I/O )""* DRG DRG 64 DRG DRG 0)0* 0DRG 0)" "*39 DRG DROVER)DROVER 1* )t* )1* DRG 321614 32 1614 Rev. 0 | Page 30 of 64 AD9910 P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE NEGATIVE STEP SIZE +t POSITIVE STEP SIZE -t UPPER LIMIT DRG OUTPUT LOWER LIMIT DROVER DRHOLD AUTO CLEAR CLEAR DRCTL RELEASE DIGITAL RAMP ENABLE CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR I/O_UPDATE 2 3 4 5 6 7 8 9 11 10 13 12 06479-020 1 39. 1--1I/O DRG 7--DRHOLD0 2--I/ODRCTL = 1 )DRCTL*DRG )DRG*DRCTL = 0DRG 8--1I/O DRG 3--DRCTL1DRG DRCTLDRG DRCTL = 0 DRG DRG 4--DRCTL0DRG DRCTLDRG DRCTL = 1 DRG DRG 5--DRCTL1 6--DRHOLD1 DRG 9--I/O1 DRG DRG 10--0 I/ODRG 11--I/O0 12--1 I/ODRG 13--I/O 1 DDSDRG DRCTL1DRG Rev. A | Page 31 of 64 AD9910 P DDS CLOCK CYCLES POSITIVE STEP SIZE +t UPPER LIMIT DRG OUTPUT LOWER LIMIT DROVER DRCTL 1 2 3 4 5 6 7 8 06479-021 ! 2DRG DRG DRG DRG DRGDRG)* ) *1DRG DRG)* 40. DRCTL DRCTL )DRCTL* 40 1--I/O 2--DRCTL1DRG 3--DRCTL0DRG DRCTL )DRCTL* 4--1DRG DRCTL0 1 DRG DRCTL DRG DRCTL10 DRG DRG DRCTL01DRG 5--DRCTL01 67--DRG DRCTL DRG )DROVER1* DROVER)DDS* 40DRG 1I/O DROVER)1* 8--1DRG DRCTL0 1 DRCTL10DRG DROVER DROVERDRG DRG/DROVER1 0 DRG DROVERDDS Rev. 0 | Page 32 of 64 AD9910 RAM// RAMI/O32 /RAM / 10 1RAMRAM I/O)profile * 2 STATE MACHINE U/D Q RAM 32 SERIAL I/O PORT ADDRESS CLOCK 10 PROFILE SDIO SCLK I/O_RESET CS 41. RAM/ 10 RAM profile 16 3RAM profile RAM DDSRAM )/* RAM/! RAM/RAM 0RAM 1. ! 2. 3 PROGRAMMING REGISTERS UP/DOWN COUNTER 8RAM profile profileprofile t t t t t t WAVEFORM START ADDRESS 10 WAVEFORM END ADDRESS 06479-022 RAM8 DDS RAM profileRAM(0x16)! )*RAM)"! "*41RAM/! DATA RAM AD99101024 x 32RAMRAM /RAM I/O/ RAM 3. ! ! ! ADDRESS RAM RAM Profile 0RAM Profile 7! profileRAM profile RAM RAM profile I/O RAM profileRAMRAM profile RAM() RAM RAMRAM1RAM PROFILE[2:0]profile RAMRAM )* 42RAM Rev. A | Page 33 of 64 AD9910 WAVEFORM START ADDRESS WAVEFORM END ADDRESS ADDRESS RAMP RATE RAM MODE NO DWELL 10 3 STATE MACHINE 3 PROFILE UP/DOWN COUNTER U/D Q 10 RAM 32 RAM RAM5 TO DDS SIGNAL CONTROL PARAMETER 06479-023 2 DATA 16 ADDRESS 10 RAM PROFILE REGISTERS RAM_SWP_OVR(RAM) RAM_SWP_OVR RAM RAM0 DDS CLOCK 42. RAM / 16 DDS RAM profile16 RAM profile 16M f f !!!!= DDSCLOCK = SYSCLK M 4M (t) t = 1 Playback Rate = 4M f SYSCLK I/ORAM/ RAMI/O RAM32DDS 1 RAM3212 12. RAM RAM CFR1[30:29] DDS DDS 00 01 10 11 31:0 !!!!!!!!!!!!31:16 31:18 31:16 () 15:2 () () t t t t t RAM profile3RAM RAMprofileRAM profile13 13. RAM RAM Profile 000, 101, 110, 111 001 010 011 100 RAM RAM RAM PROFILE[2:0]RAM profile32 DDS32 RAMprofile10 RAM_SWP_OVR0 8FSKPSKASK RAM ) FSK * RAM profile RAM profileRAM 32profile DDS Rev. 0 | Page 34 of 64 AD9910 RAM )*RAM RAMDDS 43 profile RAM 1(t)profile M DDS CLOCK CYCLES DDSDDS )DDS 3600* DDS) DDS* t WAVEFORM END ADDRESS RAM ADDRESS (BPSK)AD9910 BPSK 180 BPSK WAVEFORM START ADDRESS WAVEFORM END ADDRESS RAM ADDRESS DDS RAMDDS RAM I/OprofileRAM RAM profile RAM profile RAM RAMRAMDDS RAM RAM_SWP_OVR NO-DWELL HIGH = 0 1 NO-DWELL HIGH = 1 1 WAVEFORM START ADDRESS RAM_SWP_OVER I/O_UPDATE 1 2 3 06479-024 profile profile 43. 43 1--I/Oprofile RAM_SWP_OVR0 2-- profile RAM_SWP_OVR1 3-- profileRAM_SWP_OVR0 Rev. A | Page 35 of 64 AD9910 SBNQspgjmf 13. RAM Profile(CFR1[20:17]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Profile profile Profile 0Profile 1 Profile 0Profile 2 Profile 0Profile 3 Profile 0Profile 4 Profile 0Profile 5 Profile 0Profile 6 Profile 0Profile 7 Profile 0Profile 1 Profile 0Profile 2 Profile 0Profile 3 Profile 0Profile 4 Profile 0Profile 5 Profile 0Profile 6 Profile 0Profile 7 profileprofile )RAM profileRAM profile* profile1RAM profile RAM profile profile profile PROFILE[2:0]Profile14 profile Profile 0 Profile 0profile profileprofile profile profile 1(CFR1)profile 14 profile Profile 0profileprofile I/O 44CFR1 profile0010RAM Profile 1 RAM Profile 0RAM Profile 2 RAM Profile 1profile profile/ profilet Rev. 0 | Page 36 of 64 AD9910 0 RAM PROFILE 1 2 WAVEFORM END ADDRESS 2 t2 WAVEFORM START ADDRESS 2 1 WAVEFORM END ADDRESS 1 t1 RAM ADDRESS WAVEFORM START ADDRESS 1 1 WAVEFORM END ADDRESS 0 t0 1 WAVEFORM START ADDRESS 0 RAM_SWP_OVER 1 2 3 4 5 6 7 06479-025 I/O_UPDATE 44. Profile() profile 1--I/Oprofile) 1*0010RAM_SWP_OVR0 RAM Profile 0RAM Profile 0t0)RAM Profile 0 * 2 -- R A M Profi le 0 RAM_SWP_OVRDDS 3--RAM Profile 0 RAM Profile 1 RAM Profile 1RAM Profile 1 t1 4 -- R A M Profi le 1 RAM_SWP_OVRDDS 5--RAM Profile 1 RAM Profile 2 RAM Profile 2RAM Profile 2 t2 6--RAM Profile 2 RAM_SWP_OVRDDS 7--RAM Profile 2 Rev. A | Page 37 of 64 AD9910 0 RAM PROFILE 1 WAVEFORM END ADDRESS 1 1 0 1 t1 1 WAVEFORM START ADDRESS 1 RAM ADDRESS 0 WAVEFORM END ADDRESS 0 t0 1 WAVEFORM START ADDRESS 0 RAM_SWP_OVER 1 2 3 4 5 6 7 8 9 10 11 06479-026 I/O_UPDATE 45. Profile Profile 45profile profile(1)1000 RAM Profile 1RAM Profile 0 profile 1--I/Oprofile( 1)1000RAM_SWP_OVR0 RAM Profile 0RAM Profile 0t0(RAM Profile 0 ) 2--RAM Profile 0 RAM_SWP_OVRDDS 3--RAM Profile 0 RAM Profile 1 RAM Profile 1RAM Profile 1 t1 4-- R AM Pr ofi le 1 RAM_SWP_OVRDDS 5--RAM Profile 1 RAM Profile 0 RAM Profile 0RAM Profile 0 t0 511--profile I/O RAM I/ORAMRAM Profile 0) 8profile*RAM profile RAMRAMDDS PROFILE[2:1] RAM profileRAM profile RAMRAM profile I/Oprofile RAM PROFILE01 PROFILE0Logic 1 RAM ROFILE0 0PROFILE0 0 RAM Rev. 0 | Page 38 of 64 AD9910 M DDS CLOCK CYCLES t WAVEFORM END ADDRESS RAM ADRESS t 1 WAVEFORM START ADDRESS RAM_SWP_OVER PROFILE0 1 2 3 4 5 6 7 8 06479-027 I/O_UPDATE 46. PROFILE0 46PROFILE0 RAM_SWP_OVR RAM_SWP_OVR 1PROFILE0 01RAM_SWP_OVR 1 46 1--I/OprofileRAM RAM_SWP_OVR 0 2--PROFILE01RAM 3--PROFILE01 RAM_ SWP_OVR1 4--PROFILE00RAM RAM_ SWP_OVR1 5--PROFILE01 RAM)* RAM_SWP_OVR 6--PROFILE00 RAM RAM_SWP_OVR 7--PROFILE00 RAM_SWP_OVR 8--PROFILE01 RAM RAM_SWP_OVR 0 PROFILE001 RAM I/Oprofile RAMPROFILEx RAM profileRAM profile RAMRAM DDS I/Oprofile RAM Rev. A | Page 39 of 64 AD9910 M DDS CLOCK CYCLES t WAVEFORM END ADDRESS RAM ADRESS t 1 WAVEFORM START ADDRESS I/O_UPDATE 1 2 3 06479-028 RAM_SWP_OVER 47. PROFILE RAM profile 2--RAM_SWP_OVR 1 RAM_SWP_OVR 1,0 3--RAM_SWP_OVR 0 47 1--I/OprofileRAM RAM_SWP_OVR 0 Rev. 0 | Page 40 of 64 AD9910 M DDS CLOCK CYCLES t WAVEFORM END ADDRESS RAM ADRESS 1 WAVEFORM START ADDRESS RAM_SWP_OVER 1 2 3 4 5 06479-029 I/O_UPDATE 48. RAM I/Oprofile ProfileRAM profile RAM_SWP_OVR DDS 48 1--I/Oprofile RAM_SWP_OVR0 2-- profile RAM_SWP_OVR1DDS 3-- 4-- profile RAM_SWP_OVRDDS 1 5-- 45--I/Oprofile Rev. B | Page 41 of 64 AD9910 PROFILE AD9910profile 8Profile ProfileI/O (PROFILE[2:0])profile profile profile15 15. Profile ProfileSYNC_CLK I/O_UPDATESYNC_CLK I/O_UPDATEI/O Profile 0 1 2 3 4 5 6 7 PROFILE[2:0] 000 001 010 011 100 101 110 111 PROFILE1PROFILE20PROFILE0 PROFILE0 SYNC_CLK SYNC_CLK AD9910 8profile RAM = 0profile profile"" RAM = 1RAM profile profile(FSK) FSK (1)(0) (FSK)Profile 0 Profile 1 I/O_UPDATE SYNC_CLK DAC() SPIDAC SYNC_CLK I/O_UPDATE I/O_UPDATE PROFILE[2:0] 49 SYSCLK A B SYNC_CLK I/O_UPDATE DATA IN REGISTERS N N+1 N+1 N+2 06479-061 DATA IN I/O BUFFERS N N-1 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. 49. I/O_UPDATEI/O Rev. B | Page 42 of 64 AD9910 I/O ! AD9910I/O 2(CFR2)I/O AD9910 I/O_UPDATE I/O I/O(CFR2[15:14])16 16. I/O (CFR2[15:14]) 00 01 10 11 I/O 12 SYSCLKs 24 SYSCLKs 48 SYSCLKs 96 SYSCLKs I/O I/O I/OI/O CFR2I/O I/O 32I/O1/4 fSYSCLK 11/21/41/8 32I/O fI/O_UPDATE = f SYSCLK 2 A +2 B t t t t %"$ DAC REFCLK I/O 0 1(CFR1)4 EXT_PWR_DWN 0 )I/O* 0 EXT_PWR_DWN 1 EXT_PWR_DWN1 CFR1 EXT_PWR_DWN DACPLLVCO AI/O2B I/O32 A0B0xFFFFB 0x0003I/O_UPDATE 1 Rev. B | Page 43 of 64 AD9910 AD9910 SYNC_Inx 50 SYSCLK 51 AD9910 /16 SYSCLK D Q 0 1 SYNC POLARITY 9 PROGAMMABLE DELAY 5 R SYNC_OUT+ 10 SYNC_OUT- 10 LVDS DRIVER SYNC GENERATOR DELAY SYNC GENERATOR ENABLE 06479-051 I/O 51. 90 REF_CLK 91 REF_CLK SYNC_OUTx LVDS50% SYNC GENERATOR DELAY REF_CLK INPUT CIRCUITRY SYNC POLARITY SYNC GENERATOR ENABLE SYSCLK f SYNC _ OUT = 5 9 SYNC_OUT+ 10 SYNC_OUT- INPUT DELAY AND EDGE DETECTION 7 SYNC_IN+ 8 SYNC_IN- SETUP AND HOLD VALIDATION 12 SYNC_SMP_ERR SYNC GENERATOR SYNC_OUTx SYSCLKSYNC_OUTx SYSCLKSYSCLK I/O5 ~150 ps SYNC_OUTx SYNC RECEIVER DELAY 5 SYNC RECEIVER 4 SYNC SYNC TIMING VALIDATION VALIDATION DELAY DISABLE (52)(0x0A[27]) 06479-050 INTERNAL CLOCKS CLOCK GENERATOR SYNC RECEIVER ENABLE f SYSCLK 16 50. REFCLK REFCLK( 53) Rev. B | Page 44 of 64 AD9910 CLOCK STATE SYNC RECEIVER ENABLE DELAYED SYNC-IN SIGNAL LVDS RECEIVER 7 SYNC_IN- 8 RISING EDGE DETECTOR AND STROBE GENERATOR PROGAMMABLE DELAY SYNC TIMING VALIDATION DISABLE s s s s s s INTERNAL CLOCKS Qn RESET CLOCK GENERATOR SETUP AND HOLD VALIDATION SYNC_SMP_ERR 12 Q0 SYSCLK 4 SYNC VALIDATION DELAY SYNC PULSE 06479-052 SYNC_IN+ SYNC RECEIVER DELAY 5 52. CLOCK DISTRIBUTION AND DELAY EQUALIZATION EDGE ALIGNED AT REF_CLK INPUTS CLOCK SOURCE (FOR EXAMPLE AD951x) REF_CLK PDCLK DATA FPGA NUMBER 1 SYNC SYNC IN OUT REF_CLK PDCLK DATA FPGA AD9910 AD9910 MASTER DEVICE EDGE ALIGNED AT SYNC_IN INPUTS. NUMBER 2 SYNC SYNC IN OUT SYNCHRONIZATION DISTRIBUTION AND DELAY EQUALIZATION (FOR EXAMPLE AD951x) REF_CLK AD9910 NUMBER 3 SYNC SYNC IN OUT 06479-053 FPGA PDCLK DATA 53. SYNC_Inx LVDS 5~150 ps SYNC_Inx SYNC_Inx SYSCLK SYNC_Inx SYSCLKSYNC_Inx ( SYSCLK) (6 )SYSCLK SYSCLK ( ) AD9910SYNC_Inx SYNC_INx Rev. B | Page 45 of 64 AD9910 SYSCLKSYNC_INx (54) ()53 3AD9910 SYNC_INx REFCLK REFCLK SYNC_OUTxSYNC_INx () SYNC_OUT x SYNC_INx 2 ( 4~150 ps) SYSCLK SYNC_INx SYNC_SMP_ERR() REFCLK( )SYNC_INx( ) ( ) SYSCLK SYSCLK1 GHz(1 ns) 12(150ps300ps)SYNC_SMP_ERR SYNC RECEIVER FROM SYNC RECEIVER DELAY LOGIC RISING EDGE DETECTOR AND STROBE GENERATOR D Q SYNC PULSE TO CLOCK GENERATION LOGIC DELAY 44 4 SETUP VALIDATION D Q SYNC VALIDATION DELAY CHECK LOGIC SETUP AND HOLD VALIDATION 12 12 SYNC_SMP_ERR DELAY HOLD VALIDATION SYNC TIMING VALIDATION DISABLE 54. Rev. B | Page 46 of 64 06479-054 DQ SYSCLK AD9910 AD9910 1.8 V 1 0.1 F0.01 F10 F 1718 fOUT50 MHz400 MHz~5% 3.3 V3.3 V1.8 V1.8 V 3.3 V DVDD_I/O (3.3V)(11/15/21/28/45/56/66) 3.3 V AVDD (3.3V)(747783) 3.3 V DAC28 mA 3.3V DVDD (1.8V)(17/23/30/47/57/64) AVDD (1.8V)(3) 1.8 VREFCLK(PLL) 7 mAPLL 1.8 V AVDD 8992 3 PLL3PLL 3 AVDD (1.8V)(6) DVDD 1.8 V AVDD (1.8V)(89/92) 1.8 V REFCLK15 mA 338992 1.8 V Rev. B | Page 47 of 64 AD9910 --I/O AD9910 I/O /AD9910 MSBLSB /(SDIO)2- / (SDIO/SDO) 3- (I/O_RESETCS)AD9910 I/O AD9910 ("") 2(0x01)24 SCLK I/O_RESET I/O_RESETI/O I/O I/O AD99108SCLK I/O_UPDATE I/O profileI/O 2 SCLK profile(0x0E0x15) profileprofileProfile 5 (0x13) PROFILE[0:2]101profile MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 R/W X X A4 A3 A2 A1 A0 R/W--7 .10 X, X--65 A4, A3, A2, A1, A0--43210 I/O SCLK-- /AD9910 CS-- CS SDOSDIO CS(CS) SCLK /(SDIO) AD9910 CFR1(0x00)1 0SDIO (SDO) AD9910I/O Rev. B | Page 48 of 64 AD9910 /(I/O_RESET) I/O I/O_RESETI/O I/O_RESET I/O_RESET(0) 5558I/O I/O /(I/O_UPDATE) MSB/LSB I/O_UPDATEI/O I/O_UPDATE 1SYNC_CLKI/O AD9910(MSB) (LSB) 1 (0x00)0MSBLSB LSB MSB LSB(" "17) INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I5 I6 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 06479-030 SCLK D0 55. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 DON'T CARE DO7 SDO DO5 DO6 DO4 DO3 DO2 DO1 DO0 06479-031 SDIO 56. 3 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 06479-032 SDIO DO0 06479-033 SCLK 57. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 58. 2 Rev. B | Page 49 of 64 DO3 DO2 DO1 AD9910 17. () () 7 (MSB) 6 CFR1 -- 1 (0x00) 31:24 RAM 23:16 OSK Sinc 15:8 LRR @ I/O ARR @ I/O 7:0 DAC REFCLK DAC CFR2-- 2 (0x01) CFR3-- 3 (0x02) 4 3 2 1 0x00 profile DDS 0x00 OSK OSK 0x00 SDIO LSB 0x00 profiles 0x00 23:16 I/O 15:8 I/O 7:0 31:24 23:16 15:8 REFCLK REFCLK B SYNC_CLK 0 (LSB) 31:24 7:0 31:24 23:16 15:8 7:0 I/O 31:24 (0x04) 23:16 15:8 7:0 FTW-- 31:24 23:16 (0x07) 15:8 7:0 DAC (0x03) 5 RAM FTW PDCLK PDCLK DRV0[1:0] Icp[2:0] N[6:0] FSC[7:0] I/O[31:24] I/O[23:16] I/O[15:8] I/O[7:0] [31:24] [23:16] [15:8] [7:0] Rev. B | Page 50 of 64 PFD ( ) TxEnable FM 0x40 0x08 0x20 VCO SEL[2:0] PLL 0x1F 0x3F 0x40 0x00 0x00 0x00 0x00 0x7F 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 1 AD9910 ( ) )* () 7 (MSB) 6 POW-- (0x08) ASF-- (0x09) 15:8 7:0 [15:8] [7:0] 0x00 0x00 31:24 23:16 15:8 [15:8] [7:0] [13:6] 0x00 0x00 0x00 0x00 7:0 (0x0A) (0x0B) (0x0C) (0x0D) Profile 0 (0x0E) 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 5 4 3 2 [5:0] [3:0] 0 (LSB) [1:0] [5:0] [4:0] [4:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0[13:8] 0[7:0] 0[15:8] 0[7:0] 0[31:24] 0[23:16] 0[15:8] 0[7:0] Rev. B | Page 51 of 64 1 0x00 0x00 0x00 0x00 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x08 0xB5 0x00 0x00 0x00 0x00 0x00 0x00 1 AD9910 )* () 7 (MSB) 6 RAM Profile 0 (0x0E) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Profile 1 (0x0F) RAM Profile 1 (0x0F) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 Profile 2 (0x10) RAM Profile 2 (0x10) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 RAM Profile 0 [1:0] RAM Profile 0 [1:0] RAM Profile 1 [1:0] RAM Profile 1 [1:0] RAM Profile 2 [1:0] RAM Profile 2 [1:0] 5 4 3 2 1 0 (LSB) ( ) RAM Profile 0[15:8] RAM Profile 0[7:0] RAM Profile 0[9:2] 0x00 0x00 0x00 0x00 0x00 RAM Profile 0[9:2] 0x00 0x00 RAM Profile 0[2:0] 0x00 1[13:8] 1[7:0] 1[15:8] 1[7:0] 1[31:24] 1[23:16] 1[15:8] 1[7:0] RAM Profile 1[15:8] RAM Profile 1[7:0] RAM Profile 1[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 1[9:2] 0x00 0x00 RAM Profile 1[2:0] 0x00 2[13:8] 2[7:0] 2[15:8] 2[7:0] 2[31:24] 2[23:16] 2[15:8] 2[7:0] RAM Profile 2[15:8] RAM Profile 2[7:0] RAM Profile 2[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 2[9:2] 0x00 0x00 Rev. B | Page 52 of 64 RAM Profile 2[2:0] 0x00 1 AD9910 )* () 7 (MSB) 6 Profile 3 (0x11) 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 RAM Profile 3 (0x11) 31:24 RAM Profile 3 [1:0] 23:16 Profile 4 (0x12) RAM Profile 4 (0x12) 15:8 RAM Profile 3 [1:0] 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 Profile 5 (0x13) RAM Profile 4 [1:0] RAM Profile 4 [1:0] 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 5 4 3 2 1 0 (LSB) ( ) 3[13:8] 3[7:0] 3[15:8] 3[7:0] 3[31:24] 3[23:16] 3[15:8] 3[7:0] RAM Profile 3[15:8] RAM Profile 3[7:0] RAM Profile 3[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 3[9:2] 0x00 0x00 RAM Profile 3[2:0] 0x00 4[13:8] 4[7:0] 4[15:8] 4[7:0] 4[31:24] 4[23:16] 4[15:8] 4[7:0] RAM Profile 4[15:8] RAM Profile 4[7:0] RAM Profile 4[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 4[9:2] 0x00 0x00 5[13:8] 5[7:0] 5[15:8] 5[7:0] 5[31:24] 5[23:16] 5[15:8] 5[7:0] Rev. B | Page 53 of 64 RAM Profile 4[2:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1 AD9910 )* () 7 (MSB) 6 RAM Profile 5 (0x13) 63:56 55:48 47:40 39:32 31:24 RAM Profile 5 [1:0] 23:16 Profile 6 (0x14) RAM Profile 6 (0x14) 15:8 RAM Profile 5 [1:0] 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 Profile 7 (0x15) RAM Profile 7 (0x15) RAM Profile 6 [1:0] RAM Profile 6 [1:0] 7:0 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 63:56 55:48 47:40 39:32 31:24 RAM Profile 7 [1:0] 23:16 RAM (0x16) 1 15:8 RAM Profile 7 [1:0] 7:0 31:0 5 4 3 2 1 0 (LSB) ( ) RAM Profile 5[15:8] RAM Profile 5[7:0] RAM Profile 5[9:2] 0x00 0x00 0x00 0x00 0x00 RAM Profile 5[9:2] 0x00 0x00 RAM Profile 5[2:0] 0x00 6[13:8] 6[7:0] 6[15:8] 6[7:0] 6[31:24] 6[23:16] 6[15:8] 6[7:0] RAM Profile 6[15:8] RAM Profile 6[7:0] RAM Profile 6[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 6[9:2] 0x00 0x00 RAM Profile 6[2:0] 0x00 7[13:8] 7[7:0] 7[15:8] 7[7:0] 7[31:24] 7[23:16] 7[15:8] 7[7:0] RAM Profile 7[15:8] RAM Profile 7[7:0] RAM Profile 7[9:2] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RAM Profile 7[9:2] 0x00 0x00 RAM[31:0] N/A = Rev. B | Page 54 of 64 RAM Profile 7[2:0] 0x00 0x00 1 AD9910 ! I/O023(0x00 0x16)24 22 56(0x050x06) 0x00 1CFR1 () (A:B) (A)(B)5:2 520LSB I/O_UPDATEprofile AD9910 1 (CFR1)--0x00 18. CFR1 31 RAM 0 = RAM() 1 = RAM(/) 1200b 30:29 28:24 23 RAM OSK 22 Sinc 21 20:17 profilel 16 DDS 15 LRR @ I/O 14 0 = DRG() 1 = DDS I/O_UPDATEPROFILE[2:0] I/O _UPDATE PROFILE[2:0] SYNC_CLK 13 0 = DDS() 1 = I/O_UPDATEprofileDDS CFR1[9:8] = 10b 0 = OSK() 1 = OSKOSK("") 0 = SincSinc() 1 = Sinc CFR1[31] = 1I/O 140000b 0 = DDS() 1 = DDS CFR2[19] = 1 0 = () 1 = I/OJJPDATEPROFILE[2:0] Rev. B | Page 55 of 64 AD9910 12 0 = DRG() 1 = DRG1 I/O _UPDATEPROFILE[2:0]SYNC_CLK 11 10 ARR @ I/O 9 OSK 8 OSK 7 6 DAC 5 REFCLK 4 DAC 3 0 = DDS() 1 = DRG CFR1[9:8] = 11b 0 = OSK() 1 = I/OJJPDATEPROFILE[2:0] OSK 0 = OSK() 1 = OSK CFR1[9] = 1 0 =OSK() 1 = OSK I/O 0 = () 1 = 0 = DAC() 1 = DAC I/O 0 = REFCLKPLL() 1 = REFCLKPLL 0 = DAC() 1 = DAC 0 = EXT_PWR_DWN() 1 = EXT_PWR_DWN 2 1 SDIO 0 = SDIO2() 1 = I/O(SDIO)3 0 LSB 0 = I/OMSB() 1 = I/OLSB Rev. B | Page 56 of 64 AD9910 2 (CFR2)--0x01 19. CFR2 31:25 24 profile 23 I/O 22 SYNC_CLK 0 = SYNC_CLK0 1 = SYNC_CLK1/4 fsysclkI/O() 21:20 1100b"(DRG)" 19 18 17 16 FTW 0 = () 1 = "(DRG)" 0 = () 1 = "(DRG)" 0 = () 1 = 0 = FTWI/OFTW() CFR2[19] = 1CFR1[31] = 1CFR1[9] = 1 0 = () 1 = profileASF I/O 0 =I/OI/O_UPDATE () 1 = I/OI/O (I/OJJPDATE) 1 = FTWI/ODDS32 15:14 I/O CFR2[23] = 1I/O 00 = 1() 01 = 2 10 = 4 11 = 8 13:12 11 PDCLK 10 PDCLK 9 TxEnable 8 7 0 = PDCLK0 1 = PDCLKPDCLK() 0 = PDCLKQ1I0() 1 = PDCLK 0 = 1 = 0 = DDS() 1 = DDS Rev. B | Page 57 of 64 AD9910 6 5 4 3:0 FM CFR2[4] = 1 0 = TxENABLE0 D[15:0] F[1:0]()TxENABLE0 1 =TxENABLE1 D[15:0]F[1:0] 0 = SYNC_SMP_ERR() 1 = SYNC_SMP_ERR0() "" 0 =() 1 = ""0000b 3 (CFR3)--0x02 20. CFR3 31:30 29:28 27 26:24 23:22 21:19 18:16 15 DRV0 VCO SEL Icp REFCLK 14 REFCLKB 13:11 10 PFD 9 8 PLL 7:1 N 0 REFCLK_OUT(7)00b REFCLK PLL VCO(8)111b REFCLK PLL(9)111b 0 = () 1 = 0 = 1 =() 0 =() 1 = 0 = REFCLK PLL() 1 = REFCLK PLL 7REFCLK PLL0000000b DAC--0x03 21. DAC 31:8 7:0 FSC 8DAC(DAC)0x7F Rev. B | Page 58 of 64 AD9910 I/O--0x04 I/O 22. I/O 31:0 I/O CFR2[23] = 132/O ("I/O")0xFFFFFFFF (FTW)--0x07 23. FTW 31:0 32 (POW)--0x08 24. POW 15:0 16 (ASF)--0x09 25. ASF 31:16 16CFR1[9:8] = 11b"(OSK)" 15:2 1:0 14 CFR1[9:8] = 11b"(OSK)" Rev. B | Page 59 of 64 AD9910 --0x0A 26. 31:28 27 26 25 24 23:18 17:16 15:11 10:8 7:3 2:0 4SYSCLKSYNC_Inx (~150 ps)0000b 0 = () 1 = 0 = () 1 = 0 = SYSCLK() 1 = SYSCLK 6000000b 5(~150 ps) 00000b 5(~150 ps)00000b --0x0B CFR2[19] = 1"(DRG)" 27. 63:32 31:0 32 32 --0x0C CFR2[19] = 1"(DRG)" 28. 63:32 32 31:0 32 1y1E CFR2[19] = 1"(DRG)" 29. 31:16 16 15:0 16 Rev. B | Page 60 of 64 AD9910 Profile profile8I/O(0x0E 0x015)8profileprofileRAM profileCFR1[31] = 1RAM profileCFR1 [31] = 0CFR2[19] = 0CFR2[4] = 0profile PROFILE[2:0]profile CFR1[31] = 1CFR1 [20:17] 0000bprofile("RAM Profile") Profile 0Profile 7--0x0E0x15 30. Profile 0Profile 7 63:62 61:48 47:32 31:0 14DDS 16DDS 32DDS RAM Profile 0RAM Profile 7--0x0E0x15 31. Profile 0Profile 7 RAM 63:56 55:40 39:30 29:24 23:14 13:6 5 4 3 2:0 RAM 16 10 10 RAM 0 = RAM 1 = RAM RAM 0 = 1 = 13 RAM--0x16 RAM 32. RAM 31:0 RAM RAM Profile 0RAM Profile 7 RAM32(11024) Rev. B | Page 61 of 64 AD9910 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 100 1 75 76 75 100 1 PIN 1 *EXPOSED PAD TOP VIEW (PINS DOWN) 0 MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY 51 25 26 50 BOTTOM VIEW (PINS UP) 51 26 0.50 BSC LEAD PITCH VIEW A 25 50 VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 060408-A 1.05 1.00 0.95 5.00 SQ 59. 100[TQFP_EP] (SV-100-4)() Model AD9910BSVZ1 AD9910BSVZ-REEL1 AD9910/PCBZ1 1 Temperature Range -40C+85C -40C+85C Temperature Range 100(TQFP_EP) 100(TQFP_EP) Z = RoHS Rev. B | Page 62 of 64 Package Option SV-100-4 SV-100-4 AD9910 Rev. B | Page 63 of 64 AD9910 (c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06479-0-12/08( B) Rev. B | Page 64 of 64 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9910/PCBZ AD9910BSVZ-REEL AD9910BSVZ