ADIዐ࿔Ӳຕ֩ᆈ࿔Ӳຕ֩ڦᅳ࿔Lj൩ଌᅳዐీ٪ሞڦᇕჾፇኯᅳٱဃLjADIփܔᅳዐ٪ሞڦֶᅴᆯׂُิڦٱဃሴăසႴඓණඪࢆَᇕڦጚඓႠLj൩֖ADI༵ࠃ
ڦፌႎᆈ࿔Ӳຕ֩ă
1 GSPSĂ14࿋Ă3.3 V CMOS
থຕጴೕ୲ࢇׯഗ
AD9910
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specications subject to change without notice. No
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14-BIT DAC
1GSPS DDS CORE
LINEAR
RAMP
GENERATOR
1024-
ELEMENT
RAM
HIGH SPEED PARALLEL
DATA INTERFACE
TIMING AND CONTROL
SERIAL CONTROL
DATA PORT
REFCLK
MULTIPLIER
06479-001
AD9910
༬Ⴀ
1 GSPSాև้ዓ܈(ߛٳ400 MHzఇె)
ాዃ1 GSPSĂ14࿋DAC
ೕ୲ݴՐ୲ǖ0.23 Hzᅜฉ
၎࿋ሯำǖ≤–125 dBc/Hz(1 kHzೋᅎLj400 MHzሜհ)
ጝሁڦۯༀႠీǖ>80 dB ټSFDR
زႜ/(I/O)
ጲۯ၍Ⴀඪᅪೕ୲/၎࿋/ናޗ௮ࠀీ
8ዖೕ୲ࢅ၎࿋ೋᅎႚ๕
Sin(X)/(X)ၯኟ(ݒኟ၀୳հഗ)
֑ᆩ1.8 Vࢅ3.3 Vۉᇸࠃۉ
/ᆘڦูۉࠀీ
100ᆅগTQFP_EPހጎ
ׯ1024ጴ×32࿋ڦRAM
PLL REFCLKױ݆ഗ
ժႜຕୟ০থ
ڇৗ༹ൻۯڦాևናږഗ
ۙ၎ࠀీ
ۙޗࠀీ
ܠഗཞօ
ᆌᆩ
যՎԨና(LO)ೕ୲ࢇׯ
Պײ้ዓ݀ิഗ
ૃٳࢅ௮ဣཥڦFM၍Ⴀۙೕᇸ
֪ᇑ֪ଉยԢ
ำ࠼ยԢൻۯഗ
ࣅۙഗ
ཌೕ
ࠀీ
1.
!ྔևPLL࣍ୟ୳հഗᇮ ................................................... 27
PLLۨኸସ ................................................................................. 27
ናޗ(OSK) .................................................................... 27
!ۯOSK ................................................................................ 27
!ጲۯOSK ................................................................................ 28
ຕጴၽೢ݀ิഗ(DRG) ............................................................... 28
DRG߁ຎ ................................................................................ 28
DRGၽ୲ ....................................................................... 30
DRG၌ኵ ....................................................................... 30
DRGેഗൣଭ .................................................................. 30
! ኟၽೢ݀ิ ....................................................................... 30
! ݥጂାၽೢ݀ิ ................................................................... 32
DROVERᆅগ ....................................................................... 32
RAM ....................................................................................... 33
RAM߁ຎ ............................................................................... 33
RAMሜ/܁ൽ֡ፕ ............................................................ 33
RAMխݣ֡ፕ)հႚ݀ิ* .................................................. 33
RAM_SWP_OVR)RAM௮ྜׯ*ᆅগ ........................... 34
RAMխݣఇ๕߁ຎ .............................................................. 34
RAMথገ࣑ఇ๕ .............................................................. 34
! ଭሁRAMথገ࣑ఇ๕ ................................................ 35
RAMฉၽೢఇ๕ .................................................................. 35
RAMฉၽೢాևProleఇ๕ ..................................... 36
!ాևProleჄհႚ้Ⴞ ...................................... 38
RAMມၠၽೢఇ๕ .............................................................. 38
RAMჄມၠၽೢఇ๕ ..................................................... 39
RAMჄთ࣍ఇ๕ .............................................................. 41
ഄ༬Ⴀ ........................................................................................ 42
Prole ...................................................................................... 42
I/O_UPDATEĂSYNC_CLKࢅဣཥ้ዓ࠲ဣ ............... 42
!ጲۯI/O߸ႎ .......................................................................... 43
༬Ⴀ ................................................................................................... 1
ᆌᆩ ................................................................................................... 1
ࠀీ ........................................................................................... 1
Ⴊ۩૦๏ ........................................................................................... 4
߁ຎ ................................................................................................... 5
ຍࡀ߭ ........................................................................................... 6
ۉഘࡀ߭ .................................................................................. 6
ܔፌٷܮۨኵ ............................................................................. 9
ڪၳۉୟ .................................................................................. 9
ESDয়ߢ ................................................................................... 9
ᆅগದዃࢅࠀీ௮ຎ ................................................................... 10
ۆ႙߾ፕ༬Ⴀ ................................................................................ 13
ᆌᆩۉୟ ........................................................................................ 16
߾ፕᇱ ........................................................................................ 17
! ڇೕۙఇ๕ ....................................................................... 17
RAMۙఇ๕ ...................................................................... 18
! ຕጴၽೢۙఇ๕ .............................................................. 19
! ժႜຕ܋ۙఇ๕ ...................................................... 20
! !!ժႜຕ้ዓ(PDCLK) ................................................... 20
! !!݀ໃ๑ీ(TxENABLE) .................................................... 21
! ఇ๕ᆫံ ............................................................................ 22
ࠀీၘ ................................................................................ 23
DDSాࢃ ................................................................................ 23
14࿋DAC ....................................................................... 23
! !!ޤዺDAC ............................................................................ 24
!ݒsinc୳հഗ ......................................................................... 24
! ้ዓ(REF_CLK/REF_CLK) ........................................ 24
REF_CLK/REF_CLK ߁ຎ ............................................... 24
! !!ৗ༹ൻۯREF_CLK/REF_CLK ....................................... 25
! !!থൻۯREF_CLK/REF_CLK ....................................... 25
! !!၎࣍(PLL)ױ݆ഗ ......................................................... 25
PLLۉࢁԭ ......................................................................... 26
ణ
AD9910
Rev. B | Page 2 of 64
! !!/ް࿋(I/O_RESET) .......................................... 49
!!!/߸ႎ(I/O_UPDATE) ...................................... 49
!زႜI/O ้Ⴞ ..................................................................... 49
MSB/LSBد ........................................................................ 49
٪ഗࢅ࿋ࠀీ௮ຎ .............................................................. 50
! ٪ഗ࿋ࠀీ௮ຎ .............................................................. 55
! !!ࠀీ٪ഗ1 (CFR1)—ں0x00 .......................... 55
! !!ࠀీ٪ഗ2 (CFR2)—ں0x01 .......................... 57
! !!ࠀీ٪ഗ3 (CFR3)—ں0x02 .......................... 58
!!!ޤዺDAC٪ഗ—ں0x03 ................................. 58
!!!I/O߸ႎ୲٪ഗ—ں0x04 .................................... 59
! !!ೕ୲ۙၿጴ٪ഗ(FTW)— ں0x07 ......................... 59
! !!၎࿋ೋᅎጴ٪ഗ(POW)—ں0x08 ......................... 59
! !!ናޗԲ૩ᅺጱ٪ഗ(ASF)—ں0x09 ....................... 59
! !!ܠႊೌཞօ٪ഗ—ں0x0A ..................................... 60
! !!ຕጴၽೢ၌ኵ٪ഗ—ں0x0B ................................. 60
! !!ຕጴၽೢօ٪ഗ—ں0x0C ................................. 60
! !!ຕጴၽೢ୲٪ഗ—ں0x0D ................................ 60
!!!Prole٪ഗ ..................................................................... 61
ྔႚ٫ ........................................................................................ 62
! ۩ࠔኸళ ................................................................................ 73
! ูۉ ................................................................................ 43
ܠഗཞօ .................................................................................... 44
ۉᇸݴፇ ........................................................................................ 47
3.3 Vۉᇸ ................................................................................ 47
DVDD_I/O (3.3V))ᆅগ11/15/21/28/45/56/66* ........... 47
AVDD (3.3V))ᆅগ7477/83* ...................................... 47
1.8 Vۉᇸ ................................................................................ 47
DVDD (1.8V))ᆅগ17/23/30/47/57/64* ......................... 47
AVDD (1.8V))ᆅগ3* ........................................................ 47
AVDD (1.8V))ᆅগ6* ........................................................ 47
AVDD (1.8V))ᆅগ89/92* ................................................ 47
زႜՊײ ........................................................................................ 48
! থ—زႜI/O ............................................................. 48
! ཚᆩزႜI/O֡ፕ ................................................................. 48
! ኸସጴব ................................................................................ 48
! !!ኸସጴব႑တ࿋ ........................................................... 48
!زႜI/O܋ᆅগࠀీ௮ຎ ............................................... 48
! !!زႜ้ዓ(SCLK) ............................................................... 48
!!!CSႊೌስԀ ................................................................... 48
! !!زႜຕ/(SDIO) ............................................ 48
! !!زႜຕ(SDO) ........................................................ 48
AD9910
Rev. B | Page 3 of 64
Ⴊ߀“DVDD (1.8V)(ᆅগ17/23/30/47/57/64)”ևݴࢅ
“AVDD (1.8V)(ᆅগ89/92)”ևݴ ............................................... 47
Ⴊ߀“থ—زႜI/O”ևݴ ................................................ 48
Ⴊ߀17 ......................................................................................... 50
Ⴊ߀19 ......................................................................................... 57
Ⴊ߀20ࢅ21 ................................................................................ 58
20082ሆ—Ⴊ۩Ӳ0Ⴊ۩ӲA
Ⴊ߀“༬Ⴀ”ևݴ .............................................................................. 1
Ⴊ߀1ዐREFCLKױ݆ഗຍࡀ߭ .......................................... 5
Ⴊ߀SYNC_CLKፌ܌ยዃ้ .................................................... 6
Ⴊ߀I/O Update/Prole[2:0]้Ⴞ༬Ⴀ ........................................ 6
Ⴊ߀TxENABLE/ຕยዃ้(PDCLK)ࢅ
TxENABLE/ຕԍ้(PDCLK) ...................................... 6
Ⴊ߀ഄ้Ⴞ༬Ⴀևݴ ................................................................ 6
Ⴊ߀3 ........................................................................................... 10
Ⴊ߀9Ă10Ă11Ă12Ă13ࢅ14 .......................... 12
Ⴊ߀30ࢅ7 .............................................................................. 24
Ⴊ߀“ጲۯI/O߸ႎ”ևݴ ............................................................. 41
ሺ16LjዘႎಇႾ ................................................................... 41
Ⴊ߀4953 ........................................................................... 43
ሺ“ۉᇸݴፇ”ևݴ ................................................................... 46
ሺ“ཚᆩزႜI/O֡ፕ”ևݴ .................................................... 47
Ⴊ߀17 ......................................................................................... 49
Ⴊ߀19 ......................................................................................... 56
Ⴊ߀20 ......................................................................................... 57
ሺ32 ......................................................................................... 60
20075ሆ—Ⴊ۩Ӳ0ǖ؛๔Ӳ
200812ሆ—Ⴊ۩ӲAႪ۩ӲB
Ⴊ߀2 ............................................................................................ 5
1ዐڦI/O_UPDATEஞ؋܈֖ຕࢅ
Proleፌ܌ൎ࣑ዜ֖ຕ߸߀ .................................................... 7
1ዐሺXTAL_SEL֖ຕ .................................................. 8
Ⴊ߀3 ........................................................................................... 11
Ⴊ߀20 ......................................................................................... 16
Ⴊ߀22 ......................................................................................... 17
Ⴊ߀23 ......................................................................................... 18
Ⴊ߀24 ......................................................................................... 19
Ⴊ߀25 ......................................................................................... 20
Ⴊ߀“REF_CLK/REF_CLK߁ຎ”ևݴ ....................................... 24
Ⴊ߀“ৗናREF_CLK/REF_CLK ”ևݴ ...................................... 25
Ⴊ߀“PLLۨኸସ”ևݴࢅ
“ናޗ(OSK)”ևݴ ........................................................ 27
Ⴊ߀“DRGၽ୲”ևݴࢅ“Քጚၽೢ݀ิ”ևݴ ............... 30
Ⴊ߀“DROVERᆅগ”ևݴ ........................................................... 32
Ⴊ߀43 ......................................................................................... 35
Ⴊ߀“45ࢅాևProleჄհႚ้Ⴞ”
ևݴ ................................................................................................. 38
Ⴊ߀47 ......................................................................................... 40
Ⴊ߀48 ......................................................................................... 41
أ“I/O_UPDATEᆅগ”ևݴ ................................................... 41
Ⴊ߀“Prole”ևݴ ......................................................................... 42
ሺ“I/O_UPDATEĂSYNC_CLKࢅဣཥ้ዓ࠲ဣ”ևݴ ... 42
ሺ“49ǗዘႎಇႾ” ............................................................... 42
Ⴊ߀“ܠഗཞօ”ևݴ ............................................................... 44
AD9910
Rev. B | Page 4 of 64
Ⴊ۩૦๏
AD9910
Rev. B | Page 5 of 64
߁ຎ
06479-002
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
POWER-
DOWN
CONTROL
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK
RAM_SWP_OVR
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
DRCTL
DRHOLD
DROVER
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_CLK
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DAC
14-BIT
DDS
AUX
DAC
8-BIT
AD9910ᅃాዃ14࿋DACڦথຕጴೕ୲ࢇׯഗ
(DDS)Ljኧߛٳ1 GSPS֑ᄣ୲ăAD9910֑ᆩߛDDS
ጆ૧ຍLjሞփဎึႠీڦമ༵ူٷইگࠀࡼă
DDS/DACፇࢇࠓׯຕጴՊײڦߛೕఇెೕ୲ࢇׯ
ഗLjీࠕሞߛٳ400 MHzڦೕ୲ူิׯೕ୲যՎኟ၀հႚă
ᆩࢽᅜݡ࿚ෙ߲ᆩᇀDDSڦ႑ࡽ֖ຕLjԈઔǖ
ೕ୲Ă၎࿋ᇑናޗăDDS૧ᆩ32࿋ેഗ༵ࠃཌೕ
ࢅೕ୲ۙၿݴՐ୲ăሞ1 GSPS֑ᄣ୲ူLjۙၿݴՐ୲ሀ
ྺ0.23 HzăኄDDS࣏ํ၄କ၎࿋ᇑޗ܈ൎ࣑ࠀీă
ᆩࢽཚࡗزႜI/O܋ܔAD9910ڦాև٪ഗႜ
ՊײLjᅜํ၄ܔAD9910ڦăAD9910ׯକৢༀ
RAMLjኧೕ୲Ă၎࿋ࢅ/ናޗۙڦܠዖፇࢇă
AD9910࣏ኧᆩࢽۨᅭڦຕຕጴၽೢ߾ፕఇ๕ăሞఇ
๕ူLjೕ୲Ă၎࿋ናޗໜ้װ၍ႠՎࣅăAD9910ాዃ
ڦߛժႜຕ܋ీํ၄থೕ୲Ă၎࿋Ăናޗ
ࣅۙLjᅜኧ߸ߛڦۙࠀీă
AD9910ሞકቛڦ߾ᄽ࿒܈ݔྷా߾ፕ(ᇡକ߸ܠ႑
တLj൩֖ຕ֩ڦ“ܔፌٷܮۨኵ”ևݴ)ă
2. ၘဦ
ຍࡀ߭
AVDD (1.8V)ࢅDVDD (1.8V) = 1.8 V ± 5%LjAVDD (3.3V) = 3.3 V ± 5%LjDVDD_I/O (3.3V) = 3.3 V ± 5%LjT = 25°CLjRSET = 10 kΩLj
IOUT = 20 mALj্ᆩ้֖ዓ(REFCLK)ױ݆ഗLjྔև้֖ዓೕ୲ = 1000 MHzLjأݥଷᆶຫă
AD9910
Rev. B | Page 6 of 64
ۉഘࡀ߭
ཉ0ጀ֖ຕ ፌၭኵ ۆ႙ኵ ፌٷኵ ڇ࿋
REFCLK༬Ⴀ
ೕ୲ݔྷ
REFCLKױ݆ഗ ্ᆩ 60 1000 MHz
๑ీ 3.2 60 MHz
ඇ࿒܈ݔྷፌٷREFCLKݴೕഗೕ୲ 1500 1900 MHz
ඇ࿒܈ݔྷፌၭREFCLKݴೕഗೕ୲ 25 35 MHz
ྔևৗና 25 MHz
ۉඹ 3 pF
ፆ ֶݴ 2.8 kΩ
ڇ܋ 1.4 kΩ
Բ REFCLKױ݆ഗ্ᆩ 45 55 %
REFCLKױ݆ഗ๑ీ 40 60 %
REFCLKۉೝ ڇ܋ 50 1000 mV p-p
ֶݴ 100 2000 mV p-p
REFCLKױ݆ഗVCO༬Ⴀ
VCOሺᅮ(KV) @ ዐ႐ೕ୲ VCOݔྷยዃ0 429 MHz/V
VCOݔྷยዃ1 500 MHz/V
VCOݔྷยዃ2 555 MHz/V
VCOݔྷยዃ3 750 MHz/V
VCOݔྷยዃ4 789 MHz/V
VCOݔྷยዃ51850 MHz/V
REFCLK_OUT༬Ⴀ
ፌٷඹႠሜ 20 pF
ፌٷೕ୲ 25 MHz
DAC༬Ⴀ
ଉײۉୁ 8.6 20 31.6 mA
ሺᅮဃֶ −10 +10 % FS
ೋᅎ 2.3 µA
ֶݴݥ၍Ⴀ 0.8 LSB
ݴݥ၍Ⴀ 1.5 LSB
ۉඹ 5 pF
֘ା၎࿋ሯำ 1 kHzೋᅎLj20 MHz AOUT
REFCLKױ݆ഗ ্ᆩ −152 dBc/Hz
๑ీLj20x −140 dBc/Hz
๑ీLj100x −140 dBc/Hz
DACۉუݔྷ −0.5 +0.5 V
ټSFDR ֖ۆ႙Ⴀీ
༬Ⴀևݴ
ټSFDR
50.1 MHzఇె ±500 kHz –87 dBc
521± kHz –87 dBc
5.21± kHz –96 dBc
101.3 MHzఇె ±500 kHz –87 dBc
521± kHz –87 dBc
5.21± kHz –95 dBc
1
AD9910
Rev. B | Page 7 of 64
ཉ0ጀ֖ຕ ፌၭኵ ۆ႙ኵ ፌٷኵ ڇ࿋
201.1 MHz ఇె ±500 kHz –87 dBc
521± kHz –87 dBc
5.21± kHz –91 dBc
301.1 MHz ఇె ±500 kHz –86 dBc
521± kHz –86 dBc
5.21± kHz –88 dBc
401.3 MHz ఇె ±500 kHz –84 dBc
521± kHz –84 dBc
5.21± kHz –85 dBc
ز้Ⴞ༬Ⴀ
ፌٷSCLKೕ୲ 70 Mbps
ፌၭSCLK้ዓஞ؋܈ گ 4 ns
4ߛ ns
SCLKፌٷฉื/ူই้ 2 ns
SCLKፌ܌ຕ૬้ 5 ns
SCLKፌ܌ຕԍ้ 0 ns
܁ൽఇ๕ူፌຕᆶၳ้ 11 ns
I/O_UPDATE/PROFILE[2:0]้Ⴞ
༬Ⴀ
SYNC_CLKፌ܌૬้ 1.75 ns
SYNC_CLKፌ܌ԍ้ 0 ns
I/O_UPDATEஞ؋܈ ߛ >1 SYNC_CL
K
ዜ
Proleፌ܌ൎ้࣑ 2 SYNC_CL
K
ዜ
Tx_ENABLEࢅ16࿋ժႜDŽຕDžጺ၍้Ⴞ༬Ⴀ
PDCLKፌٷೕ୲ 250 MHz
TxENABLE/ຕ૬้)PDCLK* 1.75 ns
TxENABLE/ຕԍ้)PDCLK* 0 ns
ഄ้Ⴞ༬Ⴀ
࣓ႝ้2
࣬ް 8 SYSCLK ዜ3
ศ܈ລఇ๕ REFCLKױ݆ഗ๑ీ 1 ms
REFCLKױ݆ഗ্ᆩ
ፌ܌ް࿋ஞ؋܈้)ߛۉೝ* 5 SYSCLK ዜ3
ຕჽ)ୁ၍ჽ*
ڇೕProleఇ๕ຕჽ
ೕ୲Ă၎࿋ࢅናޗDAC ದჽ๑ీࢅOSK
๑ీ
91 SYSCLK ዜ3
ೕ୲ࢅ၎࿋DAC ದჽ๑ీࢅOSK
্ᆩ
79 SYSCLK ዜ3
ದჽ্ᆩ 79 SYSCLK ዜ3
ናޗDAC ದჽ্ᆩ 47 SYSCLK ዜ3
RAMఇ๕ຕჽ
ೕ୲ࢅ၎࿋DAC 94 SYSCLK ዜ3
ದჽ๑ీ/্ᆩ
ናޗDAC ದჽ๑ీ 106 SYSCLK ዜ3
ದჽ্ᆩ 58 SYSCLK ዜ3
௮ఇ๕ຕჽ
ೕ୲ࢅ၎࿋DAC 91 SYSCLK ዜ3
ದჽ๑ీ/্ᆩ
ናޗDAC ದჽ๑ీ 91 SYSCLK ዜ3
ದჽ্ᆩ 47 SYSCLK ዜ3
16࿋ۙఇ๕ຕჽ
ೕ୲ࢅ၎࿋DAC ದჽ๑ీ 103 SYSCLK ዜ3
ದჽ্ᆩ 91 SYSCLK ዜ3
ཉ0ጀ֖ຕ ፌၭኵ ۆ႙ኵ ፌٷኵ ڇ࿋
AD9910
Rev. B | Page 8 of 64
CMOSஇ
Logic 1ۉუ 2.0 V
Logic 0ۉუ 0.8 V
Logic 1ۉୁ 90 120 µA
Logic 0ۉୁ 38 50 µA
ۉඹ 2 pF
XTAL_SEL
Logic 1ۉუ 2.0 V
Logic 0ۉუ 0.8 V
Logic 1ۉୁ 90 120 µA
Logic 0ۉୁ 38 50 µA
ۉඹ 2 pF
CMOSஇ 1 mA ሜ
Logic 1ۉუ 2.8 V
Logic 0ۉუ 0.4 V
ۉᇸۉୁ
IAVDD (1.8 V) 110 mA
IAVDD (3.3 V) 29 mA
IDVDD (1.8 V) 222 mA
IDVDD (3.3 V) 11 mA
ጺࠀࡼ
ڇೕۙఇ๕ 715 850 mW
ูۉఇ๕ 330 400 mW
ศ܈ລఇ๕ 19 25 mW
1VCOݔྷยዃ5ڦሺᅮኵሞೕ୲1000 MHz֪ڥă
࣓ႝ้ኸูٗۉఇ๕࣬ްኟఇ๕ڦ้ăፌ้ኸPLL้֖ዓױ݆ഗPLLዘႎ้֖ۨዓႴ้ă࣓ႝ้ۨ๑ᆩླྀڦPLL࣍ୟ୳հഗኵă
SYSCLKዜኸDDSೌా๑ᆩڦํ้ዓೕ୲ăසࡕ๑ᆩ้֖ዓױ݆ഗױᅜྔև้֖ዓೕ୲LjSYSCLKೕ୲ྺྔևೕ୲ױᅜ้֖ዓԠೕဣຕăසࡕփ๑ᆩ
้֖ዓױ݆ഗLjSYSCLKೕ୲ᇑྔև้֖ዓೕ୲၎ཞă
2
3
ጀᅪLjגᅜฉଚڦܔፌٷܮۨኵీڞዂഗᆦ৳
Ⴀ࣋ăኄኻഽۙڦܮۨኵLjփภഗሞኄၵඪࢆ
ഄཉူגԨຍࡀ߭ኸՔڦࠀీႠ֡ፕăሞ
ܔፌٷܮۨኵཉူ߾ፕࣷᆖၚഗڦႠă
AD9910
Rev. B | Page 9 of 64
ܔፌٷܮۨኵ
2
֖ຕ֖ຕ
AVDD (1.8V)ࢅDVDD (1.8V)ۉᇸ 2 V
AVDD (3.3V)ࢅDVDD_I/O (3.3V)ۉᇸ 4 V
ຕጴۉუ −0.7 V to +4 V
ຕጴۉୁ 5 mA
٪ئ࿒܈ݔྷ −65°C to +150°C
߾ፕ࿒܈ݔྷ −40°C to +85°C
θJA W/C°22
θJC W/C°8.2
ፌߛ࿒ 150°C
ᆅগ࿒܈DŽࡰথ10௱Dž 300°C
ڪၳۉୟ
06479-003
MUST TERMINATE OUTPUTS TO AGND
FOR CURRENT FLOW. DO NOT EXCEED
THE OUTPUT VOLTAGE COMPLIANCE
RATING.
IOUT IOUT
DAC OUTPUTS
AVDD
AVOID OVERDRIVING DIGITAL INPUTS.
FORWARD BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE ONTO POWER
PINS.
DIGITAL INPUTS
INPUT
DVDD_I/O
06479-055
ESDয়ߢ
3. ڪၳۉୟ
4. ڪၳۉୟ
ESD)ৢۉݣۉ*௺ߌഗă
ټۉഗࢅۉୟӱీࣷሞுᆶִڦ൧ူݣۉă
࠶Ԩׂᆶጆ૧ጆᆩԍࢺۉୟLjڍሞᇜڟߛీ
ଉESD้Ljഗీࣷ࣋ăᅺُLjᆌړ֑ൽړڦ
ESDݞݔٯแLjᅜՆ௨ഗႠీူইࠀీෟ฿ă
5. ᆅগದዃ
AD9910
Rev. B | Page 10 of 64
ᆅগದዃࢅࠀీ௮ຎ
26
27
28
29
30
55
54
53
52
51
TQFP-100 (E_PAD)
TOP VIEW
(Not to Scale)
AD9910
D14
D13
DVDD_I/O (3.3V)
DGND
DVDD (1.8V)
5
4
3
2
7
6
9
8
1
11
10
16
15
14
13
18
17
20
19
22
21
12
24
23
25
32
33
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
31
37
D12
D11
D10
D9
D8
D7
D6
D5
D4
PDCLK
TxENABLE
DGND
D3
D2
D1
DVDD_I/O (3.3V)
DVDD (1.8V)
D0
F1
F0
80 IOUT
79 AGND
78 AGND
77 AVDD (3.3V)
76 AVDD (3.3V)
75 AVDD (3. 3V)
74 AVDD (3. 3V)
73 AGND
72 NC
71 I/O_RESET
70 CS
69 SCLK
68 SDO
67 SDIO
66 DVDD_I/O (3.3V)
65 DGND
64 DVDD (1.8V)
63 DRHOLD
62 DRCTL
61 DROVER
60 OSK
59 I/O_UPDATE
58 DGND
57 DVDD (1.8V)
56 DVDD_I/O (3.3V)
SYNC_CLK
PROFILE0
PROFILE1
PROFILE2
DGND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
NC
AGND
XTAL_SEL
REFCLK_OUT
NC
AVDD (1.8V)
REF_CLK
REF_CLK
AVDD (1.8V)
AGND
NC
NC
AGND
DAC_RSET
AVDD (3.3V)
AGND
IOUT
NC
PLL_LOOP_FILTER
AVDD (1.8V)
AGND
AGND
AVDD (1.8V)
SYNC_IN+
SYNC_IN–
SYNC_OUT+
SYNC_OUT–
DVDD_I/O (3.3V)
SYNC_SMP_ERR
DGND
MASTER_RESET
DVDD_I/O (3.3V)
DGND
DVDD (1.8V)
EXT_PWR_DWN
PLL_LOCK
NC
DVDD_I/O (3.3V)
DGND
DVDD (1.8V)
RAM_SWP_OVR
D15
06479-004
PIN 1
INDICATOR
NOTES:
1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.
2. NC = NO CONNECT.
AD9910
Rev. B | Page 11 of 64
3. ᆅগࠀీ௮ຎ
ᆅগՊࡽ I/Oᆅগఁ 1௮ຎ
1, 20, 72, 86, 87,
93, 97 100
NC ႴথăሎႹׂᆅগă
2 PLL_LOOP_FILTER I
PLL࣍ୟ୳հഗցᆅগăၘ൧൩֖“ྔևPLL࣍ୟ୳հഗᇮ”ևݴă
3, 6, 89, 92 AVDD (1.8V) I ఇెాࢃVDDLj1.8Vఇెۉᇸۉუă
AVDD (3.3V) I ఇెDAC VDDLj3.3Vఇెۉᇸۉუă74 77, 83
17, 23, 30, 47,
57, 64
DVDD (1.8V) I ຕጴాࢃVDDLj1.8Vຕጴۉᇸۉუă
11, 15, 21, 28, 45,
56, 66
DVDD_I/O (3.3V) I ຕጴ/VDDLj3.3Vຕጴۉᇸۉუă
4, 5, 73, 78, 79, 82,
85, 88, 96
AGND I ఇెںă
13, 16, 22, 29, 46,
51, 58, 65
DGND I ຕጴںă
7 SYNC_IN+ I
8 SYNC_IN− I
9 SYNC_OUT+ O
10 SYNC_OUT− O
12 SYNC_SMP_ERR O
14 MASTER_RESET I
18 EXT_PWR_DWN I
19 PLL_LOCK O
24 RAM_SWP_OVR O
25 27, 31 39,
42 44, 48
D[15:0] I
49, 50 F[1:0] I ۙ߭๕ᆅগăຕጴඓۨۙ߭๕ă
40 PDCLK O
41 TxENABLE I
52 54 PROFILE[2:0] I
55 SYNC_CLK O
ཞօ႑ࡽ(LVDS)Ljຕጴ)ฉืᄂᆶၳ*ăྔևዷ้ዓڦཞօ႑ࡽཞօాևጱ้ዓă
ၘ൧൩֖“ܠഗཞօ”ևݴă
ཞօ႑ࡽ(LVDS)Ljຕጴăྔևዷ้ዓڦཞօ႑ࡽཞօాևጱ้ዓă
ၘ൧൩֖“ܠഗཞօ”ևݴă
ཞօ႑ࡽ(LVDS)Ljຕጴ)ฉืᄂᆶၳ*ăాևഗጱ้ዓڦཞօ႑ࡽཞօྔևٗഗă
ၘ൧൩֖“ܠഗཞօ”ևݴă
ཞօ႑ࡽ(LVDS)Ljຕጴăాևഗጱ้ዓڦཞօ႑ࡽཞօྔևٗഗă
ၘ൧൩֖“ܠഗཞօ”ևݴă
ཞօ֑ᄣဃֶLjຕጴ)ߛۉೝᆶၳ*ăཞօ֑ᄣဃֶǖُᆅগߛۉೝAD9910࿄
ڟᆶၳSYNC_IN+/SYNC_IN−ཞօ႑ࡽă
ዷް࿋Ljຕጴ)ߛۉೝᆶၳ*ăዷް࿋ǖᆶ٪ئᇮൣ0Lj٪ഗยዃྺఐණኵă
ྔևูۉఇ๕Ljຕጴ)ߛۉೝᆶၳ*ăُᆅগߛۉೝࣷഔᆩړമՊײڦูۉሏႜఇ๕ă
ၘ൧൩֖“ูۉ”ևݴăස࿄๑ᆩLjᆌথںă
้ዓױ݆ഗPLLۨLjຕጴ)ߛۉೝᆶၳ*ăُᆅগߛۉೝ๖้ዓױ݆ഗPLLᅙۨ
้֖ዓă
RAM௮ྜׯLjຕጴ)ߛۉೝᆶၳ*ăُᆅগߛۉೝ๖RAM௮ྜׯă
RAM௮ྜׯLjຕጴ)ߛۉೝᆶၳ*ăُᆅগߛۉೝ๖RAM௮ྜׯă
ժႜຕ้ዓăຌᇀຕጴ)้ዓ*ăժႜຕ้ዓ༵ࠃ้Ⴞ႑ࡽܔഋժႜຕă
݀ໃ๑ీăຕጴ)ߛۉೝᆶၳ*ăሞ݀ఇ๕ཚ႑ዐLjُᆅগߛۉೝ๖݀ໃႎຕă
ሞჄఇ๕ዐLjُᆅগ๔ዕԍߛۉೝă
1/4้ዓăຌᇀຕጴ)้ዓ*ăAD9910ዐܠຕጴLjසI/O_UPDATEࢅ
PROFILE[2:0]LjۼႴᄲሞ႑ࡽฉืᄂยዃă
Proleስᆅগăຕጴ)ߛۉೝᆶၳ*ă๑ᆩُᆅগስᅃዖDDS၎࿋/ೕ୲prole
)ࠌ8ዖ*ă߀ՎᆅগጒༀLjᆶړമI/O࣐؋ాඹدڟ၎ᆌ٪ഗăᄲ߀ՎጒༀLj
ยዃSYNC_CLKᆅগă
ཞօ႑ࡽ(LVDS)Ljຕጴ(ฉืᄂᆶၳ)ăྔևዷ้ዓڦཞօ႑ࡽཞօాևጱ้ዓă
ၘ൧൩֖“ܠഗཞօ”ևݴă
ናޗăຕጴ(ߛۉೝᆶၳ)ăሞۯጲۯఇ๕ዐഔᆩOSKࠀీ้Ljཚࡗ
ُᆅগăሞۯఇ๕ዐLjُᆅগሞ0(گ)ࢅՊײናޗԲ૩ᅺጱ(ߛ)ኮൎ࣑ױ݆
ഗăሞጲۯఇ๕ዐLjگۉೝၠူ௮ናޗ0Ljߛۉೝၠฉ௮ናޗናޗԲ૩ᅺ
ጱă
ຕጴၽೢຐăຕጴ(ߛۉೝᆶၳ)ăړຕጴၽೢ݀ิഗٳڟፌٷ/ፌၭՊײኵ
้Ljُᆅগൎ࣑ڟஇ1ă
ຕጴၽೢăຕጴ(ߛۉೝᆶၳ)ăُᆅগຕጴၽೢ݀ิഗڦၽ୲Ⴀă
ၘ൧൩֖“ຕጴၽೢ݀ิഗ(DRG)”ևݴăසࡕ࿄๑ᆩຕጴၽೢ݀ิഗLjُᆅগᇑ
இ0থă
ຕጴၽೢԍăຕጴ(ߛۉೝᆶၳ)ăُᆅগ๑ຕጴၽೢ݀ิഗԍړമጒༀă
ၘ൧൩֖“ຕጴၽೢ݀ิഗ(DRG)”ևݴăසࡕ࿄๑ᆩຕጴၽೢ݀ิഗLjُᆅগᇑ
இ0থă
زႜຕ/ăຕጴ/(ߛۉೝᆶၳ)ăߵದዃ൧Ljُᆅগኧڇၠ
ࢅມၠDŽఐණDžଇዖఇ๕ăසࡕມၠزႜ܋ఇ๕Ljُᆅগᆩᇀزႜຕ
ࢅăසࡕڇၠఇ๕Ljৈኧຕă
زႜຕăຕጴ(ߛۉೝᆶၳ)ăُᆅগৈܔڇၠزႜຕఇ๕ᆶၳLjᆩᇀ
ຕăມၠఇ๕ዐLjُᆅগ֡ፕLjᆌă
زႜຕ้ዓăຕጴ้ዓ(ฉืᄂኴႜႀ֡ፕLjူইᄂኴႜ܁֡ፕ)ăُᆅগ༵ࠃ
ຕୟ০ڦزႜຕ้ዓăAD9910ႀ֡ፕ๑ᆩฉืᄂLj࣮܁֡ፕ๑ᆩူইᄂă
ႊೌስăຕጴ(گۉೝᆶၳ)ăAD9910૧ᆩُᆅগሞຕୟ০ཚᆩزႜ
ጺ၍ฉሏႜăᆅগگۉೝ๑AD9910֪زႜ้ዓฉื/ူইᄂăᆅগߛۉೝ๑
AD9910ࢮزႜຕᆅগă
/ް࿋ăຕጴ(ߛۉೝᆶၳ)ăړ/ཚ႑ዜ၄ࠤቱ้Lj๑ᆩُ
ᆅগ(ၘ൧൩֖“/ް࿋(I/O_RESET)”ևݴ)ăփ๑ᆩ้Ljᆅগথںă
DACࢻցۉୁᇸăఇె(ۉୁఇ๕)ăཚࡗ50ۉፆഗᇑAGNDথă
DACۉୁᇸăఇె(ۉୁఇ๕)ăཚࡗ50ۉፆഗᇑAGNDথă
ఇె֖ᆅগăُᆅগܔDACଉײ֖ۉୁՊײăAGNDথᅃ߲10kۉፆ
ഗă
้֖ዓăఇెă๑ᆩాևናږഗ้LjُᆅগᅜཚࡗྔևናږഗൻۯLj
ኁᇑৗ༹থথăၘ൧൩֖“REF_CLK/REF_CLK ߁ຎ”ևݴă
้֖ዓăఇెăၘ൧൩֖“REF_CLK/REF_CLK ߁ຎ”ևݴă
ৗ༹ናږഗăఇెăၘ൧൩֖“REF_CLK/REF_CLK ߁ຎ”ևݴă
ৗ༹ናږഗስ)1.8 Vஇ*ăఇె)ߛۉೝᆶၳ*ăߛۉೝൻۯXTAL_SELᆅগLj
AVDD(1.8V)ᆅগ๑ాևናږഗᇑৗ༹ၿናഗࠌཞሏႜăසࡕ࿄๑ᆩLjথAGNDă
EPADᆌࡰথথںă
ᆅগՊࡽ I/Oᆅগఁ 1௮ຎ
AD9910
Rev. B | Page 12 of 64
59 I/O_UPDATE I/O
60 OSK I
61 DROVER O
62 DRCTL I
63 DRHOLD I
67 SDIO I/O
68 SDO O
69 SCLK I
70 CS I
71 I/O_RESET I
80 IOUT O
81 IOUT O
84 DAC_RSET O
90 REF_CLK I
91 REF_CLK I
94 REFCLK_OUT O
95 XTAL_SEL I
96 (EPAD) ࡰಎ
(EPAD)
1 I = ǗO = ă
AD9910
Rev. B | Page 13 of 64
ۆ႙߾ፕ༬Ⴀ
–
50
–55
–60
–65
–75
–70
06479-034
SFDR (dBc)
OUTPUT FREQUENCY (MHz)
SFDR WITHOUT PLL
SFDR WITH PLL
0 50 100 150 200 250 300 350 400
400 450052003 350200150100500
06479-046
SFDR (dBc)
OUTPUT FREQUENCY (MHz)
–75
–70
–65
–60
–55
–
45
–50
LOW SUPPLY
HIGH SUPPLY
400 450300250 350050010510020
06479-047
SFDR (dBc)
OUTPUT FREQUENCY (MHz)
–75
–70
–65
–60
–55
–
50
–40°C
+85°C
START 0Hz
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
50MHz/DIV STOP 500MHz
06479-035
1
SFDR (dBc)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
START 0Hz 50MHz/DIV STOP 500MHz
06479-036
1
SFDR (dBc)
06479-037
START 0Hz
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
50MHz/DIV STOP 500MHz
1
SFDR (dBc)
6. ټSFDRᇑೕ୲ڦ࠲ဣ
(PLL้֖ዓೕ୲ = 15.625 MHz64)
9. 10 MHzཉူڦټSFDRLjREFCLK = 1 GHz
10. 204 MHzཉူڦټSFDRLjREFCLK = 1 GHz
11. 403 MHzཉူڦټSFDRLjREFCLK = 1 GHz
7. ټSFDRᇑೕ୲ࢅۉᇸڦ࠲ဣ
(±5%)LjREFCLK = 1 GHz
8. ټSFDRᇑೕ୲ࢅ࿒܈ڦ࠲ဣLj
REFCLK = 1 GHz
AD9910
Rev. B | Page 14 of 64
06479-038
CENTER 10.32MHz
–120
–108
–96
–84
–72
–60
–48
–36
–24
–12
0
2.5kHz/DIV SPAN 25kHz
1
SFDR (dBc)
06479-039
CENTER 204.36MHz
–120
–108
–96
–84
–72
–60
–48
–36
–24
–12
0
2.5kHz/DIV SPAN 25kHz
1
SFDR (dBc)
06479-040
CENTER 403.78MHz
–120
–108
–96
–84
–72
–60
–48
–36
–24
–12
0
2.5kHz/DIV SPAN 25kHz
1
SFDR (dBc)
–
90
–100
–120
–110
–140
–150
–130
–170
–160
M001k001k01k100101 1M 10M
06479-042
MAGNITUDE (dBc/Hz)
FREQUENCY OFFSET (Hz)
fOUT = 20.1MHz
fOUT = 98.6MHz
fOUT = 201.1MHz
fOUT = 397.8MHz
12. 10.32 MHzཉူڦټSFDRLjREFCLK = 1 GHz 14. 403.78 MHzཉူڦټSFDRLjREFCLK = 1 GHz
15. ֘ା၎࿋ሯำLj1 GHz߾ፕೕ୲LjPLL্ᆩ
13. 204.36 MHzཉူڦټSFDRLjREFCLK = 1 GHz
AD9910
Rev. B | Page 15 of 64
–
90
–100
–110
–120
–130
–140
–150
–16010 100 1k 10k 100k 1M 10M 100M
06479-043
MAGNITUDE (dBc/ Hz)
FREQUENCY OFFSET (Hz)
f
OUT
= 20.1MHz
f
OUT
= 397.8MHz
f
OUT
= 98.6MHz
f
OUT
= 201.1MHz
400
450
300
250
350
200
150
100
50
0
100 200 300 400 500 600 700 800 900 1000
06479-044
POWER DISSIPATION (mW)
SYSTEM CLOCK FREQUENCY (MHz)
DVDD 3.3V
AVDD 3.3V
AVDD 1.8V
DVDD 1.8V
400
450
300
250
350
200
150
100
50
0
400 500 600 700 800 900 1000
06479-045
POWER DISSIPATION (mW)
SYSTEM CLOCK FREQUENCY (MHz)
DVDD 1.8V
AVDD 1.8V
AVDD 3.3V
DVDD 3.3V
16. ֘ା၎࿋ሯำLj1 GHz߾ፕೕ୲Lj
50 MHz้֖ዓೕ୲Lj20× PLLױ݆ഗ
17. ࠀࡼᇑဣཥ้ዓೕ୲(PLL্ᆩ)
18. ࠀࡼᇑဣཥ้ዓೕ୲(PLL๑ీ)
AD9910
Rev. B | Page 16 of 64
ᆌᆩۉୟ
LOOP
FILTER
PHASE
COMPARATOR VCO
AD9910
REF_CLK
REFERENCE
CHARGE
PUMP
AD9510, AD9511, ADF4106
÷
÷
06479-056
LPF
AD9910
(SLAVE 1)
AD9910
(MASTER)
CLOCK
SOURCE
AD9910
(SLAVE 2)
AD9910
(SLAVE 3)
FPGA
DATA
SYNC_CLK
REF_CLK
SYNC_CLK
SYNC_CLK
FPGA
DATA
FPGA
DATA
DATA
FPGA
SYNC_CLK
C1
S1
C2
S2
C3
S3
C4
S4
A1
A2
A4
A3
A_END
CENTRAL
CONTROL
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
SYNC_OUT
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
06479-058
AD9910
REFCLK
n
PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)
n = DEPENDENT ON PRODUCT SELECTION.
AD9515
AD9514
AD9513
AD9512
LVPECL
LVDS
CMOS
CH 2
06479-057
LPF
19. PLLݒઍ֖ۨೕ୲DDS༵ࠃೕ୲ࢅჽۙኝۙၿ
20. ᆩAD9510ፕྺ֖ࢅཞօ้ዓݴದഗཞօܠ߲ഗᅜሺٷཚڢඹଉ
21. ๑ᆩAD9512/AD9513/AD9514/AD9515ဣଚ้ዓݴದႊೌڦ้ዓิׯۉୟ
$'
Rev. B | Page 17 of 64
߾ፕᇱ
06479-005
16
PARAL LEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
POWER-
DOWN
CONTROL
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK A
θINVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
AUX
DAC
8-BIT
DAC
14-BIT
DDS
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
SYNC_CLK
22. ڇೕۙఇ๕
AD9910ኧ຺ዖ߾ፕఇ๕ǖ
t ڇೕۙఇ๕
t RAMۙఇ๕
t ຕጴၽೢۙఇ๕
t ժႜຕ܋ۙఇ๕
ኄၵఇ๕૧ᆩփཞڦDDSຕᇸׂิ႑ࡽ֖ຕǖೕ
୲Ă၎࿋ናޗăߵ߾ፕఇ๕ࢅ/༹࿋Ljጲۯ
ຕӀೕ୲Ă၎࿋ࢅናޗݴׯփཞڦፇࢇă
ሞڇೕۙఇ๕ዐLjথ๑ᆩᇑزႜI/O܋ᆶ࠲Պײ
٪ഗ༵ࠃڦDDS႑ࡽ֖ຕăሞRAMۙఇ๕ዐLjDDS
႑ࡽ֖ຕԍ٪ሞాևRAMዐLjཚࡗంସۙᆩăሞຕጴ
ၽೢۙఇ๕ዐLjDDS႑ࡽ֖ຕཚࡗຕጴၽೢ݀ิഗ
༵ࠃăሞժႜຕ܋ۙఇ๕ዐLjDDS႑ࡽ֖ຕᆯ
ժႜ܋থă
߳ዖۙఇ๕ᅃӯኻ๑ᆩᅃዖDDS႑ࡽ֖ຕDŽࣅۙ
߭๕๑ᆩଇዖ֖ຕDžă࿄ۙڦDDS႑ࡽ֖ຕԍ٪
ሞ၎ᆌڦՊײ٪ഗዐLjߵ߾ፕఇ๕ጲۯدໃڟ
DDSă
ଷྔLjAD9910࣏ᆶ܀૬ڦናޗ(OSK)ࠀీăཚ
ࡗ܀૬ڦຕጴ၍Ⴀၽೢ݀ิഗLjኻܔDDSናޗ֖ຕׂิፕ
ᆩăᇑഄຕᇸ၎ԲLjOSKࠀీᅜᆫံൻۯDDSናޗ
֖ຕăᅺُLjᅃڋഔᆩOSKࠀీLjഄຕᇸ݆ൻۯ
DDSናޗă
Ԩ࿔ࣷݴ՚ถ߳ዖ߾ፕఇ๕DŽԈઔOSKࠀీDžLjڍ
ํ֡ፕ้ᅜཞ้ഔᆩܠዖఇ๕ăᅺُLjኄྺದዃްሗ
ۙݛӄټઠକٷڦଳႠăྺՆ௨ܠຕᇸൻۯཞᅃ
DDS႑ࡽ֖ຕLjAD9910ׯକాևᆫံၹᅱDŽ֖
“ఇ๕ᆫံ”ዐڦ5Džă
ڇೕۙఇ๕!
ሞڇೕۙఇ๕ዐLjDDS႑ࡽ֖ຕᆯՊײ٪ഗথ
༵ࠃăProleᅃ߲ԈઔDDS႑ࡽ֖ຕڦ܀૬٪
ഗăAD9910ࠌᆶ8߲Prole٪ഗLj
߲Proleۼీڇ܀ݡ࿚ă૧ᆩෙ߲ྔևproleᆅগ
(PROFILE[2:0])ስၙᄲڦproleă߀ՎProleᆅগጒༀ
ሞSYNC_CLKူᅃฉืᄂ๑ᆩProleዐኸ֖ۨຕ߸
ႎDDSă
AD9910
Rev. B | Page 18 of 64
06479-006
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK A
θINVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
SYNC_CLK
POWER-
DOWN
CONTROL
RAMۙఇ๕
RAMۙఇ๕(֖23)ᆯRAM๑ీ࿋ࢅI/O_UPDATEᆅ
গ(߀ՎProle)ăሞُఇ๕ዐLjۙڦDDS႑ࡽ
֖ຕথཚࡗRAM༵ࠃă
RAMᆯ1024×32࿋ጴፇׯăཚࡗްሗڦాևጒༀದ
ࢇLjRAMݥଳںิׯໜ้ՎࣅڦඪᅪհႚăՊ
ײ้ۨഗRAMၠDDS݀ໃጴڦ୲ăᅺُLjՊ
ײ้ۨഗۨକၠDDS݀ໃڦ32࿋ᄣԨڦ֑ᄣ୲ă
DDS༹႑ࡽ֖ຕ(RAMᄣԨ݀ໃణڦں)ᄺཚࡗ8߲
܀૬ڦRAM Prole٪ഗՊײă๑ᆩෙ߲ྔևProle
ᆅগ(PROFILE[2:0])ስ༹ڦProleăඪࢆProleᆅগ
ጒༀڦ߀ՎࣷሞSYNC_CLKူᅃฉืᄂڦRAM
Proleă
ሞRAMۙఇ๕ዐLjิׯໜ้ՎࣅڦናޗĂ၎࿋ೕ
୲႑ࡽLjܸٗํ၄ܔඪᅪDDSሜհ႑ࡽ֖ຕۙڦࠀ
ీăଷྔLj૧ᆩࣅۙ߭๕࣏ీRAMᄣԨݴׯናޗݴ
ଉࢅ၎࿋ݴଉǗ၎࿋ݴଉ܈ྺ16࿋Ljናޗݴଉ܈ྺ14
࿋ă
23. RAMۙఇ๕
AD9910
Rev. B | Page 19 of 64
06479-007
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK A
θINVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
SYNC_CLK
POWER-
DOWN
CONTROL
24. ຕጴၽೢۙఇ๕
ຕጴၽೢۙఇ๕
ሞຕጴၽೢۙఇ๕(֖24)ዐLjۙڦDDS႑ࡽ
֖ຕᆯຕጴၽೢ݀ิഗ(DRG)থ༵ࠃăၽೢ݀ิ֖ຕᆯ
زႜI/O܋ă
૧ᆩၽೢ݀ิ֖ຕLjᆩࢽᅜၽೢڦฉืࢅူইၽ
୲ăၽೢڦฉူ၌ኵĂၽೢฉื/ူইևݴڦօࢅօ୲
Պײă
ၽೢ֑ᆩຕጴࣅิׯLjݴՐ୲32࿋ăDRGڦ32࿋
ᅜܔೕ୲Ă၎࿋ናޗႜՊײăՊײೕ୲้Ljᄲᆩڟ
ᆶ32࿋ăܸՊײ၎࿋ናޗ้ݴ՚ኻႴᆩ16࿋ࢅ14࿋
MSBă
ၽೢݛၠ(ฉืူই)ཚࡗDRCTLᆅগྔևăᆩࢽ๑
ᆩDRHOLDᆅগ࣏ీԍၽೢ݀ิഗڦړമጒༀă
25. ժႜຕ܋ۙఇ๕
AD9910
Rev. B | Page 20 of 64
06479-008
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
POWER-
DOWN
CONTROL
EXT_PWR_DWN
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK A
θINVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CLOCK MODE
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SERIAL I/O PORT
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYNC_SMP_ERR
SYNC_OUT
SYNC_IN
PLL_LOCK
PLL_LOOP_FILTER
MASTER_RESET
2
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
SYNC_CLK
ժႜຕ܋ۙఇ๕
ሞժႜຕ܋ۙఇ๕(֖25)ዐLjۙڦDDS႑ࡽ
֖ຕথᆯ18࿋ժႜຕ܋༵ࠃă
ຕ܋ݴྺଇևݴă16߲MSB࿋ፇׯ16࿋ຕጴ(D[15:0]
ᆅগ)Ljଇ߲LSB࿋ፇׯ2࿋ణڦጴ(F[1:0]ᆅগ)ăణڦጴۨ
ᅭକ16࿋ຕጴፕྺDDS႑ࡽࢆዖ֖ຕ๑ᆩă4ߴ
କణڦ࿋Ă16࿋ຕጴࣄݴᅜຕణڦ(࠲ᇀDDS႑ࡽ
֖ຕ)ኮڦ࠲ဣăஃణڦසࢆLj16࿋ຕጴۼ֑ᆩ
ޙࡽܾ߭๕๖ă
ړణڦ࿋ኸ๖ຕጴྺDDSೕ୲֖ຕ้Lj16࿋ຕጴ
ፕྺFTW٪ഗዐ32࿋ೕ୲ۙၿጴڦೋᅎጴăᄺ৽ຫ
16࿋ຕጴՂႷᇑFTW٪ഗዐڦ32࿋ጴཚࡗగዖݛ๕ኟ
ඓܔഋăኄᅃۅᅜཚࡗՊײ٪ഗዐڦ4࿋FMሺᅮጴํ
၄ăᆩࢽᅜཚࡗFMሺᅮጴྺ16࿋ຕጴཁᅃ߲
ᅺጱăఐණጒༀူ(0)Lj16࿋ຕጴࢅFTW٪ഗዐڦ32࿋
ጴཚࡗLSBܔഋăFMሺᅮጴኵڿሺ1ۼࣷ16࿋ຕጴ
၎ܔᇀFTW٪ഗዐڦ32࿋ጴၠፑᅎ1࿋Ljܸٗ16࿋ຕ
ጴܔFTW٪ഗۨᅭೕ୲ڦᆖၚՎٷLjᅺጱྺ2ăFM
ሺᅮጴᅜᆶၳຕጴহۨڦೕ୲ݔྷă
ժႜຕ้ዓ(PDCLK)
AD9910ᅜሞPDCLKᆅগฉׂิᅃ߲1/4 DAC֑ᄣ୲ڦ
้ዓ႑ࡽ(ժႜຕ܋֑ᄣ୲)ăPDCLKፕྺժႜ܋
ڦຕ้ዓ๑ᆩăఐණ൧ူLjPDCLKڦ߲ฉืᄂᆩᇀ
ᆩࢽ༵ࠃڦ18࿋ຕ٪ሞຕ܋ዐăᄂڦႠཚ
ࡗPDCLKݒገ࿋߸߀ăଷྔLjPDCLK႑ࡽᅜᆩ
PDCLK๑ీ࿋࠲ԿăփࡗLj๑ీ࠲Կ႑ࡽLjᅈ৹
ሞాևሏႜLjཚࡗాևPDCLK้Ⴞվጛժႜ܋ฉڦຕ
ăጀᅪPDCLK্ᆩ้ྺྺஇ0ă
AD9910
Rev. A | Page 21 of 64
4. ժႜ܋ణڦ࿋
ኁLjසࡕփTxENABLEᆅগፕྺோLjᄺᅜཚࡗ
ᅜժႜ܋ຕ୲ሏႜڦ้ዓ႑ࡽൻۯTxENABLEăᆯ
้ዓ႑ࡽൻۯ้Ljᆯڟኈڦጒༀገ࣑ՂႷፁ߲ዜ
૬ࢅԍ้ᄲ൱Ljඓԍኟ߾ፕăTxENABLEࢅ
PDCLK้Ⴞ֖26ă
݀ໃ๑ీ(TxENABLE)
AD9910࣏ీཚࡗTxENABLEᆅগኧᆩࢽิׯڦ႑ࡽLj
ᆅগፕྺᆩࢽຕڦோăሞఐණ൧ူLjTxEN-
ABLEᆅগஇோዐ1๖ኈLj0๖ǗփࡗLjཚࡗTxEN-
ABLEݒ၎࿋ᅜ๑ᆅগᆶݒၠஇ༬ႠăړTxENABLE
ྺኈ้LjሞᇨڦPDCLKᄂฉຕ٪ሞഗዐ)ᇀ
PDCLKݒ၎࿋*ăړTxENABLEྺ้Lj๑PDCLKీࠕ
ჄሏႜLjഗᄺࣷࢮၠ܋༵ࠃڦຕăଷྔLjړ
TxENABLEᆅগԍ้Ljഗࣷሞాևൣأ18࿋ຕ
ጴLjኁԍାຕ܋ሞTxENABLEൎ࣑ڟஇጒༀമ
ڦፌࢫڦኵă(ൽᇀຕࣹՊഗසࢆԍାፌࢫڦຕኵ࿋ڦ
ยዃ൧)ă
F[1:0] D[15:0] ֖ຕ Ԣጀ
00 D[15:2] 14 ࿋ናޗ֖ຕDŽޙࡽኝຕDž
01 D[15:0] 16 ࿋၎࿋֖ຕDŽޙࡽኝຕDž
10 D[15:0] 32 ࿋ೕ୲֖ຕDŽޙࡽኝຕDž
11 D[15:8] 8࿋ናޗ֖ຕDŽޙࡽኝຕDž
D[7:0] 8࿋၎࿋֖ຕDŽޙࡽኝຕDž
ናޗݔྷǖ01 − 2−14ăD[1:0]࿄๑ᆩă
၎࿋ೋᅎݔྷǖ02π(1 − 2−16)ࢷ܈ă
ܔഋ16࿋ຕጴࢅ32࿋ೕ୲֖ຕᆯՊײ٪ഗዐڦ4࿋FMሺᅮጴă
ຕጴናޗMSBᇑDDS 14࿋ናޗ֖ຕMSBܔഋăDDSናޗ֖ຕ6࿋LSBᆯ
ASF٪ഗڦ[5:0]࿋ኸۨăׂิڦ14࿋ጴ๑ናޗݔྷٳڟǖ01 − 2−14ă
ຕጴ၎࿋MSBᇑDDS 16࿋၎࿋֖ຕMSBܔഋăDDS၎࿋֖ຕ8࿋LSBᆯ
POW٪ഗڦ[7:0]࿋ኸۨăׂิڦ16࿋ጴ๑၎࿋ೋᅎݔྷٳڟǖ02π
(1 − 2−16)ࢷ܈ă
06479-009
FALSE
TRUE
TxENABLE
(BURST)
TxENABLE
(CLOCK)
WORD1WORD2WORD3WORD4WORDN – 4 WORDN
PDCLK
PARALLEL
DATA PORT
t
DS
t
DS
t
DH
t
DH
26. PDCLKࢅTxENABLE้Ⴞ
AD9910
Rev. 0 | Page 22 of 64
ఇ๕ᆫံ
ෙዖփཞڦۙఇ๕ۼీิׯDDS႑ࡽ֖ຕǖೕ୲Ă
၎࿋ࢅ/ናޗăଷྔLjOSKࠀీᅜิׯDDSናޗຕ
֖ຕă๑ᆩࢇڦ࿋ཚࡗزႜI/O܋ᅜ܀૬ۙ
ᆩฉຎඪᅃዖࠀీă
܀૬ኄၵࠀీᅜํ၄ܠዖຕᇸࠌ٪Ljൻۯཞᅃ
DDS႑ࡽ֖ຕڦణڦăྺՆ௨؋LjAD9910ׯକᅃ
༫ᆫံ
ဣཥă5ߴକዖDDS႑ࡽ֖ຕڦᆫံ
ă5ዐڦႜ๖గዖDDS႑ࡽ֖ຕڦຕᇸLjӀ
ইႾಇଚᆫံă૩සLjසࡕRAMࢅժႜຕ܋ཞ้๑
ీLjଇዖఇ๕Պײׂิೕ୲֖ຕLjఫDDSೕ୲֖
ຕᆌᆯRAMൻۯLjܸփժႜຕ܋ă
5. ຕᇸᆫံ
ᆫံ
DDS႑ࡽ֖ຕ
ናޗ၎࿋ೕ୲
ຕᇸ ཉ ຕᇸ ཉ ຕᇸ ཉ
ፌߛ
ᆫံ
RAM RAM๑ీLjຕ
ణڦྺೕ୲
RAM RAM๑ీLjຕ
ణڦྺ၎࿋Ⴀ
OSK݀ิഗ OSK๑ీ
(ጲۯఇ๕)
DRG DRG๑ీLjຕ
ణڦྺೕ୲
DRG DRG๑ీLjຕ
ణڦྺ၎࿋
ASF٪ഗ OSK๑ీ
)ۯఇ๕*
ժႜຕ܋
ࢅFTW٪ഗ
ժႜຕ܋๑ీLj
ຕణڦྺೕ୲
ժႜຕ܋ ժႜຕ܋๑ీLj
ຕణڦྺ၎࿋
RAM RAM๑ీLjຕ
ణڦྺናޗႠ
FTW٪ഗ RAM๑ీLjຕ
ణڦྺ၎࿋Ăናޗ
Ⴀ
ժႜຕ܋૾থ
POW٪ഗLSB
ժႜຕ܋๑ీLj
ຕణڦྺႠ
DRG DRG๑ీLjຕ
ణڦྺናޗ
ᆶၳFTWڇೕ
prole٪ഗ
DRG๑ీLjຕ
ణڦྺ၎࿋ናޗ
POW٪ഗ RAM๑ీLjຕ
ణڦྺೕ୲ናޗ
ժႜຕ܋ ժႜຕ܋๑ీLj
ຕణڦྺናޗ
ᆶၳFTWڇೕ
prole٪ഗ
ժႜຕ܋๑ీLj
ຕణڦྺ၎࿋Ă
ናޗႠ
ᆶၳPOWڇೕ
prole٪ഗ
DRG๑ీLjຕ
ణڦྺೕ୲ናޗ
ժႜຕ܋૾থ
ASF٪ഗLSB
ժႜຕ܋๑ీLj
ຕణڦྺႠ
ᆶၳFTWڇೕ
prole٪ഗ
ᆶၳPOWڇೕ
prole٪ഗ
ժႜຕ܋๑ీLj
ຕణڦྺೕ୲
ናޗ
ᆶၳASFڇೕprole
٪ഗ
ናޗݔྷᆯ
ڇೕprole ࿋ፇ
(CFR2[24])
ፌگ
ᆫံ
ᆶၳPOWڇೕ
prole٪ഗ
ናޗݔྷ
AD9910
Rev. A | Page 23 of 64
ࠀీၘ!
DDSాࢃ
থຕጴೕ୲ࢇׯഗ(DDS)ఇׂิ֖႑ࡽ)ኟ၀ᇆ၀
ൽᇀስDDSኟ၀࿋CFR1[16]*ă ֖႑ࡽڦ֖ຕ
)ೕ୲Ă၎࿋ࢅናޗ*ᆯDDSೕ୲Ă၎࿋ೋᅎࢅናޗ
႑ࡽۨLjස27๖ă
DDS႑ࡽڦ၎ܔ၎࿋ཚࡗ16࿋ڦ၎࿋ೋᅎጴ(POW)ઠ
ă၎࿋ೋᅎሞDDSాࢃঙ܈ናޗገ࣑ఇኮമׂิă၎
ܔ၎࿋ೋᅎ(Δθ)ᆯᅜူࠅ๕໙ǖ
ഄዐǖฉև၎࿋ೋᅎኵڦڇ࿋ࢷ܈Ljူևڇ࿋܈ຕă
ܔᇀඪᅪߴۨڦΔθLj૧ᆩฉຎࠅ๕൱POWLjም
ࡕ຺ป)ݛ݆ᇑ໙ඪᅪFTWૌຼ*ă
DDS႑ࡽڦ၎ܔናޗݔྷ)၎ܔᇀଉײ*ᆯ14࿋ናޗԲ
૩ᅺጱ(ASF)ႜຕጴࣅăናޗݔྷኵሞDDSాࢃঙ܈
ናޗገ࣑ఇׂ้ิăናޗݔྷڦ໙ࠅ๕ྺǖ
ഄዐǖฉևናޗኵᅜଉײݴຕ๖LjူևኵᅜdB๖
ଉײڦԲዘăܔᇀߴۨԲ૩ᅺጱLj૧ᆩࠅ๕3൱
ASFLjࡕ຺ป)ݛ݆ᇑ໙ඪᅪFTWૌຼ*ă
AD9910ՊײۙඪᅪDDS႑ࡽ֖ຕ้Ljፌٷ֑ۙᄣ
୲ྺ¼ fSYSCLKăᄺ৽ຫۙ႑ࡽׂิڦၟኻᆶ¼ fSYSCLK
ڦԠೕă๑ᆩԨഗፕྺۙഗ้ՂႷ୯ኄၵၟׂิ
ڦᆖၚă
14࿋DAC
AD9910ాዃᅃ߲14࿋ۉୁDACă૧ᆩଇୟԍኤ
ۉୁ႑ࡽڦೝ࢚ăೝ࢚ీࠕইگDAC้യሞڦ
ࠌఇሯำLj༵ࠃ߸ڦ႑ሯԲăሞDAC_RSETࢅAGND
ᆅগኮথᅃ߲ྔևۉፆ(RSET)૬֖ۉୁăDAC
ଉײۉୁ(IOUT)ྺ֖ۉୁڦᅃևݴ)֖“ޤዺDAC”
ևݴ*ăླྀ๑ᆩ10 kΩྔևۉፆഗ(RSET)ă
ᆌጀᅪሜ܋থۉፆڦٷၭLjԍኤۉუتᇀຩٗۉუ
ࡀۨڦݔྷాǗۉუג၌ඹᅟׂิࡗܠ฿ኈLjሰׯDAC
ۉୟ࣋ă
AD9910ڦೕ୲(fOUT)ᆯDDSೕ୲ڦೕ୲ۙၿ
ጴ(FTW)ăfOUTĂFTWࢅfSYSCLKኮڦ࠲ဣᆯᅜူࠅ
๕๖ǖ
ഄዐǖFTWᇀ02,147,483,647 (231 − 1)ኮڦ32࿋ኝ
ຕLj๖ྜኝ32࿋ՎଉڦگӷևăُݔྷԈઔٗdcలઊ
ຯ༬ೕ୲(½ fSYSCLK)ాڦᆶೕ୲ă
ܔᇀߴۨၙᄲڦfOUTኵLjཚࡗࠅ๕1൱FTWLjසࠅ๕2
๖ǖ
ഄዐǖࡧຕround(x)ጲՎଉ)xڦኵ*຺ปྺፌথৎڦ
ኝຕăኄᅺྺFTWՂႷྺᅃ߲ኝຕኵă૩සLjසࡕfOUT
= 41 MHzLjfSYSCLK = 122.88 MHzLjఫFTW = 1,433,053,867
(0x556AAAAB)ă
සࡕFTWٷᇀ231LjՊײࢫࣷሞೕ୲ዐׂิ۠
ၟLjǖ
27. DDSࠀీ
06479-010
DDS_CLK
32 19
FREQUENCY
CONTROL
ANGLE-TO-
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
PHASE
OFFSET
CONTROL
TO DAC
(MSBs)
DQ
R
ACCUMULATOR
RESET
32
16
MSB ALIGNED
AMPLITUDE
CONTROL
14
DDS SIGNAL CONTROL PARAMETERS
16
1419
32
32 14
14
32-BIT
ACCUMULATOR
OUT
f=
SYSCLK
f
FTW
232 ¸
¹
·
¨
©
§
=
FTW
¸
¸
¹
·
¨
¨
©
§
¸
¸
¹
·
¨
¨
©
§
SYSCLK
OUT
f
f
32
2
OUT
f= (for FTW ≥ 231)
SYSCLK
f
FTW
2
1
32
¸
¹
·
¨
©
§−
=
Δθ
¸
¹
·
¨
©
§
¸
¹
·
¨
©
§
16
16
2
360
2
2
POW
POW
π
=
ScaleAmplitude
¸
¹
·
¨
©
§
14
14
2
20log
2
ASF
ASF
(1)
(2)
(3)
AD9910
Rev. 0 | Page 24 of 64
ޤዺDAC
ዷDACଉײۉୁ(IOUT)ᆯ8࿋ޤዺDACăԍ٪ሞ
၎ᆌ٪ഗዐڦ8࿋ஓጴࣷߵᅜူࠅ๕໙IOUTǖ
ഄዐǖRSET ۉፆഗRSETڦፆኵ)ڇ࿋ǖΩ*ǗCODEၠޤዺ
DAC݀ໃڦ8࿋ຕኵ)ఐණኵ127*ă૩සǖRSET = 10,000ΩLj
CODE = 127LjሶIOUT = 20.07 mAă
ݒSinc୳հഗ
ԥ֑ᄣڦሜհຕୁAD9910ాዃຕఇገ࣑ഗ(DAC)ڦ
႑ࡽăᆯᇀDAC႑ࡽࠦᆶڦଭԍၳᆌLjDACڦ
ೕࣷԥsin(x)/x)Sinc*Ԉஏኝႚăᆯᇀഄհႚ்
କLjᅜᅜܔSincԈஏႜցăُԈஏ࣬ްࠀీ
ᆯDACఇമڦݒSinc୳հഗํ၄ăݒSinc୳հഗڦፕᆩ
၎ړᇀຕጴFIR୳հഗăഄၚᆌ༬ႠݥথৎݒSincԈஏă
ݒSinc୳հഗڦၚᆌ֖28)ᇑSincԈஏܔԲ*ă
ݒၠSinc୳հഗᆯCFR1[22]๑ీă୳հഗ؏ཀྵဣຕ6ă
୳հഗཚࡗ߀ՎDACڦຕLjඓԍܔSincԈஏႜց
LjᅜՆ௨ೕ฿ኈă
ݒSinc୳հഗ๑ీࢫLjׂࣷิ~3.0 dB֭ࡼăܔᇀփג
ࡗ40% DAC֑ᄣ୲ڦೕ୲LjݒSincհցᆶၳă
ሞ28ዐLjSincԈஏׂิକᅃ߲ᇑೕ୲ᆶ࠲ڦປLjሞల
ઊຯ༬ೕ୲ۅ(DAC֑ᄣ୲ڦ1/2)ฉፌٷٳ4 dBăසࡕ
ுᆶݒSinc୳հഗLjDACࣷڟSincԈஏೕ୲ປᆖ
ၚăݒSinc୳հഗᅜᆶၳປሞ±0.05 dBݔྷాă
29ྺ֑ᆩݒSinc୳հഗࢫڦႪኟSincၚᆌă
ဣཥă5ߴକዖDDS႑ࡽ֖ຕڦᆫံ
ă5ዐڦႜ๖గዖDDS႑ࡽ֖ຕڦຕᇸLjӀ
ইႾಇଚᆫံă૩සLjසࡕRAMࢅժႜຕ܋ཞ้๑
ీLjଇዖఇ๕Պײׂิೕ୲֖ຕLjఫDDSೕ୲֖
ຕᆌᆯRAMൻۯLjܸփժႜຕ܋ă
้ዓ(REF_CLK/REF_CLK )
REF_CLK/ REF_CLK߁ຎ
ཚࡗREF_CLK/REF_CLKᆅগLjAD9910༵ࠃܠዖׂิ
ాևSYSCLK႑ࡽ)DAC֑ᄣ้ዓ*ڦݛ݆ă REF_CLK
ᅜথᆯֶݴڇ܋႑ࡽᇸൻۯLjኁᆯথଇ߲
ᆅগڦৗናൻۯăଷྔLjాև၎࣍(PLL)ױ݆ഗᅜڇ
܀๑ీăREF_CLKࠀీ30ă߳ዖದዃᆯ
XTAL_SELᆅগࢅCFR3٪ഗڦ࿋ă30࣏၂๖
କCFR3࿋ᇑ༹ࠀీఇኮڦ࠲ဣă
¸
¹
·
¨
©
§+= 96
CODE
1
R
86.4
SET
out
I
6. ݒSinc୳հഗ؏ཀྵဣຕ
؏ཀྵࡽ ؏ཀྵኵ
1, 7 −35
2, 6 +134
3, 5 −562
9276+ 4
1
0
–1
–2
–3
–4 4.02.01.005.03.0
06479-011
(dB)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
INVERSE
SINC
SINC
28. SincࢅݒSincၚᆌ
29.ټݒSincցڦDACၚᆌ
–2.8
–2.9
–3.0
–3.1 4.02.01.005.03.0
06479-012
(dB)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
COMPENSATED RESPONSE
AD9910
Rev. A | Page 25 of 64
থൻۯ
REF_CLK/REF_CLK
ཚࡗ႑ࡽᇸথൻۯREF_CLK/REF_CLK้Ljᅜ֑
ᆩڇ܋႑ࡽኁֶݴ႑ࡽăܔᇀֶݴ႑ࡽᇸLj
REF_CLK/REF_CLK ᆅগᆯࢻց႑ࡽൻۯLjཞ้ཚࡗ0.1 μF
ۉඹୁ᳘ࢇăܔᇀڇ܋႑ࡽᇸLjᅜ֑ᆩڇ܋ֶݴገ
࣑Ljᄺᅜᆯڇ܋႑ࡽথൻۯREF_CLKăஃన
ᅃዖ൧Ljۼᄲᆩ0.1 μFۉඹᇑଇ߲REF_CLK/REF_CLK ᆅ
গႜୁ᳘ࢇLjᅜ௨߅ඡాև~1.35 Vڦୁೋዃۉუă
ၘ൧൩֖32ă
REF_CLK/REF_CLK ڦۉፆྺ~2.5 kΩ)ֶݴ*~1.2 kΩ)ڇ
܋*ăٷܠຕ႑ࡽᇸፆ၎ܔডၭăREF_CLK/REF_CLK
ۉፆ၎ܔডߛLjᅺُLjܔ܋থፆڦᆖၚᅜࢮ
ǗᅜLj܋থۉፆཚᅜӀቷ႑ࡽᇸڦፆઠ
ስă32ዐڦူ௬ଇ߲૩ጱۨ႑ࡽᇸፆྺ50 Ωă
PLL๑ీ࿋ᆩᇀስPLLୟ০থୟ০ăስথ
ୟ০้LjREF_CLK/REF_CLK ᆅগՂႷᆯྔև႑ࡽᇸ
ൻۯ)ڇ܋ֶݴ*ăፌٷೕ୲ٳ2 GHzăܔᇀٷᇀ1 GHz
ڦೕ୲LjՂႷഔᆩݴೕഗLj֍ీԍኤഗኟ߾ፕă
PLL๑ీࢫLjREFCLK_OUTᆅগᆶ࣐؋้ዓ႑ࡽă
้ዓ႑ࡽᇑREF_CLK႑ࡽೕ୲၎ཞăኄᅃۅሞ๑ᆩৗ
ና้༬՚ᆶᆩLjᅜྺᆩࢽްৗና้ዓ႑ࡽLjൻۯഄ
ྔևഗăREFCLK_OUTᆶՊײൻۯీ૰ăీ૰
ᆯଇ߲࿋Lj֖7ă
ৗ༹ൻۯREF_CLK/REF_CLK
๑ᆩৗ༹ፕྺREF_CLK/REF_CLK้Ljၿናೕ୲ٷሀ
ྺ25 MHză31ߴକླྀڦۉୟದዃăాևናږഗኻኧ
ఇৗ༹ăৗ༹߾ፕᆯXTAL_SELᆅগஇ1)Ⴔᄲ1.8Vஇ
ۉೝ*ă
30. REF_CLKࠀీ
REF_CLK
REF_CLK
PLL
VCO
SELECT
DIVIDE
CHARGE
PUMP
OUTIN
PLL_LOOP_FILTERENABLE
PLL_LOOP_FILTER
DRV0
CFR3
[29:28]
REFCLK_OUT
XTAL_SEL
REFCLK
INPUT
SELECT
LOGIC
SYSCLK
I
CP
CFR3
[21:19]
N
CFR3
[7:1]
VCO SEL
CFR3
[26:24]
÷2
REFCLK
INPUT DIVIDER BYPASS
CFR3[15]
PLL ENABLE
CFR3
[8]
REFCLK
INPUT DIVIDER
RESETB
CFR3[14]
94
95 2
90
91
0
1
0
1
2
2
7 3
0
1
06479-013
7. REFCLK_OUT࣐؋
DRV0࿋(CFR3[29:28])
্ᆩ)ෙༀ* 00
01 گۉୁ
ዐۉୁ 01
11 ߛۉୁ
REFCLK _ OUT࣐؋
06479-014
REF_CLK
REF_CLK
39pF39pF
XTAL
90
91
31. ৗ༹থ
32. থথ
06479-015
TERMINATION
REF_CLK
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
90
91
0.1μF
0.1μF
PECL,
LVPECL,
OR
LVDS
DRIVER
REF_CLK
90
91
50
0.1μF
0.1μF
BALUN
(1:1)
REF_CLK
REF_CLK
REF_CLK
REF_CLK
90
91
0.1μF
0.1μF
50
AD9910
Rev. 0 | Page 26 of 64
၎࣍(PLL)Ԡೕഗ
ాև၎࣍(PLL)ᅜ๑ᆩᇺᇺၭᇀဣཥ้ዓೕ୲ڦ้֖
ዓೕ୲ăPLLኧڦݥڦՊײԠೕဣຕ)12×
127×*ĂՊײۉࢁԭۉୁᅜྔև࣍ୟ୳հഗᇮ)ཚࡗ
PLL_LOOP_FILTERᆅগথ*ăኄၵࠀీ༵ߛକPLLڦଳ
ႠLjᅜᆫࣅ၎࿋ሯำႠీLjሺഽೕ୲ࡀࣄڦଳႠă
PLL࣏༵ࠃᅃ߲PLL_LOCKᆅগă
ཚࡗాևVCOLjPLLೕ୲ݔྷ(fSYSCLK)၌ۨሞ420 MHz
1 GHzኮăଷྔLjᆩࢽՂႷܔVCOႜՊײLjሞୃ߲
߾ፕೕ୲ݔྷዐስᅃ߲LjඟfSYSCLKሞݔྷă33ࢅ
34ଚକVCOڦݔྷă
33ߴᆶ၄ᆶഗሞඇ࿒܈ࢅۉᇸۉუݔྷాሎႹڦ
VCOೕ୲ฉူ၌ኵăᄺ৽ຫLjٗ၄ᆶഗዐໜൽڦ
ܠ߲ഗሞ߳ዖփཞཉူሏႜႴᄲ๑ᆩփཞڦኵܔCFR3
[26:24]ՊײLjᅜٳڟሞ၎ཞೕ୲ሏႜڦణڦă૩සLjໜ
ൽڦഗAሞ−10°C࣍ৣ࿒܈ူሏႜLjဣཥ้ዓೕ୲ྺ
900 MHzLjሶႴᄲCFR3[26:24]ยྺ100bǗໜൽڦഗ
Bሞ90°C࣍ৣ࿒܈ူሏႜLjဣཥ้ዓೕ୲ྺ900 MHzLjሶ
ႴᄲCFR3[26:24]ยྺ101băසࡕܔᇀڦೕ୲ࡀࣄLj
ဣཥ้ዓೕ୲߾ፕሞᅃፇೕ୲ݔྷా)ස33๖*Ljሶփ
ཞഗኮยۨڦCFR3[26:24]ኵ၎ཞă
34ߴڇ߲၄ᆶഗሞඇ࿒܈ࢅۉᇸۉუݔྷాሎႹڦ
VCOೕ୲ฉူ၌ኵă34၂๖ሞ߳ዖཉူLjڇ߲ഗ
ڦVCOೕ୲ݔྷࣷ๔ዕዘ۠ă
සࡕᆩࢽၙCFR3[26:24]ยྺڇᅃఐණኵLjስڦೕ୲
ᆌሞ33ዐڦగ߲ೕ୲ݔྷăଷྔLjܔᇀඪᅪߴۨڦ
ڇ߲ഗLjVCOݔྷዘ۠Lj๖ഗሞᆶ߾ፕཉူ
ڦඇևVCOೕ୲ݔྷాۼփࣷ၄ೕ୲ဤă
PLLۉࢁԭ
ۉࢁԭۉୁ(ICP)ᅜՊײLjྺᆩࢽᆫࣅPLLႠీ༵ࠃ
କ߸ٷڦଳႠă9ଚକ࿋ยዃࢅՔۉࢁԭۉୁኮ
ڦ࠲ဣă
34. ۆ႙ڦVCOݔྷ
06479-059
VCO0
VCO1
V
CO2
VCO3
V
CO4
VCO5
395 495 595 695 795 895 995
f
LOW
= 400
f
HIGH
= 460
f
LOW
= 455
f
HIGH
= 530
f
LOW
= 530
f
HIGH
= 615
f
LOW
= 760
f
HIGH
= 875
f
LOW
= 920
f
HIGH
= 1030
f
LOW
= 650
f
HIGH
= 790
(MHz)
33. VCOݔྷLjԈઔۆ႙ڦৗᇶ߾ᅝೋၽ
335 435 535 635 735 835 935 1035 1135
VCO0
VCO1
V
CO2
VCO3
VCO4
VCO5
06479-060
f
LOW
= 370
f
HIGH
= 510
f
LOW
= 420
f
HIGH
= 590
f
LOW
= 500
f
HIGH
= 700
f
LOW
= 700
f
HIGH
= 950
f
LOW
= 820
f
HIGH
=1150
f
LOW
= 600
f
HIGH
= 880
(MHz)
8. VCOೕ୲ݔྷ࿋ยዃ
VCOስ࿋(CFR3[26:24]) VCOݔྷ
0OCV 000
1OCV 100
2OCV 010
3OCV 110
4OCV 001
5OCV 101
LLP 011 ԥಖୟ
LLP 111 ԥಖୟ
9. PLLۉࢁԭۉୁ
ICPยዃ࿋(CFR3[21:19])ۉࢁԭۉୁLjICP (μA)
000 212
001 237
010 262
011 287
100 312
101 337
110 363
111 387
AD9910
Rev. A | Page 27 of 64
ྔևPLL࣍ୟ୳հഗᇮ
PLL_LOOP_FILTERᆅগ༵ࠃକྔև࣍ୟ୳հഗᇮথ
থăཚࡗ๑ᆩۨ࣍ୟ୳հഗᇮLjᆩࢽᅜ߸ଳ
ںᆫࣅPLLႠీă35ߴକPLLࢅྔև࣍ୟ୳հഗᇮ
থႚ๕ă
PLLۨኸ๖
๑ᆩPLL้LjPLL_LOCKᆅগᅜᆶၳߛۉೝ๖PLLᅙۨ
REFCLK႑ࡽăጀᅪPLL_LOCKᆅগྺ٪ăPLL
ԥಖୟࢫLjᆅগࣷԍஇ1ăยዃPFDް࿋࿋Ljᅜ
PLL_LOCKᆅগൣଭăኟ֡ፕ้LjPFDް࿋࿋ՂႷൣ0ă
ᅎ࿋(OSK)
OSKࠀీ(֖36)ሎႹᆩࢽDDS႑ࡽڦናޗă
ࠀీ༵ࠃۯࢅጲۯଇዖݛ๕ăᇑඪࢆഄၠDDS
݀ໃՊײናޗຕڦఇ၎ԲLjOSKఇׂิڦናޗຕ
ᆫံፌߛăᅺُLjOSKຕᇸ๑ీࢫLjഄᆫံᇀ
ᆶഄናޗຕᇸă
OSKࠀీᆯଇ߲CFR1٪ഗ࿋)OSK๑ీ࿋ࢅስጲۯOSK
࿋*ĂྔևOSKᆅগࢅASF٪ഗඇև32࿋ጴ࠶ăዷᄲ
OSKఇڦOSK๑ీ࿋ăOSKࠀీ্ᆩࢫLjOSK
ࣷԥࢮLjాև้ዓ࠲Կă
OSKࠀీ๑ీࢫLjཚࡗስጲۯOSK࿋ᅜስጲۯ
ۯ֡ፕఇ๕ăஇ0๖ۯఇ๕)ఐණ*ă
ۯOSK
ሞۯఇ๕ዐLjཚࡗሞASF٪ഗናޗԲ૩ᅺጱևݴჄ
ႀ֡ፕLj๑ናޗ݀ิ߀Վă႑ࡽናޗՎࣅ୲
زႜI/O܋܈၌ăሞۯఇ๕ዐLjOSKᆅগࠀీൽ
ᇀۯOSKྔև࿋ڦጒༀăړOSKᆅগྺஇ0้Lj
ናޗഽྺ0ǗޏሶLjናޗࣷᆯናޗԲ૩ᅺጱ
ۨă
ሞዷୁຍጨଙዐLjኄዖದዃᅜڥᅃ߲ෙII႙PLLă
ᄲ໙୳հഗᇮ֖ຕኵLjံᄲኪڢݒઍݴೕဣຕ
(N)Ă၎ഗሺᅮ(KD)ᅜVCOሺᅮ(KV)(KVᅜߵVCO
ስ࿋ยዃሞ1ዐֱቴ)ă࣍ୟ୳հഗᇮኵൽᇀణՔ
࣍ټ(fOL)ࢅ၎࿋ᇆଉ(φ)Lj໙ࠅ๕සူǖ
R1= (4)
C1= (5)
C2= (6)
ഄዐǖ
KDڪᇀICPՊײኵă
KVཚࡗ1ֱቴă
ඓԍࠅ๕46ڦՎଉ๑ᆩടړڦڇ࿋ǖICPڇ࿋ՂႷҾ
ಢLjփీ9ዐ၄ڦྲҾDŽuADžǗKV ՂႷྺࢍጦ/ޚ
(Hz/V)Ljփీ1ዐڦቹࢍ/ޚ(MHz/V)Ǘ࣍ୟټ
(fOL)ڇ࿋ՂႷࢍጦ(Hz)Ǘ၎࿋ᇆଉڇ࿋ՂႷྺࢷ܈(φ)ă
૩සLjۨPLLՊײยዃǖICP = 287 μALjKV = 625 MHz/VLj
N = 25Ǘසࡕၙᄲڦ࣍ୟټࢅ၎࿋ᇆଉݴ՚50 kHzࢅ
45°Ljఫ࣍ୟ୳հഗᇮኵݴ՚ǖR1 = 52.85 ΩLjC1 =
145.4 nFLjC2 = 30.11 nFă
35. REFCLK PLLྔև࣍ୟ୳հഗ
47/!PTLࠀీ
PFD CP
PLL_LOOP_FILTER
VCO
÷N
PLL OUT
PLL IN
AVDD
REFCLK PLL
2
R1
C1
C2
06479-016
¸
¸
¹
·
¨
¨
©
§+)sin(
1
1
ϕ
VD
OL
KK
πNf
2
2)(
)tan(
OL
VD
πfN
KK
ϕ
¸
¸
¹
·
¨
¨
©
§−
)cos(
)sin(
)(
ϕ
ϕ
1
2
2
OL
VD
πfN
KK
06479-017
OSK ENABLE
AMPLITUDE SCALE FACTOR
(ASF[15:2])
AMPLITUDE RAMP RATE
(ASF[31:16])
AMPLITUDE STEP SIZE
(ASF[1:0])
MANUAL OSK EXTERNAL
AUTO OSK ENABLE
OSK
DDS CLOCK
TO DDS
AMPLITUDE
CONTROL
PARAMETER
60
LOAD ARR AT I/O_UPDATE
OSK
CONTROLLER
14
16
14
2
AD9910
Rev. 0 | Page 28 of 64
ጲۯOSK
ሞጲۯఇ๕ዐLjOSKࠀీࣷጲۯิׯߵ้װ၍ႠՎࣅ
ڦናޗ൸၍)ᄺྺናޗၽೢ*ăናޗၽೢᆯෙ߲֖ຕ
ǖፌٷናޗԲ૩ᅺጱĂናޗօᅜօ้߰ăና
ޗၽೢ֖ຕԍ٪ሞ32࿋ASF٪ഗዐLjཚࡗزႜI/O܋Պ
ײăօ้߰ᆯASF٪ഗዐ16࿋ናޗၽೢ୲և
ݴ)[31:16]࿋*ยዃăፌٷናޗԲ૩ᅺጱᆯASF٪ഗዐ14࿋
ናޗԲ૩ᅺጱևݴ)[15:2]࿋*ยዃăናޗօᆯASF٪ഗ
ዐ2࿋ናޗօևݴ)[1:0]࿋*ยዃăଷྔLjၽೢݛၠ)ኟ/
ၽ୲*ᆯྔևOSKᆅগă
օ߰ሶᆯᅜ¼ fSYSCLKሏႜڦ16࿋Պײ้ۨഗă
૧ᆩ้ۨഗዜยዃናޗօ้߰(Δt)Ljഄ໙ࠅ๕
ྺǖ
Δt =
ഄዐǖMԍ٪ሞASF٪ഗናޗၽೢ୲(ARR)ևݴڦ16࿋
ຕጴă૩සLjසࡕfSYSCLK = 750 MHzLjM = 23218 (0x5AB2)Lj
ఫΔt ≈ 123.8293 μsă
OSK૧ᆩ14࿋ޙࡽຕጺ၍DDSናޗ֖ຕ)ཉ
OSK๑ీ࿋ᅙዃ1*ăOSKᆅগዃ1ࢫLjOSKኵٗଭ(0)
๔LjᅜՊײڦናޗօڿሺLjٳڟՊײยۨڦፌٷ
ናޗኵăOSKᆅগൣ0ࢫLjOSKᆯړമኵ๔LjᅜՊײ
ናޗօڿLjڟٳଭ(0)ຐă
සࡕሞڟٳፌٷኵമOSKᆅগൎ࣑ྺஇ0LjሶOSK
ᅜփᆩሺፌٷናޗኵăཞᄣLjසࡕሞڟٳ0ኵമ
OSKᆅগൎ࣑ྺஇ1LjOSKኵᄺփᅃۨইڟଭ(0)ă
ᅃڋOSK๑ీ࿋ስጲۯOSK࿋ൣ0ࢫLjฉۉް࿋ڦ
OSK؛๔ኵۼྺଭ(0)ă
OSKናޗօᆯASF٪ഗዐڦናޗօ࿋ยዃLj֖
10ăօኸ14࿋OSKኵڦLSBዘăஃՊײօ
සࢆLjOSKۼփࣷגࡗASF٪ഗዐՊײยۨڦፌ
ٷናޗኵă
ኟසമ࿔ຎLjօ้߰ᆯ16࿋Պײ้ۨഗă
ཚLj้ۨഗג้ࢫۼࣷሜՊײยۨڦ้ኵLj๔ႎ
ڦ้ዜăփࡗLjሞ้ۨഗג้മᆶෙዖ൧ࣷᆅഐย
้ۨኵዘሜăڼᅃዖ൧ስጲۯOSK࿋ᆯ0ڟ1Վ
ࣅLjໜࢫ၄I/O߸ႎăڼܾዖ൧OSKᆅগጒༀ݀ิ߀
Վăڼෙዖ൧ൽᇀሜARR @ I/O ߸ႎ࿋ڦጒༀăසࡕ
࿋ԥൣ0Ljሶփࣷ݀ิ้ۨഗዘሜǗޏሶLjI/O_UPDATE
ᆅগዃ1)prole݀ิՎࣅ*้Lj้ۨഗࣷዘዃྺ؛๔้
ۅă
ຕጴၽೢ݀ิഗ(DRG)
DRG߁ຎ
AD9910ዐׯକඇຕጴ๕ຕጴၽೢ݀ิഗLjᅜٗՊײย
ۨڦഐۅڟዕۅ௮၎࿋Ăೕ୲ࢅናޗăDRGᄲᆩڟ9߲
٪ഗ࿋Lj3߲ྔևᆅগĂ2߲64࿋٪ഗࢅᅃ߲32࿋
٪ഗ)֖37*ă
37. ຕጴၽೢࠀీ
21/!PTLናޗօ
SYSCLK
f
4M
ናޗօ࿋(ASF[1:0])ናޗօ
1 00
2 10
4 01
8 11
DIGITAL RAMP LIMIT REGISTER
DRCTL
DDS CLOCK
DRHOLD
DROVER
DIGITAL RAMP RATE REGISTER
DIGITAL RAMP STEP REGISTER
06479-018
TO DDS
SIGNAL
CONTROL
PARAMETER
DIGITAL RAMP ENABLE
DROVER PIN ACTIVE
LOAD LRR AT I/O_UPDATE
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
64
64
DIGITAL RAMP DESTINATION
2
DIGITAL RAMP NO-DWELL
2
32
32
DIGITAL
RAMP
GENERATOR
62 61 63
DDS CLOCK
DQ
R
LOWER
LIMIT
0
1
DECREMENT STEP SIZE
PRESET
Q
DRCTL
LOAD
CLEAR DIGITAL RAMP ACCUMULATO
R
AUTOCLEAR DIGITAL RAMP ACC
.
NO DWELL
LIMIT CONTROL
DIGITAL RAMP ACCUMULATO
R
INCREMENT STEP SIZE
32
32
0
1
NEGATIVE SLOPE RATE
POSITIVE SLOPE RATE
16
16
32
16
62
DRHOLD 63
32
32
LOAD
CONTROL
LOGIC
LOAD LRR AT I/O_UPDATE
DIGITAL
RAMP
TIMER
ACCUMULATOR
RESET
CONTROL
LOGIC
NO-DWELL
CONTROL
2
3232
TO DDS
SIGNAL
CONTROL
PARAMETER
UPPER
LIMIT
32
06479-019
AD9910
Rev. A | Page 29 of 64
DRGڦዷᄲຕጴၽೢ๑ీ࿋ă্ᆩ࿋ࢫLjDRGഄ
ڦࣷԥࢮLjాև้ዓ࠲Կᅜবీă
DRG֑ᆩ32࿋ޙࡽຕጺ၍LjᅜᇑDDSෙዖ႑ࡽ
֖ຕዐڦඪᅪᅃዖথăDRGᆯࠀీ٪ഗ2ዐ
ڦଇ߲ຕጴၽೢణڦ࿋Lj֖11ăߵణڦ࿋ۨ
ᅭLj32࿋ጺ၍ᅜᇑ32࿋ೕ୲֖ຕĂ16࿋၎࿋֖ຕᅜ
14࿋ናޗ֖ຕཚࡗMSBܔഋăසࡕణڦ࿋၎࿋ና
ޗLj࿄๑ᆩڦLSBࣷԥࢮă
DRGڦၽೢ༬Ⴀ֖ຕྜඇՊײăԈઔǖၽೢฉူ၌ኵĂ
ኟ/ၽ୲ၽೢڦօࢅօ୲ڇ܀ăDRGၘဦස
38๖ă
ၽೢݛၠᆯDRCTLᆅগăُᆅগฉஇ0๑DRGิ
ׯၽ୲ၽೢLjஇ1ׂิኟၽ୲ၽೢă
ଷྔLjDRG࣏ኧᆯDRHOLDᆅগڦԍࠀీăړُ
ᆅগยྺஇ1้LjDRGཕାሞፌࢫڦጒༀዐǗޏሶLj
DRGࣷኟ߾ፕă
ݥDRGణڦ࿋ۨᅭڦDDS႑ࡽ֖ຕൽጲᆶၳproleă
ຕጴၽೢణڦ࿋
(CFR2[21:20])
DDS႑ࡽ
֖ຕ
DDS֖ຕ
ኸۨ࿋
00 ೕ୲
01 ၎࿋ 31:16
1x1 ናޗ 31:18
1 x = ࠲ă
38. ຕጴၽೢ݀ิഗၘ
10. OSKናޗօ
31:0
AD9910
Rev. 0 | Page 30 of 64
DRGၽ୲
DRGڦాࢃᅜՊײ้ۨഗྺ้ዓڦ32࿋ેഗăܸۨ
้ഗڦ้֖DDS้ዓLj߾ፕሞ¼ fSYSCLKೕ୲ă้ۨ
ഗᆩᇀ૬ેഗଇ߲Ⴤ߸ႎኮڦ้߰ăኟၽ୲
օ߰(+Δt)ࢅၽ୲օ߰(−Δt)ۼీ܀૬Պײ
Lj໙ࠅ๕ྺǖ
+Δt=
−Δt=
ഄዐǖPࢅNԍ٪ሞ32࿋ຕጴၽೢ୲٪ഗዐڦଇ߲16࿋
ຕኵLjᆩᇀօ߰ăNኸၽ୲ၽೢڦօ߰ă
Pኸኟၽ୲ၽೢօ߰ă
ኟၽ୲ၽೢօ(STEPP)ࢅၽ୲ၽೢօ(STEPN)֑ᆩ32
࿋ຕኵLjᆯ64࿋ຕጴၽೢօ٪ഗՊײăᅃօ
ڦՊײኵޙࡽኝຕ)ᆘࣷጲۯSTEPNፕኵ*ă
32࿋օኵࢅೕ୲Ă၎࿋ᅜናޗڇ࿋ኮڦ࠲ဣൽᇀ
ຕጴၽೢణڦ࿋ăᆩSTEPN STEPP༺࣑ူଚࠅ๕ዐڦMLj
ᅜ໙ํೕ୲Ă၎࿋ࢅናޗօǖ
!!!!ೕ୲օ=
!!!!၎࿋օ= DŽࢷ܈Dž
!!!!၎࿋օ= DŽ܈ຕDž
!!!!ናޗօ =
ጀᅪೕ୲ڇ࿋ᇑfSYSCLK๑ᆩڦڇ࿋ԍᅃዂ)૩සǖMHz*ă
ናޗڇ࿋ᇑDACଉײۉୁIFS๑ᆩڦڇ࿋ԍᅃዂ
)૩සǖmA*ă
၎࿋ࢅናޗօࠅ๕໙ڦࡕೝօăօે
܈ٳ32࿋Lj၎࿋ࢅናޗݴ՚ኻᆩڟ16࿋ࢅ14࿋ăᅺ
ُLjํ၎࿋ࢅናޗօࣷߵణڦ࿋ેڦ32࿋
ኵপൽྺ16࿋ࢅ14࿋ࡕă
ߵമ࿔ຎLjօ߰ᆯ16࿋Պײ้ۨഗăᆶෙ
ዖ൧ࣷሰׯ้ۨഗג้മዘሜăڼᅃዖ൧ຕጴၽೢ
๑ీ࿋ᆯ0Վྺ1LjໜࢫႜI/O߸ႎăڼܾዖ൧
DRCTLᆅগጒༀ݀ิ߀Վăڼෙዖ൧ሜLRR @ I/O߸
ႎ࿋๑ీ)֖“٪ഗࢅ࿋ࠀీ௮ຎ”ևݴ*ă
DRG၌ኵ
ၽೢેഗࢫยᆶ၌ኵஇLjᅜഽยۨၽೢ݀ิ
ഗ႑ࡽڦฉူՉহăሞඪࢆ൧ူLjDRG๑ీࢫڦ
႑ࡽۼփࣷגࡗՊײยۨڦ၌ኵăฉူ၌ኵᆯ64࿋ຕጴ
ၽೢ၌ኵ٪ഗăጀᅪฉ၌ኵᄲٷᇀူ၌ኵLj֍ీԍ
ኤDRGኟሏႜă
DRGેഗൣଭ
ཚࡗՊײᅜ๑ၽೢેഗൣ0)ް࿋0*ăၽೢે
ഗൣ0ࢫLjࣷഽDRGӀຕጴၽೢ၌ኵ٪ഗዐՊײย
ۨڦူ၌ኵă
ཚࡗ၌ኵఇഴેഗݒઍୟ০ዐLjް࿋ેഗ
၎ړᇀഄᇨዃྺူ၌ኵă
ኟၽೢ݀ิ
ኟၽೢ݀ิኸଇ߲ݥጂା࿋ඇևൣ0)ၘ൧൩֖“ݥጂା
ၽೢ݀ิ”ևݴ*ăሞ39ዐLjߴକᅃ߲ၽೢհႚ૩ጱ
ഄႴ႑ࡽǖፌฉ௬ڦ၍ྺDRGǗူᅃཉ၍
DROVERᆅগጒༀ)ۨDROVERᆅগᆶၳ࿋ᅙዃ
1*Ǘഄڦ၍ྺ࿋ࢅᆅগǗଷྔLj၎࠲ၽೢ֖
ຕᄺᇎᅜକՔጀ)ฉူ၌ኵĂօࢅኟၽ୲ၽೢڦΔt*ă
ሞڦڹևLjټᇶංຕጴՔକ߳ዖ༹๚ăփཞຕጴ
Պࡽ๖ڦ๚)๚1Ljڪڪ*Ljሞူ௬ڦႜຫ
ă
ሞԨ૩ዐLjྺକ၂๖DRGڦଳႠLjၽೢڦኟၽ୲ܔ
փཞڦăኟଇዖၽ୲֖ຕᅜՊײྺ၎ཞኵă
SYSCLK
f
4p
SYSCLK
f
4N
SYSCLK
32
f
2¸
¹
·
¨
©
§M
31
2
M
π
29
2
45 M
FS
I
M¸
¹
·
¨
©
§
32
2
AD9910
Rev. A | Page 31 of 64
๚1—ຕጴၽೢ๑ీ࿋ዃ1Ljᆯᇀ࿋ՂႷሞᅃ߲I/O߸ႎ
ࢫ֍ᆶၳLjᅺُփࣷᆖၚDRGă
๚2—I/O߸ႎ๑ీ࿋ăසࡕُ้DRCTL = 1ᆶၳ
)DRCTL၍ࣨևݴ*LjఫDRGࣷ૬Վׯኟၽ୲
)DRG၍ࣨևݴ*ăޏሶLjසࡕDRCTL = 0LjDRG
ࣷԥ؛๔ࣅྺူ၌ኵă
๚3—DRCTLᆅগገ࣑ׯஇ1LjഔۯDRGኟၽ୲ă
ሞԨ૩ዐLjDRCTLᆅগጒༀԍ้ፁࠕLjᅜ๑DRGٳ
ڟഄՊײยۨڦฉ၌ኵăሞၽೢેഗൣଭLjDRCTL = 0Lj
ኁዘႎฉ၌ኵՊײยۨྺ߸ߛኵኮമLjDRG๔ዕԍฉ
၌ኵăܔᇀፌࢫᅃዖ൧LjDRGࣷ૬࣬ްኮമڦኟ
ၽ୲൸၍ă
๚4—DRCTLᆅগገ࣑ׯஇ0LjഔۯDRGၽ୲ă
ሞԨ૩ዐLjDRCTLᆅগጒༀԍ้ፁࠕLjᅜ๑DRGٳ
ڟഄՊײยۨڦူ၌ኵăሞDRCTL = 1ኁူ၌ኵዘႎՊײ
ڥ߸گኵኮമLjDRG๔ዕԍူ၌ኵăܔᇀࢫᅃዖ
൧LjDRGࣷ૬࣬ްኮമڦၽ୲൸၍ă
๚5—DRCTLᆅগڼْܾገ࣑ׯஇ1Ljഔۯڼْܾኟၽ
୲ă
๚6—DRHOLDᆅগገ࣑ྺஇ1Ljኟၽ୲൸၍ዐ
ăኄ๑ڥၽೢેഗཕኹሏ໙LjժDRG۳ሞፌ
ࢫڦኵฉă
๚7—DRHOLDᆅগገ࣑ྺஇ0LjݣၽೢેഗLj࣬
ްኮമڦኟၽ୲൸၍ă
๚8—ൣأຕጴၽೢેഗ࿋ዃ1Ljᆯᇀ࿋ՂႷሞI/O߸
ႎة݀ࢫ֍ᆶၳLjᅺُփࣷᆖၚDRGă
๚9—I/O߸ႎକൣأຕጴၽೢેഗ࿋ᅙዃ1Ljܔၽ
ೢેഗް࿋LjഽDRG၌ۨྺՊײยۨڦူ၌
ኵăሞൣأཉᅎأമLjDRG๔ዕԍူ၌ኵă
๚10—ൣأຕጴၽೢેഗ࿋ᅙൣ0Ljᆯᇀ࿋ՂႷሞ
I/O߸ႎة݀ࢫ֍ᆶၳLjᅺُփࣷᆖၚDRGă
๚11—I/O߸ႎକൣأຕጴၽೢેഗ࿋ᅙൣ0Lj
ݣၽೢેഗLjዘႎ࣬ްኮമڦኟၽ୲൸၍ă
๚12—ጲۯൣأຕጴၽೢેഗ࿋ᅙዃ1Ljᆯᇀ࿋ՂႷ
ሞI/O߸ႎة݀ࢫ֍ᆶၳLjᅺُփࣷᆖၚDRGă
๚13—I/O߸ႎକጲۯൣأຕጴၽೢેഗ࿋ᅙዃ
1LjዘዃၽೢેഗăጀᅪLj๑ᆩጲۯൣأLjၽೢેഗ
ኻሞᅃ߲DDS้ዓዜాԍዘዃጒༀăኄ๑DRGᅜူ
၌ኵLjڍၽೢેഗࣷ૬࣬ްኟሏႜăሞԨ૩
ዐLjDRCTLᆅগԍஇ1ǗᅺُLjDRGዘႎ࣬ްኮ
മڦኟၽ୲൸၍ă
39. ኟၽೢ݀ิ
DRG OUTPUT
LOWER LIMIT
UPPER LIMIT
DRCTL
DRHOLD
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
CLEAR DIGITAL
RAMP ACCUMULATOR
I/O_UPDATE
POSITIVE
STEP SIZE
NEGATIVE
STEP SIZE
P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE
DIGITAL RAMP ENABLE
DROVER
06479-020
CLEAR
RELEASE
AUTO
CLEAR
–
t
+
t
1 2 3 4 5 6 7 8 9
10
11
12
13
UPPER LIMIT
P DDS CLOCK CYCLES
1 2 3 4 5 6 7 8
DRG OUTPUT
LOWER LIMIT
DRCTL
POSITIVE
STEP SIZE
DROVER
+
t
06479-021
AD9910
Rev. 0 | Page 32 of 64
ݥጂାၽೢ݀ิ!
ࠀీ٪ഗ2ዐڦଇ߲ݥጂା࿋ሺٷକDRGڦᆌᆩଳ
Ⴀăሞኟၽೢ݀ิࡗײዐLjړDRGٳڟՊײยۨ
ڦฉ၌ኵူ၌ኵ้Ljසࡕ߾ፕ֖ຕփ݀ิՎࣅLjDRGࣷ
๔ዕԍ၌ኵăփࡗLjሞݥጂା֡ፕዐLjDRG
փᅃۨԍሞฉူ၌ኵă૩සLjยዃຕጴၽೢݥጂାߛ
࿋LjሶړDRGٳڟฉ၌ኵ้LjDRGࣷጲۯ)૬*ཌڟူ၌
ኵ)ኄᅃࡗײժݥᅜၽೢݛ๕ݓ࣮ူ၌ኵLjܸথཌူ
၌ኵ*ăૌຼںLjຕጴၽೢݥጂାگ࿋ዃ1ࢫLjړDRGٳڟ
ူ၌ኵ้LjDRGࣷጲۯ)૬*ཌڟฉ၌ኵă
ሞݥጂା֡ፕLjৈDRCTLᆅগڦጒༀՎࣅǗᄺ৽
ຫLjৢༀஇۉೝփׂࣷิᆖၚă
ሞݥጂାߛ࿋֡ፕLjDRCTLᆅগኟၠገ้࣑Ljࣷഔۯ
ኟၽ୲ၽೢLjሞٳڟฉ၌ኵኮമࣷ๔ዕᅜኟၽ୲ၽೢ
)փඪࢆDRCTLᆅগۯᆖၚ*ă
ሞݥጂାگ࿋֡ፕLjDRCTLᆅগၠገ้࣑Ljࣷഔۯ
ၽ୲ၽೢLjሞٳڟူ၌ኵኮമࣷ๔ዕᅜၽ୲ၽೢ
)փඪࢆDRCTLᆅগۯᆖၚ*ă
ยዃଇ߲ݥጂା࿋ࣷۙᆩჄၽೢሏႜఇ๕Ǘᄺ৽ຫLj
DRGཚࡗՊײၽ୲֖ຕጲۯሞଇ߲၌ኵኮናږăଷ
ྔLjDRCTLᆅগࠀీᄺᆶփཞăᆯᇱઠၽೢႾଚ؛
๔ࣅՎׯኻ߀ՎၽೢݛၠǗᄺ৽ຫLjړDRGتᇀኟ
ၽ୲ၽೢዐ้LjDRCTLᆅগٗஇ1Վׯஇ0Ljఫ
DRGࣷ૬ൎ࣑ׯၽ୲֖ຕLj࣬ްሞଇ߲၌ኵኮናږ
ăૌຼںLjසࡕDRGتᇀၽ୲ၽೢዐLj
DRCTLᆅগᆯஇ0Վྺஇ1LjఫDRGࣷ૬ൎ࣑ׯኟ
ၽ୲֖ຕLj࣬ްሞଇ߲၌ኵኮናږă
ړଇ߲ݥጂା࿋ཞ้ยዃ้LjْDRGٳڟՊײยۨ
ڦฉ၌ኵူ၌ኵࢫ)ۨDROVERᆅগᆶၳ࿋ᅙዃ1*Lj
DROVER႑ࡽׂࣷิᅃ߲ኟஞ؋)ଇ߲DDS้ዓዜ*ă
40ߴକݥጂାߛ࿋DRGհႚăհႚۨຕጴ
ၽೢݥጂାߛ࿋ᅙዃ1LjժᆯI/O߸ႎăଷྔLjዐ࣏
ߴDROVERᆅগڦጒༀ)ۨᆶၳ࿋ᅙዃ1*ă
40ዐټᇶංຕጴ๖փཞ๚Lj༹ࡤᅭසူǖ
๚1—๖I/O߸ႎକᅙยዃڦຕጴၽೢ๑ీ࿋ă
๚2—DRCTLᆅগገ࣑ׯஇ1LjഔۯDRGኟၽ୲ă
๚3—DRCTLᆅগገ࣑ׯஇ0LjփࣷᆖၚDRGă
๚4—ᆯᇀຕጴၽೢݥጂାߛ࿋ᅙዃ1LjړDRGٳڟ
ฉ၌ኵ้Ljࣷ૬ൎ࣑ڟူ၌ኵLjሞDRCTLٗஇ0Վׯ
இ1ኮമLj๔ዕԍူ၌ኵă
๚5—DRCTLᆯஇ0ገ࣑ׯஇ1Ljዘႎኟၽ୲ၽ
ೢă
๚6ࢅ๚7—ሞDRGٳڟՊײฉ၌ኵኮമLjࢮ
DRCTLᆅগஇՎࣅă
๚8—ᆯᇀຕጴၽೢݥጂାߛ࿋ᅙዃ1LjړDRGٳڟ
ฉ၌ኵ้Ljࣷ૬ൎ࣑ڟူ၌ኵLjሞDRCTLٗஇ0Վׯ
இ1ኮമLj๔ዕԍူ၌ኵă
ຕጴၽೢݥጂାگ࿋ᇑຕጴၽೢݥጂାߛ࿋ยዃ൧၎
ຼLjփཞኮྔሞᇀDRCTLᆅগٗஇ1Վׯஇ0้LjDRG
ᅜၽ୲ၽೢLjժሞٳڟူ၌ኵ้Lj૬ൎ࣑ڟฉ၌
ኵă
DROVERᆅগ
DROVERᆅগ༵ࠃྔև႑ࡽ๖DRGጒༀă༹ઠLjړ
DRGتᇀฉ၌ኵ/ူ၌ኵ้LjDROVERᆅগྺஇ1Ǘ
أُኮྔLjۼྺஇ0ăܔᇀଇ߲ݥጂା࿋ۼยዃڦ༬
൧LjْDRGٳڟՊײยۨڦඪᅪ၌ኵ้Lj
DROVERᆅগׂิᅃ߲ኟஞ؋Ljஞ؋܈ྺଇ߲DDS้ዓ
ዜࣷă
40. ݥጂାߛ࿋ၽೢ݀ิ
RAM
ADDRESS
DATA
QSCLK
I/O_RESET
SDIO
CS
PROFILE
WAVEFORM END ADDRESS
WAVEFORM START ADDRESS
ADDRESS CLOCK
PROGRAMMING
REGISTERS
STATE
MACHINE
UP/DOWN
COUNTER
SERIAL
I/O
PORT
2
32
10
10
U/D
3
06479-022
AD9910
Rev. A | Page 33 of 64
RAM
RAM߁ຎ
AD9910֑ᆩᅃ߲1024 × 32࿋RAMăRAMᆶଇ߲Ԩ߾ፕ
ఇ๕ǖຕሜ/܁ൽఇ๕ࢅխݣఇ๕ăړRAMຕཚࡗ
زႜI/O܋ሜ܁ൽ้Ljຕሜ/܁ൽఇ๕ᆶၳăړ
RAMాඹ݀ໃగᅃ߲ాևຕణڦ֖ຕ้Ljխݣఇ๕
ᆶၳă
ߵ༹ڦխݣఇ๕LjᆩࢽᅜRAMፌܠݴׯ8߲܀૬
้ᇘհႚăኄၵհႚൻۯDDS႑ࡽ֖ຕLjኧೕ୲Ă
၎࿋ĂናޗႠۙ႑ࡽă
ሞࠀీ٪ഗ1ዐยዃRAM๑ీ࿋ᅜ๑ీRAM֡
ፕǗᄲ߀Վُ๑ీ࿋ڦጒༀႴᄲI/O߸ႎ)prole݀ิՎ
ࣅ*ă
հႚᆯ8߲RAM prole٪ഗิׯLj٪ഗཚࡗෙ߲
proleᆅগă߲proleԈࡤᅜူాඹǖ
t10࿋հႚഐ๔ںጴ
t 10࿋հႚຐںጴ
t 16࿋ںօ୲ጴ
t 3࿋RAMఇ๕ጴ
t ݥጂାߛ࿋
t ଭሁ࿋
ᆩࢽՂႷඓԍຐںٷᇀഐ๔ںă
߲proleۼࣷۨᅭߴۨհႚڦ֑ᄣۅຕࢅ֑ᄣ୲ă૧
ᆩాևጒༀLjRAMాඹࣷӀࡀۨڦ୲݀ໃ၎ᆌڦ
DDS႑ࡽ֖ຕăଷྔLjጒༀ࣏ీٗRAMዐൽᄣ
ڦຩႾ)ኟၠ/ݒၠ*Ljᅜ༵ߛ้ܔհႚڦ݀ิၳ୲ă
RAMሜ/܁ൽ֡ፕ!
ഽଜᅱኴႜRAMሜ/܁ൽ֡ፕ้LjRAM๑ీ࿋ยྺ
0ăሜ܁ൽRAMాඹႴᄲෙ߲օየǖ
1. ܔRAM Prole 0RAM Prole 7٪ഗڦഐ๔!
! ࢅຐںՊײLjۨᅭ߲܀૬հႚڦՉহă
2. ܔproleᆅগแࢇڦஇۉೝLjൽణՔRAM
proleă
3. ӀRAM prole٪ഗၠRAM(ں0x16)ዐႀ!
! )ٗዐ܁ൽ*ኸۨጴຕڦRAMጴ)ၘ“زႜՊ!
!ײ”ևݴ*ă41ࠀీ၂๖କRAMຕሜ/܁ൽ!
! ֡ፕ๑ᆩڦࠀీᇮă
ሞRAMሜ/܁ൽ֡ፕዐLjጒༀࣷሺ/ຕഗደօ
ٳڟణՔRAM࿋ዃăຕഗᇑزႜI/O܋ཞօLjᅜ๑32
࿋ጴڦزႜ/ժႜገ࣑ᇑ၎ᆌڦRAMں݀ิӀኟඓ
ڦ้ႾܔഋLjኴႜႴڦ܁/ႀ֡ፕă
RAM prole၎ࢻኮྜඇ܀૬Ljᅺُᅜዘ۠ۨᅭںݔ
ྷăኄᄣLjፌႎႀ֡ፕڦຕӝᅙঢ়ႀዘ۠ں࿋
ዃڦຕޮ߃ă
ᅜܠ߲հႚྺڇᅃհႚሜRAMLjᄺ৽ຫLjᆶ
հႚᅜߵ้ᇘথăݛ݆Ljܔగᅃ߲RAM proleՊ
ײLjยዃഄഐ๔ࢅຐںLj๑ഄԈࡤኝ߲থհႚăኮ
ࢫཚࡗزႜI/O܋ഐ๔ࢅຐںՊײڦRAM
proleڦᅃ߲থհႚႀRAMăഄᇆڦRAM proleՂႷ
๑ᆩኟඓڦഐ๔ࢅຐںܔ߲ڇᅃհႚՊײă
RAMխݣ֡ፕ(հႚ݀ิ)
ܔRAMሜణՔհႚຕࢫLjሞխݣࡗײዐิׯհ
ႚăRAMխݣ֡ፕႴᄲRAM๑ీ࿋ยྺ1ăᄲխݣRAM
ຕLj๑ᆩPROFILE[2:0]ᆅগൽႴڦհႚăprole
ཚࡗۨᅭհႚڦRAMںݔྷLjٗRAMዐൽ֑ᄣۅڦ
୲)խݣ୲*Ă֡ፕఇ๕ᅜޏ๑ᆩݥጂାࠀీLjઠ
ాևጒༀă42ࠀీ၂๖କRAMխݣ֡ፕ๑
ᆩڦࠀీᇮă
41. RAMຕሜ/܁ൽ֡ፕ
13. RAM߾ፕఇ๕
RAM Prole
ఇ๕ጴ
RAM߾ፕఇ๕
000, 101, 110, 111 থገ࣑ఇ๕
001 ฉၽೢఇ๕
010 ມၠၽೢఇ๕
011 Ⴤມၠၽೢఇ๕
100 Ⴤთ࣍ఇ๕
12. RAM࣮ݣణڦ
RAM࣮ݣణڦ࿋
CFR1[30:29]
DDS႑ࡽ
֖ຕ
DDS֖ຕኸۨ࿋
00 ೕ୲ 31:0
01 ၎࿋!!!!!!!!!!!!
10 ޗ܈ 31:18
11 Ⴀ
(၎࿋ࢅޗ܈)
31:16 (၎࿋)
15:2 (ޗ܈)
AD9910
Rev. 0 | Page 34 of 64
࣮ݣLjጒༀᆩሺ/ຕഗደօٳڟኸۨڦں࿋
ዃăُຕഗڦ้ዓ୲ۨᅭକ࣮ݣ୲Ljิׯհႚڦ
֑ᄣ୲ăຕഗڦ้ዓᆯጒༀాևڦ16࿋Պײ้ۨ
ഗă้ۨഗሶᆯDDS้ዓLj้߰ཚࡗԍ٪
ሞRAM prole٪ഗዐڦ16࿋ںڦօ୲ยۨă
ںօ୲ۨխݣ୲ă૩සLjසࡕగᅃRAM proleڦ
ںօ୲16࿋ኵྺMLjఫཚࡗᅜူࠅ๕ᅜ໙ڥ
࣮ݣ୲ǖ
!!!!࣮ݣ୲=
ᇑ࣮ݣ୲ᆶ࠲ڦ֑ᄣ้߰(Δt)ྺǖ
Δt =
ཚࡗI/O܋ኴႜڦRAMຕ/܁ൽ֡ፕᆫံߛᇀ࣮
ݣ֡ፕăሞ࣮ݣఇ๕ዐܔRAMႜڦI/O֡ፕᅜዐඪ
ࢆհႚ݀ิă
࣮ݣRAMڦ32࿋ጴ݀ໃ၎ᆌڦDDS႑ࡽ
֖ຕLj༹న߲֖ຕLjᆯࠀీ٪ഗ1ዐ
ڦଇ߲RAM࣮ݣణڦ࿋ઠۨă32࿋ጴݴૌ12ă
RAM_SWP_OVR(RAM௮ྜׯ)ᆅগ
RAM_SWP_OVRᆅগ༵ࠃߛۉೝᆶၳڦ႑ࡽLjᆩઠ๖ᅃ
߲࣮ݣႾଚ֡ፕຐăُᆅগ֡ፕໜRAM߾ፕఇ๕Վࣅܸ
ՎࣅLjၘᅜူቤবăසࡕRAM๑ీ࿋ྺ0Ljُᆅগഽ
ྺஇگۉೝă
RAM࣮ݣఇ๕߁ຎ
RAMࠌᆶ5ዖ࣮ݣఇ๕ă
t থገ࣑ఇ๕
t ฉၽೢఇ๕
t ມၠၽೢఇ๕
t Ⴤມၠၽೢఇ๕
t Ⴤთ࣍ఇ๕
߾ፕఇ๕ཚࡗ࿋ᇀ߲RAM prole٪ഗዐڦ3࿋RAMఇ
๕ጴስăᅺُLjRAM߾ፕఇ๕ൽᇀproleăRAM
proleఇ๕ጴၘ13ă
RAMথገ࣑ఇ๕
ሞথገ࣑ఇ๕ዐLjRAMփፕྺհႚ݀ิഗ๑ᆩăᅺُLj
๑ᆩPROFILE[2:0]ᆅগስRAM proleࢫLjኻᆶڇ߲32࿋
ጴፕྺ႑ࡽ֖ຕ݀ໃڟDDSăኄ߲32࿋ڦጴԍ٪
ሞRAMዐproleڦ10࿋հႚഐ๔ںتă
ሞথገ࣑ఇ๕ዐLjRAM_SWP_OVRᆅগ๔ዕྺஇ0Lj
ཞ้ࢮݥጂାߛ࿋ă
থገ࣑ఇ๕ፌߛኧ8FSKĂPSKASKۙǗۙ
ૌ႙ᆯRAM࣮ݣణڦ࿋)FSKೕ୲ڪ*ă߲RAM
proleۼᇑ༹ڦೕ୲Ă၎࿋ࢅޗ܈ᆶ࠲ă߲RAM
proleዐ߳ྸᅃհႚഐ๔ںᆯԍ٪ሞ၎ᆌRAM࿋ዃڦ
32࿋ጴݡ࿚ăܸٗํ၄proleᆅগࠀీLjӀႴᄲ
ۙDDSă
42. RAMխݣ֡ፕ
RAM
ADDRESS
DATA
Q
PROFILE
DDS CLOCK
RAM
PROFILE
REGISTERS
STATE
MACHINE
UP/DOWN
COUNTER
3210
2
3
16
10
10
U/D
3
06479-023
WAVEFORM END ADDRESS
WAVEFORM START ADDRESS
ADDRESS RAMP RATE
NO DWELL
RAM MODE
TO DDS
SIGNAL
CONTROL
PARAMETER
M
f
M
f
SYSCLKDDSCLOCK
4
=
SYSCLK
f
M
atePlayback R
4
=
1
31:16
06479-024
WAVEFORM START ADDRESS
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
M DDS CLOCK CYCLES
WAVEFORM END ADDRESS
NO-DWELL
HIGH = 0
NO-DWELL
HIGH = 1
1
RAM ADDRESS
RAM ADDRESS
RAM_SWP_OVER
I/O_UPDATE
1 2 3
t
AD9910
Rev. A | Page 35 of 64
ጀᅪኻᄲ๑ᆩෙ߲proleᆅগڦഄዐᅃ߲ሞଇ߲փཞ֖ຕ
ኵኮൎ࣑ీํ၄ଇۙăཞᄣLjᄲํ၄຺ۙLj
ኻᄲ๑ᆩෙ߲proleᆅগዐڦଇ߲ă༹๑ᆩన߲ᆅ
গுᆶ၌ă
ଭሁRAMথገ࣑ఇ๕
༬ڦଭሁ)ଭሁ࿋๑ీ*ࠀీኻሞRAMথገ࣑ఇ๕
ዐ๑ᆩăଷྔLjኻᆶሞRAM࣮ݣణڦ࿋၎࿋ኸۨྺDDS
႑ࡽ֖ຕࢫLj֍ీ๑ᆩଭሁࠀీă
๑ీଭሁࠀీᅜჽDDSႎ၎࿋ኵLjჽٗDDS၎
࿋ેഗٗଉײՎྺଭገ)DDS၎࿋ેഗ၎࿋ঙ܈
ᆯ360°Վྺ0°ڦገՎۅ*ăᆯᇀኟ၀հ၎࿋ڦଭሁۅᇑޗ
܈ڦଭሁۅܔᆌLjᅺُኄܔDDSՊײิׯኟ၀հ)๑ᆩ
ስDDSኟ၀࿋*ݥᆶӻዺă
ܔᇀܾ၎ᅎ(BPSK)Ljଭሁ༬Ⴀᅜ๑AD9910ํ
၄BPSK 180°၎࿋ཌՎLjీࠕፌٷײ܈ຨ้ޗ܈ՎࣅLj
ܸٗՆ௨BPSK้ۙঢ়၄ڦೕොพă
ଭሁ༬ႠణڦᆩᇀDDSኟ၀Ljᄺᆩᇀᇆ
၀ăሞኄዖ൧ူLjړޗ܈ٳڟኟރኵ้Ljٗ
RAMዐڥڦ၎࿋ኵࣷԍ٪ሞDDSዐă
RAMฉၽೢఇ๕
ሞฉၽೢఇ๕ዐLjړI/O߸ႎዃ࿋ኁproleՎࣅ้LjRAM
ፕྺհႚ݀ิഗLj๑ᆩRAM prole٪ഗዐڦՊײ
֖ຕă૧ᆩRAM proleڦհႚഐ๔ںĂհႚຐں
ᅜںၽೢ୲ኵLjሞኸۨڦںݔྷൽRAMຕ
ăRAMຕߵRAM࣮ݣణڦ࿋݀ໃኸۨڦDDS႑ࡽ
֖ຕă
ాևጒༀٗհႚഐ๔ں๔ٗRAMൽႴຕLj
ڟຐںăڟٳຐںࢫLjߵݥጂାߛ࿋ۨᅭ൧
LjጒༀᅜԍհႚຐںLjኁݓ࣮հႚഐ๔ں
ăኮࢫጒༀዐኹLjRAM_SWP_OVRᆅগՎྺߛۉೝă
ฉၽೢ้Ⴞ
43၂๖କฉၽೢሏႜఇ๕LjԈࡤଇዖ൧ǖኟࢅݥጂ
ା֡ፕă
ฉ௬ڦଇཉࡆ๖ٗproleڦഐ๔ںڟຐں
ڦRAMհႚჄՎࣅ൧ăጒༀాև้ۨഗْᅯLj
ںኵۼࣷ1ă้ۨഗዜ(Δt)ᆯproleڦںၽೢ
୲ۨăฉ௬ଇཉࡆڦ൶՚ྺݥጂାዃߛ࿋ጒༀڦփ
ཞă
43ዐټᇶංຕጴ๖փཞ๚Lj༹ࡤᅭසူǖ
๚1—I/O߸ႎኁprole߀Վăُ๚ጒༀ؛๔ࣅ
հႚഐ๔ںLjժRAM_SWP_OVRᆅগยྺஇ0ă
๚2—ጒༀٳڟproleڦհႚຐںኵă
RAM_SWP_OVRᆅগൎ࣑ڟஇ1Lj๖ኟհႚ݀ิ֡
ፕຐă
๚3—ጒༀൎ࣑ڟհႚഐ๔ںLj๖ݥጂା֡ፕڦ
հႚ݀ิ֡ፕຐă
߸߀proleRAM_SWP_OVRᆅগዘዃྺஇ0ࣷጲۯዐኹ
ړമհႚ݀ิLjഔۯႎስڦհႚă
43. ฉၽೢ้Ⴞ
ాևProle࿋(CFR1[20:17])հႚૌ႙ ాևProle௮ຎ
0000 ాևprole্ᆩă
0001 ݀ ኴႜProle 0LjProle 1Ljࢫዐኹă
0010 ݀ ኴႜProle 0Prole 2Ljࢫዐኹă
0011 ݀ ኴႜProle 0Prole 3Ljࢫዐኹă
0100 ݀ ኴႜProle 0Prole 4Ljࢫዐኹă
0101 ݀ ኴႜProle 0Prole 5Ljࢫዐኹă
0110 ݀ ኴႜProle 0Prole 6Ljࢫዐኹă
0111 ݀ ኴႜProle 0Prole 7Ljࢫዐኹă
1000 Ⴤ ኴႜProle 0LjProle 1LjჄă
1001 Ⴤ ኴႜProle 0Prole 2LjჄă
1010 Ⴤ ኴႜProle 0Prole 3LjჄă
1011 Ⴤ ኴႜProle 0Prole 4LjჄă
1100 Ⴤ ኴႜProle 0Prole 5LjჄă
1101 Ⴤ ኴႜProle 0Prole 6LjჄă
1110 Ⴤ ኴႜProle 0Prole 7LjჄă
ၳă 1111
13. RAM߾ፕఇ๕
AD9910
Rev. 0 | Page 36 of 64
SBNฉၽೢాևQspgjmfఇ๕
߲ࡗײᆯࠀీ٪ഗ1(CFR1)ዐڦాևprole࿋࠶
Ljၘ14ă
ُ้Ljޏႜူᅃዜۯፕൽᇀհႚ࣏݀
Ⴤăܔᇀ݀հႚLjጒༀሞڟٳፌࢫᅃ߲proleհႚ
ຐںࢫዐኹ֡ፕăܔᇀჄհႚLjጒༀጲۯཌ
Prole 0LjӀproleຩႾጲۯׂิհႚăཚࡗాևprole
࿋ՊײࢅI/O߸ႎᆶၳยዃᅜዐኹჄհႚڦ݀ิă
݀հႚ้Ⴞ֖44ăۨCFR1٪ഗዐڦాև
prole࿋Պײኵྺ0010LjRAM Prole 1 ዐڦഐ๔ں
ٷᇀRAM Prole 0ዐڦຐںǗRAM Prole 2ዐڦഐ๔
ںٷᇀRAM Prole 1ዐڦຐںăڍᇑ߲proleᆶ
࠲ڦࠀీᅜߵ߲proleڦഐ๔/ຐںඪᅪ
ስăଷྔLj๖૩࣏၂๖߲proleᅜ๑ᆩփཞڦΔt
ኵă
ฉၽೢాևproleఇ๕ᆯ຺߲ాևprole࿋
)փRAM prole٪ഗዐڦRAM proleఇ๕࿋*ă
සࡕඪࢆాևprole࿋ኮᅃዃ1LjሶRAM prole٪ഗ
ዐڦRAM proleఇ๕࿋ࣷԥࢮăُఇ๕ࣷࢮݥጂ
ାߛ࿋ăాևproleఇ๕ᇑฉၽೢఇ๕ૌຼLjփཞኮ
تሞᇀాևproleఇ๕ൎ࣑ᅜํ၄ాևጲۯൎ࣑Ǘ
ࢮPROFILE[2:0]ᆅগጒༀăProleዜ֖14ă
ాևproleᆶଇዖհႚ݀ิႚ๕ǖ݀հႚࢅჄհ
ႚăܔᇀኄଇዖૌ႙ڦհႚLjጒༀۼӀProle 0ዐࡀۨڦ
հႚഐ๔ںĂհႚຐںࢅںၽೢ୲֡ፕăٳڟ
Prole 0ዐհႚຐںࢫLjጒༀጲۯူᅃ߲proleLj
ምӀႎprole֖ຕׂิኸۨհႚăړጒༀٳڟႎproleհ
ႚڦຐں้LjჄူᅃ߲proleăُ֡ፕჄ
ႜLjጒༀٳڟፌࢫᅃ߲proleڦհႚຐںLjኝ
AD9910
Rev. A | Page 37 of 64
࢙حۥևڦࣨཉ๖ኸۨproleڦ้߰ăዐټ
ᇶංڦຕጴ๖༹ڦ๚ǖ
๚1—I/O߸ႎ٪ഗాևprole࿋ԍ٪ྺ)ሞ
ࠀీ٪ഗ1*0010ăRAM_SWP_OVRᆅগยྺஇ0ăጒ
ༀ؛๔ࣅྺRAM Prole 0ڦհႚഐ๔ںLjժሞRAM
Prole 0ยۨڦኝ߲ںݔྷฉӀΔt0߰)ᆯRAM Prole 0
ڦںၽೢ୲ඓۨ*๔ڿሺă
๚2—ጒༀڟٳRAM Prole 0ڦհႚຐںLj
RAM_SWP_OVRᆅগׂิଇ߲DDS้ዓዜڦኟஞ؋ă
๚3—ڟٳRAM Prole 0ڦհႚຐںࢫLjాև้ۨഗ
ူᅃْᅯࣷ๑ጒༀRAM Prole 1ăጒༀ؛๔ࣅ
ྺRAM Prole 1ڦհႚഐ๔ںLjժሞRAM Prole 1ยۨڦ
ኝ߲ںݔྷฉӀΔt1߰๔ڿሺă
๚4—ጒༀڟٳRAM Prole 1ڦհႚຐںLj
RAM_SWP_OVRᆅগׂิଇ߲DDS้ዓዜڦኟஞ؋ă
๚5—ڟٳRAM Prole 1ڦհႚຐںࢫLjాև้ۨഗ
ူᅃْᅯࣷ๑ጒༀRAM Prole 2ăጒༀ؛๔ࣅ
ྺRAM Prole 2ڦհႚഐ๔ںLjժሞRAM Prole 2ยۨڦ
ኝ߲ںݔྷฉӀΔt2߰๔ڿሺă
๚6—ጒༀڟٳRAM Prole 2ڦհႚຐںLj
RAM_SWP_OVRᆅগׂิଇ߲DDS้ዓዜڦኟஞ؋ă
๚7—ڟٳRAM Prole 2հႚຐںࢫLjాև้ۨഗူ
ᅃْᅯࣷ๑ጒༀዐኹLjՔኾኝ߲݀ஞ؋հႚิׯࡗ
ײᅙྜׯă
RAM_SWP_OVER
WAVEFORM START ADDRESS 0
WAVEFORM END ADDRESS 0
1
WAVEFORM START ADDRESS 1
WAVEFORM END ADDRESS 1
1
WAVEFORM END ADDRESS 2
1
RAM PROFILE 210
WAVEFORM START ADDRESS 2
RAM
ADDRESS
I/O_UPDATE
t
0
t
1
t
2
1 2 3 4 5 6 7
0
6479-025
44. ాևProle้Ⴞ(݀հႚ)
WAVEFORM START
ADDRESS 0
WAVEFORM END
ADDRESS 0
WAVEFORM START
ADDRESS 1
WAVEFORM END
ADDRESS 1
0
6479-026
1
RAM_SWP_OVER
RAM PROFILE
RAM
ADDRESS
I/O_UPDATE
010 0 11
1 2 3 4 5 6 7 8 9 10 11
t
0
t
1
1
AD9910
Rev. 0 | Page 38 of 64
45. ాևProle้ႾDŽჄհႚDž
๚5๚11—ኄၵ๚ࣷ၌ዘްLjأݥాևprole
࿋ዘႎՊײLjI/O߸ႎዃ࿋Ljă
RAMມၠၽೢఇ๕
ሞມၠၽೢఇ๕ዐLjI/O߸ႎዃ࿋ࢫLjRAMኻ๑ᆩRAM
Prole 0ዐڦᅙՊײ֖ຕׂิհႚ)փཞᇀฉၽೢఇ๕๑ᆩ
ඇև8߲prole*ă૧ᆩRAM proleڦհႚഐ๔ںĂ
հႚຐںᅜںၽೢ୲ኵLjሞኸۨڦںݔྷฉ
ൽRAMຕăຕߵRAM࣮ݣణڦ࿋݀ໃኸۨڦDDS
႑ࡽ֖ຕă
ሞُఇ๕ዐLjPROFILE[2:1]ᆅগጒༀᆯాևஇࢮă
ስሏႜُఇ๕ڦՊײRAM proleࢫLjሞRAM proleዘႎ
Պײ֑ᆩഄRAM֡ፕఇ๕മLj݆ስഄRAM
proleăُఇ๕ࣷࢮݥጂାߛ࿋ă
ཚࡗI/O߸ႎ߀Վproleມၠၽೢఇ๕้Ljాևጒༀ
ᅜٗհႚഐ๔ں๔ڥRAMຕăړ
PROFILE0ྺஇ1้๔ൽຕLjኸ๖ጒༀሞኝ߲ں
ݔྷฉ๔ڿሺăኻᄲPROFILE0ᆅগԍLogic 1Ljጒༀ
ࣷሞڟٳհႚຐںമ๔ዕٗRAMൽຕăڟٳ
ຐںࢫLjጒༀۯፕዐኹLjසࡕROFILE0ᆅগՎྺஇ
0Ljሶጒༀሞኝ߲ںݔྷฉ๔ڿăኻᄲPROFILE0
ᆅগԍஇ0Ljጒༀࣷሞڟٳհႚഐ๔ںമ๔ዕٗ
RAMൽຕăڟٳഐ๔ںࢫLjጒༀۯፕዐኹă
ాևProleჄհႚ้Ⴞ
45ߴକాևproleڦჄհႚ้Ⴞăۨ
ాևprole࿋(ሞࠀీ٪ഗ1ዐ)Պײྺ1000Ljཞ
้ۨRAM Prole 1ዐڦഐ๔ںٷᇀRAM Prole 0ዐڦ
ຐںă
࢙حۥևڦࣨཉཉ๖ኸۨproleڦ้߰ăዐ
ټංຕጴ๖༹ڦ๚ă
๚1—I/O߸ႎ٪ഗాևprole࿋ԍ٪ྺ(ሞ
ࠀీ٪ഗ1)1000ăRAM_SWP_OVRᆅগยྺஇ0ăጒ
ༀ؛๔ࣅྺRAM Prole 0ڦհႚഐ๔ںLjժሞRAM
Prole 0ڦኝ߲ںݔྷฉӀΔt0߰(ᆯRAM Prole 0ڦں
ၽೢ୲ඓۨ)๔ڿሺă
๚2—ጒༀڟٳRAM Prole 0ڦհႚຐںLj
RAM_SWP_OVRᆅগׂิଇ߲DDS้ዓዜڦኟஞ؋ă
๚3—ڟٳRAM Prole 0ڦհႚຐںࢫLjాև้ۨഗ
ူᅃْᅯࣷ๑ጒༀRAM Prole 1ăጒༀ؛๔ࣅ
ྺRAM Prole 1ڦհႚഐ๔ںLjժሞRAM Prole 1ยۨ
ڦኝ߲ںݔྷฉӀΔt1߰๔ڿሺă
๚4—ጒༀڟٳRAM Prole 1ڦհႚຐںLj
RAM_SWP_OVRᆅগׂิଇ߲DDS้ዓዜڦኟஞ؋ă
๚5—ڟٳRAM Prole 1ڦհႚຐںࢫLjాև้ۨഗ
ူᅃْᅯࣷ๑ጒༀཌ࣮RAM Prole 0ăጒༀ؛๔ࣅ
ྺRAM Prole 0ڦհႚഐ๔ںLjժሞRAM Prole 0ยۨ
ڦኝ߲ںݔྷฉӀΔt0߰๔ڿሺă
0
6479-027
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
PROFILE0
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
1 2 3 4 5 6 7 8
t
t
M DDS CLOCK CYCLES
AD9910
Rev. A | Page 39 of 64
සࡕPROFILE0ᆅগሞጒༀڟٳՊײยۨڦഐ๔ຐ
ںമ߀ՎጒༀLjాև้ۨഗࣷዘႎഔۯLjںຕഗ
๔ݒၠຕă
46၂๖କມၠၽೢఇ๕ڦ൧ăړPROFILE0ᆅগጒༀՎ
ࣅ้Ljጒༀፕ၎ᆌڦۯፕၚᆌLjཞ้ߴକ
RAM_SWP_OVRᆅগڦጒༀՎࣅă
ړጒༀڟٳհႚຐں้LjRAM_SWP_OVRᆅগൎ࣑
ڟஇ1ăሞጒༀڟٳհႚഐ๔ںժPROFILE0ᆅগ
ᆯஇ0Վׯஇ1ኮമLjRAM_SWP_OVRᆅগ๔ዕԍஇ
1ă
46ዐټᇶංຕጴ๖փཞ๚Lj༹ࡤᅭසူǖ
๚ 1—I/O߸ႎ߀ՎproleᅜRAMມၠၽೢఇ๕ă
ጒༀ؛๔ࣅྺհႚഐ๔ںLjRAM_SWP_OVRᆅগยྺ
இ0ă
๚2—ᆅগPROFILE0ൎ࣑ڟஇ1ăጒༀ๔ܔRAM
ںຕഗڿሺຕă
๚3—ᆅগPROFILE0๔ዕԍஇ1Ljڟጒༀڟٳհ
ႚຐںăRAM_ SWP_OVRᆅগ၎ᆌൎ࣑ڟஇ1ă
๚4—ᆅগPROFILE0ൎ࣑ڟஇ0ăጒༀ๔ܔRAM
ںຕഗڿຕăRAM_ SWP_OVRᆅগԍஇ1ă
๚5—ᆅগPROFILE0ൎ࣑ڟஇ1ăጒༀް࿋ాև้ۨ
ഗLjժ๑RAMںຕഗݒၠຕ)ǖ๔ڿሺ*ăᆯᇀ
ช࿄ٳڟհႚഐ๔ںLjRAM_SWP_OVRጒༀՎࣅă
๚6—ᆅগPROFILE0ൎ࣑ڟஇ0ăጒༀް࿋ాև้ۨ
ഗLjժᄺ๑RAMںຕഗݒၠຕă
RAM_SWP_OVRጒༀՎࣅă
๚7—ᆅগPROFILE0๔ዕԍஇ0Ljڟጒༀڟٳհ
ႚഐ๔ںăRAM_SWP_OVRጒༀՎࣅă
๚8—PROFILE0ൎ࣑ڟஇ1ăጒༀް࿋ాև้ۨഗLj
ժ๔ܔRAMںຕഗڿሺຕăᆯᇀᅙঢ়ٳڟଇ߲հ
ႚഐ๔ںLjRAM_SWP_OVRᆅগൎ࣑ྺஇ0Lj
PROFILE0ᆅগᆯஇ0Վྺஇ1ă
RAMჄມၠၽೢఇ๕
ሞჄມၠၽೢఇ๕ዐLjړI/O߸ႎዃ࿋ኁproleՎࣅ
้LjRAMፕྺհႚ݀ิഗLj๑ᆩPROFILExᆅগኸۨڦ
RAM prole٪ഗዐڦՊײ֖ຕă૧ᆩRAM proleڦ
հႚഐ๔ںĂհႚຐںᅜںၽೢ୲ኵLjሞኝ߲
ںݔྷฉൽRAMຕăຕߵRAM࣮ݣణڦ࿋݀
ໃኸۨڦDDS႑ࡽ֖ຕăُఇ๕ࣷࢮݥጂାߛ
࿋ă
ཚࡗI/O߸ႎ߀ՎproleჄມၠၽೢఇ๕้Ljాև
ጒༀ๔ٗհႚഐ๔ںൽRAMຕLjժڿሺں
ຕഗLjڟాևጒༀٳڟհႚຐںྺኹăُ้Ljጒ
ༀࣷጲۯ๑ںຕഗݒၠຕLjٗኝ߲ںݔྷ๔
ڿăஃٳڟనᅃ܋ںLjጒༀۼࣷ๑ںຕഗݒ
ၠຕǗኝ߲ࡗײࣷ၌Ⴤă
46. ມၠၽೢ้Ⴞ
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
t
t
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
M DDS CLOCK CYCLES
1 2 3
06479-028
AD9910
Rev. 0 | Page 40 of 64
47. Ⴤມၠၽೢ้Ⴞ
PROFILEᆅগጒༀՎࣅࢫࣷዐኹړമհႚLjᆩႎስڦ
RAM proleׂิႎհႚă
ړጒༀڟٳհႚຐں้LjRAM_SWP_OVRᆅগൎ࣑
ྺஇ1,ໜࢫሞհႚഐ๔ںݓ࣮இ0LjْڟٳںՉ
হ้ۼࣷൎ࣑ᅃْஇጒༀă
47ߴକჄມၠၽೢఇ๕ڦ๖ᅪăዐټංڦຕጴ
๖༹ڦ๚ǖ
๚1—I/O߸ႎprole߀ՎRAMჄມၠၽೢఇ
๕ăጒༀ؛๔ࣅڟհႚഐ๔ںăRAM_SWP_OVRᆅগ
ް࿋ڟஇ0ăጒༀሞኝ߲ںݔྷฉ๔ڿሺă
๚2—ጒༀڟٳհႚຐںăRAM_SWP_OVRᆅগ
ൎ࣑ྺஇ1ă
๚3—ጒༀڟٳհႚഐ๔ںăRAM_SWP_OVRᆅগ
ൎ࣑ྺஇ0ă
ሞఇ๕݀ิՎࣅമLjჄມၠၽೢࣷ၌ሏႜă
AD9910
Rev. B | Page 41 of 64
06479-029
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
1
1 2 3 4 5
RAM ADRESS
RAM_SWP_OVER
I/O_UPDATE
M DDS CLOCK CYCLES
t
48. Ⴤთ้࣍Ⴞ
RAMჄთ࣍ఇ๕
Ⴤთ࣍ఇ๕ᇑฉၽೢఇ๕ૌຼLjփཞኮتሞᇀړጒༀ
ڟٳհႚຐں้Ljాև้ۨഗူᅃג้ࣷ๑ጒༀཌ
հႚഐ๔ںăሞI/O߸ႎprole߀ՎኮമLjࣷ๔ዕዘ
ްׂิᇱᆶհႚă
ُఇ๕ࣷࢮݥጂାߛ࿋ă
Proleᆅগጒༀ߀ՎࣷዐኹړമհႚLjᆩႎስڦRAM
proleׂิႎհႚă
ړጒༀڟٳհႚຐں้LjRAM_SWP_OVRᆅগׂิ
ଇ߲DDS้ዓዜڦߛۉೝஞ؋ă
48ዐټᇶංڦຕጴ๖༹ڦ๚ǖ
๚1—I/O߸ႎኁprole߀Վăُ๚ጒༀ؛๔ࣅ
հႚഐ๔ںLjժRAM_SWP_OVRᆅগยྺஇ0ă
๚2—ጒༀٳڟproleڦհႚຐںኵă
RAM_SWP_OVRᆅগൎ࣑ྺஇ1LjჄଇ߲DDS้ዓዜ
ă
๚3—ጒༀൎ࣑ڟհႚഐ๔ںLjჄܔںຕഗ
ڿሺຕă
๚4—ጒༀምْڟٳproleڦհႚຐںLj
RAM_SWP_OVRᆅগሞଇ߲DDS้ዓዜࢫൎ࣑ྺஇ
1ă
๚5—ጒༀൎ࣑ڟհႚഐ๔ںLjჄܔںຕഗ
ڿሺຕă
๚4ࢅ๚5—ሞI/O߸ႎኁprole߀ՎമLjኄၵ๚ࣷ
փዘްă
AD9910
Rev. B | Page 42 of 64
ഄ༬Ⴀ
15. Proleᆅগ
PROFILE[2:0] ᆶၳProle
0 000
1 100
2 010
3 110
4 001
5 101
6 011
7 111
SYNC_CLK
SYSCLK
AB
NN + 1
N – 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS NN + 1 N + 2
I/O_UPDATE
T
HE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
06479-061
49. I/O_UPDATEٗI/O࣐؋ഗၠᆶၳ٪ഗدຕ
PROFILE
AD9910ኧ߳ዖproleࠀీLjᆯᅃፇԈࡤᇑ༹֡ፕఇ๕
ᆶ࠲֖ຕڦ8߲٪ഗፇׯă๑ᆩProleᅜሞփཞ֖ຕย
ዃኮൎ࣑ăProle֖ຕཚࡗزႜI/O܋ՊײăՊײ
ࢫLjᆯෙ߲ྔևᆅগ(PROFILE[2:0])ስ༬ۨڦproleă
ܔproleᆅগแࢇڦஇۉೝᅜ༬ۨڦ
proleLjၘ൧൩֖15ă
ߵഗ֑ᆩڦփཞ֡ፕఇ๕Lj8߲prole٪ഗᅜ
ଇፇփཞڦ֖ຕăړRAM๑ీ࿋ = 0Ljprole֖ຕ֑ᆩڇ
ᅼprole߭๕Ljၘ“٪ഗࢅ࿋ࠀీ௮ຎ”ևݴăړ
RAM๑ీ࿋ = 1้Lj֑ᆩRAM prole߭๕ă
ܔᇀproleڦ๑ᆩLjᅜԨڦມೕೕᅎ(FSK)ྺ૩ă
FSK๑ᆩزႜԲ༬ୁܾຕٗଇዖփཞڦೕ୲ႜ
ስǖدࡽೕ୲(இ1)ࢅࡽೕ୲(இ0)ăഗ֑ᆩڇᅼఇ
๕ํ၄ೕᅎ(FSK)ăڇᅼProle 0٪ഗ๑ᆩࢇڦೕ
୲ۙၿጴՊײׂิܔᆌࡽڦೕ୲ăڇᅼProle 1٪ഗ๑
ᆩࢇڦೕ୲ۙၿጴՊײׂิܔᆌدࡽڦೕ୲ăࢫLj
PROFILE1ࢅPROFILE2ᆅগথஇ0LjPROFILE0ᆅগ
থزႜԲ༬ୁăኄᄣᅜ૧ᆩPROFILE0ᆅগڦஇጒༀ
ߵزႜԲ༬ୁܾຕׂิടړڦدࡽࢅࡽೕ୲ă
ProleᆅগՂႷፁSYNC_CLKฉืᄂڦ૬ࢅԍ้
ᄲ൱ă
I/O_UPDATEĂSYNC_CLKࢅဣཥ้ዓ࠲ဣ
I/O_UPDATEᆅগᆩᇀزႜI/O࣐؋ഗዐڦຕدڟഗ
ᆶၳ٪ഗዐăኻ٪ሞ࣐؋ഗዐڦຕၳڦă
SYNC_CLKຌᇀฉืᄂᆶၳ႑ࡽLjᆯ຺ݴೕۉୟܔဣཥ้
ዓݴೕࢫڥă๑ᆩSYNC_CLKLjᅜํ၄ྔևᆘ
ᇑAD9910ాև้ዓཞօă
I/O_UPDATEᆩᇀഔۯ࣐؋ഗຕገᅎLjᅜᇑ
SYNC_CLKཞօᅴօăසࡕፁ႑ࡽڦ૬้ᄲ
൱LjሶDACᅜڥ࢛ۨڦჽ(ୁ၍)ă૩සLjස
ࡕႴᄲཚࡗSPI܋ݒް߀Վ၎࿋ೋᅎLjDACዐڦኄ
ၵՎࣅჽԍփՎǗޏሶLjࣷ၄ᅃ߲SYNC_CLKዜ
ڦփඓ้ۨă
ඍู൧ူLjI/O_UPDATEᆅগཚ႑ࡽࣷܔഗ߾
ፕ֖ຕႜཞօ߸ႎăሞI/O_UPDATEฉืᄂLj٪ഗా
ඹࣷԥدڟഗڦాև߾ፕᇮăኁLjٗՊײ٪ഗ
ڟాևᆘڦՊײຕدᅜཚࡗ߀ՎPROFILE[2:0]ᆅ
গጒༀํ၄ă
49ዐڦ้Ⴞ၂๖କ࣐؋ഗຕၠᆶၳ٪ഗدڦ൧
ă
AD9910
Rev. B | Page 43 of 64
16. ஞ؋܈ยዃ
I/O߸ႎ୲࿋
(CFR2[15:14]) I/O߸ႎஞ؋܈
21 00 SYSCLKs
42 10 SYSCLKs
84 01 SYSCLKs
69 11 SYSCLKs
ጲۯI/O߸ႎ
AD9910༵ࠃᅃዖၜLjഄI/O߸ႎࠀీᅜጲۯዃ࿋Lj
Ⴔᅈડᆩࢽ༵ࠃྔև႑ࡽăᄲํ၄ُࠀీLjዃ࿋ࠀీ
٪ഗ2(CFR2)ዐڦాևI/O߸ႎᆶၳ࿋ă
ഔᆩُࠀీࢫLjI/O_UPDATEᆅগࣷՎׯᆅগLj݀
ิᅃ߲ాևI/O߸ႎࢫۼׂࣷิᅃ߲ߛۉೝᆶၳஞ؋ăஞ
؋܈ᆯI/O߸ႎ୲࿋(CFR2[15:14])ඓۨă16ߴକ
ٷዂڦஞ؋܈ยዃă
বۉ!
AD9910ᅜݴ՚ܔഗ຺༹߲ఇႜবۉăবۉ
ࠀీᆩڦ༹ఇԈઔǖ
t ຕጴాࢃ
t %"$
t ޤዺDAC
t REFCLK้ዓۉୟ
ຕጴాࢃবۉఇ๕্ࣷᆩزႜI/O܋߸ႎăڍLjཚࡗ
زႜ܋ධీൣ0ຕጴবۉ࿋Ljᅜݞ၄݆࣬ްኟ
߾ፕጒༀڦ൧ă
বۉཚࡗࠀీ٪ഗ1(CFR1)ዐڦ4߲܀૬ব
ۉ࿋࠶ăবۉႴᄲEXT_PWR_DWNᆅ
গጒༀഽยྺஇ0ăሞኄዖ൧ူLjยዃ၎ᆌڦবۉ
࿋)ཚࡗزႜI/O܋*ܔ၎ᆌఇํแবۉLj
࿋ൣ0ᅜ࣬ްኟ߾ፕጒༀă
ኁLjཚࡗEXT_PWR_DWNᆅগ૧ᆩྔևᆘᅜ
๑຺߲ࠀీఇཞู้ۉఇ๕ăړُᆅগഽยྺஇ
1้Ljஃবۉ࿋ጒༀසࢆLj຺߲ۉୟఇۼࣷ
বۉఇ๕Ǘᄺ৽ຫLjړEXT_PWR_DWNྺஇ1้Lj
CFR1ዐڦ܀૬বۉ࿋ࣷԥࢮă
ߵྔևবۉ࿋ڦጒༀLjEXT_PWR_DWNᆅগᅜ
֑ᆩྜඇবۉఇ๕ኁ࣬ްবۉఇ๕ă࣬ްবۉ
ఇ๕ԍܔDACೋዃۉୟĂPLLĂVCOࢅ้ዓۉୟࠃ
ۉă࣬ްูۉఇ๕বీၳࡕփසྜඇูۉఇ๕Lj
ڍᅜํ၄ഗูٗۉጒༀ࣬ްڟኟሏႜă
I/O߸ႎཚ႑ࡽᅜᆩઠཚኪྔևഗLjഗᅙሞా
ևׂิକᅃ߲I/O߸ႎă
ాևI/O߸ႎڦೕ୲ཚࡗزႜI/O܋Պײยዃăೕ୲ᆯଇ
߲֖ຕǖڼᅃ߲֖ຕCFR2ዐڦଇ߲I/O߸ႎ୲
࿋Ǘڼܾ߲ยዃాևຕഗݔྷڦI/O߸ႎ୲٪
ഗዐڦ32࿋ጴăI/O߸ႎ୲࿋ᅜሞ¼ fSYSCLKڦ
إฉׂิ1Ă1/2Ă1/41/8ڦ้ዓ႑ࡽăݴೕഗ้ዓᆯ
ฉຎ32࿋ాևຕഗăI/O߸ႎڦೕ୲໙ࠅ๕ǖ
fI/O_UPDATE =
ഄዐǖ
AԈࡤI/O߸ႎ୲࿋ڦ2࿋ጴڦኵăBԍ٪ሞ
I/O߸ႎ୲٪ഗዐڦ32࿋ጴڦኵă
Aڦඍูኵྺ0LjBڦඍูኵྺ0xFFFFăසࡕBڦՊײኵၭ
ᇀڪᇀ0x0003LjI/O_UPDATEᆅগփምׂิஞ؋Ljܸ
Ⴤྺஇ1ጒༀă
B
f
A
SYSCLK
2
2+
AD9910
Rev. B | Page 44 of 64
ܠഗཞօ
0
6479-050
SYNC
GENERATOR
REF_CLK
5
SYSCLK
INTERNAL
CLOCKS
5
4
SYNC
RECEIVER
SYNC
GENERATOR
ENABLE
SYNC
GENERATOR
DELAY
SYNC
POLARITY
90
91
9
10
REF_CLK
INPUT
CIRCUITRY
7
8
12
SYNC_IN+
REF_CLK
SYNC_IN–
SYNC_SMP_ERR
SYNC
VALIDATION
DELAY
SYNC
TIMING
VALIDATION
DISABLE
CLOCK
GENERATOR
SETUP AND
HOLD VALIDATION
SYNC
RECEIVER
ENABLE
SYNC
RECEIVER
DELAY
INPUT DELAY
AND EDGE
DETECTION
SYNC_OUT+
SYNC_OUT–
50. ཞօۉୟࠀీ
SYSCLK
SYNC
GENERATOR
ENABLE
SYNC
GENERATOR
DELAY
SYNC
POLARITY
SYNC_OUT+
SYNC_OUT–
0
1
DQ
R
PROGAMMABLE
DELAY
÷16
5
9
10
9
10
LVDS
DRIVER
0
6479-051
51. ཞօ݀ิഗ
ሞ้ዓጒༀದጒༀገ࣑ཞօڦཉူLjᅜํ၄ܠഗ
ཞօă้ዓཞօᅜሎႹᆩࢽႜܠഗᅴօՊײLjܸ
ཚࡗܔᆶഗཞ้ႜI/O߸ႎઠཞօՊײాඹă
AD9910ዐڦཞօஇࠀీᅜഽాև้ዓ݀ิഗᇨ
ۨᅭڦጒༀLjᇑSYNC_Inxᆅগฉྔևཞօ႑ࡽԍᅃ
ዂăසࡕᆶഗۼഽ֑ᆩ၎ཞڦ้ዓጒༀLjᇑཞᅃྔ
և႑ࡽԍཞօLjߵۨᅭLjሶኄၵഗཞօă50ߴ
କཞօڦࠀీăཞօஇݴྺଇ߲܀૬ڦఇǖ
ཞօ݀ิഗࢅཞօথഗLjଇևݴ๑ᆩԨںSYSCLK႑
ࡽፕྺాև้ۨă
ཞօ݀ิഗఇ֖51Ljᆯཞօ݀ิഗ๑ీ࿋ă૧
ᆩཞօ݀ิഗᅜ๑AD9910ፕྺᅃፇഗዐڦዷ้ዓ֖
ᇸLjഄᇆྺዷڦٗഗă
16
_
SYSCLK
OUTSYNC
f
f=
ཞօ݀ิഗሞSYNC_OUTxᆅগฉׂิ้ዓ႑ࡽLj้ዓ
႑ࡽᆯLVDSൻۯഗ݀ໃLjԲྺ50%ă้ዓڦࠦۨೕ୲
໙ࠅ๕ǖ
ߵཞօ݀ิഗႠ࿋LjSYNC_OUTxᆅগ้ዓ႑ࡽᅜ
ᇑాևSYSCLK႑ࡽฉืူইᄂཞօăᆯᇀSYNC_OUTx
႑ࡽᇑዷഗڦాևSYSCLKཞօLjዷഗڦSYSCLKፕ
ྺᆶٗഗڦ֖ᇸăཚࡗزႜI/O܋ܔ5࿋ཞօ
݀ิഗჽጴᅜ~150 psօՊײLjᆩࢽᅜጲႜۙব
SYNC_OUTx႑ࡽڦჽăՊײჽᆶዺᇀ߀
Չᄂ้ႾܔഋڦଳႠLj༵ߛኝ༹ཞօႠీă
ཞօথഗఇ(֖52)ᆯཞօথഗ๑ీ࿋(0x0A[27])
ăཞօথഗԈઔෙ߲ጱఇǖჽࢅՉᄂ֪
ఇĂాև้ዓ݀ิഗఇĂ૬ࢅԍᄓኤఇă
๑ཞօথഗ࿄๑ీLj้ዓ݀ิഗఇᄺࣷԍ߾ፕጒ
ༀă
ཞօᇀසူยLj߲ഗฉڦREFCLK႑ࡽీ
ᇑྔևREFCLKݴದဣཥׂิڦ႑ࡽํ၄Չᄂܔഋ(֖
53)ă
AD9910
Rev. B | Page 45 of 64
LVDS
RECEIVER
PROGAMMABLE
DELAY
5
INTERNAL
CLOCKS
CLOCK
STATE
SYNC PULSE
SYSCLK
SETUP AND HOLD
VALIDATION
4
Q0
RESET
Qn
DELAYED SYNC-IN SIGNAL
SYNC
RECEIVER
DELAY
SYNC
RECEIVER
ENABLE
SYNC_SMP_ERR
7
8
12
RISING EDGE
DETECTOR
AND
STROBE
GENERATOR
SYNC
TIMING
VALIDATION
DISABLE
SYNC
VALIDATION
DELAY
06479-052
CLOCK
GENERATOR
s
s
s
s
s
s
SYNC_IN+
SYNC_IN–
52. ཞօথഗ
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 1 MASTER DEVICE
FPGA
DATA
FPGA
DATA
FPGA
DATA
EDGE
ALIGNED
A
T REF_CLK
INPUTS
EDGE
ALIGNED
AT SYNC_IN
INPUTS.
PDCLK
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 2
PDCLK
SYNC
IN
SYNC
OUT
REF_CLK
AD9910
NUMBER 3
PDCLK
(FOR EXAMPLE AD951x)
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
06479-053
CLOCK
SOURCE
53. ܠഗཞօ๖૩
ཞօথഗথSYNC_InxᆅগฉڦዜႠ้ዓ႑ࡽă
ُۨ႑ࡽᆯLVDSඹൻۯഗׂิăཚࡗܠഗཞօ٪
ഗዐ5࿋ཞօথഗჽጴӀ~150 psօՊײᅜܔ
SYNC_Inx႑ࡽႜჽăՊײჽ႑ࡽჽ
ڦSYNC_Inx႑ࡽă
Չᄂ֪இิׂཞօஞ؋Ljஞ؋܈ྺᅃ߲SYSCLK้
ዓዜLjዘް୲ڪᇀSYNC_Inxᆅগڦ႑ࡽೕ୲ăཞօஞ
؋ཚࡗԨںSYSCLKڦฉืᄂܔჽڦSYNC_Inx႑ࡽڦฉ
ืᄂ֑ᄣׂิăཞօஞ؋݀ໃాև้ዓ݀ิഗ(၎ړᇀᅜ
SYSCLK୲ሏႜڦᇨዃຕഗ)ăཞօஞ؋ຕഗย
ྺᇨۨᅭጒༀ(ཚࡗܠഗཞօ٪ഗዐڦ6࿋ཞօጒༀᇨ
ยጴՊײ)ăᇨۨᅭጒༀኻܔڇ߲SYSCLKዜᆶၳLjຐ
ࢫLj้ዓ݀ิഗࣷཚࡗSYSCLK୲ዐڦጒༀႾଚ࣬ްኟ
თ࣍ăኄᅃ܀༬ڦጒༀᇨย༵ߛକᆩࢽ๑ᆩଳ
ႠLjཚࡗܔ༬ۨ၎ܔ้ዓጒༀೋዃํ၄ഗཞօ(ܔ߲
ഗݴದփཞڦཞօጒༀᇨยኵ)ă
ܔ߲AD9910༵ࠃᅃ߲ᇑᆶഗՉᄂܔഋڦSYNC_Inx
႑ࡽᅜڥܠഗཞօăසࡕᆶഗڦSYNC_INx႑
ࡽํ၄ՉᄂܔഋLjᆶ၎ཞڦཞօথഗჽࢅཞօጒༀ
AD9910
Rev. B | Page 46 of 64
SYNC
PULSE
SYSCLK
DELAY
DELAY
CHECK LOGIC
4SYNC VALIDATION
DELAY
4
4SYNC_SMP_ERR
SYNC RECEIVE
R
12
SYNC TIMING VALIDATION DISABLE
SETUP
VALIDATION
HOLD
VALIDATION
DQ
12
SETUP AND HOLD VALIDATION
TO
CLOCK
GENERATION
LOGIC
FROM
SYNC
RECEIVER
DELAY
LOGIC
DQ
DQ
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
06479-054
54. ཞօ้Ⴞᄓኤఇ
ᇨยኵLjሶᆶഗۼࣷᆶದ้ዓጒༀ(ཞօ)ă53
ߴኄᅃ߁๖ᅪLj3߲AD9910ഗཞօLjᅃ߲ഗፕ
ྺዷ้ዓഗLjഄྺٗഗă
ዷഗՂႷSYNC_INxᆅগፕྺཞօݴದࢅჽ࢚
ڦᅃևݴLj֍ీํ၄ᇑٗഗཞօă
ཞօ้ٗዓݴದࢅჽ࢚ఇ๔Ljᆩᇀඓԍᆶ
ഗۼీথڟՉᄂܔഋڦREFCLK႑ࡽăփࡗLj๑
ᆶഗڦREFCLK႑ࡽۼํ၄ՉᄂܔഋLjڇೞُᄺփీԍ
ኤ߲ాև้ዓ݀ิഗڦ้ዓጒༀۼీᇑഄഗԍᅃ
ዂăኄ৽Ⴔᄲ๑ᆩཞօࢅჽ࢚ఇăُఇথዷഗ
ׂิڦSYNC_OUTx႑ࡽLjഄፕྺSYNC_INxዘႎ
ݴದߴٗഗ(ཞ้ݒઍߴዷഗ)ăዘႎݴದዷഗׂิ
ڦSYNC_OUT x႑ࡽڦణڦ๑ᆶཞօথഗڥՉᄂ
ܔഋڦSYNC_INx႑ࡽă
ۨᆶഗۼᆶ၎ཞڦREFCLKᄂ(૧ᆩ้ዓݴದࢅჽ
࢚ఇ)Ljժᆶഗۼᆶ၎ཞڦSYNC_INxᄂ(૧ᆩཞ
օࢅჽ࢚ఇ)Ljఫᆶഗۼׂࣷิᅃ߲ᅃዂڦా
ևཞօஞ؋(ۨᆶഗۼᆶ၎ཞڦཞօথഗჽ
ኵ)ăසࡕᅃօࡀۨᆶഗۼᆶ၎ཞڦཞօጒༀᇨย
ኵLjఫঢ়ࡗཞօتڦཞօஞ؋ᅜ๑ᆶᇨย၎ཞ้
ዓጒༀڦഗཞօLjᆶഗాև้ዓํ၄ྜඇཞօă
ཞօൽᇀཞօথഗዐՉᄂ֪ఇీޏ࿘ׂۨิ
ཞօஞ؋ăփࡗLjᄲׂิᆶၳڦཞօஞ؋LjႴᄲཚࡗԨں
SYSCLKฉืᄂܔჽSYNC_INx႑ࡽฉืᄂႜኟඓ֑
ᄣăසࡕኄၵ႑ࡽڦՉᄂ้Ⴞ݆ፁՉᄂհۉୟాև
٪ڦ૬ԍ้ᄲ൱Ljሶᆶీׂ݆ิࢇڦཞ
օஞ؋ăᆩࢽᅜ૧ᆩ૬ࢅԍᄓኤఇ(֖54)ᄓ
ኤଇ߲႑ࡽኮޏᆶኟඓڦՉᄂ้Ⴞă
ཚࡗࠀీ٪ഗ2ዐڦཞօ้Ⴞᄓኤ্ᆩ࿋ᅜ্ᆩ
૬ࢅԍᄓኤఇă
ᄓኤఇኧᆩࢽጲۨᅭ้ش(૧ᆩܠႊೌཞօ٪ഗ
ዐڦ4࿋ཞօᄓኤჽጴӀ~150 psօՊײ)ă૬ࢅԍ
ᄓኤۉୟ๑ᆩڦ٪ഗᇑฉืᄂ֪ഗࢅཚ႑ࡽ݀
ิഗᅃᄣڦăՊײ้شᆩᇀೋၽԨںSYSCLK႑
ࡽฉืᄂࢅჽSYNC_INx႑ࡽฉืᄂኮڦ้Ⴞăසࡕ
ԍ૬ᄓኤۉୟ݆֪ڟᆶၳՉᄂ֑ᄣLjሶࣷཚࡗ
SYNC_SMP_ERRᆅগ၂๖(ߛۉೝᆶၳ)ă
ᆩࢽՂႷࢇስSYSCLKዜڦᅃևݴፕྺཞօᄓኤჽ
ኵă૩සLjසࡕSYSCLKೕ୲ྺ1 GHz(ዜ1 ns)Ljࢇኵᆌ
ྺ12(150ps300ps)ăኵٷඹᅟ๑SYNC_SMP_ERRᆅ
গׂิٱဃڦࠤቱ႑ࡽǗኵၭሶඍ݄࿘ۨႠă
AD9910
Rev. B | Page 47 of 64
ۉᇸݴፇ
AD9910ኧܠዖۉᇸLj༹ࠀࡼሶൽᇀۉᇸದዃăԨব
ถକۉᇸݴፇᅜ߲ఇࠀࡼໜೕ୲Վࣅڦ൧ă
ԨবዐڦᆅᆩڦຕৈࠃܔԲ֖ቷă༹ຕኵ֖1ă
ፇۉᇸᆌ๑ᆩ0.1 μF0.01 μFಖୟۉඹᇑ10 μFժă
ُتۉᇸݴፇᅱৈᆩᇀۆ႙ᆌᆩLj༹ݴྺ຺ૌǖ
3.3 VຕጴĂ3.3 VఇెĂ1.8 Vຕጴࢅ1.8 Vఇెă
ܔᇀᆶডߛႠీᄲ൱ڦᆌᆩీႴᄲሺۉᇸ߰ᇮă
3.3 Vۉᇸ
DVDD_I/O (3.3V)(ᆅগ11/15/21/28/45/56/66)
ኄၵ3.3 Vۉᇸݴྺᅃፇăኄၵᆅগࠀࡼࣷߵزႜ܋
ཚ႑൧ۯༀՎࣅă
AVDD (3.3V)(ᆅগ7477ࢅᆅগ83)
ኄၵ3.3 V DACۉᇸۆ႙ࡼۉଉྺ28 mAăณLjႴᄲᆩᅃ
߲ཎᄟ༹ىዩኄၵۉᇸᇑഄ3.3Vۉᇸ߰Ljፌࡻీ๑
ᆩ߰࿘უഗăኄၵۉᇸڦࡼۉዷᄲઠጲೋዃۉୁLjᅺُ
փࣷໜೕ୲Վࣅܸ݀ิՎࣅă
1.8 Vۉᇸ
DVDD (1.8V)(ᆅগ17/23/30/47/57/64)
ኄၵᆅগᅜݴྺᅃፇăᆅগࡼۉଉࣷໜጣဣཥ้ዓೕ୲
ሺٷܸ၍Ⴀሺٷă17ࢅ18ߴକۆ႙ࡼۉ൸၍ăଷྔLj
ړfOUTٗ50 MHzሺڟ400 MHz้Lj࣏ࣷሺ~5%ፑᆸۉᇸ
ၩࡼă
AVDD (1.8V)(ᆅগ3)
ُ1.8 VۉᇸዷᄲࠃᆌREFCLKױ݆ഗ(PLL)Ljࡼۉଉٷሀྺ
7 mAăܔᇀ๑ᆩPLLڦ߸ߛႠీᆌᆩLjُۉᇸᆌ๑ᆩ߰࿘
უഗᇑഄ1.8 V AVDDۉᇸ߰ăܔᇀᄲ൱փߛڦᆌᆩLj
ُۉᇸᅜփ๑ᆩ࿘უഗLj૧ᆩཎᄟ༹ىዩᆅগ89ࢅ92
ᇑᆅগ3߰ă
PLLڦ࣍ୟ୳հഗᆌথᇑᆅগ3থă๑PLLԥಖୟLj
ᆅগ3ධᄲࠃۉLjڍᅜփႜ߰ă
AVDD (1.8V)(ᆅগ6)
ُᆅগᅜᇑDVDD 1.8 Vۉᇸᆅগݴྺᅃፇăܔᇀ߸ߛႠ
ీᆌᆩLjᆌ๑ᆩཎᄟ༹ىዩ߰Ljፌࡻ๑ᆩ߰࿘უഗă
AVDD (1.8V)(ᆅগ89/92)
1.8 V REFCLKۉᇸࡼۉଉٷሀྺ15 mAăኄၵᆅগᅜ
ᇑᆅগ3ݴፇLj๑ᆩཎᄟ༹ىዩᆅগ3ᇑᆅগ89ࢅ92߰
ăณᆌ๑ᆩཎᄟ༹ىዩኄၵۉᇸᇑഄ1.8 Vۉᇸ
߰ăփࡗLjܔᇀ߸ߛႠీڦᆌᆩLjᅱ๑ᆩ߰࿘უ
ഗă
AD9910
Rev. B | Page 48 of 64
زႜՊײ
ኸସጴব႑တ࿋
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
R/W X X A4 A3 A2 A1 A0
থ—زႜI/O
AD9910زႜ܋ᅃዖଳڦཞօزႜཚრ܋Ljᅜ
ݛՍںᇑܠዖ߾ᄽᆩྲഗࢅྲتഗথăُزႜ
I/O܋ኧٷܠຕཞօد߭๕ă
ُথႜ܁/ႀ֡ፕLjݡ࿚ᆶAD9910ದዃ٪ഗă
ኧMSBᆫံࢅLSBᆫံد߭๕ăଷྔLjزႜথ܋
࣏ీದዃྺڇᆅগ/(SDIO)Ljፕྺ2-၍๕থ๑
ᆩǗኁLjᄺದዃྺଇ߲ڇၠ/ᆅগ
(SDIO/SDO)Ljፕྺ3-၍থ๑ᆩăଇ߲ᆅগ
(I/O_RESETࢅCS)ᅜ༵ߛ֑ᆩAD9910ڦยဣཥଳ
Ⴀă
ཚᆩزႜI/O֡ፕ
زႜཚ႑ዜݴྺଇ߲ăڼᅃ߲ኸସLjኸ
ସጴবႀAD9910ăኸସጴবԈࡤᄲݡ࿚ڦ٪ഗں
(֖“٪ഗ٪ئ൶ݴದࢅ࿋ࠀీ௮ຎ”ևݴ)Ljᅜۨ
ᅭႜڦຕد܁֡ፕ࣏ႀ֡ፕă
ڼܾႀዜኸٗزႜ܋ഗၠزႜ܋࣐؋ഗ
دຕăدڦጴবຕൽᇀݡ࿚ڦ٪ഗă૩සLjස
ࡕݡ࿚ࠀీ٪ഗ2(ں0x01)Ljڼ2Ⴔᄲد4߲
ጴবăຕᅃ࿋ۼ٪ሞSCLKڦ၎ᆌฉืᄂăزႜ܋
ഗႴᄲݡ࿚٪ഗڦᆶጴবǗޏሶLjزႜ܋
ഗሞူᅃ߲ཚ႑ዜཽ߾ፕ้ႾăփࡗLjᆶᅃ߲ݛ݆
ᅜႀณଉڦጴবLj๑ᆩI/O_RESETᆅগࠀీă૧ᆩ
I/O_RESETᆅগࠀీൽၩI/O֡ፕLjܔزႜ܋ഗኸኍ
ް࿋ăሞI/Oް࿋ࢫLjူᅃ߲ጴবྺኸସጴবăጀᅪሞ
I/Oް࿋മ߲ᅙྜඇႀڦጴবۼࣷԍ٪ሞزႜ܋࣐
؋ഗዐăᆶևݴႀڦጴব࿄ԍ٪ăሞඪᅃཚ႑ዜຐ
ࢫLjAD9910زႜ܋ۼথူઠڦ8߲SCLKฉืᄂᆩᇀႀ
ኸସጴবLj๔ူᅃ߲ཚ႑ዜă
ႀዜຐࢫLjՊײຕጂାሞزႜ܋࣐؋ഗዐLjت
ᇀၳጒༀăI/O_UPDATEزႜ܋࣐؋ഗዐڦຕد
ڟᆶၳ٪ഗăI/O߸ႎᅜሞྜׯᅃ߲ཚ႑ዜࢫ
ႜLjᄺᅜሞᆶزႜ֡ፕຐࢫႜăଷྔLj߀Վᅃ
ْproleᆅগጒༀᅜഔۯᅃْI/O߸ႎă
ܔᇀ܁ൽዜLjڼ2ᇑႀዜᅃዂLjփཞኮتሞ
ᇀǖٗᆶၳ٪ഗ܁ൽຕLjܸݥزႜ܋࣐؋ഗLjຕ
ሞSCLKူইᄂă
ጀᅪǖᄲ࣮܁ඪࢆprole٪ഗ(0x0E0x15)LjՂႷ๑ᆩෙ߲
ྔևproleᆅগă૩සLjසࡕprole٪ഗProle 5 (0x13)Lj
ఫPROFILE[0:2]ᆅগՂႷڪᇀ101ăኄփႴᄲႀprole
٪ഗă
ኸସጴব
ኸସጴবԈࡤසူ႑တLjၘኸସጴব႑တ࿋ă
R/W—ኸସጴব࿋7ۨኸସጴবႀዜຐࢫႜ܁࣏
ႀ֡ፕă.இ1๖܁֡ፕăൣ0๖ႀ֡ፕă
X, X—ኸସጴবڦ࿋6ࢅ࿋5ྺ࠲࿋ă
A4, A3, A2, A1, A0—ኸସጴবڦ࿋4Ă࿋3Ă࿋2Ă࿋1ࢅ࿋0
ۨཚ႑ዜዐຕدݡ࿚నᅃ߲٪ഗă
زႜI/O܋ᆅগࠀీ௮ຎ
SCLK—زႜ้ዓ
زႜ้ዓᆅগᆩᇀཞօ/AD9910ڦຕLjሏႜా
ևጒༀă
CS—ೌ႑ࡽ
CSگۉೝᆶၳLjԥᆩઠሞཞᅃཉزႜཚ႑၍ୟฉথܠ
߲ഗăړُྺߛۉೝ้LjSDOࢅSDIOᆅগࣷߛ
ፆጒༀăසࡕሞඪࢆཚ႑ዜా၄ߛۉೝLjሶُཚ႑
ዜሡཕLjڟCSዘႎԥگۉೝăೌ႑ࡽ(CS)
ᅜሞဣཥዐԥઙگLjᅜԍኤܔSCLKڦᆶၳă
زႜຕ/(SDIO)
ၠAD9910ႀຕՂႷཚࡗُᆅগႜăփࡗLjᆅগᄺ
ీፕྺມၠຕ၍๑ᆩăCFR1٪ഗ(ں0x00)ڦ࿋1
ُᆅগದዃăඍูྺൣ0LjSDIOᆅগದዃྺມၠຕ
၍ă
زႜຕ(SDO)
සࡕၹᅱስᆩփཞڦཚ႑၍ઠ݀ໃࢅথຕLjఫຕ
ٗᆅগ܁ڦăړAD9910ᅜڇ܀ڦມၠI/Oఇ๕ሏ
ႜ้LjُᆅগփࣷຕLjժዃྺߛፆጒༀă
AD9910
Rev. B | Page 49 of 64
I7
SDIO
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
CS
I6I5I4I3I2I1I0D7D6D5D4D3D2D1D0
06479-030
55. زႜ܋ႀ้ႾLj้ዓှྺگ
D
O7
INSTRUCTION CYCLE DATA TRANSFER CYCLE
DON'T CARE
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
SDIO
SCL
K
CS
SDO D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
06479-031
56. 3၍๕زႜ܋܁ൽ้ႾLj้ዓှྺگ
I
7
SDIO
INSTRUCTION CYCLE DATA TRANSFER CYCLE
S
CL
K
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
06479-032
57. زႜ܋ႀ้ႾLj้ዓှྺߛ
I7
SDIO
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCL
K
CS
I6I5I4I3I2I1I0DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
06479-033
58. 2၍๕زႜ܋܁ൽ้ႾLj้ዓှྺߛ
/ް࿋(I/O_RESET)
I/O_RESETᅜཞօI/O܋ጒༀLjփࣷᆖၚლ٪
ഗڦాඹăI/O_RESETᆅগᆶၳߛۉೝLjᅜ๑ړമ
ཚ႑ዜዐኹăሞI/O_RESETݓ࣮گۉೝࢫ(இ0)Ljଷᅃ
߲ཚ႑ዜ֍ీ๔Ljံኸସጴবႀă
/߸ႎ(I/O_UPDATE)
I/O_UPDATEᆩᇀI/O܋࣐؋ഗዐႀڦຕدڟᆶ
ၳ٪ഗăI/O_UPDATEሞฉืᄂᆶၳLjஞ؋܈ՂႷٷ
ᇀ1߲SYNC_CLKዜăߵܔాևI/O߸ႎᆶၳ࿋ڦՊײ
൧Ljᆅগᅜፕྺኁᆅগă
زႜI/O้Ⴞ
5558ߴକᅃၵԨ๖૩Lj௮ຎزႜI/O܋߳ዖ
႑ࡽኮڦ้Ⴞ࠲ဣăሞI/O߸ႎዃ࿋മLj٪ഗዐ
ڦٷܠຕ࿋ۼփࣷدڟഄాևణڦںLjኄᅃۅժ࿄ሞ
ူଚ้Ⴞዐݒᆙઠă
MSB/LSBد
AD9910زႜ܋ኧፌߛᆶၳ࿋(MSB)ᆫံࢅፌگᆶၳ࿋
(LSB)ᆫံଇዖຕ߭๕ăُࠀీᆯࠀీ٪ഗ1
(0x00)ዐڦ࿋0ăඍู߭๕MSBᆫံăසࡕLSBᆫံ
ᆶၳLjᆶຕLjԈઔኸସጴবLjՂႷፏთLSBᆫံᇱ
ሶăጀᅪLj߲٪ഗ࿋ᇘଚዐڦፌٷຕMSBLjፌၭຕ
٪ഗڦLSB(֖“٪ഗ٪ئ൶ݴದࢅ࿋ࠀీ௮
ຎ”ևݴࢅ17)ă
AD9910
Rev. B | Page 50 of 64
٪ഗ٪ئ൶ݴದࢅ࿋ࠀీ௮ຎ
17. ٪ഗ٪ئ൶ݴದ
٪ഗఁ
(Ⴤں)
࿋ݔྷ
(ాևں)࿋7 (MSB) ࿋0 (LSB)࿋6
ඍูኵ1
(ๆୃ
)
CFR1 —
ࠀీ
٪ഗ1
(0x00)
31:24 RAMዘݣᆩ 00x0ୟ
ۯOSK
ྔև
ݒSinc୳
հഗ๑ీ
ୟ 0x00
15:8 ሜ LRR
@ I/O߸ႎ
ጲۯൣଭ
ຕጴၽೢ
ેഗ
ጲۯൣଭ
၎࿋ેഗ
ൣଭຕጴ
ၽೢ
ેഗ
ൣଭ၎࿋
ેഗ
ሜ ARR
@ I/O ߸ႎ
OSK๑ీ ስጲۯ
OSK
0x00
0x00
7:0 ຕጴև
ݴۖۉ
DACۖۉ REFCLK
ۖۉ
ޤዺDAC
ۖۉ
ྔևۖۉ
ୟ ৈྺSDIO
LSBᆫံ
CFR2—
ࠀీ
٪ഗ2
(0x01)
๑ీڇᅼ
proles
ۙޗ܈
ୟ31:24 0x00
23:16 ాևI/O
߸ႎᆶၳ
SYNC_CLK
๑ీ
ຕጴၽೢᆩ ຕጴၽೢ
๑ీ
ຕጴၽೢ
ݥጂାߛ࿋
ຕጴၽೢ
ݥጂାگ࿋
܁ൽᆶၳڦ
FTW
0x40
15:8 ୟ PDCLK
๑ీ
PDCLK
ݒၠ
TxEnable
ݒၠ
ୟ
7:0 ჽದ
๑ీ
ຕࣹՊഗ
ԍାፌࢫኵ
ཞօ้Ⴞ
ᄓኤ্ᆩ
ժႜຕ
܋๑ీ
FMሺᅮ 0x20
CFR3—
3
(0x02)
31:24 ୟ DRV0[1:0] ୟ VCO SEL[2:0] 0x1F
Icp[2:0]ୟ23:16 ୟ 0x3F
15:8 REFCLK
ݴೕ
୲ഗಖୟ
REFCLK
ݴೕ୲ഗ
ዘዃB
ୟ PFDް࿋ ୟ PLL๑ీ 0x40
ୟN[6:0] 7:0 0x00
ޤዺDAC
(0x03)
0x00ୟ31:24
0x00ୟ23:16
0x00ୟ15:8
0x7FFSC[7:0]7:0
I/O߸ႎ୲
(0x04)
0xFFI/O߸ႎ୲[31:24]31:24
23:16 I/O߸ႎ୲[23:16] 0xFF
15:8 I/O߸ႎ୲[15:8] 0xFF
7:0 I/O߸ႎ୲[7:0] 0xFF
FTW—
ೕ୲ۙၿጴ
(0x07)
0x00ೕ୲ۙၿጴ[31:24]31:24
23:16 ೕ୲ۙၿጴ[23:16] 0x00
15:8 ೕ୲ۙၿጴ[15:8] 0x00
7:0 ೕ୲ۙၿጴ[7:0] 0x00
ስDDS
ኟ၀հ
ాևprole
23:16
RAM๑ీ
I/O߸ႎ୲ 0x08
࿋5࿋4࿋3࿋2࿋1
AD9910
Rev. B | Page 51 of 64
POW—
၎࿋ೋᅎጴ
(0x08)
00x0၎࿋ೋᅎጴ[15:8]15:8
7:0 ၎࿋ೋᅎጴ[7:0] 0x00
ASF—
ናޗԲ૩
ᅺጱ(0x09)
00x0ናޗၽೢ୲[15:8]31:24
ናޗၽೢ୲[7:0]23:16 00x0
15:8 ናޗԲ૩ᅺጱ[13:6] 0x00
7:0 ናޗԲ૩ᅺጱ[5:0] ናޗօ[1:0] 0x00
0x00
ܠႊೌཞօ
(0x0A)
31:24 ཞօᄓኤჽ[3:0] ཞօথ
ഗ๑ీ
ཞօ݀ิ
ഗ๑ీ
ཞօ݀ิ
ഗႠ
ୟ
23:16 ཞօጒༀᇨยኵ[5:0] ୟ 0x00
15:8 ཞօ݀ิഗჽ[4:0] ୟ 0x00
7:0 ཞօ݀ิഗჽ[4:0] ୟ 0x00
ຕጴၽೢ
၌ኵ(0x0B)
A/Nຕጴၽೢฉ၌ኵ[31:24]63:56
55:48 ຕጴၽೢฉ၌ኵ[23:16] N/A
47:40 ຕጴၽೢฉ၌ኵ[15:8] N/A
39:32 ຕጴၽೢฉ၌ኵ[7:0] N/A
31:24 ຕጴၽೢူ၌ኵ[31:24] N/A
23:16 ຕጴၽೢူ၌ኵ[23:16] N/A
15:8 ຕጴၽೢူ၌ኵ[15:8] N/A
7:0 ຕጴၽೢူ၌ኵ[7:0] N/A
ຕጴၽೢ
օ(0x0C)
A/Nຕጴၽೢڿօ[31:24]63:56
55:48 ຕጴၽೢڿօ[23:16] N/A
47:40 ຕጴၽೢڿօ[15:8] N/A
39:32 ຕጴၽೢڿօ[7:0] N/A
31:24 ຕጴၽೢڿሺօ[31:24] N/A
23:16 ຕጴၽೢڿሺօ[23:16] N/A
15:8 ຕጴၽೢڿሺօ[15:8] N/A
7:0 ຕጴၽೢڿሺօ[7:0] N/A
ຕጴၽೢ
୲(0x0D)
A/Nຕጴၽೢၽ୲[15:8]31:24
23:16 ຕጴၽೢၽ୲[7:0] N/A
15:8 ຕጴၽೢኟၽ୲[15:8] N/A
7:0 ຕጴၽೢኟၽ୲[7:0] N/A
ڇೕۙ
Prole 0
(0x0E)
80x0ናޗԲ૩ᅺጱ0[13:8]ୟ63:56
55:48 ናޗԲ૩ᅺጱ0[7:0] 0xB5
47:40 ၎࿋ೋᅎጴ0[15:8] 0x00
39:32 ၎࿋ೋᅎጴ0[7:0] 0x00
31:24 ೕ୲ۙၿጴ0[31:24] 0x00
23:16 ೕ୲ۙၿጴ0[23:16] 0x00
15:8 ೕ୲ۙၿጴ0[15:8] 0x00
7:0 ೕ୲ۙၿጴ0[7:0] 0x00
٪ഗఁ
)زႜں*
࿋ݔྷ
(ాևں)࿋7 (MSB) ࿋0 (LSB)࿋6
ඍูኵ1
(ๆୃ
)࿋5࿋4࿋3࿋2࿋1
AD9910
Rev. B | Page 52 of 64
RAM
Prole 0
(0x0E)
ୟ63:56
55:48 RAM Prole 0ںօ୲[15:8] 0x00
0x00
47:40 RAM Prole 0ںօ୲[7:0] 0x00
39:32 RAM Prole 0հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 0հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 0հႚഐ๔ں[9:2] 0x00
0x00
0x00
15:8 RAM Prole 0հႚഐ๔
ں[1:0]
ୟ
7:0 ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 0ఇ๕[2:0]
ڇೕۙ
Prole 1
(0x0F)
ናޗԲ૩ᅺጱ1[13:8]ୟ
ୟ
63:56
55:48 ናޗԲ૩ᅺጱ1[7:0] 0x00
0x00
47:40 ၎࿋ೋᅎጴ1[15:8] 0x00
39:32 ၎࿋ೋᅎጴ1[7:0] 0x00
31:24 ೕ୲ۙၿጴ1[31:24] 0x00
23:16 ೕ୲ۙၿጴ1[23:16] 0x00
15:8 ೕ୲ۙၿጴ1[15:8] 0x00
7:0 ೕ୲ۙၿጴ1[7:0] 0x00
0x00
RAM
Prole 1
(0x0F)
ୟ63:56
55:48 RAM Prole 1ںօ୲[15:8] 0x00
47:40 RAM Prole 1ںօ୲[7:0] 0x00
39:32 RAM Prole 1հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 1հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 1հႚഐ๔ں[9:2] 0x00
0x00
0x00
0x00
15:8 RAM Prole 1հႚഐ๔
ں[1:0]
ୟ
7:0 ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 1ఇ๕[2:0]
ڇೕۙ
Prole 2
(0x10)
ናޗԲ૩ᅺጱ2[13:8]
ୟ
ୟ
ୟ
63:56
55:48 ናޗԲ૩ᅺጱ2[7:0] 0x00
47:40 ၎࿋ೋᅎጴ2[15:8] 0x00
39:32 ၎࿋ೋᅎጴ2[7:0] 0x00
31:24 ೕ୲ۙၿጴ2[31:24] 0x00
23:16 ೕ୲ۙၿጴ2[23:16] 0x00
15:8 ೕ୲ۙၿጴ2[15:8] 0x00
7:0 ೕ୲ۙၿጴ2[7:0] 0x00
0x00
RAM
Prole 2
(0x10)
ୟ63:56
55:48 RAM Prole 2ںօ୲[15:8] 0x00
47:40 RAM Prole 2ںօ୲[7:0] 0x00
39:32 RAM Prole 2հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 2հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 2հႚഐ๔ں[9:2] 0x00
0x00
0x00
15:8 RAM Prole 2հႚഐ๔
ں[1:0]
ୟ
7:0 ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 2ఇ๕[2:0]
٪ഗఁ
)زႜں*
࿋ݔྷ
(ాևں)࿋7 (MSB) ࿋0 (LSB)࿋6
ඍูኵ1
(ๆୃ
)࿋5࿋4࿋3࿋2࿋1
AD9910
Rev. B | Page 53 of 64
ڇೕۙ
Prole 3
(0x11)
ናޗԲ૩ᅺጱ3[13:8]ୟ63:56
55:48 ናޗԲ૩ᅺጱ3[7:0] 0x00
0x00
47:40 ၎࿋ೋᅎጴ3[15:8] 0x00
39:32 ၎࿋ೋᅎጴ3[7:0] 0x00
31:24 ೕ୲ۙၿጴ3[31:24] 0x00
23:16 ೕ୲ۙၿጴ3[23:16] 0x00
15:8 ೕ୲ۙၿጴ3[15:8] 0x00
7:0 ೕ୲ۙၿጴ3[7:0] 0x00
0x00
RAM
Prole 3
(0x11)
ୟ63:56
55:48 RAM Prole 3ںօ୲[15:8] 0x00
47:40 RAM Prole 3ںօ୲[7:0] 0x00
39:32 RAM Prole 3հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 3հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 3հႚഐ๔ں[9:2] 0x00
0x00
15:8 RAM Prole 3հႚഐ๔
ں[1:0]
ୟ
7:0 ୟ
ୟ
ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 3ఇ๕[2:0] 0x00
0x00
ڇೕۙ
Prole 4
(0x12)
ናޗԲ૩ᅺጱ4[13:8]ୟ63:56
55:48 ናޗԲ૩ᅺጱ4[7:0] 0x00
47:40 ၎࿋ೋᅎጴ4[15:8] 0x00
39:32 ၎࿋ೋᅎጴ4[7:0] 0x00
31:24 ೕ୲ۙၿጴ4[31:24] 0x00
23:16 ೕ୲ۙၿጴ4[23:16] 0x00
15:8 ೕ୲ۙၿጴ4[15:8] 0x00
7:0 ೕ୲ۙၿጴ4[7:0] 0x00
0x00
RAM
Prole 4
(0x12)
ୟ63:56
55:48 RAM Prole 4ںօ୲[15:8] 0x00
47:40 RAM Prole 4ںօ୲[7:0] 0x00
39:32 RAM Prole 4հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 4հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 4հႚഐ๔ں[9:2] 0x00
0x00
0x00
0x00
15:8 RAM Prole 4հႚഐ๔
ں[1:0]
ୟ
7:0 ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 4ఇ๕[2:0]
ڇೕۙ
Prole 5
(0x13)
ናޗԲ૩ᅺጱ5[13:8]ୟ63:56
55:48 ናޗԲ૩ᅺጱ5[7:0] 0x00
47:40 ၎࿋ೋᅎጴ5[15:8] 0x00
39:32 ၎࿋ೋᅎጴ5[7:0] 0x00
31:24 ೕ୲ۙၿጴ5[31:24] 0x00
23:16 ೕ୲ۙၿጴ5[23:16] 0x00
15:8 ೕ୲ۙၿጴ5[15:8] 0x00
7:0 ೕ୲ۙၿጴ5[7:0] 0x00
٪ഗఁ
)زႜں*
࿋ݔྷ
(ాևں)࿋7 (MSB) ࿋0 (LSB)࿋6
ඍูኵ1
(ๆୃ
)࿋5࿋4࿋3࿋2࿋1
AD9910
Rev. B | Page 54 of 64
RAM
Prole 5
(0x13)
ୟ63:56
55:48 RAM Prole 5ںօ୲[15:8] 0x00
0x00
47:40 RAM Prole 5ںօ୲[7:0] 0x00
39:32 RAM Prole 5հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 5հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 5հႚഐ๔ں[9:2] 0x00
0x00
0x00
0x00
15:8 RAM Prole 5հႚഐ๔
ں[1:0]
ୟ
7:0 ୟ ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 5ఇ๕[2:0]
ڇೕۙ
Prole 6
(0x14)
ናޗԲ૩ᅺጱ6[13:8]ୟ63:56
55:48 ናޗԲ૩ᅺጱ6[7:0] 0x00
47:40 ၎࿋ೋᅎጴ6[15:8] 0x00
39:32 ၎࿋ೋᅎጴ6[7:0] 0x00
31:24 ೕ୲ۙၿጴ6[31:24] 0x00
23:16 ೕ୲ۙၿጴ6[23:16] 0x00
15:8 ೕ୲ۙၿጴ6[15:8] 0x00
7:0 ೕ୲ۙၿጴ6[7:0] 0x00
0x00
RAM
Prole 6
(0x14)
ୟ63:56
55:48 RAM Prole 6ںօ୲[15:8] 0x00
47:40 RAM Prole 6ںօ୲[7:0] 0x00
39:32 RAM Prole 6հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 6հႚຐ
ں[1:0]
RAM Prole 6հႚഐ๔
ں[1:0]
ୟ
23:16 RAM Prole 6հႚഐ๔ں[9:2] 0x00
0x00
0x00
0x00
15:8 ୟ
7:0 ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 6ఇ๕[2:0]
ڇೕۙ
Prole 7
(0x15)
ናޗԲ૩ᅺጱ7[13:8]ୟ
ୟ
63:56
55:48 ናޗԲ૩ᅺጱ7[7:0] 0x00
47:40 ၎࿋ೋᅎጴ7[15:8] 0x00
39:32 ၎࿋ೋᅎጴ7[7:0] 0x00
31:24 ೕ୲ۙၿጴ7[31:24] 0x00
23:16 ೕ୲ۙၿጴ7[23:16] 0x00
15:8 ೕ୲ۙၿጴ7[15:8] 0x00
7:0 ೕ୲ۙၿጴ7[7:0] 0x00
0x00
RAM
Prole 7
(0x15)
ୟ63:56
55:48 RAM Prole 7ںօ୲[15:8] 0x00
47:40 RAM Prole 7ںօ୲[7:0] 0x00
39:32 RAM Prole 7հႚຐں[9:2] 0x00
0x00
31:24 RAM Prole 7հႚຐ
ں[1:0]
ୟ
23:16 RAM Prole 7հႚഐ๔ں[9:2] 0x00
0x00
0x00
15:8 RAM Prole 7հႚഐ๔
ں[1:0]
ୟ
7:0 ୟ ݥጂାߛ࿋ ୟ ଭሁ RAM Prole 7ఇ๕[2:0]
RAM (0x16) RAMጴ[31:0] 0x00
1 N/A = փᆩă
٪ഗఁ
)زႜں*
࿋ݔྷ
(ాևں)࿋7 (MSB) ࿋0 (LSB)࿋6
ඍูኵ1
(ๆୃ
)࿋5࿋4࿋3࿋2࿋1
31:0
AD9910
Rev. B | Page 55 of 64
18. CFR1ڦ࿋ݴದ
࿋ ᆅগఁ ௮ຎ
31 RAM๑ీ 0 = RAMࠀీ্ᆩ(ඍู)ă
1 = RAMࠀీ๑ీ(ሜ/܁ൽࢅ࣮ݣ֡ፕႴᄲ)ă
30:29 RAM࣮ݣణڦں ၘ൧֖12Ljඍูኵྺ00bă
28:24 ୟ
23 ۯOSKྔև ৈሞCFR1[9:8] = 10b้ᆶၳă
0 = OSKᆅগၳ(ඍู)ă
1 = OSKᆅগ๑ీۯOSK(ၘ൧൩֖“ናޗ”ևݴ)ă
22 ݒSinc୳հഗ๑ీ 0 = ݒSincSinc୳հഗԥಖཚ(ඍู)ă
1 = ݒSinc୳հഗᆶၳă
ୟ 21
20:17 ాևprolelৈሞCFR1[31] = 1้ᆶၳăኄၵ࿋ႴႜI/O߸ႎీิၳă
ၘ൧൩֖14Ljඍูኵྺ0000bă
16 ስDDSኟ၀հ 0 = ስDDSᇆ၀(ඍู)ă
1 = ስDDSኟ၀ă
15 ሜLRR @ I/O߸ႎ ৈሞCFR2[19] = 1้ᆶၳă
0 = ຕጴၽೢ้ۨഗኟ֡ፕ(ඍู)ă
1 = I/OJJPDATEዃ࿋ኁPROFILE[2:0]߸߀ࢫLjຕጴၽೢ้ۨഗໜ้ሜă
14 ጲۯൣଭຕጴၽೢેഗ 0 = DRGેഗኟ߾ፕ(ඍู)ă
1 = ঢ়ࡗᅃ߲DDS้ዓዜࢫLjၽೢેഗް࿋Ljໜࢫેഗጲۯ࣬ްኟ֡ፕă
ኻᄲُ࿋ԍยዃLjْI/O_UPDATEዃ࿋ኁPROFILE[2:0]߸߀ࢫLj
ၽೢેഗۼࣷሡ้ް࿋ăُ࿋ᇑI/O _UPDATEዃ࿋
PROFILE[2:0]߸߀ሞ SYNC_CLKူᅃ߲ฉืᄂཞօă
13 ጲۯൣଭ၎࿋ેഗ 0 = DDS၎࿋ેഗኟ߾ፕ(ඍู)ă
1 = ሞI/O_UPDATEዃ࿋ኁprole߸߀ࢫLjཞօް࿋DDS၎࿋ેഗă
٪ഗ࿋ࠀీ௮ຎ!
زႜI/O܋٪ഗںݔྷٗ023(ๆୃǖ0x00
0x16)Ljࠌᆶ24߲٪ഗăڍLjഄዐᆶଇ߲٪ഗ࿄๑
ᆩLjᅜኻᆶ22߲ᆩ٪ഗă࿄๑ᆩڦ٪ഗྺ٪ഗ
5ࢅ٪ഗ6(0x05ࢅ0x06)ă
٪ഗݴದڟڦጴবຕ߳փ၎ཞăᄺ৽ຫLj٪ഗᆶ
փཞڦศ܈Ljഄጴবඹଉൽᇀ༬ۨڦࠀీᄲ൱ăଷྔLj
٪ഗዷᄲߵഄࠀీంఁăᆶ้ࢪ٪ഗࣷᇀݛՍ
ᅬڦᇱሶంఁă૩සLjزႜں0x00ڦ٪ഗంఁྺ
ࠀీ٪ഗ1Lj๖ྺඹᅟᅬڦCFR1ă
ူ࿔ၘဦถକAD9910٪ഗዐڦᅃ߲࿋ڦࠀీăܔ
ᇀᆯܠ߲࿋ࠌཞํ၄గᅃ༬ۨࠀీڦ൧Ljኝ߲࿋ፇ
ྺᅃ߲ܾጴLjዐᅜຫă
ԨবాඹӀ٪ഗزႜںຩႾፇኯă߲ޭՔ༶ᆯ٪
ഗఁࢅڦ٪ഗ(ઔࡽా)ፇׯăଷྔLj࣏ଚ
କ٪ഗڦๆୃ߭๕زႜںࢅڦጴবຕă
߲ޭՔ༶ࢫۼଚᆶᅃቧLjၘဦຫ٪ഗዐ߲߳࿋
ڦࠀీፕᆩă٪ഗዐ࿋ڦ༹࿋ዃᆯڇ߲ຕጴLjଇ߲
ᆯஶࡽ߰ڦຕጴ๖Ǘଇ߲߰ڦຕጴ(සǖA:B)๖ٗ
ፌߛᆶၳ࿋(A)ڟፌگᆶၳ࿋(B)ڦ࿋ݔྷă૩සLj5:2๖
ٗԲ༬࿋5Բ༬࿋2LjԈઔLjᆯ0࿋๖٪ഗڦLSBă
أଷᆶຫLjሞI/O_UPDATEᆅগዃ࿋ኁprole߸߀ኮ
മLjᅙՊײ࿋փࣷدڟాևణڦ࿋ዃă
ࠀీ٪ഗ1 (CFR1)—ں0x00
ُ٪ഗݴದକ຺߲ጴবă
AD9910
Rev. B | Page 56 of 64
࿋ ᆅগఁ ௮ຎ
12 ൣଭຕጴၽೢેഗ 0 = DRGેഗኟ߾ፕ(ඍู)ă
1 = DRGેഗᅴօLjৢༀް࿋ăኻᄲُ࿋ዃ1Ljၽೢેഗ๔ዕԍް࿋ጒༀă
ُ࿋ᇑI/O _UPDATEPROFILE[2:0]߸߀ሞSYNC_CLKူᅃ߲ฉืᄂཞօă
11 ൣଭ၎࿋ેഗ 0 = DDS၎࿋ેഗኟ߾ፕ(ඍู)ă
1 = DRG၎࿋ેഗᅴօLjৢༀް࿋ă
10 ሜARR @ I/O ߸ႎ ৈሞCFR1[9:8] = 11b้ᆶၳă
0 = OSKናޗၽೢ୲้ۨഗኟ֡ፕ(ඍู)ă
1 = I/OJJPDATEዃ࿋ኁPROFILE[2:0]߸߀ࢫLj
OSKናޗၽೢ୲้ۨഗໜ้ᅜዘႎሜă
9 OSK๑ీ ናޗ๑ీ࿋ă
0 = OSK্ᆩ(ඍู)ă
1 = OSK๑ీă
8 ስጲۯOSK ৈሞCFR1[9] = 1้ᆶၳă
0 =ۯOSK๑ీ(ඍู)ă
1 = ጲۯOSK๑ీă
7 ຕጴևݴ࠲ۉ ُ࿋ႴI/O߸ႎิၳă
0 = ຕጴాࢃ้ዓ႑ࡽᆶၳ(ඍู)ă
1 = ຕጴాࢃ้ዓ႑ࡽ্ᆩă
6 DAC࠲ۉ 0 = DAC้ዓ႑ࡽࢅೋዃۉୟᆶၳ(ඍู)ă
1 = DAC้ዓ႑ࡽࢅೋዃۉୟ্ᆩă
5 REFCLK࠲ۉ ُ࿋ႴI/O߸ႎิၳă
0 = REFCLKۉୟࢅPLLᆶၳ(ඍู)ă
1 = REFCLKۉୟࢅPLL্ᆩă
4 ޤዺDAC࠲ۉ 0 = ޤዺDAC้ዓ႑ࡽࢅೋዃۉୟᆶၳ(ඍู)ă
1 = ޤዺDAC้ዓ႑ࡽࢅೋዃۉୟ্ᆩă
3 ྔև࠲ۉ 0 = EXT_PWR_DWNᆅগዃ࿋ํ၄ඇ௬࠲ۉ(ඍู)ă
1 = EXT_PWR_DWNᆅগዃ࿋֑ᆩ࣬ް࠲ۉఇ๕ሏႜă
ୟ 2
1 ৈྺSDIO 0 = ದዃSDIOᆅগႜມၠ֡ፕǗ2၍๕زႜՊײఇ๕(ඍู)ă
1 = زႜຕI/Oᆅগ(SDIO)ৈದዃྺᆅগLj3၍๕زႜՊײఇ๕ă
0 LSBᆫံ 0 = ದዃزႜI/O܋ྺMSBᆫံ߭๕(ඍู)ă
1 = ದዃزႜI/O܋ྺLSBᆫံ߭๕ă
AD9910
Rev. B | Page 57 of 64
ࠀీ٪ഗ2 (CFR2)—ں0x01
ُ٪ഗݴದକ຺߲ጴবă
19. CFR2ڦ࿋ݴದ
࿋ ᆅগఁ ௮ຎ
31:25
24 ڇೕۙprole
ናޗݔྷ๑ీ
ୟ
CFR2[19] = 1LjCFR1[31] = 1CFR1[9] = 1้Ljၳă
0 = বీఇ๕ူLjናޗԲ૩ഗԥಖཚLj࠲Կ(ඍู)ă
1 = ናޗԲ૩ᆯᆶၳproleዐڦASFă
23 ాևI/O߸ႎᆶၳ ُ࿋ႴI/O߸ႎิၳă
0 =زႜI/OՊײᇑྔևI/O_UPDATEᆅগዃ࿋ཞօLj
ᆅগԥದዃྺᆅগ(ඍู)ă
1 = زႜI/OՊײᇑాևׂิڦI/O߸ႎ႑ࡽཞօ
(ాև႑ࡽሞದዃྺᆅগڦI/OJJPDATEᆅগฉׂิ)ă
22 SYNC_CLK๑ీ
ຕጴၽೢణڦں
0 = SYNC_CLKᆅগ্ᆩǗৢༀஇ0ă
1 = SYNC_CLKᆅগׂิ1/4 fsysclk้ዓ႑ࡽLjᆩᇀཞօزႜI/O܋(ඍู)ă
21:20 ၘ൧൩֖11ăඍูኵྺ00băၘ൧൩֖“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
19 ຕጴၽೢ๑ీ 0 = ຕጴၽೢ݀ิഗࠀీ্ᆩ(ඍู)ă
1 = ຕጴၽೢ݀ิഗࠀీ๑ీă
18 ຕጴၽೢݥጂାߛ࿋ ၘ൧൩֖“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
0 = ݥጂାߛ࿋ࠀీ্ᆩ(ඍู)ă
1 = ݥጂାߛ࿋ࠀీ๑ీă
17 ຕጴၽೢݥጂାگ࿋ ၘ൧൩֖“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
0 = ݥጂାگ࿋ࠀీ্ᆩ(ඍู)ă
1 = ݥጂାگ࿋ࠀీ๑ీă
16 ܁ൽᆶၳڦFTW
I/O߸ႎ୲
ୟ
0 = FTW٪ഗڦزႜI/O܋܁֡ፕLj܁ൽFTW٪ഗዐڦాඹ(ඍู)ă
1 = FTW٪ഗڦزႜI/O܋܁֡ፕLj܁ൽDDS၎࿋ેഗฉڦํ32࿋ጴă
15:14 ৈሞCFR2[23] = 1ڦ้ᆶၳăยዃ֖ቷጲۯI/O߸ႎ้ۨഗሏႜݴೕഗڦᇨݴೕኵǖ
00 = 1ݴೕ(ඍู)ă
01 = 2ݴೕă
10 = 4ݴೕă
11 = 8ݴೕă
13:12
11 PDCLK๑ీ 0 = PDCLKᆅগ্ᆩLjժഽྺৢༀஇ0Ǘ
ాև้ዓ႑ࡽࣷჄሏႜLjྺຕࣹՊഗ༵ࠃ้Ⴞă
1 = PDCLKᆅগฉׂฉPDCLK႑ࡽ(ඍู)ă
10 PDCLKݒၠ 0 = PDCLKኟႠǗQຕᇑஇ1ᆶ࠲ǗIຕᇑஇ0ᆶ࠲(ඍู)ă
1 = PDCLKݒၠႠă
9 TxEnableݒၠ 0 = ݒၠă
1 = ݒၠă
ୟ 8
7 ჽದ๑ీ 0 = DDSናޗĂ၎࿋ࢅೕ୲ՎࣅཞօᆌᆩӀଚຩႾ(ඍู)ă
1 = DDSናޗĂ၎࿋ࢅೕ୲Վࣅཞօᆌᆩཞօă
AD9910
Rev. B | Page 58 of 64
࿋ ᆅগఁ ௮ຎ
6 ຕࣹՊഗԍାፌࢫኵ ৈሞCFR2[4] = 1้ᆶၳă
0 = ړTxENABLEᆅগྺஇ0้Ljժႜຕ܋ڦຕࣹՊഗഽాևୟ০ྺଭLj
ཞ้ࢮD[15:0] ࢅF[1:0]ᆅগฉڦ႑ࡽ(ඍู)ăᄺ৽ຫLjړTxENABLEྺஇ0้Lj
ժႜຕ܋ฉڦణڦںڦኵྺናޗă
1 =ړTxENABLEᆅগྺஇ1้Ljժႜຕ܋ຕࣹՊഗഽԍٗ
D[15:0]ࢅF[1:0]ᆅগฉڟڦፌࢫኵă
5 ཞօ้Ⴞᄓኤ্ᆩ 0 = SYNC_SMP_ERRᆅগ๑ీLjኸ๖(ߛۉೝᆶၳ)֪ڟཞօஞ؋֑ᄣٱဃă
1 = SYNC_SMP_ERRᆅগഽྺৢༀஇ0ጒༀ(ඍู)ă
4 ժႜຕ܋๑ీ ၘ൧൩֖“ժႜຕ܋ۙఇ๕”ևݴă
0 =ժႜຕ܋ۙࠀీ্ᆩ(ඍู)ă
1 = ժႜຕ܋ۙࠀీ๑ీă
3:0 FMሺᅮ ၘ൧൩֖“ժႜຕ܋ۙఇ๕”ևݴăඍูኵྺ0000bă
ࠀీ٪ഗ3 (CFR3)—ں0x02
ُ٪ഗݴದକ຺߲ጴবă
20. CFR3ڦ࿋ݴದ
31:30 ୟ
DRV0
29:28 REFCLK_OUTᆅগ(ၘ7)Ǘඍูኵྺ00bă
ୟ
VCO SEL
ୟ
Icp
ୟ
72
26:24 ൽREFCLK PLL VCOڦೕ(ၘ8)Ǘඍูኵ111bă
23:22
21:19 ൽREFCLK PLLዐڦۉࢁԭۉୁኵ(ၘ9)Ǘඍูኵ111bă
18:16
15 REFCLKݴೕ୲ഗಖୟ 0 = ൽݴೕഗ(ඍู)ă
1 = ݴೕഗԥಖୟă
14 REFCLKݴೕ୲ഗዘዃB
ୟ
0 = ݴೕഗԥዘዃă
1 =ݴೕഗኟ߾ፕ(ඍู)ă
13:11
10 PFDް࿋ 0 =ኟ߾ፕ(ඍู)ă
1 =၎ഗ্ᆩă
ୟ 9
8 PLL๑ీ
N
0 = REFCLK PLLԥಖୟ(ඍู)ă
1 = REFCLK PLL๑ీă
7:1 ُ7࿋ຕጴREFCLK PLLݒઍݴօഗڦݴೕఇຕLjඍูኵྺ0000000bă
ୟ 0
ޤዺDAC٪ഗ—ں0x03
ُ٪ഗݴದକ຺߲ጴবă
21. DAC٪ഗ࿋ݴದ
ୟ
FSC
31:8
7:0 ُ8࿋ຕጴᆩᇀዷDACଉײۉୁ(֖ޤዺDACևݴ)Ǘඍูኵ0x7Fă
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
AD9910
Rev. B | Page 59 of 64
I/O߸ႎ୲٪ഗ—ں0x04
ُ٪ഗݴದକ຺߲ጴবăُ٪ഗႴI/O߸ႎิၳă
22. I/O߸ႎ୲٪ഗ࿋ݴದ
31:0 I/O߸ႎ୲ ৈሞCFR2[23] = 1ڦ้ᆶၳăُ32࿋ຕጴጲۯ/O߸ႎ୲
(ၘ൧൩֖“ጲۯI/O߸ႎ”ևݴ)Ǘඍูኵ0xFFFFFFFFă
ೕ୲ۙၿጴ٪ഗ(FTW)—ں0x07
ُ٪ഗݴದକ຺߲ጴবă
23. FTW٪ഗ࿋ݴದ
31:0 ೕ୲ۙၿጴ 32࿋ೕ୲ۙၿጴ
၎࿋ೋᅎጴ٪ഗ(POW)—ں0x08
ُ٪ഗݴದକଇ߲ጴবă
24. POW٪ഗ࿋ݴದ
15:0 ၎࿋ೋᅎጴ 16࿋၎࿋ೋᅎጴ
ናޗԲ૩ᅺጱ٪ഗ(ASF)—ں0x09
ُ٪ഗݴದକ຺߲ጴবă
25. ASF٪ഗ࿋ݴದ
31:16 ናޗၽೢ୲ 16࿋ናޗၽೢ୲ኵăৈሞCFR1[9:8] = 11b้ᆶၳǗၘ“ናޗ(OSK)”ևݴă
15:2 ናޗԲ૩ᅺጱ 14࿋ናޗԲ૩ᅺጱă
1:0 ናޗօ ৈሞCFR1[9:8] = 11b้ᆶၳǗၘ“ናޗ(OSK)”ևݴă
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
AD9910
Rev. B | Page 60 of 64
ܠႊೌཞօ٪ഗ—ں0x0A
ُ٪ഗݴದକ຺߲ጴবă
26. ܠႊೌཞօ٪ഗ
31:28 ཞօᄓኤჽ ُ4࿋ຕยዃཞօথഗዐཞօᄓኤఇڦSYSCLKࢅჽSYNC_Inx႑ࡽኮڦ้Ⴞೋၽ
(~150 psሺଉ)ăඍูኵྺ0000bă
27 ཞօথഗ๑ీ 0 = ཞօఇথഗ্ᆩ(ඍู)ă
1 = ཞօ้ዓথഗ๑ీă
26 ཞօ݀ิഗ๑ీ 0 = ཞօ้ዓ݀ิഗ্ᆩ(ඍู)ă
1 = ཞօ้ዓ݀ิഗ๑ీă
ඍูኵྺ00000bă
25 ཞօ݀ิഗႠ 0 = ཞօ้ዓ݀ิഗᇑSYSCLKฉืᄂᅃዂ(ඍู)ă
1 = ཞօ้ዓ݀ิഗᇑSYSCLKူইᄂᅃዂă
24 ୟ
23:18 ཞօጒༀᇨยኵ ُ6࿋ຕጴྺాև้ዓ݀ิഗڟཞօஞ؋้ۨڦጒༀăඍูኵྺ000000bă
17:16 ୟ
15:11 ཞօ݀ิഗჽ ُ5࿋ຕጴยዃཞօ݀ิഗჽ(Ӏ~150 psڦሺଉ)ă
10:8 ୟ
7:3 ཞօথഗჽ ُ5࿋ຕጴยዃཞօথഗჽ(Ӏ~150 psڦሺଉ)ăඍูኵྺ00000bă
2:0 ୟ
ຕጴၽೢ၌ኵ٪ഗ—ں0x0B
ُ٪ഗݴದକӗ߲ጴবăৈሞCFR2[19] = 1ُ้٪ഗᆶၳăၘ“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
27. ຕጴၽೢ၌ኵ٪ഗ࿋ݴದ
63:32 ຕጴၽೢฉ၌ኵ 32࿋ຕጴၽೢฉ၌ኵă
31:0 ຕጴၽೢူ၌ኵ 32࿋ຕጴၽೢူ၌ኵă
ຕጴၽೢօ٪ഗ—ں0x0C
ُ٪ഗݴದକӗ߲ጴবăৈሞCFR2[19] = 1ُ้٪ഗᆶၳăၘ“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
28. ຕጴၽೢ၌ኵօ٪ഗ࿋ݴದ
63:32 ຕጴၽೢڿօ 32࿋ຕጴၽೢڿօኵă
31:0 ຕጴၽೢڿሺօ 32࿋ຕጴၽೢڿሺօኵă
ຕጴၽೢ୲٪ഗĊں1y1E
ُ٪ഗݴದକ຺߲ጴবăৈሞCFR2[19] = 1ُ้٪ഗᆶၳăၘ“ຕጴၽೢ݀ิഗ(DRG)”ևݴă
29. ຕጴၽೢ୲٪ഗ࿋ݴದ
31:16 ຕጴၽೢၽ୲ ُ16࿋ຕጴၽೢၽ୲ኵۨᅭଇ߲ڿኵኮڦ้߰ă
15:0 ຕጴၽೢኟၽ୲ ُ16࿋ຕጴၽೢኟၽ୲ኵۨᅭଇ߲ڿሺኵኮڦ้߰ă
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
AD9910
Rev. B | Page 61 of 64
Prole٪ഗ
Prole 0Prole 7Ljڇೕ٪ഗ—ں0x0Eں0x15
߲٪ഗݴದକӗ߲ጴবă
30. Prole 0Prole 7ڇೕ٪ഗ࿋ݴದ
63:62 ୟ
61:48 ናޗԲ૩ᅺጱ ُ14࿋ຕDDSናޗă
47:32 ၎࿋ೋᅎጴ ُ16࿋ຕDDS၎࿋ೋᅎă
31:0 ೕ୲ۙၿጴ ُ32࿋ຕDDSೕ୲ă
RAM Prole 0RAM Prole 7Lj٪ഗ—ں0x0Eں0x15
߲٪ഗݴದକӗ߲ጴবă
31. Prole 0Prole 7 RAM٪ഗ࿋ݴದ
63:56
55:40 16࿋ںօ୲ኵă
39:30 հႚຐں 10࿋հႚຐںă
29:24 ୟ
23:14 հႚഐ๔ں 10࿋հႚഐ๔ںă
ୟ13:6
5 ݥጂାߛ࿋
ୟ
ںօ୲
ৈሞฉၽೢRAMఇ๕้ᆶၳă
0 = ړRAMጒༀڟٳຐں้Ljዕኹă
1 = ړRAMጒༀڟٳຐں้Ljཌഐ๔ںࢫዕኹă
ୟ4
3 ଭሁ ৈሞRAMఇ๕้ᆶၳLjথገ࣑ă
0 = ଭሁࠀీ্ᆩă
1 = ଭሁࠀీ๑ీă
2:0 RAMఇ๕ ၘ൧൩֖13ă
RAM٪ഗ—ں0x16
RAM٪ഗݴದକ຺߲ጴবă
32. RAM٪ഗ࿋ݴದ
31:0 RAMጴRAM Prole 0RAM Prole 7٪ഗዐڦഐ๔ࢅ
ຐںۨᅭႀRAM٪ഗڦ32࿋ጴ(11024)ă
ഗڦproleࠌ๑ᆩ8߲ჄڦزႜI/Oں(ں0x0Eں
0x015)ăᆶ8߲prole٪ഗݴྺڇೕproleࢅRAM
proleଇዖăړCFR1[31] = 1้RAM proleᆶၳǗړCFR1
[31] = 0LjCFR2[19] = 0ᅜCFR2[4] = 0้Ljڇೕproleᆶ
ၳă
ኟ൧ူLj๑ᆩྔևPROFILE[2:0]ᆅগስᆶၳprole
٪ഗăփࡗLjܔᇀ༹൧LjසࡕCFR1[31] = 1ࢅCFR1
[20:17] ≠ 0000bLjࣷጲۯስᆶၳprole(֖“RAMฉၽೢా
ևProleఇ๕”ևݴ)ă
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
࿋ ᆅগఁ ௮ຎ
AD9910
Rev. B | Page 62 of 64
ྔႚ٫
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
1
25
0562
76
100
75
51
14.00 BSC SQ
16.00 BSC SQ
0.75
0.60
0.45
1.20
MAX
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
0.27
0.22
0.17
0.50 BSC
LEAD PITCH
1
25
2650
00167
75
51
BOTTOM VIEW
(PINS UP)
5.00 SQ
*EXPOSED
PAD
060408-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
59. 100ᆅগࡰಎĂגԋ຺ݛՌೝހጎ[TQFP_EP] (SV-100-4)٫(ڇ࿋ǖࡹ)
۩ࠔኸళ
Model Temperature Range Temperature Range Package Option
AD9910BSVZ1 –40°C+85°C 100ᆅগࡰಎĂגԋ຺ݛՌೝހጎ(TQFP_EP) SV-100-4
AD9910BSVZ-REEL1–40°C+85°C 100ᆅগࡰಎĂגԋ຺ݛՌೝހጎ(TQFP_EP) SV-100-4
AD9910/PCBZ1ೠࠚӱ
1 Z = RoHSඹഗ
AD9910
Rev. B | Page 63 of 64
ጀ
AD9910
Rev. B | Page 64 of 64
ጀ
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