ADRV-DPD1/PCBZ User Guide UG-1238 One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106, U.S.A. * Tel: 781.329.4700 * Fax: 781.461.3113 * www.analog.com ADRV-DPD1/PCBZ Small Cell Radio Reference Design with Digital Predistortion FEATURES GENERAL DESCRIPTION Complete JESD204B to antenna port design with AD9375 DPD and SKY66297-11 PA 2 x 2 LTE 20 MHz, 250 mW output power per antenna, Band 7 FDD Contains transceiver, 2 PAs, 2 LNAs, duplex filters, and dc power solution Power consumption of radio board: approximately 10 W Powered from single 12 V supply Evaluation kit connects to baseband subsystem The ADRV-DPD1/PCBZ is a 24 dBm per path, 2 x 2 multiple input, multiple output (MIMO) radio board, which uses the AD9375, a highly integrated radio frequency (RF) transceiver with integrated digital predistortion (DPD). The radio board is designed to be used with the dual connector interposer board to interface with the EVAL-TPG-ZYNQ3 or other Xilinx(R) or Avnet evaluation boards for the Xilinx ZynqTM-7000 field programmable gate array (FPGA) platform, which has a dual core ARM Cortex(R)-A9 processor running a Linux(R) variant. EVALUATION KIT CONTENTS The AD9375 small cell evaluation software (SCES), AD9375 Small Cell Radio Reference Design Evaluation Software GUI, can configure and control the ADRV-DPD1/PCBZ board. ADRV-DPD1/PCBZ radio board ADRV-INTERPOS1/PCBZ interposer board with clock solution One 8 GB SD card RF adapters between series SMP (F) and SMA (F) 12 V, 60 W ac/dc external desktop (Class I) power supply EQUIPMENT NEEDED EVAL-TPG-ZYNQ3 evaluation board for Xilinx Zynq-7000 FPGA Ethernet cable IEC C13 ac power cable (not included) Note that the Mykonos transceiver evaluation software (MTES) and DPD graphical user interface (GUI) software are not compatible with the ADRV-DPD1/PCBZ. Full specifications on the AD9375 are available in the AD9375 data sheet available from Analog Devices, Inc., and must be consulted in conjunction with this user guide when using the evaluation board. SOFTWARE NEEDED AD9375 Small Cell Radio Reference Design Evaluation Software GUI PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Calibration Tab ................................................................... 35 Evaluation Kit Contents ................................................................... 1 JESD204b Setup Tab .......................................................... 36 Equipment Needed ........................................................................... 1 AGC Tab .............................................................................. 37 Software Needed ............................................................................... 1 GPIO Tabs ........................................................................... 38 General Description ......................................................................... 1 Revision History ............................................................................... 3 Rx Summary, Tx Summary, and ObsRx/Sniffer Summary Tabs .................................................................... 40 ADRV-DPD1/PCBZ Evaluation Kit Photograph ......................... 4 Clock Setup ......................................................................... 41 Getting Started .................................................................................. 5 Programming the Evaluation System .............................. 42 Software Installation .................................................................... 5 Other SCES Features .................................................................. 42 SCES Setup Requirements ........................................................... 5 Device Dropdown Menu ....................................................... 42 SCES Setup .................................................................................... 5 File Dropdown Menu ............................................................ 42 Evaluation Kit Setup..................................................................... 8 Tools Dropdown Menu ......................................................... 45 Hardware Operation ................................................................ 9 Help Dropdown Menu .......................................................... 46 SCES Quickstart ......................................................................... 10 System Status Bar ................................................................... 47 Basic Receiver Setup .............................................................. 10 Receiver Setup ................................................................................. 48 Basic Transmitter Setup ......................................................... 10 Receive Data Options ................................................................ 48 Basic DPD Setup..................................................................... 11 Observation Receiver Signal Chain ......................................... 49 Evaluation Kit Hardware ............................................................... 12 Transmitter Setup ........................................................................... 51 Power Supply Connection ......................................................... 12 Transmit Data Options .............................................................. 52 ADRV-DPD1/PCBZ Top and Bottom View Photographs.... 13 RF Path and DPD Controls ........................................................... 53 Interposer Board Reference ...................................................... 15 Transmitter RF Path Controls .................................................. 53 System Reference Clocks ........................................................... 15 Receiver RF Path Controls ........................................................ 53 LED Indicators ............................................................................ 15 DPD Controls ............................................................................. 54 ADP5054 Enable Jumper........................................................... 16 Scripting ........................................................................................... 55 EEPROM Write Protect Enable Headers ................................ 16 IronPython Script Example ...................................................... 56 Debug Headers............................................................................ 17 Troubleshooting .............................................................................. 58 RF A Header Pins ................................................................... 17 Startup .......................................................................................... 58 RF B Header Pins ................................................................... 17 No LED Activity (Zynq) ........................................................ 58 JTAG Header Pins .................................................................. 18 LEDs Active but SCES Reports that Hardware is Not Connected ............................................................................... 58 SPI Chip Select Lines ................................................................. 18 LED 1 and LED 2 (STATUS 1 and STATUS 0) on Interposer Board Do Not Illuminate After Programming ...................... 58 Pin Configurations and Function Descriptions ......................... 20 Using the Software for Testing ...................................................... 30 Graphical User Interface Operation......................................... 30 Starting the AD9375 SCES ........................................................ 30 Demo Mode ............................................................................ 30 Normal Operation ...................................................................... 32 Software Update ..................................................................... 32 GUI Reference............................................................................. 33 Configuring the AD9375 ...................................................... 33 Configuration Tab .............................................................. 33 Error Handling ........................................................................... 58 Typical Performance ...................................................................... 59 Electrical Specifications ............................................................. 60 Bill of Materials ............................................................................... 61 Interposer Board Schematics ........................................................ 68 Radio Board Schematics ................................................................ 88 Interposer Board PCB Layers ..................................................... 102 Radio Board PCB Layers ............................................................. 110 Interposer Board Connectors and LEDs ................................... 114 Rev. A | Page 2 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 REVISION HISTORY 7/2018--Rev. 0 to Rev. A Updated Format.................................................................. Universal Changes to Features Section and General Description Section ....... 1 Changes to Figure 1 Caption ........................................................... 4 Changed Evaluation Board Software Section to Getting Started Section ................................................................................................ 5 Added Software Installation Section .............................................. 5 Changes to SCES Setup Requirements Section and SCES Setup Section ................................................................................................ 5 Changes to Figure 6 Caption ........................................................... 7 Changed Evaluation Board Hardware Section and Hardware Setup Section to Evaluation Kit Setup Section .............................. 7 Changes to Evaluation Kit Setup ..................................................... 7 Changes to Hardware Operation .................................................... 9 Changes to SCES Quickstart Section and Basic Transmitter Setup Section ..............................................................................................10 Changes to Basic DPD Setup Section ...........................................11 Added Evaluation Kit Hardware Section, Power Supply Connection Section, and Figure 11; Renumbered Sequentially ............................ 12 Added Figure 12, ADRV-DPD1/PCBZ Top and Bottom View Photographs Section, Figure 13 and Figure 14............................13 Added Figure 15 to Figure 18, Table 1, and Table 2; Renumbered Sequentially ......................................................................................14 Added Interposer Board Reference Section, Figure 19, System Reference Clocks Section, Figure 20, LED Indicators Section, and Figure 21 ...........................................................................................15 Added Table 3, ADP5054 Enable Jumper Section, Figure 22, EEPROM Write Protect Enable Headers Section, and Figure 23 ...........................................................................................16 Added Figure 24, Debug Headers Section, RF A Header Pins Section, Figures 25, RF B Header Pins Section, and Figure 26.....17 Added JTAG Header Pins Section, Figure 27, and SPI Chip Select Lines Section ....................................................................................18 Added Table 4 ..................................................................................19 Added Pin Configurations and Function Descriptions Section, Figure 28, and Table 5 .....................................................................20 Added Figure 29 and Table 6 .........................................................23 Added Figure 30, Table 7, and Table 8 ..........................................27 Added Figure 31, Table 9, and Table 10........................................28 Added Figure 32 and Table 11 .......................................................29 Changed AD9375 Small Cell Reference Design Evaluation Software GUI Operation Section to Using the Software for Testing Section .................................................................................30 Added Graphical User Interface Operation Section ...................30 Changes to Figure 33 Caption .......................................................30 Changes to GPIO Tabs Section and Figure 44 Caption .............39 Changed Rx, Tx, and ObsRx/Sniffer Summary Tab Section to Rx Summary, Tx Summary, and ObsRx/Sniffer Summary Tabs Section...............................................................................................40 Changes to Clock Setup Section ....................................................41 Changed Rx Signal Chain Section to Receive Data Options Section...............................................................................................48 Changed Observation Rx Signal Chain Section to Observation Receiver Signal Chain Section .......................................................49 Changes to Observation Receiver Signal Chain Section............49 Changed Transmitter Data Options Section to Transmit Data Options Section ...............................................................................52 Changes to Transmit Data Options Section ................................52 Changes to DPD Controls Section and Figure 62 Caption .......54 Changes to IronPython Script Example Section .........................56 Changed LED 1 and LED 2 on Interposer Board Do Not Light up After Programming Section to LED 1 and LED 2 (STATUS 1 and STATUS 0) on Interposer Board Do Not Illuminate After Programming Section .....................................................................58 Added Typical Performance Section, Figure 66 to Figure 69, and Table 12 to Table 15 .........................................................................59 Added Table 16 to Table 19, Electrical Specifications Section, and Table 20 to Table 21 .................................................................................... 60 Added Bill of Materials Section and Table 22..............................61 Added Table 23 to Table 25 ............................................................64 Added Table 26 and Table 27 .........................................................67 Added Interposer Board Schematics Section and Figure 70 to Figure 97 ...........................................................................................68 Added Radio Board Schematics Section and Figure 88 to Figure 116 .........................................................................................88 Added Interposer Board PCB Layers Section and Figure 117 to Figure 124 ...................................................................................... 102 Added Radio Board PCB Layers Section Figure 125 to Figure 133 ...................................................................................... 110 1/2018--Revision 0: Initial Version Rev. A | Page 3 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide 16493-001 ADRV-DPD1/PCBZ EVALUATION KIT PHOTOGRAPH Figure 1. ADRV-DPD1/PCBZ Evaluation Kit with Radio Board Heatsink Removed Rev. A | Page 4 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 GETTING STARTED SOFTWARE INSTALLATION SCES SETUP The AD9375 SCES, when connected to the evaluation kit, reads the hardware identification data and verifies that the AD9375 Small Cell Radio Reference Design Evaluation Software GUI is connected to the appropriate hardware. After the evaluation hardware is connected, the desired operating parameters can be set up with SCES, and the software can program the reference platform. To install the AD9375 Small Cell Radio Reference Design Evaluation Software GUI, complete the following steps: 2. After the device is configured, the evaluation software can transmit waveforms, observe received waveforms, and initiate correction algorithms. In addition, sequences of application programming interface (API) commands in the form of IronPython scripts can be generated and executed using SCES. 3. SCES SETUP REQUIREMENTS The SCES requires the following: * * * * * An evaluation board for the Xilinx Zynq-7000 system on a chip (SoC) FPGA, such as the EVAL-TPG-ZYNQ3 (not included in the AD9375 evaluation kit). Both the Xilinx EK-Z7-ZC706 Rev 1.2 and Avnet AES-Z7-JESD3-G Rev 1.2 are compatible with the AD9375 evaluation kit. The ADRV-DPD1/PCBZ Small Cell Radio Reference design kit. Operating system of Windows 7 SP1 or later. Free Ethernet port or USB to Ethernet adapter. AD9375 SCES installer, available on the ADRV-DPD1 product page. Administrative privileges on the controlling PC. Figure 2. Run Window for Network Connections 16493-003 * After the software zip folder downloads, copy the software to the target system and unzip the files. The extracted files include an executable file named Small Cell Evaluation Software Vx.x.x.exe. After running the executable file, a standard installation wizard opens. The wizard, by default, installs optional components, including the Microsoft .NET Framework 4.5 (which is mandatory for the software to operate) and IronPython 2.7.4 (which is optional but recommended), as shown in Figure 3. Open the Start > Run window and type ncpa.cpl into the text box, then click OK (see Figure 2). 16493-002 1. Figure 3. Software Installation Components Rev. A | Page 5 of 115 UG-1238 6. * * 7. 8. 9. IP address: 192.168.1.2. Subnet mask: 255.255.255.0. 16493-105 5. Enable the selected device, right click on the device, and click Properties. A window appears, as shown in Figure 5. Double click Internet Protocol Version 4 (TCP/IPv4). Select Use the following IP address: and enter the following values: Click OK at the bottom of the Internet Protocol Version 4 (TCP/IPv4) Properties window, then click OK at the bottom of the Local Area Connection x Properties window (where x is the number of local area network (LAN) devices installed on the computer). Close the Network Connections window. Create an outbound transmission control protocol (TCP). Create an always allow rule for the firewall for Port 22 and Port 55555 in Windows Firewall or other antivirus programs (such as Avast, Norton, AVG, or Sophos), as shown in Figure 6. Steps for creating these rules in Windows Firewall follow. To create an always allow rule in Windows Firewall, open the Start > Run window and type wf.msc into the box. Click OK (see Figure 4). Approve the User Account Control dialog box by clicking Yes. Figure 4. Run Window for Windows Firewall 10. In the Windows Firewall with Advanced Security window, click Outbound Rules in the left pane, and click New Rule... in the right pane. 11. Select the following options in the New Outbound Rule Wizard (see Figure 7). * * * * * Under the Rule Type section, select Port, then click Next >. Under the Protocol and Ports section, click TCP, click Specific remote ports, and enter 22, 555555. Click Next >. Under the Action section, click Allow the connection then click Next >. Under the Profile section, select the Domain, Private, and Public check boxes, and click Next >. Under the Name section, enter SCES in the Name field, then click Finish. 16493-004 4. ADRV-DPD1/PCBZ User Guide Figure 5. Internet Protocol (IP) Settings for Ethernet Device Rev. A | Page 6 of 115 UG-1238 16493-005 ADRV-DPD1/PCBZ User Guide 16493-107 Figure 6. Windows Firewall with Advanced Security Window Figure 7. New Outbound Rule Wizard Window Rev. A | Page 7 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide EVALUATION KIT SETUP 4. The hardware setup is shown in Figure 8. The Xilinx ZC706 Zynq evaluation board, shown in Figure 8 and Figure 9, is an older model of the EVAL-TPG-ZYNQ3, but the two boards are otherwise identical in terms of connections and compatibility. 5. To set up the hardware, complete the following steps: 2. 3. Connect the PC and the EVAL-TPG-ZYNQ3 evaluation board with an Ethernet cable. Ensure that all jumpers on the EVAL-TPG-ZYNQ3 are configured as shown in Figure 9, and Switch 1, Switch 2, and Switch 5 are set to the A position and that SW1 is set as shown in Figure 9. Insert the secure digital (SD) card into the EVAL-TPGZYNQ3 and connect the interposer board to the connectors on the EVAL-TPG-ZYNQ3, and the radio board to the interposer board using the high pin count (HPC) FPGA mezzanine card (FMC) connectors, as shown in Figure 8. Ensure that the connectors are properly aligned. 6. 7. ETHERNET CONNECTION PC RUNNING EVALUATION SOFTWARE REF B CLOCK SOURCE REF A CLOCK SOURCE SIGNAL SYNTHESIZER ANT1 ANT2 SIGNAL ANALYZER SD CARD WITH IMAGE 12V DC POWER SUPPLY 12V DC POWER SUPPLY Figure 8. Hardware Connection Diagram Rev. A | Page 8 of 115 16493-006 1. Ensure that the interposer board Header J16 is set to short the middle two pins, Pin 3 to Pin 4, which is the automatic position (see Figure 133 for the location of these pins). Connect a reference clock signal to the interposer board at J8 (REF_A, default 10 MHz) or J13 (REF_B, default 30.72 MHz). After SCES programs the system, two green light emitting diodes (LEDs) on the interposer board, Status 0 and Status 1, turn on. Lit LEDs indicate that the correct reference clock is provided and the phase locked loops (PLLs) in the AD9528 are locked. The Status 0 LED (PLL1 lock) remains unlit if no reference signal is present. The Status 1 LED (PLL2 lock) is always lit. A suitable input level for the reference signals at J8 or J13 is 380 mVp-p to 1200 mVp-p into 100 (-7 dBm to +3 dBm from a 50 sine wave generator). A square wave is preferred but a sine wave is acceptable. See the System Reference Clocks section for more details Connect the 12 V, 5 A power supply to the EVAL-TPGZYNQ3 at the J22 power input. Connect the 12 V, 5 A radio power supply to the interposer board at J14. ADRV-DPD1/PCBZ User Guide UG-1238 J68 - EXTERNAL Rx TRIGGER J67 - EXTERNAL Tx TRIGGER SW9 - SHUTDOWN SW8 - REBOOT LED L - RF Rx JESD SYNC LED C - RF Sn/Obs Rx JESD SYNC LED R - RF Tx JESD SYNC LED O - FPGA PLLs LOCK SW1 - POWER SWITCH J22 - 12V POWER INPUT 16493-007 GPIO GPIO GPIO GPIO Figure 9. Xilinx ZC706 Zynq Evaluation Board with Jumper Settings and Switch Position Configured to Work with the ADRV-DPD1/PCBZ (Identical to the EVAL-TPG-ZYNQ3) Hardware Operation To operate the evaluation hardware, complete the following steps: The following is the startup sequence that can be observed when booting the evaluation kit: 1. a. 2. Turn on the evaluation system by switching on both 12 V, 5 A power supplies connected to the EVAL-TPG-ZYNQ3 and the interposer board, then switch the EVAL-TPGZYNQ3 power switch, SW1, to the on position. The EVAL-TPG-ZYNQ3 evaluation system uses a Linux operating system. It takes approximately 30 sec before the system is ready for operation and can accept commands from PC software. Boot status can be observed on the EVAL-TPG-ZYNQ3 general-purpose input/output (GPIO) LEDs (L, C, R, and O). Rev. A | Page 9 of 115 b. c. After turning on SW1, all four LEDs are on for approximately 15 sec. During this time, the Linux boot image is copied from the SD card into the FPGA memory. The LEDs begin flashing (moving the single on light), indicating the Linux operating system is starting up. This startup takes another 15 sec. When the LEDs stop flashing, the system is ready for normal operation and awaits connection with the PC over the Ethernet local area network (LAN), which can be established using the SCES. UG-1238 d. ADRV-DPD1/PCBZ User Guide methods prevent corruption of the SD card. The shutdown takes 25 sec. When the EVAL-TPG-ZYNQ3 LEDs blink simultaneously, the user can safely turn off the evaluation system by switching SW1 off (see Figure 9), and turn off the interposer board by switching the power supply off. LED status during normal operation is represented on the EVAL-TPG-ZYNQ3 by the following (see Figure 9): * * e. 3. For receiver testing on the ADRV-DPD1/PCBZ evaluation kit, use a high quality signal generator with low phase noise to provide an input signal to the selected RF input. Use a low loss 50 SMA coaxial cable and keep the cable as short as possible to reduce cable losses and interference pickup from local base stations. The SMA cable attaches the SMA F to SMP F adapter and into either Antenna Connection 1 or Antenna Connection 2 on the radio board. a. b. c. 4. 5. GPIO LED L is the RF receiver (Rx) JESD SYNC. GPIO LED C is the RF sniffer (Sn)/observation (ObsRx) receiver JESD SYNC. * GPIO LED R is the RF transmitter (Tx) JESD SYNC. * GPIO LED O is the FPGA PLLs lock. When shutdown is executed using the SCES, the Linux operating system starts the power-down procedure. The power-down procedure takes a few seconds to finish. All four LEDs blinking simultaneously indicates that the user can safely power off the system using SW1 on the EVAL-TPGZYNQ3, and the power supplies for both boards can be powered down safely. To set the input level near the receiver full scale, it is recommended to set the generator level (for a single tone signal) to approximately -15 dBm. This level depends on the input frequency and the gain settings through the receiver path (see the RF Path and DPD Controls section). Do not apply an input signal to the receiver inputs when performing an initial calibration. The observation receiver input level depends on the transmitter output power and the loss of the RF feedback path. When the transmitter output is transmitting at full power, the observation receiver signal peaks must not reach full scale. For correct DPD operation, reduce the gain if the observation receiver comes close to clipping. The sniffer receivers are not connected on the ADRVDPD1/PCBZ and cannot be used. For transmitter testing, connect a spectrum analyzer to either transmitter output on the ADRV-DPD1/PCBZ. Use a low loss 50 SMA coaxial cable to connect the spectrum analyzer. It is recommended that the power amplifier (PA) be disabled while initial calibrations are running to prevent high power test tones from appearing at the antenna. The SMA cable attaches to the SMA F to SMP F adapter and into either Antenna Connection 1 or Antenna Connection 2 on the radio board. Shutdown must be executed using the SCES software. Alternatively, the user can shut down the Zynq system using the SW9 push button (see Figure 9). These shutdown SCES QUICKSTART After the user follows the steps in the Normal Operation section, the software is fully connected to the device. Complete the following steps to create a basic setup of the different modes. For all basic setups, the attached reference clock must be set by completing the following steps: 1. 2. 3. Connect the reference clock source to SMA Connector A or SMA Connector B on the interposer board with the frequency that matches that of the reference signal. Other frequencies can also be used. If other frequencies are used, attach the reference signal to either clock input. In the evaluation software under the Config tab, select Interposer in the tree diagram on the left under DaughterCard. Select the reference frequency for the attached clock signal on the left and the connector that is connected on the right. Basic Receiver Setup For a basic receiver setup, complete the following steps: 1. 2. 3. 4. 5. 6. In the evaluation software, select AD9375 Radio under the DaughterCard tree in the Config tab and select the Configuration tab. For Rx Chnl, select RX1_RX2. Select an Rx Profile to receive from the signal generator or leave it at the default value. Ensure that the frequency of Rx PLL matches that of the signal generator carrier frequency. Click Program in the menu bar. The programming progress is located in the bottom right of the window. Wait for this progress bar to finish before proceeding to the next step. Click the Receive Data tab (see the Receive Data Options section for more information). Click the Play button in the toolbar. Observe the waveform transmitted from the signal generator output attached to the subminiature push on (SMP) connectors on the radio board. Basic Transmitter Setup For a basic transmitter setup, complete the following steps: 1. 2. 3. Rev. A | Page 10 of 115 In the evaluation software, select AD9375 Radio under the DaughterCard tree in the Config tab and select the Configuration tab. For Tx Chnl, select TX1_TX2. Select a Tx Profile. Any profile is operable, but select a profile that matches the signal received on a spectrum analyzer. Set the Tx PLL frequency to the carrier frequency received at the spectrum analyzer. ADRV-DPD1/PCBZ User Guide 4. UG-1238 Click Program in the menu bar. The programming progress can be seen in the bottom right of the window. Wait for the progress bar to finish before proceeding to the next step. 5. Click the Transmit Data tab (see the Transmitter Setup section and Figure 59 for more information). 6. Load waveforms onto Tx1 and Tx2 with the Load Waveform buttons, labeled Load TX1 and Load TX2. There are several waveforms included with the software. Note that the software scales the waveform to full scale 0 dBFS if Scaling required is selected in the Select a file window. Alternatively, tone parameters can be set to generate basic waveforms. 7. Set the Tx RF attenuation and waveform digital attenuation for each Tx channel. 8. Click Run Cals. This process takes a few seconds and the button becomes clickable again once the process is completed. 9. Click Play in the Transmit Data tab toolbar. After a few seconds, the waveform that is sent to the gain amplifier appears. 10. Switch on the gain amplifier in the RF Control tab for the antenna or antennas that have spectrum analyzers connected to them. 11. Switch on the corresponding power amplifiers for the same antennas. 12. When powering down, power down the amplifiers in reverse order. Then the user can then stop or change the waveform in the Transmit Data tab to avoid sending unwanted power to the spectrum analyzer. Basic DPD Setup For a basic DPD setup, complete the following steps: 1. After following the steps in the Basic Transmitter Setup section, return to the Config tab and ensure that a TxDPD profile is set in the Tx Profile dropdown menu (see Figure 39). 2. In the Calibration tab, enable all the internal transmitter local oscillator leakage (LOL) and quadrature error correction (QEC) options. 3. Click Program to program the device and wait for the programming to complete. 4. Ensure that all the transmitter LOL and QEC tracking options are enabled on the left of the Transmit Data tab. 5. Click Run Cals. This calibration takes a few seconds; the button becomes clickable when calibration is completed. 6. Click the Play button in the Transmit Data toolbar. After a few seconds, the waveform that is being sent to the gain amplifier appears. 7. Switch on the gain amplifier for the antenna or desired antenna ports. 8. Switch on the corresponding power amplifiers for the antenna ports. 9. Click the DPD Control tab. 10. Select the checkboxes for the desired outputs to enable DPD. 11. Click Start DPD (see Figure 62). Note that the adjacent channel leakage drops on the spectrum analyzer. 12. When powering down, disable the DPD by clicking Reset DPD (see Figure 62), and power off the amplifiers in reverse order. The user can then stop or change the waveform in the Transmit Data tab. Rev. A | Page 11 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide EVALUATION KIT HARDWARE This section documents both the interposer board (ADRVINTERPOS1/PCBZ) and the radio board (ADRV-DPD1/PCBZ) reference design. Figure 10 shows the radio board reference design block diagram. The radio board connects to the interposer board, which interfaces the radio board with the EVAL-TPGZYNQ3 for controlling it with the SCES. The interposer board is designed with a Schottky diode to protect against accidental connection of reverse polarity dc power and a transient voltage suppressor (TVS) diode to protect against overvoltage. PA ADL5335 PA_ENABLE Take care to avoid applying voltages below -0.3 V or above +14.5 V. Applying voltages below -0.3 V or above +14.5 V can cause one or more of these protective diode clamps to conduct, resulting in large current flow that could blow the fuse. Prolonged application of reverse voltage or overvoltage at high currents can also damage the protection circuitry or blow the on-board fuse. ANT1 LNA AD9375 PA PA_ENABLE ANT2 LNA 16493-036 ADL5335 distribution when the interposer board is switched on. The J15 and J26 connectors can be used for probing the radio board supply voltages when desired. The other points that can be probed are the not-fitted header Pin J27 and Pin J32. These pins can provide a more accurate reading of the 5.1 V supply, as shown in Figure 72 and Figure 73. Figure 10. AD9375 SCRD Radio Board Receiver and Transmitter RF Paths POWER SUPPLY CONNECTION The universal ac to dc power adaptor included in this evaluation kit requires an IEC C13 cord to connect to the local ac power outlet. The IEC C13 power cord is not included as part of the evaluation kit. The J15 and J26 power terminal connectors are labeled as external 5.1 V input, but the connectors are not necessary to power attached radio boards. This voltage is also not recommended to power the radio board using these connectors because the power is provided from the on-board power Rev. A | Page 12 of 115 16493-211 There are three power supply connectors on the interposer board: J14, J15, and J26. The power for the interposer board typically comes from J14 with a 2-wire CUI PJ-102BH power supply connector at 12 V. The provided universal ac to dc power adaptor is recommended for powering the interposer board. A laboratory power supply can be used if desired. When using a laboratory power supply, it must supply a nominal dc input voltage of 12 V 5% and supply 2.0 A for a single radio board or 3.5 A for two simultaneously connected to the interposer board. The DCPP2 series FC6814671 plug (5.5 mm barrel plug to fit a connector with a 2.5 mm center pin) crimped with 16 AWG wire is recommended for use with a laboratory power supply. Figure 11. 12 V DC Barrel Power Connector ADRV-DPD1/PCBZ User Guide UG-1238 J15 12V DC BARREL CONNECTOR 5.1V TERMINAL BLOCK J14 ADP5054 RF CARD A QUAD BUCK REGULATOR J26 EVAL-TPG-ZYNQ3 INTERPOSER BOARD SYSTEMS 5.1V TERMINAL BLOCK 16493-212 RF CARD B INTERPOSER BOARD Figure 12. Power Supply Diagram 16493-213 16493-214 ADRV-DPD1/PCBZ TOP AND BOTTOM VIEW PHOTOGRAPHS Figure 13. ADRV-DPD1/PCBZ Top View with Heatsink Removed The top side of the ADRV-DPD1/PCBZ interfaces with the heatsink using a thermal gasket. It is possible but not recommended to remove the heatsink by removing three screws on the rear side of the board (as shown in Figure 13). Figure 14. ADRV-DPD1/PCBZ Bottom View The bottom side of the PCB directly interfaces with the interposer board via the SAMTEC 100-way 0.8 mm pitch system connector. For more information, see Table 25. Rev. A | Page 13 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide 88.50 58.30 22.70 4 75.50 22.70 4 40.25 29.50 16493-215 80.50 4 16493-217 4 16.50 83.50 4.30 Figure 15. Mechanical Drawing and Dimensions 16493-216 4.45 1.60 REF 34 Figure 17. 3D CAD Drawing of Reference Design 16493-218 Figure 16. Thermal Gasket and Heatsink Mechanical Drawing Side View Figure 18. 3D CAD Drawing of Reference Design with Heatsink Removed Table 1. LTE Band 7 Configuration1 Frequency Band 7 1 Up-Link (MHz) 2500 to 2570 Frequency Range Down-Link (MHz) 2620 to 2690 Duplex FDD Other LTE bands hardware customizations are available upon request. Table 2. Power Consumption Parameter Total Current Total Power Consumption Total Power Dissipation Min Value Typ Max 2060 2100 Unit mA 10.3 9.8 W W 10.5 10 Test Conditions VDD = 5 V, VDD_IF = 2.5 V, 2T2R, LTE 20 MHz BW, 24 dBm output power (O/P), DPD enabled VDD = 5 V, VDD_IF = 2.5 V, 2T2R, LTE 20 MHz BW, 24 dBm O/P, DPD enabled VDD = 5 V, VDD_IF = 2.5 V, 2T2R, LTE 20 MHz BW, 24 dBm O/P, DPD enabled Rev. A | Page 14 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 16493-219 INTERPOSER BOARD REFERENCE Figure 19. Interposer Board Attached to Radio Board, Heatsink Removed (Top View) SYSTEM REFERENCE CLOCKS Two system reference clock options are available to provide a reference clock input to the AD9528 JESD204B clock generator. Reference A is the default 10.00 MHz input. Reference B is the default 30.72 MHz input. It is recommended to use only one input at a time so that the system operates correctly. The selection of the clock source is modified using the SCES (see the Clock Setup section for more details). CLOCK INPUT REF_B 30.72 MHz Clock input signals are ideally in the form of a square wave input in the range of -7 dBm to +3 dBm, although a sine wave input is also acceptable. In addition, there is an option to fit Resistor R45, Resistor R46, Resistor R52, and Resistor R53 (51 , 0402 size) to the interposer board to give REF_A and REF_B a 50 input impedance. The system reference clock frequencies mentioned previously are default options. However, the hardware is compatible with reference frequencies from 10 MHz to 80 MHz. Consult the product data sheet for further details on AD9528 PLL operation. LED INDICATORS There are eight LED indicators in the interposer to show the status of the board. CLOCK INPUTREF_A 10.00 MHz AD9528 AUXILIARY CLOCK OUT POSITIVE 16493-220 AD9528 AUXILIARY CLOCK OUT NEGATIVE The input impedance on both clock inputs is 1 M dc and 100 ac. Rev. A | Page 15 of 115 16493-221 Figure 20. Reference Clock Inputs and Outputs Figure 21. LED Indicators UG-1238 ADRV-DPD1/PCBZ User Guide Table 3. List of LEDs and Associated Functions LED Order1 1 2 3 4 5 6 7 8 1 LED Name LED 5 LED 8 LED 9 LED 12 LED 11 LED 7 LED 1 LED 2 Color Green Green Green Red Green Green Green Green Function +12 VDC (VIN_DC) present. +3.9 VDC (VCC_3V9) present from ADP5054ACPZ-R7 (SW3). +3.3 VDC (VCC_3V3) present from ADM7154ARDZ-3.3-27. ADP5054 PWRGD output. Illuminates when ADP5054 Channel 1 (VCC_5V1_A) voltage is not correct. +5.1 VDC for RF Module B (VCC_5V1_B). Present from ADP5054ACPZ-R7 (SW2) +5.1 VDC for RF Module A (VCC_5V1_A). Present from ADP5054ACPZ-R7 (SW1). AD9528 STATUS_1 output. Normally programmed as PLL2 lock indicator. AD9528 STATUS_0 output. Normally programmed as PLL1 lock indicator. The order of LEDs here is not sequential to how they are listed on the card. See Figure 21 for order of LEDs. ADP5054 ENABLE JUMPER EEPROM WRITE PROTECT ENABLE HEADERS The ADP5054 enable jumper, labeled J16, is used to select the mode of operation for the ADP5054 power regulator. The modes are as follows: There are two electronical erasable program memory (EEPROM) write protect enable headers provided on the interposer board, one per RF card. These headers enable or disable write operations to the RF calibration data serial peripheral interface (SPI) EEPROM accessible via the SPI bus and located on the RF card. Note that the SPI EEPROM is currently unsupported in the GUI (SCES), API, and interposer board. * * * Always off: ADP5054 is disabled. Automatic: ADP5054 is enabled upon detection of PGOOD signal from EVAL-TPG-ZYNQ3. Always on: ADP5054 is enabled whenever 12 V is present on the dc power connector. 16493-223 For typical operation, place a jumper in the automatic position, shorting Pin 3 and Pin 4. Pin 1 is indicated by a white dot on the board. 16493-222 Figure 23. EEPROM Write Protect Header RF A Figure 22. ADP5054 Enable Jumper Rev. A | Page 16 of 115 UG-1238 16493-225 16493-224 ADRV-DPD1/PCBZ User Guide Figure 24. EEPROM Write Protect Header RF B Placement of the jumper ensures that the write protect line is enabled and write operations to the EEPROM are disabled. Removing the header allows write operations to be carried out on the EEPROM over the SPI interface, controlled from the EVAL-TPG-ZYNQ3. DEBUG HEADERS There are three sets of headers intended as a debug aid to probe signals required for interfacing the RF card and interposer board with the EVAL-TPG-ZYNQ3 platform. The main RF headers have 16-way IDC type connectors that are recommended to be used as protection from shorting pins together accidentally. The 16-way 28 American wire gauge (AWG) ribbon cable can be crimped into these connectors for probing the pins with a logic analyzer or multimeter. A single white dot on the silkscreen indicates Pin 1. Subsequent pins can be then be determined from the schematic in Figure 89. Figure 25. RF A Debug Header Pins RF B Header Pins The headers for RF B are located near the interposer board LEDs, as shown in Figure 26. The RF B signals are accessible on the J1 and J9 connectors. For a complete listing of RF B pin functions and descriptions, see Table 9 and Table 10. RF A Header Pins 16493-226 The RF A headers are located adjacent to where the RF A card fits on the interposer board, as shown in Figure 25. For a complete listing of RF A pin functions and descriptions, see Table 7 and Table 8. Figure 26. RF B Debug Header Pins Rev. A | Page 17 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide JTAG Header Pins SPI CHIP SELECT LINES The JTAG interface can be probed using the JTAG headers (Figure 27) at J7 with a 2 x 10, 20-way, 0.05 inch pitch rectangular connector that is not included in the evaluation kit. The SAMTEC cable assembly with the FFSD-10-S-12.00-01-N part number is recommended for connecting to these header pins. Note that this JTAG cable connector does not fit if the J2 connector is also attached at the J2 header pins. As such, only the J2 connector or the JTAG interface must be connected at any one time. Take care when connectors are removed from header pins because there is a danger of shorting pins. Insulating tape is recommended to cover the J2 headers when the JTAG headers are in use. The chip select (CS) lines from the EVAL-TPG-ZYNQ3 card via the FMC are encoded and are decoded by the CS decoder circuit on the interposer board shown in Figure 82. The chip select codes for each device are detailed in Table 4 with FMC_SPI_CS0 being the least significant bit (LSB) and FMC_SPI_CS4 the most significant bit (MSB). The codes for each chip select are detailed in Table 4. The Selected Chip Acronym column refers to the name written on the schematics in the interposer board schematics section. CS0 to CS2 are the device selects, CS3 is the radio board select, and CS4 is for address space expansion. The clock generator on the interposer board appears as an RF A device. 16493-227 For JTAG boundary scan, refer to the AD9375 System Development User Guide for more information. For a complete list of JTAG pins and descriptions, see Table 11. Figure 27. JTAG Debug Header Pins Rev. A | Page 18 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 Table 4. SPI Encoding Codes Chip Select Code 00000 00001 00010 00011 00100 00101 00110 00111, 01111, 1xxxx 01000 01001 01010 01011 01100 01101 01110 Selected Chip Acronym SPI_DRV1_CS_A SPI_DRV2_CS_A SPI_SPARE_CS2 SPI_EEPROM_CS_A SPI_SPARE_CS0 SPI_PLL_CS SPI_MYK_CS_A NC SPI_DRV1_CS_B SPI_DRV2_CS_B SPI_SPARE_CS3 SPI_EEPROM_CS_B SPI_SPARE_CS1 NC SPI_MYK_CS_B Description Chip select driver amplifier on Tx1 on RF Card A, active low. Chip select driver amplifier on Tx2 on RF Card A, active low. No connect on the ADRV-DPD1/PCBZ. Selects the SPI EEPROM on RF Card A. No connect on the ADRV-DPD1/PCBZ. Selects the AD9528 phase locked loop generator. Selects the transceiver device on the RF A Card. No connect. Chip select driver amplifier on Tx1 on RF Card B, active low. Chip select driver amplifier on Tx2 on RF Card B, active low. No connect on the ADRV-DPD1/PCBZ. Selects the SPI EEPROM on RF Card B. No connect on the ADRV-DPD1/PCBZ. No connect. Selects the transceiver device on the RF B Card. Rev. A | Page 19 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Not all connections are present on the reference design card that are present on the interposer board. These connections are noted in the pin description. 99 100 2 16493-228 1 Figure 28. RF Card Pin Configuration Table 5. RF Card Pin Function Descriptions I/O Voltage RF Pin No. 1, 2, 7, 8, 13, 14, 19, 20, 25, 26, 32, 38, 44, 49, 50, 56, 61, 66, 75, 76, 85, 89, 90, 91, 92 3, 5 Mnemonic GND Type1 GND Description Connected to Ground. SYNCINB1-, SYNCINB1+ I LVDS 4, 6 SERDOUT3-, SERDOUT3+ O 9, 11 SYNCINB0, SYNCINB0+ I 10, 12 SERDOUT1-, SERDOUT1+ O 15, 17 SYSREF_IN-, SYSREF_IN+ I Low Voltage Differential Signaling (LVDS) Sync Signal Associated with Observation Receiver/Sniffer Channel Data on the JESD204B Interface. RF Current Mode Logic (CML) Differential Output 3. This JESD204B lane can be used by the receiver data or by the sniffer/observation receiver data. LVDS Sync Signal Associated with Receiver Channel Data on the JESD204B Interface. RF CML Differential Output 1. This JESD204B lane can be used by receiver data or by sniffer/observation receiver data. LVDS System Reference Clock Inputs for the JESD204B Interface. 16, 18 SERDOUT2-, SERDOUT2+ O CML 21, 23 I 22, 24 DEV_CLK_IN-, DEV_CLK_IN+ SERDOUT0-, SERDOUT0+ RF CML Differential Output 2. This lane can be used by the receiver data or by the sniffer/observation receiver data. Device Clock LVDS Input, AC-Coupled with a 0.10 F Capacitor. CML 27 TX2_ENABLE I 28, 30 SERDIN2-, SERDIN2+ I RF CML Differential Output 0. This JESD204B lane can be used by receiver data or by sniffer/observation receiver data. Enable for Tx2 on the Transceiver Device. On the ADRV-DPD1/PCBZ, this pin is not connected because the TX1_ENABLE pin enables both Tx1 and Tx2 simultaneously. RF CML Differential Input 2. 29 RX2_ENABLE I VDD_IF 31 nPRESENCE RF 33, 35 I 34, 36 TX_DRV1_EN, TX_DRV2_EN SERDIN0-, SERDIN0+ Enable for Rx2 on the Transceiver Device. On the ADRV-DPD1/PCBZ, this pin is not connected because the RX1_ENABLE pin enables both Rx1 and Rx2 simultaneously. Connected to Ground on Radio Board to Indicate Connection to Interposer Board. Enable Line for Tx1 and Tx2 Drivers. This signal is buffered. I RF CML Differential Input 0. CML 37 RX1_RADIO_EN I Enables the Rx1 and Rx2 Signal Paths on the AD9375. VDD_IF 39, 41 I Enables the LNA for Rx1 and Rx2 Signal Paths. These lines are buffered. VDD_IF 40, 42 RX_LNA1_EN, RX_LNA2_EN SERDIN3-, SERDIN3+ I RF CML Differential Input 3. CML 43 TX1_RADIO_EN I Enables the Tx1 and Tx2 Signal Paths on the AD9375. VDD_IF 45, 47 TX_PA1_EN, TX_PA2_EN I Enable the SKY66297-11 PA for Tx1 and Tx2 Independently. VDD_IF 46, 48 SERDIN1-, SERDIN1+ I RF CML Differential Input 1. CML 51 GPIO17 I/O General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. VDD_IF O Rev. A | Page 20 of 115 CML LVDS CML LVDS LVDS VDD_IF CML VDD_IF ADRV-DPD1/PCBZ User Guide RF Pin No. 52, 54 UG-1238 Type1 O 53 Mnemonic SYNCOUTB0-, SYNCOUTB0+ EEPROM_WP I 55 SPI_EEPROM_CS I 57 SPI_DRV2_CS I 58 GPIO11 I/O 59 SPI_DRV1_CS I/O 60 GPIO12 I/O 62 GPIO13 I/O 63 SPI_MYK_CS I 64 GPIO14 I/O 65 SPI_SCLK I 67 SPI_MOSI I/O 68 GPIO15 I/O 69 SPI_MISO O 70 GPIO8 I/O 71 GP_INTERRUPT O 72 GPIO9 I/O 73 RESET I 74 GPIO10 I/O 77 GPIO0 I/O 78 GPIO4 I/O 79 GPIO1 I/O 80 GPIO5 I/O 81 GPIO2 I/O 82 GPIO6 I/O 83 GPIO3 I/O 84 GPIO7 I/O 86 GPIO18 I/O 87 VDD_IF P Description LVDS Sync Signal Associated with Transmitter Channel Data on the JESD204B Interface. Write Protect the SPI EEPROM when Low, Enabled by Jumper on Interposer Board. Select EEPROM for SPI Communication, Active Low. Pull up this pin to 3.3 V when this pin is floating. Select Tx2 Driver for SPI Communication, Active Low. Pull up this pin to 3.3 V when this pin floating. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. Select Tx1 Driver for SPI Communication, Active Low. Pull up this pin to 3.3 V when this pin is floating. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. Chip Select AD9375 (Mykonos) Device for SPI Communication, Active Low. Pull up this pin to VDD_IF when this pin floating. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. Serial Clock for SPI Communication Referenced to VDD_IF. I/O Voltage LVDS GND GND GND VDD_IF GND VDD_IF VDD_IF GND VDD_IF VDD_IF Master Output Slave Input for SPI. This pin is used to write to selected device when device uses 4-wire SPI. Pull up this pin to VDD_IF included. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. Master Input Slave Output for SPI. This pin is used to read from selected device when the device is a 4-wire SPI or as a half-duplex line when the device is a 3-wire SPI. See the SPI Chip Select Lines to understand which chip is selected. Pull up this pin to VDD_IF included. General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. General-Purpose AD9375 Interrupt Signal Output. VDD_IF General-Purpose Input and Output. This pin is not connected on the ADRV-DPD1/PCBZ. Active Low AD9375 Reset. Pull up this pin to VDD_IF included. VDD_IF General-Purpose Input and Output. No pull-up resistor on ADRVDPD/PCBZ. General-Purpose Input and Output. No pull-up resistor on ADRVDPD/PCBZ. General-Purpose Input and Output. Pull-up resistor included on ADRV-DPD1/PCBZ. General-Purpose Input and Output. No pull-up resistor on ADRVDPD/PCBZ. General-Purpose Input and Output. Pull-up resistor included on ADRV-DPD1/PCBZ. General-Purpose Input and Output. No pull-up resistor on ADRVDPD/PCBZ. General-Purpose Input and Output. Pull-up resistor included on ADRV-DPD1/PCBZ. General-Purpose Input and Output. No pull-up resistor on ADRVDPD/PCBZ. General-Purpose Input and Output. Pull-up resistor included on ADRV-DPD1/PCBZ. General-Purpose Input and Output. Pull-up resistor included on ADRV-DPD1/PCBZ. CMOS/LVDS Interface Supply to Radio Board. VDD_IF Rev. A | Page 21 of 115 VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF VDD_IF +2.5 V UG-1238 ADRV-DPD1/PCBZ User Guide RF Pin No. 88 Mnemonic TEST Type1 I Description See AD9375 User Guide for JTAG Boundary Scan. 93 to 100 POWER P 5 V Supply Connection to Power the Board. Pin 100 is used as a sense line on the PAs. 1 P is power, I is input, O is output, I/O is input/output, and GND is ground. Rev. A | Page 22 of 115 I/O Voltage VDD_IF +5 V ADRV-DPD1/PCBZ User Guide UG-1238 The ground connections are not indicated in the pin configuration detailed in Table 6, as all ground connections are marked in the ANSI/VITA 57.1 FPGA mezzanine card (FMC) standard. These connections are also marked in Figure 92, Figure 93, Figure 94, and Figure 95. The FMC HPC connector pin configuration consists of the following interfaces: * JESD204B high speed interface between the host (EVALTPG-ZYNQ3) and radio transceiver (AD9375). A detailed Analog Devices interface specification is provided in the AD9528 data sheet. A subset of the AD9375 GPIOs routed via the interposer. * * * * PA and LNA control lines for transmit and receive operations. SPI interface for AD9375 radio transceiver, as specified in the AD9528 data sheet. SPI interface for EEPROM (ON SEMI CAT25128YI-GT3). The AD9375 system development user guide is available as part of the AD9375 design files zip package. SPI interface for ADL5335 PGA. VDD_IF (2.5 V), CMOS, and LVDS signal power. 3P3AUX (3.3 V) for the interposer board I2C EEPROM, VCC12_P (12 V) is unused on the interposer board. 16493-229 * * K40 Figure 29. 400 Pin FMC HPC Connector, Corner Pins Marked Table 6. FMC HPC Connector Pin Function Descriptions Pin No. A2, A3 A6, A7 A10, A11 A14, A15 A18, A19 A22, A23 A26, A27 A30, A31 A34, A35 A38, A39 B1, B4, B5, B8, B9 B12, B13 B16, B17 B20, B21 B24, B25, B28, B29 B32, B33 EVAL-TPG-ZYNQ3 Mnemonic FMC_HPC_DP1_M2C_P, FMC_HPC_DP1_M2C_N FMC_HPC_DP2_M2C_P, FMC_HPC_DP2_M2C_N FMC_HPC_DP3_M2C_P, FMC_HPC_DP3_M2C_N FMC_HPC_DP4_M2C_P, FMC_HPC_DP4_M2C_N FMC_HPC_DP5_M2C_P, FMC_HPC_DP5_M2C_N FMC_HPC_DP1_C2M_P, FMC_HPC_DP1_C2M_N FMC_HPC_DP2_C2M_P, FMC_HPC_DP2_C2M_N FMC_HPC_DP3_C2M_P, FMC_HPC_DP3_C2M_N FMC_HPC_DP4_C2M_P, FMC_HPC_DP4_C2M_N FMC_HPC_DP5_C2M_P, FMC_HPC_DP5_C2M_N NC FMC_HPC_DP7_M2C_P, FMC_HPC_DP7_M2C_N FMC_HPC_DP6_M2C_P, FMC_HPC_DP6_M2C_N FMC_HPC_GBTCLK1_M2C_P, FMC_HPC_GBTCLK1_M2C_N NC FMC_HPC_DP7_C2M_P, FMC_HPC_DP7_C2M_N Interposer Board Mnemonic SERDOUT0_A+, SERDOUT0_A- SERDOUT1_A+, SERDOUT1_A- SERDOUT3_A+, SERDOUT3_A- SERDOUT0_B+, SERDOUT0_B- SERDOUT1_B+, SERDOUT1_B- SERDIN3_A+, SERDIN3_A- SERDIN0_A+, SERDIN0_A- SERDIN2_A+, SERDIN2_A- SERDIN0_B+, SERDIN0_B- SERDIN1_B+, SERDIN1_B- NC SERDOUT2_B+, SERDOUT2_B- SERDOUT3_B+, SERDOUT3_B- FPGA_REF_CLK_A+, FPGA_REF_CLK_A- NC SERDIN2_B+, SERDIN2_B- Rev. A | Page 23 of 115 Description JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card A. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card A. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card A. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card B. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card B. JESD204B Serial Data From RF Card A to EVAL-TPG-ZYNQ3. JESD204B Serial Data From RF Card A to EVAL-TPG-ZYNQ3. JESD204B Serial Data From RF Card A to EVAL-TPG-ZYNQ3. JESD204B Serial Data From RF Card B to EVAL-TPG-ZYNQ3. JESD204B Serial Data From RF Card B to EVAL-TPG-ZYNQ3. No Connect. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card B. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card B. Reference Clock A from AD9528 to FPGA. No Connect. JESD204B Serial Data From RF Card B to EVAL-TPG-ZYNQ3. UG-1238 Pin No. B36, B37 ADRV-DPD1/PCBZ User Guide EVAL-TPG-ZYNQ3 Mnemonic FMC_HPC_DP6_C2M_P, FMC_HPC_DP6_C2M_N NC FMC_HPC_DP0_C2M_P, FMC_HPC_DP0_C2M_N FMC_HPC_DP0_M2C_P, FMC_HPC_DP0_M2C_N FMC_HPC_LA06_P, FMC_HPC_LA06_N FMC_HPC_LA10_P, FMC_HPC_LA10_N FMC_HPC_LA14_P, FMC_HPC_LA14_N FMC_HPC_LA18_CC_P, FMC_HPC_LA18_CC_N FMC_HPC_LA27_P, FMC_HPC_LA27_N Interposer Board Mnemonic SERDIN3_B+, SERDIN3_B- NC SERDIN1_A+, SERDIN1_A- SERDOUT2_A+, SERDOUT2_A- FMC_TX1_DRV_EN_A, FMC_TX2_DRV_EN_A FMC_SPI_CS3, FMC_SPI_CS4 FMC_TX2_ENABLE_A, FMC_RX2_ENABLE_A GPIO6_A, GPIO7_A Description JESD204B Serial Data From RF Card B to EVAL-TPG-ZYNQ3. No Connect. JESD204B Serial Data From RF Card A to EVAL-TPG-ZYNQ3. JESD204B Serial Data From EVAL-TPGZYNQ3 to RF Card A. Tx1 and Tx2 Driver Amplifier Enable for RF Card A, Prebuffer. SPI Chip Select Multiplex Bits from EVALTPG-ZYNQ3 to Interposer Board. Tx2 and Rx2 Enable on RF Card A Transceiver Device. General-Purpose Input and Output. FMC_TDD1_SWITCH_A, FMC_TDD2_SWITCH_A C30 C31 C34 C35, C37 C39 D1 FMC_HPC_IIC_SCL FMC_HPC_IIC_SDA GA0 VCC12_P VCC3V3 PWRCTL1_FMC_PG_C2M FMC_I2C_SCL FMC_I2C_SDA EEPROM_A0 FMCA_VCC_12P0V 3P3V ADP5054_EN D4, D5 FMC_HPC_GBTCLK0_M2C_P, FMC_HPC_GBTCLK0_M2C_N FMC_HPC_LA01_CC_P, FMC_HPC_LA01_CC_N FMC_HPC_LA05_P FPGA_REF_CLK_B+, FPGA_REF_CLK_B- SYSREF_FROM_FPGA+, SYSREF_FROM_FPGA- FMC_TEST Time Division Duplex 1 and Duplex 2 Switch on RF Card A. No connect on Rev A interposer board 100-pin connector, prebuffer. I2C Interface Clock. I2C Interface Data. I2C EEPROM Address Bit 0. 12 V from EVAL-TPG-ZYNQ3 Card. 3.3 V from EVAL-TPG-ZYNQ3 Card. ADP5054 Enabled Signal from Interposer Board to EVAL-TPG-ZYNQ3. Reference Clock B from AD9528 to FPGA. FMC_HPC_LA05_N FMC_HPC_LA09_P, FMC_HPC_LA09_N FMC_HPC_LA13_P, FMC_HPC_LA17_CC_P, FMC_HPC_LA13_N, FMC_HPC_LA17_CC_N FMC_HPC_LA23_P, FMC_HPC_LA23_N FMC_HPC_LA26_P FMC_HPC_LA26_N FMC_HPC_TCK_BUF FMC_TDI_BUF FMC_HPC_TDO_FMC_LPC_TDI 3P3AUX FMC_HPC_TMS_BUF NC GA1 VCC3V3 NC NC NC GPIO18_A FMC_SPI_CS0, FMC_SPI_CS1 FMC_TX1_ENABLE_A, FMC_TX2_ENABLE_B, FMC_RX1_ENABLE_A, FMC_RX2_ENABLE_B FMC_RX1_LNA_ENABLE_A, FMC_RX2_LNA_ENABLE_A FMC_CLK_RESET FMC_CLK_SYSREF_REQUEST NC JTAG_TDI JTAG_TDO 3P3VAUX NC NC EEPROM_A1 3P3V NC NC GPIO10_A, GPIO11_A, GPIO16_A, GPIO17_A, GPIO13_B, GPIO14_B B40 C2, C3 C6, C7 C10, C11 C14, C15 C18, C19 C22, C23 C26, C27 D8, D9 D11 D12 D14, D15 D17, D20, D18, D21 D23, D24 D26 D27 D29 D30 D31 D32 D33 D34 D35 D36, D38, D40 E2, E3 E3 E6, E7, E9, E10, E12, E13 Rev. A | Page 24 of 115 SYSREF from EVAL-TPG-ZYNQ3 to AD9528 on Interposer Board. JTAG Test Signal from EVAL-TPG-ZYNQ3 to Interposer Board. General-Purpose Input and Output. SPI Chip Select Multiplex Bits from EVALTPG-ZYNQ3 to Interposer Board. Tx1, Tx2, Rx1, and Rx2 Enable to the Indicated RF Card Transceiver Device. Rx1 and Rx2 Low Noise Amplifier Enable on RF Card A, Postbuffer. Reset Signal to AD9528, Prebuffer. SYSREF Request Signal to AD9528, Prebuffer. No Connect on the Interposer Board. Loopback to the JTAG_TDO Pin. Loopback to the JTAG_TDI Pin. 3.3 V from EVAL-TPG-ZYNQ3 Card. No Connect on Interposer Board. No Connect. I2C EEPROM Address Bit 1. 3.3 V from EVAL-TPG-ZYNQ3 Card. No Connect. No Connect. General-Purpose Input and Output. These pins are not connected on the EVAL-TPGZYNQ3. ADRV-DPD1/PCBZ User Guide UG-1238 Pin No. E15, E16, E18, E19, E21, E22, E24, E25, E27, E28, E30, E31, E33, E34, E36, E37 E39, F40, G39, H40 EVAL-TPG-ZYNQ3 Mnemonic NC Interposer Board Mnemonic NC Description No Connect. VADJ FMC_VDD_IF F1 F4, F5 F7, F8, F10, F11, F13, F14, F16, F17 FMC_HPC_PG_M2C NC NC F19, F20, F22, F23, F25, F26, F28, F29, F31, F32, F34, F35, F37, F38 G2, G3 NC 3P3V NC GPIO8_A, GPIO9_A, GPIO14_A, GPIO15_A, GPIO11_B, GPIO12_B, GPIO16_B, GPIO17_B NC LVDS Supply on EVAL-TPG-ZYNQ3 and CMOS Digital Power Supply for the Radio Board and Interposer Board. 3.3 V from EVAL-TPG-ZYNQ3 Card. No Connect. General-Purpose Input and Output. No connect on the EVAL-TPG-ZYNQ3. No Connect. NC No Connect on Interposer Board. FPGA_SYSREF+, FPGA_SYSREF- SYNCINB0_A+, SYNCINB0_A- FMC_SPI_MISO SYSREF from Interposer Board to EVALTPG-ZYNQ3. JESD204B SYNCIN Signal to RF Card A. G12 FMC_HPC_CLK1_M2C_P, FMC_HPC_CLK1_M2C_N FMC_HPC_LA00_CC_P, FMC_HPC_LA00_CC_N FMC_HPC_LA03_P, FMC_HPC_LA03_N FMC_HPC_LA08_P G13 FMC_HPC_LA08_N FMC_SPI_CS2 G15, G16 FMC_HPC_LA12_P, FMC_HPC_LA12_N FMC_HPC_LA16_P, FMC_HPC_LA16_N, FMC_HPC_LA20_P, FMC_HPC_LA20_N, FMC_HPC_LA22_P, FMC_HPC_LA22_N FMC_HPC_LA25_P, FMC_HPC_LA25_N FMC_HPC_LA29_P, FMC_HPC_LA29_N FMC_HPC_LA31_P, FMC_HPC_LA31_N FMC_HPC_LA33_P, FMC_HPC_LA33_N NC FMC_HPC_PRSNT_M2C_B FMC_TX1_ENABLE_B, FMC_RX1_ENABLE_B GPIO2_A, GPIO3_A, GPIO4_B, GPIO5_B, GPIO0_B, GPIO1_B SYNCINB1_A+, SYNCINB1_A- GPIO6_B, GPIO7_B NC H10 FMC_HPC_CLK0_M2C_P, FMC_HPC_CLK0_M2C_N FMC_HPC_LA02_P, FMC_HPC_LA02_N FMC_HPC_LA04_P H11 FMC_HPC_LA04_N FMC_GP_INTERRUPT_A H13 FMC_HPC_LA07_P FMC_SPI_CLK H14 FMC_HPC_LA07_N FMC_SPI_MOSI G6, G7 G9, G10 G18, G19, G21, G22, G24, G25 G27, G28 G30, G31 G33, G34 G36, G37 H1 H2 H4, H5 H7, H8 SYNCINB1_B+, SYNCINB1_B- FMC_TX1_PA_ENABLE_B, FMC_TX2_PA_ENABLE_B NC FMC_RF_PRESENCE SYNCOUTB0_A+, SYNCOUTB0_A- FMC_RESET_A Rev. A | Page 25 of 115 SPI Data from EVAL-TPG-ZYNQ3 to Chip Selected. Also half duplex line for some devices, prebuffer. SPI Chip Select Multiplex Bits from EVALTPG-ZYNQ3 to Interposer Board. Tx1 and Rx1 Enable on RF Card B Transceiver Device, Prebuffer. General-Purpose Input and Output. JESD204B SYNCIN signal to RF Card A. General-Purpose Input and Output. JESD204B SYNCIN Signal to RF Card B. Tx1 and Tx2 Power Amplifier Enable on RF Card B, Prebuffer. No Connect. Active Low Presence Signal from Radio Board. No Connect on Interposer Board. JESD204B SYNCOUT Signal to RF Card A. Reset Signal to Transceiver Device on RF Card A, Prebuffer. General-Purpose Interrupt from the Transceiver Device on RF card A, Postbuffer. SPI Clock Signal from EVAL-TPG-ZYNQ3 to Selected Chip. SPI Data from Chip Selected to EVAL-TPGZYNQ3, Prebuffer. UG-1238 Pin No. H16, H17 ADRV-DPD1/PCBZ User Guide EVAL-TPG-ZYNQ3 Mnemonic FMC_HPC_LA11_P, FMC_HPC_LA11_N FMC_HPC_LA15_P, FMC_HPC_LA15_N, FMC_HPC_LA19_P, FMC_HPC_LA19_N, FMC_HPC_LA21_P, FMC_HPC_LA21_N FMC_HPC_LA24_P, FMC_HPC_LA24_N FMC_HPC_LA28_P, FMC_HPC_LA28_N FMC_HPC_LA30_P, FMC_HPC_LA30_N FMC_HPC_LA32_P, FMC_HPC_LA32_N NC NC Interposer Board Mnemonic SYNCOUTB0_B+, SYNCOUTB0_B- GPIO0_A, GPIO1_A, GPIO2_A, GPIO3_A, GPIO4_A, GPIO5_A FMC_TX1_PA_ENABLE_A, FMC_TX2_PA_ENABLE_A FMC_RX1_LNA_ENABLE_B, FMC_RX2_LNA_ENABLE_B SYNCINB0_B+, SYNCINB0_B- FMC_TX1_DRV_EN_B, FMC_TX2_DRV_EN_B NC FMC_TDD1_SWITCH_B, FMC_TDD2_SWITCH_B J9, J10, J12, J13, J15 NC J16, J18, J19, J21, J22, J24, J25, J27, J28, J30, J31, J33, J34, J36, J37, J39, K1, K4, K5 K7, K8 NC GPIO12_A, GPIO13_A, GPIO9_B, GPIO10_B, GPIO18_B NC K10 NC FMC_RF_PRESENCE_A, FMC_RF_PRESENCE_B FMC_RESET_B K11 NC FMC_GP_INTERRUPT_B K13, K14 NC GPIO8_B, GPIO15_B K16, K17, K19, K20, K22, K23, K25, K26, K28, K29, K31, K32, K34, K35, K37, K38, K40 NC NC H19, H20, H22, H23, H25, H26 H28, H29 H31, H32 H34, H35 H37, H38 J2, J3 J6, J7 NC Rev. A | Page 26 of 115 Description JESD204B SYNCOUT Signal to RF Card B. General-Purpose Input and Output. Tx1 and Tx2 Power Amplifier Enable on RF Card A, Prebuffer. Rx1 and Rx2 Low Noise Amplifier Enable on RF Card B, Postbuffer. JESD204B SYNCIN Signal to RF Card B. Tx1 and Tx2 Driver Amplifier Enable for RF Card B, Prebuffer. No Connect. Time Division Duplex 1 and Duplex 2 Switch on RF Card B. Not connected on Rev. A interposer board 100-pin connector, prebuffer. General-Purpose Input and Output. Not connected on the EVAL-TPG-ZYNQ3. No Connect. Presence Signal from RF Card Indicated, Active Low. Reset Signal to Transceiver Device on RF Card B, Prebuffer. General-Purpose Interrupt from the Transceiver Device on RF Card B, Postbuffer. Not connected on EVAL-TPG-ZYNQ3. General-Purpose Input and Output. Not connected on the EVAL-TPG-ZYNQ3. No Connect. ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF J10 1 2 TX1_DRV_EN_A 3 4 TX2_DRV_EN_A 5 6 FMC_SPI_CLK 7 8 9 10 11 12 13 14 15 16 FMC_SPI_MISO FMC_SPI_MOSI ISENSE_5V1_A NC SPI_DRV1_CS_A SPI_DRV2_CS_A SPI_MOSI SPI_MISO SPI_CLK FMC_RESET_A TEST_A VDD_IF J2 RX1_ENABLE_A RX2_ENABLE_A GPIO0_A GPIO1_A GPIO2_A GPIO3_A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TX1_ENABLE_A TX2_ENABLE_A RX1_LNA_ENABLE_A RX2_LNA_ENABLE_A TX1_PA_ENABLE_A TX2_PA_ENABLE_A TDD1_SWITCH_A 16493-230 TDD2_SWITCH_A 1 Figure 30. RF A J10 and J2 Debug Headers Pin Configuration Table 7. J10 Debug Headers Pin Function Descriptions Pin No. 1 2, 4 6 7 8 9 10 11 12 13 14 Mnemonic VDD_IF SPI_DRV1_CS_A, SPI_DRV2_CS_A TX1_DRV_EN_A, TX2_DRV_EN_A SPI_MOSI FMC_SPI_CLK SPI_MISO FMC_SPI_MISO SPI_CLK FMC_SPI_MOSI FMC_RESET_A NC TEST_A 15 16 ISENSE_5V1_A GND 3, 5 Description CMOS and LVDS Supply, 2.5 V Nominal. Low Indicates Tx1 and Tx2 Driver is Selected for SPI Communication on RF Card A. Tx1 and Tx2 Driver on RF Card A Enabled when High. SPI Master Out Slave In Signal from EVAL-TPG-ZYNQ3 Postbuffer. SPI Clock Signal from EVAL-TPG-ZYNQ3 Prebuffer. SPI Master In Slave Out Signal from Device Selected for SPI Communication Prebuffer. SPI Master In Slave Out Signal from Device Selected for SPI communication Postbuffer. SPI Clock Signal from EVAL-TPG-ZYNQ3 Postbuffer. SPI Master Out Slave In Signal from EVAL-TPG-ZYNQ3 Prebuffer. Transceiver Device Reset Signal Active Low for RF Board A Prebuffer. No Connect. Used for JTAG Boundary Scan. If the JTAG boundary scan is desired, an 0402 size 0 resistor must be soldered to the solder pads labeled R129. TEST_A then yields a buffered output of FMC_TEST. Otherwise, this pin can be left floating. Output of AD8211 Current Shunt Monitor for RF Card A. Connected to Ground. Table 8. J2 Debug Headers Pin Function Descriptions Pin No. 1 2, 4 3, 5 6, 8 7, 9, 11, 13 10, 12 14, 15 16 Mnemonic VDD_IF TX1_ENABLE_A, TX2_ENABLE_A RX1_ENABLE_A, RX2_ENABLE_A RX1_LNA_ENABLE_A, RX2_LNA_ENABLE_A GPIO0_A, GPIO1_A, GPIO2_A, GPIO3_A TX1_PA_ENABLE_A, TX2_PA_ENABLE_A TDD1_SWITCH_A, TDD2_SWITCH_A GND Description CMOS and LVDS Supply, 2.5 V Nominal. Enable Signal to the Transceiver Device on RF Card A for Tx1 and Tx2. Enable Signal to the Transceiver Device on RF Card A for Rx1 and Rx2. Enable Signal to the LNA on RF Card A for Rx1 and Rx2. General-Purpose Input and Output Monitoring for RF Card A. Enable Signal to the PA on RF Card A for Tx1 and Tx2. Time Division Duplex Switch to RF Card A. Not connected on ADRV-DPD1 RF card. Connected to Ground. Rev. A | Page 27 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide VDD_IF J1 TX2_DRV_EN_B FMC_SPI_CS0 FMC_SPI_CS1 FMC_SPI_CS2 FMC_SPI_CS3 FMC_SPI_CS4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TX1_DRV_EN_B SPI_DRV1_CS_B SPI_DRV2_CS_B FMC_I2C_SDA FMC_I2C_SCL FMC_RESET_B TEST_B ISENSE_5V1_B VDD_IF J9 RX1_ENABLE_B RX2_ENABLE_B GPIO0_B GPIO1_B GPIO2_B GPIO3_B 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TX1_ENABLE_B TX2_ENABLE_B RX1_LNA_ENABLE_B RX2_LNA_ENABLE_B TX1_PA_ENABLE_B TX2_PA_ENABLE_B TDD1_SWITCH_B 16493-231 TDD2_SWITCH_B 1 Figure 31. RF B J1 and J9 Debug Headers Pin Configuration Table 9. J1 Debug Header Pin Function Descriptions Pin No. 1 2, 3 4, 6 5, 7, 9, 11, 13 8, 10 12 14 Mnemonic VDD_IF TX1_DRV_EN_B, TX2_DRV_EN_B SPI_DRV1_CS_B, SPI_DRV2_CS_B FMC_SPI_CS0, FMC_SPI_CS1, FMC_SPI_CS2, FMC_SPI_CS3, FMC_SPI_CS4 FMC_I2C_SDA, FMC_I2C_SCL FMC_RESET_B TEST_B 15 16 ISENSE_5V1_B GND Description CMOS and LVDS Supply, 2.5 V Nominal. Tx1 and Tx2 Driver on RF Card B Enabled when High. Low Indicates Tx1 and Tx2 Driver is Selected for SPI Communication on RF Card B. Serial Peripheral Interface Encoded Bit, see SPI Chip Select Lines for Code Table. I2C Serial Data and Clock Line from EVAL-TPG-ZYNQ3. Transceiver Device Reset Signal Active Low for RF Card B Prebuffer. Used for JTAG Boundary Scan. To perform a JTAG boundary scan, an 0402 size 0 resistor must be soldered to solder pads labeled R89. This pin is then a buffered output of FMC_TEST. Otherwise, this pin can be left floating. Output of AD8211 Current Shunt Monitor for RF Card B. Connected to Ground. Table 10. J9 Debug Header Pin Function Descriptions Pin No. 1 2, 4 3, 5 6, 8 7, 9, 11, 13 10, 12 14, 15 16 Mnemonic VDD_IF TX1_ENABLE_B, TX2_ENABLE_B RX1_ENABLE_B, RX2_ENABLE_B RX1_LNA_ENABLE_B, RX2_LNA_ENABLE_B GPIO0_B, GPIO1_B, GPIO2_B, GPIO3_B TX1_PA_ENABLE_B, TX2_PA_ENABLE_B TDD1_SWITCH_B, TDD1_SWITCH_B GND Description CMOS and LVDS Supply, 2.5 V Nominal. Enable Signal to the Transceiver Device on RF Card B for Tx1 and Tx2. Enable Signal to the Transceiver Device on RF Card B for Rx1 and Rx2. Enable Signal to the LNA on RF Card B for Rx1 and Rx2. General-Purpose Input and Output Monitoring for RF Card B. Enable Signal to the PA on RF Card B for Tx1 and Tx2. Time Division Duplex Switch to RF Card B. Not connected on ADRV-DPD1 RF card. Connected to Ground. Rev. A | Page 28 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF JTAG J7 1 2 TMS 3 4 TCLK 5 6 TDO 7 8 TDI 9 10 11 12 13 14 15 16 17 18 19 20 TRST GPIO7_A GPIO18_A GPIO5_A GPIO6_A GPIO4_A 16493-232 R127 51k Figure 32. JTAG Pin Configuration Table 11. JTAG Debug Header Pin Function Descriptions Pin No. 1 2 3, 5, 9, 15, 17, 19 4 6 7, 10 to 14, 18, 20 8 16 1 Mnemonic VDD_IF TMS GND TCLK TDO NC TDI TRST Type1 O O GND O O NC O O Description CMOS and LVDS supply, 2.5 V nominal. JTAG test mode select line, connected to GPIO 7 on RF card A. Connected to ground. JTAG test clock line, connected to GPIO 18 on RF card A. JTAG test data out line, connected to GPIO 5 on RF card A. Not connected, this pin can be left floating. JTAG test data in line, connected to GPIO 6 on RF card A. JTAG test reset active low. O is the output from the header pins. GND is ground. NC is no connect. Rev. A | Page 29 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide USING THE SOFTWARE FOR TESTING The GUI is the controller of the ADRV-DPD1/PCBZ and interposer board. It controls the connection to the EVAL-TPGZYNQ3 and interfaces with the ADRV-DPD1/PCBZ through the EVAL-TPG-ZYNQ3. 1. Connect to the EVAL-TPG-ZYNQ3 by clicking Connect from the graphical user interface (GUI) menu. Once connected, the hardware tree pane on the left side of the window updates with the radio board and the interposer board, shown in Figure 37. 2. When connecting to the EVAL-TPG-ZYNQ3 for the first time, the user must update the device platform files by clicking Device > Update > Platform Files. 3. Select the interposer board from the hardware tree pane, and from the Ref Clock Setup tab (see Figure 46), select the desired reference clock. 4. Select the radio board from the hardware tree view and from the Config tab, select the desired radio configuration. 5. Use the other configuration tab (see the Configuring the AD9375 section) for the radio board to set up the desired configuration. 6. When all the configuration tabs are completed as desired, click Program in the menu bar to configure the ADRV-DPD1/PCBZ and ADRV-INTERPOS1/PCBZ evaluation kit. 7. The AD9375 is in radio on mode. 8. In transmit mode, the user can load data to send via the Transmit Data tab from the system tabs. Test waveform data can be loaded from a file, or the built-in tone generator tool (see Figure 60) can be used to generate data. Click Play to send the waveform data to the transmit. 9. Use the RF Controls tab from the system tabs to configure the transmit RF path from the AD9375 to the antenna connectors. 10. In receive mode, the Receive Data tab can observe data received by the AD9375. Use the RF Controls tab from the system tabs to enable or disable the low noise amplifiers (LNAs) in the receive RF path from the antenna connectors to the AD9375. 11. Use the DPD Control tab from the system tabs to enable or disable DPD adaptation on the transmit paths. STARTING THE AD9375 SCES Start the GUI by clicking Start > All Programs > Analog Devices > Small Cell Evaluation Software > Small Cell Evaluation Software. Figure 34 shows the opening page of the SCES after it is activated. Demo Mode Figure 35 shows the opening page of the SCES when the evaluation hardware is not connected. The user can use the software in demo mode by completing the following steps: 1. 2. Click Connect in the top left corner of the window. Click OK in the Zynq Not connected error box (see Figure 33). 3. After clicking OK, the software progresses into demo mode, in which a superset of all features is displayed. 16493-110 GRAPHICAL USER INTERFACE OPERATION Figure 33. Zynq Not connected Window Connection status is indicated at the bottom of the software window titled Zynq Platform. When the status display reads Disconnected, the SCES is operating in demo mode. Demo mode is a generic limited version of the software that provides an overview of the transceiver features and evaluation software. Demo mode does not support some features that are specific to the ADRV-DPD1/PCBZ. Rev. A | Page 30 of 115 UG-1238 16493-009 ADRV-DPD1/PCBZ User Guide 16493-010 Figure 34. ADRV-DPD1/PCBZ SCES Opening Page Figure 35. SCES Demo Mode Rev. A | Page 31 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide NORMAL OPERATION The user can click the DaughterCard option in the device tree, shown in Figure 37. After selecting DaughterCard, information about revisions of different setup blocks appears in the main window. The bottom of that window shows the TCP IP address, set to 192.168.1.10, and the port number, set to 55555. Figure 36 shows an example of the correct connection between a PC and a Zynq system with a daughter card connected to it. 16493-012 When the hardware is connected to a PC and the user wants to use the complete evaluation system, SCES establishes a connection to the Zynq system via the Ethernet cable after the user clicks Connect. When a proper connection is established, the software identifies the hardware connected. The software exits demo mode and enters small cell evaluation system connected mode. The daughter card device tree updates and shows the connected radio board and interposer board. Figure 36. Correct PC Zynq Connection with Daughter Card Software Update Typically, when installing an SCES update, the user is also required to update the platform files. The user can perform a platform files update by clicking Device > Update > Platform Files. SCES automatically updates files on the EVAL-TPGZYNQ3 SD card and reboots the ADRV-DPD1/PCBZ system. When all updates are installed, the system is ready for normal operation. 16493-011 Full version details of the software and hardware can be retrieved by clicking Help > About in the SCES menu. Figure 37. Project Setup Page of the ADRV-DPD1/PCBZ Software Rev. A | Page 32 of 115 UG-1238 16493-013 ADRV-DPD1/PCBZ User Guide Figure 38. Checking the Full Version Details of the Hardware and Software GUI REFERENCE The following sections outline all the options within the pages and tabs of the SCES for user reference. Configuring the AD9375 The SCES contains four main user configurable tabs (see Figure 39, Figure 40, Figure 41, and Figure 46). After the user selects AD9375 Radio Card in the device tree, the Config tab appears. Contained within this tab are nine subtabs that contain setup options for the device. The small cell reference design (SCRD) radio has frequencyselective components in the RF paths. The LO frequencies chosen and the RF signal bandwidths used to contain the RF signal entirely within the specified operating bandwidth. For third generation partnership project long-term evolution (3GPP LTE) Band 7 radio boards, the usable transmitter range for a 20 MHz signal bandwidth is 2630 MHz to 2680 MHz, as the Band 7 specification is 2620 MHz to 2690 MHz. Configuration Tab The first tab displayed is the Configuration tab. When this tab is selected, the initial screen appears, shown in Figure 39, and the user can select the following: * * * * * * The device clock frequency The number of active receive channels The number of active transmit channels The observation/sniffer input Profiles for receiver, transmitter, observation receiver, and sniffer receiver Receiver, transmitter, and sniffer receiver/observation receiver local oscillator (LO) frequency Rev. A | Page 33 of 115 ADRV-DPD1/PCBZ User Guide 16493-014 UG-1238 Figure 39. Configuration Tab Rev. A | Page 34 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 Calibration Tab 16493-015 The second user configurable tab is Calibration, and it enables initializations and tracking receiver/transmitter QEC and LOL calibrations. Figure 40 shows a configuration example. The user can enable or disable initialization calibrations as well as tracking calibrations. For External Tx LOL initialization calibration together with either Tx1 LOL or Tx2 LOL tracking calibrations, use an external circuit. This section explains the internal hardware configuration only. Refer to the AD9375 Design File Package for details on the external hardware configuration. The External Init Attn option allows the user to control the level of attenuation applied initially at both of the AD9375 transmitter outputs simultaneously. Figure 40. Calibration Tab Rev. A | Page 35 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide JESD204b Setup Tab Note that the receiver and observation receiver share JESD204B lanes. Lanes configured for receiver cannot also be used for the observation receiver. 16493-016 The third user configurable tab is JESD204b Setup, which sets the characteristics of the digital data interface. Figure 41 shows a configuration example. The user can set the desired JESD204B lane configuration, select scrambling, and determine whether the selected framer/deframer relinks on SYSREF. The user can also select the use of an internal (free running) or external (provided by the AD9528) SYSREF to synchronize the JESD204B links. Figure 41. JESD204b Setup Tab Rev. A | Page 36 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 AGC Tab 16493-119 The automatic gain control (AGC) can be configured in the AGC tab. For details about modifiable settings for the AGC and consequent changes on the AD9375 device, refer to the AD9375 Design File Package. Figure 42. AGC Tab Rev. A | Page 37 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide GPIO Tabs The GPIO Config tab and the 3v3 GPIO tab are used for GPIO configuration. The GPIO Config tab contains all the configuration options for the GPIO header pins on the interposer board that the user can configure to debug, test, or evaluate the SCRD. GPIO Pin 8, Pin 9, and Pin 11 to Pin 17 are not connected to the radio board, but can still be controlled in the GPIO Config tab. 16493-017 The pins are for interfacing with test equipment or providing signals to output devices such as LEDs, or inputting options with switches. The function of each pin is defined in this tab. The state of the pins written or read by the SCRD can be verified with the software by clicking Check GPIO. After changing options in the tab, clicking Program GPIO updates the configuration in the hardware. Figure 43. GPIO Config Tab Rev. A | Page 38 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 The 3v3 GPIO tab sets the characteristics of the 3.3 V GPIO interface of the AD9375. and the settings are overwritten by the software when required. Connections for these pins are shown in Figure 102. For the ADRV-DPD1/PCBZ, the AD9375 3v3 GPIO Pin 0 to Pin 5 are used for devices on board. It is not recommended to use these pins, because using these pins may yield unexpected results, 3v3 GPIO Pin 6 to Pin 11 are not connected to anything on the radio board, but can still be controlled in the 3v3 GPIO tab. 16493-018 Figure 44 shows the default configuration. Figure 44. 3v3 GPIO Tab Rev. A | Page 39 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide Rx Summary, Tx Summary, and ObsRx/Sniffer Summary Tabs zoom area, as well as restoring the plot to full scale by right clicking on the graph area and selecting Zoom Out. The Rx Summary, Tx Summary, and ObsRx/Sniffer Summary tabs summarize the setup and include a corresponding graph. They are based on the profile selection in the Configuration tab (see Figure 39). In each of these tabs, the user can check clock rates at each filter node, as well as filter characteristics and their pass band flatness. The SCES also provides the capability to export the data plotted on the graphs to an external file. This export is performed by right clicking on the graph area and selecting Export Data to File. Data can then be saved to a file for later analysis. Figure 45 shows an example of the Rx Summary tab with the resulting composite filter response for the chosen profile. 16493-019 Quick zooming capability allows zooming of the pass band response by using the mouse cursor to drag a box to select the Figure 45. Rx Summary Tab Rev. A | Page 40 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 Clock Setup Set the values of the reference clock inputs for Ref A and Ref B using the respective boxes, and select the active reference clock using Ref Clock Selection. For details on the connections on the interposer board, refer to the System Reference Clocks section. 16493-020 The interposer board utilizes the AD9528 clock device to provide the main clock (DEV_CLK) and SYSREF with pulses to the AD9375 via the 100-way connector. The interposer board also provides various clocks and SYSREF with pulses to the FPGA on the EVAL-TPG-ZYNQ3 via the FMC connector. The AD9528 can be configured using the Ref Clock Setup tab, as shown in Figure 46. Figure 46. Ref Clock Setup Tab Rev. A | Page 41 of 115 ADRV-DPD1/PCBZ User Guide 16493-021 UG-1238 Figure 47. Device Programmed Successfully Programming the Evaluation System After all the tabs are configured, the user can click Program. The SCES sends a series of API commands that are executed by a dedicated Linux application running on the EVAL-TPG-ZYNQ3. When programming is complete, the system is ready to operate. A progress bar is visible at the bottom of the window. Figure 47 shows the window with the progress bar and message after the device has been programmed. File Dropdown Menu Figure 49 shows all commands in the File dropdown menu. The File dropdown menu allows the user to select the following commands: OTHER SCES FEATURES * The AD9375 SCES software provides the user with multiple options to store and load SCES configurations as well as hardware configurations. * * Device Dropdown Menu Figure 48 shows all commands in the Device dropdown menu. The Device dropdown menu allows the user to select the following commands: * * * * * Click Update > Platform Files when a new version of the AD9375 SCES software is installed or prior to first time use, when files stored on the EVAL-TPG-ZYNQ3 SD card need to be updated. See the Software Update section for more details. Click Reboot Zynq Platform when a soft restart of the evaluation system is desired. Click Shutdown Zynq Platform when the user wants to power down the ADRV-DPD1/PCBZ. The user must use this command to execute the correct power-down sequence. If this procedure is not followed, the file system on the SD card can become corrupted and cause the ADRV-DPD1/PCBZ system to stop operating. Save GUI Setup stores all AD9375 SCES configuration settings. SCES generates an XML file with all software settings recorded. The user can reload software settings by clicking Load Setup and selecting the saved setup file. Load GUI Setup loads all AD9375 SCES configuration settings stored in XML files that were saved using the Save GUI Setup command. Load Custom Profile loads a custom version of the AD9375 SCES profile. Use separate software to generate an AD9375 custom profile. Clear Custom Profile restores the AD9375 SCES software to its state prior to loading custom profile using the Load Custom Profile command. View Log Files monitors API activities. This command opens the window shown in Figure 50. In this window, the user can select from the following options: * AD9371DLL Log is not applicable to the hardware discussed in this user guide. It shows a sample IronPython script as a placeholder. * ErrorLog monitors the error log. The user can observe error messages reported by the API software layer. The content in the Log Window is updated when the user clicks Refresh Log. The Log Window allows the user to store log messages in the form of text files for further analysis. The log window can be cleared by clicking Clear Log. Rev. A | Page 42 of 115 ADRV-DPD1/PCBZ User Guide * * Close GUI Only closes only the SCES software, leaving the Zynq system active. Cancel closes the window. 16493-022 Exit opens the Shutdown window, as shown in Figure 51. In this window, the user can select from the following options: * Switch Zynq Off powers down the Zynq FPGA system and closes the SCES software. 16493-023 Figure 48. AD9375 SCES Device Dropdown Menu Figure 49. AD9375 SCES File Dropdown Menu 16493-024 * UG-1238 Figure 50. AD9375 SCES Log Window Rev. A | Page 43 of 115 ADRV-DPD1/PCBZ User Guide 16493-025 UG-1238 Figure 51. AD9375 SCES Shutdown Window Rev. A | Page 44 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 Tools Dropdown Menu Figure 52 shows all commands in the Tools dropdown menu. The Tools dropdown menu allows the user to select the following commands: * Options opens the Options window, shown in Figure 53. This window allows the user to set the path to the IronPython library folder. This setting is automatically populated with a path set during the installation process. Create Script allows the user to store an AD9375 initialization script. The SCES allows the user to create a script in the following forms: * Python asks for a script file name and directory in which it can be stored. AD9375 SCES generates a new_name.py file with all API initialization calls in the form of IronPython functions. That file can then be executed using the Iron Python Script tab, as shown in Figure 63. See the Scripting section for more information. * C Script opens the Save As window, requiring the user to give the file a name and specify a location for storage. Based on configuration settings outlined in the Configuring the AD9375 section, the SCES sets up structure members values that are used by the API commands. The SCES allows the user to create a *.c file that contains the initial values. This file can be imported into a user system that utilizes the AD9375 APIs. The SCES generates the following five separate files: * Headless.c provides an example file that makes calls into the AD9375 API to initialize the AD9375 device. * Headless.h is the header file for headless.c. * User_name.c contains all initialization values for the structure members used by AD9375 APIs. * User_name.h is the header file for user_name.c. * User_name_ad9528init.c contains all initialization values for the structures used by the AD9528 clock integrated circuit (IC) APIs. Memory Dump provides users with the ability to store register values from the AD9375 internal ARM processor, the AD9375 register map, and the Zynq FPGA register map. When the user clicks Memory Dump, the user must enter a name for the files and select a location where they are to be stored. The SCES then reads the internal register values and stores them in the following three separate files: * File_name.bin stores the AD9375 internal ARM processor dump. * File_name_MykonosReg.txt stores the AD9375 register dump. * File_name_FpgaReg.txt stores the Zynq FPGA register dump. 16493-026 * * Figure 52. AD9375 SCES Tools Dropdown Menu Rev. A | Page 45 of 115 ADRV-DPD1/PCBZ User Guide 16493-027 UG-1238 Figure 53. AD9375 SCES Options Window * * * API Help File opens the Mykonos Device API file in Windows help format (*.chm). Refer to this document when looking for detailed information about AD9375 API commands. DLL Help File opens the ADI ZC706 TCP/IP Client DLL file in Windows help format (*.chm). Refer to this document when looking for detailed information about functions to control the AD9375, which use the Xilinx ZC706 FPGA platform. About opens a window containing information about the SCES and DLL versions installed on the PC of the user, as well as software and firmware versions installed on the EVAL-TPG-ZYNQ3 SD card. It also displays information about the AD9375 internal ARM firmware version (see Figure 54). Rev. A | Page 46 of 115 16493-028 Help Dropdown Menu Figure 56 shows all commands in the Help dropdown menu. The Help dropdown menu allows the user to select the following commands: Figure 54. AD9375 SCES Help/About Window ADRV-DPD1/PCBZ User Guide UG-1238 System Status Bar The AD9375 SCES provides the user with visual information about the current state of the evaluation system. Figure 56 shows an example of the SCES status bar information. * The status bar information can be interpreted as follows: * 16493-029 * Zynq Platform: Connected indicates that a connection between the PC and the EVAL-TPG-ZYNQ3 is established. Zynq Platform: Disconnected indicates no established connection between the PC and the EVAL-TPG-ZYNQ3. Radio: On indicates that the AD9375 is enabled and ready to transmit and receive. Radio: Off indicates that the Figure 55. AD9375 SCES Help Dropdown Menu 16493-030 * AD9375 must be initialized and moved into the Radio: On state before signals can be transmitted or received. Tracking: TxQEC TxLOL RxQEC displays the status of the tracking calibrations utilized by the AD9375. A green indicator indicates that calibration is enabled and active. A red indicator indicates that calibration is enabled but not active. A grey indicator indicates that SCES calibration is disabled using the Calibration tab (see the Calibration Tab section). Programmed Successfully indicates progress when programming the evaluation system. Figure 56. AD9375 SCES Status Bar Rev. A | Page 47 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide RECEIVER SETUP RECEIVE DATA OPTIONS After configuring the AD9375 SCES using the Config tab and programming the system by clicking Program, the system is ready for normal operation. Clicking the Receive Data tab opens the window shown in Figure 57. When the Receive Data tab is open, the user can enter the RF receiver center frequency in megahertz. The receiver gain can be set by entering the desired gain index for each receiver channel. The gain index refers to the value in the programmable gain index table. Refer to the AD9375 Design File Package for details on gain index table implementation. The user can also enable or disable Rx1 or Rx2 QEC tracking calibrations as well as rerun receiver initialization calibrations. The lower plot shows the time domain waveform. The user can select whether both Rx1 and Rx2 data are displayed in this pane, or only one of them, by selecting the corresponding check boxes. The user can also select if only in phase (I) or only quadrature phase (Q) data are displayed, or both. The time domain waveform display supports zooming by selecting a region of the time domain plot to zoom. Right clicking in the Time Domain pane and selecting Undo All Zoom/Pan returns the time domain plot to its original scale. The user can enable autoscaling in the Time Domain plot by selecting the AutoScale check box. If the FFT analysis is selected by clicking the multicolored pie chart button in the toolbar, basic analysis information from the FFT is displayed on the left side of the screen. The FFT results are displayed separately for each receiver channel. 16493-031 By clicking the play button in the Receiver Data tab toolbar, the AD9375 moves to the receive state and graphs the received data in both frequency and time domains. An example of a captured waveform is shown in Figure 57. The upper plot displays the fast Fourier transform (FFT) result. The user can select if both Rx1 and Rx2 data are displayed in this pane or only one of them by selecting the corresponding check boxes. Figure 57. Receive Data Tab Rev. A | Page 48 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 The RxTrigger dropdown menu can select the following settings: OBSERVATION RECEIVER SIGNAL CHAIN * Clicking the ObsRx Sniffer Data tab opens the page shown in Figure 58. Note this tab is only fully functional if the transmitter is running because the observation receiver requires the transmitter local oscillator (TXLO). When this tab is open, the user can enter the observation receiver RF center frequency in megahertz. The observation receiver gain can be set by entering the desired gain index. The gain index refers to the value in the programmable gain index table. Refer to the AD9375 Design File Package for details on gain index table implementation. * * IMMEDIATE starts the capture as soon as the SPI command is received to initiate capture. EXT_SMA starts the capture when a high level is present at Connector J68 on the EVAL-TPG-ZYNQ3. TDD_SM_PULSE gives control of the receiver data paths to the state machine that is implemented in the Zynq FPGA. This setting is used when the AD9375 is operating in time division duplex (TDD) mode. TDD mode is not currently supported. The SCRD radio is currently available only as a frequency division duplex (FDD) variant. The received data can be saved to a file by clicking the save button in the toolbar. This button opens a dialogue box allowing selection of the format for the exported data. The following file types are supported: * * * The user can select the observation channel from the ObsChannel dropdown menu. The following options are available: * Agilent Data adds a header to the saved file so that Agilent (Keysight) vector signal analysis (VSA) software can read it and use it to demodulate the data. The header is followed by data stored in I <TAB> Q <NEW_LINE> format. No Header (Tab delimited) saves data as a text file where I data is separated by a <TAB> from Q data. Each data record is finished with a <NEW_LINE> character. There is no header information stored in this file format. No Header (Comma delimited) saves data as a text file where I data is separated by a comma from Q data. Each data line is finished with the <NEW_LINE> character. There is no header information stored in this file format. The number of points saved to the file is determined by the number of samples selected in the # Samples spin box. The user can also rerun initial Rx calibrations by clicking Run Cals. When calibrations are in progress, this button text temporarily changes to Running until the calibration completes. It is not recommended to apply an input signal to the receiver input when performing an initial calibration. The user can also enable or disable Rx1 and Rx2 QEC tracking calibrations. The Rx1 QEC Tracking check box enables tracking calibration for the Rx1 path and the Rx2 QEC Tracking check box enables tracking calibration for the Rx2 path. Tracking calibrations operate when a receiver signal path receives data. * * * * * * * Internal path allows the ObsRx path to be used by internal calibrations. Refer to the AD9375 Design File Package for details on calibration requirements. Sniffer A. Sniffer B. Sniffer C. ORX1 with TXLO. ORX2 with TXLO. ORX1 with SNIFFERLO. ORX2 with SNIFFERLO. None of the AD9375 sniffer receiver inputs are connected to anything on the radio board. After pressing the play button in the toolbar in the ObsRx Sniffer Data tab, the AD9375 moves to the receive state and graphs the output data. An example of a captured waveform is shown in Figure 58. The upper plot displays the FFT result. If the FFT analysis is selected by clicking the pie chart button in the toolbar, basic analysis information from the FFT is displayed on the left side of the screen. The lower plot shows the time domain waveform. The user can select whether only I or only Q data is displayed. The time domain waveform display supports zooming by selecting a region of the time plot to zoom. Right clicking on the Time Domain plot and selecting Undo All Zoom/Pan returns the time domain plot to its original scale. The data received by the observation receiver channel can be saved to a file in the same manner as the receiver data, by following the instructions in the Receive Data Options section. Rev. A | Page 49 of 115 ADRV-DPD1/PCBZ User Guide 16493-032 UG-1238 Figure 58. ObsRx Sniffer Data Tab Rev. A | Page 50 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 TRANSMITTER SETUP Clicking the Transmit Data tab opens the page shown in Figure 59. The upper plot displays the FFT result. The user can select whether both Tx1 and Tx2 data are displayed in this pane, or only one of the frequency plots, by selecting the corresponding check boxes. When the Transmit Data tab is open, the user can enter the RF transmitter center frequency in megahertz in the RFLO Frequency spin box, change attenuation level independently for each transmitter output, enable or disable different calibrations, control data scaling, and transmit continuous waveform (CW) tones or a waveform loaded in a transmitter data file. 16493-033 The lower plot shows the time domain waveform. The user can select whether both Tx1 and Tx2 time plots are displayed in this pane, or only one of these plots, by selecting the corresponding check boxes. The user can also select whether only I or only Q data is displayed. The time domain waveform display supports zooming by selecting a region of the plot to zoom. Right clicking on the Time Domain pane and selecting Undo All Zoom/Pan returns the time domain plot to its original scale. The user can enable autoscaling by right clicking in the time domain plot and selecting AutoScale. Figure 59. Transmit Data Tab Rev. A | Page 51 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide TRANSMIT DATA OPTIONS The SCES provides the following options for inputting transmitter data: * * A single tone or dual tone signal can be generated by the evaluation system using the ToneParameters dialog box, as shown in Figure 60. In this box, the user can select the number of tones (one or two) that are transmitted on the selected transmitter output. The user has control over the tone frequency offset relative to the LO frequency, as well as the tone amplitude(s) in decibels relative to full scale. The user can store those signals in the form of text files by clicking Save Tx Raw Data into a File. Click the play button in the toolbar before data is populated into these files. User generated data files can be selected by clicking Load Tx1 and Load Tx2. * Format these files as I sample <TAB> and Q sample <NEW_LINE> per line. Each I or Q sample must be an integer in the range between +32,768 to -32,767. * If peak values of I and Q samples are very low, the signal can be normalized to full scale using the Scaling Required check box in the Load window. * File size is limited to four megasamples (MS) for each channel (I data = 4 MS maximum, Q data = 4 MS maximum). The EVAL-TPG-ZYNQ3 allocates 134,217,728 bytes for each buffer. Rx1, Rx2, observation receiver, Tx1, and Tx2 have separate buffers. Each data path uses 4 bytes per complex sample (16 bits for the I sample and 16 bits for the Q sample). Therefore, each data path has 33,554,432 16-bit I/Q pairs. A 122.88 MSPS I/Q rate therefore translates to a maximum of just over 273 ms of capture time for each channel. Clicking the play button on the toolbar starts signal transmission on the AD9375 Tx1 and/or Tx2 outputs. Clicking play starts a process in which the generated CW data or the I/Q waveform data in the Tx1 and Tx2 files are sent to the AD9375. The data is loaded into the random access memory (RAM) of the EVALTPG-ZYNQ3, and a RAM pointer loops through the data continuously until the user clicks stop on the toolbar. Scaling (dBFS) box performs the same operation on the data sent over the Tx2 channel. It is recommended to apply some of this digital scaling to a signal that is close to full scale (0 dBFS) when DPD is applied, which allows for gain expansion of the signal. The Tx1 LOL Tracking check box enables transmitter LOL tracking calibration. Calibration improves the LOL performance on the Tx1 channel. The Tx2 LOL Tracking check box performs the same operation on the Tx2 channel. To perform Tx LOL tracking calibrations, circuitry external to the AD9375 is required to route the transmitter signal back to the observation receiver input. The SCRD radio has this circuitry. The Tx1 QEC Tracking check box enables transmitter QEC tracking calibration on the Tx1 channel. Calibration improves the analog quadrature modulator performance of the AD9375. The Tx2 QEC Tracking check box performs the same operation on the Tx2 channel. Tx1 and Tx2 LOL and QEC tracking calibrations can operate only when the observation receiver path is configured to be used with internal calibration. When the user enables transmitter outputs, the AD9375 SCES automatically reconfigures the observation receiver path to the internal calibration mode. The user can change the observation receiver path at any time using the ObsRx Sniffer Data tab. Refer to the AD9375 Design File Package for details on calibration. The Tx Init Cals button runs transmitter initialization QEC and LOL calibrations. It is recommended to run these calibrations first, before the user starts to transmit signals. While the initial calibrations are running, high level tones are present at the AD9375 transmitter outputs. Therefore, it is recommended to disable the PA until this calibration finishes. Both of the AD9375 transmitter outputs are recommended to be terminated with 50 loads during the initial calibration process. The Tx1 Scaling (dBFS) spin box allows the user to control digital scaling of data sent over the Tx1 channel. The scaling can be set in 1 dB increments. Scaling is only available for transmitter data loaded using the Load Tx1 button. The Tx2 Rev. A | Page 52 of 115 16493-034 The Tx1 Attenuation (dB) spin box allows the user to control analog attenuation in the Tx1 channel. The Txl Attenuation (dB) spin box provides 0.05 dB of attenuation control resolution. The Tx2 Attenuation (dB) spin box performs the same operation on the Tx2 channel. Figure 60. Transmitter ToneParameters Dialog Box ADRV-DPD1/PCBZ User Guide UG-1238 RF PATH AND DPD CONTROLS By default, the transmitter output RF paths and the Rx input RF paths are disabled. To configure and enable the RF paths, use the RF Control and DPD Control tabs. TRANSMITTER RF PATH CONTROLS RECEIVER RF PATH CONTROLS Each receiver RF path features an LNA, as shown in Figure 10. The LNAs for Rx1 and Rx2 can be independently enabled or disabled by clicking the respective button in the RF Control tab, shown in Figure 61. 16493-035 Each transmitter RF path features a gain amplifier with a built in step attenuator and a PA, as shown in Figure 10. The RF Control tab features the controls to enable or disable the amplifiers and to set the digital step attenuator, as shown in Figure 61. The minimum attenuation that can be set is 0 dB. The maximum attenuation depends on the device fitted as the gain amplifier. For example, radio boards with ADL5335 gain amplifiers exhibit an attenuation range of 0 dB to 20 dB in 0.5 dB increments. Figure 61. RF Control Tab Rev. A | Page 53 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide DPD CONTROLS The AD9375 transceiver features a low power DPD algorithm that runs on-chip on an ARM processor. This feature can be enabled or disabled via the DPD controls on the DPD Control tab, as shown in Figure 62. Note that DPD can only be used after the initial calibrations are done, while the transmitter is enabled, while the waveform playback is running, and while the gain amplifier and PA are both enabled. 16493-037 To enable the DPD feature, select the transmitter path(s) for which linearization is required by selecting the Tx1 Dpd Adaptation and Tx2 Dpd Adaptation check boxes, then enable DPD tracking by clicking Start DPD. To disable the DPD feature for a transmitter path, select the check box for the transmitter path that no longer requires linearization and disable DPD tracking by clicking Reset DPD. Figure 62. DPD Control Tab Rev. A | Page 54 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 SCRIPTING After the user configures the device to the desired profile, a script can be generated with all API initialization calls in the form of IronPython functions. The Tools > Create Script > Python command can be used to accomplish this task. See the Tools Dropdown Menu section for more details. The Iron Python Script tab allows the user to use the IronPython language to write a unique sequence of events and then execute them using the ADRV-DPD1/PCBZ system. * * * * New creates a new IronPython script that connects to the AD9375 small cell reference system and checks the AD9375 API version operating on the EVAL-TPG-ZYNQ3. Load allows the user to load previously stored IronPython scripts. Save and Save As allow the user to store IronPython scripts. Close closes the currently active Iron Python Script tab without saving. 16493-039 Scripts generated using the Tools > Create Script > Python command can be loaded, modified if needed, and run in the Iron Python Script tab. Figure 63 shows the Iron Python Script tab after executing the File > New command in the Iron Python Script tab. The top pane contains IronPython script commands, and the bottom pane of the window displays the script output. The Iron Python Script tab provides the user with a number of options to manipulate the editing and execution of the IronPython scripts. The File dropdown menu in the Iron Python Script tab, shown in Figure 64, contains the following commands: Figure 63. Iron Python Script Tab Rev. A | Page 55 of 115 ADRV-DPD1/PCBZ User Guide 16493-040 UG-1238 16493-041 Figure 64. File Menu in the Iron Python Script Tab Figure 65. Build Menu in the Iron Python Script Tab The Build dropdown menu in the Iron Python Script tab, shown in Figure 65, contains the following commands: * * * Run executes the IronPython script open in the currently active Iron Python Script tab using the ADRV-DPD1/PCBZ. Script output is displayed at the bottom of the Iron Python Script tab. Clear Script clears the IronPython script editing pane. Clear Output clears the IronPython script output pane. IRONPYTHON SCRIPT EXAMPLE tab, must be renamed according to the Mykonos API syntax, such as MYKONOS_functionName(), to reflect the IronPython syntax, Mykonos.functionName(). A header with a new class instance for a new connection must be added. For example, after calling #Create an Instance of the Class Link = AdiCommandServerClient.Instance The new class instance for the AD9375 evaluation hardware is Link. The following example, which is generated by executing the File > New command in the IronPython Script tab, connects to the AD9375 small cell reference system and then checks and displays the version of the AD9375 API operating on the EVAL-TPGZYNQ3. When using the Iron Python Script tab, the user can execute any API command. The list of all API commands is provided by the SCES. The list can be viewed by clicking DLL Help File in the Help menu. All AD9375 API functions, when called in the Iron Python Script An example of an API function called using IronPython follows. If the user wants to check the gain index for the Rx1 signal chain using the AD9375 API function called MYKONOS_getRx1Gain() The user calls the following IronPython function: print Link.Mykonos.getRx1Gain() This call assumes that the platform is initialized using the example code described in this section. Rev. A | Page 56 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 ######################## #ADI Demo Python Script ######################## #Import Reference to the DLL import clr clr.AddReferenceToFileAndPath("C:\\Program Files (x86)\\Analog Devices\\Small Cell Evaluation Software\\AdiCmdServerClient.dll"") from AdiCmdServerClient import AdiCommandServerClient from AdiCmdServerClient import Mykonos #Create an Instance of the Class Link = AdiCommandServerClient.Instance #Connect to the Zynq Platform if(Link.hw.Connected == 1): Connect = 0 else: Connect = 1 Link.hw.Connect("192.168.1.10", 55555) #Read the Version print Link.version() #Disconnect from the Zynq Platform if(Connect == 1): Link.hw.Disconnect() Rev. A | Page 57 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide TROUBLESHOOTING This section provides a quick help guide with a description of what to do if the system is not operational. This guide assumes that the user followed all the instructions and that the hardware configuration matches the one described in this user guide. STARTUP 3. No LED Activity (Zynq) If there is no LED activity on the EVAL-TPG-ZYNQ3 board, 1. Check if the EVAL-TPG-ZYNQ3 is properly powered. There must be 12 V present at the J22 input, and after powering the EVAL-TPG-ZYNQ3 on (with SW1 turned on), the following must be true: * * 2. 4. The fan on the EVAL-TPG-ZYNQ3 is active. A number of green LEDs on the EVAL-TPG-ZYNQ3 near SW1 are on with no red LEDs active on the EVAL-TPG-ZYNQ3. EVAL-TPG-ZYNQ3 GPIO LEDs follow the sequence described in the Hardware Operation section. If the LED sequence does not follow the one described, check the jumper settings and SW11 positions on the EVAL-TPG-ZYNQ3. If the jumper settings are correct, check that the SD card is properly inserted into the socket (J30). It is recommended to use the SD card provided with the evaluation system. The SD card can be updated to the appropriate image that is available in the SCES under Device > Update > Platform Files. LED 1 and LED 2 (STATUS 1 and STATUS 0) on Interposer Board Do Not Illuminate After Programming If one or more of the status LEDs on the interposer board do not illuminate, 1. 2. 3. If there is still a problem and the user is certain that the EVALTPG-ZYNQ3 is operational, contact an Analog Devices representative for assistance. LEDs Active but SCES Reports that Hardware is Not Connected 2. Check if the clock is set up properly on the external reference clock. Ensure the clock is connected properly to J8 or J13 and to the reference out connection on the external clock device. In the Ref Clock Setup tab, check that the frequency in the Ref A or Ref B box is the same as the reference clock, and the selected Ref Clock Selection option button is the same as the connector being used on the interposer board to receive the clock signal (see the Clock Setup section for details). ERROR HANDLING If the SCES reports that the hardware is not connected, 1. over the Ethernet port with the EVAL-TPG-ZYNQ3. Check if the IP address and open ports for the Ethernet connection used to communicate with the EVAL-TPGZYNQ3 follow the advice provided in the SCES Setup section. Run cmd.exe on the Windows OS and type ping 192.168.1.10. The user can see a reply from the EVALTPG-ZYNQ3. If no reply is received, reexamine the connection with the EVAL-TPG-ZYNQ3. If a connection with the EVAL-TPG-ZYNQ3 is established but SCES still reports that the hardware is not available, ensure that Port 22 (secure shell (SSH)) and Port 55555 (evaluation software) are not blocked by firewall software on the Ethernet connection used to communicate with the EVAL-TPG-ZYNQ3. Both ports must be open for normal operation. Refer to the SCES Setup section for more details. Check if the Ethernet cable is properly connected to the PC used to run the SCES and the EVAL-TPG-ZYNQ3. LEDs on the EVAL-TPG-ZYNQ3 next to the Ethernet socket flash when the connection is active. If the Ethernet cable is properly connected, check that the Windows operating system (OS) is able to communicate The SCES provides the user with a number of error messages in case there are problems with the hardware or software configuration. The error messages the SCES can display are intended to provide a description of the problem encountered by the software. If the error description refers to the DLL command, refer to the API and DLL help files supplied with the SCES. Rev. A | Page 58 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 TYPICAL PERFORMANCE 5 5 -5 -5 DPD OFF DPD ON -25 -35 -45 -55 16493-269 -65 -25 -45 16493-266 -65 2.672 2.670 2.667 2.665 2.662 2.660 2.657 2.655 2.652 2.650 2.647 2.645 2.642 2.640 2.637 -75 FREQUENCY (GHz) Figure 66. Tx1 5 MHz ACLR 5 2.71 2.70 Power measured is the total channel power of the 4.515 MHz or 18.015 MHz channels relative to the transmit channel power. All measurements are taken on a transmitted signal with a transmit power of 24 dBm at the antenna connector. The test waveforms were 3GPP E-TM1.1, 7.0 dB peak to mean -11 dBFS rms, centered on the transmitter LO. Table 12. Tx1 5 MHz DPD Off ACLR -5 Offset (MHz) -15 -10 -5 +5 +10 +15 DPD OFF DPD ON -15 -25 -35 -45 Power (dBc) -63.8 -52.4 -39.6 -41.1 -53.0 -63.7 -55 Table 13. TX1 5 MHz DPD On ACLR 16493-267 -65 2.71 2.70 2.69 2.68 2.67 2.66 2.65 2.64 2.63 2.62 2.61 2.60 -75 FREQUENCY (GHz) Figure 67. Tx1 20 MHz ACLR 5 -5 DPD OFF DPD ON -15 Offset (MHz) -15 -10 -5 +5 +10 +15 Power (dBc) -67.4 -63.1 -60.1 -59.1 -62.5 -66.9 Table 14. TX1 20 MHz DPD Off ACLR Offset (MHz) -40 -20 +20 +40 -25 -35 -45 Power (dBc) -54.6 -38.8 -42.1 -54.4 -55 Table 15. TX1 20 MHz DPD On ACLR 16493-268 -65 FREQUENCY (GHz) Figure 68. Tx2 5 MHz ACLR 2.672 2.670 2.667 2.665 2.662 2.660 2.657 2.655 2.652 2.650 2.647 2.645 2.642 2.640 -75 2.637 POWER (dB) 2.69 2.68 2.67 2.66 2.65 2.64 2.63 2.62 FREQUENCY (GHz) Figure 69. Tx2 20 MHz ACLR -55 POWER (dB) 2.61 -75 -35 2.60 POWER (dB) -15 DPD OFF DPD ON -15 POWER (dB) Figure 66, Figure 67, Figure 68, and Figure 69 show typical transmitter adjacent channel leakage power ratio (ACLR) performance of the ADRV-DPD1/PCBZ radio board. The difference between the DPD turned on and off is shown in the improved ACLR performance when DPD is enabled on these 5 MHz and 20 MHz bandwidth LTE carriers. Offset (MHz) -40 -20 +20 +40 Rev. A | Page 59 of 115 Power (dBc) -62.5 -57.3 -57.3 -64.6 UG-1238 ADRV-DPD1/PCBZ User Guide Table 16. TX2 5 MHz DPD Off ACLR Table 18. TX2 20 MHz DPD Off ACLR Offset (MHz) -15 -10 -5 +5 +10 +15 Offset (MHz) -40 -20 +20 +40 Power (dBc) -64.2 -53.4 -39.7 -41.1 -53.7 -63.9 Table 19. TX2 20 MHz DPD On ACLR Offset (MHz) -40 -20 +20 +40 Table 17. TX2 5 MHz DPD On ACLR Offset (MHz) -15 -10 -5 +5 +10 +15 Power (dBc) -55.2 -39.0 -41.5 -53.8 Power (dBc) -68.5 -64.5 -59.7 -59.5 -64.4 -68.2 Power (dBc) -63.0 -57.0 -55.6 -64.0 ELECTRICAL SPECIFICATIONS Table 20. General TA = 25C, VDD = 5.1 V, 50 System Parameter Frequency and Bandwidths RF Transmitter Frequency Range RF Bandwidth Environmental Operational Temperature 1 Value Typ Min Max Unit Test Conditions 2620 2500 2690 2570 40 MHz MHz MHz Tx Rx 0 351 C Maximum operational temperature refers to temperature in still air with heatsink supplied. Other heatsinking arrangements are possible. Table 21. RF Performance TA = 25C, VDD = 5.1 V, 50 System Parameter Transmitter Specification Maximum Transmitter Output Power1 Transmitter Output Power Accuracy ACLR at 20 MHz Offset Error Vector Magnitude (EVM)2 Receiver Specification Receiver Noise Figure Receiver Front End Gain Receiver AD9375 Gain 1 2 Min 47 Value Typ Max Unit Test Conditions 24 dBm 20 MHz bandwidth, LTE E-TM1.1, peak to average power ratio (PAR) = 7 dB 0.025 52 4.8 dB dBc % 20 MHz bandwidth, LTE E-TM1.1, O/P = 24 dBm, PAR = 7 dB 20 MHz bandwidth, LTE E-TM3.1 (64 QAM), PAR = 7 dB dB dB dB 2535 MHz Antenna port to AD9375 AD9375 7.9 6 30 10.7 9 Output power at each antenna port. EVM measured with specific crest factor reduction algorithm. Rev. A | Page 60 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 BILL OF MATERIALS Table 22. ADRV-DPD1/PCBZ Electrical Bill of Materials Designator C1, C3, C5, C9, C144, C145, C198, C199, C200, C201 Description Capacitors, 0201, 100 pF, 50 V, C0G, 5% Capacitors, 0201, 0.5 pF, 25 V, C0G, 0.1 pF Capacitors, 0201, 1.0 pF, 25 V, C0G, 0.1 pF Capacitors, 0201, 6.0 pF, 25 V, C0G, 0.5 pF Capacitors, 0201, 5.6 pF, 25 V, C0G, 0.5 pF Capacitors, 0402, 1.0 F, 10 V, X5R, 10% C2, C7 C4, C8, C197, C205 C6, C10, C12, C14 C11, C13 C15, C21, C24, C26, C27, C30, C33, C34, C37, C41, C43, C45, C50, C52, C54, C55, C57, C58, C59, C60, C62, C64, C81, C82, C110, C134, C143, C152, C153, C158, C159, C214 C16, C70, C74, C122, C141, C150, C167 C17, C18, C19, C20, C22, C23, C25, C28, C29, C35, C38, C39, C40, C42, C48, C49, C51, C53, C56, C61, C63, C66, C67, C71, C75, C108, C132, C139, C147, C211, C215 C31 C32, C36, C46, C47, C65, C68, C69, C213 C44, C168, C212 C72, C76, C84, C91, C96, C99, C113, C123, C126, C129, C138, C160, C171, C175, C203 C73, C83 C77, C78, C79, C80, C86, C87, C88, C89, C94, C95, C109, C125, C131, C133, C156, C157, C164, C166, C169, C170 C85, C92, C98, C106 C90, C93, C101, C102, C111, C112, C120, C121, C135, C136, C165, C208 C97, C100 C105, C115, C116, C127, C140, C146, C162, C163, C173, C174, C182, C183, C188, C189, C190, C191, C220, C221 C107, C114, C118, C119, C124, C128, C130, C137, C148, C149, C155, C161, C172, C178, C179, C180, C181, C184, C185, C186, C187, C202, C206, C207 C117, C154, C222, C223 C176, C177 C192, C193, C194, C195 C216, C217, C218, C219 D2, D3 J1 Manufacturer Murata Part Number GRM0335C1H101JD01D Murata GJM0335C1ER50BB01D Murata GJM0335C1E1R0BB01D Murata GJM0335C1E6R0DB01D Murata GJM0335C1E5R6DB01D Murata GRM155R61A105KE15D Capacitors, 0603, 10 F, 10 V, X5R, 10% Capacitors, 0201, 0.10 F, 10 V, X5R, 10% Murata GRM188R61A106KE69D Murata GRM033R61A104KE84D Capacitors, 0201, 1000 pF, 25 V, X7R, 10% Capacitors, 0805, 100 F, 4 V, X5R, 20% Capacitors, 0201, 10000 pF, 10 V, X7R, 10% Capacitors, 0402, 0.10 F, 16 V, X5R, 10% Capacitors, 1206, 100 F, 10 V, X5R, 20% Capacitors, 0805, 47 F, 10 V, X5R, 20% Capacitors, 0805, 10 F, 25 V, X5R, 10% Capacitors, 0402, 3300 pF, 50 V, X7R, 10% Capacitors, 0402, 2200 pF, 50 V, X5R, 10% Capacitors, 0402, 8.2 pF, 50 V, C0G, 0.1 pF Capacitors, 0402, 100 pF, 50 V, C0G, 5% Murata GRM033R71E102KA01D Murata GRM21BR60G107ME15 Murata GRM033R71A103KA01D Murata GRM155R61C104KA88D TDK C3216X5R1A107M160AC Murata GRM21BR61A476ME15D Murata GRM219R61E106KA12D Murata GRM155R71H332KA01D Murata GRM155R61H222KA01D Murata GJM1555C1H8R2BB01D Murata GRM1555C1H101JA01D Murata GJM0335C1E4R3CB01D Murata GRM188R71H104KA93D Murata GJM0336C1E8R2DB01D Murata GJM1555C1H1R3BB01D Skyworks CLA4606-085LF SAMTEC ERM8-050-02.0-S-DV-K-TR Capacitors, 0201, 4.3 pF, 25 V, C0G, 0.25 pF Capacitors, 0603, 0.10 F, 50 V, X7R, 10% Capacitors, 0201, 8.2 pF, 25 V, C0H, 0.5 pF Capacitors, 0402, 1.3 pF, 50 V, C0G, 0.1 pF Surface mount limiter diodes, 75 V 100-position connector header Rev. A | Page 61 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide Designator J3, J4 L1, L2 L3, L4 L6, L30 L7, L31 L8, L32 L10, L11 L12, L18, L21, L23, L26 L13, L15 L14, L19, L20, L22, L25, L52, L66, L70 L16, L17 L24, L51, L53 L27, L37, L38, L39 L28, L29 L33, L34, L40, L41, L55, L56, L57, L59, L60, L61, L67, L71, L78, L79, L80, L81 L35, L36 L42, L43 L44, L45, L46, L47 L48 L54, L62 L58, L63 L85, L87 Q1 R1 R2, R6, R87, R92, R109, R131, R147, R148 R4 R5 R7, R8, R15, R23, R47, R52, R56, R76, R85, R88, R89, R91, R104, R105, R106, R107, R108, R113, R116, R132, R133 R9, R14, R20, R21, R32, R33, R35, R36, R42, R43, R54, R69, R110, R111, R114, R125, R126, R137, R140, R143, R144, R146 R10 R11, R22, R27 R17, R94, R112, R117, R124, R135 R18 R19, R26 R24, R34, R39, R57, R58, R62, R64, R74 Description SMP RF connectors, PCB Straight receptacle, 4 solder legs Inductors, 0201, 3.9 nH, 0.1 nH Inductors, 0201, 6.2 nH, 3% Inductors, 0402, 36 nH, 2% Inductors, 0402, 1.0 nH, 0.3 nH Inductors, 0402, 30 nH, 2% Ferrites, 0201, 33 , 25% Ferrites, 0402, 120 , 25% Inductors, 0201, 10 nH, 3% Ferrites, 0402, 470 m, 25% Inductors, 0201, 27 nH, 5% Ferrites, 0402, 220 , 25% Ferrites, 0603, 120 , 25% Inductors, 2.5 x 2.0 x 1.2, 2.2 H, 20% Ferrites, 0402, 33 , 25% Manufacturer Radiall Part Number R222 426 300 Murata LQP03TN3N9B02P Murata Murata Murata LQP03TN6N2H02P LQW15AN36NG00 LQG15HN1N0S02 Murata Murata Murata Murata Murata LQW15AN30NG00 BLM03PX330SN1 BLM15PX121SN1D LQP03TN10NH02P BLM15PX471SN1D TDK Murata Murata Toko MLK0603L27NJT000 BLM15PX221SN1D BLM18KG121TN1D 1239AS-H-2R2M Murata BLM15PX330SN1D Inductors, 4020, 1 H, 20% Inductors, 0402, 24 nH, 2% Inductors, 0402, 27 nH, 5% Ferrite, 0805, 33 , 25% Inductors, 0402, 8.2 nH, 2% Inductors, 0402, 4.7 nH, 0.1 nH Inductors, 0402, 2.7 nH, 0.1 nH Dual N-channel 20 V (D-S) MOSFET Resistor, 0201, 100 , thick film, 1% Resistors, 0402, 4.7 k, thick film, 1% Resistor, 0402, 1 k, thick film, 1% Resistor, 0402, 14.3 k, thick film, 1% Resistors, 0402, 10 k, thick film, 1% Resistors, 0402, 0 , thick film Resistor, 0402, 15 k, thick film, 1% Resistors, 0402, 10 k, thick film, 0.5% Resistors, 0402, 100 k, thick film, 1% Resistor, 0402, 31.6 k, thick film, 0.5% Resistor, 0402, 22 k, thick film, 1% Resistors, 0201, 0 , thick film Coilcraft Murata Murata Tayio Yuden Murata Murata XFL4020-102MEC LQW15AN24NG00 LQW15AN27NJ00 FBMJ2125HM330-T LQW15AN8N2G00D LQW15AN4N7B00D Murata LQW15AN2N7B00D Vishay SiA906EDJ-T1-GE3 Rohm MCR006YZPF1000 Rohm MCR01MZPF4701 Rohm MCR01MZPF1001 Rohm MCR01MZPF1432 Rohm MCR01MZPF1002 Rohm MCR01MZPJ000 Rohm MCR01MZPF1502 Yageo RT0402DRD0710KL Rohm MCR01MZPF1003 Yageo RT0402DRD0731K6L Rohm MCR01MZPF2202 Rohm MCR006YZPJ000 Rev. A | Page 62 of 115 ADRV-DPD1/PCBZ User Guide Designator R25 R29 R40, R72, R93, R121 R41, R45 R44, R48, R49, R60 R46, R66 R50, R65 R51, R53, R67, R68 R55, R70, R77, R90 R59, R78 R61, R63, R81, R83 R127, R128 T2, T5 T3, T6 U1 U2 U3 U4, U8 U5, U9 U6, U11 U7, U15 U10, U14 U12, U13 U16, U21 U17, U18 U19 U20, U22 U23 SH1 SH2 SH3 UG-1238 Description Resistor, 0402, 13 k, thick film, 0.5% Resistor, 0402, 10.2 k, thick film, 0.5% Resistors, 0402, 2.2 k, thick film, 1% Resistors, 0402, 18 , thick film, 1% Resistors, 0402, 294 , thick film, 1% Resistors, 0402, 105 , thick film, 1% Resistors, 0603, 49.9 , thick film, 1% Resistors, 0402, 78.7 , thick film, 1% Resistors, 0402, 8.2 k, thick film, 1% Resistors, 0402, 12 , thick film, 1% Resistors, 0402, 430 , thick film, 1% Resistors, 0402, 6.34 k, thick film, 0.5% Ultra low profile 0805 baluns 50 to 50 balanced Ultra low profile 0805 baluns 50 to 200 balanced Integrated dual RF transceiver with observation Low voltage temperature sensors Quad buck regulator integrated power solution 2655 MHz isolators (CW) 30 dB directional couplers Band 7 UPD series duplexers Programmable gain amplifiers (0.7 GHz to 3.4 GHz) 2490 MHz to 2690 MHz power amplifiers 200 MHz to 3800 MHz broadband low noise amplifiers RF filters for small cells (2535 MHz) Buffers with open drain outputs Inverters with open drain outputs RF low-pass filters 128 kB SPI CMOS serial EEPROM, TSSOP-8 ADI RF card bottom shieldcan ADI RF card top shieldcan ADI RF card PSU shieldcan Rev. A | Page 63 of 115 Manufacturer Yageo Part Number RT0402DRD0713KL Yageo RT0402DRD0710K2L Rohm MCR01MZPF2201 Rohm MCR01MZPF18R0 Rohm MCR01MZPF2940 Rohm MCR01MZPF1050 Rohm MCR03EZPFX49R9 Rohm MCR01MZPF78R7 Rohm MCR01MZPF8201 Rohm MCR01MZPF12R0 Rohm MCR01MZPF4300 Yageo RT0402DRD076K34L Anaren B0322J5050AHF Anaren BD0826J50200AHF Analog Devices Analog Devices Analog Devices TDK Anaren CTS Analog Devices Skyworks AD9375BBCZ SKY66297-11 Skyworks SKY67159-396LF TDK B9629 NXP 74LVC2G07GW NXP 74LVC2G06GW TDK On-Semi DEA162690LT-5051B1 CAT25128YI-GT3 Benetel 31082267 Benetel Benetel 31082268 31082269 TMP36GRTZ-REEL7 ADP5054ACPZ CU4S0506AT-2655-00 X3C26P1-30S UPD007A ADL5335ACPZ UG-1238 ADRV-DPD1/PCBZ User Guide Designator PCB1 Description AD9375 small cell reference design PCB_REV1.3 PCB adhesive, applied to U6 and U11 HW1, HW2, HW3, HW4 Manufacturer Benetel Part Number 31282247 RS 567-581 Table 23. ADRV-DPD1/PCBZ Mechanicals Bill of Materials Designator HW5, HW6, HW7 HW8, HW9, HW10, HW11 HW12, HW13, HW14 HW15, HW16, HW17 HW18 HW19 HW20 HW21 HW22, HW23 HW24 H25, H26, H27 Description Screws, M3, 16 mm long pozi pan Screws, M3, steel, 6 mm, bright zinc, flat/countersunk head pozidriv Washers, plain, M3 Washers, lock, M3 Heatsink, machining Heatsink, interface Thermal compound, syringe, 10 ML Gap pad Gap pads EMC gasket Standoffs and spacers, 9 mm Manufacturer Duratool Duratool Duratool Duratool Benetel Benetel Fischer Elektronik Benetel Benetel Benetel RAF Electronic Hardware Part Number 1420393 1420397 1377551 1624024 31082282 31082283 WLPK 10 31082284 31082285 31082287 M0538-3-AL Table 24. ADRV-DPD1/PCBZ Empty Pads (Do Not Fit) Designator C103, C104, C142, C151, C196, C204, C209, C210 L72, L73, L75, L76, L84, L86 R73, R75, R82, R84, R86, R95 R12, R13, R28, R30, R31, R37, R38, R71, R97, R98, R100, R101, R136, R138, R139, R141 R3, R16 Description Capacitors, 0201 Inductors, 0402 Resistors, 0201 Resistors, 0402 Resistors, 0603 Table 25. ADRV-INTERPOS1/PCBZ Electrical Bill of Materials Designator C1, C39, C54, C56, C57, C58, C59, C60, C63, C64, C83, C86, C88, C89, C116, C127, C128, C129, C130, C132 C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C25, C26, C40, C46, C52, C53, C65, C69, C76, C81, C90, C91, C92, C93, C94, C95, C96, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C115, C117, C125 C21, C28, C29, C62, C113, C123 C22, C66, C67, C68, C77, C78, C80, C82, C84, C85 C23, C33, C41, C50 C30, C32 C34, C35, C43, C44 C36 C37, C70, C79 C38, C48, C49, C55, C71, C72, C73, C74, C75, C108, C109, C110, C111, C112, C114, C119 C45 C47 C51, C118 C61 Description Capacitors, 0402, 1.0 F, 6.3 V, X5R Manufacturer Murata Part Number GRM155R60J105KE19D Capacitors, 0402, 0.1 F, 16 V, X7R Murata GRM155R71C104KA88D Capacitors, 0402, 0.01 F, 25 V, X5R Capacitors, 0805, 10 F, 25 V, X5R Capacitors, 0402, 1000 pF, 50 V, C0G Capacitors, 0402, 470 pF, 50 V, C0G Capacitors, 1206, 100000 pF, 50 V, C0G Capacitors, 0603, 0.47 F, 16 V, X7R Capacitors, 0402, 3900 pF, 10 V, C0G Capacitors, 1210, 47 F, 16 V, X5R TDK TDK Murata Murata Murata C1005X5R1E103K050BA C2012X5R1E106M GRM1555C1H102JA01D GRM1555C1H471GA01D GRM31C5C1H104JA01 Murata Murata Murata GCM188R71C474KA55D GRM1557U1A392JA01D GRM32ER61C476ME15L Capacitor, 0603, 1500 pF, 50 V, C0G Capacitor, 0402, 1 F, 25 V, X6S Capacitors, 1206, 0.1 F, 50 V, C0G Capacitor, polarized, 100 F, 25 V Murata Murata Murata Panasonic GRM1885C1H152JA01D GRM155C81E105KE11 GRM31C5C1H104JA01L EEE-FC1E101P Rev. A | Page 64 of 115 ADRV-DPD1/PCBZ User Guide Designator D1, D4, D5 D2 D3 F1 FB1, FB2, FB3, FB4, FB5, FB6, FB7, FB8, FB9 FL1 J1, J2, J9, J10 J3, J4, J8, J13 J5, J6, J11, J12 J7 J14 J15, J26 J16 J20, J22 J21 J23, J28 J24 L3 L4, L5 LED1, LED2, LED5, LED7, LED8, LED9, LED11 LED12 Q1, Q2 R2, R4, R5, R7, R9, R13, R14, R16, R18, R20, R28, R29, R34, R36, R44, R49, R50, R71, R73, R74, R75, R76, R77, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R92, R93, R125, R126, R128, R130, R134, R137, R139, R141, R145, R146, R149, R150, R152, R154, R155, R156, R157, R158, R159, R160, R162, R164, R165, R166, R167, R168, R169, R170, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R191, R199, R200, R201, R202, R203, R205, R207, R209, R218, R219, R220, R221, R261, R262, R263, R277, R278, R279, R280, R281, R282, R283, R284, R303, R317, R321, R322, R323, R324, R325, R328, R371, R372 R8, R10, R11, R15, R48, R136 R12 UG-1238 Description Diodes, Schottky, 40 V, 5 A surface mount SMC Diode, Schottky, 30 V, 5 A surface mount TVS DIODE 13 VWM 27.2 VC SMB Surface mount fuse, 5 A VFA slimline, 1206 Ferrite, 120 EMI network filter, 50 M 25 V 15 A EMIFIL Headers 2 x 8 0.1 inches SMA connector jacks, female socket 50 MMCX vertical surface mount connectors 20-position header, unshrouded connector 0.05 inches DC power connectors power jacks 4-position 2.54 mm solder ST through holes 10 A and contacts Header 2 x 3 0.1 inches 100-position connector headers 160-position board to board connector 2-pin headers 400-position board to board connector Inductor, 15 H Inductor, 4.7 H Green LEDs, 2.2 V, 0603 Red LED, 1.8 V, 0603 MOSFETs N-channel 20 V 12 A Resistors, 0402, 0 Resistors, 0402, 100 Resistor, 0402, 430 k Rev. A | Page 65 of 115 Manufacturer On Semiconductor Part Number MBRS540T3G Micro Commercial Components STMicroelectronics Littlefuse SK53A-LTP SMBJ13A-TR 0466005.NR Murata Murata BLM18KG121TN1D BNX016-01 SAMTEC Cinch Technology TSW-108-08-G-D 142-0701-201 SAMTEC MMCX-J-P-H-ST-SM1 SAMTEC FTSH-110-01-L-DV-K CUI TE Connectivity PJ-102BH 282834-4 SAMTEC SAMTEC SAMTEC TSW-103-08-G-D ERF8-050-05.0-S-DV-K-TR ASP-134604-01 Amphenol Connex SAMTEC 69157-102 ASP-134488-01 Coilcraft Coilcraft Rohm Rohm Vishay Siliconix Rohm XAL4040-153MEB XAL6060-472MEB SML-310MTT86 SML-311UTT86 SIA448DJ-T1-GE3 MCR01MZPJ000 Rohm Rohm MCR01MZPF1000 MCR01MZPF4303 UG-1238 Designator R22, R25, R60, R65, R66, R67, R68, R69, R70, R97, R108, R114, R118, R120, R123, R143, R147, R148, R161, R163, R171, R194, R197, R198, R204, R210, R212, R213, R214, R216, R217, R225, R226, R227, R228, R229, R230, R231, R232, R235, R240, R244, R245, R249, R254, R256, R257, R258, R259, R264, R265, R266, R267, R268, R272, R273, R274, R275, R285, R287, R288, R289, R290, R291, R292, R293, R294, R311, R312, R315, R316, R320, R326, R331, R332, R334, R335, R336, R337, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R355, R356, R357, R358, R362, R363, R364, R365, R367, R368, R369, R370, R374, R376, R381, R382, R383, R384, R385 R23, R24 R30, R43, R54, R58, R59, R61, R62, R64, R115, R117, R121, R124, R153, R206, R208, R215, R233, R234, R250, R251, R252, R255, R271, R286, R314, R327, R329, R330, R333, R338, R353, R354, R359, R360, R361, R366, R375, R377 R32, R99, R101, R188, R189 R33, R100, R106, R127 R40, R42 R41, R91, R195, R196 R47, R56, R57, R72 R63 R78, R96 R94, R241 R95 R98, R187 R103, R151 R104, R109 R105, R111, R119, R192 R110 R112 R113 R122 R211 R319 T1, T2 U1 U2 U3 Y2 (U4) U5 U6, U13, U14, U18, U19, U21, U22, U35, U36, U37, U38 U7 U8 U9, U11, U15, U23, U24, U25, U27, U28, U30, U31, U32, U33, U34 ADRV-DPD1/PCBZ User Guide Description Resistors, 0402, 10 k Manufacturer Rohm Part Number MCR01MZPF1002 Resistors, 0402, 390 Resistors, 0402, 1 k Rohm Rohm MCR01MZPF3900 MCR01MZPF1001 Resistors, 0402, 2.7 k Resistors, 0402, 51 k Resistors, 0402, 100 k Resistors, 1206, 0 Resistors, 0402, 1 M Resistor, 0402, 332 Resistors, 0603, 1.0 k Current sense resistors, 0.05 Resistor, 1206, 1.5 k Resistors, 0402, 51.1 k Resistors, 0402, 10 k Resistors, 0402, 13 k Resistors, 0402, 200 Resistor, 0402, 39 k Resistor, 2512, 0.1 Resistor, 0402, 3.9 k Resistor, 0402, 220 Resistor, 0402, 680 Resistor, 0603, 0 4.5 MHz to 3000 MHz, 1:1 transmission line transformers IC clock generator, 1.25 GHz VCO Buffer, noninverting, 3 element, 1 bit per element General-purpose amplifier, 1 circuit, rail to rail VCXO oscillator 122.880 MHz, 14 x 9 mm IC EEPROM 2 kB 400 KHz Buffers and line drivers quad bus buffer gate Single 2-input positive-OR gate Hex buffer/driver with open drain output TVS diodes, 3.3 VWM, 17 VC Rohm Rohm Rohm Rohm Rohm Rohm Koa Speer Ohmite Rohm Panasonic Vishay Dale Rohm Rohm Panasonic Vishay Dale Rohm Rohm Rohm Rohm Macom MCR01MZPF2701 MCR01MZPF5102 MCR01MZPF1003 MCR18EZPJ000 MCR01MZPF1004 MCR01MZPF3320 RK73H1JTTD1001F LVK12R050DER MCR18EZPJ152 ERA-2AEB5112X TNPW040210K0BEED MCR01MZPF1302 MCR01MZPF2000 ERA-2AEB393X WSLT2512R1000FEA MCR01MZPJ392 MCR01MZPF2200 MCR01MZPF6800 MCR03EZPJ000 MABA-007159-000000 Analog Devices Texas Instruments AD9528BCPZ SN74LVC3G34DCUR Analog Devices AD8605ARTZ Abracon ABLNO-V-122.880MHZ ST Microelectronics Texas Instruments M24C02-WDW6TP SN74AUC125RGYR Texas Instruments Texas Instruments SN74LVC1G32DRL SN74AUC07RGYR Diodes Inc. D1213A-04SO-7 Rev. A | Page 66 of 115 ADRV-DPD1/PCBZ User Guide Designator U10, U12 U16, U26 U17 U20 U29, U39 PCB1 UG-1238 Description Single Schmitt trigger buffers High voltage, current shunt monitors Quad buck regulator integrated power solution Linear voltage regulator IC positive fixed Decoders/demultiplexers 1 x 3:8 31112258_Interposer_PCB_Rev1.0 Manufacturer Texas Instruments Analog Devices Part Number SN74AUC1G17DRLR AD8211YRJZ-RL7 Analog Devices ADP5054ACPZ Analog Devices ADM7154ARDZ-3.3 Texas Instruments Benetel SN74LVC138ARGYR 31112258_Rev1.0 Manufacturer Farnell Farnell Farnell Mouser Farnell Benetel Part Number 1419986 1624024 1377551 761-M1304-3005-AL 2505007 31322366 Table 26. ADRV-INTERPOS1/PCBZ Mechanical Bill of Materials Designator H1, H2, H3, H4, H5, H6, H7, H8 H9, H10, H11, H12, H13, H14, H15, H16 H17, H18, H19, H20, H21, H22, H23, H24 H25, H26, H27, H28, H29, H30, H31, H32 HW13, HW14, HW15 HW16 Description Screws, M3, 6 mm long, pozi pan Washers, lock, M3 Washers, plain M3 7 mm metric standoffs 2 way headers Cable, power Table 27. ADRV-INTERPOS1/PCBZ Empty Pads (Do Not Fit) Designator C24, C27, C31, C42, C87 Description Capacitors, 0402 D6, D7 3 A, low VF mega Schottky barrier rectifiers, 40 V Resistors, 0402 R1, R3, R6, R17, R19, R21, R26, R27, R31, R35, R37, R38, R39, R45, R46, R51, R52, R53, R55, R89, R90, R102, R107, R116, R129, R132, R133, R135, R138, R140, R142, R144, R190, R193, R302, R304, R313, R378, R379, R380 Y1 (U4) J17, J18, J27, J32 VCXO oscillator 122.880 MHz 5 mm x 9 mm option Headers 1 x 2 0.1" Rev. A | Page 67 of 115 Manufacturer Murata (Recommended) NXP Part Number Not applicable PMEG4030ER Rohm (Recommended) Not applicable Taiten A0145-O-002-3122.88000MHz SAMTEC TSW-102-08-G-S UG-1238 ADRV-DPD1/PCBZ User Guide INTERPOSER BOARD SCHEMATICS QUAD BUCK REGULATOR RED 16493-270 1-2 OFF 3-4 AUTOMATIC 5-6 ON Figure 70. ADP5054 Connections FMCA_VCC_12P0V +12V INPUT FROM EXTERNAL PSU 1 2 3 R91 0 F1 FL1 BIAS CB CG CG 3 PSG CG DC POWER FILTER 1 5A D1 D3 Figure 71. Power Supply Connector Rev. A | Page 68 of 115 2 4 6 5 D2 C61 100F TP21 VIN_DC LED5 R95 1.5k 16493-271 J14 GND GND UG-1238 +5.1V SENSE +5.1V ADRV-DPD1/PCBZ User Guide J15 4 3 2 1 TERMINAL BLOCK FOR EXTERNAL 5.1V INPUT D4 VCC_5V1_SENSE_B R98 R99 FB1 2.7k 51.1k0.1% C65 J27 1 0.10F R133 DNF R103 10k 0.1% 5.10V 2.0A 2 R101 2.7k R302 DNF DNF VCC_5V1_B R195 FB6 0 L5 D5 D4 D3 D2 D1 SW1 R241 C75 120 C71 47F C72 47F C73 47F C74 47F R105 200 0.05 47F 4.7H V+ LED7 VIN+ 3 DL1 G S2 S1 VIN- 4 R107 DNF FOR CORRECT CURRENT SENSE OPERATION, THE + AND - INPUTS MUST BE FLIPPED Figure 72. RF A Power Supply Connection Rev. A | Page 69 of 115 5 U16 AD8211 2 GND ISENSE_5V1_B 1 OUT R78 1.0k 16493-272 Q1 GND +5.1V GND ADRV-DPD1/PCBZ User Guide +5.1V SENSE UG-1238 J26 TERMINAL BLOCK FOR 4 3 2 1 EXTERNAL 5.1V INPUT D5 VCC_5V1_SENSE_B R187 R188 51.1k 0.1% 2.7k FB2 C106 J32 1 0.10F R190 DNF 5.10V 2.0A 2 R90 DNF R189 2.7k DNF R151 10k 0.1% VCC_5V1_B FB9 R196 0 D5 D4 D3 D1 C109 47F 47F SW2 D2 120 C108 L4 R94 C110 47F 0.05 R192 200 C111 47F C112 47F 4.7H V+ U26 Q2 LED11 5 VIN+ 3 ISENSE_5V1_B G 1 OUT AD8211 VIN- 4 FOR CORRECT CURRENT SENSE OPERATION, THE + AND - INPUTS MUST BE FLIPPED R96 1.0k 2 GND 16493-273 S2 R193 DNF S1 DL2 Figure 73. RF B Power Supply Connection U25 2 CH1 CH2 CH3 VN 16493-274 1 6 REF_A REF_B REFB+ REFB- VP CH4 5 CH1 CH2 2 1 3 6 CH3 VN CH4 VP 4 5 CH1 CH2 CH3 2 1 3 4 6 VN 3 U24 VP CH4 5 VDD_IF VDD_IF U15 4 VDD_IF REFA+ REFA- Figure 74. Clock ESD Protection VCC_3V3_CLK FB1 FB2 120 120 C23 1000pF TP6 C22 10F 16493-275 VCC_3V3 Figure 75. Clock Power Filter VCC_3V3_CLK C2 0.10F C3 0.10F C4 0.10F C5 0.10F C6 0.10F C7 0.10F C8 C9 0.10F 0.10F C10 0.10F C11 C12 0.10F 0.10F C13 C14 0.10F 0.10F C15 C16 C17 0.10F 0.10F 0.10F C18 C19 C20 0.10F 0.10F 0.10F 16493-276 C1 1.0F Figure 76. Clock Power Decoupling Rev. A | Page 70 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 R49 R44 CLK_A+ CLK_B+ 0 T2 R53 DNF 0.1F CLK_A- CLK_B- R72 1M 16493-277 0.1F R47 1M C118 30.72MHz EXT REF 3 R46 DNF 4 4 C51 10.00MHz EXT REF T1 J13 3 J8 R52 DNF 1 5 R45 DNF 1 5 0 Figure 77. Clock Input Baluns R2 OUT1+ J3 FPGA_REF_CLK_A+ 0 C28 FPGA CLK INPUTS SELF BIASED AT 0.8V R3 ROUTE DIFFERENTIAL 100 TRACE DNF R4 FPGA_REF_CLK_A- 0 OUT1- OUT7+ 0.01uF R48 100 R56 1M J4 C29 OUT7- 0.01uF R7 OUT3+ 0 R8 100 R9 OUT3- R57 1M FPGA_SYSREF+ ROUTE DIFFERENTIAL 100 TRACE FPGA_SYSREF- 0 J6 R17 DNF R18 R134 OUT4+ R135 DNF OUT4- 0 R5 OUT10+ FPGA_REF_CLK_B+ FPGA_REF_CLK_B- 0 DEV_CLK_B+ 0 FPGA CLK INPUTS SELF BIASED AT 0.8V ROUTE DIFFERENTIAL 100 TRACE ROUTE DIFFERENTIAL 100 TRACE R19 DNF R20 OUT10- DEV_CLK_B- 0 J5 R21 DNF R14 OUT6+ 0 R15 100 R16 OUT6- SYSREF_B+ ROUTE DIFFERENTIAL 100 TRACE SYSREF_B- 0 J11 R138 DNF R139 OUT13+ R13 OUT12+ 0 R136 100 R137 OUT12- 0 SYSREF_A+ R140 DNF ROUTE DIFFERENTIAL 100 TRACE SYSREF_A- 0 DEV_CLK_A+ ROUTE DIFFERENTIAL 100 TRACE R141 OUT13- DEV_CLK_A- 0 J12 R142 DNF C24 DIR_CLK+ DNF TP12 C25 REFA+ CLK_A+ 0.10F TP13 REFB+ 0.10F C26 R11 100 REFA- 0.10F C117 C27 CLK_B- DIR_CLK- REFB- TP23 DNF Figure 78. Differential Lines Rev. A | Page 71 of 115 0.10F 16493-278 CLK_A- TP22 C115 CLK_B+ R10 100 UG-1238 ADRV-DPD1/PCBZ User Guide VCXO_CTRL_2 VCC_3V3_CLK PLL1 LOOP FILTER 1 10 16 20 27 30 33 36 39 42 45 48 51 54 60 63 66 69 72 R12 430k C34 100000pF U1 C35 100000pF OUT0 OUT0 R6 DNF VCXO_VT VCXO_IN VCXO_IN 2 REFA+ REFB 6 REFB- REFB 4 SYSREF_REQ SYSREF_IN SYSREF_IN 7 14 21 19 22 15 SPI_PLL_CS_3V3 CLK_RESET_3V3 SPI_CLK_3V3 PLL2 LOOP FILTER 55 56 OUT8 OUT8 OUT9 OUT9 OUT10 OUT10 OUT11 OUT11 STATUS0 STATUS1 OUT12 OUT12 OUT13 OUT13 EPAD SDIO/SDA SDO 64 65 OUT1+ OUT1- 61 62 58 59 52 53 OUT3+ OUT3- OUT4+ OUT4- 49 50 46 47 43 44 OUT6+ OUT6- OUT7+ OUT7- 40 41 37 38 34 35 OUT10+ OUT10- 31 32 28 29 25 26 23 24 OUT12+ OUT12- OUT13+ OUT13- SPI_MOSI_3V3 SPI_DOUT_9528_3V3 EPAD NC NC 18 GND R171 10k 17 R97 10k OUT7 OUT7 LF1 LF2_CAP CS RESET SCLK/SCL LDO_VCO GND C36 0.47F C31 DNF OUT6 OUT6 JESD204B CLOCK GENERATOR 9 C30 470pF OUT5 OUT5 AD9528 REF_SEL 57 70 71 CLK_SYSREF_REQUEST_3V3 SYSREF_FROM_FPGA+ SYSREF_FROM_FPGA- OUT4 OUT4 REFA 5 REFB+ OUT3 OUT3 REFA 3 REFA- OUT2 OUT2 13 VCXO_CTRL_1 VCXO+ VCXO- OUT1 OUT1 8 11 12 67 68 VCC_3V3 C52 TP10 U2 TP11 1 3 R143 10k 6 R22 10k 1A VCC 1Y 2A 2Y 3A 3Y GND 8 7 0.10F 5 2 4 R23 390 R25 10k LED1 STATUS 1 R24 390 LED2 STATUS 0 Figure 79. AD9528 Clock Generator Connections Rev. A | Page 72 of 115 16493-279 C32 470pF VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C33 1000pF ADRV-DPD1/PCBZ User Guide UG-1238 3P3VAUX R1 DNF R144 DNF R39 DNF 1 2 3 4 EEPROM_A0 EEPROM_A1 R40 100k R42 100k C47 1F U5 E0 E1 E2 VSS VCC WC SCL SDA 8 7 6 5 FMC_I2C_SCL FMC_I2C_SDA R43 1k VCC_3V3_VCXO VCC_3V3 FB4 FB5 R41 120 120 0 C50 1000pF C48 47F C49 47F C38 47F C55 47F C114 47F VCC_3V3_VCXO VCON TRI_STATE TP17 PCB REFERENCE DESIGNATOR IS U4 Y2 6 1 POS_VS VCNTRL 2 4 EN_DISABLE O/P 3 5 GND NC TP18 OUT COMP_VOUT ABLNO-V-122.880MHZ FOOTPRINT OVERLAP IN LAYOUT FOR CRYSTAL PACKAGE OPTION Figure 80. Oscillator and EEPROM Connection Rev. A | Page 73 of 115 16493-280 TP16 UG-1238 ADRV-DPD1/PCBZ User Guide R26 VCXO_CTRL_1 DNF VCC_3V3_VCXO C39 FB3 120 1.0F 5 U3 R33 VCXO_CTRL_2 3 51k - AD8605 R32 1 VCON 2.7k + 2 4 C45 1500pF VCC_3V3_VCXO C41 1000pF C40 0.10F R30 1k Y1 1 VCON 2 TRISTATE 3 R35 DNF DNF VCON VDD TRISTATE OUT GND COMP_VOUT 6 4 OUT 5 COMP_VOUT A0145-O-002-3-122.88000MHz C43 C44 100000pF 100000pF R27 R28 0 R29 R37 R36 0 DNF SHARE PADS R34 C42 COMP_VOUT VCXO- 0 R31 DNF 0 DNF C46 0.10F VCXO+ TP34 R38 SHARE PADS DNF Figure 81. Oscillator Buffer and Optional Alternative Oscillator Rev. A | Page 74 of 115 DIR_CLK+ 16493-281 OUT DIR_CLK- DNF TP33 ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF VDD_IF R233 1k R206 1k R208 R255 1k 1k R69 10k U39 1 2 3 4 5 6 FMC_SPI_CS0 FMC_SPI_CS1 FMC_SPI_CS2 FMC_SPI_CS3 FMC_SPI_CS4 16 15 14 13 12 11 10 9 7 A VCC B Y0 C Y1 G2A Y2 G2B Y3 G1 Y4 Y5 GND Y6 GND Y7 8 17 TP27 SPI_DRV1_CS_A SPI_DRV2_CS_A SPI_SPARE_CS2 SPI_EEPROM_CS_A SPI_SPARE_CS0 SPI_PLL_CS SPI_MYK_CS_A TP8 VDD_IF U29 FMC_SPI_CS4 FMC_SPI_CS3 R311 10k R312 10k 16 15 14 13 12 11 10 9 7 A VCC B Y0 C Y1 G2A Y2 G2B Y3 G1 Y4 Y5 GND Y6 GND Y7 8 17 TP40 SPI_DRV1_CS_B SPI_DRV2_CS_B SPI_SPARE_CS3 SPI_EEPROM_CS_B SPI_SPARE_CS1 TP41 SPI_MYK_CS_B 16493-282 1 2 3 4 5 6 FMC_SPI_CS0 FMC_SPI_CS1 FMC_SPI_CS2 Figure 82. SPI Chip Select Decoder VDD_IF 2 GP_INTERRUPT_A 5 FMC_SPI_MOSI 9 12 FMC_RESET_A R380 DNF R194 10k 15 R65 10k 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND R268 10k R267 10k 13 4 1 10 3OE 2OE R379 DNF 1OE VCC 14 VDD_IF R266 10k 4OE R265 10k C129 1.0F GND 3 FMC_GP_INTERRUPT_A 6 SPI_MOSI 8 11 RESET_A 7 U13 VDD_IF 9 FMC_TEST 12 RF_PRESENCE_N_A R64 1k 15 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND R204 10k 4OE 10 3OE 2OE 4 R198 10k GND U38 Figure 83. RF A General Buffers Rev. A | Page 75 of 115 3 6 8 11 7 TDD1_SWITCH_A TDD2_SWITCH_A TEST_A FMC_RF_PRESENCE_N_A 16493-283 5 FMC_TDD2_SWITCH_A 1OE 1 VCC 2 FMC_TDD1_SWITCH_A R197 10k 13 R264 10k C128 1.0F 14 R147 10k UG-1238 ADRV-DPD1/PCBZ User Guide VDD_IF R60 10k R67 10k R275 10k R58 1k C54 1.0F R68 10k SPI_PLL_CS FMC_CLK_RESET FMC_CLK_SYSREF_REQUEST FMC_SPI_MOSI VCC_3V3 VDD_IF R59 1k R61 R62 1k 1k U8 1 3 5 9 11 13 R163 7 10k 14 2 4 TP29 6 8 TP31 10 12 15 VCC 1Y 2Y 3Y 4Y 5Y 6Y GND 1A 2A 3A 4A 5A 6A GND TP28 SPI_PLL_CS_3V3 CLK_RESET_3V3 CLK_SYSREF_REQUEST_3V3 SPI_MOSI_3V3 TP30 BUFFER, OPEN-DRAIN OUTPUT VDD_IF SPI_CLK 1 FMC_SPI_CLK 2 3 U10 NC A C132 1.0F VCC Y GND 5 4 VCC_3V3 VCC_3V3 TP35 SCHMITT TRIGGER BUFFER R63 332 U12 1 NC VCC 2 A Y 3 GND BYPASS SPI_MISO U7 1 SPI_MYK_CS_A 2 SPI_MYK_CS_B 3 A 4 VDD_IF DNF VCC 5 B GND R66 10k 4 Y SPI_CLK_3V3 C53 0.10F SCHMITT TRIGGER BUFFER FMC_SPI_MISO C56 1.0F TP32 5 C125 0.10F OR GATE VDD_IF SPI_PLL_CS 5 9 12 R161 10k R210 10k 15 13 1Y 2A 2Y 3A 3Y 4A 4Y GND C127 1.0F 4OE 10 3OE 1 4 2OE 1A U14 R108 10k GND 3 8 11 7 LINE DRIVING BUFFER Figure 84. General Buffers Rev. A | Page 76 of 115 FMC_SPI_MISO 6 16493-284 2 SPI_MISO SPI_DOUT_9528_3V3 1OE VCC 14 R70 10k ADRV-DPD1/PCBZ User Guide UG-1238 2 FMC_TDD1_SWITCH_B 5 FMC_TDD2_SWITCH_B 9 12 RF_PRESENCE_B 15 R244 10k 13 3OE 2OE 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND U18 R214 10k 4OE 4 R213 10k 10 R212 10k 1 R240 10k 1OE C57 1.0F VCC R148 10k 14 VDD_IF GND 3 TDD1_SWITCH_B 6 TDD2_SWITCH_B 8 11 FMC_RF_PRESENCE_B 7 LINE DRIVING BUFFER VDD_IF 5 FMC_RESET_B FMC_TEST 9 GP_INTERRUPT_B 12 15 R378 DNF R254 10k R215 1k 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND U19 GND LINE DRIVING BUFFER Figure 85. RF B General Buffers Rev. A | Page 77 of 115 R259 10k 13 10 3OE 4 1 R258 10k 3 6 8 11 RESET_B TEST_B FMC_GP_INTERRUPT_B 7 16493-285 2 2OE R51 DNF 1OE 14 VCC VDD_IF R257 10k 4OE R256 10k C130 1.0F ADRV-DPD1/PCBZ User Guide VDD_IF GPIO15_A VDD_IF U28 VN CH2 CH1 1 CH1 VN VP 2 1 3 4 6 CH3 U30 6 CH1 CH2 CH3 CH4 VP 5 2 CH4 5 CH1 GPIO14_A GPIO11_A 1 GPIO13_A GPIO10_A 2 1 6 GPIO12_A GPIO9_A VN VP CH4 CH1 1 CH2 3 CH3 4 CH4 6 GPIO8_A 2 U27 5 CH2 2 VN 3 VDD_IF U9 5 VP CH2 GPIO7_A 3 GPIO6_A GPIO3_A 3 CH4 GPIO5_A GPIO2_A CH3 GPIO4_A GPIO1_A VN VP CH3 GPIO0_A VDD_IF U23 6 CH1 CH2 1 CH3 3 CH4 4 6 5 2 VN VP 4 VDD_IF U11 5 4 VDD_IF 4 UG-1238 GPIO16_A GPIO0_B GPIO17_A GPIO1_B GPIO18_A GPIO2_B GPIO3_B U32 2 CH1 VN VP CH4 CH1 5 GPIO4_B 1 3 4 6 1 CH2 3 CH4 4 6 VDD_IF 2 CH2 VN VP CH3 U31 5 CH3 VDD_IF GPIO8_B GPIO5_B GPIO9_B GPIO6_B GPIO10_B GPIO7_B GPIO11_B VDD_IF U33 U34 GPIO16_B GPIO14_B GPIO17_B GPIO15_B GPIO18_B Figure 86. GPIO ESD Protection Rev. A | Page 78 of 115 CH1 1 CH2 3 2 16493-286 GPIO13_B CH3 CH4 GPIO12_B VN VP 4 5 6 CH2 CH3 VDD_IF 1 3 4 6 2 CH1 VN VP CH4 5 ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF R349 10k 5 FMC_TX2_ENABLE_A 9 FMC_RX1_ENABLE_A 12 FMC_RX2_ENABLE_A R382 10k R383 10k R384 10k R385 10k 15 13 4OE 10 4 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND 3 R360 1k 6 R361 1k 8 R377 1k 11 R366 1k TX1_ENABLE_A TX2_ENABLE_A RX1_ENABLE_A RX2_ENABLE_A 7 GND U37 R352 10k R351 10k 3OE 2OE VCC 2 FMC_TX1_ENABLE_A R350 10k 1OE 1 14 C116 1.0F LINE DRIVING BUFFER R367 10k R368 10k R369 R370 10k 10k VDD_IF R225 10k 5 FMC_TX2_DRV_EN_A 9 FMC_RX1_LNA_ENABLE_A 12 FMC_RX2_LNA_ENABLE_A R229 10k R230 10k R231 10k R232 10k 15 4OE 13 10 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND U6 R228 10k R227 10k 3OE 4 2OE 1OE VCC 2 FMC_TX1_DRV_EN_A R226 10k 1 14 C58 1.0F GND 3 R234 1k 6 R250 1k 8 R251 1k 11 R252 1k TX1_DRV_EN_A TX2_DRV_EN_A RX1_LNA_ENABLE_A RX2_LNA_ENABLE_A 7 LINE DRIVING BUFFER R272 10k R273 10k R274 10k R285 10k VDD_IF 5 FMC_TX2_PA_ENABLE_A 9 12 R331 10k R287 10k R288 10k 15 1A 1Y 2A 2Y 3A 3Y 4A GND U21 R249 10k 13 10 3OE 4 2OE 1 R217 10k 4Y GND 3 R271 1k 6 R286 1k TX1_PA_ENABLE_A TX2_PA_ENABLE_A 8 11 7 LINE DRIVING BUFFER R289 10k R290 10k 16493-287 R320 10k 1OE 14 VCC 2 FMC_TX1_PA_ENABLE_A R216 10k 4OE R235 10k C59 1.0F Figure 87. RF A Enable Buffers Rev. A | Page 79 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide VDD_IF 9 FMC_RX1_ENABLE_B 12 FMC_RX2_ENABLE_B R358 10k R362 10k R374 10k 13 2A 2Y 3A 3Y 4Y 3 R353 1k 6 R354 1k 8 R359 1k 11 R375 1k TX1_ENABLE_B TX2_ENABLE_B RX1_ENABLE_B RX2_ENABLE_B 7 GND GND U36 R346 10k 4OE 10 3OE 1 1OE 1Y 4A 15 R381 10k R345 10k 1A 5 FMC_TX2_ENABLE_B 2OE 14 VCC 2 FMC_TX1_ENABLE_B R344 10k 4 R343 10k C89 1.0F LINE DRIVING BUFFER R363 10k R364 10k R376 10k R365 10k VDD_IF 5 FMC_TX2_DRV_EN_B 9 FMC_RX1_LNA_ENABLE_B 12 FMC_RX2_LNA_ENABLE_B R332 10k R347 10k R348 10k 15 R355 10k 4OE 1A 1Y 2A 2Y 3A 3Y 4A 4Y GND GND U22 R294 10k 13 10 R293 10k 3OE 2OE 1OE 1 14 VCC 2 FMC_TX1_DRV_EN_B R292 10k 4 R291 10k C60 1.0F 3 R314 1k 6 R327 1k 8 R329 1k 11 R330 1k TX1_DRV_EN_B TX2_DRV_EN_B RX1_LNA_ENABLE_B RX2_LNA_ENABLE_B 7 LINE DRIVING BUFFER R334 10k R335 10k R336 10k R337 10k VDD_IF FMC_TX2_PA_ENABLE_B 9 12 R356 10k R357 10k R340 10k R339 10k 15 13 1A 1Y 2A 2Y 3A 3Y 4A GND U35 R245 10k 4OE 10 3OE 2OE 4 R326 10k 4Y GND LINE DRIVING BUFFER Figure 88. RF B Enable Buffers Rev. A | Page 80 of 115 3 R333 1k 6 R338 1k TX1_PA_ENABLE_B TX2_PA_ENABLE_B 8 11 7 R341 10k R342 10k 16493-288 5 1OE 14 VCC 2 FMC_TX1_PA_ENABLE_B R316 10k 1 R315 10k C88 1.0F ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF 1 3 5 7 9 11 13 15 TX1_DRV_EN_A TX2_DRV_EN_A FMC_SPI_CLK FMC_SPI_MISO FMC_SPI_MOSI ISENSE_5V1_A J10 2 4 6 8 10 12 14 16 R129 DNF SPI_DRV1_CS_A SPI_DRV2_CS_A SPI_MOSI SPI_MISO SPI_CLK FMC_RESET_A TEST_A VDD_IF RX1_ENABLE_A RX2_ENABLE_A GPIO0_A GPIO1_A GPIO2_A GPIO3_A TDD2_SWITCH_A 0 0 0 0 R81 R83 R85 R125 J2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 TX1_ENABLE_A TX2_ENABLE_A RX1_LNA_ENABLE_A RX2_LNA_ENABLE_A TX1_PA_ENABLE_A TX2_PA_ENABLE_A TDD1_SWITCH_A VDD_IF J1 TX2_DRV_EN_B FMC_SPI_CS0 FMC_SPI_CS1 FMC_SPI_CS2 FMC_SPI_CS3 FMC_SPI_CS4 1 3 5 7 9 11 13 15 ISENSE_5V1_B 2 4 6 8 10 12 14 16 R89 DNF TX1_DRV_EN_B SPI_DRV1_CS_B SPI_DRV2_CS_B FMC_I2C_SDA FMC_I2C_SCL FMC_RESET_B TEST_B VDD_IF RX1_ENABLE_B RX2_ENABLE_B GPIO0_B GPIO1_B GPIO2_B GPIO3_B TDD2_SWITCH_B R82 R84 R86 R126 0 0 0 0 1 3 5 7 9 11 13 15 J9 2 4 6 8 10 12 14 16 TX1_ENABLE_B TX2_ENABLE_B RX1_LNA_ENABLE_B RX2_LNA_ENABLE_B TX1_PA_ENABLE_B TX2_PA_ENABLE_B TDD1_SWITCH_B VDD_IF TP4 TP38 DNF DNF 1 3 5 7 9 11 13 15 17 19 JTAG J7 2 TMS R73 4 TCLK R75 6 TDO R77 TDI R79 8 10 12 14 16 TRST R87 18 20 0 0 0 0 GPIO7_A GPIO18_A GPIO5_A GPIO6_A 0 GPIO4_A 16493-289 R127 51k Figure 89. Header Pin Connectors Rev. A | Page 81 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide J20 SYNCINB0_A- SYNCINB0_A+ SYSREF_A- SYSREF_A+ DEV_CLK_A- DEV_CLK_A+ TX2_ENABLE_A RX2_ENABLE_A RF_PRESENCE_A TX1_DRV_EN_A TX2_DRV_EN_A RX1_ENABLE_A RX1_LNA_ENABLE_A RX2_LNA_ENABLE_A TX1_ENABLE_A TX1_PA_ENABLE_A TX2_PA_ENABLE_A RF MODULE A EEPROM WP GPIO17_A J23 SPI_EEPROM_CS_A SPI_DRV2_CS_A SPI_DRV1_CS_A SPI_MYK_CS_A SPI_CLK SPI_MOSI SPI_MISO GP_INTERRUPT_A RESET_A GPIO0_A GPIO1_A GPIO2_A GPIO3_A VDD_IF VCC_5V1_A 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 SERDOUT3_A- SERDOUT3_A+ SERDOUT1_A- SERDOUT1_A+ SERDOUT2_A- SERDOUT2_A+ SERDOUT0_A- SERDOUT0_A+ SERDIN2_A- SERDIN2_A+ SERDIN0_A- SERDIN0_A+ SERDIN3_A- SERDIN3_A+ SERDIN1_A- SERDIN1_A+ SYNCOUTB0_A- SYNCOUTB0_A+ GPIO11_A GPIO12_A GPIO13_A GPIO14_A GPIO15_A GPIO8_A GPIO9_A GPIO10_A GPIO4_A GPIO5_A GPIO6_A GPIO7_A GPIO18_A TEST_A VCC_5V1_A VCC_5V1_SENSE_A REMOTE +5V SENSE ON RADIO BOARD 16493-290 SYNCINB1_A- SYNCINB1_A+ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Figure 90. RF A 100-Pin Connector Rev. A | Page 82 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 J22 SYNCINB0_B- SYNCINB0_B+ SYSREF_B- SYSREF_B+ DEV_CLK_B- DEV_CLK_B+ TX2_ENABLE_B RX2_ENABLE_B RF_PRESENCE_B TX1_DRV_EN_B TX2_DRV_EN_B RX1_ENABLE_B RX1_LNA_ENABLE_B RX2_LNA_ENABLE_B TX1_ENABLE_B TX1_PA_ENABLE_B TX2_PA_ENABLE_B RF MODULE B EEPROM_WP GPIO17_B J28 SPI_EEPROM_CS_B SPI_DRV2_CS_B SPI_DRV1_CS_B SPI_MYK_CS_B SPI_CLK SPI_MOSI SPI_MISO GP_INTERRUPT_B RESET_B GPIO0_B GPIO1_B GPIO2_B GPIO3_B VDD_IF VCC_5V1_B 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 SERDOUT3_B- SERDOUT3_B+ SERDOUT1_B- SERDOUT1_B+ SERDOUT2_B- SERDOUT2_B+ SERDOUT0_B- SERDOUT0_B+ SERDIN2_B- SERDIN2_B+ SERDIN0_B- SERDIN0_B+ SERDIN3_B- SERDIN3_B+ SERDIN1_B- SERDIN1_B+ SYNCOUTB0_B- SYNCOUTB0_B+ GPIO11_B GPIO12_B GPIO13_B GPIO14_B GPIO15_B GPIO8_B GPIO9_B GPIO10_B GPIO4_B GPIO5_B GPIO6_B GPIO7_B GPIO18_B TEST_B VCC_5V1_B VCC_5V1_SENSE_B REMOTE +5V SENSE ON RADIO BOARD 16493-291 SYNCINB1_B- SYNCINB1_B+ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Figure 91. RF B 100-Pin Connector Rev. A | Page 83 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide J24A 0.10F C91 0.10F C92 SERDOUT1_A+ SERDOUT1_A- C94 0.10F C97 0.10F C96 SERDOUT3_A+ SERDOUT3_A- C100 SERDOUT0_B+ SERDOUT0_B- 0.10F 0.10F 0.10F C101 C104 SERDOUT1_B+ SERDOUT1_B- 0.10F 0.10F 0.10F C105 SERDIN3_A+ SERDIN3_A- SERDIN0_A+ SERDIN0_A- SERDIN2_A+ SERDIN2_A- SERDIN0_B+ SERDIN0_B- SERDIN1_B+ SERDIN1_B- B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 0.10F C98 SERDOUT2_B+ SERDOUT2_B- 0.10F C99 0.10F C102 0.01F C62 C113 SERDOUT3_B+ SERDOUT3_B- 0.10F C103 0.01F FPGA_REF_CLK_A+ FPGA_REF_CLK_A- SERDIN2_B+ SERDIN2_B- SERDIN3_B+ SERDIN3_B- 16493-292 C90 SERDOUT0_A+ SERDOUT0_A- A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 Figure 92. FMC HPC Row A and Row B J24B SERDIN1_A+ SERDIN1_A- FMC_TX1_DRV_EN_A FMC_TX2_DRV_EN_A FMC_SPI_CS3 FMC_SPI_CS4 FMC_TX2_ENABLE_A FMC_RX2_ENABLE_A GPIO6_A GPIO7_A C95 0.10F R145 R146 0 0 R149 R71 0 0 R178 R179 0 0 R167 R76 0 0 FMC_TDD1_SWITCH_A FMC_TDD2_SWITCH_A FMC_I2C_SCL FMC_I2C_SDA R160 R162 0 0 EEPROM_A0 FMCA_VCC_12P0V D7 D6 DNF DNF 3P3V D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 PG_C2M SIGNAL FROM EVAL-TPG-ZYNQ3 C123 0.01uF C21 0.01uF ADP5054_EN FPGA_REF_CLK_B+ FPGA_REF_CLK_B- R181 R183 0 0 R184 R185 0 0 FMC_TEST GPIO18_A R186 R328 0 0 FMC_SPI_CS0 FMC_SPI_CS1 R150 R152 0 0 FMC_TX1_ENABLE_A FMC_RX1_ENABLE_A R92 R74 0 0 FMC_TX2_ENABLE_B FMC_RX2_ENABLE_B R154 R155 0 0 R158 R159 0 0 R50 0 SYSREF_FROM_FPGA+ SYSREF_FROM_FPGA- FMC_RX1_LNA_ENABLE_A FMC_RX2_LNA_ENABLE_A FMC_CLK_RESET FMC_CLK_SYSREF_REQUEST JTAG_TDI JTAG_TDO 3P3VAUX EEPROM_A1 3P3V 3P3V 3P3V TP39 16493-293 SERDOUT2_A+ SERDOUT2_A- 0.10F C93 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 Figure 93. FMC HPC Row C and Row D Rev. A | Page 84 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 FPGA_SYSREF+ FPGA_SYSREF- SYNCINB0_A+ SYNCINB0_A- FMC_SPI_MISO FMC_SPI_CS2 FMC_TX1_ENABLE_B FMC_RX1_ENABLE_B GPIO2_A GPIO3_A GPIO4_B GPIO5_B GPIO0_B GPIO1_B R156 R321 0 0 R322 R169 0 0 R157 R164 0 0 R80 R203 0 0 R205 R128 0 0 SYNCINB1_A+ SYNCINB1_A- GPIO6_B GPIO7_B SYNCINB1_B+ SYNCINB1_B- FMC_TX1_PA_ENABLE_B FMC_TX2_PA_ENABLE_B R180 R283 FMC_VDD_IF 0 0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 FMC_RF_PRESENCE R168 0 SYNCOUTB0_A+ SYNCOUTB0_A- R303 R170 0 0 R172 R173 0 0 FMC_RESET_A FMC_GP_INTERRUPT_A FMC_SPI_CLK FMC_SPI_MOSI SYNCOUTB0_B+ SYNCOUTB0_B- R177 R209 0 0 GPIO0_A GPIO1_A R219 R220 0 0 GPIO2_B GPIO3_B R323 R324 0 0 GPIO4_A GPIO5_A R174 R221 0 0 R175 R325 0 0 FMC_TX1_PA_ENABLE_A FMC_TX2_PA_ENABLE_A FMC_RX1_LNA_ENABLE_B FMC_RX2_LNA_ENABLE_B SYNCINB0_B+ SYNCINB0_B- R176 R284 0 0 FMC_VDD_IF Figure 94. FMC HPC Row G and Row H Rev. A | Page 85 of 115 FMC_TX1_DRV_EN_B FMC_TX2_DRV_EN_B 16493-294 J24D UG-1238 ADRV-DPD1/PCBZ User Guide GPIO12_A GPIO13_A GPIO9_B GPIO10_B GPIO18_B R317 R282 0 0 R261 R262 0 0 R263 0 FMC_VDD_IF K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 R304 DNF FMC_RF_PRESENCE_A FMC_RF_PRESENCE_B R165 R166 0 0 R88 R218 0 0 FMC_RESET_B FMC_GP_INTERRUPT_B GPIO8_B GPIO15_B 3P3V GPIO10_A GPIO11_A GPIO16_A GPIO17_A GPIO13_B GPIO14_B TP9 VDD_IF C119 47F SIGNAL PINS IN E, F, J, AND K ARE NOT CONNECTED ON THE EVAL-TPG-ZYNQ3, ONLY POWER PINS. SEE EVAL-TPG-ZYNQ3 DATA SHEET FOR MORE INFORMATION R313 DNF R182 R191 0 0 R371 R199 0 0 R372 R200 0 0 R319 0 FMC_VDD_IF FMC_VDD_IF J24C E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 R153 1k PG_M2C F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 R277 R278 0 0 GPIO8_A GPIO9_A R201 R279 0 0 GPIO14_A GPIO15_A R202 R280 0 0 GPIO11_B GPIO12_B R207 R281 0 0 GPIO16_B GPIO17_B FMC_VDD_IF Figure 95. FMC HPC Row E, Row F, Row J, and Row K, Not Connected on EVAL-TPG-ZYNQ3 (Except for Power Connections) Rev. A | Page 86 of 115 16493-295 FMC_TDD1_SWITCH_B FMC_TDD2_SWITCH_B J24E J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 ADRV-DPD1/PCBZ User Guide UG-1238 DUMMY CONNECTOR TO EASE CONNECTION TO EVAL-TPG-ZYNQ3 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 16493-296 J21B J21A C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 Figure 96. FMC LPC Dummy Connector H1 H2 H3 H4 H5 H6 H7 H8 SCREW SCREW SCREW SCREW SCREW SCREW SCREW SCREW H9 H10 H11 H12 H13 H14 H15 H16 WASHER LOCK WASHER LOCK WASHER LOCK WASHER LOCK WASHER LOCK WASHER LOCK WASHER LOCK WASHER LOCK H17 H18 H19 H20 H21 H22 H23 H24 WASHER WASHER WASHER WASHER WASHER WASHER WASHER WASHER H25 H26 H27 H28 H29 H30 H31 H32 STANDOFF STANDOFF STANDOFF STANDOFF STANDOFF STANDOFF STANDOFF STANDOFF PCB1 HW13 HW14 HW15 HW16 2505007 2505007 2505007 31322366 PCB-GENERIC Figure 97. Mechanicals Rev. A | Page 87 of 115 16493-297 PCB L48 Figure 98. ADP5054 Power Supply Rev. A | Page 88 of 115 1.3_DIGITAL P_GOOD_ANALOG +5V C83 100F R17 100k C106 10F C98 10F R135 100k VREG C92 10F VREG 1.3_DIGITAL C85 10F C73 100F +5V 10k 3300pF 2200pF C100 2200pF 48 47 6 21 20 24 23 22 22k R26 49 14 15 7 SS = 2ms 13 22k R19 R23 C97 39 40 38 37 SS = 2ms 18 10k C93 3300pF C90 43 1.0F C82 36 45 1.0F C81 R15 VREG EPAD EN4 ADP5054 QUAD BUCK REGULATOR 17 11 10 16 9 8 12 3 2 46 5 4 1 19 28 25 26 27 29 30 31 35 34 33 32 41 42 44 1.3_DIGITAL PWRGD PGND4 PGND4 FB4 SW4 SW4 BST4 PGND3 PGND3 FB3 SW3 SW3 BST3 FB2 BST2 SW2 SW2 SW2 DL2 PGND DL1 SW1 SW1 SW1 BST1 FB1 RT SYNC/MODE POWER SEQUENCING: 1. +1.3_DIG (CH2) 2. +1.3V_ANG (CH1), +1.8V (CH4) 3. +3.3V (CH3) COMP4 PVIN4 CFG34 EN3 COMP3 PVIN3 EN2 COMP2 PVIN2 PVIN2 PVIN2 CFG12 EN1 COMP1 PVIN1 PVIN1 PVIN1 VDD VREG U3 VREG 1.3_ANALOG R27 10k 2.2H L29 C88 47F C87 47F R127 S1 D1 G1 D2 S2 D1_P G2 D2_P Q1 6 3 7 8 C86 47F 13k R25 C164 47F 31.6k L37 C109 47F C94 47F C170 47F +1.8V C95 47F C125 47F +1.3V_DIG C166 47F L39 C169 47F L38 +3.3V +1.3V_DIG 1.0H L36 1.3_DIGITAL L35 1.0H 0.10F C176 0.10F C177 R128 C89 47F +1.3V_ANG 1.3_ANALOG 6.34k +1.3V_ANG 6.34k C77 47F L27 DUAL N-CHANNEL MOSFET R18 R29 10.2k P_GOOD_ANALOG C99 0.10F R22 10k 0 R20 2.2H C96 0.10F L28 C91 0.10F DNF 1 2 4 5 C80 47F 10k 0 R11 R13 DNF R12 15k C84 0.10F R10 R9 C78 47F fSW = 1.2MHz C79 47F 1.3_ANALOG UG-1238 ADRV-DPD1/PCBZ User Guide RADIO BOARD SCHEMATICS 16493-298 ADRV-DPD1/PCBZ User Guide UG-1238 16493-299 AD9375 Figure 99. AD9375 Power Connections for VDD_IF, +1.8 V, +1.3_DIG, and +1.3_ANG Rev. A | Page 89 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide +1.3V_ANG L66 C35 0.10F +1.3V_ANG C67 0.10F C68 100F U1E L19 L67 VDDA_BB E5 C36 100F C37 1.0F VDDA_RXVCO C7 C49 0.10F C63 0.10F VDDA_SNRXSYNTH G7 VDDA_DES N9 L21 C51 0.10F L53 JESD_VTT_DES P9 C47 100F C152 1.0F C45 1.0F VDDA_SNRXVCO C4 C50 1.0F L52 C38 0.10F VDDA_RXRF B1 VDDA_TXVCO F11 VDDA_RXTX F2 VDDA_TXSYNTH G8 C66 0.10F C62 1.0F C69 100F L22 L70 C64 1.0F C211 0.10F C212 10000pF C53 0.10F AD9375 C52 1.0F VDDA_SER P8 L71 C213 100F C214 1.0F C215 0.10F VDDA_SER N8 VCLK_VCO_LDO M1 VRX_VCO_LDO C8 L51 C34 1.0F C48 0.10F VTX_VCO_LDO F13 C59 1.0F Figure 100. AD9375 Power Connections for +1.3_ANG and Signal Grounds Rev. A | Page 90 of 115 C58 1.0F C57 1.0F C54 1.0F 16493-300 C65 100F VSNRX_VCO_LDO C3 ADRV-DPD1/PCBZ User Guide UG-1238 U1D VSSD L7 VSSD L10 VSSA G1 VSSA F9 VSSA F8 VSSA F7 VSSA F6 VSSA F5 VSSA F4 VSSA F3 VSSA E10 VSSA E9 VSSA E6 VSSA D9 VSSA D8 VSSA D7 VSSA D6 VSSA C10 VSSA C9 VSSA C5 VSSA B13 VSSA B12 VSSA B11 VSSA B10 VSSA B9 VSSA B6 VSSA B5 VSSA B4 VSSA B3 VSSA B2 VSSA A14 VSSA A11 VSSA A8 VSSA A7 VSSA A4 VSSA A1 VSSA F10 VSSA G2 VSSA G5 VSSA G10 VSSA G11 VSSA G12 VSSA G13 VSSA G14 VSSA H2 VSSA H3 VSSA H4 VSSA H5 VSSA H6 VSSA H7 VSSA H8 VSSA H9 VSSA H10 VSSA H13 VSSA J2 VSSA J13 VSSA K1 VSSA K2 VSSA K13 VSSA K14 VSSA L1 VSSA L2 VSSA G3 VSSA L13 VSSA L14 VSSA M2 VSSA M9 VSSA N2 VSSA N7 VSSA N14 VSSA P1 VSSA P2 VSSA P3 VSSA P10 Figure 101. AD9375 Grounding Rev. A | Page 91 of 115 16493-301 AD9375 UG-1238 ADRV-DPD1/PCBZ User Guide C23 0.10F DEV_CLK_IN- U1C R1 100 E8 DEV_CLK_IN- GPIO_0 E7 DEV_CLK_IN+ GPIO_1 C25 0.10F DEV_CLK_IN+ GPIO_2 GPIO_3 TMP_SENSE VDD_IF C31 1000pF R2 4.7k R6 4.7k E13 AUXADC_0 C11 AUXADC_1 GPIO_4 C12 AUXADC_2 D11 AUXADC_3 GPIO_6 GPIO_5 GPIO_7 GPIO_8 R92 R87 4.7k 4.7k GPIO_9 K9 SPI_SCLK SCLK GPIO_10 SDIO GPIO_11 J10 SDO GPIO_12 J9 SPI_MOSI SPI_MISO K10 SPI_MYK_CS GPIO_13 CS GPIO_14 J4 RESET GPIO_15 RESET AD9375 GPIO_16 GPIO_17 J5 GP_INTERRUPT GP_INTERRUPT R109 4.7k GPIO_18 GPIO_3P3_0 J6 TEST TEST C14 R4 1k RBIAS K8 J8 J7 K7 K6 K5 L5 L6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 TRST GPIO5 TDO GPIO6 TDI GPIO7 TMS L12 K12 J12 GPIO10 H12 H11 J11 K11 L11 UNCONNECTED GPIOs ASSIGNED AS OUTPUTS AND ASSERTED LOW M11 M10 J3 C1 GPIO18 TCK GPIO_0_PA1_EN GPIO_3P3_1 C2 GPIO_1_LNA1_EN GPIO_3P3_2 F1 GPIO_2_PA2_EN GPIO_3P3_3 D1 GPIO_3_LNA2_EN GPIO_3P3_4 E1 GPIO_4_DRV1_EN GPIO_3P3_5 D5 GPIO_5_DRV2_EN GPIO_3P3_6 E14 GPIO_3P3_7 D12 GPIO_3P3_8 D13 GPIO_3P3_9 C13 GPIO_3P3_10 D14 GPIO_3P3_11 F14 UNCONNECTED GPIOs ASSIGNED AS OUTPUTS AND ASSERTED LOW 16493-302 R5 14.3k Figure 102. AD9375 Connections for GPIO, 3V3 GPIO, AUXDAC, Interrupt, Clock, and SPI Communications SERDIN0- SERDOUT0- SERDIN0+ SERDOUT0+ SERDOUT1- SERDIN1+ SERDOUT1+ SERDOUT2- SERDIN2- SERDIN2+ SERDOUT2+ SERDIN3- SERDOUT3- SERDIN3+ AD9375 SERDOUT3+ SYNCOUTB0- SYNCINB0- SYNCOUTB0+ SYNCINB0+ SYSREF_IN- K3 SYSREF_IN+ SYNCINB1- SYNCINB1+ TX1_ENABLE RX1_ENABLE TX2_ENABLE RX2_ENABLE 16493-303 SERDIN3- Figure 103. AD9375 JESD204B and Receiver and Transmitter Enables Rev. A | Page 92 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 VDD_IF R104 10k R105 10k R106 10k R107 10k R108 10k +3.3V U2 2 4 3 GPIO4 GPIO5 GPIO6 VOUT 1 TMP36 TMP_SENSE GND 5 16493-304 C26 1.0F VCC SHD NC GPIO7 GPIO18 Figure 104. GPIO Pull-Up and Temperature Sensor C2 0.5pF L1 3.9nH C3 100pF C5 100pF RX1+ RX2- L2 3.9nH C7 0.5pF C9 100pF RX2+ U1_TX1- A10 A9 A6 A5 RX1- RX1+ J14 H14 U1_TX1+ RX2- RX2+ D4 E4 D3 E3 D2 E2 B7 B8 TX1- TX1+ AD9375 ORX1- ORX1+ SNRXA- SNRXA+ SNRXB- SNRXB+ SNRXC- SNRXC+ C6 6.0pF A13 A12 C4 1.0pF ORX1- L3 6.2nH C10 6.0pF ORX1+ RX_2 TX2- TX2+ H1 J1 RX_2 RX_EXTLO- RX_EXTLO+ ORX2- ORX2+ E11 TX_EXTLO- E12 TX_EXTLO+ C12 6.0pF A3 A2 ORX2- L4 6.2nH C8 1.0pF C14 6.0pF 16493-305 RX1- C1 100pF ORX2+ Figure 105. AD9375 RF Interface Connections C196 DNF C194 8.2pF U1_TX1+ R24 0 C117 4.3pF C192 8.2pF U1_TX1- C197 1.0pF C154 4.3pF L45 27nH L44 27nH TX_1- C210 DNF C209 DNF R34 0 TX_1+ PLACE CLOSE TO RFIN OF U15 INPUT PORTS +1.8V_TX_BAL L10 C16 10F C18 0.10F C201 100pF C200 100pF GND 4 RX1- 6 T3 BAL2 UNBAL BAL1 GND/DC NC GND 1 R58 0 2 R57 0 ORX1+ 3 4 6 T2 BAL2 UNBAL BAL1 GND/DC NC GND/NC L13 10nH R75 DNF 5 RX_1 C145 100pF 1 C11 5.6pF 2 R86 DNF 5 R73 DNF ORX_1 L16 27nH C142 DNF Figure 106. Rx1 Balanced to Unbalanced Transformer and Tx1 Filtering Rev. A | Page 93 of 115 16493-306 3 RX1+ ORX1- GND GND GND UG-1238 ADRV-DPD1/PCBZ User Guide C222 4.3pF C193 8.2pF U1_TX2- U1_TX2+ C204 DNF C195 8.2pF R39 0 R74 0 TX_2+ PLACE CLOSE TO RFIN OF U7 INPUT PORTS L47 27nH L46 27nH C103 DNF C205 1.0pF C223 4.3pF TX_2- C104 DNF +1.8V_TX_BA L L11 RX2+ RX2- 3 4 6 T6 BAL2 UNBAL BAL1 GND/DC NC C20 0.10F C199 100pF GND 1 R62 0 2 ORX2+ 3 4 6 T5 BAL2 UNBAL BAL1 GND/DC NC GND/NC RX_2 L15 10nH R82 DNF 5 R64 0 ORX2- C150 10F C144 100pF 1 C13 5.6pF 2 R95 DNF 5 R84 DNF ORX_2 L17 27nH C151 DNF Figure 107. Rx2 Balanced to Unbalanced Transformer and Tx2 Filtering Rev. A | Page 94 of 115 16493-307 C198 100pF ADRV-DPD1/PCBZ User Guide UG-1238 PA1_RFOUT 16493-308 Figure 108. ADL5335 and SKY66297 Connections Rev. A | Page 95 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide BYPASS R30 DNF R28 DNF C162 1 PA1_RFOUT 4 8.2pF U5 INPUT DIRECT COUPLED ISO R97 DNF R98 DNF GND DIRECTIONAL COUPLER 6 5 4 2 3 5 U4 IN GND GND 1 2 3 OUT GND GND ISOLATOR R50 49.9 R136 DNF R137 0 13dB PAD R138 R46 105 DNF R53 78.7 R51 78.7 3 BYPASS R3 J4 U20 3 O/I I/O 4 GND GND 8.2pF L84 DNF 1 2 DUPLEXER GND ANT 4 2 RX C190 U6 TX DNF 1 LOW PASS FILTER ANT_RX1 16493-309 ORX_1 Figure 109. Tx1 and Rx1 Antenna and ORX_1 Connection +5V +5V_LNA_MAIN +5V_LNA_MAIN R54 L33 0 C72 0.10F C70 10F C114 100pF R55 8.2k C113 0.10F 1 C115 L7 2 8.2pF 1.0nH 3 ANT_RX1 L8 30nH 4 9 C119 100pF N/C RFIN VBIAS N/C L6 36nH U13 8 N/C 7 RFOUT 6 ENABLE 5 N/C GND LOW NOISE AMPLIFIER C112 3300pF C116 8.2pF R61 430 6dB PAD R59 C183 12 8.2pF LNA2_OUT R63 430 C118 100pF L57 LNA1_EN BYPASS R31 R21 L58 4.7nH U21 L54 8.2nH R14 C182 L85 0 8.2pF 2.7nH C216 1.3pF RX_1 C217 1.3pF 16493-310 2 3 5 L42 24nH DNF BULK ACOUSTIC WAVE RF UPLINK FILTER FOR LTE BAND 7 1 4 IN OUT GND GND GND C173 8.2pF 0 2 LNA2_OUT D2 CLA4606-085LF 1 3 Figure 110. Rx1 SKY67159 Low Noise Amplifier Rev. A | Page 96 of 115 SPI_DRV2_CS SPI_SCLK SPI_MOSI TX_2+ TX_2- 0 +5V_DRV_DIV R144 0 R143 +5V_DRV_DIV 0 +5V_DRV_DIV R126 C203 0.10F C175 0.10F C171 0.10F C185 100pF 16 15 14 3 2 CS SCLK SDIO RFIN+ RFIN- U7 C206 100pF C202 100pF C172 100pF L81 1 VPOS1 GND1 5 C121 3300pF 11 13 4 ADL5335 EP FA RFOUT +5V +5V 17 12 10 L41 L80 R146 0 L75 DNF L76 DNF C133 47F +5V_PA_DIV 18 R60 294 R41 3dB PAD +5V_PA_DIV +5V_PA_DIV PA2_EN 8.2pF C221 C157 47F C167 10F +5V_DRV_DIV L60 L59 R44 294 0 R36 8.2pF C127 C185 100pF GND GND GND RFIN GND U14 C135 3300pF C134 1.0F 17 4 3 2 1 C121 3300pF 16 C187 100pF C186 100pF GND GND VCC3 C184 100pF RFOUT SKY66297-11 VCC1 VBIAS 5 ENBL 15 GND PAEN 6 VPOS2 GND2 6 GND5 13 GND GND VPOS3 GND3 7 GND4 8 Figure 111. Tx2 ADL5335 and SKY66297 Connections 9 14 VCC2 GND 7 Rev. A | Page 97 of 115 8 DRV2_EN 12 9 10 11 +5V_PA_DIV PA2_RFOUT C130 100pF +5V_PA_DIV 0 C120 3300pF R35 ADRV-DPD1/PCBZ User Guide UG-1238 16493-311 UG-1238 ADRV-DPD1/PCBZ User Guide BYPASS R37 DNF C163 1 PA2_RFOUT 4 8.2pF R101 DNF U9 INPUT DIRECT COUPLED ISO R100 DNF GND DIRECTIONAL COUPLER R38 DNF 2 6 5 4 3 5 U8 IN OUT GND GND GND GND ISOLATOR 1 2 3 R65 49.9 R139 DNF R140 0 13dB PAD R66 R141 105 R67 78.7 DNF R68 78.7 3 BYPASS R16 U11 TX DNF DUPLEXER J3 U22 1 3 I/O O/I 4 2 GND GND LOW PASS FILTER 8.2pF ANT GND 4 1 L86 DNF 2 RX C191 ANT_RX2 16493-312 ORX_2 Figure 112. Tx2 and Rx2 Antenna and ORX_2 Connection +5V +5V_LNA_DIV +5V_LNA_DIV R69 L34 0 C74 10F C76 0.10F C138 0.10F C137 100pF R70 8.2k 1 C146 L31 8.2pF 1.0nH L32 30nH ANT_RX2 2 3 4 9 C149 100pF C136 3300pF L30 36nH U12 8 N/C 7 RFIN RFOUT 6 VBIAS ENABLE 5 N/C N/C 6dB PAD N/C GND LOW NOISE AMPLIFIER C140 8.2pF R81 430 R78 C189 12 8.2pF LNA2_OUT R83 430 C148 100pF L61 LNA2_EN BYPASS R71 U16 R32 L62 8.2nH 0 C188 L87 8.2pF 2.7nH C218 1.3pF RX_2 C219 1.3pF 16493-313 L63 4.7nH GND GND GND L43 24nH DNF BULK ACOUSTIC WAVE UPLINK FILTER FOR LTE BAND 7 4 1 OUT IN 2 3 5 R33 0 2 LNA2_OUT D3 CLA4606-085LF 1 3 C174 8.2pF Figure 113. Rx2 Low Noise Amplifier Rev. A | Page 98 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 J1 SYNCINB0- SYNCINB0+ SYSREF_IN- SYSREF_IN+ DEV_CLK_IN- DEV_CLK_IN+ PRESENCE RF TX_DRV1_EN TX_DRV2_EN RX1_RADIO_EN RX_LNA1_EN RX_LNA2_EN TX1_RADIO_EN TX_PA1_EN TX_PA2_EN EEPROM_WP SPI_EEPROM_CS SPI_DRV2_CS SPI_DRV1_CS SPI_MYK_CS SPI_SCLK SPI_MOSI SPI_MISO GP_INTERRUPT RESET GPIO0 GPIO1 GPIO2 GPIO3 VDD_IF +5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 SERDOUT3SERDOUT3+ SERDOUT1- SERDOUT1+ SERDOUT2SERDOUT2+ SERDOUT0- SERDOUT0+ C17 C19 0.10F 0.10F SERDIN2- SERDIN2+ C71 C75 0.10F 0.10F SERDIN0- SERDIN0+ C108 C132 0.10F 0.10F SERDIN3SERDIN3+ C139 C147 0.10F 0.10F SERDIN1- SERDIN1+ SYNCOUTB0- SYNCOUTB0+ GPIO10 GPIO4 GPIO5 GPIO6 GPIO7 GPIO18 TEST +5V +5V REMOTE +5V SENSE ON PA PIN 100 Figure 114. 100-Way Connector Rev. A | Page 99 of 115 TRST TDO TDI TMS TCK 16493-314 SYNCINB1- SYNCINB1+ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 UG-1238 ADRV-DPD1/PCBZ User Guide R40 GPIO_0_PA1_EN BUFFER WITH OPEN-DRAIN OUTPUTS U17 1 1A 2 GND 3 2A TX_PA1_EN TX_PA2_EN R52 10k PA1_EN VDD_IF 6 1Y 2.2k R47 10k 5 VCC 4 2Y C15 1.0F R56 10k PA2_EN R72 GPIO_2_PA2_EN R76 10k 2.2k R77 BUFFER WITH OPEN-DRAIN OUTPUTS U18 1 1A 2 GND 3 2A TX_DRV1_EN TX_DRV2_EN R88 10k 1Y VCC 2Y GPIO_4_DRV1_EN 8.2k DRV1_EN VDD_IF 6 R85 10k 5 4 C158 1.0F R89 10k DRV2_EN R90 GPIO_5_DRV2_EN 8.2k R91 10k +5V R93 GPIO_1_LNA1_EN RX_LNA2_EN R113 10k R94 100k LNA1_EN INVERTER WITH OPEN-DRAIN OUTPUTS U19 1 6 1A 1Y 2 5 GND VCC 3 4 2A 2Y RX_LNA1_EN 2.2k R112 100k VDD_IF C159 1.0F +5V R116 10k R117 100k LNA2_EN R121 GPIO_3_LNA2_EN VDD_IF 2.2k VDD_IF VDD_IF SPI_EEPROM_CS SPI_MISO EEPROM_WP R131 4.7k 1 2 3 4 U23 CS SO WP GND VCC HOLD SCL SI 8 7 6 5 R132 10k SPI_SCLK SPI_MOSI R147 4.7k SPI_CSB2 SPI_CSB1 Figure 115. Amplifier Enable Buffers and SPI EEPROM Rev. A | Page 100 of 115 SPI_CSB2 SPI_CSB1 R148 4.7k 16493-315 C160 0.10F R133 10k R124 100k PCB1 PCB SH1 31082267 SH2 31082268 UG-1238 SH3 31082269 31282247 HW1 PCB HW2 PCB HW3 PCB HW4 PCB 567-581 567-581 567-581 567-581 HW5 HW6 HW7 HW8 HW9 HW10 HW11 HW12 SCREW SCREW SCREW SCREW SCREW SCREW SCREW WASHER PLAIN HW13 HW14 HW15 HW16 HW17 HW18 HW19 HW20 WASHER PLAIN WASHER PLAIN WASHER LOCK WASHER LOCK WASHER LOCK HEATSINK, MACHINING HEATSINK, INTERFACE THERMAL COMPOUND HW21 HW22 HW23 HW24 HW25 HW26 HW27 HW27 GAP PAD GAP PAD GAP PAD EMC GASKET M0538-3-AL M0538-3-AL M0538-3-AL M0538-3-AL Figure 116. Mechanicals Rev. A | Page 101 of 115 16493-316 ADRV-DPD1/PCBZ User Guide UG-1238 ADRV-DPD1/PCBZ User Guide INTERPOSER BOARD PCB LAYERS 16493-317 The eight layers of etched copper in the interposer board are shown in Figure 117 to Figure 124. Grey indicates a plated through hole to the adjacent layer(s). The board layers are made from Isola FR408HR FR4 with a copper foil. The boards make use of blind vias to connect between layers. Figure 117. Layer 1 (Top) Rev. A | Page 102 of 115 UG-1238 16493-318 ADRV-DPD1/PCBZ User Guide Figure 118. Layer 2 Rev. A | Page 103 of 115 ADRV-DPD1/PCBZ User Guide 16493-319 UG-1238 Figure 119. Layer 3 Rev. A | Page 104 of 115 UG-1238 16493-320 ADRV-DPD1/PCBZ User Guide Figure 120. Layer 4 Rev. A | Page 105 of 115 ADRV-DPD1/PCBZ User Guide 16493-321 UG-1238 Figure 121. Layer 5 Rev. A | Page 106 of 115 UG-1238 16493-322 ADRV-DPD1/PCBZ User Guide Figure 122. Layer 6 Rev. A | Page 107 of 115 ADRV-DPD1/PCBZ User Guide 16493-323 UG-1238 Figure 123. Layer 7 Rev. A | Page 108 of 115 UG-1238 16493-324 ADRV-DPD1/PCBZ User Guide Figure 124. Layer 8 (Bottom) Rev. A | Page 109 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide RADIO BOARD PCB LAYERS 16493-325 The eight layers of etched copper in the radio board are shown in Figure 125 to Figure 132. Grey indicates a plated through hole to the adjacent layer(s). The board layers are made from Isola FR408HR FR4 with a copper foil. The boards make use of blind vias to connect between layers. 16493-326 Figure 125. Layer 1 (Bottom, 100-Pin Connector Side) Figure 126. Layer 2 Rev. A | Page 110 of 115 UG-1238 16493-327 ADRV-DPD1/PCBZ User Guide 16493-328 Figure 127. Layer 3 Figure 128. Layer 4 Rev. A | Page 111 of 115 ADRV-DPD1/PCBZ User Guide 16493-329 UG-1238 16493-330 Figure 129. Layer 5 Figure 130. Layer 6 Rev. A | Page 112 of 115 UG-1238 16493-331 ADRV-DPD1/PCBZ User Guide 16493-332 Figure 131. Layer 7 Figure 132. Layer 8 (Top, Antenna Connector Side) Rev. A | Page 113 of 115 UG-1238 ADRV-DPD1/PCBZ User Guide INTERPOSER BOARD CONNECTORS AND LEDS 16493-042 Figure 133. ADRV-INTERPOS1/PCBZ Board Layout Schematic Rev. A | Page 114 of 115 ADRV-DPD1/PCBZ User Guide UG-1238 NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the "Evaluation Board"), you are agreeing to be bound by the terms and conditions set forth below ("Agreement") unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you ("Customer") and Analog Devices, Inc. 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