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1
SP3220E/EB/EU
+3.0V to +5.5V RS-232 Driver/Receiver Pair
The SP3220E devices are RS-232 driver/receiver solutions intended for portable or hand-held
applications such as palmtop computers, instrumentation and consumer products. These
devices incorporate a high-e󰀩ciency, charge-pump power supply that allows the SP3220E
devices to deliver true RS-232 performance from a single power supply ranging from +3.0V
to +5.0V. This charge pump requires only 0.1µF capacitors in 3.3V operation. The ESD toler-
ance of the these devices are over +/-15kV for both Human Body Model and IEC61000-4-2
Air discharge test methods. All devices have a low-power shutdown mode where the driver
outputs and charge pumps are disabled. During shutdown, the supply current falls to less
than 1µA.
FEATURES
■ Meets all EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
• Interoperable with RS-232 and V.28 at +2.7V
■ Supports High Serial Data Rates:
• 120kbps SP3220E
• 250kbps SP3220EB
• 1Mbps SP3220EU
■ 1µA Low Power Shutdown Mode
■ Footprint Compatible with MAX3221E, ISL3221
■ 4 x 1.0µF External Charge Pump Capacitors
■ Improved ESD Specications:
+15kV Human Body Model
+15kV IEC61000-4-2 Air Discharge
+8kV IEC61000-4-2 Contact Discharge
DESCRIPTION
SELECTION TABLE
Now Available in Lead Free Packaging
V-
1
2
3
413
14
15
16
5
6
7
12
11
10
C1+
V+
C1-
C2+
C2-
R1IN
GND
V
CC
T1OUT
No Connect
89
SP3220
E/EB/EU
T1IN
No Connect
R1OUT
EN SHDN
MODEL Power
Supplies
RS-232
Drivers
RS-232
Receivers
External
Components
Shutdown Data Rate
SP3220E +3.0V to +5.5V 1 1 4 Capacitors Yes 120kbps
SP3220EB +3.0V to +5.5V 1 1 4 Capacitors Yes 250kbps
SP3220EU +3.0V to +5.5V 1 1 4 Capacitors Yes 1Mbps
2
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NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute di󰀨erence cannot exceed 13V.
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
a󰀨ect reliability and cause permanent damage to the
device.
VCC.......................................................-0.3V to +6.0V
V+ (NOTE 1).......................................-0.3V to +7.0V
V- (NOTE 1)........................................+0.3V to -7.0V
V+ + |V-| (NOTE 1)...........................................+13V
ICC (DC VCC or GND current).........................+100mA
Input Voltages
TxIN, EN, SHDN...........................-0.3V to Vcc + 0.3V
RxIN...................................................................+25V
Output Voltages
TxOUT.............................................................+13.2V
RxOUT, .......................................-0.3V to (VCC +0.3V)
Short-Circuit Duration
TxOUT....................................................Continuous
Storage Temperature......................-65°C to +150°C
Unless otherwise noted, the following specications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at Vcc = +3.3V or +5.0V and TAMB = 25oC, C1 - C4 = 0.1µF.
Power Dissipation per package
16-pin SSOP (derate 9.69mW/oC above +70oC)...............775mW
16-pin TSSOP (derate 10.5mW/oC above +70oC)..............840mW
ELECTRICAL CHARACTERISTICS
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
DC CHARACTERISTICS
Supply Current 0.3 1.0 mA no load, VCC = 3.3V,
TAMB = 25oC, TxIN = GND or VCC
Shutdown Supply Current 1.0 10 µA SHDN = GND, VCC = 3.3V,
TAMB = 25oC, TxIN = Vcc or GND
LOGIC INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold LOW GND 0.8 V TxIN, EN, SHDN, Note 2
Input Logic Threshold HIGH 2.0 V Vcc = 3.3V, Note 2
Input Logic Threshold HIGH 2.4 V Vcc = 5.0V, Note 2
Input Leakage Current +0.01 +1.0 µA TxIN, EN, SHDN,
TAMB = +25oC, VIN = 0V to VCC
Output Leakage Current +0.05 +10 µA Receivers disabled, VOUT = 0V to VCC
Output Voltage LOW 0.4 V IOUT = 1.6mA
Output Voltage HIGH VCC -0.6 VCC -0.1 V IOUT = -1.0mA
DRIVER OUTPUTS
Output Voltage Swing +5.0 +5.4 V Driver output loaded with 3KΩ to
GND, TAMB = +25oC
ABSOLUTE MAXIMUM RATINGS
NOTE 2: Driver input hysteresis is typically 250mV.
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Unless otherwise noted, the following specications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX,
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
ELECTRICAL CHARACTERISTICS
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
DRIVER OUTPUTS (continued)
Output Resistance 300 VCC = V+ = V- = 0V, TOUT=+2V
Output Short-Circuit Current +35 +60 mA VOUT = 0V
Output Leakage Current +25 µA VOUT = +12V, VCC = GND to 5.5V,
Drivers disabled
RECEIVER INPUTS
Input Voltage Range -15 +15 V
Input Threshold LOW 0.6 1.2 V Vcc = 3.3V
Input Threshold LOW 0.8 1.5 V Vcc = 5.0V
Input Threshold HIGH 1.5 2.4 V Vcc = 3.3V
Input Threshold HIGH 1.8 2.4 V Vcc = 5.0V
Input Hysteresis 0.3 V
Input Resistance 35 7 kΩ
TIMING CHARACTERISTICS
Data Rate SP3220E 120 235 kbps RL = 3KΩ, CL = 1000pF
Data Rate SP3220EB 250 kbps RL = 3KΩ, CL = 1000pF
Data Rate SP3220EU 1000 kbps RL = 3KΩ, CL = 250pF
Receiver Propagation Delay, tPHL
0.15 µs Receiver input to Receiver
output, CL = 150pF
Receiver Propagation Delay, tPLH 0.15 µs Receiver input to Receiver
output, CL = 150pF
Receiver Output Enable Time 200 ns
Receiver Output Disable Time 200 ns
Driver Skew 100 ns | tPHL - tPLH |, TAMB = 25°C
Receiver Skew 50 ns | tPHL - tPLH |
Transition-Region Slew Rate 30 V/µs Vcc = 3.3V, RL = 3kΩ, TAMB =
25°C, measurements taken from
-3.0V to +3.0V or +3.0V to -3.0V
(SP3220E and SP3220EB)
Transition-Region Slew Rate 90 V/µs Vcc = 3.3V, RL = 3kΩ, TAMB =
25°C, measurements taken from
-3.0V to +3.0V or +3.0V to -3.0V
(SP3220EU)
4
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all
drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
Figure 2. Transmitter Output Voltage vs Load
Capacitance for the SP3220EB.
Figure 1. Icc vs Load Capacitance for the
SP3220EB.
30
25
20
15
10
5
0
Icc (mA)
Load Capacitance (pF)
0 1000 2000 3000 4000 5000
125Kbps
20Kbps
60Kbps
T1 at Full Data Rate
T2 at 1/16 Full Data Rate
T1+T2 Loaded with 3k/CLoad
Figure 3. Transmitter Output Voltage vs Supply
Voltage for the SP3220EB.
TYPICAL PERFORMANCE CHARACTERISTICS
6
4
2
0
-2
-4
-6 0 1000 2000 3000 4000 5000
TxOUT +
TxOUT -
Transmitter Output
Voltage (V)
Load Capacitance (pF)
T1 at 250Kbps
2.7 3 3.5 4 4.5 5
Supply V oltage (V)
Transmitter Output
Voltage (V)
6
4
2
0
-2
-4
-6
TxOUT +
TxOUT -
Figure 4. Supply Current vs Supply Voltage for the
SP3220EB.
12
10
8
6
4
2
02.7 3 3.5 4 4.5 5
Supply Current (mA)
Supply Voltage (V)
T1 Loaded with 3K // 1000pf @ 250Kbps
Figure 5. Slew Rate vs Load Capacitance for the
SP3220EB.
Figure 6. Supply Current vs Supply Voltage for the
SP3220EU.
25
20
15
10
5
00 500 1000 2000 3000 4000 5000
Slew rate (V/s)
Load Capacitance (pF)
- Slew
+ Slew
40
30
20
10
0
0 250 500 1000 2000 3000 4000
Icc (mA)
Load Capacitance (pF)
500Kbps
1Mbps
2Mbps
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Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all
drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
0 250 500 1000 1500 2000
Load Capacitance (pF)
Transmitter
Output V oltage (V)
6
4
2
0
-2
-4
-6
2Mbps 1.5Mbps 1Mbps
2Mbps 1.5Mbps 1Mbps
2.5 2.7 3 3.5 4 4.5 5
Supply V oltage (V)
Transmitter Output
Voltage (V)
6
4
2
0
-2
-4
-6
TxOUT +
TxOUT -
16
14
12
10
8
6
4
2
02.7 3 3.5 4 4.5 5
Supply Current (mA)
Supply Voltage (V)
T1 Loaded with 3K // 1000pf @1Mbps
Figure 7. Transmitter Output Voltage vs Load
Capacitance for the SP3220EU.
Figure 8. Transmitter Output Voltage vs Supply
Voltage for the SP3220EU.
Figure 9. Supply Current vs Supply Voltage for the
SP3220EU.
6
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Table 1. Device Pin Description
NAME FUNCTION PIN NUMBER
EN Receiver Enable. Apply Logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state) 1
C1+ Positive terminal of the voltage doubler charge-pump capacitor 2
V+ +5.5V output generated by the charge pump 3
C1- Negative terminal of the voltage doubler charge-pump capacitor 4
C2+ Positive terminal of the inverting charge-pump capacitor 5
C2- Negative terminal of the inverting charge-pump capacitor 6
V- -5.5V output generated by the charge pump 7
R1IN RS-232 receiver input 8
R1OUT TTL/CMOS receiver output 9
T1IN TTL/CMOS driver input 11
T1OUT RS-232 driver output. 13
GND Ground 14
VCC +3.0V to +5.5V supply voltage 15
SHDN
Shutdown Control Input. Drive HIGH for normal device operation.
Drive LOW to shutdown the drivers (high-Z output) and the on-
board power supply
16
N.C. No Connect 10, 12
PIN FUNCTION
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7
Figure 10. Pinout Congurations for the SP3220E/EB/EU
V-
1
2
3
413
14
15
16
5
6
7
12
11
10
C1+
V+
C1-
C2+
C2-
R1IN
GND
VCC
T1OUT
No Connect
89
SP3220
E/EB/EU
T1IN
No Connect
R1OUT
EN SHDN
PINOUT
8
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Figure 11. SP3220E/EB/EU Typical Operating Circuit
SP3220
2
4
6
5
3
7
15
GND
T1IN T1OUT
C1+
C1-
C2+
C2-
V+
V-
V
CC
11
0.1µF
0.1
0.1
+
C2
C5
C1
+
+*C3
C4
+
+
0.1
0.1
13 RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
14
5kΩ
R1IN
R1OUT
98
LOGIC
OUTPUTS
*can be returned to
either V
CC
or GND
EN
1SHDN 16
µF
µF
µF
µF
E/EB/EU
TYPICAL OPERATING CIRCUITS
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The SP3220E/EB/EU devices meet the
EIA/TIA-232 and ITU-T V.28/V.24 commu-
nication protocols and can be implemented
in battery-powered, portable, or hand-held
applications such as notebook or palmtop
computers. The SP3220E/EB/EU devices
feature Exar's proprietary on-board charge
pump circuitry that generates ±5.5V for RS-
232 voltage levels from a single +3.0V to
+5.5V power supply. This series is ideal for
+3.3V-only systems, mixed +3.3V to +5.5V
systems, or +5.0V-only systems that require
true RS-232 performance. The SP3220EB
device has a driver that can operate at a data
rate of 250kbps fully loaded. The SP3220EU
can operate at 1000kbps; the SP3220E
device can operate at a typical data rate of
235kbps when fully loaded.
The SP3220E/EB/EU is a 1-driver/1- receiver
device ideal for portable or hand-held ap-
plications. The SP3220E/EB/EU features a
1µA shutdown mode that reduces power
consumption and extends battery life in por-
table systems. Its receivers remain active in
shutdown mode, allowing external devices
such as modems to be monitored using only
1µA supply current.
THEORY OF OPERATION
The SP3220E/EB/EU series is made up of
three basic circuit blocks:
1. Driver
2. Receiver
3. The Exar proprietary charge pump
Driver
The driver is an inverting level transmitter that
converts TTL or CMOS logic levels to +5.0V
EIA/TIA-232 levels with an inverted sense
relative to the input logic levels. Typically,
the RS-232 output voltage swing is +5.5V
with no load and at least +5V minimum fully
loaded. The driver outputs are protected
against innite short-circuits to ground with-
out degradation in reliability. Driver outputs
will meet EIA/TIA-562 levels of +/-3.7V with
supply voltages as low as 2.7V.
The SP3220EB driver can guarantee a data
rate of 250kbps fully loaded with 3kΩ in
parallel with 1000pF, ensuring compatibility
with PC-to-PC communication software. The
SP3220EU driver can guarantee a data rate
of 1000kbps fully loaded with 3kΩ in parallel
with 250pF.
The slew rate of the SP3220E and
SP3220EB outputs are internally limited to a
maximum of 30V/µs in order to meet the EIA
standards (EIA RS-232D 2.1.7, Paragraph
5). The transition of the loaded output from
HIGH to LOW also meet the monotonicity
requirements of the standard. The slew rate
of the SP3220EU is not limited. This allows
it to transmit at much faster data rates.
Figure 12 shows a loopback test circuit
used to test the RS-232 Driver. Figure
13 shows the test results of the loopback
circuit with the SP3220EB driver active at
250kbps with RS-232 load in parallel with
a 1000pF capacitor. Figure 14 shows the
test results where the SP3220EU driver
was active at 1000kbps and loaded with an
RS-232 receiver in parallel with 250pF ca-
pacitors. A solid RS-232 data transmission
rate of 250kbps provides compatibility with
many designs in personal computer periph-
erals and LAN applications.
The SP3220E/EB/EU driver's output stage
is turned o󰀨 (tri-state) when the device
is in shutdown mode. When the power is
o󰀨, the SP3220E/EB/EU device permits
the outputs to be driven up to +/-12V. The
driver's inputs do not have pull-up resistors.
Designers should connect unused inputs to
Vcc or GND.
In the shutdown mode, the supply current
falls to less than 1µA, where SHDN = LOW.
When the SP3220E/EB/EU device is shut
down, the device's driver output is disabled
DESCRIPTION
10
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(tri-stated) and the charge pump is turned
o󰀨 with V+ pulled down to Vcc and V- pulled
to GND. The time required to exit shutdown
is typically 100ms. Connect SHDN to Vcc if
the shutdown mode is not used. SHDN has
no e󰀨ect on RxOUT. Note that the driver is
enabled only when the magnitude of V- ex-
ceeds approximately 3V.
Receiver
The receiver converts EIA/TIA-232 levels
to TTL or CMOS logic output levels. The
receiver has an inverting high-impedance
output. This receiver output (RxOUT) is at
high-impedance when the enable control
EN = HIGH. In the shutdown mode, the
receiver can be active or inactive. EN has
no e󰀨ect on TxOUT. The truth table logic
of the SP3220E/EB/EU driver and receiver
outputs can be found in Table 2.
Table 2. SP3220E/EB/EU Truth Table Logic for
Shutdown and Enable Control
Figure 12. SP3220E/EB/EU Driver Loopback Test
Circuit
Since receiver input is usually from a trans-
mission line where long cable lengths and
system interference can degrade the signal,
the inputs have a typical hysteresis margin
of 300mV. This ensures that the receiver is
virtually immune to noisy transmission lines.
Should an input be left unconnected, an
internal 5KΩ pull-down resistor to ground
will commit the output of the receiver to a
HIGH state.
Figure 14. SP3220EU Loopback Test results at
1Mbps
Figure 13. SP3220EB Loopback Test results at
250kbps
SP3220
E/EB/EU
GND
TxIN TxOUT
C1+
C1-
C2+
C2-
V+
V-
V
CC
0.1µF
0.1
0.1
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
0.1
LOGIC
INPUTS
V
CC
5kΩ
RxIN
RxOUT
LOGIC
OUTPUTS
EN *SHDN
(SP3220EU 250pF)
(SP3220E/EB 1000pF)
V
CC
µF
µF
µF
µF
SHDN EN TxOUT RxOUT
0 0 Tri-state Active
01 Tri-state Tri-state
10Active Active
1 1 Active Tri-state
DESCRIPTION
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11
Charge Pump
The charge pump is an Exar-patended
design (U.S. 5,306,954) and uses a unique
approach compared to older less-e󰀩cient
designs. The charge pump still requires four
external capacitors, but uses a four-phase
voltage shifting technique to attain sym-
metrical 5.5V power supplies. The internal
power supply consists of a regulated dual
charge pump that provides output voltages
of +/-5.5V regardless of the input voltage
(Vcc) over the +3.0V to +5.5V range.
In most circumstances, decoupling the
power supply can be achieved adequately
using a 0.1µF bypass capacitor at C5 (refer
to gures 6 and 7). In applications that are
sensitive to power-supply noise, decouple
Vcc to ground with a capacitor of the same
value as charge-pump capacitor C1. Physi-
cally connect bypass capacitor as close to
the IC as possible.
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— VSS charge storage During this phase
of the clock cycle, the positive side of capaci-
tors C1 and C2 are initially charged to VCC.
Cl
+ is then switched to GND and the charge
in C1
is transferred to C2
. Since C2
+ is con-
nected to VCC, the voltage potential across
capacitor C2 is now 2 times VCC.
Phase 2
VSS transfer Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of
C2 to GND. This transfers a negative gener-
ated voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C3, the positive side of capacitor C1
is switched to VCC and the negative side is
connected to GND.
Phase 3
VDD charge storage — The third phase of
the clock is identical to the rst phase the
charge transferred in C1 produces –VCC in
the negative terminal of C1, which is applied
to the negative side of capacitor C2. Since
C2
+ is at VCC, the voltage potential across C2
is 2 times VCC.
Phase 4
VDD transfer — The fourth phase of
the clock connects the negative terminal
of C2 to GND, and transfers this positive
generated voltage across C2 to C4, the
VDD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched
to VCC and the negative side is con-
nected to GND, allowing the charge
pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal
oscillator are present.
Since both V+ and V are separately gener-
ated from VCC, in a no–load condition V+
and V will be symmetrical. Older charge
pump approaches that generate V from
V+ will show a decrease in the magnitude
of V compared to V+ due to the inherent
ine󰀩ciencies in the design.
DESCRIPTION
12
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DESCRIPTION
Charge Pump Design Guidelines
The charge pump operates with 0.1µF ca-
pacitors for 3.3V operation. For other supply
voltages, see the table for required capacitor
values. Do not use values smaller than those
listed. Increasing the capacitor values (e.g.,
by doubling in value) reduces ripple on the
transmitter outputs and may slightly reduce
power consumption. C2, C3, and C4 may be
increased without changing C1’s value.
Minimum recommended charge pump
capacitor value
Input Voltage
Vcc
Charge pump
capacitor value for
SP3220E/EB/EU
3.0V to 3.6V C1 - C4 = 0.1µF
3.0V to 5.5V C1 - C4 = 0.22µF
The charge pump oscillator typically operates
at greater than 250kHz allowing the pump to
run e󰀩ciently with small 0.1μF capacitors.
E󰀩cient operation depends on rapidly charg-
ing and discharging C1 and C2, therefore
capacitors should be mounted close to the
IC and have low ESR (equivalent series
resistance).
Low cost surface mount ceramic capacitors
(such as are widely used for power-supply
decoupling) are ideal for use on the charge
pump. However the charge pumps are de-
signed to be able to function properly with a
wide range of capacitor styles and values.
If polarized capacitors are used the positive
and negative terminals should be connected
as shown in the Typical Operating Circuit.
Voltage potential across any of the capaci-
tors will never exceed 2 x VCC. Therefore
capacitors with working voltages as low as
6.3V rating may be used with a 3.0V VCC
supply. The reference terminal of the V+
capacitor may be connected either to VCC
or ground, but if connected to ground a
minimum 10V working voltage is required.
Higher working voltages and/or capacitance
values may be advised if operating at higher
VCC or to provide greater stability as the
capacitors age.
Under lightly loaded conditions the intelligent
pump oscillator maximizes e󰀩ciency by
running only as needed to maintain V+ and
V-. Since interface transceivers often spend
much of their time at idle this power-e󰀩cient
innovation can greatly reduce total power
consumption. This improvement is made
possible by the independent phase sequence
of the Exar charge-pump design.
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13
Figure 16. Charge Pump — Phase 2
V
CC
= +5V
V
SS
Storage Capacitor
V
DD
Storage Capacito
C
1
C
2
C
3
C
4
+
+
++
-5.5V
VCC = +5V
–5V –5V
+5V
VSS Storage Capacitor
VDD Storage Capacitor
C1C2
C3
C4
+
+
++
Figure 15. Charge Pump — Phase 1
Figure 18. Charge Pump — Phase 3
V
CC
= +5V
–5V –5V
+5V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
Figure 19. Charge Pump — Phase 4
VCC = +5V
VSS Storage Capacitor
VDD Storage Capacito
r
C1C2
C3
C4
+
+
++
+5.5V
Figure 17. Charge Pump Waveforms
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V
2
1T
T[]
T
+6V
a) C
2+
b) C
2
-
GND
GND
-6V
DESCRIPTION
14
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
ESD TOLERANCE
The SP3220E/EB/EU device incorpo-
rates ruggedized ESD cells on all driver
output and receiver input pins. The ESD
structure is improved over our previous
family for more rugged applications and
environments sensitive to electro-static
discharges and associated transients. The
improved ESD tolerance is at least +15kV
without damage nor latch-up.
There are di󰀨erent methods of ESD testing
applied:
a) MIL-STD-883, Method 3015.7
b) IEC61000-4-2 Air-Discharge
c) IEC61000-4-2 Direct Contact
The Human Body Model has been the
generally accepted ESD testing method
for semi-conductors. This method is also
specied in MIL-STD-883, Method 3015.7
for ESD testing. The premise of this ESD test
is to simulate the human body’s potential to
store electro-static energy and discharge it
to an integrated circuit. The simulation is
performed by using a test model as shown
in Figure 20. This method will test the IC’s
capability to withstand an ESD transient
during normal handling such as in manu-
facturing areas where the IC's tend to be
handled frequently.
The IEC-61000-4-2, formerly IEC801-2, is
generally used for testing ESD on equipment
and systems. For system manufacturers,
they must guarantee a certain amount of ESD
protection since the system itself is exposed
to the outside environment and human pres-
ence. The premise with IEC61000-4-2 is that
the system is required to withstand an amount
of static electricity when ESD is applied to
points and surfaces of the equipment that
are accessible to personnel during normal
usage. The transceiver IC receives most
of the ESD current when the ESD source is
applied to the connector pins. The test circuit
for IEC61000-4-2 is shown on Figure 21.
There are two methods within IEC61000-4-2,
the Air Discharge method and the Contact
Discharge method.
With the Air Discharge Method, an ESD
voltage is applied to the equipment under
test (EUT) through air. This simulates an
electrically charged person ready to connect
a cable onto the rear of the system only to
nd an unpleasant zap just before the person
touches the back panel. The high energy
potential on the person discharges through
an arcing path to the rear panel of the system
before he or she even touches the system.
This energy, whether discharged directly or
through air, is predominantly a function of the
discharge current rather than the discharge
voltage. Variables with an air discharge such
as approach speed of the object carrying the
ESD potential to the system and humidity
will tend to change the discharge current.
For example, the rise time of the discharge
current varies with the approach speed.
The Contact Discharge Method applies the
ESD current directly to the EUT. This method
was devised to reduce the unpredictability
of the ESD arc. The discharge current rise
time is constant since the energy is directly
transferred without the air-gap arc. In situ-
ations such as hand held systems, the ESD
charge can be directly discharged to the
Figure 20. ESD Test Circuit for Human Body Model
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
DESCRIPTION
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
15
DEVICE PIN HUMAN BODY IEC61000-4-2
TESTED MODEL Air Discharge Direct Contact Level
Driver Outputs +15kV +15kV +8kV 4
Receiver Inputs +15kV +15kV +8kV 4
equipment from a person already holding
the equipment. The current is transferred
on to the keypad or the serial port of the
equipment directly and then travels through
the PCB and nally to the IC.
The circuit models in Figures 20 and 21 rep-
resent the typical ESD testing circuit used for
all three methods. The CS is initially charged
with the DC power supply when the rst
switch (SW1) is on. Now that the capacitor
is charged, the second switch (SW2) is on
while SW1 switches o󰀨. The voltage stored
in the capacitor is then applied through RS,
the current limiting resistor, onto the device
under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under
test receives a duration of voltage.
For the Human Body Model, the current
limiting resistor (RS) and the source capacitor
(CS) are 1.5kΩ an 100pF, respectively. For
IEC-61000-4-2, the current limiting resistor
(RS) and the source capacitor (CS) are 330Ω
an 150pF, respectively.
Figure 22. ESD Test Waveform for IEC61000-4-2
Figure 21. ESD Test Circuit for IEC61000-4-2
Table 3. Transceiver ESD Tolerance Levels
R
S
and
R
V
add up to 330Ω for IEC61000-4-2.
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
R
V
Contact-Discharge Model
t = 0ns t = 30ns
0A
15A
30A
I →
t →
The higher CS value and lower RS value in
the IEC61000-4-2 model are more stringent
than the Human Body Model. The larger
storage capacitor injects a higher voltage
to the test point when SW2 is switched on.
The lower current limiting resistor increases
the current charge onto the test point.
DESCRIPTION
16
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
PACKAGE: 16 PIN SSOP
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
17
PACKAGE: 16 PIN TSSOP
18
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
ORDERING INFORMATION(1)
Part Number
Operating
Temperature Range Lead-Free Package Package Method
SP3220EBCA-L/TR 0°C to 70°C
Yes(2)
SSOP Tape and Reel
SP3220EBCY-L/TR 0°C to 70°C TSSOP Tape and Reel
SP3220EBCY-L 0°C to 70°C TSSOP Rail
SP3220EBEA-L/TR -40°C to 85°C SSOP Tape and Reel
SP3220EBEA-L -40°C to 85°C SSOP Rail
SP3220EBEY-L/TR -40°C to 85°C TSSOP Tape and Reel
SP3220EBEY-L -40°C to 85°C TSSOP Rail
SP3220ECA-L/TR 0°C to 70°C SSOP Tape and Reel
SP3220ECA-L 0°C to 70°C SSOP Rail
SP3220ECY-L/TR 0°C to 70°C TSSOP Tape and Reel
SP3220ECY-L 0°C to 70°C TSSOP Rail
SP3220EEA-L/TR -40°C to 85°C SSOP Tape and Reel
SP3220EEA-L -40°C to 85°C SSOP Rail
SP3220EEY-L/TR -40°C to 85°C TSSOP Tape and Reel
SP3220EEY-L -40°C to 85°C TSSOP Rail
SP3220EUEY-L/TR -40°C to 85°C TSSOP Tape and Reel
NOTES:
1. Refer to www.exar.com/SP3220E, www.exar.com/SP3220EB, www.exar.com/SP3220EU for the most up-to-date Ordering Information.
2. Visit www.exar.com for additional information on Environmental Rating.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_102_102016
19
REVISION HISTORY
Notice
EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reli-
ability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are
only for illustration purposes and may vary depending upon a user's specic application. While the information in this publication has been carefully
checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to signicantly a󰀨ect its safety or e󰀨ectiveness. Products are not authorized for
use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been
minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2012-16 EXAR Corporation
Datasheet October 2016
For technical questions please email Exar's Serial Technical Support group at: serialtechsupport@exar.com
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Date Revision Description
08/30/05 -- Legacy Sipex Datasheet
02/02/11 1.0.0 Convert to Exar Format and update ordering information.
06/03/11 1.0.1 Remove SP3220EUCA-L(/TR) and SP3220EUEA-L(/TR) per
PDN 110510-01
10/20/16 1.0.2 Update input voltage range of receiver from +/-25V to +/-15V,
update ordering information table, remove WSOIC package
information