Integrated Circuit Solution Inc. 1
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The 1+51 IC62LV2568L and IC62LV2568LL are low power
and low VCC, 262,144-bit words by 8 bits CMOS static RAMs.
They are fabricated using 1+51's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance and
low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62LV2568L and IC62LV2568LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE2
OE
WE
2048 x 128 x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE1
IC62LV2568L
IC62LV2568LL
256K x 8 LOW POWER and LOW V++
CMOS STATIC RAM
FEATURES
Access times of 55, 70, 100 ns
Low active power: 126 mW (max, L, LL)
Low standby power: 36 µW (max, L) and 7.2
µW (max, LL) CMOS standby
Low data retention voltage: 1.5V (min.)
Available in Low Power (-L) and Ultra-Low
Power (-LL)
Output Enable (OE) and two Chip Enable
TTL compatible inputs and outputs
Single 2.7V-3.6V power supply
Available in the 32-pin 8x20mm TSOP-1, 32-pin
8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA
2Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN CONFIGURATIONS
32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1
PIN DESCRIPTIONS
A0-A17 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Data Input/Output
NC No Connection
Vcc Power
GND Ground
48-Pin 6*8mm TF-BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0 A1 CE2 A3 A6 A8
I/O
4
A2 WE A4 A7 I/O
0
I/O
5
NC A5 I/O
1
GND Vcc
Vcc GND
I/O
6
NC A17 I/O
2
I/O
7
OE CE1 A16 A15 I/O
3
A9 A10 A11 A12 A13 A14
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V - 3.6V
Industrial 40°C to +85°C 2.7V - 3.6V
Integrated Circuit Solution Inc. 3
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 V
VCC Vcc related to GND 0.3 to +4.0 V
TBIAS Temperature Under Bias 40 to +85 °C
TSTG Storage Temperature 65 to +150 °C
PTPower Dissipation 0.7 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = 1.0 mA 2.2 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL(1) Input LOW Voltage(1) 0.3 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC 1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC 1 1 µA
Notes:
1. VIL = 2.0V for pulse width less than 10 ns.
TRUTH TABLE
Mode WEWE
WEWE
WE CE1CE1
CE1CE1
CE1 CE2 OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X X High-Z ISB, ISB
(Power-down) X X L X High-Z ISB, ISB
Output Disabled H L H H High-Z ICC
Read HLHL DOUT ICC
Write L L H X DIN ICC
4Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
IC62LV2568L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. 40 30 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind.45 35 25
ISBTTL Standby Current VCC = Max., Com. 0.4 0.4 0.4 mA
(TTL Inputs) VIN = VIH or VIL, Ind. 1.0 1.0 1.0
CE1
≥
VIH or CE2
≤
VIL, f = 0
ISB CMOS Standby VCC = Max., f = 0 Com. 35 35 35 µA
Current (CMOS Inputs) CE1
≥
VCC 0.2V, Ind. 50 50 50
CE2
≤
0.2V,
or VIN
≥
VCC 0.2V, VIN
≤
0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV2568LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. 40 30 20 mA
Supply Current IOUT = 0 mA, f = fMAX Ind.45 35 25
ISBTTL Standby Current VCC = Max., Com. 0.4 0.4 0.4 mA
(TTL Inputs) VIN = VIH or VIL, Ind. 1.0 1.0 1.0
CE1
≥
VIH or CE2
≤
VIL, f = 0
ISB CMOS Standby VCC = Max., f = 0 Com. 10 10 10 µA
Current (CMOS Inputs) CE
≥
VCC 0.2V, Ind. 15 15 15
CE2
≤
0.2V,
or VIN
≥
VCC 0.2V, VIN
≤
0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc. 5
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 55 70 100 ns
tAA Address Access Time 55 70 100 ns
tOHA Output Hold Time 10 10 15 ns
tACE1CE1 Access Time 55 70 100 ns
tACE2 CE2 Access Time 55 70 100 ns
tDOE OE Access Time 30 35 50 ns
tLZOE
(2)
OE to Low-Z Output 5 5 5 ns
tHZOE
(2)
OE to High-Z Output 20 0 25 0 30 ns
tLZCE1
(2)
CE1 to Low-Z Output 10 10 10 ns
tLZCE2
(2)
CE2 to Low-Z Output 10 10 10 ns
tHZCE
(2)
CE1 or CE2 to Low-Z Output 0 20 0 25 0 30 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
5 pF
Including
jig and
scope
OUTPUT
1 TTL
100 pF
Including
jig and
scope
OUTPUT
1 TTL
6Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIL.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
AC WAVEFORMS
READ CYCLE NO. 2(1,3)
AC TEST LOADS
READ CYCLE NO.1(1,2)
DATA VALID
tAA
tOHA tOHA
tRC
DOUT
ADDRESS
Integrated Circuit Solution Inc. 7
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
-55 -70 -100
Symbol Parameter Min. Max. Min. Max. Min. Max Unit
tWC Write Cycle Time 55 70 100 ns
tSCE1CE1 to Write End 45 65 80 ns
tSCE2 CE2 to Write End 45 65 80 ns
tAW Address Setup Time to Write End 45 65 80 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Setup Time 0 0 0 ns
tPWE
(4)
WE Pulse Width 50 55 70 ns
tSD Data Setup to Write End 25 30 40 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE
(3)
WE LOW to High-Z Output 25 25 30 ns
tLZWE
(3)
WE HIGH to Low-Z Output 5 5 5 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE
(4)
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE1
CE2
WE
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
8Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE1
t
SA
t
HA
t
SCE2
t
PWE(4)
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
DIN
CE1
CE2
WE
DOUT
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the HIGH-z state if OE =VIH.
Integrated Circuit Solution Inc. 9
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V
IDR Data Retention Current Vcc = 2.0V, CE1
≥
Vcc 0.2V Com. (-L) 20 µA
Com. (-LL) 5 µA
Ind. (-L) 25 µA
Ind. (-LL) 7 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC ns
DATA RETENTION WAVEFORM (CE2 Controlled)
V
CC
t
SDR
t
RDR
V
DR
0.4V
2.7V
CE2
GND
2.2V
Data Retention Mode
CE2 ≤ 0.2V
DATA RETENTION WAVEFORM (CE1 Controlled)
V
CC
CE1 ≥ V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
2.7V
2.2V
Data Retention Mode
10 Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IC62LV2568L-55T 8*20mm TSOP-1
IC62LV2568L-55H 8*13.4mm TSOP-1
IC62LV2568L-55B 6*8mm TF-BGA
70 IC62LV2568L-70T 8*20mm TSOP-1
IC62LV2568L-70H 8*13.4mm TSOP-1
IC62LV2568L-70B 6*8mm TF-BGA
100 IC62LV2568L-100T 8*20mm TSOP-1
IC62LV2568L-100H 8*13.4mm TSOP-1
IC62LV2568L-100B 6*8mm TF-BGA
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
55 IC62LV2568L-55TI 8*20mm TSOP-1
IC62LV2568L-55HI 8*13.4mm TSOP-1
IC62LV2568L-55BI 6*8mm TF-BGA
70 IC62LV2568L-70TI 8*20mm TSOP-1
IC62LV2568L-70HI 8*13.4mm TSOP-1
IC62LV2568L-70BI 6*8mm TF-BGA
100 IC62LV2568L-100TI 8*20mm TSOP-1
IC62LV2568L-100HI 8*13.4mm TSOP-1
IC62LV2568L-100BI 6*8mm TF-BGA
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IC62LV2568LL-55T 8*20mm TSOP-1
IC62LV2568LL-55H 8*13.4mm TSOP-1
IC62LV2568LL-55B 6*8mm TF-BGA
70 IC62LV2568LL-70T 8*20mm TSOP-1
IC62LV2568LL-70H 8*13.4mm TSOP-1
IC62LV2568LL-70B 6*8mm TF-BGA
100 IC62LV2568LL-100T 8*20mm TSOP-1
IC62LV2568LL-100H 8*13.4mm TSOP-1
IC62LV2568LL-100B 6*8mm TF-BGA
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
55 IC62LV2568LL-55TI 8*20mm TSOP-1
IC62LV2568LL-55HI 8*13.4mm TSOP-1
IC62LV2568LL-55BI 6*8mm TF-BGA
70 IC62LV2568LL-70TI 8*20mm TSOP-1
IC62LV2568LL-70HI 8*13.4mm TSOP-1
IC62LV2568LL-70BI 6*8mm TF-BGA
100 IC62LV2568LL-100TI 8*20mm TSOP-1
IC62LV2568LL-100HI 8*13.4mm TSOP-1
IC62LV2568LL-100BI 6*8mm TF-BGA
