SEMICONDUCTOR
8-3
Features
• Accurate Timing From Microseconds Through Hours
• Astable and Monostable Operation
• Adjustable Duty Cycle
• Output Capable of Sourcing or Sinking up to 200mA
• Output Capable of Driving TTL Devices
• Normally ON and OFF Outputs
• High Temperature Stability . . . . . . . . . . . . . . 0.005%/oC
• Directly Interchangeable with SE555, NE555, MC1555,
and MC1455
Applications
• Precision Timing • Pulse Generation
• Sequential Timing • Pulse Detector
• Time Delay Generation • Pulse Width and Position
Modulation
Description
The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accu-
rate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately con-
trolled free running frequency and duty cycle with only two
external resistors and one capacitor.
The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.
Ordering Information
PART NUMBER
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA0555E -55 to 125 8 Ld PDIP E8.3
CA0555M (555) -55 to 125 8 Ld SOIC M8.15
CA0555M96 (555) -55 to 125 8 Ld SOIC † M8.15
CA0555T -55 to 125 8 Pin Metal Can T8.C
CA0555CE 0 to 70 8 Ld PDIP E8.3
CA0555CM (555C) 0 to 70 8 Ld SOIC M8.15
CA0555CM96 (555C) 0 to 70 8 Ld SOIC † M8.15
CA0555CT 0 to 70 8 Pin Metal Can T8.C
LM555N -55 to 125 8 Ld PDIP E8.3
LM555CN 0 to 70 8 Ld PDIP E8.3
NE555N 0 to 70 8 Ld PDIP E8.3
NOTE: † Denotes Tape and Reel
Pinouts
CA555, CA555C (PDIP, SOIC)
LM555, LM555C, NE555 (PDIP)
TOP VIEW
CA555, CA555C (METAL CAN)
TOP VIEW
Functional Block Diagram
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
V+
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
V+
THRESHOLD
TRIGGER
RESET
GND
OUTPUT
DISCHARGE
CONTROL
2
4
6
1
3
7
5
8TAB
VOLTAGE
THRESHOLD
COMPAR
6
THRESHOLD
8
V+
5
TRIGGER
COMPAR
2
CONTROL
VOLTAGE
TRIGGER
FLIP-FLOP
OUTPUT
3
OUTPUT
7
DISCHARGE
4
RESET
1
GND
May 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
CA555, CA555C,
LM555, LM555C, NE555
Timers f or Timing Dela ys and Oscillator Application
in Commer cial, Industrial and Military Equipment
File Number 834.4
8-4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Operating Conditions
Temperature Range
CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Metal Can Package . . . . . . . . . . . . . . . 170 85
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
SOIC Package. . . . . . . . . . . . . . . . . . . 160 N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA555, LM555 CA555C, LM555C, NE555
UNITSMIN TYP MAX MIN TYP MAX
DC Supply Voltage V+ 4.5 - 18 4.5 - 16 V
DC Supply Current (Low State),
(Note 2) I+ V+ = 5V, RL = ∞-35- 36mA
V+ = 15V, RL = ∞- 10 12 - 10 15 mA
Threshold Voltage VTH -(
2
/
3
)V+ - - (2/3)V+ - V
Trigger Voltage V+ = 5V 1.45 1.67 1.9 - 1.67 - V
V+ = 15V 4.8 5 5.2 - 5 - V
Trigger Current - 0.5 - - 0.5 - µA
Threshold Current (Note 3) ITH - 0.1 0.25 - 0.1 0.25 µA
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current - 0.1 - - 0.1 - mA
Control Voltage Level V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V
V+ = 15V 9.6 10 10.4 9 10 11 V
Output Voltage VOL V+ = 5V, ISINK = 5mA - - - - 0.25 0.35 V
Low State ISINK = 8mA - 0.1 0.25 - - - V
V+ = 15V, ISINK = 10mA - 0.1 0.15 - 0.1 0.25 V
ISINK = 50mA - 0.4 0.5 - 0.4 0.75 V
ISINK = 100mA - 2.0 2.2 - 2.0 2.5 V
ISINK = 200mA - 2.5 - - 2.5 - V
Output Voltage VOH V+ = 5V, ISOURCE = 100mA 3.0 3.3 - 2.75 3.3 - V
High State V+ = 15V, ISOURCE = 100mA 13.0 13.3 - 12.75 13.3 - V
ISOURCE = 200mA - 12.5 - - 12.5 - V
Timing Error (Monostable) R1, R2 = 1kΩ to 100k Ω,
C = 0.1µF
Tested at V+ = 5V, V+ = 15V
- 0.5 2 - 1 - %
Frequency Drift with Temperature - 30 100 - 50 - ppm/oC
Drift with Supply Voltage - 0.05 0.2 - 0.1 - %/V
CA555, CA555C, LM555, LM555C, NE555
8-5
Schematic Diagram
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay ener-
gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R1CT. When the
voltage across the capacitor equals 2/3 V+, the comparator
resets the flip-flop which in turn discharges the capacitor rap-
idly and drives the output to its lo w state.
Output Rise Time tR- 100 - - 100 - ns
Output Fall Time tF- 100 - - 100 - ns
NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total
R1 + R2 = 20MΩ.
Electrical Specifications TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS
CA555, LM555 CA555C, LM555C, NE555
UNITSMIN TYP MAX MIN TYP MAX
6
THRESHOLD
7
RESET
DISCHARGE
V-
RESET
DISCHARGE
3
OUTPUT
OUTPUTFLIP-FLOP
TRIGGER
COMPARATOR
THRESHOLD
COMPARATOR
4.7K 830 4.7K
D2
D1
Q3Q4
Q7
Q5
Q2
Q1
10K
Q8
Q6100
100K
Q9
Q11 Q12
1K
Q10
5K
Q13
Q16
7K
D3
Q14
Q15
Q17
3.9K
Q19
Q20
Q21
Q18
8
V+
CONTROL
VOLTAGE
5K 6.8K
5K
4.7K
220
4.7K
5
2
4
1
TRIGGER
D4
NOTE: Resistance values are in ohms.
CA555, CA555C, LM555, LM555C, NE555
8-6
Since the charge rate and threshold level of the comparator
are both directly propor tional to V+, the timing interval is rel-
atively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Applying a negative pulse simultaneously to the reset ter mi-
nal (4) and the trigger terminal (2) during the timing cycle
discharges CT and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges CT, but the timing cycle does not restart.
Figure 2 shows the typical waveforms generated during this
mode of operation, and Figure 3 gives the family of time
delay curves with variations in R1 and CT.
Repeat Cycle Timer (Astable Operation)
Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R1 and R2.
T = 0.693 (R1 + 2R2) CT = t1 + t2
where t1 = 0.693 (R1 + R2) CT
and t2 = 0.693 (R2) CT
the duty cycle is:
Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of cur ves of
free running frequency with variations in the value of
(R1+2R
2
) and CT.
1
CA555 EO
8
5
2
6
7
3
4680
RESET
R1
CT4.7K 680
10K
0.01µF
RELAY
COIL
1N4001
V+
5V
S1
START
NOTE: All resistance values are in ohms.
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
tD
3V
3.3V
5V
0
0
0
SWITCH S1 “OPEN”
SWITCH S1 “CLOSED”
INPUT
VOLTAGE (TERMINAL 2)
CAPACITOR
VOLTAGE (TERMINALS 6, 7)
OUTPUT
VOLTAGE
(TERMINAL 3)
FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER
TIME DELAY(s)
10110-1
0.1
0.01
0.001
TA = 25oC
R1 = 1kΩ10kΩ
CAPACITANCE (µF)
1
10
100
V+ = 5V
100kΩ
1MΩ10MΩ
10-2
10-3
10-4
10-5
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE
1
CA555 EO
8
5
2
6
7
3
4
R1
CT0.01µF
RELAY
COIL
R2
V+
5V
FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)
t1
t1t2
+
---------------- =R1R2
+
R12R2
+
------------------------
CA555, CA555C, LM555, LM555C, NE555
8-7
Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)
FIGURE 5. TYPICAL W AVEFORMS FOR REPEAT CYCLE TIMER FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE
Typical Performance Curves
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER
VOLTAGE FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs
SOURCE CURRENT FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
5V
0
3.3V
1.7V
0
t2
t1100
10
0.1
0.01
0.001
CAPACITANCE (µF)
FREQUENCY (Hz)
10-1 110
102103104105
TA = 25oC, V+ = 5V
R1 + 2R2 = 1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
1
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
0.40.30.20.10
150
100
50
TA = -55oC
25oC
125oC
70oC
0oC
MINIMUM PULSE WIDTH (ns)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1512.5107.552.50
10
9
8
7
6
5
4
3
2
1
TA = 125oC
25oC
50oC
SOURCE CURRENT (mA)
SUPPLY VOLTAGE - OUTPUT VOLTAGE (V)
100101
2.0
1.6
1.2
0.8
0.4
0
25oC
TA = -55oC
125oC
5V ≤ V+ ≤ 15V
SINK CURRENT (mA)
OUTPUT V OLTAGE - LOW STATE (V)
100101
10.0
1.0
0.1
0.01
25oC
TA = -55oC
125oC
V+ = 5V
CA555, CA555C, LM555, LM555C, NE555
8-8
FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE FIGURE 14. DELAY TIME vs TEMPERATURE
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE
Typical Performance Curves
(Continued)
SINK CURRENT (mA)
OUTPUT V OLTAGE - LOW STATE (V)
100101
10.0
1.0
0.1
0.01
25oC125oC
V+ = 10V
125oC
25oC
TA = -55oC
SINK CURRENT (mA)
OUTPUT V OLTAGE - LOW STATE (V)
100101
10.0
1.0
0.1
0.01
-55oC
V+ = 15V
125oC
25oC
TA = -55oC
SUPPLY VOLTAGE (V)
NORMALIZED DELAY TIME
1512.5107.552.50
1.100
1.000
0.990
0.980
TA = 25oC
17.5
TEMPERATURE (oC)
1007550250-25-75
1.005
0.995
0.985 125
-50
NORMALIZED DELAY TIME
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
0.40.30.20.10
150
100
50
TA = -55oC
0oC
PROPAGATION DELAY TIME (ns)
200
250
300
25oC
125oC
70oC
CA555, CA555C, LM555, LM555C, NE555
