Am27H256 256 Kilobit (32,768 x 8-Bit) High Speed CMOS EPROM al Advanced Micro Devices DISTINCTIVE CHARACTERISTICS @ Fast access time 35ns @ JEDEC-approved pinout Pin compatible with Am27C256 @ Single +5 V power supply @ +10% power supply tolerance available @ 100% Flashrite programming Typical programming time of 4 seconds @ Latch-up protected to 100 mA from 1 V to Vec+1V H High noise immunity @ Standard 28-pin DIP, PDIP, 32-pin LCC and PLCC packages m@ DESC SMD No. 5962-86063 GENERAL DESCRIPTION The Am27H256 is an 256 Kbit ultraviolet erasable pro- grammabie read-only memory. It is organized as 32K words by 8 bits per word, operates froma single +5 V supply, and features fast single address location pro- gramming. Products are available in windowed ceramic DIP and LCC packages as well as plastic one time pro- grammable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 35 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27H256 offers separate Output Enable (OE) and Chip Enable (CE) BLOCK DIAGRAM Oo> Vpp Oo Vcc Oo* Vss ar Output Enable OE Chip Enable CE and P Y Decoder A0-A14 Address Inputs xX Decoder controls, thus eliminating bus contention in a multiple bus microprocessor system. AMDs CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 220 mW in active mode, and 50 mW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27H256 supports AMDs Flash- rite programming algorithm (100 ps pulses) resulting in typical programming time of 4 seconds. Data Outputs DQ0-DQ7 hha tsar Output Buffers 262,144-Bit Cell Matrix 14944C-1 Publication# 14944 Rev.C Amendment/0 Issue Date: July 1993 3-9cl AMD PRODUCT SELECTOR GUIDE Family Part No. Am27H256 Ordering Part Number Vec +5% -35V05 Vec + 10% -35 -45 Max Access Time (ns) 35 -45 CE (E) Access Time (ns) 35 -45 OE (G) Access Time (ns) 20 20 CONNECTION DIAGRAMS Top View DIP PLCC/LCC _ wet a Veep 1 ~ 281] Voc @ Al2 [2 27 {] a14 2 N ow A7 []3 26 [] A13 exziQls A [4 25 [] A8 MMMM AS [I5 24 [] Ag 432 4 A4 []6 23 [] att AG a3 7 22 [] OE G) AS A2 [8 211] Ato A4 Ai f]9 20 1 cE &) ne Ao [J 10 19 1] Daz At pao {] 11 18 [] Dae AO pai {j 12 17) bas NC paz J 13 16 |] Da4 DaC Vss [] 14 15 [] Das SSE 14944C-2 GOS BNGS R389 Notes: < 1. JEDEC nomenclature is in parentheses. S 2. Dont use (DU) for PLCC. A8 AQ Alt NC A10 DQ7 DQ6 OE (G) CE (E) 14944C-3 PIN DESIGNATIONS LOGIC SYMBOL A0-A14 = Address Inputs CE (E) = Chip Enable 15 DQ0-DQ7 = Data Inputs/Outputs tr> AO-A14 NC = No Internal Connection OE (G) = Output Enable Input 8 Vec = Vcc Supply Voltage DQ0-DQ7 K/> Vpp = Program Supply Voltage Vss = Ground } CE (E) | OE (G) 14944C-4 3-10 Am27H256AMD al ORDERING INFORMATION EPROM Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27H256 35 D Cc Le OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in TEMPERATURE RANGE Commercial (0C to +70C) Industrial (-40C to +85C) Extended Commercial (-55C to +125C) oO | | E PACKAGE TYPE D = 28-Pin Ceramic DIP (CDV028) L = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H256 256 Kilobit (32,768 x 8-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27H256-35 DC, DCB, Di, DIB, Valid Combinations list configurations planned to AM27H256-35V05 | LC, LI, LCB, LIB be supported in volume for this device. Consult AM27H256-45 DC, DCB, DE, DEB the local AMD sales office to confirm availability of DI, DIB, "LC. LCB specific valid combinations and to check on newly LI, LIB, LE, LEB , released combinations. Am27H256 3-1161 amo ORDERING INFORMATION OTP Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27H256 -35 P Cc Le OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 032) J 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H256 256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM Valid Combinations AM27H256-35V05 PC. JC Valid Combinations list configurations planned to AM27H256-45 , be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations 312 Am27H256AMD al ORDERING INFORMATION Military APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27H256 -45 /B xX A LL LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 28-Pin Ceramic DIP (CDV032) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H256 256 Kilobit (32,768 x 8-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27H256-45 /BXA, /BUA Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am27H256 3-13al AMD FUNCTIONAL DESCRIPTION Erasing the Am27H256 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27H256 to an ultraviolet light source. A dosage of 15 W seconds/cm2is required to completely erase an Am27H256. This dos- age can be obtained by exposure to an ultraviolet lampwavelength of 2537 Awith intensity of 12,000 unW/cm? for 15 to 20 minutes. The Am27H256 should be directly under and about one inch from the source and all filters should be removed from the UV light Source prior to erasure. It is important to note that the Am27H256 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 25374, exposure to fluorescent light and sunlight will eventually erase the Am27H256 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27H256 Upon delivery or after each erasure the Am27H256 has all 262,144 bits in the ONE or HIGH state. ZEROs are loaded into the Am27H256 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 V is applied to the Ver pin, CE is at Vi. and OE is at Vin. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Fiashrite algorithm reduces programming time by using 100 us programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. if the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27H256. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Vcc = Vep = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27H256 in parallel with \ dif- ferent data is also easily accomplished. Except for CE, all like inputs of the parallel Am27H256 may be com- mon. A TTL low-level program pulse applied to an Am27H256 CE input with Vpp = 12.75 V+ 0.25 V andOE high, will program that Am27H256. A high-level CE input inhibits the other Am27H256 devices from being pro- grammed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at Vi, CE at Vin and Vep between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27H256. To activate this mode, the programming equipment must force 12.0 V + 0.5 V on address line AQ of the Am27H256. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (AO = ViL) represents the manufacturer code, and byte 1 (AO = Vin), the device code. For the Am27H256, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27H256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that ad- dresses are stable, address access time (tacc ) is equal to the delay from CE to output (tce). Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Datais available at the outputs toe after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tacc toe. 3-14 Am27H256Standby Mode The Am27H256 has a standby mode which reduces the maximum Vcc current to 50% of the active current. It is placed in standby mode when CE is at Vin. The amount of current drawn in standby mode depends on the fre- quency and the number of address pins switching. The Am27H256 is specified with 50% of the address lines toggling at 10 MHz. A reduction of the frequency or quantity of address lines toggling will significantly re- duce actual standby current. Output OR-Tieing To accommodate multiple memory connection, a two- line control function is provided to allow for: B Low memory power dissipation @ Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and con- AMD al nected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular mem- ory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1-.F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Voc and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7-L1F bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode __ Pins . CE OE Ao rX:) Vep Outputs Read Vi VIL AO AQ Voc Dout Output Disable VIL VIH X X Voc Hi-Z Standby Vi xX X X Vec Hi-Z Program Vit Vin X X Vpp DIN Program Verify Vin Vit X X Vpp Dour Program Inhibit ViH VIH X X Vpp Hi-Z Auto Select Manufacturer Code ViL ViL VIL VH Vec 01H (Note 3) Device Code Vit Vit Vi VH Vec 10H Notes: 1. Vo=12.0V405V 2. X= Either Vin or Vit 3. A1-A8 = A10-A14 = Vit 4 . The Am27H256 uses the same Flashrite algorithm during programming as the Am27C256. Am27H256 3-15al AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ................. 65C to +125C All Other Products .............. -65C to +150C Ambient Temperature with Power Applied ............. 55C to +4125C Voltage with Respect to Vss All pins except A9,Vpp Vcc .... 0.6 V to Vcc +0.5 V (Note 1) AQ and Vpp (Note 2)............ 0.6Vt0o+13.5V VEC Lecce eee 0.6Vto+7.0V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot Vss to -2.0 V for pe- riods of up to 20 ns. Maximum DC voltage on input and lO pins is Vcc + 0.5 Vwhich may overshoot to Vcc + 2.0 Vfor periods up to 20ns. 2. For A9 and Vpp the minimum DC input is -0.5 V. During transitions, A9 and Vpp may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed 13.5 V for any period of time . Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C Industrial (I) Devices Case Temperature (Tc) ........ 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc) ....... 55C to +125C Military (M) Devices Case Temperature (Tc) ....... 55C to +125C Supply Read Voltages Vec for AM27H256-XXV05 ... +4.75 V to +5.25 V Vcc for AmM27H256-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 3-16 Am27H256DC CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 2, 3 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 7 and 8 are tested unless otherwise noted) AMD al Parameter Symbol | Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage loH = -4 mA 2.4 Vv VoL Output LOW Voltage lo.=12mA 0.45 Vv VIH Input HIGH Voltage 2.0 Voc + 0.5 V VIL Input LOW Voltage 0.3 +0.8 V CA Devices 1.0 lu Input Load Current VIN = 0 V to +Vcc yA E/M Devices 1.0 C/l Devices 10.0 ILo Output Leakage Current VouT = 0 V to +Vcc A E/M Devices 10.0 lees Vcc Active Current CE = Vit, f = 10 MHz C/I Devices 50 (Note 3) lout = O mA mA E/M Devices 60 Icc2 Vcc Standby Current CE = VIH C/I Devices 25 mA E/M Devices 35 IPP Vpp Current During Read CE = OE = Vil, Vpp = Voc 100 pA Notes: 1. 2 3. 4 Vcc must be applied simultaneously or before Vep, and removed simultaneously or after Ver. Caution: The Am27H256 must not be removed from (or inserted into) a socket when Vec or Vep is applied. Icc1 is tested with OE/Vpp = Vin to simulate open outputs. . Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc + 0.5 V, which may overshoot to Vcc + 2.0 V for periods less than 20 ns. 70 55 yaa < 60 ~ 50 S ye 5 6 4 ac ze 5 SES g 1 as 5 Q | 40 AD 40 30 35 1 2 3 4 5 6 7 8 9 10 -60 40 -20 20 40 60 80 100 120 140 Frequency in MHz Temperature C 14944C-5 14944C-6 Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vee = 5.0 V, T = 25C Veco = 5.0 V, f = 10 MHz Am27H256 3-17cl AMD CAPACITANCE Parameter Test CDV028 CLV032 PD 028 PL 032 Symbol Parameter Description Conditions Typ | Max| Typ | Max | Typ | Max | Typ | Max | Unit CIN Input Capacitance VIN =0 6 12 6 12 8 12 8 12 pF CouT Output Capacitance Vout = 0 8 15 6 15 10 15 10 15 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. Ta = +25C, f = 1 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9,10 and 11 are tested unless otherwise noted) Parameter Am27H256 Symbols -35V05 JEDEC Standard Parameter Description Test Conditions -35 -45 tavav tRec Address to CE = OE = Vi Min Output Delay CL =Cu Max 35 45 tELQV tce Chip Enable to OE = Vit Min Output Delay Ci = Cu Max 35 45 teLav toe Output Enable to CE = Vi Min Output Delay Cr = Cu Max 20 20 tEHQZ, tDF Chip Enable HIGH or Ci = Cre Min 0 0 Output Enable HIGH, tGHQz (Note 2) whichever comes Max 20 20 first, to Output Float tAaxax tOH Output Hold from Min 0 0 Addresses, CE, Max or OE, whichever occurred first Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27H256 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4 . Output Load: 1 TTL gate and C = C1 Input Rise and Fall Times: 5 ns Input Pulse Levels: 0 V to 3 V. Timing Measurement Reference Level: 1.5 V for inputs and outputs 3-18 Am27H256AMD al SWITCHING TEST CIRCUIT Ri Device . Under WN Vi Test CL Ri =121Q VL =1.9V Ci = 30 pF Cz =5p 14944C-7 SWITCHING TEST WAVEFORM 3V 1 i Test Points \ OV Input Output 14944C-8 AC Testing: Inputs are driven at 3.0 V for a logic "1" and 0 V for a logic 0. Input pulse rise and fall times are < 5 ns. Am27H256 3-19al AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L to H from L to H Dont Care, Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedence Off State KS000010 SWITCHING WAVEFORMS 3V -~ Addresses ee 15V Addresses Valid 1.5V OV ---- CE \ _ OE \ E ---- tDF taco toe > (Note 2) High Z (Note 1) oo High Z Output ( Valid Output by) } oe 14944C-9 Notes: 1. OE may be delayed up to tacc toe after the falling edge of the addresses without impact on tacc. 2. tDF is specified from OE or CE, whichever occurs first. 3-20 Am27H256