Cover Marvell(R) PXA270 Processor Electrical, Mechanical, Thermal Specification Doc. No. MV-S104690-00 , Rev. D April 2009 Marvell. Moving Forward Faster Released PXA270 Processor Electrical, Mechanical, and Thermal Specification Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Draft For internal use. This document has not passed a complete technical review cycle and ECN signoff process. Preliminary Tapeout (Advance) This document contains design specifications for a product in its initial stage of design and development. A revision of this document or supplementary information may be published at a later date. Marvell may make changes to these specifications at any time without notice. Contact Marvell Field Application Engineers for more information. Preliminary Information This document contains preliminary specifications. A revision of this document or supplementary information may be published at a later date. Marvell may make changes to these specifications at any time without notice. . Contact Marvell Field Application Engineers for more information. Complete Information This document contains specifications for a product in its final qualification stages. Marvell may make changes to these specifications at any time without notice. Contact Marvell Field Application Engineers for more information. Milestone Indicator: Draft = 0.xx Advance = 1.xx Preliminary = 2.xx Doc Status: X.YZ Work in Progress Indicator Zero means document is released. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2009. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. Intel XScale(R) is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. All other trademarks are the property of their respective owners. Doc. No. MV-S104690-00 Rev. D Page 2 Copyright (c) 2009 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 1 Introduction..................................................................................................................................11 1.1 About This Document......................................................................................................................................11 1.1.1 Number Representation....................................................................................................................11 1.1.2 Typographical Conventions ..............................................................................................................11 1.1.3 Applicable Documents ......................................................................................................................11 2 Functional Overview ...................................................................................................................13 3 Package Information ...................................................................................................................15 3.1 Package Information .......................................................................................................................................16 3.2 Processor Materials ........................................................................................................................................24 3.3 Junction To Case Temperature Thermal Resistance......................................................................................25 3.4 Processor Markings ........................................................................................................................................25 3.5 Tray Drawing ...................................................................................................................................................25 4 Pin Listing and Signal Definitions .............................................................................................27 4.1 Ball Map View .................................................................................................................................................27 4.1.1 13x13 mm VF-BGA Ball map............................................................................................................27 4.1.2 23x23 mm PBGA Ball map ...............................................................................................................32 4.2 Pin Use............................................................................................................................................................35 4.3 Signal Types ...................................................................................................................................................58 4.4 Memory Controller Reset and Initialization......................................................................................................59 4.5 Power-Supply Pins ..........................................................................................................................................60 5 Electrical Specifications .............................................................................................................63 5.1 Absolute Maximum Ratings ............................................................................................................................63 5.2 Operating Conditions ......................................................................................................................................64 5.2.1 Internal Power Domains ...................................................................................................................68 5.3 Power-Consumption Specifications.................................................................................................................69 5.4 DC Specification..............................................................................................................................................74 5.5 Oscillator Electrical Specifications...................................................................................................................75 5.5.1 32.768-kHz Oscillator Specifications ................................................................................................75 5.5.2 13.000-MHz Oscillator Specifications ...............................................................................................77 5.6 CLK_PIO and CLK_TOUT Specifications .......................................................................................................78 5.7 48 MHz Output Specifications .........................................................................................................................79 6 AC Timing Specifications ...........................................................................................................81 6.1 AC Test Load Specifications ...........................................................................................................................81 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 3 PXA270 Processor Electrical, Mechanical, and Thermal Specification 6.2 Reset and Power Manager Timing Specifications...........................................................................................82 6.2.1 Power-On Timing Specifications.......................................................................................................82 6.2.2 Hardware Reset Timing ....................................................................................................................84 6.2.3 Watchdog Reset Timing ...................................................................................................................84 6.2.4 GPIO Reset Timing...........................................................................................................................84 6.2.5 Sleep Mode Timing ...........................................................................................................................86 6.2.6 Deep-Sleep Mode Timing .................................................................................................................87 6.2.7 GPIO states in Deep-Sleep mode ....................................................................................................88 6.2.8 Standby-Mode Timing.......................................................................................................................90 6.2.9 Idle-Mode Timing ..............................................................................................................................90 6.2.10 Frequency-Change Timing ...............................................................................................................90 6.2.11 Voltage-Change Timing ....................................................................................................................90 6.3 GPIO Timing Specifications ............................................................................................................................91 6.4 Memory and Expansion-Card Timing Specifications.......................................................................................91 6.4.1 Internal SRAM Read/Write Timing Specifications.............................................................................92 6.4.2 SDRAM Parameters and Timing Diagrams ......................................................................................92 6.4.3 ROM Parameters and Timing Diagrams...........................................................................................98 6.4.4 Flash Memory Parameters and Timing Diagrams ..........................................................................103 6.4.5 SRAM Parameters and Timing Diagrams.......................................................................................113 6.4.6 Variable-Latency I/O Parameters and Timing Diagrams ................................................................116 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams ........................................................119 6.5 LCD Timing Specifications ............................................................................................................................122 6.6 SSP Timing Specifications ............................................................................................................................123 6.7 JTAG Boundary Scan Timing Specifications.................................................................................................126 6.8 Marvell(R) Quick Capture Technology AC Timing...........................................................................................127 6.9 MultiMediaCard Timing Specifications ..........................................................................................................129 6.10 Secure Digital (SD/SDIO) Timing ..................................................................................................................129 Doc. No. MV-S104690-00 Rev. D Page 4 Copyright (c) 4/3/09 Marvell April 2009 Released Figure 1: Marvell(R) PXA270 Processor Block Diagram, Typical System .........................................................14 Figure 2: Marvell(R) PXA270M Processor Part Numbers ..................................................................................15 Figure 3: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, top view...............................................16 Figure 4: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, bottom view.........................................17 Figure 5: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, side view .............................................18 Figure 6: Marvell(R) PXA270M 13mm x 13mm Package Mark Diagram ...........................................................19 Figure 7: Marvell(R) PXA270M 23mm x 23mm Package Mark Diagram ...........................................................20 Figure 8: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Top View) ..............................................21 Figure 9: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Bottom View).........................................22 Figure 10: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Side View) .............................................22 Figure 11: Package Compliance Criteria ...........................................................................................................23 Figure 12: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, bottom view.........................................24 Figure 13: Marvell(R) PXA270 Processor Production Markings, (Laser Mark on Top Side)................................25 Figure 14: 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) ............................................................28 Figure 15: 13x13 mm VF-BGA Ball Map, Top View (upper right quarter)..........................................................29 Figure 16: 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) ..........................................................30 Figure 17: 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) .......................................................31 Figure 18: 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter).............................................................32 Figure 19: 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter) ..........................................................33 Figure 20: 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter).............................................................34 Figure 21: 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter) ..........................................................35 Figure 22: AC Test Load ....................................................................................................................................81 Figure 23: Power On Reset Timing....................................................................................................................83 Figure 24: Hardware Reset Timing ....................................................................................................................84 Figure 25: GPIO Reset Timing...........................................................................................................................85 Figure 26: Sleep Mode Timing ...........................................................................................................................86 Figure 27: Deep-Sleep-Mode Timing .................................................................................................................87 Figure 28: SDRAM Timing .................................................................................................................................95 Figure 29: SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing ............................................................96 Figure 30: SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing................................................97 Figure 31: SDRAM Fly-by DMA Timing .............................................................................................................98 Figure 32: 32-Bit Non-burst ROM, SRAM, or Flash Read Timing....................................................................100 Figure 33: 32-Bit Burst-of-Eight ROM or Flash Read Timing...........................................................................101 Figure 34: Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing ........................................102 Figure 35: 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing...................................................................103 Figure 36: Synchronous Flash Burst-of-Eight Read Timing.............................................................................106 Figure 37: Synchronous Flash Stacked Burst-of-Eight Read Timing...............................................................107 Figure 38: First-Access Latency Configuration Timing ....................................................................................108 Figure 39: Synchronous Flash Burst Read Example .......................................................................................110 Figure 40: 32-Bit Flash Write Timing ...............................................................................................................111 Figure 41: 32-Bit Stacked Flash Write Timing .................................................................................................112 Figure 42: 16-Bit Flash Write Timing ...............................................................................................................113 Figure 43: 32-Bit SRAM Write Timing ..............................................................................................................115 Figure 44: 16-bit SRAM Write for 4/2/1 Byte(s) Timing....................................................................................116 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 5 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 45: 32-Bit VLIO Read Timing................................................................................................................118 Figure 46: 32-Bit VLIO Write Timing ................................................................................................................119 Figure 47: Expansion-Card Memory or I/O 16-Bit Access Timing ...................................................................121 Figure 48: Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ...........................................122 Figure 49: LCD Timing Definitions ...................................................................................................................122 Figure 50: SSP Master Mode Timing Definitions .............................................................................................124 Figure 51: Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral .......................125 Figure 52: Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral ............................125 Figure 53: JTAG Boundary-Scan Timing .........................................................................................................127 Figure 54: Marvell(R) Quick Capture Interface Timing.......................................................................................128 Figure 55: MultiMedia Card timing Diagrams...................................................................................................129 Figure 56: SD/SDIO timing diagrams...............................................................................................................130 Doc. No. MV-S104690-00 Rev. D Page 6 Copyright (c) 4/3/09 Marvell April 2009 Released Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 7 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 1: Supplemental Documentation...........................................................................................................12 Table 2: Processor Material Properties ..........................................................................................................25 Table 3: Pin Use Summary .............................................................................................................................36 Table 4: Pin Use and Mapping Notes .............................................................................................................58 Table 5: Signal Types .....................................................................................................................................59 Table 6: Memory Controller Pin Reset Values................................................................................................59 Table 7: Discrete (13x13 VF-BGA) Power Supply Pin Summary ...................................................................60 Table 8: Absolute Maximum Ratings ..............................................................................................................63 Table 9: Voltage, Temperature, and Frequency Electrical Specifications ......................................................64 Table 10: Memory Voltage and Frequency Electrical Specifications ................................................................66 Table 11: Core Voltage and Frequency Electrical Specifications .....................................................................67 Table 12: Internally Generated Power Domain Descriptions ............................................................................68 Table 13: Core Voltage Specifications For Lower Power Modes......................................................................68 Table 14: Typical Power-Consumption Specifications......................................................................................69 Table 15: Maximum Idle and Low Power Mode Power-Consumption Specifications .......................................72 Table 16: Standard Input, Output, and I/O Pin DC Operating Conditions ........................................................74 Table 17: Typical 32.768-kHz Crystal Requirements........................................................................................75 Table 18: Typical External 32.768-kHz Oscillator Requirements.....................................................................77 Table 19: Typical 13.000-MHz Crystal Requirements ......................................................................................77 Table 20: Typical External 13.000-MHz Oscillator Requirements ....................................................................78 Table 21: CLK_PIO Specifications ...................................................................................................................78 Table 22: CLK_TOUT Specifications ................................................................................................................79 Table 23: 48 MHz Output Specifications ..........................................................................................................79 Table 24: Standard Input, Output, and I/O-Pin AC Operating Conditions ........................................................81 Table 25: Power-On Timing Specifications(OSCC[CRI] = 0)............................................................................83 Table 26: Hardware Reset Timing Specifications (OSCC[CRI] = 0).................................................................84 Table 27: Hardware Reset Timing Specifications (OSCC[CRI] = 1)................................................................84 Table 28: GPIO Reset Timing Specifications ..................................................................................................85 Table 29: Sleep-Mode Timing Specifications ...................................................................................................87 Table 30: Deep-Sleep Mode Timing Specifications ..........................................................................................87 Table 31: GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode ................................................................89 Table 32: Standby-Mode Timing Specifications ...............................................................................................90 Table 33: Idle-Mode Timing Specifications.......................................................................................................90 Table 34: Frequency-Change Timing Specifications ........................................................................................90 Table 35: Voltage-Change Timing Specification for a 1-Byte Command..........................................................91 Table 36: GPIO Timing Specifications ..............................................................................................................91 Table 37: SRAM Read/Write AC Specification .................................................................................................92 Table 38: SDRAM Interface AC Specifications.................................................................................................92 Table 39: ROM AC Specification ......................................................................................................................99 Table 40: Synchronous Flash Read AC Specifications ..................................................................................104 Table 41: Flash Memory AC Specification......................................................................................................110 Table 42: SRAM Write AC Specification.........................................................................................................114 Table 43: VLIO Timing ....................................................................................................................................117 Table 44: Expansion-Card Interface AC Specifications ..................................................................................120 Doc. No. MV-S104690-00 Rev. D Page 8 Copyright (c) 4/3/09 Marvell April 2009 Released Table 45: LCD Timing Specifications..............................................................................................................123 Table 46: SSP Master Mode Timing Specifications........................................................................................124 Table 47: Timing Specification SSP Slave Mode Transmitting Data to External Peripheral...........................125 Table 48: Timing Specification for SSP Slave Mode Receiving Data from External Peripheral .....................126 Table 49: Boundary Scan Timing Specifications ............................................................................................126 Table 50: Marvell(R) Quick Capture AC Timing Specification ..........................................................................127 Table 51: MultiMedia Card timing specifications ............................................................................................129 Table 52: SD/SDIO Timing Specifications ......................................................................................................130 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 9 PXA270 Processor Electrical, Mechanical, and Thermal Specification Doc. No. MV-S104690-00 Rev. D Page 10 Copyright (c) 4/3/09 Marvell April 2009 Released 1 Introduction The Marvell(R) PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Marvell advances in mobile technology over its predecessor, the Marvell(R) PXA255 processor. These same attributes and features also make the PXA270 processor ideal for embedded applications. The PXA270 processor redefines scalability by operating from 104 MHz up to 624 MHz, providing enough performance for the most demanding mobile applications. The PXA270 processor is the first Marvell processor to include Intel(R) Wireless MMXTM technology, enabling high-performance, low-power multimedia acceleration with a general-purpose instruction set. The Marvell(R) Quick Capture Interface provides a flexible and powerful camera interface for capturing digital images and video. While performance is key in the PXA270 processor, power consumption is also a critical component. The new capabilities of Wireless Intel SpeedStep(R) technology set the standard for low-power consumption. The PXA270 processor is offered in two packages: 13x13 mm VFBGA and 23x23 mm PBGA. 1.1 About This Document This document constitutes the electrical, mechanical, and thermal specifications for the PXA270 processor. It contains a functional overview, mechanical data, package signal locations, targeted electrical specifications, and functional bus waveforms. For detailed functional descriptions other than parametric performance, refer to the Marvell(R) PXA27x Processor Family Developers Manual. 1.1.1 Number Representation All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in hexadecimal and 0b110_1011 in binary. 1.1.2 Typographical Conventions All signal and register-bit names appear in uppercase. Active low items are prefixed with a lowercase "n". Bits within a signal name are enclosed in angle brackets: EXTERNAL_ADDRESS<31:0> nCS<1> Bits within a register bit field are enclosed in square brackets: REGISTER_BITFIELD[3:0] REGISTER_BIT[0] Single-bit items have either of two states: 1.1.3 clear -- the item contains the value 0b0. To clear a bit, write 0b0 to it. set -- the item contains the value 0b1. To set a bit, write 0b1 to it. Applicable Documents Table 1 lists supplemental information sources for the PXA270 processor. Contact a Marvell representative for the latest document revisions and ordering instructions. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev.D Page 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 1: Supplemental Documentation D o c u m e n t Tit l e Marvell(R) PXA27x Processor Family Developers Manual ARM(R) Architecture Version 5T Specification (Document number ARM* DDI 0100D-10), and ARM(R) Architecture Reference Manual (Document number ARM* DDI 0100B) Intel XScale(R) Core Developer's Manual Intel(R) Wireless MMXTM Technology Developer's Guide Marvell(R) PXA27x Processor Design Guide Marvell(R) PXA27x Processor Power Supply Requirements Application Note Doc. No. MV-S104690-00 Rev.D Page 12 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 2 Functional Overview The Marvell(R) PXA270 processor is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices as well as embedded platforms. It incorporates the Intel XScale(R) technology which complies with the ARM* version 5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer's model. The PXA270 processor also provides Intel(R) Wireless MMXTM media enhancement technology, which supports integer instructions to accelerate audio and video processing. In addition, it incorporates Wireless Intel Speedstep(R) Technology, which provides sophisticated power management capabilities enabling excellent MIPs/mW performance. The PXA270 processor provides a scalable, bi-directional data interface to a cellular baseband processor, supporting seven logical channels and other features. The operating-system (OS) timer channels and synchronous serial ports (SSPs) also accept an external network clock input so that they can be synchronized to the cellular network. The processor also provides a Universal Subscriber Identity Module* (USIM) card interface. The PXA270 processor memory interface gives designers flexibility as it supports a variety of external memory types. The processor also provides four 64 kilobyte banks of on-chip SRAM, which can be used for program code or multimedia data. Each bank can be configured independently to retain its contents when the processor enters a low-power mode. An integrated LCD panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. A 256-byte palette RAM provides flexible color mapping. A set of serial devices and general-system resources offers computational and connectivity capability for a variety of applications. Figure 1 shows the block diagram for a typical PXA270 processor system. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 1: Marvell(R) PXA270 Processor Block Diagram, Typical System LCD LCD RTC RTC 44xxPWM PWM Memory Memory Controller Controller Interrupt Interrupt Controller C ontrolle r InternalInternal LCDLCD Camera Controller SRAM SRAM Interface Controller 33xxSSP SSP USIM U SIM Full FullFunction Func tion UART UA RT Bluetooth Bluet oot h* UART UAR T IrDA IrD A I2I2CC USB U SB Client Client BB B BProcessor Pr ocess or Interface Inter face Keypad Ke ypad Interface Interfa ce SDCard/MMC S DC ard/M MC Interface Inter face Memory MemoryStick Stick Interface Int er face USB USB OTG OTG Camera Interface DMA DMA Controller Controller And and Bridge Bridge Variable Variable Latency Latency I/O I/O Control Control System System Bus Bus Marvell(R) Wireless MMXTM Intel(R) Wireless MMXTM GeneralPur Purpose I/O General pose I/O AC97 AC 97 Peripheral Bus Per iphera l Bus 2 I2IS S Address Address and and Data Data Intel(R) Intel(R) XScaleTM (R) XScaleTM USB USB Host Host Debug Debug Controller Controller 13 13 MHz MHz Osc Osc Power PowerManagement Management Clock ClockControl Control ASIC ASIC Socket Socket00 PCMCIA PCMCIA &&CF CF Control Control MicroMicroarchitecture architecture Addressand andData DataBBus Address us OS OSTimers Tim ers 32.768 32.768 kHz kHz Osc Osc Dynamic Dynamic Memory Memor y Control Control Static Static Memory Memory Control Control XCVR XCVR Socket Socket11 SDRAM/ SDRAM Boot ROM ROM/ ROM/ Flash/ Flash/ SRAM SRAM Primary Primar yGPIO GPIO JTAG JTAG Note Note Memory Stick is not available on PXA270M (AP270M) SKUs. Doc. No. MV-S104690-00 Rev. D Page 14 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 3 Package Information This chapter provides the mechanical specifications for the PXA270 processor. The PXA270 processor is offered in two packages. Part numbers are shown in Figure 2. The 13- by 13-mm, 356-ball, 0.50-mm VF-BGA molded matrix array package is shown in Figure 3, Figure 4, Figure 5, and Figure 6. The 23- by 23-mm, 360-ball, 1.0-mm PBGA molded matrix array package is shown in Figure 7, Figure 8, Figure 9, and Figure 10. Figure 2: Marvell(R) PXA270M Processor Part Numbers Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 3.1 Package Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 3: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, top view A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A B C D E F G H J K L M N P R T U V W Note Note Doc. No. MV-S104690-00 Rev. D Page 16 Figure 4 and Figure 5 show all dimensions in millimeters (mm). Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 4: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, bottom view 0.15 M C 0.15 M C A B 0.50 11.50 130.10 o0.300.05 (356) 0.50 A 11.50 B Copyright (c) 4/3/09 Marvell April 2009 Released 130.10 Doc. No. MV-S104690-00 Rev. D Page 17 PXA270 Processor Electrical, Mechanical, and Thermal Specification Doc. No. MV-S104690-00 Rev. D Page 18 0.91 MIN. - 1.0 MAX. 0.12 C 0.10 C SEATING PLANE C 0.18 MIN. - 0.30 MAX. 0.210.04 0.450.05 Figure 5: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, side view Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 6: Marvell(R) PXA270M 13mm x 13mm Package Mark Diagram Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 19 PXA270 Processor Electrical, Mechanical, and Thermal Specification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 7: Marvell(R) PXA270M 23mm x 23mm Package Mark Diagram Doc. No. MV-S104690-00 Rev. D Page 20 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Note Note Figure 8, Figure 9 and Figure 10 show all dimensions in millimeters (mm). Figure 8: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Top View) A1 CORNER 14.70 0.25 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 21 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 9: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Bottom View) PIN #1 CORNER 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB 1.00 1.00 Ball Diameter = 0.60 +/-0.10 mm 1.00 1.00 Figure 10: 23x23 mm PBGA Marvell(R) PXA270 Processor Package (Side View) // 0.15 C 0.20 C 3 SEATING PLANE Doc. No. MV-S104690-00 Rev. D Page 22 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 11: Package Compliance Criteria Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 23 PXA270 Processor Electrical, Mechanical, and Thermal Specification 3.2 Processor Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 12: 13x13mm VF-BGA Marvell(R) PXA270 Processor Package, bottom view Table 2 describes the basic material properties of the processor components. Doc. No. MV-S104690-00 Rev. D Page 24 Copyright (c) 4/3/09 Marvell April 2009 Released Table 2: Processor Material Properties 3.3 3.4 Component V F -B G A M a t e ri a l P B G A M a te ri a l Mold compound ShinEtsu KMC 2500 VAT1 Sumitomo G770LE Solder balls(Leaded) 63% Sn/37% Pb 63% Sn/37% Pb Solder balls(Pb-free) 94.5% Sn / 5.0% Ag / 0.5% Cu 94.5% Sn / 5.0% Ag / 0.5% Cu Junction To Case Temperature Thermal Resistance P a ra m e t e r V F - B G A Va l u e a n d U n i ts P B G A Va l u e a n d U n i ts Theta Jc 2 degrees C / watt 1.4 degrees C / watt Processor Markings The diagram in this section details the processor's top markings, which identify the PXA270 processor in the 356-ball VF-BGA and 360-ball PBGA package. A Pb-Free (lead-free) package is indicated by the letter "E" on the 3rd line of information (Marvell legal line). The "E" appears after the date stamp. Figure 13: Marvell(R) PXA270 Processor Production Markings, (Laser Mark on Top Side) Bulverde Production Mark Diagram Laser Mark on top side of Package i Product PXA270C0C416 FPO# Lot # M C `03 Intel Legal TAIWAN COO PIN 1 INDICATOR 3.5 Tray Drawing For tray drawing information, refer to the Intel Developer website for the Intel(R) Wireless Communications and Computing Package Users Guide. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Doc. No. MV-S104690-00 Rev. D Page 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Copyright (c) 4/3/09 Marvell April 2009 Released 4 Pin Listing and Signal Definitions This chapter describes the signals and pins for the Marvell(R) PXA270 processor. For descriptions of all PXA270 processor signals, refer to the "System Architecture" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual. Table 4 lists the mapping of signals to specific package pins. Many of the package pins are multiplexed so that they can be configured for use as a general-purpose I/O signal or as one of two or three alternate functions using the GPIO alternate-function select registers. Some signals can be configured to appear on one of several different package pins. 4.1 Ball Map View Note Note 4.1.1 In the following ball map figures the lowercase letter "n", which normally indicates negation, appears as uppercase "N". 13x13 mm VF-BGA Ball map Figure 14 through Figure 17 shows the ball map for the VF-BGA PXA270 processor. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 14: 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) 1 2 4 5 6 VCC_MEM VCC_SRAM MA<1> A VSS_CORE VSS_CORE GPIO<15> B VSS_CORE VSS_CORE NCS<0> VCC_SRAM VSS_CORE 7 8 9 VCC_CORE VCC_SRAM VCC_SRAM 10 11 12 GPIO<49> GPIO<47> VCC_IO GPIO<33> GPIO<78> VCC_MEM GPIO<18> GPIO<12> GPIO<46> VCC_CORE GPIO<80> GPIO<79> RDNWR GPIO<13> GPIO<11> GPIO<31> VSS_MEM VSS_CORE VSS_IO VSS_CORE C MA<18> MA<22> VCC_MEM MA<24> VSS_MEM MA<0> D MA<17> MA<21> VCC_CORE MA<23> VSS_MEM MA<25> E MA<13> VCC_MEM MA<19> MA<20> F VCC_MEM MA<14> MA<16> VSS_MEM G MA<8> MA<11> MA<12> MA<15> H VCC_MEM MA<9> MA<10> VSS_MEM J MA<3> MA<6> MA<7> VSS_MEM K MD<15> MA<4> MA<5> MA<2> VSS_CORE VSS_CORE VSS_CORE L MD<14> MD<31> VCC_MEM VSS_MEM VSS_CORE VSS_CORE VSS_CORE M VCC_MEM MD<30> MD<29> MD<13> VSS_CORE VSS_CORE VSS_CORE Doc. No. MV-S104690-00 Rev. D Page 28 3 VSS_CORE VSS_CORE Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 15: 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) 13 14 15 16 17 18 19 20 21 22 23 24 GPIO<113> GPIO<28> GPIO<37> VCC_IO GPIO<24> GPIO<16> GPIO<92> GPIO<32> GPIO<34> GPIO<118> VCC_USB VCC_USB A GPIO<29> GPIO<38> GPIO<26> GPIO<23> GPIO<110> GPIO<112> GPIO<35> GPIO<44> VCC_CORE USBC_P VCC_USB VCC_USB B GPIO<30> GPIO<36> GPIO<27> GPIO<17> GPIO<111> GPIO<41> GPIO<45> USBC_N GPIO<42> GPIO<43> GPIO<88> GPIO<116> C GPIO<22> GPIO<40> VSS_IO GPIO<25> GPIO<109> VSS_IO GPIO<39> USBH_N<1> GPIO<114> D GPIO<117> VSS_CORE GPIO<89> GPIO<115> USBH_P<1> UIO VCC_USIM E VSS_IO GPIO<90> GPIO<91> VCC_CORE F VSS_CORE GPIO<59> GPIO<60> GPIO<58> G VSS_IO GPIO<62> GPIO<63> GPIO<61> H VSS_CORE GPIO<64> VCC_CORE VCC_LCD J VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<66> GPIO<67> GPIO<65> K VSS_CORE VSS_CORE VSS_CORE GPIO<68> GPIO<71> GPIO<69> VCC_CORE L VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<73> VCC_CORE GPIO<70> M Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Doc. No. MV-S104690-00 Rev. D Page 29 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 16: 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) N MD<27> MD<28> MD<12> VSS_MEM VSS_CORE VSS_CORE VSS_CORE P VCC_MEM MD<11> MD<26> MD<10> VSS_CORE VSS_CORE VSS_CORE R MD<24> VSS_MEM MD<25> MD<9> VSS_CORE VSS_CORE VSS_CORE T MD<23> VCC_CORE MD<8> VSS_MEM U MD<7> VCC_MEM VSS_CORE MD<5> V MD<21> MD<22> MD<6> VSS_MEM W MD<20> VCC_MEM Y MD<19> MD<4> MD<3> VSS_MEM AA MD<18> VCC_MEM MD<2> MD<16> VSS_MEM NSDCAS VSS_CORE VSS_MEM VSS_MEM GPIO<55> GPIO<84> VSS_CORE AB MD<1> VSS_MEM MD<17> MD<0> NWE GPIO<20> NSDCS<0> NSDCS<1> DQM<0> DQM<1> GPIO<56> GPIO<81> AC VCC_MEM VCC_MEM VSS_MEM SDCLK<0> NOE VCC_MEM NSDRAS VCC_MEM DQM<2> DQM<3> GPIO<57> GPIO<85> AD VCC_MEM VCC_MEM SDCLK<2> VCC_CORE GPIO<21> SDCKE SDCLK<1> VCC_MEM GPIO<82> GPIO<83> VCC_CORE VCC_BB 1 2 5 6 7 8 9 10 11 12 Doc. No. MV-S104690-00 Rev. D Page 30 VCC_CORE VSS_CORE 3 4 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 17: 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO<86> GPIO<87> GPIO<72> N VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<76> GPIO<75> VCC_LCD P VSS_CORE VSS_CORE VSS_CORE GPIO<77> GPIO<19> GPIO<74> VCC_CORE R TMS TCK TESTCLK GPIO<14> T NTRST GPIO<9> TDI VSS_IO U VSS GPIO<0> GPIO<10> TDO V GPIO<3> NVDD_FAUL T GPIO<4> CLK_REQ W NRESET_O UT NRESET PWR_EN GPIO<1> Y VSS TXTAL_IN TXTAL_OUT SYS_EN AA PWR_CAP< PWR_OUT 0> BOOT_SEL NBATT_FAU LT AB VSS_BB GPIO<54> VSS_CORE GPIO<97> GPIO<95> VSS_IO PWR_CAP< 3> GPIO<50> GPIO<53> GPIO<106> GPIO<105> GPIO<102> GPIO<99> GPIO<93> VCC_BATT GPIO<48> GPIO<52> GPIO<107> GPIO<103> GPIO<101> GPIO<100> GPIO<96> VCC_PLL PXTAL_IN PWR_CAP< 2> VSS VSS AC GPIO<51> GPIO<108> GPIO<104> VCC_CORE AD 13 14 Copyright (c) 4/3/09 Marvell April 2009 Released 15 VSS_IO 16 VCC_IO GPIO<98> GPIO<94> VSS_PLL PXTAL_OUT PWR_CAP< 1> VSS VSS 17 18 19 20 21 22 23 24 Doc. No. MV-S104690-00 Rev. D Page 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 4.1.2 23x23 mm PBGA Ball map Figure 18: 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) 1 2 3 4 5 6 7 8 9 10 11 A VSS_MEM VSS_MEM MA[25] GPIO[15] GPIO[79] GPIO[13] GPIO[12] GPIO[11] GPIO[46] GPIO[113] GPIO[29] B VSS_MEM VCC_MEM VSS_MEM VCC_RAM MA[1] VSS_MEM VCC_RAM VCC_RAM VSS_MEM VCC_IO GPIO[30] C MA[16] MA[17] VCC_MEM MA[24] VCC_RAM VCC_MEM GPIO[33] RDNWR VCC_MEM GPIO[47] GPIO[31] D MA[14] MA[15] MA[19] MA[22] MA[0] NCS_0 GPIO[80] GPIO[78] GPIO[18] GPIO[49] VCC_CORE E MA[11] MA[12] MA[21] MA[23] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE F MA[9] VSS_MEM VCC_MEM MA[20] VCC_CORE G MA[7] MA[8] MA[13] MA[18] VSS_CORE H MA[4] VSS_MEM VCC_MEM MA[10] VCC_CORE J MA[3] MA[2] MA[6] MA[5] VSS_CORE K MD[15] MD[30] VCC_MEM MD[31] VSS_CORE VSS_CORE VSS_CORE L MD[14] VSS_MEM MD[29] VCC_CORE VSS_CORE VSS_CORE VSS_CORE Doc. No. MV-S104690-00 Rev. D Page 32 VSS_CORE VSS_CORE VSS_CORE Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 19: 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter) 12 13 14 15 16 17 18 19 20 21 22 GPIO[22] GPIO[38] GPIO[26] GPIO[25] GPIO[23] GPIO[111] GPIO[92] GPIO[41] GPIO[44] VCC_USB VCC_USB A VSS_IO GPIO[36] GPIO[24] VSS_IO GPIO[112] GPIO[39] VSS_IO GPIO[34] GPIO[118] GPIO[43] VCC_USB B GPIO[40] GPIO[27] GPIO[16] GPIO[110] GPIO[32] GPIO[45] GPIO[117] NC NC GPIO[89] GPIO[88] C GPIO[28] GPIO[37] VCC_IO GPIO[17] GPIO[109] GPIO[35] USBC_P VCC_USB GPIO[42] VSS_IO USBH_N[1] D USBC_N GPIO[116] GPIO[115] USBH_P[1] E VCC_CORE GPIO[114] UIO VCC_USIM GPIO[61] F VSS_CORE GPIO[91] GPIO[58] GPIO[60] GPIO[62] G VCC_CORE GPIO[90] GPIO[59] VSS_IO GPIO[64] H VSS_CORE GPIO[66] GPIO[63] VCC_LCD GPIO[69] J VSS_CORE VSS_CORE VSS_CORE GPIO[67] GPIO[65] GPIO[68] GPIO[70] K VSS_CORE VSS_CORE VSS_CORE VCC_CORE GPIO[71] GPIO[72] GPIO[73] L VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE VSS_CORE VSS_CORE VSS_CORE Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 20: 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) M MD[13] MD[11] VCC_MEM MD[12] VSS_CORE VSS_CORE VSS_CORE N MD[28] MD[26] MD[24] MD[25] VSS_CORE VSS_CORE VSS_CORE P MD[27] VSS_MEM VCC_MEM MD[8] VSS_CORE R MD[10] MD[23] MD[21] MD[7] VCC_CORE T MD[9] VSS_MEM VCC_MEM MD[5] VSS_CORE U MD[22] MD[6] MD[4] MD[2] VCC_CORE V MD[20] VSS_MEM VCC_MEM MD[16] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE W MD[19] MD[18] MD[1] MD[0] GPIO[20] NSDRAS SDCKE DQM[0] GPIO[55] GPIO[81] VCC_CORE Y MD[3] MD[17] VCC_MEM NSDCAS VCC_MEM GPIO[21] VCC_MEM NSDCS[1] VCC_MEM GPIO[84] GPIO[48] AA VSS_MEM VCC_MEM NWE NOE NSDCS[0] VSS_MEM DQM[1] GPIO[82] VSS_MEM GPIO[85] VCC_BB AB VSS_MEM VSS_MEM SDCLK[0] SDCLK[2] SDCLK[1] DQM[2] DQM[3] GPIO[56] GPIO[57] GPIO[83] VSS_BB 1 2 3 4 5 6 7 8 9 10 11 Doc. No. MV-S104690-00 Rev. D Page 34 VSS_CORE VSS_CORE VSS_CORE Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 21: 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter) VSS_CORE VSS_CORE VSS_CORE VCC_LCD GPIO[86] VSS_IO GPIO[87] M VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO[75] GPIO[76] GPIO[74] N VSS_CORE GPIO[19] GPIO[14] GPIO[77] TESTCLK P VCC_CORE TCK TMS TDO TDI R VSS_CORE GPIO[4] NTRST CLK_REQ GPIO[9] T VCC_CORE NBATT_FAU LT GPIO[0] GPIO[1] GPIO[10] U NVDD_FAUL T SYS_EN GPIO[3] V VSS_CORE VSS_CORE VSS_CORE VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL 4.2 GPIO[50] GPIO[106] GPIO[104] VCC_IO GPIO[96] PWR_CAP [3] VSS PWR_OUT NRESET NRESET_O UT PWR_EN W GPIO[52] GPIO[105] GPIO[102] GPIO[97] GPIO[93] VCC_BATT PWR_CAP [2] PWR_CAP [0] VSS TXTAL_IN TXTAL_OUT Y GPIO[53] GPIO[108] VSS_IO GPIO[100] GPIO[98] GPIO[94] VSS_IO VSS_PLL PXTAL_OUT PWR_CAP [1] VSS AA GPIO[51] GPIO[54] GPIO[107] GPIO[103] GPIO[101] GPIO[99] GPIO[95] VCC_PLL PXTAL_IN VSS VSS AB 12 13 14 15 16 17 18 19 20 21 22 Pin Use The pin-use summary shown in Table 3 does not include the 36 center balls identified as K10 through R15 (VF-BGA) or J9 through P14 (PBGA), all of which function as VSS_CORE (see the recommendations for connecting the 36 center balls in the Marvell(R) PXA27x Processor Family Design Guide). Each signal's alternate function inputs are shown in the upper section of each signal row and the outputs are shown in the lower section of each signal row. For example, GPIO<48> has a primary input function of CIF_DD<5> and a secondary output function of nPOE. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i r d A l t e r n a te Function S e c o n d a ry A lt e rn a t e Function P r im a r y F u n c t i o n F u n c t i o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 1 of 22) PBGA Ball# (23x23) VF-BGA Ball# (13x13) Table 3: VCC_MEM D6 A3 MA<25> OCZ MA<25> MA<25> -- -- Refer to Table 6 C4 C4 MA<24> OCZ MA<24> MA<24> -- -- Refer to Table 6 D4 E4 MA<23> OCZ MA<23> MA<23> -- -- Refer to Table 6 C2 D4 MA<22> OCZ MA<22> MA<22> -- -- Refer to Table 6 D2 E3 MA<21> OCZ MA<21> MA<21> -- -- Refer to Table 6 E4 F4 MA<20> OCZ MA<20> MA<20> -- -- Refer to Table 6 E3 D3 MA<19> OCZ MA<19> MA<19> -- -- Refer to Table 6 C1 G4 MA<18> OCZ MA<18> MA<18> -- -- Refer to Table 6 D1 C2 MA<17> OCZ MA<17> MA<17> -- -- Refer to Table 6 F3 C1 MA<16> OCZ MA<16> MA<16> -- -- Refer to Table 6 G4 D2 MA<15> OCZ MA<15> MA<15> -- -- Refer to Table 6 F2 D1 MA<14> OCZ MA<14> MA<14> -- -- Refer to Table 6 E1 G3 MA<13> OCZ MA<13> MA<13> -- -- Refer to Table 6 G3 E2 MA<12> OCZ MA<12> MA<12> -- -- Refer to Table 6 G2 E1 MA<11> OCZ MA<11> MA<11> -- -- Refer to Table 6 H3 H4 MA<10> OCZ MA<10> MA<10> -- -- Refer to Table 6 H2 F1 MA<9> OCZ MA<9> MA<9> -- -- Refer to Table 6 G1 G2 MA<8> OCZ MA<8> MA<8> -- -- Refer to Table 6 J3 G1 MA<7> OCZ MA<7> MA<7> -- -- Refer to Table 6 J2 J3 MA<6> OCZ MA<6> MA<6> -- -- Refer to Table 6 K3 J4 MA<5> OCZ MA<5> MA<5> -- -- Refer to Table 6 K2 H1 MA<4> OCZ MA<4> MA<4> -- -- Refer to Table 6 J1 J1 MA<3> OCZ MA<3> MA<3> -- -- Refer to Table 6 K4 J2 MA<2> OCZ MA<2> MA<2> -- -- Refer to Table 6 A6 B5 MA<1> OCZ MA<1> MA<1> -- -- Refer to Table 6 C6 D5 MA<0> OCZ MA<0> MA<0> -- -- Refer to Table 6 NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 36 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 2 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: L2 K4 MD<31> ICO CZ MD<31> MD<31> -- -- Refer to Table 6 M2 K2 MD<30> ICO CZ MD<30> MD<30> -- -- Refer to Table 6 M3 L3 MD<29> ICO CZ MD<29> MD<29> -- -- Refer to Table 6 N2 N1 MD<28> ICO CZ MD<28> MD<28> -- -- Refer to Table 6 N1 P1 MD<27> ICO CZ MD<27> MD<27> -- -- Refer to Table 6 P3 N2 MD<26> ICO CZ MD<26> MD<26> -- -- Refer to Table 6 R3 N4 MD<25> ICO CZ MD<25> MD<25> -- -- Refer to Table 6 R1 N3 MD<24> ICO CZ MD<24> MD<24> -- -- Refer to Table 6 T1 R2 MD<23> ICO CZ MD<23> MD<23> -- -- Refer to Table 6 V2 U1 MD<22> ICO CZ MD<22> MD<22> -- -- Refer to Table 6 V1 R3 MD<21> ICO CZ MD<21> MD<21> -- -- Refer to Table 6 W1 V1 MD<20> ICO CZ MD<20> MD<20> -- -- Refer to Table 6 Y1 W1 MD<19> ICO CZ MD<19> MD<19> -- -- Refer to Table 6 AA1 W2 MD<18> ICO CZ MD<18> MD<18> -- -- Refer to Table 6 AB3 Y2 MD<17> ICO CZ MD<17> MD<17> -- -- Refer to Table 6 AA4 V4 MD<16> ICO CZ MD<16> MD<16> -- -- Refer to Table 6 K1 K1 MD<15> ICO CZ MD<15> MD<15> -- -- Refer to Table 6 NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n Ty p e Name F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 3 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: L1 L1 MD<14> ICO CZ MD<14> MD<14> -- -- Refer to Table 6 M4 M1 MD<13> ICO CZ MD<13> MD<13> -- -- Refer to Table 6 N3 M4 MD<12> ICO CZ MD<12> MD<12> -- -- Refer to Table 6 P2 M2 MD<11> ICO CZ MD<11> MD<11> -- -- Refer to Table 6 P4 R1 MD<10> ICO CZ MD<10> MD<10> -- -- Refer to Table 6 R4 T1 MD<9> ICO CZ MD<9> MD<9> -- -- Refer to Table 6 T3 P4 MD<8> ICO CZ MD<8> MD<8> -- -- Refer to Table 6 U1 R4 MD<7> ICO CZ MD<7> MD<7> -- -- Refer to Table 6 V3 U2 MD<6> ICO CZ MD<6> MD<6> -- -- Refer to Table 6 U4 T4 MD<5> ICO CZ MD<5> MD<5> -- -- Refer to Table 6 Y2 U3 MD<4> ICO CZ MD<4> MD<4> -- -- Refer to Table 6 Y3 Y1 MD<3> ICO CZ MD<3> MD<3> -- -- Refer to Table 6 AA3 U4 MD<2> ICO CZ MD<2> MD<2> -- -- Refer to Table 6 AB1 W3 MD<1> ICO CZ MD<1> MD<1> -- -- Refer to Table 6 AB4 W4 MD<0> ICO CZ MD<0> MD<0> -- -- Refer to Table 6 AC5 AA4 NOE OCZ nOE nOE -- -- Refer to Table 6 AB5 AA3 NWE OCZ nWE nWE -- -- Refer to Table 6 AC7 W6 NSDRAS OCZ nSDRAS nSDRAS -- -- Refer to Table 6 NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 38 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n Ty p e P r i m a r y F u n c ti o n Name F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 4 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: AA6 Y4 NSDCAS OCZ nSDCAS nSDCAS -- -- Refer to Table 6 AB9 W8 DQM<0> OCZ DQM<0> DQM<0> -- -- Refer to Table 6 AB10 AA7 DQM<1> OCZ DQM<1> DQM<1> -- -- Refer to Table 6 AC9 AB6 DQM<2> OCZ DQM<2> DQM<2> -- -- Refer to Table 6 AC10 AB7 DQM<3> OCZ DQM<3> DQM<3> -- -- Refer to Table 6 AB7 AA5 NSDCS< 0> OCZ nSDCS<0> nSDCS<0> -- -- Refer to Table 6 AB8 Y8 NSDCS< 1> OC nSDCS<1> nSDCS<1> -- -- Refer to Table 6 AD6 W7 SDCKE OC SDCKE SDCKE -- -- Refer to Table 6 AC4 AB3 SDCLK< 0> OC SDCLK<0> SDCLK<0> -- -- Refer to Table 6 AD7 AB5 SDCLK< 1> OCZ SDCLK<1> SDCLK<1> -- -- Refer to Table 6 AD3 AB4 SDCLK< 2> OC SDCLK<2> SDCLK<2> -- -- Refer to Table 6 C9 C8 RDNWR OCZ RDnWR RDnWR -- -- Refer to Table 6 B3 D6 NCS<0> OCZ nCS<0> nCS<0> -- -- Refer to Table 6 A3 A4 GPIO<15 > ICO CZ GPIO<15> -- -- -- nPCE<1> nCS<1> Refer to Table 6 -- GPIO<18 > ICO CZ GPIO<18> RDY -- -- -- -- -- GPIO<20 > ICO CZ GPIO<20> DREQ<0> MBREQ -- nSDCS<2> Refer to Table 6 -- -- GPIO<21 > ICO CZ GPIO<21> -- -- -- nSDCS<3> Refer to Table 6 DVAL<0> MBGNT B9 AB6 AD5 D9 W5 Y6 Pu-1 Note[1] Note[4] Pd-0 Note[1] Note [3] Pu-1 Note[1] Note[3] Pu-1 Note[1] Note[3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification B6 A10 B7 C8 C7 D10 D8 A5 D7 GPIO<33 > ICO CZ GPIO<33> GPIO<49 > ICO CZ GPIO<49> GPIO<78 > ICO CZ GPIO<78> GPIO<79 > ICO CZ GPIO<79> GPIO<80 > ICO CZ GPIO<80> FFRXD19 FFDSR19 -- DVAL<1> nCS<5> Refer to Table 6 MBGNT -- -- -- -- nPWE Refer to Table 6 -- -- -- -- nPCE<2> nCS<2> Refer to Table 6 -- -- -- -- PSKTSEL nCS<3> Refer to Table 6 PWM_OUT <2> DREQ<1> MBREQ -- -- nCS<4> Refer to Table 6 PWM_OUT <3> CIF_DD<5> -- -- BB_OB_DAT< 1> nPOE Refer to Table 6 -- CIF_DD<3> -- SSPSCLK <2> BB_OB_DAT< 2> nPIOIR Refer to Table 6 SSPSCLK <2> CIF_DD<2> -- -- BB_OB_DAT< 3> nPIOIW Refer to Table 6 -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name C7 Ty p e Pin Use Summary (Sheet 5 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pu-1 Note[1] Note [4] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note[4] Pu-1 Note[1] Note[4] Pu-1 Note[1] Note[4] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [5] VCC_BB AC13 AB13 AD13 Y11 W12 AB12 GPIO<48 > ICO CZ GPIO<48> GPIO<50 > ICO CZ GPIO<50> GPIO<51 > ICO CZ GPIO<51> NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 40 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 AC14 AB14 AA14 AA10 AB11 AC11 AB12 AD9 AD10 AA11 AC12 AA12 AB13 W9 AB8 AB9 W10 AA8 AB10 Y10 AA10 GPIO<52 > ICO CZ GPIO<52> GPIO<53 > ICO CZ GPIO<53> GPIO<54 > ICO CZ GPIO<54> GPIO<55 > ICO CZ GPIO<55> GPIO<56 > GPIO<57 > ICO CZ ICO CZ GPIO<56> GPIO<57> GPIO<81 > ICO CZ GPIO<81> GPIO<82 > ICO CZ GPIO<82> GPIO<83 > ICO CZ GPIO<83> GPIO<84 > ICO CZ GPIO<84> GPIO<85 > ICO CZ GPIO<85> CIF_DD<4> SSPSCLK<3> -- BB_OB_CLK SSPSCLK<3> -- FFRXD USB_P2_3 -- BB_OB_STB CIF_MCLK SSPSYSC LK -- BB_OB_WAIT CIF_PCLK nPCE<2> -- CIF_DD<1> BB_IB_DAT<1 > -- -- nPREG -- nPWAIT BB_IB_DAT<2 > -- USB_P3_4 -- -- nIOIS16 BB_IB_DAT<3 > -- -- -- SSPTXD -- CIF_DD<0> -- SSPTXD3 BB_OB_DAT< 0> -- SSPRXD3 BB_IB_DAT<0 > CIF_DD<5 > -- -- FFDTR SSPSFRM3 BB_IB_CLK CIF_DD<4 > SSPSFRM3 FFTXD FFRTS SSPSCLK3 BB_IB_STB CIF_FV SSPSCLK3 -- CIF_FV FFRXD DREQ<2> CIF_LV nPCE<1> BB_IB_WAIT CIF_LV S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Y12 Ty p e Pin Use Summary (Sheet 6 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [5] Pu-1 Note[1] Note [3] Pu-1 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] VCC_LCD NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification T24 R22 G24 G22 G23 H24 H22 H23 J22 K24 K22 K23 L21 L23 P19 G20 H20 G21 F22 G22 J20 H22 K20 J19 K19 K21 J22 GPIO<14 > ICO CZ GPIO<14> GPIO<19 > ICO CZ GPIO<19> GPIO<58 > ICO CZ GPIO<58> GPIO<59 > ICO CZ GPIO<59> GPIO<60 > ICO CZ GPIO<60> GPIO<61 > ICO CZ GPIO<61> GPIO<62 > ICO CZ GPIO<62> GPIO<63 > ICO CZ GPIO<63> GPIO<64 > ICO CZ GPIO<64> GPIO<65 > ICO CZ GPIO<65> GPIO<66 > ICO CZ GPIO<66> GPIO<67 > ICO CZ GPIO<67> GPIO<68 > ICO CZ GPIO<68> GPIO<69 > ICO CZ GPIO<69> L_VSYNC SSPSFRM2 -- -- SSPSFRM2 UCLK SSPSCLK2 -- FFRXD SSPSCLK2 L_CS nURST -- LDD<0> -- -- LDD<0> -- -- LDD<1> -- -- LDD<1> -- -- LDD<2> -- -- LDD<2> -- -- LDD<3> -- -- LDD<3> -- -- LDD<4> -- -- LDD<4> -- -- LDD<5> -- -- LDD<5> -- -- LDD<6> -- -- LDD<6> -- -- LDD<7> -- -- LDD<7> -- -- LDD<8> -- -- LDD<8> -- -- LDD<9> -- -- LDD<9> -- -- LDD<10> -- -- LDD<10> -- -- LDD<11> -- -- LDD<11> -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name P20 Ty p e Pin Use Summary (Sheet 7 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 42 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 M24 L22 N24 M22 R23 P23 P22 R21 N22 N23 L20 L21 L22 N22 N20 N21 P21 M20 M22 GPIO<70 > ICO CZ GPIO<70> GPIO<71 > ICO CZ GPIO<71> GPIO<72 > ICO CZ GPIO<72> GPIO<73 > ICO CZ GPIO<73> GPIO<74 > ICO CZ GPIO<74> GPIO<75 > ICO CZ GPIO<75> GPIO<76 > ICO CZ GPIO<76> GPIO<77 > ICO CZ GPIO<77> GPIO<86 > ICO CZ GPIO<86> GPIO<87 > ICO CZ GPIO<87> -- LDD<12> -- -- LDD<12> -- -- LDD<13> -- -- LDD<13> -- -- LDD<14> -- -- LDD<14> -- -- LDD<15> -- -- LDD<15> -- -- -- -- -- L_FCLK_RD -- -- -- -- -- L_LCLK _A0 -- -- -- -- -- L_PCLK_WR -- -- -- -- -- L_BIAS -- SSPRXD2 LDD<16> USB_P3_5 nPCE<1> LDD<16> -- nPCE<2> LDD<17> USB_P3_1 SSPTXD2 LDD<17> SSPSFRM 2 EXT_SYNC<0 > SSPRXD2 USB_P3_1 CHOUT<0> PWM_OUT2 48_MHz EXT_SYNC<1 > CIF_DD<7> -- CHOUT<1> PWM_OUT3 48_MHz S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name K22 Ty p e Pin Use Summary (Sheet 8 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3], Note[11 Pd-0 Note[1] Note [3], Note[11 VCC_IO C11 B10 A8 A7 GPIO<11 > GPIO<12 > ICO CZ ICO CZ GPIO<11> GPIO<12> NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification C10 A18 C16 D13 B16 A17 D16 B15 C15 A14 B13 C14 D15 A12 A16 B14 A15 A14 C13 D12 A11 GPIO<13 > ICO CZ GPIO<13> GPIO<16 > ICO CZ GPIO<16> GPIO<17 > ICO CZ GPIO<17> GPIO<22 > ICO CZ GPIO<22> GPIO<23 > ICO CZ GPIO<23> GPIO<24 > ICO CZ GPIO<24> GPIO<25 > ICO CZ GPIO<25> GPIO<26 > ICO CZ GPIO<26> GPIO<27 > ICO CZ GPIO<27> GPIO<28 > ICO CZ GPIO<28> GPIO<29 > ICO CZ GPIO<29> CLK_EXT KP_DKIN<7> KP_MKIN< 7> SSPTXD2 -- -- KP_MKIN<5> -- -- -- PWM_OUT<0 > FFTXD KP_MKIN<6> CIF_DD<6> -- -- PWM_OUT<1 > -- SSPEXTCLK2 SSPSCLKEN2 SSPSCLK2 KP_MKOUT<7 > SSPSYSCLK2 SSPSCLK2 -- SSPSCLK -- CIF_MCLK SSPSCLK -- CIF_FV SSPSFRM -- CIF_FV SSPSFRM -- CIF_LV -- -- CIF_LV SSPTXD -- SSPRXD CIF_PCLK FFCTS -- -- -- SSPEXTCLK SSPSCLKEN CIF_DD<0 > SSPSYSCLK -- FFRTS AC97_BITCLK I2S_BITCLK SSPSFRM I2S_BITCLK -- SSPSFRM AC97_SDATA _IN_0 I2S_SDATA_I N SSPSCLK SSPRXD2 -- SSPSCLK S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name A6 Ty p e Pin Use Summary (Sheet 9 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3], Note[11 ] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 44 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 C13 C12 A20 A21 B19 C14 A15 B14 D19 D14 C18 C11 C16 B19 D17 B13 D13 A13 B17 C12 A19 GPIO<30 > ICO CZ GPIO<30> GPIO<31 > ICO CZ GPIO<31> GPIO<32 > ICO CZ GPIO<32> GPIO<34 > ICO CZ GPIO<34> GPIO<35 > ICO CZ GPIO<35> GPIO<36 > GPIO<37 > ICO CZ ICO CZ GPIO<36> GPIO<37> GPIO<38 > ICO CZ GPIO<38> GPIO<39 > ICO CZ GPIO<39> GPIO<40 > ICO CZ GPIO<40> GPIO<41 > ICO CZ GPIO<41> -- -- -- I2S_SDATA_O UT AC97_SDATA _OUT USB_P3_2 -- -- -- I2S_SYNC AC97_SYNC USB_P3_6 -- -- -- MSSCLK MMCLK -- FFRXD KP_MKIN<3> SSPSCLK3 USB_P2_2 -- SSPSCLK3 FFCTS USB_P2_1 SSPSFRM 3 -- KP_MKOUT< 6> SSPTXD3 FFDCD SSPSCLK2 KP_MKIN< 7> USB_P2_4 SSPSCLK2 -- FFDSR SSPSFRM2 KP_MKIN< 3> USB_P2_8 SSPSFRM2 FFTXD FFRI KP_MKIN<4> USB_P2_3 SSPTXD3 SSPTXD2 PWM_OUT <1> KP_MKIN<4> -- SSPSFRM 3 USB_P2_6 FFTXD SSPSFRM 3 SSPRXD2 -- USB_P2_5 KP_MKOUT<6 > FFDTR SSPSCLK3 FFRXD USB_P2_7 SSPRXD3 KP_MKOUT<7 > FFRTS -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name B11 Ty p e Pin Use Summary (Sheet 10 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification C21 C22 B20 C19 B11 A11 C23 D22 A19 AB19 AD19 B21 A20 C17 A9 C10 C22 C21 A18 Y16 AA17 GPIO<42 > ICO CZ GPIO<42> GPIO<43 > ICO CZ GPIO<43> GPIO<44 > ICO CZ GPIO<44> GPIO<45 > ICO CZ GPIO<45> GPIO<46 > ICO CZ GPIO<46> GPIO<47 > ICO CZ GPIO<47> GPIO<88 > ICO CZ GPIO<88> GPIO<89 > ICO CZ GPIO<89> GPIO<92 > ICO CZ GPIO<92> GPIO<93 > ICO CZ GPIO<93> GPIO<94 > ICO CZ GPIO<94> BTRXD ICP_RXD -- -- -- CIF_MCLK -- -- CIF_FV ICP_TXD BTTXD CIF_FV BTCTS -- CIF_LV -- -- CIF_LV -- -- CIF_PCLK AC97_SYSCL K BTRTS SSPSYSC LK3 ICP_RXD STD_RXD -- -- PWM_OUT<2 > -- CIF_DD<0> -- -- STD_TXD ICP_TXD PWM_OUT <3> USBHPWR<1 > SSPRXD2 SSPSFRM 2 -- -- SSPSFRM 2 SSPRXD3 -- FFRI AC97_SYSCL K USBHPEN<1> SSPTXD2 MMDAT<0> -- -- MMDAT<0> MSBS -- KP_DKIN<0> CIF_DD<6> -- AC97_SDATA _OUT -- -- KP_DKIN<1> CIF_DD<5> -- AC97_SYNC -- -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name D20 Ty p e Pin Use Summary (Sheet 11 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 46 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 AA18 AC19 AA17 AD18 AB18 AC18 AC17 AB17 AC16 AD15 AB16 W16 Y15 AA16 AB17 AA15 AB16 Y14 AB15 W14 Y13 GPIO<95 > ICO CZ GPIO<95> GPIO<96 > ICO CZ GPIO<96> GPIO<97 > ICO CZ GPIO<97> GPIO<98 > GPIO<99 > ICO CZ ICO CZ GPIO<98> GPIO<99> KP_DKIN<2> CIF_DD<4> KP_MKIN< 6> AC97_RESET _n -- -- KP_DKIN<3> MBREQ FFRXD DVAL<1> KP_MKOU T<6> KP_DKIN<4> DREQ<1> KP_MKIN< 3> -- MBGNT -- KP_DKIN<5> CIF_DD<0> KP_MKIN< 4> AC97_SYSCL K -- FFRTS KP_DKIN<6> AC97_SDATA _IN_1 KP_MKIN< 5> -- -- FFTXD GPIO<10 0> ICO CZ GPIO<100 > KP_MKIN<0> DREQ<2> FFCTS -- -- -- GPIO<10 1> ICO CZ GPIO<101 > KP_MKIN<1> -- -- -- -- -- GPIO<10 2> ICO CZ GPIO<102 > KP_MKIN<2> -- FFRXD nPCE<1> -- -- GPIO<10 3> ICO CZ GPIO<103 > CIF_DD<3> -- -- -- KP_MKOUT< 0> -- GPIO<10 4> ICO CZ GPIO<104 > CIF_DD<2> -- -- PSKTSEL KP_MKOUT< 1> -- GPIO<10 5> ICO CZ GPIO<105 > CIF_DD<1> -- -- nPCE<2> KP_MKOUT< 2> -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name AB18 Ty p e Pin Use Summary (Sheet 12 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note [1] Note [3] Pd-0 Note [1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification AB15 AC15 AD14 D17 B17 C17 B18 A13 D24 E21 AB14 AA13 D16 C15 A17 B16 A10 F19 E21 GPIO<10 6> ICO CZ GPIO<106 > CIF_DD<9> -- -- -- KP_MKOUT< 3> -- GPIO<10 7> ICO CZ GPIO<107 > CIF_DD<8> -- -- -- KP_MKOUT< 4> -- GPIO<10 8> ICO CZ GPIO<108 > CIF_DD<7> -- -- CHOUT<0> KP_MKOUT< 5> -- GPIO<10 9> ICO CZ GPIO<109 > MMDAT<1> MSSDIO -- MMDAT<1> MSSDIO -- GPIO<11 0> ICO CZ GPIO<110 > MMDAT<2>/M MCCS<0> -- -- MMDAT<2>/M MCCS<0> -- -- MMDAT<3>/M MCCS<1> -- -- MMDAT<3>/M MCCS<1> -- -- GPIO<11 1> ICO CZ GPIO<111 > GPIO<11 2> ICO CZ GPIO<112 > MMCMD nMSINS -- MMCMD -- -- GPIO<11 3> ICO CZ GPIO<113 > -- -- USB_P3_3 I2S_SYSCLK AC97_RESET _n -- GPIO<11 4> Note [17] ICO CZ GPIO<114 > Note [17] CIFDD_<1> -- -- UVS0 -- GPIO<11 5> Note [17] ICO CZ GPIO<115 > Note [17] DREQ<0> CIF_DD<3> MBREQ UEN nUVS1 PWM_OUT <1> S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name W13 Ty p e Pin Use Summary (Sheet 13 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pd-0 Note[1] Note [3] Pu-1 Note[1] Note [3] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 48 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 C24 D20 A22 C18 B20 GPIO<11 6> ICO CZ GPIO<116 > CIF_DD<2> AC97_SDATA _IN_0 UDET DVAL<0> nUVS2 MBGNT GPIO<11 7> ICO CZ GPIO<117 > SCL -- -- SCL -- -- GPIO<11 8> ICO CZ GPIO<118 > SDA -- -- SDA -- -- S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n Ty p e Name E20 F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 14 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: Pu-1 Note[1] Note [3] Pu-1 Note[1] Note [3], Note[1 2] Pu-1 Note[1] Note [3], Note[1 2] VCC_USB B22 D18 USBC_P IAO AZ USBC_P USBC_P -- -- Hi-Z Hi-Z C20 E19 USBC_N IAO AZ USBC_N USBC_N -- -- Hi-Z Hi-Z E22 E22 USBH_P <1> IAO AZ USBH_P< 1> USBH_P<1> -- -- Hi-Z Hi-Z D23 D22 USBH_N <1> IAO AZ USBH_N< 1> USBH_N<1> -- -- Hi-Z Hi-Z KP_MKIN<5> USB_P3_5 CIF_DD<4 > Pd-0 Note[1] Note [3] -- nURST -- KP_MKIN<6> USB_P3_1 CIF_DD<5 > Pd-0 Note[1] Note [3] -- UCLK -- UIO -- -- Driven Low Hi-Z VCC_USIM F22 F23 E23 H19 G19 GPIO<90 > GPIO<91 > F20 UIO ICO CZ ICO CZ ICO CZ GPIO<90> GPIO<91> UIO VCC_REG V22 U20 GPIO<0> ICO CZ GPIO<0> GPIO<0> -- -- Pd-0 Note[1] Note [3] Y24 U21 GPIO<1> ICO CZ GPIO<1> GPIO<1> -- -- Pu-1 Note[1] Note [7] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 15 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: W21 V22 GPIO<3> ICO CZ GPIO<3> PWR_SCL -- -- Pu-1 Note[1] Hi-Z W23 T19 GPIO<4> ICO CZ GPIO<4> PWR_SDA -- -- Pu-1 Note[1] Hi-Z U22 T22 GPIO<9> Note [18] ICO CZ GPIO<9> Note [18] -- -- FFCTS Note [7] HZ_CLK -- CHOUT<0 > Pd-0 Note[1] GPIO<10 > Note [18] ICO CZ GPIO<10> Note [18] FFDCD -- USB_P3_5 Pd-0 Note[1] Note [7] HZ_CLK -- CHOUT<1 > Pd-0 Note[1] Note [7] V23 U22 W24 T21 CLK_RE Q ICO CZ CLK_REQ CLK_REQ -- -- Pu-1 Note [8] Y22 W20 NRESET IC nRESET nRESET -- -- Input Note [9] Input Y21 W21 NRESET _OUT OC nRESET_ OUT nRESET_OUT -- -- Low Note [8] AB23 V19 BOOT_S EL IC BOOT_SE L BOOT_SEL -- -- Input Input Y23 W22 PWR_E N OC PWR_EN PWR_EN -- -- Note[16] Note [8] AB24 U19 NBATT_ FAULT IC nBATT_FA ULT nBATT_FAULT -- -- Low Input W22 V20 NVDD_F AULT IC nVDD_FA ULT nVDD_FAULT -- -- Low Input AA24 V21 SYS_EN ICO CZ SYS_EN SYS_EN -- -- -- Note [7] AB21 Y19 PWR_C AP<0> OA -- PWR_CAP<0> -- -- -- Note [7] AD22 AA21 PWR_C AP<1> OA -- PWR_CAP<1> -- -- -- Note [7] AC22 Y18 PWR_C AP<2> OA -- PWR_CAP<2> -- -- -- Note [7] NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 50 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n Ty p e Name F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 16 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: AA20 W17 PWR_C AP<3> OA -- PWR_CAP<3> -- -- -- Note [7] U21 T20 NTRST IC nTRST nTRST -- -- Input Note [9] Input U23 R22 TDI IC TDI TDI -- -- Input Note [9] Input V24 R21 TDO OCZ TDO TDO -- -- Hi-Z Hi-Z T21 R20 TMS IC TMS TMS -- -- Input Note [9] Input T22 R19 TCK IC TCK TCK -- -- Input Input T23 P22 TESTCL K IC TESTCLK TESTCLK -- -- Pd-0 Input VCC_OSC AC21 AB20 PXTAL_I N IA PXTAL_IN PXTAL_IN -- -- Note[2] Note [2] AD21 AA20 PXTAL_ OUT OA PXTAL_O UT PXTAL_OUT -- -- Note[2] Note [2] AA22 Y21 TXTAL_I N IA TXTAL_IN TXTAL_IN -- -- Note[2] Note [2] AA23 Y22 TXTAL_ OUT OA TXTAL_OU T TXTAL_OUT -- -- Note[2] Note [2] AB22 W19 PWR_O UT OA PWR_OUT PWR_OUT -- -- Hi-Z Hi-Z SUPPLIES AB20 Y17 VCC_BA TT PS VCC_BAT T VCC_BATT -- -- Input Input A12 B10 VCC_IO PS VCC_IO VCC_IO -- -- Input Input AD17 W15 VCC_IO PS VCC_IO VCC_IO -- -- Input Input A16 D14 VCC_IO PS VCC_IO VCC_IO -- -- Input Input B24 A21 VCC_US B PS VCC_USB VCC_USB -- -- Input Input A24 A22 VCC_US B PS VCC_USB VCC_USB -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 17 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: A23 B22 VCC_US B PS VCC_USB VCC_USB -- -- Input Input B23 D19 VCC_US B PS VCC_USB VCC_USB -- -- Input Input P24 M19 VCC_LC D PS VCC_LCD 0 VCC_LCD -- -- Input Input J24 J21 VCC_LC D PS VCC_LCD 1 VCC_LCD -- -- Input Input P1 B2 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input C3 C3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input E2 C6 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input L3 C9 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AD2 F3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AC2 H3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AC1 K3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AD1 M3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input M1 P3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input H1 T3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input F1 V3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AD8 Y3 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input U2 Y5 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 52 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 18 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: AA2 Y7 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AC8 Y9 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input B8 AA2 VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input A4 N/A VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AC6 N/A VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input W2 N/A VCC_ME M PS VCC_MEM VCC_MEM -- -- Input Input AD12 AA11 VCC_BB PS VCC_BB VCC_BB -- -- Input Input AC20 AB19 VCC_PL L PS VCC_PLL VCC_PLL -- -- Input Input A9 B4 VCC_SR AM PS VCC_SRA M VCC_SRAM -- -- Input Input A8 B7 VCC_SR AM PS VCC_SRA M VCC_SRAM -- -- Input Input A5 B8 VCC_SR AM PS VCC_SRA M VCC_SRAM -- -- Input Input B4 C5 VCC_SR AM PS VCC_SRA M VCC_SRAM -- -- Input Input B12 D11 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input A7 E6 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input D3 E8 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input J23 F5 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input L24 H5 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n Ty p e Name F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 19 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: F24 L4 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input AD16 E15 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input R24 E17 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input M23 F18 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input B21 H18 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input W3 L19 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input AD4 R5 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input T2 U5 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input AD11 V6 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A V8 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A W11 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A R18 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A U18 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A V15 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input N/A V17 VCC_CO RE PS VCC_COR E VCC_CORE -- -- Input Input E24 F21 VCC_US IM PS VCC_USI M VCC_USIM -- -- Input Input AA21 W18 VSS PS VSS VSS -- -- Input Input AC24 Y20 VSS PS VSS VSS -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 54 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n Ty p e Name F u n c ti o n A ft e r R e s e t Pin Use Summary (Sheet 20 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: AD24 AA22 VSS PS VSS VSS -- -- Input Input AC23 AB21 VSS PS VSS VSS -- -- Input Input AD23 AB22 VSS PS VSS VSS -- -- Input Input V21 N/A VSS PS VSS VSS -- -- Input Input D11 B12 VSS_IO PS VSS_IO VSS_IO -- -- Input Input AA19 B15 VSS_IO PS VSS_IO VSS_IO -- -- Input Input D15 B18 VSS_IO PS VSS_IO VSS_IO -- -- Input Input N21 D21 VSS_IO PS VSS_IO VSS_IO -- -- Input Input AA16 H21 VSS_IO PS VSS_IO VSS_IO -- -- Input Input H21 M21 VSS_IO PS VSS_IO VSS_IO -- -- Input Input F21 N19 VSS_IO PS VSS_IO VSS_IO -- -- Input Input D18 AA14 VSS_IO PS VSS_IO VSS_IO -- -- Input Input U24 AA18 VSS_IO PS VSS_IO VSS_IO -- -- Input Input D5 A1 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input F4 A2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input H4 B1 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input J4 B3 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input AC3 B6 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input AB2 B9 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input L4 F2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input T4 H2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input V4 L2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 21 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: AA5 P2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input AA8 T2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input AA9 V2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input D9 AA1 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input N4 AA6 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input R2 AA9 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input C5 AB1 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input Y4 AB2 VSS_ME M PS VSS_MEM VSS_MEM -- -- Input Input AA13 AB11 VSS_BB PS VSS_BB VSS_BB -- -- Input Input AD20 AA19 VSS_PL L PS VSS_PLL VSS_PLL -- -- Input Input B2 E5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input A2 E7 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input B1 E9 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input A1 G5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input J21 J5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input D10 E14 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input AA15 E16 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Doc. No. MV-S104690-00 Rev. D Page 56 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S l e e p Sta t e R e s e t Sta t e T h i rd A lt e r n a t e F u n c ti o n S e co n d a ry A l te rn at e F u n c ti o n P r i m a r y F u n c ti o n F u n c ti o n A ft e r R e s e t Name Ty p e Pin Use Summary (Sheet 22 of 22) PBGA Ball# (23x23) V F -B G A B a ll # ( 1 3 x 1 3 ) Table 3: M21 E18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input U3 G18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input AA7 J18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input P21 P5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input K21 T5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input G21 V5 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input D21 V7 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input D12 V9 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input D8 P18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input W4 T18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input AA12 V14 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input B5 V16 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input D7 V18 VSS_CO RE PS VSS_COR E VSS_CORE -- -- Input Input NOTE: Refer to Table 4 for Numbered Notes on Reset and Sleep States. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 4.3 Signal Types Table 4: Note Pin Use and Mapping Notes (Sheet 1 of 2) D e s c r i p t io n [1] GPIO reset/deep sleep operation: After any reset is asserted or if the PXA270 processor is in deep sleep mode, these pins are configured as GPIO inputs by default. The input buffers for these pins are disabled to prevent current drain and must be enabled prior to use by clearing the read disable hold bit, PSSR[RDH]. Until RDH is cleared, each pin is pulled high (Pu-1), pulled low (Pd-0), or floated (Hi-Z). [2] Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators and are not affected by either reset or sleep. For more information, see the "Clocks and Power" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual. [3] GPIO sleep operation: During the transition into sleep mode, the configuration of these pins is determined by the corresponding GPIO setting. This pin is not driven during sleep if the direction of the pin is selected to be an input. If the direction of the pin is selected as an output, the value contained in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) is driven out onto the pin and held while the PXA270 processor is in sleep mode. Upon exit from sleep mode, GPIOs that are configured as outputs continue to hold the standby, sleep, or deep-sleep state until software clears the peripheral control hold bit, PSSR[PH]. Software must clear this bit (by writing 0b1 to it) after the peripherals have been fully configured, as described in Note[1], but before the process actually uses them. GPIOs that are configured as inputs immediately after exiting sleep mode cannot be used until PSSR[RDH] is cleared. [4] Static memory control pins: During sleep mode, these pins can be programmed either to drive the value in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software must set PCFR[FS]. If FS is not set, these pins function as described in Note[3] during the transition to sleep mode. [5] PCMCIA control pins: During sleep mode, these pins can be programmed either to drive the value in the Power Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software must set PCFR[FP]. If FP is not set, these pins function as described in Note[3] during the transition to sleep mode. [6] (reserved) [7] When the power manager overrides the GPIO alternate function, the Power Manager GPIO Sleep-State registers (PGSR0/1/2/3) and the PSSR[RDH] bit are ignored. Pullup and pulldown are disabled immediately after the power manager overrides the GPIO function. [8] Output functions during sleep mode [9] Pull-up always enabled [10] (reserved) [11] Pins do not function during sleep mode if the OS timer is active [12] Pins must be floated by software during sleep mode (floating does not happen automatically) [13] (reserved) [14] (reserved) [15] The pin is three-stateable (Hi-Z) based on the value of PCFR[FS]. There is no PGSR0/1/2/3 setting associated with the pin because it is not a GPIO. [16] PWR_EN goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset within the PXA270 processor, after SYS_EN is driven high. Doc. No. MV-S104690-00 Rev. D Page 58 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 4: Note Pin Use and Mapping Notes (Sheet 2 of 2) D e s c r i p t io n [17] GPIOs 114 and115: The alternate function configuration of these pins is ignored when either PUCR[USIM114] or PUCR[USIM115] bits are set. Setting these bits forces the USIM enable signal onto these GPIOs. [18] When software sets the OSCC[PIO_EN] or OSCC[TOUT_EN] bits, then any GPIO alternate function setting applied to GPIO<9> or GPIO <10> is overridden with the CLK_PIO function on GPIO<9> and CLK_TOUT on GPIO<10>. [19] Refer to Table 6. Table 5: Signal Types 4.4 Ty p e D e s c r i p t io n IC CMOS input OC CMOS output OCZ CMOS output, three-stateable ICOCZ CMOS bidirectional, three-stateable IA Analog input OA Analog output IAOA Analog bidirectional IAOAZ Analog bidirectional - three-stateable PS Power supply Memory Controller Reset and Initialization On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by BOOT_SEL (see the Marvell(R) PXA27x Processor Family Developers Manual, Memory Controller chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory interface control registers are available for writing. On hardware reset, the memory pins and controller are in the state shown in Table 6. Table 6: Memory Controller Pin Reset Values (Sheet 1 of 2) Pin Name R e s e t , S l e e p , Sta n d b y, D e e p - S l e e p , F r e q u e n c y C h a n g e , a n d M a n u a l S e l f- R e fr e s h M o d e Va l u e s SDCLK <31:0> 0b000 SDCKE 0 DQM <3:0> 0b0000 nSDCS <3:2> GPIO (memory controller drives 0b11) nSDCS <1:0> 0b11 nWE 1 nSDRAS 1 nSDCAS 1 nOE 1 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 6: Memory Controller Pin Reset Values (Sheet 2 of 2) Pin Name R e s e t , S l e e p , Sta n d b y, D e e p - S l e e p , F r e q u e n c y C h a n g e , a n d M a n u a l S e l f- R e fr e s h M o d e Va l u e s MA <25:0> 0x0000_00001 RDnWR 0 MD <31:0> 0x0000_00002 nCS <0> 1 nCS <5:1> GPIO (memory controller drives 0b11111) nPIOIR GPIO (memory controller drives high) nPIOIW GPIO (memory controller drives high) nPOE GPIO (memory controller drives high) nPWE GPIO (memory controller drives high) NOTE: This indicates that the GPIO pin, if configured for the alternate function used by the memory controller during reset, drives the represented value. NOTE: SCLK<3> is only available on PXA270 processor family packages 1. MA pins are driven 2. MD pins are pulled low The address signals are driven low and data signals are pulled low during sleep, standby, deep-sleep, frequency-change modes, and manual self-refresh. All other memory control signals are in the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they are kept there by driving SDCKE low. 4.5 Power-Supply Pins Table 7 summarize the power-supply ball count. Table 7: Discrete (13x13 VF-BGA) Power Supply Pin Summary (Sheet 1 of 2) Name Doc. No. MV-S104690-00 Rev. D Page 60 Number of Package B a l ls 1 3 x 1 3 m m V F -B G A Number of Pachage Balls 23x23 mm PBGA VCC_BATT 1 1 VCC_IO 3 3 VCC_USB 4 4 VCC_LCD 2 2 VCC_MEM 19 16 VCC_BB 1 1 VCC_PLL 1 1 VCC_SRAM 4 4 VCC_CORE 14 20 VCC_USIM 1 1 VSS 6 5 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 7: Discrete (13x13 VF-BGA) Power Supply Pin Summary (Sheet 2 of 2) Name Copyright (c) 4/3/09 Marvell April 2009 Released Number of Package B a l ls 1 3 x 1 3 m m V F -B G A Number of Pachage Balls 23x23 mm PBGA VSS_IO 9 9 VSS_MEM 17 17 VSS_BB 1 1 VSS_PLL 1 1 VSS_CORE 56 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Doc. No. MV-S104690-00 Rev. D Page 61 PXA270 Processor Electrical, Mechanical, and Thermal Specification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Doc. No. MV-S104690-00 Rev. D Page 62 Copyright (c) 4/3/09 Marvell April 2009 Released 5 Electrical Specifications 5.1 Absolute Maximum Ratings The absolute maximum ratings (shown in Table 8) define limitations for electrical and thermal stresses. These limits prevent permanent damage to the Marvell(R) PXA270 processor. Note Note Table 8: Absolute maximum ratings are not operating ranges. Absolute Maximum Ratings Symbol Description Min Max U n its TS Storage temperature -40 125 C VCC_OL1 Offset voltage between any of the following pins: VCC_CORE -0.3 0.3 V VCC_OL2 Offset voltage between any of the following pins: VCC_SRAM -0.3 0.3 V VCC_OH1 Offset voltage between any of the following pins: VCC_MEM -0.3 0.3 V VCC_OH2 Offset voltage between any of the following pins: VCC_IO -0.3 0.3 V VCC_OH3 Offset voltage between VCC_LCD<0> and VCC_LCD<1> -0.3 0.3 V VCC_HV Voltage applied to high-voltage supply pins (VCC_BB, VCC_USB, VCC_USIM, VCC_MEM, VCC_IO<, VCC_LCD) VSS-0.3 VSS+4.0 V VCC_LV Voltage applied to low-voltage supply pins (VCC_CORE, VCC_PLL, VCC_SRAM) VSS-0.3 VSS+1.45 V VIP Voltage applied to non-supply pins except PXTAL_IN, PXTAL_OUT, TXTAL_IN, and TXTAL_OUT pins VSS-0.3 VSS+4.0 V VIP_X Voltage applied to XTAL pins (PXTAL_IN, PXTAL_OUT, TXTAL_IN, TXTAL_OUT) VSS-0.3 VSS+1.45 V VESD Maximum ESD stress voltage, three stresses maximum: Any pin to any supply pin, either polarity, or Any pin to all non-supply pins together, either polarity -- 2000 V IEOS Maximum DC input current (electrical overstress) for any non-supply pin -- 5 mA Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 5.2 Operating Conditions This section shows operating voltage, frequency, and temperature specifications for the PXA270 processor. Table 9 shows each power domains supported voltages (except for VCC_MEM and VCC_CORE). Table 10 shows all of the supported memory voltages and frequency operating ranges (VCC_MEM). Table shows all of the supported core voltage and frequency ranges (VCC_CORE). The operating temperature specification is a function of voltage and frequency. Table 9: Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 3) Symbol Description Min Ty p i c a l Max U n its -25 -- +85 C -40 -- +85 Junction-to-case temperature gradient (VF-BGA) -- 2 -- Junction-to-case temperature gradient (PBGA) -- 1.4 -- Operating Temperature Tcase Package operating temperature (Standard Temp) Package operating temperature (Extended Temp - PBGA ONLY) Theta Jc C / watt VCC_BATT Voltage VVCC0 Voltage applied on VCC_BATT @3.0V 2.40 3.00 3.75 V VVDF1 Voltage difference between VCC_BATT and VCC_IO during power-on reset or deep-sleep wake-up (from the assertion of SYS_EN to the de-assertion of nRESET_OUT) 0 -- 0.30 V VVDF2 Voltage difference between VCC_BATT and VCC_IO when VCC_IO is enabled 0 -- 0.20 V Tbramp Ramp Rate -- 10 12 mV/S VCC_PLL Voltage VVCC1 Voltage applied on VCC_PLL @1.3V (+10 / -10%) 1.17 1.30 1.43 V Tpwrramp Ramp Rate -- 10 12 mV/S VCC_BB Voltages VVCC2a Voltage applied on VCC_BB @1.8V (+20 / -5%) 1.71 1.80 2.16 V VVCC2b Voltage applied on VCC_BB @2.5V (+10 / -10%) 2.25 2.50 2.75 V VVCC2c Voltage applied on VCC_BB @3.0V (+10 / -10%) 2.70 3.0 3.30 V VVCC2d Voltage applied on VCC_BB @3.3V (+10 / -10%) 2.97 3.3 3.63 V Tsysramp Ramp Rate -- 10 12 mV/S Doc. No. MV-S104690-00 Rev. D Page 64 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 9: Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 3) Symbol Description Min Ty p i c a l Max U n its VCC_BB may optionally be tied to the same PMIC regulator as VCC_IO if the system design allows both VCC_IO and VCC_BB to use the same voltage level. This allows the GPIO's on VCC_BB to be used at the same voltage level. VCC_LCD Voltages VVCC3a Voltage applied on VCC_LCD @1.8V (+20 / -5%) 1.71 1.80 2.16 V VVCC3b Voltage applied on VCC_LCD @2.5V (+10 / -10%) 2.25 2.50 2.75 V VVCC3c Voltage applied on VCC_LCD @3.0V (+10 / -10%) 2.70 3.0 3.30 V VVCC3d Voltage applied on VCC_LCD @3.3V (+10 / -10%) 2.97 3.3 3.63 V Tsysramp Ramp Rate -- 10 12 mV/S VCC_IO Voltages VVCC4a Voltage applied on VCC_IO @3.0V (+10 / -10.3%) 2.69175 3.0 3.30 V VVCC4b Voltage applied on VCC_IO @3.3V (+10 / -10%) 2.97 3.3 3.63 V Tsysramp Ramp Rate -- 10 12 mV/S VCC_IO must be maintained at a voltage as high as or higher than, all other supplies except for VCC_BATT and VCC_USB VCC_USIM Voltages VVCC5a Voltage applied on VCC_USIM @1.8V (+20 / -5%) 1.71 1.80 2.16 V VVCC5b Voltage applied on VCC_USIM @3.0V (+10 / -10%) 2.70 3.0 3.30 V Tsysramp Ramp Rate -- 10 12 mV/S If the system does NOT use the USIM module, VCC_USIM can be tied to VCC_IO (at any supported VCC_IO voltage level). This allows the GPIO's on VCC_USIM to be used at the same voltage level as VCC_IO GPIO's. NOTE: Software must NOT configure USIM signals to be used if this is done. VCC_SRAM Voltage VVCC6 Voltage applied on VCC_SRAM @1.1V (+10 / -10%) 0.99 1.10 1.21 V Tpwrramp Ramp Rate -- 10 12 mV/S 2.70 3.00 3.30 V VCC_USB Voltage VVCC7a Copyright (c) 4/3/09 Marvell April 2009 Released Voltage applied on VCC_USB @3.0V (+10 / -10%) Doc. No. MV-S104690-00 Rev. D Page 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 9: Voltage, Temperature, and Frequency Electrical Specifications (Sheet 3 of 3) Symbol Description Min Ty p i c a l Max U n its VVCC7b Voltage applied on VCC_USB @3.3V (+10 / -10%) 2.97 3.30 3.63 V Tsysramp Ramp Rate -- 10 12 mV/S System design must ensure that the device case temperature is maintained within the specified limits. In some system applications it may be necessary to use external thermal management (for example, a package-mounted heat spreader) or configure the device to limit power consumption and maintain acceptable case temperatures. Table 10 shows the supported memory frequency and memory supply voltage operating ranges for the PXA270 processor. Table 10: Memory Voltage and Frequency Electrical Specifications Symbol Description Min Ty p i c a l Max U n its Memory Voltage and Frequency Range 1 VMEM1 Voltage applied on VCC_MEM 1.71 1.80 2.16 V fSM1A External synchronous memory frequency, SDCLK1, SDCLK2 13 -- 104 MHz fSM1B External synchronous memory frequency, SDCLK0 13 -- 104 MHz Tsysramp Ramp Rate -- 10 12 mV/S Memory Voltage and Frequency Range 2 VMEM2 Voltage applied on VCC_MEM 2.25 2.50 2.75 V fSM2A External synchronous memory frequency, SDCLK1, SDCLK2 13 -- 104 MHz fSM2B External synchronous memory frequency, SDCLK0 13 -- 104 MHz Tsysramp Ramp Rate -- 10 12 mV/S 2.70 3.0 3.3 V Memory Voltage and Frequency Range 3 VMEM3 Voltage applied on VCC_MEM fSM3A External synchronous memory frequency, SDCLK1, SDCLK2 13 -- 104 MHz fSM3B External synchronous memory frequency, SDCLK0 13 -- 104 MHz Tsysramp Ramp Rate -- 10 12 mV/S Memory Voltage and Frequency Range 4 VMEM4 Voltage applied on VCC_MEM 2.97 3.30 3.63 V fSM4A External synchronous memory frequency, SDCLK1, SDCLK2 13 -- 104 MHz fSM4B External synchronous memory frequency, SDCLK0 13 -- 104 MHz Tsysramp Ramp Rate -- 10 12 mV/S Table 11 shows the supported core frequency and core supply voltage operating ranges for the PXA270 processor. Each frequency range is specified in the following format: Doc. No. MV-S104690-00 Rev. D Page 66 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 (core frequency/internal system bus frequency/memory controller frequency/SDRAM frequency) Note Note Refer to the "Clocks and Power" section of the Marvell(R) PXA27x Processor Family Developers Manual for supported frequencies, clock register settings as listed in Table 11. Table 11: Core Voltage and Frequency Electrical Specifications (Sheet 1 of 2) Symbol Description Min Ty p i c a l Max U n its Core Voltage and Frequency Range 1 (13/13/13/13 CCCR[CPDIS]=1, CCCR[PPDIS]=1) VVCCC1 Voltage applied on VCC_CORE 0.95 1.0 1.705 V fCORE1 Core operating frequency 13 -- 13 MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 2 (13/13/13/13 CCCR[CPDIS]=1, CCCR[PPDIS]=0), (91/45.5/91/45.5), and (104/104/104/104) VVCCC2 Voltage applied on VCC_CORE 0.95 1.0 1.705 V fCORE2 Core operating frequency 91 -- 104 MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 3 (156/104/104/104) VVCCC3 Voltage applied on VCC_CORE 0.95 1.00 1.705 V fCORE3 Core operating frequency -- 156 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 4 (208/208/208/104) and (208/208/104/104) VVCCC4 Voltage applied on VCC_CORE 1.12 1.18 1.705 V fCORE4 Core operating frequency -- 208 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 4a (208/104/104/104) VVCCC4a Voltage applied on VCC_CORE 0.9975 1.05 1.705 V fCORE4a Core operating frequency -- 208 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 5 (312/208/208/104) and (312/208/104/104) VVCCC5 Voltage applied on VCC_CORE 1.1875 1.25 1.705 V fCORE5 Core operating frequency -- 312 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 5a (312/104/104/104) VVCCC5a Voltage applied on VCC_CORE 0.99 1.1 1.705 V fCORE5a Core operating frequency -- 312 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 67 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 11: Core Voltage and Frequency Electrical Specifications (Sheet 2 of 2) Core Voltage and Frequency Range 6 (416/208/208/104) amd (416/208/104/104) VVCCC6 Voltage applied on VCC_CORE 1.2825 1.35 1.705 V fCORE6 Core operating frequency -- 416 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 7 (520/208/208/104) and (520/208/104/104) VVCCC7 Voltage applied on VCC_CORE 1.3775 1.45 1.705 V fCORE7 Core operating frequency -- 520 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core Voltage and Frequency Range 8 (624/208/208/104) and (624/208/104/104) VVCCC8 Voltage applied on VCC_CORE 1.4725 1.55 1.705 V fCORE8 Core operating frequency -- 624 -- MHz Tpwrramp Ramp Rate -- 10 12 mV/S Core operating frequency not offered in PBGA package. 5.2.1 Internal Power Domains The external power supplies are used to generate several internal power domains, which are shown in Table 12. Refer to the Power Manager / Internal Power Domain Block Diagram in the "Clocks and Power" section of the Marvell(R) PXA27x Processor Family Developers Manual for more information on internal power domains. Table 12: Internally Generated Power Domain Descriptions Name U n i ts Generation VCC_REG IO associated with deep-sleep-active units Switched between VCC_BATT and VCC_IO VCC_OSC Oscillator power supplies Generated from VCC_REG VCC_RTC RTC and power manager supply Switched between VCC_OSC and VCC_CORE - Power manager I2C supply Switched between VCC_OSC and VCC_CORE - VCC_CPU CPU core Independent power-down from VCC_CORE - VCC_PER Peripheral units Independent power-down from VCC_CORE - Particular internal SRAM unit Switched between VCC_OSC and VCC_SRAM - VCC_PI VCC_Rx To l e r a n c e +/- 30% Table 13 shows the recommended core voltage specification for each of the lower power modes. Table 13: Core Voltage Specifications For Lower Power Modes Mode Description Min Ty p i c a l Max U n i ts Standby Voltage applied on VCC_CORE 1.045 1.1 1.21 V Deep-Idle Voltage applied on VCC_CORE 0.95 1.0 1.705 V Doc. No. MV-S104690-00 Rev. D Page 68 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.3 Power-Consumption Specifications Power consumption depends on the operating voltage and frequency, peripherals enabled, external switching activity, and external loading and other factors. Use these specifications as a guideline for power consumption capacity. These typical guidelines vary across different platforms and software applications. Table 14 contains three sets of power consumption information: Active Power Consumption, Idle Power Consumption, and Low-Power Modes Power Consumption. The data set are projected numbers based off of measured data at room temperature. For Active Power Consumption data, no peripherals are enabled except for UART. Table 15 contains idle and low power mode maximum power consumption information based on experimental and manufacturing test limits. Table 14: Typical Power-Consumption Specifications (Sheet 1 of 4) P a ra m e t e r D e s c r i p t i o n Ty p i c a l U n i ts Conditions 624 MHz Active Power (208 MHz System bus) 925 mW VCC_CORE = 1.55V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 520 MHz Active Power (208 MHz System bus) 747 mW VCC_CORE = 1.45V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 416 MHz Active Power (208 MHz System bus) 570 mW VCC_CORE = 1.35V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 312 MHz Active Power (208 MHz System bus) 390 mW VCC_CORE = 1.25V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 312 MHz Active Power (104 MHz System bus) 375 mW VCC_CORE = 1.1V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Active Power Consumption Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 69 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 14: Typical Power-Consumption Specifications (Sheet 2 of 4) P a ra m e t e r D e s c r i p t i o n Ty p i c a l U n i ts Conditions 208 MHz Active Power (208 MHz System bus) 279 mW VCC_CORE = 1.15V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 104 MHz Active Power (104 MHz System bus) 116 mW VCC_CORE = 0.9V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 13 MHz Active Power (CCCR[CPDIS=1) 44.2 mW VCC_CORE = 0.85V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 624 MHz Idle Power (208 MHz System bus) 260 mW VCC_CORE = 1.55V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 520 MHz Idle Power (208 MHz System bus) 222 mW VCC_CORE = 1.45V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 416 MHz Idle Power (208 MHz System bus) 186 mW VCC_CORE = 1.35V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 312 MHz Idle Power (208 MHz System bus) 154 mW VCC_CORE = 1.25V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Idle Power Consumption Doc. No. MV-S104690-00 Rev. D Page 70 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 14: Typical Power-Consumption Specifications (Sheet 3 of 4) P a ra m e t e r D e s c r i p t i o n Ty p i c a l U n i ts Conditions 312 MHz Idle Power (104 MHz System bus) 109 mW VCC_CORE = 1.1V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 208 MHz Idle Power (208 MHz System bus) 129 mW VCC_CORE = 1.15V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 104 MHz Idle Power (104 MHz System bus) 64 mW VCC_CORE = 0.9V VCC_SRAM = 1.1V VCC_PLL = 1.3V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 13 MHz Idle Mode1 Power (LCD on) 15.4 mW VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V 13 MHz Idle Mode1 Power (LCD off) 8.5 mW VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Deep-Sleep mode 0.1014 mW VCC_CORE, VCC_SRAM, VCC_PLL = 0V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Low Power modes Power Consumption Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 14: Typical Power-Consumption Specifications (Sheet 4 of 4) P a ra m e t e r D e s c r i p t i o n Ty p i c a l U n i ts Conditions Sleep mode 0.1630 mW VCC_CORE, VCC_SRAM, VCC_PLL = 0V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V Standby mode 1.7224 mW VCC_CORE, VCC_SRAM, VCC_PLL = 1.1V VCC_MEM, VCC_BB, VCC_USIM, VCC_LCD = 1.8V VCC_IO, VCC_BATT, VCC_USB= 3.0V NOTE: 1) 13 MHz Idle Mode (CCCR[CPDIS] =1 (CCCR[PPDIS] = 1) Table 15: Maximum Idle and Low Power Mode Power-Consumption Specifications P a ra m e t e r D e s c r i p t i o n Maximum U n i ts C o n d i ti o n s 624MHz Idle Current on VCC_CORE (PX=208MHz) 770 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=1.705V, VCC_PERI1=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V 520MHz Idle Current on VCC_CORE (PX=208MHz) 630 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=1.595V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V 416MHz Idle Current on VCC_CORE (PX=208MHz) 500 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=1.485V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V 312MHz Idle Current on VCC_CORE (PX=208MHz) 380 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=1.375V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V 208MHz Idle Current on VCC_CORE (PX=208MHz) 260 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=1.265V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V Idle Mode Power Consumption Doc. No. MV-S104690-00 Rev. D Page 72 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 P a ra m e t e r D e s c r i p t i o n Maximum U n i ts C o n d i ti o n s 104MHz Idle Current on VCC_CORE, (PX=104MHz) 150 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=0.99V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V Idle Current on VCC_PERI1, All Core Speeds 200 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=any, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V Idle Current on VCC_IO, All Core Speeds 50 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=any, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V Idle Current on VCC_PLL, All Core Speeds 100 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=any, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V 105 mA Temp=85C Tcase, VCC_CORE=VCC_SRAM=VC C_PLL=0.935V, VCC_PERI=3.63V, VCC_IO=3.63V, VCC_BATT=3.75V Standby Current on VCC_CORE 5 mA Temp=Room, VCC_CORE=VCC_SRAM=VC C_PLL=1.1V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V Standby Current on VCC_PERI 1.6 mA Temp=Room, VCC_CORE=VCC_SRAM=VC C_PLL=1.1V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V Standby Current on VCC_IO 1 mA Temp=Room, VCC_CORE=VCC_SRAM=VC C_PLL=1.1V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V 0.15 mA Temp=Room, VCC_CORE=VCC_PLL=0V, VCC_SRAM=0.95V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V Deep-Idle Mode Power Consumption 13MHz Deep Idle Current on VCC_CORE (LCD off) Standby Mode Power Consumption Sleep Mode Power Consumption Sleep Current on VCC_CORE Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification P a ra m e t e r D e s c r i p t i o n Maximum U n i ts C o n d i ti o n s Sleep Current on VCC_PERI 0.47 mA Temp=Room, VCC_CORE=VCC_PLL=0V, VCC_SRAM=0.95V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V Sleep Current on VCC_IO 0.70 mA Temp=Room, VCC_CORE=VCC_PLL=0V, VCC_SRAM=0.95V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V Sleep Current on VCC_PLL 0.043 mA Temp=Room, VCC_CORE=VCC_PLL=0V, VCC_SRAM=0.95V, VCC_PERI=1.8V, VCC_IO=VCC_BATT=3.0V NOTE: 1) VCC_PERI = VCC_MEM + VCC_BB + VCC_USIM + VCC_LCD 5.4 DC Specification The DC characteristics for each pin include input sense levels, output drive levels, and currents. These parameters can be used to determine maximum DC loading and to determine maximum transition times for a given load. Table 16 shows the DC operating conditions for the high- and low-strength input, output, and I/O pins. Note Note VCC_IO must be maintained at a voltage as high as or higher than all other supplies except VCC_BATT and VCC_USB. Table 16: Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 1 of 2) Symbol D e s c ri p t i o n M in Max U n i ts Te s t in g C o n d i t io n s / Notes Input DC Operating Conditions (VCC = 1.8V, 2.5, 3.0, 3.3 Typical) VIH1 Input high voltage, all standard input and I/O pins, relative to applicable VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, or VCC_USIM) 0.8 * VCC VCC + 0.1 V -- VIH_USB Input high voltage for the USB bus voltage domain (VCC_USB) 0.8 * VCC 3.6 V -- VIL1 Input low voltage, all standard input and I/O pins, relative to applicable VSS (VSS_IO, VSS_MEM, or VSS_BB) and VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) VSS - 0.1 0.2 * VCC V -- OS DC Overshoot voltage / duration -- +1 V Max duration of 4nS Doc. No. MV-S104690-00 Rev. D Page 74 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 16: Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 2 of 2) Symbol D e s c ri p t i o n M in Max U n i ts Te s t in g C o n d i t io n s / Notes US DC Undershoot voltage / duration -- -1 V Max duration of 4nS Output DC Operating Conditions (VCC = 1.8, 2.5, 3.0, 3.3 Typical) VOH1 Output high voltage, all standard output and I/O pins, relative to applicable VCC (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, or VCC_USIM) VCC - 0.3 VCC V IOH = -4 mA2, -3 mA3 VOL1 Output low voltage, all standard output and I/O pins, relative to applicable VSS (VSS_IO, VSS_MEM, or VSS_BB) VSS VSS + 0.3 V IOH = 4 mA2, 3 mA3 NOTES: 1. Programmable drive strengths set to 0x5 for memory and LCD programmable signals. 2. The current for the high-strength pins are MA<25:0>, MD<31:0>, nOE, nWE, nSDRAS, nSDCAS, DQM<3:0>, nSDCS<3:0>, SDCKE<1>, SDCLK<3:0>, RDnWR, nCS<5:0>, and nPWE. 3. The current for all other output and I/O pins are low strength. 5.5 Oscillator Electrical Specifications The PXA270 processor contains two oscillators: a 32.768-kHz oscillator and a 13.000-MHz oscillator. Each oscillator requires a specific crystal. 5.5.1 32.768-kHz Oscillator Specifications The 32.768-kHz oscillator is connected between the TXTAL_IN (amplifier input) and TXTAL_OUT (amplified output). Table 17 and Table 18 list the appropriate 32.768-kHz specifications. To drive the 32.768-kHz crystal pins from an external source: 1. 2. Drive the TXTAL_IN pin with a digital signal that has low and high levels as listed in Table 18. Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The minimum slew rate is 1 volt per 1 s. The maximum current drawn from the external clock source when the clock is at its maximum positive voltage is typically 1 mA. Float the TXTAL_OUT pin or drive it in complement to the TXTAL_IN pin, with the same voltage level and slew rate. Warning Warning The TXTAL_IN and TXTAL_OUT pins must not be driven from an external source if the PXA270 processor sleep / deep sleep DC-DC converter is enabled. Table 17: Typical 32.768-kHz Crystal Requirements (Sheet 1 of 2) Parameter M in i m u m Ty p i c a l Maximum U n its Frequency range -- 32.768 -- kHz Frequency tolerance -30 -- +30 ppm Frequency stability, parabolic coefficient -- -- -0.04 ppm/(C )2 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 17: Typical 32.768-kHz Crystal Requirements (Sheet 2 of 2) Parameter M in i m u m Ty p i c a l Maximum U n its Drive level -- -- 1.0 uW Load capacitance (CL) 6 7.5 12.5 pf Shunt capacitance (CO) -- 0.9 -- pf Motional capacitance (CI) -- 2.1 -- fF Equivalent series resistance (RS) -- 18 65 k Insulation resistance at 100 VDC 100 -- -- M Aging, at operating temperature per year -- -- 3.0 ppm Doc. No. MV-S104690-00 Rev. D Page 76 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 18: Typical External 32.768-kHz Oscillator Requirements Symbol D e s c ri p ti o n Min Ty p i c a l Max U n i ts Amplifier Specifications VIH_X Input high voltage, TXTAL_IN 0.99 1.10 1.21 V VIL_X Input low voltage, TXTAL_IN -0.10 0.00 0.10 V IIN_XT Input leakage, TXTAL_IN -- -- 1 A CIN_XT Input capacitance, TXTAL_IN/TXTAL_OUT -- 18 25 pf tS_XT Stabilization time -- -- 10 s Board Specifications 5.5.2 RP_XT Parasitic resistance, TXTAL_IN/TXTAL_OUT to any node 20 -- -- M CP_XT Parasitic capacitance, TXTAL_IN/TXTAL_OUT, total -- -- 5 pf COP_XT Parasitic shunt capacitance, TXTAL_IN to TXTAL_OUT -- -- 0.4 pf 13.000-MHz Oscillator Specifications The 13.000-MHz oscillator is connected between the PXTAL_IN (amplifier input) and PXTAL_OUT (amplified output). Table 19 and Table 20 list the 13.000-MHz specifications. To drive the 13.000-MHz crystal pins from an external source: 1. 2. Drive the PXTAL_IN pin with a digital signal with low and high levels as listed in Table 20. Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The minimum slew rate is 1 volt / 1 ns. The maximum current drawn from the external clock source when the clock is at its maximum positive voltage typically is 1 mA. Float the PXTAL_OUT pin or drive it in complement to the PXTAL_IN pin, with the same voltage level, slew rate, and input current restrictions. Warning Warning The PXTAL_IN and PXTAL_OUT pins must not be driven from an external source if the PXA270 processor sleep / deep sleep DC-DC converter is enabled. Table 19: Typical 13.000-MHz Crystal Requirements Parameter M in i m u m Ty p i c a l Maximum U n its Frequency range 12.997 13.000 13.002 MHz Frequency tolerance at 25C -50 -- +50 ppm Oscillation mode -- Fnd -- -- Maximum change over temperature range -50 -- +50 ppm Drive level -- 10 100 uW Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 19: Typical 13.000-MHz Crystal Requirements (continued) Parameter M in i m u m Ty p i c a l Maximum U n its Load capacitance (CL) -- 10 -- pf Maximum series resistance (RS) -- 50 -- Aging per year, at operating temperature -- -- 5.0 ppm Table 20: Typical External 13.000-MHz Oscillator Requirements S ymbo l D e s c ri p ti o n Min Ty p i c a l Max U n its Amplifier Specifications VIH_X Input high voltage, PXTAL_IN 0.99 1.10 1.21 V VIL_X Input low voltage, PXTAL_IN -0.10 0.00 0.10 V IIN_XP Input leakage, PXTAL_IN -- -- 10 A CIN_XP Input capacitance, PXTAL_IN/PXTAL_OUT -- 40 50 pf tS_XP Stabilization time -- -- 67.8 ms Board Specifications 5.6 RP_XP Parasitic resistance, PXTAL_IN/PXTAL_OUT to any node 20 -- -- M CP_XP Parasitic capacitance, PXTAL_IN/PXTAL_OUT, total -- -- 5 pf COP_XP Parasitic shunt capacitance, PXTAL_IN to PXTAL_OUT -- -- 0.4 pf CLK_PIO and CLK_TOUT Specifications CLK_PIO can be used to drive a buffered version of the PXTAL_IN oscillator input or can be used as a clock input alternative to PXTAL_IN. Refer to Table 21 for CLK_PIO specifications. A buffered and inverted version of the TXTAL_IN oscillator output is driven out on CLK_TOUT. Refer to Table 22 for CLK_TOUT specifications. Note Note CLK_TOUT and CLK_PIO are only available when software sets the OSCC[PIO_EN] and OSCC[TOUT_EN] bits. Table 21: CLK_PIO Specifications Doc. No. MV-S104690-00 Rev. D Page 78 Parameter Sp e c i fi c a t i o n s Frequency 13 MHz Frequency Accuracy (derived from 13 MHz crystal) +/-200ppm Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 21: CLK_PIO Specifications (continued) Parameter Sp e c i fi c a t i o n s Jitter +/-20pS max Load capacitance (CL) 50pf max Rise and Fall time (Tr & Tf) 15nS max with 50pF load Table 22: CLK_TOUT Specifications 5.7 Parameter Sp e c i fi c a t i o n s Frequency 32KHz Frequency Accuracy (derived from 32 kHz crystal) +/-200ppm Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC Jitter +/-20pS max Load capacitance (CL) 50pf max Rise and Fall time (Tr & Tf) 15nS max with 50pF load 48 MHz Output Specifications Software may configure GPIO<11> or GPIO<12> alternate functions to enable the 48-MHz clock output. The 48-MHz output clock is a divided-down output generated from the 312-MHz peripheral PLL. Refer to Table 23 for the 48-MHz output specifications. Refer to Section 3 of this document for GPIO alternate functions in the pin usage table. Table 23: 48 MHz Output Specifications Copyright (c) 4/3/09 Marvell April 2009 Released Parameter Sp e c i fi c a t i o n s Frequency (derived from 13 MHz crystal) 48 MHz Frequency Accuracy (derived from 13 MHz crystal) +/-200ppm (maximum) Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC Jitter +/-20pS max Load capacitance (CL) 50pf max Rise and Fall time (Tr & Tf) 15nS max with 50pF load Doc. No. MV-S104690-00 Rev. D Page 79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Doc. No. MV-S104690-00 Rev. D Page 80 Copyright (c) 4/3/09 Marvell April 2009 Released 6 AC Timing Specifications A pin's alternating-current (AC) characteristics include input and output capacitance. These factors determine the loading for external drivers and other load analyses. The AC characteristics also include a derating factor, which indicates how much the AC timings might vary with different loads. Note Note The timing diagrams in this chapter show bursts that start at 0 and proceed to 3 or 7. However, the least significant address (0) is not always received first during a burst transfer, because the Marvell(R) PXA270 processor requests the critical word first during burst accesses. Table 24 shows the AC operating conditions for the high- and low-strength input, output, and I/O pins. All AC specification values are valid for the device's entire temperature range. Table 24: Standard Input, Output, and I/O-Pin AC Operating Conditions 6.1 Symbol Description Min Ty p i c a l Max U n its CIN Input capacitance, all standard input and I/O pins -- -- 10 pf COUT_H Output capacitance, all standard high-strength output and I/O pins 20 -- 50 pf COUT_L Output capacitance, all standard low-strength output and I/O pins 20 -- 50 pf AC Test Load Specifications Figure 22 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers use IBIS or other simulation tools to correlate the timing reference load to system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). Figure 22: AC Test Load I/O = 50 Copyright (c) 4/3/09 Marvell April 2009 Released 50pf Doc. No. MV-S104690-00 Rev. D Page 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 6.2 Reset and Power Manager Timing Specifications The processor asserts the nRESET_OUT pin in one of several different modes: Power-on reset Hardware reset Watchdog reset GPIO reset Sleep mode Deep-sleep mode The following sections give the timing and specifications for entry into and exit from these modes. 6.2.1 Power-On Timing Specifications Power-on reset begins when a power supply is detected on the backup battery pin, VCC_BATT, after the processor has been powered off. A power-on reset is equivalent to a hardware reset, in that all units are reset to the same known state as with a hardware reset. A power-on reset is a complete and total reset that occurs only at initial power on. The external power-supply system must enable the power supplies for the processor in a specific sequence to ensure proper operation. Figure 23 shows the timing diagram for a power-on reset sequence. Table 25 details the timing. The sequence for power-on reset is as follows: 1. 2. 3. 4. 5. 6. 7. VCC_BATT is established, then nRESET should be de-asserted to initiate power-on reset. PWR_OUT is asserted. The processor asserts nRESET_OUT. The external power-control subsystem de-asserts nBATT_FAULT to signal that the main battery is connected and not discharged. The processor asserts the SYS_EN signal to enable the power supplies VCC_IO, VCC_MEM, VCC_BB, VCC_USB, and VCC_LCD. VCC_USIM can be established at this time also but can be independently controlled through its own control signals. VCC_IO must be established first. The other supplies can turn on in any order, but they must all be established within 125 milliseconds of the assertion of SYS_EN. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE, VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be established within 125 milliseconds of the assertion of PWR_EN. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system power supplies have been properly established. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset vector. Note Note Doc. No. MV-S104690-00 Rev. D Page 82 nVDD_FAULT is sampled only when the SYS_DEL and PWR_DEL timers have expired. Refer to the Marvell(R) PXA27x Processor Family Developer's Manual, "Initial Power On" and "Deep-Sleep Exit States" for a state diagram. Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 23: Power On Reset Timing t1 t2 t3 t5 VCC_BATT nBATT_FAULT tbramp nRESET SYS_EN VCC_USB, VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USIM PWR_EN VCC_CORE, VCC_SRAM, VCC_PLL tsysramp tpwrramp nVDD_FAULT t4 nRESET_OUT Table 25: Power-On Timing Specifications(OSCC[CRI] = 0) Symbol D e s c ri p t i o n Min Ty p i c a l Max U n i ts t1 Delay from VCC_BATT assertion to nRESET de-assertion 10 -- -- ms t2 Delay from nRESET de-assertion to SYS_EN assertion -- 101 -- ms t3 Delay from SYS_EN assertion to PWR_EN assertion -- 125 -- ms t4 Power supply stabilization time (time to the de-assertion of nVDD_FAULT after the assertion of PWR_EN) -- -- 120 ms t5 Delay from the assertion of PWR_EN to the de-assertion of nRESET_OUT -- 125 -- ms tbramp VCC_BATT power-on Ramp Rate -- 10 12 mV/S tsysramp Power-on Ramp Rate for all external high -voltage power domains -- 10 12 mV/S tpwrramp Power-on Ramp Rate for all external low -voltage power domains (including dynamic voltage changes on VCC_CORE) -- 10 12 mV/S NOTES: 1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS NOTE: This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied externally, which then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to stabilize. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 6.2.2 Hardware Reset Timing The timing sequences shown in Figure 24 for hardware reset and the specifications in Table 26 and Table 27 assume stable power supplies at the assertion of nRESET. Follow the timings indicated in Section 6.2.1 if the power supplies are unstable. Figure 24: Hardware Reset Timing t7 nRESET t6 t8 nRESET_OUT NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence. Table 26: Hardware Reset Timing Specifications (OSCC[CRI] = 0) Symbol D e s c r ip ti o n Min Ty p ic a l Max U n its t6 Delay between nRESET asserted and nRESET_OUT asserted -- < 100 ns 10 ms t7 Assertion time of nRESET 6 -- -- ms t8 Delay between nRESET de-asserted and nRESET_OUT de-asserted 256 -- 265 ms Table 27: Hardware Reset Timing Specifications (OSCC[CRI] = 1) 6.2.3 Symbol D e s c r ip ti o n Min Ty p ic a l Max U n its t6 Delay between nRESET asserted and nRESET_OUT asserted -- < 100 ns 10 ms t7 Assertion time of nRESET 6 -- -- ms t8 Delay between nRESET de-asserted and nRESET_OUT de-asserted 2256 -- 3265 ms Watchdog Reset Timing Watchdog reset is generated internally and therefore has no external pin dependencies. The SYS_EN and PWR_EN power signals de-assert and the nRESET_OUT pin asserts during watchdog reset. The timing is similar to that for power-on reset -- see Figure 23 for details. 6.2.4 GPIO Reset Timing GPIO reset is generated externally, and the reset GPIO source is reconfigured as a standard GPIO as soon as the reset propagates internally. The clocks module is not reset by GPIO reset, so the reset timing varies based on the selected clock frequency. Since GPIO assertions are ignored during a frequency change sequence, if GPIO<1> is asserted during a frequency change sequence, it must remain asserted low for 240 ns after the frequency change completes for the GPIO reset to be Doc. No. MV-S104690-00 Rev. D Page 84 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 recognized. Figure 25 shows the timing of GPIO reset, and Table 28 shows the GPIO reset timing specifications. Note When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is not asserted during GPIO reset. For register details, see the "Clocks and Power Manager" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual. Note Figure 25: GPIO Reset Timing tA_GPIO<1> GP[1] nRESET_OUT tDHW_OUT nCS0 tDHW_OUT_A tCS0 Table 28: GPIO Reset Timing Specifications Symbol D e s c r ip ti o n Min Ty p i c a l Max U n i ts Notes tA_GPIO<1> Minimum assert time of GPIO<1> in 13.000-MHz input clock cycles 4 -- -- cycles 1, 2, 4 tDHW_OUT_A Delay between GPIO<1> asserted and nRESET_OUT asserted in 13.000-MHz input clock cycles 6 -- 8 cycles 4 tDHW_OUT Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, run or turbo mode 230 -- -- nsec Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Symbol D e s c r ip ti o n Min Ty p i c a l Max U n i ts Notes tDHW_OUT_F Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, during frequency change sequence 5 -- 380 s 3 tCS0 Delay between nRESET_OUT de-assertion and nCS0 assertion 1000 -- -- ns 5 NOTES: 1. GPIO<1> is not recognized as a reset source again until configured to do so in software. Software must check the state of GPIO<1> before configuring as a reset to ensure that no spurious reset is generated. For details, see the "Clocks and Power Manager" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual. 2. If GPIO<1> reset is asserted during a frequency change sequence, the minimum assert time of GPIO<1> needs to be 512*N processor clock cycles plus up to 4 cycles of the 13.000-MHz input clock cycles for the reset to be recognized. 3. Time during the frequency-change sequence depends on the state of the PLL lock detector at the assertion of GPIO reset. The lock detector has a maximum time of 350 s plus synchronization. 4. In standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power mode. 5. The tCS0 specification is also applicable to Power-On reset, Hardware reset, Watchdog reset and Deep-Sleep/Sleep mode exit. 6.2.5 Sleep Mode Timing Sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals. Figure 26 and Table 29 show the required timing parameters for sleep mode. Note When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is not asserted during sleep mode. See the "Clocks and Power Manager" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register details. Note Figure 26: Sleep Mode Timing I PXA27x State: SLEEP (ENTRY) SLEEP SLEEP (EXIT) NORMAL Texit Wakeup Event SYS_EN VCC_USB, VCC_IO, VCC_BB,VCC_MEM, VCC_LCD, VCC_USIM PWR_EN (High) (Enabled) VCC_CORE, VCC_SRAM, VCC_PLL Tentry Tpwrdelay nVDD_FAULT nRESET_OUT Doc. No. MV-S104690-00 Rev. D Page 86 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 29: Sleep-Mode Timing Specifications Symbol Description Min Ty p i c a l Max3 U n its 1 tentry5 Delay between MCR sleep command issue to de-assertion of PWR_EN 0.56 -- 2.5 texit Delay between wakeup event and run mode 0.50 -- 136.652,4 msec tpwrdelay Delay between assertion of PWR_EN to PLL enable2 0 -- 125 msec msec NOTES: 1. -1mS if not using DC2DC and -0.94mS if any internal SRAM banks are not powered 2. 0.15ms less time if exiting from sleep mode to 13M mode 3. Add 0.1ms if the wake up event is external 4. Oscillator start/crystal stable times are programmable (300uS-11mS) NOTE: 5ms is user programmable using the OSCC[OSD] bit. The remaining 6ms is an internal timer which counts until the oscillator is stable. (Typical stabilization is 500s. Maximum can be upto 5ms) 5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode 6.2.6 Deep-Sleep Mode Timing Deep-sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals. Figure 27 and Table 30 show the required timing parameters for sleep mode. The timing specifications listed are for software-invoked (not battery or VDD fault) deep-sleep entry, unless specified. Figure 27: Deep-Sleep-Mode Timing I PXA27x State: DEEP SLEEP (ENTRY) Wakeup Event DEEP SLEEP Tdexit Tenable SYS_EN VCC_USB, VCC_IO, VCC_BB, VCC_MEM, VCC_LCD, VCC_USIM PWR_EN NORMAL DEEP SLEEP (EXIT) Tdsys_delay Tdentry Tdpwr_delay VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT Deep-Sleep Command Table 30: Deep-Sleep Mode Timing Specifications (Sheet 1 of 2) Symbol Min Ty p i c a l Max3 U n its msec tdentry5 Delay between deep-sleep command issue to de-assertion of SYS_EN 0.66 -- 1.661 tenable Delay between de-assertion of PWR_EN and SYS_EN -- 30 -- usec tdexit Delay between wakeup event and run mode 0.60 -- 261.752,4 msec Copyright (c) 4/3/09 Marvell April 2009 Released Description Doc. No. MV-S104690-00 Rev. D Page 87 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 30: Deep-Sleep Mode Timing Specifications (Sheet 2 of 2) Symbol Description Min Ty p i c a l Max3 U n its tdsysdelay Delay between assertion of SYS_EN to PWR_EN2 0 -- 125 msec tdpwrdelay Delay between assertion of PWR_EN to PLL enable2 0 -- 125 msec NOTE: Timing specifications for nBATT_FAULT and/or nVDD_FAULT asserted deep-sleep mode entry are below: Fault assert Delay between nBATT_FAULT or nVDD_FAULT assertion (during all modes of operation including sleep mode) and deep-sleep mode entry6(The de-assertion of SYS_EN defines when the processor is in deep-sleep mode) 0.33 -- 1.56 msec NOTES: 1. -1ms if not using DC2DC 2. 0.15ms less time if exiting from deep-sleep mode to 13M mode 3. Add 0.1ms if the wake up event is external 4. Oscillator start/crystal stable times are programmable (300uS-11mS) NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which counts until the oscillator is stable. (Typical stabilization is 500s. Maximum can be upto 5ms) 5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode 6. Assumes PMCR[BIDAE or VIDAE] bits are set to zero (default state) - The PMCR[BIDAE or VIDAE] bits are only read by the processor if nBATT_FAULT or nVDD_FAULT signals are asserted 6.2.7 GPIO states in Deep-Sleep mode If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto all the GPIO pins (that are configured as outputs) for a finite time period, then the pins default to the reset state (Pu/Pd) as described in Chapter 2 of this manual. This sequence occurs for either software-initiated or fault-initiated deep-sleep entry. Note Note GPIOs<0,1,3,4,9,10> never float. They are powered from VCC_BATT so when the system and the core power domains are removed (controlled by SYS_EN and PWR_EN), the Pu/Pd resistors remain enabled due to VCC_BATT remaining on. The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states is system dependant because the processor is performing an unpredictable workload and requires an unknown amount of time to complete current processes. Refer to the deep-sleep mode, "Clocks and Power" section of the Marvell(R) PXA27x Processor Family Developers Manual for a description on deep-sleep mode entry sequence. Table 31 shows the time period that the GPIO pullup/pulldowns are enabled. Listed below are the regulators and converter naming conventions: L1 = Sleep/Deep-Sleep Linear Regulator L2 = High-Current Linear Regulator Doc. No. MV-S104690-00 Rev. D Page 88 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 DC2DC = Sleep/Deep-Sleep DC-DC Converter Table 31: GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode Description L2 L1 DC2DC U n i ts Duration of the GPIO Pu/Pd states being enabled and the de-assertion of PWR_EN 0.1 0.13 1.13 msec Note Note Copyright (c) 4/3/09 Marvell April 2009 Released If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USB, VCC_USIM) are powered off during deep-sleep mode, the GPIOs behave the same as described above; however, they float after the supplies are removed. Doc. No. MV-S104690-00 Rev. D Page 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification 6.2.8 Standby-Mode Timing Table 32: Standby-Mode Timing Specifications Symbol Description -- 13M mode to standby mode entry -- Standby mode exit to 13M mode 1 -- -- Min Ty p i c a l Max -- 0.34 -- U n its msec 2 0.28 -- 11.28 msec Run mode to standby mode entry -- 0.34 -- msec Standby mode exit to run mode1 0.43 -- 11.432 msec NOTES: 1. The 13M oscillator is programmable 2. Add 0.1ms if the wake up event is external 6.2.9 Idle-Mode Timing Table 33: Idle-Mode Timing Specifications 6.2.10 Symbol D e s c r i p t io n M in Ty p i c a l Max U n i ts -- 13M mode to deep idle mode entry -- 1 -- s -- Deep idle mode exit to 13M mode -- 1 -- s -- Run mode to idle run mode entry -- 1 -- s -- Idle run mode exit to run mode -- 1 -- s Min Ty p i c a l Max U n i ts -- s Frequency-Change Timing Table 34: Frequency-Change Timing Specifications Symbol D e s c ri p t i o n -- Delay between MCR command to frequency change sequence completion -- 1501 -- Delay to change between turbo, half-turbo and run modes -- 12 -- s -- Delay to enter 13M mode from any Run mode 3 -- 1 -- s -- Delay to exit 13M mode to any Run mode -- 24 -- s NOTES: 1. Any change to the CCCR[2N or L] bits followed by a write to CLFCFG[F] to initiate a frequency change sequence, results in a PLL restart 2. Changing between turbo, half-turbo and run modes does not require a PLL restart 3. Software can only change into 13M mode from any run mode 4. Assuming software uses the PLL early enable feature (CCCR[PLL_EARLY_EN] prior to a frequency change sequence 6.2.11 Voltage-Change Timing The PWR I2C uses the regular I2C protocol. The PWR I2C is clocked at 40 kHz (160 kHz fast-mode operation is supported). Software controls the time required for initiating the voltage change sequence through completion. The voltage-change timing is a product of the number of commands Doc. No. MV-S104690-00 Rev. D Page 90 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 issued plus the number of software-programmed delays. Table 35 shows the timing of a 1 byte command issued to the power manager IC. Set the I2C programmable output ramp rate with a default/reset ramp rate of 10mV/s (refer to VCC_CORE ramp rate specification in the Electrical Section) to support VCC_CORE dynamic voltage management. Table 35: Voltage-Change Timing Specification for a 1-Byte Command Symbol Description Min Ty p i c a l Max U n its -- Delay between voltage change sequence start1 to command received by PMIC -- 18 -- cycles2 NOTES: 1. Write 1 to PWRMODE[VC] 2. 40 kHz cycles 6.3 GPIO Timing Specifications Table 36 shows the general-purpose I/O (GPIO) AC timing specifications. Table 36: GPIO Timing Specifications Symbol Parameter M in Max U n i ts Notes taGPIO1 Assertion time required to detect GPIO edge 154 -- ns run, idle, or sense power modes taGPIOLP2 Assertion time required to detect GPIO low-power edge 62.5 -- s standby, sleep, or deep-sleep power modes tdGPIO1 De-assertion time required to detect GPIO edge 154 -- ns run, idle, or sense power modes tdGPIOLP2 De-assertion time required to detect GPIO low-power edge 62.5 -- s standby, sleep, or deep-sleep power modes tdiGPIO3 Time required for a GPIO edge to be detected internally 231 -- ns run, idle, or sense power modes tdiGPIOLP Time required for a GPIO lowpower edge to be detected internally 93.75 -- s standby, sleep, or deep-sleep power modes 4 NOTES: 1. Period equal to two 13-MHz cycles 2. Period equal to two 32-kHz cycles 3. Period equal to three 13-MHz cycles 4. Period equal to three 32-kHz cycles Note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally (2 cycles for assertion (note 2) and 1 additional cycle for detection). 6.4 Memory and Expansion-Card Timing Specifications Interfaces with the following memories must observe the AC timing requirements given in the following subsections: Copyright (c) 4/3/09 Marvell April 2009 Released Section 6.4.1, "Internal SRAM Read/Write Timing Specifications" Section 6.4.2, "SDRAM Parameters and Timing Diagrams" Section 6.4.3, "ROM Parameters and Timing Diagrams" Doc. No. MV-S104690-00 Rev. D Page 91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Section 6.4.4, "Flash Memory Parameters and Timing Diagrams" Section 6.4.5, "SRAM Parameters and Timing Diagrams" Section 6.4.6, "Variable-Latency I/O Parameters and Timing Diagrams" Section 6.4.7, "Expansion-Card Interface Parameters and Timing Diagrams" Note The diagrams in this section use the following conventions: Note 6.4.1 Input signals to the processor are represented using dashed waveforms. Outputs and bidirectional signals are represented using solid waveforms. Fixed parameters are shown using double arrows in grey (black and white print) or green (color print). Programmable parameters are shown using bold single arrows. The processor register that is used to change a specific timing is given in the corresponding timing table. Internal SRAM Read/Write Timing Specifications Table 37: SRAM Read/Write AC Specification 6.4.2 Symbols Parameters MIN TYP MAX U n i ts tsramRD 4-beat read transfer -- 9 -- system bus clocks tsramWR 4-beat write transfer -- 7 -- system bus clocks SDRAM Parameters and Timing Diagrams Table 38 shows the timing parameters used in Figure 28. Also see Section 6.4.3 and Figure 32 for additional SDRAM bus tenure information. See Figure 31 for SDRAM fly-by bus tenures. VCC_MEM = 2 . 5 V + /- 1 0 % 4 VCC_MEM = 3 . 3 V + /- 1 0 % 5 U n i ts MIN TYP TYP TYP N o te s VCC_MEM = 1.8V +20% / -5%3 M IN MAX P a ra m e t e r s MAX Symbols MAX Table 38: SDRAM Interface AC Specifications (Sheet 1 of 3) MIN tsdCLK SDCLK1, SDCLK2 period 9.6 -- 76.9 9.6 -- 76.9 9.6 -- 76.9 ns 1, 2 tsdCMD nSDCAS, nSDRAS, nWE, nSDCS assert time 1 -- 1 1 -- 1 1 -- 1 SDCL K -- tsdCAS nSDCAS to nSDCAS assert time 2 -- -- 2 -- -- 2 -- -- SDCL K -- tsdRCD nSDRAS to nSDCAS assert time 1 MDCNF G[DTCx] 3 1 MDCNF G[DTCx] 3 1 MDCNF G[DTCx] 3 SDCL K 6 Doc. No. MV-S104690-00 Rev. D Page 92 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 VCC_MEM = 2 . 5 V + /- 1 0 % 4 VCC_MEM = 3 . 3 V + /- 1 0 % 5 U n i ts MIN TYP TYP TYP Notes VCC_MEM = 1.8V +20% / -5%3 M IN MAX P a ra m e t e r s MAX Symbols MAX Table 38: SDRAM Interface AC Specifications (Sheet 2 of 3) MIN tsdRP nSDRAS Pre charge 2 MDCNF G[DTCx] 3 2 MDCNF G[DTCx] 3 2 MDCNF G[DTCx] 3 SDCL K 6 tsdCL CAS Latency 2 MDCNF G[DTCx] 3 2 MDCNF G[DTCx] 3 2 MDCNF G[DTCx] 3 SDCL K 6 tsdRAS nSDRAS active time 3 MDCNF G[DTCx] 7 3 MDCNF G[DTCx] 7 3 MDCNF G[DTCx] 7 SDCL K 6 tsdRC nSDRAS cycle time 4 MDCNF G[DTCx] 11 4 MDCNF G[DTCx] 11 4 MDCNF G[DTCx] 11 SDCL K 6 tsdWR write recovery time (time from last data in the PRECHARGE) 2 -- 2 2 -- 2 2 -- 2 SDCL K -- tsdSDOS MA<24:10>, MD<31:0>, DQM<3:0>, nSDCS<3:0>, nSDRAS, nSDCAS, nWE, nOE, SDCKE1, RDnWR output setup time to SDCLK<2:1> rise 2.5 -- -- 2.5 -- 2.5 -- -- ns -- tsdSDOH MA<24:10>, MD<31:0>, DQM<3:0>, nSDCS<3:0>, nSDRAS, nSDCAS, nWE, nOE, SDCKE1, RDnWR output hold time from SDCLK<2:1> rise 1.5 -- -- 1.5 -- 1.5 -- -- ns -- VCC_CORE = 0.85 V +/- 10%, with 1.71 V<= VCC_MEM <= 3.63 V Copyright (c) 4/3/09 Marvell April 2009 Released VCC_CORE = 1.1 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V VCC_CORE = 1.3 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V Doc. No. MV-S104690-00 Rev. D Page 93 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification VCC_MEM = 2 . 5 V + /- 1 0 % 4 VCC_MEM = 3 . 3 V + /- 1 0 % 5 U n i ts MIN TYP TYP TYP Notes VCC_MEM = 1.8V +20% / -5%3 M IN MAX P a ra m e t e r s MAX Symbols MAX Table 38: SDRAM Interface AC Specifications (Sheet 3 of 3) MIN tsdSDIS MD<31:0> read data input setup time from SDCLK<2:1> rise 3.0 -- -- 3.0 -- -- 0.5 -- -- ns -- tsdSDIH MD<31:0> read data input hold time from SDCLK<2:1> rise 2.0 -- -- 2.0 -- -- 1.8 -- -- ns -- NOTES: 1. SDCLK for SDRAM slowest period is accomplished by divide-by-2 of the 26-MHz CLK_MEM. The fastest possible SDCLK is accomplished by configuring CLK_MEM at 104 MHz and not setting MDREFR[KxDB2]. 2. SDCLK1 and SDCLK2 frequencies are configured to be CLK_MEM frequency divided by 1 or 2, depending on the bit fields MDREFR[K1DB2] and MDREFR[K2DB2] settings. 3. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK<2:1> divide-by-2 and divide-by-4 register bits MDREFR[KxDB2] clear. 4. These numbers are for VCC_MEM = 2.5 V +/- 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-by-2 and divide-by-4 register bit MDREFR[KxDB2] clear. 5. These numbers are for VCC_MEM = 3.3 V +/- 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-by-2 and divide-by-4 register bit MDREFR[KxDB2] clear. 6. Refer to the "Memory Controller" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register configuration. Doc. No. MV-S104690-00 Rev. D Page 94 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 28: SDRAM Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 tsdCLK SDCLK<1> SDCKE<1> tsdRC tsdCL tsdRP tsdCMD tsdCMD command nop act nop read nop pre nop act nop write nop pre nop nSDCS<0> tsdRAS nSDRAS tsdRCD nSDCAS nWE tsdSDIS tsdIH MD<31:0> read tsdSDOS tsdSDOH tWR MD<31:0> write DQM<3:0> 0b0000 0 1 2 3 mask data values RDnWR Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 95 PXA270 Processor Electrical, Mechanical, and Thermal Specification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 29: SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing SDCLK<1> SDCKE<1> command read(0) pre(1) nop act(1) nop write(1) nop nSDCS<0> nSDCS<1> nSDRAS nSDCAS MA<24:10> col bank row col nWE MD<31:0> (read) rd0_0 wd1_0 wd1_1 wd1_2 wd1_3 MD<31:0> (write) DQM<3:0> rd0_1 rd0_2 rd0_3 0b0000 0 1 2 3 mask data bytes RDnWR NOTES: 1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk), MDCNFG[STACK] = 0b00 2. See the SDRAM timing diagram. Doc. No. MV-S104690-00 Rev. D Page 96 Copyright (c) 4/3/09 Marvell April 2009 Released Figure 30: SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 SDCLK<1> SDCKE<1> command nop write(0) nop write(0) nop nSDCS<0> nSDRAS nSDCAS MA<24:10> col col nWE MD<31:0> wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 wd0_7 DQM<3:0> mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 mask data bytes RDnWR NOTES: 1. MDCNFG[DTC] = 0b01 (CL = 2, tRP = 2 clks) 2. See the SDRAM timing diagram. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 97 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 31: SDRAM Fly-by DMA Timing latch data rd3 latch data rd2 latch data rd1 latch data rd0 SDCLK<1> latch DVAL[1] asserted drive data wd0 drive data wd1 drive data wd2 drive data wd3 SDCLK<2> SDCKE<1> command read pre col bank nop act nop write nop nSDCS<0> nSDCS<2> nSDRAS nSDCAS MA<24:10> row col nWE rd0 MD<31:0> rd1 rd2 rd3 0b0000 DQM<3:0> wd0 wd1 wd2 wd3 mask0 mask1 mask2 mask3 mask data bytes RDnWR DVAL<0> DVAL<1> Latch data on rising edge of SDCLK<1> when DVAL<0> is asserted. Using DVAL<1> driven two clocks early, drive data on rising edge of SDCLK<2>. NOTES: 1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk) 2. See the SDRAM timing diagram. 6.4.3 ROM Parameters and Timing Diagrams Table 39 lists the timings for ROM reads. See Figure 32, Figure 33, Figure 34, and Figure 35 for timings diagrams representing burst and non-burst ROM reads. Note Note Doc. No. MV-S104690-00 Rev. D Page 98 Table 39 lists programmable register items. See the "Memory Controller" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 39: ROM AC Specification S y m b o ls Parameters MIN TYP MAX U n i ts Notes tromAS Address setup to nCS assert 1 -- 1 clk_mem -- tromCES nCS setup to nOE asserted -- -- 0 clk_mem -- tromCEH nCS hold from nOE de-asserted -- -- 0 clk_mem -- tromDSOH MD setup to address valid 1.5 -- -- clk_mem -- tromDOH MD hold from address valid 0 -- -- clk_mem -- tromAVDVF Address valid to data latched for the first read access 2 MSCx[RDF]+2 32 clk_mem -- tromAVDVS Address valid to data latched for subsequent reads of non-burst devices 1 MSCx[RDF]+1 31 clk_mem -- tflashAVDVS Address valid to data valid for subsequent reads of burst devices 1 MSCx[RDN]+1 31 clk_mem -- tromCD nCS de-asserted after a read of next nCS or nSDCS asserted (minimum) 1 MSCx[RRR]*2+ 1 15 clk_mem -- Numbers shown as integer multiples of the clk_mem period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). For more information, refer to the "Memory Control" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 32: 32-Bit Non-burst ROM, SRAM, or Flash Read Timing CLK_MEM tromAS nCS<0> tromAVDLS tromAVDLS MA<25:2> 0 tromAVDLS tromAVDLF 1 2 3 0b00 MA<1:0>(SA1110x='0') 0b00 / 0b01 / 0b10 / 0b11 MA<1:0>(SA1110x='1') nADV(nSDCAS) tromCES tromCEH nOE nWE RDnWR tromDOH tromDSOH tromDOH tromDSOH tromDOH tromDSOH tromDOH tromDSOH MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') 0b00 corresponding mask value tromCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RRR0] = 1 Doc. No. MV-S104690-00 Rev. D Page 100 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 33: 32-Bit Burst-of-Eight ROM or Flash Read Timing CLK_MEM nCS<0> tAS MA<25:5> MA<4:2> 0 tromAVDLF tromAVDLS 1 2 3 4 5 6 7 0b00 MA<1:0>(SA1110x='0') 0b00 / 0b01 / 0b10 / 0b11 MA<1:0>(SA1110x='1') nADV(nSDCAS) tCES tCEH nOE nWE RDnWR tDOH tDSOH MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') 0b0000 corresponding mask value tromCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 1 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 34: Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing CLK_MEM nCS<0> tromAS address MA<25:4> MA<3> tromAVDLF tromAVDLS tromAVDLF MA<2:1> 0 1 2 3 tromAVDLS 0 MA<0>(SA1110x='0') 0b0 MA<0>(SA1110x='1') 0b0 / 0b1 1 2 3 nADV(nSDCAS) tromCES tromCEH nOE nWE RDnWR tromDOH tromDSOH tromDOH tromDSOH MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') 0b00 0b00 or 0b10/0b01 tromCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 0 Doc. No. MV-S104690-00 Rev. D Page 102 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 35: 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing CLK_MEM tromCD tromCD tromCD nCS<0> tromAS addr addr + 1 tromAS addr MA<0>(SA1110x='0') 0 MA<0>(SA1110x='1') 0/1 MA<25:1> tromAS addr tromAS addr addr + 1 0 0 0 0/1 0/1 0/1 nADV(nSDCAS) tromAVDLF tflashAVDVS tromAVDLS tromCES tromCEH tromAVDLF tromCES tromAVDLF tromCES tromAVDLF tromCES nOE nWE RDnWR tromDSOH tromDOH tromDSOH tromDOH tromDOH tromDOH tromDSOH tromDOH tromDSOH tromDOH tromDSOH tromDSOH MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') 0b00 mask 32-bit read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 0b00 mask 0b00 mask 0b00 mask 16-bit read 8-bit read 32-bit Read Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 16-bit burst flash Applies to: 16-bit ROM or non-burst flash 16-bit SRAM 16-bit burst flash Applies to: 16-bit Burst Flash NOTE: MSC0[RDF0] = 2, MSC0[RDN0] = 1, MSC0[RRR0] = 1 6.4.4 Flash Memory Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for asynchronous and synchronous flash-memory interfaces with the memory controller. 6.4.4.1 Flash Memory Read Parameters and Timing Diagrams Section 6.4.4.2 describes asynchronous flash reads. Section 6.4.4.3 describes synchronous flash reads. 6.4.4.2 Asynchronous Flash Read Parameters and Timing Diagrams The timings listed in Table 39 for ROM reads also apply to asynchronous flash reads. See Figure 32, Figure 33, Figure 34, and Figure 35 for timings diagrams representative of an asynchronous flash read. 6.4.4.3 Synchronous Flash Read Parameters and Timing Diagrams Table 40 lists the timing parameters used in Figure 36, and, for stacked flash packages, Figure 37. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Divide by 12 Divide by 23 Notes U n i ts MAX TYP MIN MAX TYP MIN MAX TYP MIN P a r a m e te r s Symbols Table 40: Synchronous Flash Read AC Specifications (Sheet 1 of 2) Divide by 44 tffCLK SDCLK0 period 9.6 -- 38.5 19. 2 -- 76.9 38.5 -- 154 ns 1 tffAS MA<25:0> setup to nSDCAS (as nADV) asserted 1 -- 1 1 -- 2 1 -- 4 CLK_MEM -- tffCES nCS setup to nSDCAS (as nADV) asserted 1 -- 1 1 -- 2 1 -- 4 CLK_MEM -- tffADV nSDCAS (as nADV) pulse width 1 -- 1 3 -- 3 7 -- 7 CLK_MEM -- 52 CLK_MEM 5 FCC - 1 (for FCC<5) nSDCAS (as nADV) de-assertion to nOE assertion 1 tffCEH nOE de-assertion to nCS de-assertion 4 tffDS CLK to data valid 2 tffOS 13 2 -- 4 8 FCC 15 2 FCC - 2 (for FCC>=5) VCC_MEM = 1.8V +20% / -5%6 (FCC - 1) *2 (for FCC<5) (FCC * 4) -7 (for FCC<5) 26 7 -- 8 16 -- 16 CLK_MEM -- FCC 15 2 FCC 15 CLK_MEM 5 (FCC - 2) *2 (for FCC>=5) VCC_MEM = 2.5V +/- 10%7 (FCC - 2) *4 (for FCC>=5) VCC_MEM = 3.3V +/- 10%8 tffSDOS MA<25:0>, MD<31:0>, DQM<3:0>, nCS<3:0>, nSDCAS (nADV), nWE, nOE, RDnWR output setup time to SDCLK0 rise 8 -- -- 8 -- -- 8 -- -- ns -- tffSDOH MD<31:0>, DQM<3:0>, nCS<3:0>, nSDCAS (nADV), nWE, nOE, RDnWR output hold time from SDCLK0 rise 4.5 -- -- 4.5 -- -- 4.5 -- -- ns -- Doc. No. MV-S104690-00 Rev. D Page 104 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Notes 2.2 -- -- ns -- tffSDIH MD<31:0> read data input hold time from SDCLK0 rise 2.9 -- -- 2.9 -- -- 2.9 -- -- ns -- MAX -- VCC_CORE = 1.1 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V TYP -- VCC_CORE = 0.85 V +/- 10%, with 1.71 V<= VCC_MEM <= 3.63 V MIN 2.2 MAX -- TYP -- MIN 2.2 MAX MD<31:0> read data input setup time from SDCLK0 rise TYP tffSDIS MIN U n i ts P a r a m e te r s Symbols Table 40: Synchronous Flash Read AC Specifications (Sheet 2 of 2) VCC_CORE = 1.3 V +/- 10%, with 1.71 V <= VCC_MEM <= 3.63 V NOTES: 1. SDCLK0 may be configured to be CLK_MEM divided by 1, 2 or 4. SDCLK0 for synchronous flash memory can be at the slowest, divide-by-4 of the 26-MHz CLK_MEM. The fastest possible SDCLK0 is accomplished by configuring CLK_MEM at 104 MHz and clearing the MDREFR[K0DB2] or MDREFR[K0DB4] bit fields. 2. SDCLK0 frequency equals CLK_MEM frequency (MDREFR[K0DB4] and MDREFR[K0DB2] bit fields are clear) 3. SDCLK0 frequency equals CLK_MEM/2 frequency (MDREFR[K0DB2] is set and MDREFR[K0DB4] is clear). 4. SDCLK0 frequency equals CLK_MEM/4 frequency (MDREFR[K0DB4] is set). 5. Use SXCNFG[SXCLx] to configure the value for the frequency configuration code (FCC). 6. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCN TRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK0 divide-by-2 and divide-by-4 register bits (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. 7. These numbers are for VCC_MEM = 2.5 V +/- 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2 and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. 8. These numbers are for VCC_MEM = 3.3 V +/- 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2 and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 36: Synchronous Flash Burst-of-Eight Read Timing CLK_MEM SDCLK<0> MA<19:2> 0b00 MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) 0b00/0b01/0b10/0b11 nCS<0> CODE CODE+1 nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 0b0000 corresponding mask value NOTES: 1) SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4) 2) CODE = frequency configuration code Doc. No. MV-S104690-00 Rev. D Page 106 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 37: Synchronous Flash Stacked Burst-of-Eight Read Timing CLK_MEM SDCLK<3> MA<19:2> 0b00 MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) 0b00/0b01/0b10/0b11 nCS<0> CODE CODE+1 nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 0b0000 corresponding mask value NOTE: SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4) SA1110CR[SXSTACK] = 0b01 Figure 38 indicates which clock data would be latched following the assertion of nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the number of SDCLK0 cycles between the READ command and the clock edge on which data is driven onto the bus. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 107 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 38: First-Access Latency Configuration Timing SDCLK<0> nCS<0> Valid Address MA<19:0> nSDCAS 0b0000 DQM<3:0> Code 2 Beat 0 MD (Code = 2) Beat 1 Beat 2 Beat 3 Beat 4 Beat 5 Beat 0 Beat 1 Beat 2 Beat 3 Beat 4 Beat 1 Beat 2 Beat 3 Beat 0 Beat 1 Beat 2 Beat 0 Beat 1 Code 3 MD (Code = 3) Code 4 Beat 0 MD (Code = 4) Code 5 MD (Code = 5) Code 6 MD (Code = 6) Code 7 Beat 0 MD (Code = 7) NOTE: CODE = Frequency Configuration Code The burst read example shown in Figure 39 represents waveforms that result when SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to 3. The following example can help determine the appropriate setting for SXCNFG[SXCLx]. Parameters defined by the processor: tffSDOH (max) = SDCLK<0> to CE# (nCE), ADV# (nADV), or address valid, whichever occurs last tffSDIS (min) = Data setup to SDCLK<0> Parameters defined by flash memory: tVLQV (min) = ADV# low to output delay tVLCH (min) = ADV# low to clock tCHQV (max) = SDCLK<0> to output valid Use the following equations when calculating the frequency configuration code: (1) SDCLK period = (1 / frequency) (2) n (SDCLK period) Doc. No. MV-S104690-00 Rev. D Page 108 tVLQV - tVLCH - tCHQV Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 (3) n = (tVLQV - tVLCH - tCHQV) / SDCLK period, where n = frequency configuration code rounded up to integer value (4) SDCLK period tCHQV + tffSDIS Example The timing information below is only an example. See Table 40 for actual synchronous AC timings. SDCLK<0> frequency = 50 MHz tVLQV = 70 ns (typical timing from synchronous flash memory) tVLCH = 10 ns (min) tCHQV = 14 ns (min) From Eq.(1):1 / 50 (MHz) = 20 ns From Eq.(2):n(20 ns) n(20 ns) 46 70 ns - 10 ns - 14 ns ns n = (46 / 20) ns = 2.3 ns n = 3 Use Equation 4 to help verify the maximum possible frequency at which the synchronous flash memory can run with the memory controller. The following example uses Equation 4: SDCLK<0> frequency = 66 MHz tCHQV = 11 ns (max) tffSDIS = 3 ns (min) From Eq. (1):1 / 66 (MHz) = 15.15 ns From Eq. (4):15.15 ns 15.15 ns 11 ns + 3 ns 14 ns The results from this example indicate that the 66-MHz memory works without problems with the memory controller. Note Note Copyright (c) 4/3/09 Marvell April 2009 Released All AC timings must be considered to avoid timing violations in the memory-to-memory-controller interface. Doc. No. MV-S104690-00 Rev. D Page 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 39: Synchronous Flash Burst Read Example SDCLK<0> tffSDOH nCS<0> tAVCH tffSDOH nSDCAS (ADV#) tffSDOH Valid Address MA tffSDIS tCHQV tVLQV Beat 0 MD 6.4.4.4 Beat1 Flash Memory Write Parameters and Timing Diagrams Table 41 lists the AC specification for both burst and non-burst flash writes shown in Figure 40 and, for stacked flash packages, Figure 41. Table 41: Flash Memory AC Specification (Sheet 1 of 2) S y m b o ls P a r a m e te rs MIN TYP MAX U n i ts 1 No te s tflashAS Address setup to nCS assert 1 -- 1 clk_mem -- tflashAH Address hold from nWE de-asserted 1 -- 1 clk_mem -- tflashASW Address setup to nWE asserted 1 -- 3 clk_mem 2 tflashCES nCS setup to nWE asserted 2 -- 2 clk_mem -- tflashCEH nCS hold from nWE de-asserted 1 -- 1 clk_mem -- tflashWL nWE asserted time 1 MSCx[RDF]+1 31 clk_mem -- tflashDSWH MD/DQM setup to nWE de-asserted 2 MSCx[RDF]+2 32 clk_mem -- tflashDH MD/DQM hold from nWE de-asserted 1 -- 1 clk_mem -- tflashDSOH MD setup to address valid 1.5 -- -- clk_mem -- Doc. No. MV-S104690-00 Rev. D Page 110 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 41: Flash Memory AC Specification (Sheet 2 of 2) S y m b o ls P a r a m e te rs MIN TYP MAX U n i ts 1 No te s tflashDOH MD hold from address valid 0 -- -- clk_mem -- tflashCD nCS de-asserted after a read/write to next nCS or nSDCS asserted (minimum) 1 MSCx[RRR]*2 +1 15 clk_mem -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. On the first data beat of burst transfer, the tflashASW is 3 CLK_MEM periods. On subsequent data beats, the tflashASW is 1 CLK_MEM period. Figure 40: 32-Bit Flash Write Timing CLK_MEM tflashCD nCS<0> MA<25:2> tflashAS command address tflashAS data address 0b00 0b00 MA<1:0> tflashASW tflashASW tflashCEH tflashCEH tflashCES tflashCES tflashAH tflashWL tflashAH tflashWL tflashDH tflashDSWH tflashDH tflashDSWH nWE nOE RDnWR MD<31:0> CMD DATA DQM<3:0> 0b0000 0b0000 nADV(nSDCAS) tflashCD nCSx or nSDCSx First Bus Cycle Second Bus Cycle NOTE: MSC0[RDF0] = 2, MSC0[RRR0] = 2 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 41: 32-Bit Stacked Flash Write Timing CLK_MEM tflashCD nWE MA<25:2> tflashAS command address tflashAS data address 0b00 MA<1:0> 0b00 tflashASW tflashASW tflashCEH tflashCEH tflashCES tflashCES tflashAH tflashWL tflashAH tflashWL tflashDH tflashDSWH tflashDH tflashDSWH nCS<0> or nCS<1> nOE RDnWR MD<31:0> CMD DATA DQM<3:0> 0b0000 0b0000 nADV(nSDCAS) tflashCD nCSx First Bus Cycle Second Bus Cycle * MSC0[RDF0] = 2, MSC0[RRR0] = 2, SA1110{SXSTACK] = 00 Doc. No. MV-S104690-00 Rev. D Page 112 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 42: 16-Bit Flash Write Timing CLK_MEM nCS<2> tflashAS MA<25:1> addr MA<0> 0b0 tflashCEH tflashCES tflashWL nWE nOE RDnWR tflashDH tflashDSWH MD<15:0> Bytes 1:0 DQM<1:0> 0b00 nADV(nSDCAS) tflashCD nCSx or nSDCSx Applies to: 16-bit Non-Burst Flash 16-bit Burst Flash NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2 6.4.5 SRAM Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for SRAM interfaces with the memory controller. 6.4.5.1 SRAM Read Parameters and Timing Diagrams The timing for a read access is identical to that for a non-burst ROM read (see Figure 32). The timings listed in Table 39 for ROM reads are also used for SRAM reads. See Figure 32 and Figure 35 for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s) during read-bus tenures. 6.4.5.2 SRAM Write Parameters and Timing Diagrams Figure 43 and Figure 44 show the timing for 32-bit and 16-bit SRAM writes. Table 42 lists the timings used in Figure 43 and Figure 44. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification During writes, data pins are actively driven by the processor and are not three-stated, regardless of the states of the individual DQM signals. For SRAM writes, the DQM signals are used as byte enables. Note Note Table 42 lists programmable register items. See the "Memory Controller"chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Table 42: SRAM Write AC Specification S y m b o ls P a r a m e te rs MIN TYP MAX U n i ts 1 No te s tsramAS Address setup to nCS assert 1 -- 1 clk_mem -- tsramAH Address hold from nWE de-asserted 1 -- 1 clk_mem -- tsramASW Address setup to nWE asserted 1 -- 3 clk_mem 2 tsramCES nCS setup to nWE asserted 2 -- 2 clk_mem -- tsramCEH nCS hold from nWE de-asserted 1 -- 1 clk_mem -- tsramWL nWE asserted time 1 MSCx[RDN]+1 31 clk_mem -- tsramDSWH MD/DQM setup to nWE de-asserted 2 MSCx[RDN]+2 32 clk_mem -- tsramDH MD/DQM hold from nWE de-asserted 1 -- 1 clk_mem -- tramCD nCS de-asserted after a read to next nCS or nSDCS asserted (minimum) 1 MSCx[RRR]*2+1 15 clk_mem -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. On the first data beat of burst transfer, the tsramASW is 3 CLK_MEM periods. On subsequent data beats, the tsramASW is 1 CLK_MEM period. Doc. No. MV-S104690-00 Rev. D Page 114 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 43: 32-Bit SRAM Write Timing CLK_MEM nCS<0> MA<25:2> MA<1:0> tsramAS 0 byte addr 1 2 3 byte addr byte addr byte addr tsramASW tsramCEHW tsramCESW tsramASW tsramAH tsramWL tsramWL tsramAH tsramWL tsramWL nWE nOE RDnWR tsramDH tsramDSWH tsramDOH D1 MD<31:0> D0 DQM<3:0> mask0 mask1 D2 D3 mask2 mask3 tsramCD nCSx or nSDCSx nADV(nSDCAS) NOTE: 4-Beat burst, MSC0[RDN0] = 2, MSC0[RRR0] = 1 Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 115 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 44: 16-bit SRAM Write for 4/2/1 Byte(s) Timing CLK_MEM tsramCD tsramCD nCS<2> tramAS addr MA<25:1> '0' MA<0> tramAS addr addr+1 '0' tramAS addr '0' tsramWL tsramASW tsramAH tsramCES tsramCEH tsramWL tsramWL '0' or '1' tsramCEH tsramCES tsramCEH tsramCES tsramWL tsramWL nWE nOE RDnWR tsramDH tsramDH tsramDH tsramDSWH tsramDH tsramDSWH MD<15:0> tsramDSWH Bytes 1:0 Bytes 3:2 Bytes 1:0 Byte 0 OR 1 tsramDSWH DQM<1:0> 0b00 0b00 0b01 / 0b10 nADV(nSDCAS) tsramCD nCSx or nSDCSx 32-bit Write 16-bit Write 8-bit Write NOTE: MSC1[RDF2]=1, MSC1[RDN]=2, MSC1[RRR2]=2 6.4.6 Variable-Latency I/O Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for VLIO memory interfaces with the memory controller. Table 43 lists the timing-information references for both the read and the write timing diagrams. Note Note Doc. No. MV-S104690-00 Rev. D Page 116 Table 43 lists programmable register items. For more information on these items, see the "Memory Controller" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register configurations. Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Table 43: VLIO Timing S y m b o ls P a r a m e te rs MIN TYP MAX2 U n i ts 1 No te s tvlioAS Address setup to nCS asserted 1 -- 1 clk_mem -- tvlioAH Address hold from nPWE/nOE de-asserted 2 MSCx[RDN] 30 clk_mem -- tvlioASRW0 Address setup to nPWE/nOE asserted (1st access) 3 -- 3 clk_mem -- tvlioASRWn Address setup to nPWE/nOE asserted (next access(es)) 2 MSCx[RDN] 30 clk_mem -- tvlioCES nCS setup to nPWE/nOE asserted 2 -- 2 clk_mem -- tvlioCEH nCS hold from nPWE/nOE de-asserted 1 -- 1 clk_mem -- tvlioDSWH MD/DQM setup (minimum) to nPWE de-asserted 5 MSCx[RDF]+2 32 clk_mem -- tvlioDH MD/DQM hold from nPWE de-asserted 2 MSCx[RDN] 30 clk_mem -- tvlioDSOH MD setup to address changing 1.5 -- clk_mem -- tvlioDOH MD hold from address changing 0 -- ns -- tvlioRDYH RDY hold from nPWE/nOE de-asserted 0 -- -- ns -- tvlioRWA nPWE/nOE assert period between writes 4 MSC[RDF]+1 + Waits 31 + Waits clk_mem -- tvlioRWD nPWE/nOE de-asserted period between writes 4 MSCx[RDN*2] 60 clk_mem 3 tvlioCD nCS de-asserted after a read/write to next nCS or nSDCS asserted (minimum) 1 MSCx[RRR]*2 +1 15 clk_mem -- NOTES: 1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. Maximum values reflect the register dynamic ranges. 3. Depending on the programmed value of MSC[RDN] and the clk_mem speed, this can be a significant amount of time. Processor does not drive the data bus during this time between transfers. If the VLIO does not drive the data bus during this time between transfers, the data bus is not driven for this period of time. If MSC[RDN] is programmed to 60 (which equals 60 CLK_MEM cycles), then the data bus could potentially not be driven for 30*2 = 60 CLK_MEM cycles. 6.4.6.1 Variable Latency I/O Read Timing Figure 45 shows the timing for 32-bit variable-latency I/O (VLIO) memory reads. Table 43 lists the timing parameters used in these diagrams. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 117 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 45: 32-Bit VLIO Read Timing CLK_MEM nCS<0> MA<25:2> tvlioAS addr addr + 1 addr + 3 0b00 MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') tvlioASRW0 0b00/0b01/0b10/0b11 tvlioASRWn tvlioASRWn tvlioAH 0 Waits tvlioAH 1 Wait tvlioCES nOE addr + 2 tvlioASRWn tvlioAH 2 Waits tvlioRWA tvlioRWD tvlioRWD 3 Waits tvlioRWA tvlioRWD tvlioAH tvlioCEH tvlioRWA nPWE RDnWR tvlioRDYH tvlioRDYH tvlioRDYH tvlioRDYH RDY RDY_sync tvlioDOH tvlioDSOH tvlioDOH tvlioDSOH tvlioDOH tvlioDSOH tvlioDSOH tvlioDOH MD<31:0> DQM<3:0>(SA1110x='0') 0b0000 DQM<3:0>(SA1110x='1') corresponding mask value tvlioCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 3, MSC0[RDN0 = 2, MSC0[RRR0] = 1 6.4.6.2 Variable-Latency I/O Write Timing Figure 46 shows the timing for 32-bit VLIO memory writes. Table 43 list the timing parameters used in Figure 46. Doc. No. MV-S104690-00 Rev. D Page 118 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 46: 32-Bit VLIO Write Timing CLK_MEM nCS<0> tvlioAS addr MA<25:2> addr + 1 addr + 2 addr + 3 tvlioASRWn tvlioASRWn 0b00 MA<1:0> tvlioASRW0 tvlioASRWn tvlioAH tvlioAH tvlioCES 0 Waits tvlioAH 1 Wait tvlioRWD tvlioRWA tvlioAH 2 Waits tvlioRWA tvlioRWD 3 Waits tvlioRWA tvlioRWD tvlioCEH tvlioRWA nPWE nOE RDnWR tvlioRDYH tvlioRDYH tvlioRDYH tvlioRDYH RDY RDY_sync MD<31:0> D0 DQM<3:0> mask0 tvlioDH tvlioDSWH tvlioDSWH D1 mask1 tvlioDH tvlioDSWH D2 mask2 tvlioDH tvlioDH tvlioDSWH D3 mask3 tvlioCD nCSx or nSDCSx NOTE: MSC0[RDF0] = 3, MSC0[RDN0] = 2, MSC0[RRR0] = 1 6.4.7 Expansion-Card Interface Parameters and Timing Diagrams The following sections describe the read/write parameters and timing diagrams for CompactFlash* and PC Card* (expansion card) memory interfaces with the memory controller. Table 44 shows the timing parameters used in the timing diagrams, Figure 47 and Figure 48. Note Note Copyright (c) 4/3/09 Marvell April 2009 Released Table 44 lists programmable register items. See the "Memory Controller" chapter in the Marvell(R) PXA27x Processor Family Developer's Manual for register configurations for more information on these items. Doc. No. MV-S104690-00 Rev. D Page 119 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 44: Expansion-Card Interface AC Specifications S y m b o ls P a ra m e t e rs MIN TYP MAX U n i ts Notes tcdAVCL Address Valid to CMD Low 2 MCx[SET] 127 CLK_MEM 1,2,3,4 tcdCHAI CMD High to Address Invalid 0 MCx[HOLD] 63 CLK_MEM 1,2,3,5 tcdDVCL Write Data Valid to CMD Low -- 1 -- CLK_MEM 1,3 tcdCHWDI CMD High to Write Data Invalid -- 4 -- CLK_MEM 1,3 tcdDVCH Read Data Valid to CMD High 2 -- -- CLK_MEM 1,3 tcdCHRDI CMD High to Read Data Invalid 0 -- -- ns 3 tcdCMD CMD Assert During Transfers -- tcdCLPS + tcdPHCH + nPWAIT assertion -- CLK_MEM 1,3 tcdILCL nIOIS16 Low to CMD Low 4 -- -- CLK_MEM 1,3 tcdCHIH CMD High to nIOIS16 High 2 -- -- CLK_MEM 1,3 tcdCLPS CMD Low to nPWAIT Sample -- x_ASST_WAIT -- CLK_MEM 1,3,6,7 tcdPHCH nPWAIT High to CMD High -- x_ASST_HOLD -- CLK_MEM 1,3,6,8 NOTES: 1. All numbers shown are ideal, integer multiples of the CLK_MEM period. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. Includes signals MA[25:0], nPREG, and nPSKTSEL. 3. CMD refers to signals nPWE, nPOE, nPIOW, and nPIOR 4. Refer to the Marvell(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to change the assertion of CMD using the MCx[SET] bit fields. 5. Refer to the Marvell(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to increase the assertion of CMD using the MCx[HOLD] bit fields. 6. Refer to the Marvell(R) PXA27x Processor Family Developer's Manual, Expansion Memory Timing Configuration registers to increase timings. The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card Interface Command Assertion Code table to see the effect of MCx[ASST]. 7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the Marvell(R) PXA27x Processor Family Developer's Manual for the correlation between x_ASST_WAIT and the MCx[ASST] bit field. 8. tcdPHCH equals CLK_MEM * x_ASST_HOLD. Refer to the PC Card Interface Command Assertion Code table in the Marvell(R) PXA27x Processor Family Developer's Manual for the correlation between x_ASST_HOLD and the MCx[ASST] bit field. Doc. No. MV-S104690-00 Rev. D Page 120 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 47: Expansion-Card Memory or I/O 16-Bit Access Timing Read Data Latch CLK_MEM nPCE[2],nPCE[1] tcdCHAI MA[25:0],nPREG,PSKTSEL tcdCLPS tcdPHCH tcdAVCL tcdCMD nPWE,nPOE,nPIOW,nPIOR tcdILCL tcdCHIH nIOIS16 tcdDVCL tcdCHWDI MD[15:0] (write) RDnWR nPWAIT tcdDVCH tcdCHRDI MD[15:0] (read) Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 121 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 48: Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing Read Data Latch Read Data Latch CLK_MEM MA<25:1>,nPREG,PSKTSEL MA<0> nPCE<2> nPCE<1> tcdAVCL tcdAVCL tcdCMD tcdCHAI tcdCMD tcdCHAI nPIOW (or) nPIOR RDnWR tcdILCL tcdCHIH nIOIS16 tcdPHCH tcdPHCH tcdCLPS tcdCLPS nPWAIT tcdDVCH tcdDVCH tcdCHRDI tcdCHRDI MD<7:0> (read) tcdCHWDI MD<7:0> (write) 6.5 tcdDVCL Low Byte tcdCHWDI High Byte LCD Timing Specifications Figure 49 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK_WR). Table 45 gives the values for the parameters. Figure 49: LCD Timing Definitions Doc. No. MV-S104690-00 Rev. D Page 122 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 LCCR3[PCP] = 1 L_PCLK_WR tpclkdv L_LDD tpclklv L_LCLK_A0 L_BIAS tpclkfv L_FCLK_RD tpclkbv LCCR3[PCP] = 0 L_PCLK_WR tpclkdv L_LDD tpclklv L_LCLK_A0 L_BIAS tpclkfv tpclkbv L_FCLK_RD Table 45: LCD Timing Specifications Symbol Description Min Max U n i ts N o te s Tpclkdv L_PCLK_WR rise/fall to L_LDD<17:0> driven valid -- 7 ns 1 Tpclklv L_PCLK_WR fall to L_LCLK_A0 driven valid -- 7 ns 2 Tpclkfv L_PCLK_WR fall to L_FCLK_RD driven valid -- 7 ns 2 Tpclkbv L_PCLK_WR rise to L_BIAS driven valid -- 14 ns 2 NOTES: 1. The LCD data pins can be programmed to be driven on either the rising or falling edge of the pixel clock (L_PCLK_WR). 2. These LCD signals can toggle when L_PCLK_WR is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK_WR pin. 6.6 SSP Timing Specifications Figure 50 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SSPCLK. Table 46 gives the values for the parameters. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Note In Figure 50, read the term "tSFMV" as "TSTXV." Note Figure 50: SSP Master Mode Timing Definitions SSPSCLK Tsfmv SSPSFRM Tsfmv SSPTXD Trxds Trxdh SSPRXD Table 46: SSP Master Mode Timing Specifications Symbol Description Tsfmv SSPSCLK rise to SSPSFRM driven valid Trxds SSPRXD valid to SSPSCLK fall (input setup) 11 ns Trxdh SSPSCLK fall to SSPRXD invalid (input hold) 0 ns Tsfmv SSPSCLK rise to SSPTXD valid Doc. No. MV-S104690-00 Rev. D Page 124 Min Max U n i ts 21 ns 22 Notes ns Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 51: Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral PXA27x processor transmitting data PXA27x SSP (Slave Mode) transmitting data to external peripheral SSPSCLK (from Peripheral) tSCLK2TXD_output_delay SSPSFRM (from Peripheral) tSFRM2TXD_output_delay SSPTXD (from SSP) Table 47: Timing Specification SSP Slave Mode Transmitting Data to External Peripheral Parameter Description Min Typ Max Units tSFRM2TXD_output_delay Frame to TX Data Out 10.58 ns tSCLK2TXD_output_delay Clock to Tx Data Out 10.52 ns Figure 52: Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral PXA27 processor receiving data PXA27x SSP (Slave Mode receiving data from external peripheral tSCLK_input_delay SSPSCLK (from Peripheral) Data Capture SSPSFRM (from Peripheral) tSFRM_input_delay SSPRXD (from Peripheral) Data Capture tRXD_input_delay Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 125 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Table 48: Timing Specification for SSP Slave Mode Receiving Data from External Peripheral P a ra m e t e r Description tSFRM_input_delay Frame to Rx Data Capture 5.21 ns tSCLK_input_delay Clock to Rx Data Capture 5.04 ns tRXD_input_delay Rx Data Setup to Capture 4.81 ns 6.7 Min Ty p i c a l Max U n i ts JTAG Boundary Scan Timing Specifications Table 49 shows the AC specifications for the JTAG boundary-scan test signals. Figure 53 shows the timing diagram. Table 49: Boundary Scan Timing Specifications Symbol Parameter M in Max U n i ts Notes TBSF TCK Frequency 0.0 33.33 MHz -- TBSCH TCK High Time 15.0 -- ns Measured at 1.5 V TBSCL TCK Low Time 15.0 -- ns Measured at 1.5 V TBSCR TCK Rise Time -- 5.0 ns 0.8 V to 2.0 V TBSCF TCK Fall Time -- 5.0 ns 2.0 V to 0.8 V TBSIS1 Input Setup to TCK TDI, TMS 4.0 -- ns -- TBSIH1 Input Hold from TCK TDI, TMS 6.0 -- ns -- TBSIS2 Input Setup to TCK nTRST 25.0 -- ns -- TBSIH2 Input Hold from TCK nTRST 3.0 -- ns -- TnTRST Assertion time of nTRST 6 -- ms -- TBSOV1 TDO Valid Delay 1.5 6.9 ns Relative to falling edge of TCK TOF1 TDO Float Delay 1.1 5.4 ns Relative to falling edge of TCK Doc. No. MV-S104690-00 Rev. D Page 126 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Figure 53: JTAG Boundary-Scan Timing TBSF TBSCH TBSCL TCK TBSIS2 TBSIH2 TBSIS1 TBSIH1 TnTRST nTRST TMS TBSIS1 TBSIH1 TDI TBSOV1 TBSOV1 TBSOV1 TBSOV1 TOF1 TBSOV1 TBSOV1 TBSOV1 TDO Shift-IR Run-Test/Idle 6.8 es et ic -R Te st -L og U un R Te st -L og ic -R Ex it1 p d - IR at eIR e Se -T set es le t/I ct d Se DR le le -Sc ct - IR a n -S ca C ap n tu re - IR Controller State Marvell(R) Quick Capture Technology AC Timing Table 50 lists the timing parameters used in Figure 54. Table 50: Marvell(R) Quick Capture AC Timing Specification Symbol Description M in Ty p i c a l Max U n i ts tciIS Camera Interface Setup Time 5 -- -- ns tciIH Camera Interface Hold Time 5 -- -- ns Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 127 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 54: Marvell(R) Quick Capture Interface Timing tciIS tciIH CIF_PCLK* CIF_DD * CIF_PCLK Data Sampling edge determined by the CICR 4[PCP] setting Doc. No. MV-S104690-00 Rev. D Page 128 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.9 MultiMediaCard Timing Specifications Figure 55: MultiMedia Card timing Diagrams tWH tWL tFREQ MMCLK tISU MMDAT0/1 tIH Data In Invalid Data In tOSU Data Out MMDAT2/3 Invalid tOH Data Out Table 51: MultiMedia Card timing specifications Symbol Parameter Min Max Unit Notes tFREQ MMCLK Frequency Data Transfer Mode 0 19.5 MHz tFREQ MMCLK Frequency Identification 0 Mode 400 KHz tWH Clock high time 10 -- ns tWL Clock low time 10 -- ns trise Clock rise time -- 10 ns 1 tfall Clock fall time -- 10 ns 1 tISU Data input setup time 3 -- ns tIH Data input hold time 3 -- ns tOSU Output data setup time 13.1 -- ns tOH Output data hold time 9.7 -- ns NOTE: 52.Rise and fall times measured from 10% - 90% of voltage level. 6.10 tWH Clock high time 10 -- ns tWL Clock low time 10 -- ns trise Clock rise time -- 10 ns 1 tfall Clock fall time -- 10 ns 1 Secure Digital (SD/SDIO) Timing Figure 56 and Table 52 define the Secure Digital (SD/SDIO) controller AC timing specifications. Copyright (c) 4/3/09 Marvell April 2009 Released Doc. No. MV-S104690-00 Rev. D Page 129 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PXA270 Processor Electrical, Mechanical, and Thermal Specification Figure 56: SD/SDIO timing diagrams tFREQ tWL tWH MMCLK tISU MMDAT0/1 tIH Data In Invalid td(ID) Invalid MMDAT2/3 td(Q) Data Out Table 52: SD/SDIO Timing Specifications Symbol Parameter Min Max Unit Notes tFREQ MMCLK Frequency Data Transfer Mode 0 19.5 MHz tFREQ MMCLK Frequency Identification 01/100 Mode 400 KHz tWH Clock high time 50 -- ns tWL Clock low time 50 -- ns trise Clock rise time -- 10 ns 2 tfall Clock fall time -- 10 ns 2 tISU Data input setup time 5 -- ns tIH Data input hold time 5 -- ns td(Q) Output Delay time during Data Transfer Mode 0 14 ns td(ID) Output Delay time during Identification Mode 0 50 ns NOTES: 1. 0 KHz is when the clock is stopped. The minimum 100 KHz frequency range is where continuous clock is required. 2. Rise and fall times measured from 10% - 90% of voltage level. Doc. No. MV-S104690-00 Rev. D Page 130 Copyright (c) 4/3/09 Marvell April 2009 Released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster