R5105N SERIES Microprocessor Supervisory Circuit NO.EA-159-080808 OUTLINE The R5105N Series are CMOS-based microprocessor supervisory circuit, or high accuracy and ultra low supply current voltage detector with built-in delay circuit and watchdog timer. When the supply voltage is down across the threshold, or the watchdog timer does not detect the system clock from the microprocessor, the reset output is generated. The voltage detector circuit is used for the system reset, etc. The detector threshold is fixed internally, and the accuracy is 1.0%. The released delay time (Power-on Reset Delay) circuit is built-in, and output delay time is adjustable with an external capacitor, and the accuracy is 16%*. When the supply voltage becomes higher than the released voltage, the reset state will be maintained during the delay time. The output type of the reset is selectable, Nch open-drain, or CMOS. The time out period of the watchdog timer can be also set with an external capacitor, and the accuracy is 33%*. There are another 4 products by the difference of packages and the function of voltage detector and watchdog timer. The package of R5105N is SOT-23-6. FEATURES * Supply Current...................................................................... Typ. 11A * Operating Voltage Range ..................................................... 0.9V to 6.0V < Voltage Detector Part > * Detector Threshold Range.................................................... Stepwise setting with a step of 0.1V in the range of 1.5V to 5.5V * Detector Threshold Accuracy................................................ 1.0% * Power-on Reset Delay Time accuracy ................................. 16%* (-40C < = Topt < = 105C) * Power-on reset delay time of the voltage detector ............... Typ. 370ms with an external capacitor : 0.1F < Watchdog Timer Part > * Built-in a watchdog timer's time out period accuracy ........... 33%* (-40C < = Topt < = 105C) * Timeout period for watchdog timer ....................................... Typ. 310ms with an external capacitor : 0.1F * Reset timer for watchdog timer............................................. Typ. 34ms with an external capacitor : 0.1F * Package................................................................................ SOT-23-6 *) Accuracy to center value of (Min.+Max.)/2 APPLICATIONS * Supervisory circuit for equipment with using microprocessors. 1 R5105N BLOCK DIAGRAMS Nch Open Drain Output (R5105Nxx1A) CMOS Output (R5105Nxx1C) VDD 3 VDD 3 CD 6 CD 6 Vref2 Vref1 CTW 2 WATCHDOG TIMER CLOCK DETECTOR Vref2 5 GND WATCHDOG TIMER 1 SCK RESETB 4 Vref1 CTW 2 CLOCK DETECTOR 5 GND 1 SCK RESETB 4 SELECTION GUIDE The detector threshold, the output type and the taping type for the ICs can be selected at the users' request. The selection can be made with designating the part number as shown below; R5105Nxx1x-xx-x Part Number a b c d e Code 2 Contents a Designation of Package Type; N: SOT-23-6 b Setting Detector Threshold (-VDET); Stepwise setting with a step of 0.1V in the range of 1.5V to 5.5V is possible. c Designation of Output Type; A: Nch Open Drain C: CMOS d Designation of Taping Type ; TR (Refer to Taping Specifications; TR type is the standard direction.) e Designation of Composition of pin plating -F: Lead free solder plating (SOT-23-6) R5105N SERIES SELECTION R5105N Package R5106N R5107G R5108G SOT-23-6 With INH pin (Inhibit) R5109G SSOP-8G No Yes 2 clock input No With MR pin (Manual Reset) No Yes Yes With SENSE pin No Remarks CD pin and CTW pin are combined uses. No Yes No Operating Supply Current Voltage Range 11.5A 1.5V to 6.0V PIN CONFIGURATION * SOT-23-6 6 5 4 (mark side) 1 2 3 PIN DESCRIPTIONS * SOT-23-6 Pin No. Symbol Description 1 SCK Clock Input Pin from Microprocessor 2 CTW External Capacitor Pin for setting Reset and Watchdog Timer Timeout Period 3 VDD Power supply Pin 4 RESETB 5 GND 6 CD Output Pin for Reset signal of Watchdog timer and Voltage Detector. (Output "L" at detecting Detector Threshold and Watchdog Timer Reset.) Ground Pin External Capacitor Pin for Setting delay time of Voltage Detector 3 R5105N ABSOLUTE MAXIMUM RATINGS Symbol VDD Item Rating Unit -0.3 to 7.0 V Voltage of CD Pin -0.3 to VDD + 0.3 V Voltage of CTW Pin -0.3 to VDD + 0.3 V Voltage of RESETB Pin -0.3 to 7.0 V Input Voltage Voltage of SCK Pin -0.3 to 7.0 V Output Current Current of RESETB Pin 20 mA Supply Voltage VCD VCTW Output Voltage VRESETB VSCK IRESETB Topt=25C PD Power Dissipation (SOT-23-6)* 420 mW Topt Operating Temperature Range -40 to 105 C Tstg Storage Temperature Range -55 to 125 C * ) For Power Dissipation, please refer to PACKAGE INFORMATION to be described. ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings is not assured. 4 R5105N ELECTRICAL CHARACTERISTICS VDD=6.0V, CTW=0.1F, CD=0.1F, In case of Nch Open Drain Output type, the output pin is pulled up with a resistance of 100k (R5105Nxx1A), unless otherwise noted. The specification in is checked and guaranteed by design engineering at -40C < = Topt < = 105C. * R5105Nxx1A/C Symbol * Topt=25C Item VDD Operating Voltage ISS Supply Current Min. Typ. Max. Unit 6.0 V 11 15 A Typ. Max. Unit 0.9 VDD= -VDET+0.5V, Clock pulse input VD Part Symbol Item -VDET Detector Threshold VHYS Detector Threshold Hysteresis -VDET/ Detector Threshold Topt Temperature Coefficient tPLH IRESETB * Conditions Output Delay Time Output Current (RESETB Output pin) Conditions Topt=25C -40C < = Topt < = 105C Min. x0.990 x1.010 x0.972 x1.015 -VDET x0.03 -40C < = Topt < = -VDET x0.07 100 105C CD=0.1F *1 -VDET x0.05 340 370 V V ppm/C 467 ms Nch VDD=1.2V VDS=0.1V 0.38 0.8 mA Pch *2 VDD=6.0V VDS=0.5V 0.65 0.9 mA Min. Typ. Max. Unit WDT Part Symbol Item Conditions tWD Watchdog Timeout period CTW=0.1F *1 230 310 450 ms tWR Reset Hold Time of WDT CTW=0.1F *1 29 34 48 ms VSCKH SCK Input "H" VDDx0.8 6.0 V VSCKL SCK Input "L" 0 VDDx0.2 V tSCKW SCK Input Pulse Width VSCKL=VDDx0.2 VSCKH=VDDx0.8 500 ns All of unit are tested and specified under load conditions such that Topt=25C except for Detector Threshold Temperature Coefficient. *1) The specification does not contain the temperature characteristics of the external capacitor. *2) In case of CMOS type (R5105Nxx1C) RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS) All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. 5 R5105N TIMING CHART VDD +VDET -VDET tPHL VCD tPHL +VTCD -VTCD tWD tWDI Vref2H VCTW Vref2L tPLH tPLH VSCK tWR VRESETB (1) (2) (3) (4) (1) ) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting. ) Vref2H : CTW pin voltage at the end of WDT timeout period. ) Vref2L : CTW pin voltage at the begin of WDT timeout period. OPERATION (1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level. (2) When the SCK pulse is input, the watchdog timer (WDT) is cleared, and CTW pin mode changes from the discharge mode to the charge mode. When the CTW pin voltage becomes higher than VrefH, the mode will change into the discharge mode, and next watchdog time count starts. (3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CTW pin, RESETB="L". (4) When the VDD pin becomes lower than the detector threshold voltage(-VDET), RESETB outputs "L". 6 R5105N * Watchdog Timeout period/Reset hold time The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin. The next equations describe the relation between the watchdog timeout period and the external capacitor value, or the reset hold time and the external capacitor value. tWD (s) = 3.1x106xC (F) tWR (s) = tWD/9 The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor. During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next reset hold time RESETB pin outputs "L". After starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse is input during the time period "tWDI", the clock pulse is ignored. tWDI (s) = tWD/10 * Released Delay Time (Power-on Reset delay time) The released delay time can be set with an external capacitor connected to the CD pin. The next equation describes the relation between the capacitance value and the released delay time (tPLH). tPLH (s) =3.7x106x C (F) When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay time will be shorter than tPLH which is expected. Power on Reset Operation against the input glitch (tPLH1