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FEATURES
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
DESCRIPTION/ORDERING INFORMATION
SN74LVC86A-EPQUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B DECEMBER 2003 REVISED JULY 2007
Controlled Baseline Max t
pd
of 4.6 ns at 3.3 V One Assembly/Test Site, One Fabrication Typical V
OLP
(Output Ground Bounce) <0.8 VSite at V
CC
= 3.3 V, T
A
= 25 °CExtended Temperature Performance of –40 °CTypical V
OHV
(Output V
OH
Undershoot) >2 V atto 125 °C and –55 °C to 125 °C V
CC
= 3.3 V, T
A
= 25 °CEnhanced Diminishing Manufacturing Sources(DMS) SupportEnhanced Product-Change NotificationQualification Pedigree
(1)
Operates From 2 V to 3.6 VInputs Accept Voltages to 5.5 V(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits.
The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V V
CC
operation.
The device performs the Boolean function Y = A B or Y = AB + A B in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproducedin true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at theoutput.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator ina mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
SOIC D Reel of 2500 SN74LVC86AQDREP LVC86AE–40 °C to 125 °C
TSSOP PW Reel of 2000 SN74LVC86AQPWREP LVC86AE–55 °C to 125 °C SOIC D Reel of 2500 SN74LVC86AMDREP LVC86AM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE(EACH GATE)
INPUTS
OUTPUT
YA B
L L LL H HH L HH H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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EXCLUSIVE-OR LOGIC
= 1
EXCLUSIVE OR
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings
(1)
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B DECEMBER 2003 REVISED JULY 2007
An exclusive-OR gate has many applications, some of which can be represented better by alternative logicsymbols.
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Output voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 V –50 mAI
OK
Output clamp current V
O
< 0 V –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mAD package 86θ
JA
Package thermal impedance
(4)
°C/WPW package 113T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Recommended Operating Conditions
(1)
Electrical Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC86A-EPQUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B DECEMBER 2003 REVISED JULY 2007
MIN MAX UNIT
Operating 2 3.6V
CC
Supply voltage VData retention only 1.5V
IH
High-level input voltage V
CC
= 2.7 V to 3.6 V 2 VV
IL
Low-level input voltage V
CC
= 2.7 V to 3.6 V 0.8 VV
I
Input voltage 0 5.5 VV
O
Output voltage 0 V
CC
VV
CC
= 2.7 V –12I
OH
High-level output current mAV
CC
= 3 V –24V
CC
= 2.7 V 12I
OL
Low-level output current mAV
CC
= 3 V 24
Δt/ Δv Input transition rise or fall rate 9 ns/VQ suffix –40 125T
A
Operating free-air temperature °CM suffix –55 125
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 μA 2.7 V to 3.6 V V
CC
0.22.7 V 2.2V
OH
I
OH
= –12 mA V3 V 2.4I
OH
= –24 mA 3 V 2.2I
OL
= 100 μA 2.7 V to 3.6 V 0.2V
OL
I
OL
= 12 mA 2.7 V 0.4 VI
OL
= 24 mA 3 V 0.55I
I
V
I
= 5.5 V or GND 3.6 V ±5μAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 10 μA
ΔI
CC
One input at V
CC
0.6 V, Other inputs at V
CC
or GND 2.7 V to 3.6 V 500 μAC
i
V
I
= V
CC
or GND 3.3 V 5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 3.3 VV
CC
= 2.7 VFROM TO
±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX
t
pd
A Y 5.6 1 4.6 ns
T
A
= 25 °C
V
CC
= 2.5 V V
CC
= 3.3 VTESTPARAMETER UNITCONDITIONS
TYP TYP
C
pd
Power dissipation capacitance per gate f = 10 MHz 7.5 8.5 pF
3Submit Documentation Feedback
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH - V0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
2.7 V
3.3 V ± 0.3 V 500
500
VCC RL
6 V
6 V
VLOAD CL
50 pF
50 pF 0.3 V
0.3 V
V
2.7 V
2.7 V
VI
1.5 V
1.5 V
VM
tr/tf
2.5 ns
2.5 ns
INPUTS
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCAS752B DECEMBER 2003 REVISED JULY 2007
Figure 1. Load Circuit and Voltage Waveforms
4
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC86AMDREP ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86AQDREP ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86AQPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04670-01XE ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04670-01YE ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04670-02XE ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC86A-EP :
Catalog: SN74LVC86A
Automotive: SN74LVC86A-Q1
Military: SN54LVC86A
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC86AMDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC86AQDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC86AQPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC86AMDREP SOIC D 14 2500 333.2 345.9 28.6
SN74LVC86AQDREP SOIC D 14 2500 333.2 345.9 28.6
SN74LVC86AQPWREP TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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