EVALUATION KIT AVAILABLE MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic General Description The MAX14983E integrates high-bandwidth analog switches, level-translating buffers, and 5V power switches to implement a complete 1:2 multiplexer for VGA monitors. The device switches graphics signals between a controller and two outputs. Integrated pullup resistors (2.2kI typ) are provided on the monitor-side display data channel (DDC) signal lines. The device features a simple power interface that operates with a single +5V supply input. Two integrated power switches with current limiting and reverse-current protection pass the +5V supply to external loads with minimal voltage drop. The horizontal and vertical synchronization (HSYNC/ VSYNC) buffers shift logic levels to support +2.5V to +5.0V CMOS or TTL-compatible graphics controllers while meeting the VESA drive capability requirement of Q8mA. An internal 2.5V regulator translates the DDC voltage levels to be compatible with low-voltage graphics controllers. Benefits and Features S Design Flexibility Graphics Controller Port is Protected when VCC = 0V DDC Switches Limit Voltage to Low-Voltage Supply Internal +2.5V Regulator S High Level of Integration for Enhanced Performance Low 5.5pF (typ) RGB Capacitance 2.0ns (typ) tR/tF with 10pF, 2.2kI Load on Monitor-Side SYNC Signals Source and Sink 8mA While Meeting Speed Requirements 11kV Human Body Model (HBM) S Saves Space on Board Internal Power Switches Pass +5V with 300mV (max) IR Drop Short-Circuit/Thermal/Reverse-Current Protection 5mm x 5mm, 32-Pin TQFN Package Typical Operating Circuit The device also features monitor-detect outputs and enable inputs that allow monitor switching to operate either automatically or with inputs from the graphics controller. The MAX14983E is available in a 32-pin (5mm x 5mm) TQFN package, and is specified over the -40NC to +85NC extended temperature range. +5V +2.5V 0.1F Applications 3 Servers KVM Switches 2 GRAPHICS CONTROLLER 2 Computing Graphics Cards VCC R0, G0, B0 HSYNC0, VSYNC0 HSYNC1, VSYNC1 SCL0, SDA0 SCL1, SDA1 3 2 2 VGA PORT 1 S5V1 MDOR S5V2 S5V1 R1, G1, B1 1F MAX14983E R2, G2, B2 Ordering Information appears at end of data sheet. MD1 HSYNC2, VSYNC2 MD2 SCL2, SDA2 EN1 S5V2 EN2 3 2 2 VGA PORT 2 1F REF GND 105I For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14983E.related. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. 19-5935; Rev 0; 6/11 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VCC, S5V1, S5V2, SDA_, SCL_, REF, MD_, EN_, MDOR..........................................................-0.3V to +6V HSYNC_, VSYNC_, R_, G_, B_.................. -0.3V to (VCC + 0.3V) Continuous Current Through R_, G_, B_ Switches.......... Q50mA Continuous Current Through SDA_, SCL_ Switches....... Q50mA Continuous Current Through S5V_................................ Q750mA Peak Current Through R_, G_, B_, SDA_, SCL_ (10% duty cycle)........................................................ Q100mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 34.5mW/NC above +70NC)...............2758.6mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (BJA)...........29NC/W Junction-to-Case Thermal Resistance (BJC)...............1.7NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VCC = +5V Q5%, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +5V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Quiescent Current IQ VCC = 5.25V, VEN1 = VEN2 = VCC, REF unconnected 50 150 FA Operating Current ICC HSYNC0 = 50kHz, VSYNC0 = 60Hz 10% duty cycle, RL on SYNC outputs = 2kI, REF unconnected 1.5 2.7 mA IOUT = 55mA 0.3 V IL VCC = 0V, VEN1 = VEN2 = 0V, VS5V1 = VS5V2 = 5.25V, no load on S5V1 or S5V2 10 FA RS5V1, RS5V2 VS5V1 = VS5V2 = 1V, VEN1 = VEN2 = VCC 5V SWITCH (S5V1, S5V2 OUTPUTS) S5V_ Voltage Drop Reverse Leakage Current Pulldown Resistor Output Current Limit VS5V ILIM 250 55 300 I 500 mA Thermal-Shutdown Threshold TSHDN +150 NC Thermal-Shutdown Hysteresis TSHDN_ 25 NC Maxim Integrated HYS 2 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V Q5%, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +5V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN VEN1 = VCC, VEN2 = VCC, VIN = 0V or 5.25V -1 TYP MAX UNITS +1 FA 10 FA DDC SWITCHES (SDA_, SCL_ INPUTS/OUTPUTS) Input Leakage Current IL Off-Leakage Current ILOFF On-Resistance RON SDA1, SDA2, SCL1, SCL2 Internal Pullup Resistance RPULLUP VIN = +5.25V, VCC = 0V VIN = 0.8V, ISDA_ = ISCL_ = 10V 25 I VSDA_ = VSCL_ = 4V 2.2 kI CONTROL SIGNALS (HSYNC_, VSYNC_, EN_ INPUTS/OUTPUTS) Input Logic-Low Voltage VIL HSYNC0, VSYNC0, EN1, EN2 Input Logic-High Voltage VIH HSYNC0, VSYNC0, EN1, EN2 Output Logic-Low Voltage VOL HSYNC1, HSYNC2, VSYNC1, VSYNC2, ISINK = 8mA Output Logic-High Voltage VOH HSYNC1, HSYNC2, VSYNC1, VSYNC2, ISOURCE = 8mA Rise Time/Fall Time tR, tF HSYNC0 input tR/tF < 5ns, 10% to 90% 0.8 2 V V 0.5 2.4 V V 2 ns MONITOR DETECTION OUTPUTS (MD_, MDOR) Output-Voltage Low VOL RPULLUP = 3.3kI, VPU = 3.3V (Note 3) 0.3 V Input Leakage Current ILOD VIN = 3.3V, MD_ and MDOR deasserted 1 FA R_, G_, B_ SWITCH PERFORMANCE Bandwidth fMAX Figure 1, RS = RL = 50I 800 MHz On-Loss ILOSS Figure 1, f = 50MHz, RS = RL = 50I -0.6 dB On-Resistance RON IIN = 10mA, VIN = 0.7V IIN = 10mA, VIN = 0 to 0.7V On-Resistance Matching On-Resistance Flatness B1, B2 Internal Pullup Resistance DRON 5 RFLAT(ON) IIN = 10mA, VIN = 0 to 0.7V 0.5 RB 8 I 1 I 1 I 2.5 Off-Leakage Current ILOFF Off-Capacitance COFF VR_ = VG_ = VB0 = 0V or VCC f = 1MHz; R0, G0, B0 to R_, G_, B_ On-Capacitance CON -1 kI +1 FA 2.5 pF f = 1MHz; R0, G0, B0 to R_, G_, B_ 5.5 pF High-ESD Pins ESD Protection Human Body Model (Note 4) Q11 kV All Other Pins ESD Protection Human Body Model (Note 4) Q2 kV ESD PROTECTION Note 2: All units are production tested at TA = +25NC. Specifications over temperature are guaranteed by design. Note 3: VPU is the pullup voltage. Note 4: See the Pin Description section for the ESD status of each pin. Maxim Integrated 3 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic +5V 0.1F 0V OR VCC NETWORK ANALYZER VCC EN1, EN2 50I VIN R0, G0, B0 50I ON-LOSS = 20log VOUT VIN MAX14983E R1, G1, B1 50I VOUT R2, G2, B2 MEAS GND REF 50I 50I MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. ON-LOSS IS MEASURED BETWEEN R0 AND R1 ON EACH SWITCH. SIGNAL DIRECTION THROUGH IS REVERSED; WORST VALUES ARE RECORDED. Figure 1. On-Loss Typical Operating Characteristics (VCC = +5.0V, TA = +25NC, unless otherwise noted.) DDC ON-RESISTANCE vs. ANALOG SIGNAL VOLTAGE 40 IRO = 10mA 40 RON (I) 30 20 MAX14983E toc02 ISDA0 = 10mA RON (I) 50 MAX14983E toc01 50 RGB ON-RESISTANCE vs. ANALOG SIGNAL VOLTAGE 30 20 TA = +85C TA = +25C TA = +85C TA = +25C 10 10 TA = -40C TA = -40C 0 0 0.5 1.0 VSDA0 (V) Maxim Integrated 1.5 2.0 0 0 1 2 3 4 5 VR0 (V) 4 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25NC, unless otherwise noted.) HSYNC_/ VSYNC_ OUTPUT VOLTAGE vs. TEMPERATURE FREQUENCY RESPONSE MAX14983E toc04 -2 VOH 4 -3 ISOURCE /ISINK = 8mA VOH / VOL (V) FREQUENCY RESPONSE (dB) 5 MAX14983E toc03 0 -1 -4 -5 -6 3 2 -7 -8 -9 1 VOL G0 TO G1 -10 100E+3 1E+6 10E+6 100E+6 0 1E+9 -40 -15 FREQUENCY (Hz) -10 35 60 85 TEMPERATURE (C) B1 HSYNC1 VSYNC1 REF GND VSYNC2 HSYNC2 B2 Pin Configuration 24 23 22 21 20 19 18 17 TOP VIEW 16 G1 25 G2 R1 26 15 R2 SCL1 27 14 SCL2 13 SDA2 12 S5V2 11 VCC 10 MDOR 9 EN2 SDA1 28 MAX14983E S5V1 29 MD2 30 MD1 31 *EP + 6 7 8 SCLO G0 5 SDAO RO 4 VSYNC0 3 BO 2 HSYNC0 1 GND EN1 32 TQFN *CONNECT EP TO GND. Maxim Integrated 5 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Pin Description PIN NAME 1, 20 GND FUNCTION Ground ESD -- 2 R0 RGB Analog Input Standard 3 G0 RGB Analog Input Standard 4 B0 RGB Analog Input Standard 5 HSYNC0 Horizontal Sync Input Standard 6 VSYNC0 Vertical Sync Input Standard 7 SDA0 DDC Input/Output Standard 8 SCL0 DDC Input/Output Standard 9 EN2 Active-Low Enable Input 2. Assert EN2 to connect the graphics controller to the monitor on port 2 (see Table 1). Standard 10 MDOR Logic NOR Output of MD1 and MD2. MDOR asserts whenever a monitor is detected on either port. MDOR is an active-low, open-drain output. Standard 11 VCC Supply Voltage. VCC = +5.0V 5%. Bypass VCC to GND with a 1FF or larger ceramic capacitor as close as possible to VCC. Standard 12 S5V2 Switched 5V Out 2. S5V2 is internally pulled down when not connected. High 13 SDA2 DDC Input/Output. SDA2 has a 2.2kI (typ) internal pullup resistor to S5V2. High 14 SCL2 DDC Input/Output. SCL2 has a 2.2kI (typ) internal pullup resistor to S5V2. High 15 R2 RGB Analog Output for Port 2 High 16 G2 RGB Analog Output for Port 2 High 17 B2 RGB Analog Output for Port 2 High 18 HSYNC2 Horizontal Sync Output for Port 2 High 19 VSYNC2 Vertical Sync Output for Port 2 High 21 REF Monitor-Detection Reference. Connect a 105I 1% resistor from REF to ground. Standard 22 VSYNC1 Vertical Sync Output for Port 1 High 23 HSYNC1 Horizontal Sync Output for Port 1 High 24 B1 RGB Analog Output for Port 1 High 25 G1 RGB Analog Output for Port 1 High 26 R1 RGB Analog Output for Port 1 High 27 SCL1 DDC Input/Output. SCL1 has a 2.2kI (typ) internal pullup resistor to S5V1. High 28 SDA1 DDC Input/Output. SDA1 has a 2.2kI (typ) internal pullup resistor to S5V1. High 29 S5V1 Switched 5V Out 1. S5V1 is internally pulled down when not connected. High 30 MD2 Monitor-Detect Output 2. MD2 asserts when a monitor is detected on port 2. MD2 is an activelow, open-drain output. Standard 31 MD1 Monitor-Detect Output 1. MD1 asserts when a monitor is detected on port 1. MD1 is an activelow, open-drain output. Standard 32 EN1 Enable Input 1. Assert EN1 to connect the graphics controller to the monitor on port 1 (see Table 1). Standard -- EP Maxim Integrated Exposed Pad. Connect exposed pad to GND. -- 6 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Functional Diagram VCC S5V1 250I INTERNAL VL 2.5V REGULATOR S5V2 250I MAX14983E R0 R1 G0 G1 B0 B1 MDOR R2 G2 MD1 B2 MONITOR DETECTION MD2 2.2kI S5V1 SDA1 SDA0 2.2kI SCL1 SCL0 2.2kI S5V2 SDA2 2.2kI SCL2 HSYNC0 HSYNC1 VSYNC0 VSYNC1 HSYNC2 THERMAL PROTECTION EN1 EN2 VSYNC2 CONTROL LOGIC GND Maxim Integrated 7 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Truth Tables Table 1. Channel Selection EN1 EN2 VGA CONTROLLER CONNECTED TO 0 0 Port 1 0 1 Port 1 1 0 Port 2 1 1 Not Connected 5V Power Switches (S5V1, S5V2) The device provides a switched +5V output in addition to the regular VGA signals (S5V1 and S5V2). Each output can supply 55mA with less than 300mV drop from VCC. The S5V_ outputs tolerate +5V while turned off. Note: The B_ switches are unconnected if the HSYNC_ input is idle. Table 2. Monitor Detection MONITOR 1 DETECTED MONITOR 2 DETECTED MD1 MD2 MDOR No No 1 1 1 No Yes 1 0 0 Yes No 0 1 0 Yes Yes 0 0 0 Note: MD1, MD2, and MDOR function regardless of the state of the EN_ inputs. Detailed Description The MAX14983E integrates high-bandwidth analog switches and level-translating buffers to implement a complete 1:2 multiplexer for VGA signals. The device provides switching for red-green-blue (RGB) signals, horizontal and vertical synchronization (HSYNC/VSYNC) pulses, display data channel (DDC) signals, and 5V power supplies. The power switches provide +5V power with current limiting and reverse-voltage protection. The device uses a simplified power-supply interface that operates from a single +5V supply. An internal 2.5V regulator limits the voltage passed by the DDC switches to provide compatibility with low-voltage graphics controllers. The device features two enable inputs and three monitordetection outputs. This interface signals to the graphics controller when a monitor is inserted or removed from either of the VGA ports and allows it to switch between Maxim Integrated them. Alternatively, these signals can be connected together to automatically select the port when a monitor is plugged in. A dedicated output (MDOR) signals the graphics controller when any monitor is detected. The power switches are protected against overcurrent and overtemperature faults. The device limits current supplied to each monitor side to 300mA (typ). Thermalprotection circuitry shuts off the switch when the temperature exceeds +150NC. The device is re-enabled once the temperature has fallen below +125NC. Each power switch output has a 250I (typ) pulldown resistor to discharge filter capacitors when the switch is off. RGB Switches The device provides three single-pole/double-throw (SPDT) high-bandwidth switches to route the standard VGA R, G, and B signals (Table 1). The R, G, and B analog switches are identical, and any of the three switches can be used to route red, green, or blue video signals. Horizontal/Vertical Sync Multiplexer The HSYNC_/VSYNC_ signals are buffered to provide level shifting and drive capability to meet the VESA specification. HSYNC_/VSYNC_ signals are only routed to the port selected by EN2 and EN1 (Table 1). HSYNC_ and VSYNC_ are not interchangeable. Display Data Channel Multiplexer (SDA_, SCL_) The device provides two voltage-limited SPDT switches to route DDC signals (SDA_, SCL_). These switches limit the voltage that can be passed through to the graphics controller to less than 2.5V. Internal pullup resistors on the monitor side of the switches translate the graphics controller signals to 5V compatible logic. Connect pullup resistors on SCL0 and SDA0 to define the logic level of the graphics controller. The SDA_ and SCL_ switches are identical, and either of these two switches can be used to route SDA or SCL I2C signals. 8 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Applications Information 1:2 Multiplexer for Low-Voltage Graphics Controllers The device provides the level shifting necessary to drive two standard VGA ports using a single graphics controller. Internal buffers drive the HSYNC_ and VSYNC_ signals to VGA standard TTL levels. The DDC multiplexer provides level shifting by limiting signal levels to less than 2.5V. Power-Supply Decoupling Bypass VCC to ground with a 1FF or larger ceramic capacitor as close as possible to the device. PCB Layout High-speed switches such as the MAX14983E require proper PCB layout for optimum performance. Ensure that impedance-controlled PCB traces for high-speed signals are matched in length and as short as possible. Connect the exposed pad to a solid ground plane. RC 1MI CHARGE CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kI The ESD structures withstand high ESD both in normal operation and when the device is powered down. After an ESD event, the device continues to function without latchup. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test methodology and results. Human Body Model Figure 2 shows the Human Body Model. Figure 3 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5kI resistor. IPEAK (AMPS) 100% 90% DISCHARGE RESISTANCE STORAGE CAPACITOR High-ESD Protection Electrostatic discharge (ESD)-protection structures are incorporated on all pins to protect against electrostatic discharges up to Q2kV Human Body Model (HBM) encountered during handling and assembly. All outputs are further protected against ESD up to Q11kV (HBM) without damage (see the Pin Description). DEVICE UNDER TEST Maxim Integrated PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 10% 0 Figure 2. Human Body ESD Test Model Ir 0 TIME tRL tDL Figure 3. Human Body Current Waveform 9 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX14983EETJ+ -40NC to +85NC 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed paddle. Chip Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 TQFN-EP T3255+4 21-0140 90-0012 PROCESS: BiCMOS Maxim Integrated 10 MAX14983E Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic Revision History REVISION NUMBER REVISION DATE 0 6/11 DESCRIPTION Initial release PAGES CHANGED -- Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2011 Maxim Integrated Products, Inc. 11 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.