DS109-1 (v1.2) May 7, 2003 www.xilinx.com 1
Advance Pr oduct Specificati on 1-800-255-7778
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Features
• Guaranteed to meet full electrical specifications ov er
TA= –40°C to +125°C
• Techno logy: 0.35 µm EEPROM process
• Full Boundar y Scan Te st (IEEE 1149.1) for flexible
in-system de vice and syst em testing
• Fast programmng times in production sav es time and
money
- Increases system reliability through reduced device
handling
• High-speed pin-to-pin dela ys of 10 ns (100 MHz)
• Slew rate control per output to reduce EMI
• 100% routable which enables all device resource s to
be utilized
Family Overview
The Cool Runner™ XP LA3 (extended Pr ogramma ble Logic
Array) Automotive IQ product family of CPLDs is targeted
for low power systems that include portable, handheld,
automotive, and power sensitive applications. Each mem-
ber of the XPLA3 family includes Fast Zero Power™ (FZP)
design technology that combines low power and high
speed. Wi th this design tec hnique, the XPLA 3 fa mily deliv-
ers power that is less than 100 µA at standby without the
need for "turbo bits" or other power down schemes. By
replacing conventional sense amplifier methods for imple-
menting p ro duct terms (a technique that has been used in
PLDs since the bipolar era) with a cascaded chain of pure
CMOS gates, the dynamic power is also substantially lower
than any other CPLD. CoolRunner devices are the only
Tota lCM OS PL Ds, as th ey u se both a CMOS process tech-
nology and the patented full CMOS FZP design technique.
The CoolRunner XPLA3 family employs a full PLA structure
for logi c allocation within a functon block . The PLA provides
maximum flexibility and logic density, with superior pin loc k-
ing capability, while maintaining deterministic timing.
XPLA3 CPLDs are supported by WebPACK™ and WebFIT-
TER™ from Xilinx and industry standard CAE tools
(Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys,
ViewLogic, and Synplicity), using text (ABEL, VHDL, Ver-
ilog) and schematic capture design entry. Design verifica-
tion uses industry standard simulators for functional and
timing simulation. Development is supported on personal
computer, Sparc, and HP platforms.
The XPLA3 family features also include i ndustr y-standard,
IEEE 1149 .1, JTAG interface through which boundar y -s can
testing and In-System Programming (ISP) and reprogram-
ming of the device can occur. The XPLA3 CPLD is electri-
cally reprogrammable using industry standard device
programmers.
0CoolRunne r XPLA3 CPLD
Automotive IQ Pr oduct F amily
Introdu c tion and Ordering
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Ad va nc e Pr o duct Sp eci fic ation
R
Table 1: CoolRunner XPLA3 Device Family
XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
Macrocells 32 64 128 256 384 512
Usable Gates 750 1,500 3,000 6,00 0 9,000 12,000
Registers 32 64 128 256 384 512
FSYSTEM (MHz)959595 888777
Table 2: CoolRunner XP LA3 Packages and User I/O Pins
XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
44-pin VQFP 36 36 - - - -
100-pin VQFP - 68 84 - - -
144-pin TQFP - - 108 120 - -
208-pin PQFP - - - 164 172 180