EVALUATION KIT AVAILABLE MAX14900E Octal, High-Speed, Industrial, High-Side Switch General Description The MAX14900E is an octal power switch that features per-channel configuration for high-side or pushpull operation. Low propagation delay, high-rate loadswitching makes the device suitable for next-generation high-speed PLC systems. Each high-side switch sources 850mA continuous current with a low 165m (max) on-resistance at 500mA at TA = +125C. The high-side switches feature 2s (max) input-to-output propagation delay when driving resistive loads. Long cables can be driven with switching rates of up to 100kHz for PWM/PPO control in push-pull operation. Multiple high-side switches can be connected in parallel to achieve higher drive currents. The device features a wide supply input range of 10V to 36V. The MAX14900E is configured, monitored, and driven by an SPI and/or parallel interface. In parallel mode, eight logic inputs directly control the outputs and the serial interface can be used for configuration/monitoring. Serial mode utilizes the serial interface for both setting and configuration, and features CRC error detection to ensure robust SPI communication. Current limiting and per-channel thermal shutdown protect each switch/driver. The device features a global diagnostics output as well as per-channel diagnostics and monitoring through the serial interface. The MAX14900E is available in a 48-pin (7mm x 7mm) QFN-EP or standard 48-pin TQFN-EP package, and is specified over the -40C to +125C temperature range. Applications Programmable Logic Controllers High-Density Digital Output Modules Motor Controllers PWM/PPO Control Benefits and Features Low Power for High-Density Modules * 3mA (max) Total Supply Current * 165m (max) High-Side RON at +125C Fast Switching Ideal for Accurate, High-Speed Control Systems * 2s Propagation Delays (High-Side Mode) * 0.8s Propagation Delays (Push-Pull Mode) * 100kHz (max) Push-Pull Mode Switching Rate Extensive Fault Feedback Eases Maintenance and Reduces Installation Time * Global and Per-Channel Diagnostics * Open Load/Wire Detection * Thermal Shutdown Fault Indication * Output Logic State Feedback * Undervoltage Lockout Small Packages with Serial Interface Allows Making High-Density Modules * Daisy-Chainable SPI Minimizes Isolation Cost * 7mm x 7mm, 48-Pin QFN and TQFN Packages Functional Diagram VL VDD V5 VL FLTR PUSHPL V5 UV MONITOR OL/IN1 IN2 IN5 IN6 PARALLEL INTERFACE MAX14900E DRIVE + MONITOR CONFIG AND SETTING CS DRIVE + MONITOR SERIAL INTERFACE DRIVE + MONITOR REXT O5 VDD O4 O3 O3 O2 OVERTEMP AGND O2 VDD OVERLOAD OPEN LOAD O4 VDD VDD DRIVE + MONITOR EN 19-6563; Rev 4; 4/15 O5 EN DIAGNOSTICS O7 O6 VDD EN DRIVE + MONITOR FAULT O6 EN SDO Ordering Information and Typical Operating Circuit appear at end of data sheet. VDD EN SRIAL SDI O7 EN DRIVE + MONITOR S16/IN8 O8 VDD DRIVE + MONITOR CNFG/IN7 CLK DRIVE + MONITOR O8 EN CRC/IN3 CERR/IN4 VDD VDD PGND O1 O1 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Absolute Maximum Ratings (All voltages referenced to AGND = PGND.) VDD.........................................................................-0.3V to +40V O_.............................................................. -0.3V to (VDD + 0.3V) V5, VL, FAULT, IN_, PUSHPL, FLTR, SRIAL, CLK, SDI, CS, EN.........................-0.3V to +6V REXT............................................................ -0.3V to (V5 + 0.3V) SDO.............................................................. -0.3V to (VL + 0.3V) Continuous Reverse Current (O_)........................................2.0A Inductive Kickback Current (O_)...........................................1.9A Continuous Current (Any Other Terminal).......................100mA Continuous Power Dissipation (TA = +70C) (derate 38.5mW/C above +70C).............................4400mW Operating Temperature Range.......................... -40C to +125C Junction Temperature........................................Internally Limited Storage Temperature Range............................. -65C to +150C Lead Temperature (soldering, 10s).................................. +300C Soldering Temperature (reflow)........................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) Junction-to-Ambient Thermal Resistance (JA)...............18C/W Junction-to-Case Thermal Resistance (JC)......................1C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VDD = 10V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 24V, V5 = 5V, VL = 3.3V, and TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 36 V DC CHARACTERISTICS VDD Supply Voltage VDD Supply Current VDD IDD VDD Disable Supply Current IDD_DIS VDD Undervoltage-Lockout Threshold VDD_ UVLO VDD Undervoltage-Lockout Hysteresis VDD_ V5 Supply Voltage V5 Supply Current UVHYS EN = high, O_ in push-pull mode and unloaded 0.7 1.5 EN = high, O_ in high-side mode and unloaded 0.7 1.5 EN = low 0.7 1.5 mA 7.8 8.5 V V5 = 5V, VDD rising I5 V5_UVLO V5 Undervoltage-Lockout Hysteresis V5_UVHYS V5 POR Threshold V5_POR VL Supply Voltage VL VL Supply Current IL VL POR Threshold VL_POR mA 7.0 V5 = 5V V5 V5 Undervoltage-Lockout Threshold www.maximintegrated.com 10 2.5 4.5 O_ in push-pull or high-side mode, CS = high, DC output VDD = 24V, V5 rising 3.8 VDD = 24V 5.5 V 0.9 1.5 mA 4 4.2 V 0.3 1.6 V 2.4 V 5.5 V 9 40 A 1.6 2.4 V 2.5 Logic inputs unconnected V Maxim Integrated 2 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Electrical Characteristics (continued) (VDD = 10V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 24V, V5 = 5V, VL = 3.3V, and TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 85 165 m 1.7 2.0 A +20 A DRIVER OUTPUTS (O_) High-Side Mode On-Resistance RON_HS High-side mode, EN = high, O_ = high, IO_ = 500mA High-Side Mode Current Limit ILIM_HS High-side mode, EN = high, O_ = high 1.4 High-Side Mode Leakage Current ILKG_HS EN = low, VO_ = 0V -1 Push-Pull Mode On-Resistance RON_PP Push-pull mode, EN = high IO_ = +50mA, O_ = high 1.6 4 5.2 10 0V < VO_ < VDD - 3V, O_ = high 200 ILIM_PP Push-pull mode, EN = high, during blanking time IO_ = -50mA, O_ = low 3V < VO_ < VDD, O_ = low 200 Push-Pull Current Limit 500 mA 300 Current-Limit Autoretry Blanking Time tBLANK Push-pull mode, EN = high, O_ connected to VDD or PGND 90 s Current-Limit Autoretry Off-Time tRETRY Push-pull mode, EN = high, O_ connected to VDD or PGND 11 ms OPEN-LOAD DETECTION (O_) Open-Load Pullup Current Open-Load and Status-Detect Threshold IOL VTOL_ High-side mode, O_ = off, 0V < VO_ < (VDD - 2V), OL detect = on 65 80 110 A EN = high, OL detect = on, high-side mode, O_ = off 6.3 7 7.7 V LOGIC INPUTS (IN_, PUSHPL, FLTR, SRIAL, CLK, SDI, CS, EN) Input Logic-High Voltage VIH Input Logic-Low Voltage VIL 0.7 x VL 0.3 x VL 0.1 x VL Input Threshold Hysteresis VITHYS Input Pulldown/Pullup Resistor RPULL (Note 3) Open-Drain Output Logic-Low Voltage VODL ISINK = 5mA LOGIC OUTPUTS (FAULT, CERR/IN4, SDO) Open-Drain Output Leakage Current ILKG_OD SRIAL = high, output not asserted, VOUT = 5.5V SDO Output Logic-High Voltage VOH ISOURCE = 5mA SDO Output Logic-Low Voltage VOL ISINK = 5mA SDO Pulldown Resistor www.maximintegrated.com RSDO V CS = high 140 200 -1 V 270 k 0.33 V +1 A VL - 0.33 140 V V 200 0.33 V 270 k Maxim Integrated 3 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Electrical Characteristics (continued) (VDD = 10V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 24V, V5 = 5V, VL = 3.3V, and TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tPDHS_LH High-side mode, delay from IN_ transition (parallel mode) or CS rising-edge (serial mode) to O_ rising by 0.5V; RL = 48, CL = 1nF, tR/tF 20ns, FLTR = low, Figure 1 (Note 4) 0.2 1 s tPDHS_HL High-side mode, delay from IN_ transition (parallel mode) or CS rising-edge (serial mode) to O_ falling by 0.5V, RL = 48, CL = 1nF, tR/tF 20ns, FLTR = low, Figure 1 (Note 4) 0.9 2 s tPDPP_LH Push-pull mode, delay from IN_ transition (parallel mode) or CS rising-edge (serial mode) to O_ settling to within 0.8 x VDD, RL = 5k, CL = 1nF, FLTR = low, Figure 2 0.3 0.7 s tPDPP_HL Push-pull mode, delay from IN_ transition (parallel mode) or CS rising-edge (serial mode) to O_ settling to within 0.2 x VDD, RL = 5k, CL = 1nF, FLTR = low, Figure 2 0.3 0.8 s High-side mode, 20% to 80%, RL = 48, CL = 1nF, Figure 1 1.5 4 Push-pull mode, 20% to 80%, RL = 5k, CL = 1nF, Figure 2 0.1 0.4 Push-pull mode, 20% to 80%, RL = 240, VCC = 24V, CL = 1nF, Figure 2 0.1 0.4 TIMING CHARACTERISTICS High-Side Mode LTH Output Propagation Delay High-Side Mode HTL Output Propagation Delay Push-Pull Output LTH Propagation Delay Push-Pull Output HTL Propagation Delay Output Rise and Fall Time Output Switching Rate Channel-to-Channel Skew CRC Error-Detect Propagation Delay CRC Error-Clear Propagation Delay Pulse Length of Rejected Glitch tR, tF fO tPDSK_LH, tPDSK_HL tPDL_ CERR tPDH_CERR tGL Admitted Pulse Length Glitch Filter Propagation Delay Time www.maximintegrated.com tPDGF Push-pull mode, RL = 5k or IL = 100mA to ground, CL = 1nF, SRIAL = low Push-pull mode, Figure 2 (Note 5) -100 s 100 kHz +100 ns Error detected on SDI data, from CS rising-edge to CERR/IN4 falling-edge; ISOURCE = 5mA, Figure 3 14.5 30 ns Error cleared, from CS rising-edge to CERR/IN4 rising, ISOURCE = 5mA, Figure 3 17 40 ns 80 ns FLTR = high 0 FLTR = high 300 FLTR = high ns 140 300 ns Maxim Integrated 4 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Electrical Characteristics (continued) (VDD = 10V to 36V, V5 = 4.5V to 5.5V, VL = 2.5V to 5.5V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 24V, V5 = 5V, VL = 3.3V, and TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI TIMING CHARACTERISTICS (Figure 4) CLK Clock Period tCH+CL 50 ns CLK Pulse-Width High tCH 5 ns CLK Pulse-Width Low tCL 5 ns FLTR = low (Note 4) 5 CS Fall-to-CLK Rise Time tCSS SDI Hold Time tDH 5 ns SDI Setup Time tDS 5 ns Output Data Propagation Delay tDO CL = 10pF. CLK falling-edge to SDO stable tFT CL = 10pF SDO Rise and Fall Times CS Hold Time CS Pulse-Width High tCSH tCSPW FLTR = high (Note 4) ns 300 25 4 50 FLTR = low (Note 4) 50 FLTR = high 280 ns ns ns ns PROTECTION SPECIFICATIONS Channel Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis TC_SD TC_SD_HYS Global Thermal-Shutdown Threshold TG_SD Global Thermal-Shutdown Hysteresis TG_SD_HYS ESD Protection Note Note Note Note Temperature rising VESD Temperature rising +170 C 15 C 150 C 10 C O_ pins, Human Body Model (Note 6) 15 All other pins, Human Body Model 2 kV 2: 3: 4: 5: All units are production tested at TA = +25C. Specifications over temperature are guaranteed by design. All logic input pins except CS have a pulldown resistor. CS has a pullup resistor. Specifications are guaranteed by design; not production tested. Channel-to-channel skew is defined as the difference in propagation delays between channels on the same device with the same polarity. Note 6: Bypass VDD pins to AGND with a 1F capacitor as close as possible to the device for high-ESD protection. www.maximintegrated.com Maxim Integrated 5 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Test Circuits/Timing Diagrams VL 0.1F VL 1F VDD 1F V5 VDD V5 50 TEST SOURCE MAX14900E IN_/CS FLTR O_ PUSHPL AGND CL PGND VL RL VL IN_ 50% AGND CS 50% tPDHS_LH VDD AGND tPDHS_HL VDD tPDHS_LH 0.5V AGND VDD 80% O_ tPDHS_HL VDD - 0.5V O_ 0.5V AGND 50% VDD VDD - 0.5V O_ 50% 80% O_ AGND 20% AGND tR tF 20% tR tF Figure 1. High-Side Mode Timing Characteristics www.maximintegrated.com Maxim Integrated 6 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Test Circuits/Timing Diagrams (continued) VL 0.1F VL 1F V5 V5 MAX14900E IN_/CS TEST SOURCE O_ FLTR AGND CL PGND RL VL VL IN_ 50% AGND VDD VDD VDD PUSHPL 50 1F CS 50% tPDPP_LH 50% AGND tPDPP_HL VDD 0.8 x VDD O_ tPDPP_LH 50% tPDPP_HL 0.8 x VDD O_ 0.2 x VDD AGND VDD tPDSK_LH 0.2 x VDD AGND tPDSK_HL VDD 0.8 x VDD O_ 80% O_ AGND 0.2 x VDD AGND tR tF 20% tR tF Figure 2. Push-Pull Mode Timing Characteristics www.maximintegrated.com Maxim Integrated 7 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Test Circuits/Timing Diagrams (continued) VL CS 50% 0V 50% tPDH_CERR tPDL_CERR VL VL - 0.5V CERR/IN4 0.5V 0V Figure 3. CRC Error Detection Timing CS tCSS tCL tCH tCSH CLK tDS tDH SDI tDO SDO tFT Figure 4. SPI Timing Diagram www.maximintegrated.com Maxim Integrated 8 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Typical Operating Characteristics (VDD = +24V, V5 = VL = 5.0V, TA = +25C, unless otherwise noted.) 4 3 PUSH-PULL MODE HIGH-SIDE FET IO = 50mA 8 350 300 250 HIGH-SIDE MODE IO = 500mA 200 150 250 HIGH-SIDE MODE IO = 500mA 4 200 3 150 100 1 50 0 0 0 PROPAGATION DELAY vs. VDD PUSH-PULL PROPAGATION DELAY vs. TEMPERATURE 1000 900 1000 800 tPDPP_HL tPDPP_LH 400 1.0 0.9 0.8 tPDHS_LH VDD = 36V 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) www.maximintegrated.com tPDPP_HL VDD = 36V tPDPP_HL VDD = 24V tPDPP_HL VDD = 10V 500 400 300 200 tPDPP_LH t PDPP_LH VDD = 36V V = 24V DD tPDPP_LH VDD = 10V -40 -25 -10 5 20 35 50 65 80 95 110 125 IDD vs. VDD PUSH-PULL MODE O_ UNLOADED 1.0 0.9 0.8 0.7 0.7 0.6 0.6 IDD (mA) IDD (mA) tPDHS_LH VDD = 24V 600 TEMPERATURE (C) 800 tPDHS_LH VDD = 10V 700 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 PUSH-PULL MODE: RL = 5k, CL = 1nF HIGH-SIDE MODE: RL = 48, CL = 1nF 800 100 tPDHS_LH PUSH-PULL MODE RL = 5k, CL = 1nF MAX14900E toc06 600 MAX14900E toc04 TEMPERATURE (C) PUSH-PULL MODE: RL = 5k, CL = 1nF HIGH-SIDE MODE: RL = 48, CL = 1nF 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 VDD (V) PROPAGATION DELAY (ns) 1200 10 12 14 16 18 20 22 24 26 28 30 32 34 36 MAX14900E toc05 HIGH-SIDE PROPAGATION DELAY (ns) 300 2 1000 0 350 50 HIGH-SIDE PROPAGATION DELAY vs. TEMPERATURE 400 400 1 VDD (V) 600 5 450 100 0 1200 6 PUSH-PULL MODE HIGH-SIDE FET IO = 50mA 500 2 200 1400 7 PUSH-PULL MODE LOW-SIDE FET IO = 50mA MAX14900E toc02 400 VDD = 36V 0.5 0.4 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VDD (V) 0 IDD vs. TEMPERATURE PUSH-PULL MODE O_ UNLOADED VDD = 24V VDD = 36V MAX14900E toc07 5 9 RON vs. TEMPERATURE RON HIGH-SIDE MODE (m) 6 450 RON PUSH-PULL MODE () 7 1400 PROPAGATION DELAY (ns) PUSH-PULL MODE LOW-SIDE FET IO = 50mA 8 10 MAX14900E toc03 RON PUSH-PULL MODE () 9 500 RON HIGH-SIDE MODE (m) MAX14900E toc01 RON vs. VDD 10 VDD = 10V -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Maxim Integrated 9 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Typical Operating Characteristics (continued) (VDD = +24V, V5 = VL = 5.0V, TA = +25C, unless otherwise noted.) PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY 90 POWER DISSIPATION (mW) 70 60 80 70 50 40 30 20 10 0 90 IL = 100mA ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +25C POWER DISSIPATION (mW) 80 toc08 VDD = 24V 0.01 0.1 VDD = 30V VDD = 36V 1 10 50 40 30 20 VDD = 24V 10 0.01 1.4 1.0 IL = 10mA CL = 10nF ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +25C 0.8 1.2 VDD = 30V 0.4 VDD = 24V 0.2 0.01 0.1 1 10 1.0 180.0 POWER DISSIPATION (mW) 160.0 140.0 toc12 VDD = 30V 0.4 VDD = 24V 0.2 60.0 VDD = 24V 40.0 0.01 0.1 1 10 100 140.0 PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY WITH RC LOAD toc13 IL = 10mA CL = 1nF ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +85C 120.0 VDD = 36V 100.0 VDD = 30V 80.0 60.0 VDD = 24V 40.0 20.0 20.0 0.0 200.0 180.0 VDD = 30V 80.0 toc11 VDD = 36V 0.6 160.0 VDD = 36V 100.0 100 SWITCHING FREQUENCY (kHz) IL = 10mA CL = 1nF ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +25C 120.0 10 0.8 0.0 100 POWER DISSIPATION (mW) 200.0 1 IL = 10mA CL = 10nF ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +85C SWITCHING FREQUENCY (kHz) PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY WITH RC LOAD VDD = 36V PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY WITH RC LOAD 1.6 1.4 VDD = 36V 0.6 0.0 toc10 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 0.1 VDD = 30V SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY WITH RC LOAD toc09 IL = 100mA ONE CHANNEL SWITCHING ALL OTHER CHANNELS LOW TA = +85C 60 0 100 PP MODE POWER DISSIPATION vs. SWITCHING FREQUENCY 0.01 0.1 1 10 SWITCHING FREQUENCY (kHz) www.maximintegrated.com 100 0.0 0.01 0.1 1 10 100 SWITCHING FREQUENCY (kHz) Maxim Integrated 10 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Pin Configurations N.C. N.C. N.C. REXT EN V5 AGND FLTR N.C. N.C. N.C. 29 28 27 26 25 SRIAL 37 24 PUSHPL VDD 38 23 VDD O5 39 22 O4 PGND 40 21 PGND O6 41 VDD 42 VDD 43 18 VDD O7 44 17 O2 PGND 45 16 PGND O8 46 VDD 47 FAULT 48 20 O3 19 VDD MAX14900E 15 O1 EP* + 14 VDD 1 2 3 4 5 6 7 8 9 10 11 12 CERR/IN4 CRC/IN3 IN2 OL/IN1 13 VL SDO VDD PUSHPL 18 19 20 VDD VDD 21 22 23 24 14 15 16 17 O3 PGND O4 13 VL N.C. N.C. N.C. 30 SDI 12 FLTR 31 CLK OL/IN1 EP* 27 26 25 V5 AGND 32 CS 9 10 11 MAX14900E REXT EN 33 IN5 CERR/IN4 CRC/IN3 IN2 31 30 29 28 34 IN6 SDI SDO 5 6 7 8 35 S16/IN8 34 33 32 36 CNFG/IN7 2 3 4 N.C. N.C. N.C. N.C. N.C. 38 VDD 37 SRIAL 36 35 VDD O1 PGND O2 IN5 CS CLK 1 + S16/IN8 CNFG/IN7 IN6 45 PGND 44 O7 43 VDD 42 VDD 41 O6 40 PGND 39 O5 48 FAULT 47 VDD 46 O8 TOP VIEW QFN 7mm x 7mm TQFN 7mm x 7mm *CONNECT EP TO AGND. Pin Description PIN NAME FUNCTION S16/IN8 16-Bit Serial-Select Input/IN8 Input. In serial mode (SRIAL = high), drive S16/IN8 high to select 16-bit serial operation. Drive S16/IN8 low to select 8-bit serial operation. In parallel mode (SRIAL = low), S16/IN8 sets the O8 output on/off in high-side mode or high/low in push-pull mode. S16/IN8 has an internal 200k pulldown resistor. 2 CNFG/IN7 Configure Select Input/IN7 Input. In serial mode (SRIAL = high), drive CNFG/IN7 high to select perchannel configuration over the serial interface. Drive CNFG/IN7 low to select setting the O_ outputs over the serial interface. In parallel mode (SRIAL = low), CNFG/IN7 sets the O7 output on/off in high-side mode or high/low in push-pull mode. CNFG/IN7 has an internal 200k pulldown resistor. 3 IN6 IN6 Input. In parallel mode (SRIAL = low), IN6 sets the O6 output on/off in high-side mode or high/low in push-pull mode. IN6 has an internal 200k pulldown resistor. 4 IN5 IN5 Input. In parallel mode (SRIAL = low), IN5 sets the O5 output on/off in high-side mode or high/low in push-pull mode. IN5 has an internal 200k pulldown resistor. 5 CS SPI Chip-Select Input. CS is the SPI active-low chip select. CS has an internal 200k pullup resistor. 6 CLK Serial-Clock Input. CLK is the SPI serial-clock input (up to 20MHz) and has an internal 200k pulldown resistor. 7 SDI Serial-Data Input. SDI is the SPI serial-data input and has an internal 200k pulldown resistor. 8 SDO Serial-Data Output. SDO is the SPI serial-data output. SDO has an internal 200k pulldown resistor when CS is logic-high. 1 www.maximintegrated.com Maxim Integrated 11 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Pin Description (continued) PIN NAME FUNCTION 9 CERR/IN4 CRC Error Detection Output/IN4 Input. In serial mode (SRIAL = high) with error checking enabled (CRC/IN3 = high), CERR/IN4 is an active-low open-drain output that asserts when a CRC error is detected on SDI data. In parallel mode (SRIAL = low), CERR/IN4 sets the O4 output on/off in high-side mode or high/low in push-pull mode. CERR/IN4 has an internal 200k pulldown resistor when SRIAL = 0. 10 CRC/IN3 CRC Enable Input/IN3 Input. In serial mode (SRIAL = high), drive CRC/IN3 high to enable CRC generation/error detection on SPI data. In parallel mode (SRIAL = low), CRC/IN3 sets the O3 output on/off in high-side mode or high/low in push-pull mode. CRC/IN3 has an internal 200k pulldown resistor. 11 IN2 IN2 Input. In parallel mode (SRIAL = low), IN2 sets the O2 output on/off in high-side mode or high/low in push-pull mode. IN2 has an internal 200k pulldown resistor. Open-Load Enable Input/IN1 Input. In serial mode (SRIAL = high), drive OL/IN1 high to enable open-load detection on all eight O_ outputs that are configured in high-side mode, overriding the serial configuration. Drive OL/IN1 low to disable open-load detection unless enabled by the serial interface. In parallel mode (SRIAL = low), OL/IN1 sets the O1 output on/off in high-side mode or high/low in push-pull mode. OL/IN1 has a 200k pulldown resistor that is always connected. 12 OL/IN1 13 VL 14, 18, 19, 23, 38, 42, 43, 47 VDD 15 O1 16, 21, 40, 45 PGND 17 O2 Driver Output 2. May be configured as a high-side switch or push-pull output. 20 O3 Driver Output 3. May be configured as a high-side switch or push-pull output. 22 O4 Driver Output 4. May be configured as a high-side switch or push-pull output. Logic Supply Input. VL defines the logic levels on all I/O logic interface pins from 2.5V to 5.5V. Bypass VL to AGND with a 0.1F ceramic capacitor as close as possible to the device. Supply Voltage Input. VDD supply is 10V to 36V. Bypass the VDD pins to a ground plane with a 1F ceramic capacitor. Externally connect all VDD pins and ensure that the maximum trace resistance between each VDD pin is less than 10m. Driver Output 1. May be configured as a high-side switch or push-pull output. Power Ground. Connect PGND to the ground plane. Global Push-Pull/High-Side Select Input. In parallel mode (SRIAL = low), drive PUSHPL high to globally configure all O_ outputs to operate in push-pull mode, overriding the serial configuration. Drive PUSHPL low to configure all O_ outputs to operate in high-side mode unless configured as push-pull by the serial interface. PUSHPL has an internal 200k pulldown resistor. 24 PUSHPL 25-27, 33-36 N.C. No Connection. Not internally connected. 28 FLTR Glitch Filter Enable Input. Set FLTR high to enable glitch filtering on every logic input except SDI and CLK. FLTR has an internal 200k pulldown resistor. 29 AGND Analog Ground. Connect AGND to the ground plane. 30 V5 5V Supply Input. Bypass V5 to AGND with a 1F ceramic capacitor as close as possible to the device. 31 EN Enable Input. Drive EN high to enable normal operation for all O_ outputs. Drive EN low to force all O_ outputs into high-impedance mode. EN has an internal 200k pulldown resistor. 32 REXT www.maximintegrated.com External Resistor Connection. Connect a 56k 1% resistor from REXT to AGND. Maxim Integrated 12 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Pin Description (continued) PIN NAME FUNCTION Serial/Parallel Select Input. Drive SRIAL high to set and configure the O_ outputs through the serial interface. Drive SRIAL low to set the O_ outputs through the parallel (IN_) pins. SRIAL does not affect the read back of diagnostics/status information through the serial interface. SRIAL has an internal 200k pulldown resistor. 37 SRIAL 39 O5 Driver Output 5. May be configured as a high-side switch or push-pull output. 41 O6 Driver Output 6. May be configured as a high-side switch or push-pull output. 44 O7 Driver Output 7. May be configured as a high-side switch or push-pull output. 46 O8 Driver Output 8. May be configured as a high-side switch or push-pull output. 48 FAULT -- EP Global Fault Output. FAULT is an open-drain, active-low output that asserts when a fault condition (thermal shutdown, open-load, and/or overload protection) is detected on any O_ output. Exposed Pad. Connect EP to a large ground plane, which is electrically connected to PGND, using a via farm to minimize thermal impedance; not intended as an electrical connection point. Functional Diagram VL VDD V5 VL FLTR PUSHPL V5 UV MONITOR OL/IN1 IN6 PARALLEL INTERFACE MAX14900E DRIVE + MONITOR CONFIG AND SETTING SRIAL CS SDI O6 DRIVE + MONITOR DRIVE + MONITOR O5 O5 VDD O4 O3 O3 VDD O2 OPEN LOAD O2 VDD OVERLOAD OVERTEMP O4 VDD EN DIAGNOSTICS O7 O6 VDD EN DRIVE + MONITOR REXT VDD EN SERIAL INTERFACE SDO FAULT O7 EN S16/IN8 O8 EN DRIVE + MONITOR CNFG/IN7 CLK O8 VDD DRIVE + MONITOR CRC/IN3 IN5 DRIVE + MONITOR EN IN2 CERR/IN4 VDD VDD DRIVE + MONITOR O1 O1 EN AGND www.maximintegrated.com PGND Maxim Integrated 13 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Table 1. Serial/Parallel Operating Modes SDI DATA SDO DATA SRIAL S16/IN8 CNFG/ IN7 SETTING CONFIG FAULT STATUS Parallel mode with optional SPI configuration, diagnostics, and monitoring 0 X X N/A 16-bit 8-bit 8-bit 8-bit serial mode with SPI setting and diagnostics 1 0 0 8-bit N/A 8-bit N/A 8-bit serial mode with SPI configuration and diagnostics 1 0 1 N/A 8-bit 8-bit N/A 16-bit serial mode with SPI setting, configuration, diagnostics, and monitoring 1 1 0 8-bit 8-bit 8-bit 8-bit 16-bit serial mode with SPI configuration, diagnostics, and monitoring 1 1 1 N/A 16-bit 8-bit 8-bit OPERATING MODE X = Don't care Detailed Description The MAX14900E is an octal low-propagation delay 850mA high-side switch that can be operated as a pushpull driver with high switching-rate capability. Each channel can be configured to operate in high-side or push-pull mode. Push-pull mode drives capacitive loads such as long cables that need to be driven at high switching rates. In high-side mode, each channel switches up to 850mA load current with 165m (max) on-resistance. The MAX14900E's switches/drivers are configured either individually by a serial SPI interface and/or globally by a parallel interface. In parallel operating mode (SRIAL = low), the IN_ inputs directly control the O_ outputs and the SPI interface configures each channel and reads back diagnostic and state status. In serial operating mode (SRIAL = high), the SPI interface is used to configure and set the state of each channel while the parallel inputs provide optional configuration possibilities. Current limiting, overload protection, and thermal shutdown circuitry protect each switch/driver. The device features per-channel diagnostic detection that feeds back per-channel thermal shutdown and output state information. In high-side mode, multiple channels can be connected in parallel to achieve higher load currents. Serial/Parallel Operating Modes A serial SPI and parallel interface allow configuration, monitoring, and driving of the MAX14900E. The serial interface supports per-channel configuration, setting, and diagnostics/monitoring while the parallel interface allows direct driving of the switches/outputs. Table 1 details how www.maximintegrated.com Table 2. Parallel Driving Truth Table IN_ O_ STATE PUSH-PULL HIGH-SIDE 0 Low Off 1 High On the device utilizes each interface depending on the status of the configuration select inputs. Parallel Operating Mode In parallel operating mode (SRIAL = low), the eight IN_ inputs directly set the O_ switches on/off in high-side mode or high/low in push-pull mode (Table 2). The serial interface can optionally be used to configure each output as a high-side switch or as a push-pull driver and to enable open-load detection for each high-side switch. The serial interface can also be used in parallel mode to read out per-channel fault, open-load detection, and output logic state information. The outputs can be configured globally for push-pull operation by the PUSHPL input. Global diagnostic fault and open-load information is reported by the FAULT output. Serial Operating Mode In serial operating mode (SRIAL = high), the switches/ drivers are set, configured, and monitored by the SPI interface. The S16/IN8, CNFG/IN7, CRC/IN3, and OL/IN1 inputs and the CERR/IN4 output provide further configuration and monitoring options in serial operating mode. The remaining IN_ inputs are not used. See the Serial Controller Interface section for more information. Maxim Integrated 14 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Configuration The global configuration inputs affect all eight O_ channels while serial configuration is per channel. See Table 3. The serial interface can be used to configure each output individually to be in push-pull or high-side mode and to enable open-load detection for that channel if it is in highside mode. The PUSHPL and OL/IN1 inputs override the per-channel serial configuration when they are set high. Output Drivers The drivers can be configured for high-side or push-pull operation. When configured in high-side mode, each driver can safely source 850mA (max) load current continuously. The high-side switches have active current limiting in the range between 1.4A (min) and 2.0A (max). When a driver is in push-pull mode, the output drives resistive/capacitive loads at high switching rates with load currents up to 100mA to ground. The RON is 4 (max) for the high-side and 10 (max) for the low-side drivers in push-pull mode. Monitoring the Output Logic State The voltage state of each O_ driver/switch can be read out via SPI. If the voltage on an O_ output is higher than the 7V (typ) threshold, then the corresponding S_ bit is logic 1 in the status byte. If the voltage on an O_ output is below the threshold, then the corresponding S_ bit is logic 0. Status monitoring can be read out via 16-bit serial mode. This is possible on all modes and states of the outputs: on/off/high/low. Open-Load Detection When configured in high-side mode, the device can detect when no load is connected to the O_ outputs or when a wire to a load is open circuit. Open-load detection can be globally enabled in serial mode via the OL/IN1 input, or on a per-channel basis via the serial interface in parallel and serial modes. The detection circuitry applies an 80A current to the load and monitors the O_ voltage. Openload detection occurs when the outputs are configured in high-side mode and is active while the high-side driver is off. When an open-load condition is detected on a high-side switch, the corresponding switch's fault bit is set and the global FAULT output is asserted. Turning off a high-side driver that has a large capacitive load and low bleed resistance triggers a temporary detection of an open-load condition and assert FAULT until the O_ voltage decays to below the 7V (typ) threshold. Table 3. Global Configuration Inputs INPUT SRIAL CONFIGURATION FUNCTION FLTR X Enables anti-glitch filtering on all logic input pins except SDI and CLK 0 = Glitch filtering disabled 1 = Glitch filtering enabled PUSHPL X Configures all O_ outputs as push-pull or high-side 0 = All drivers high-side mode unless configured as push-pull by serial interface 1 = All drivers push-pull mode EN X Enables normal operation of all O_ outputs 0 = All O_ outputs high impedance 1 = Normal operation OL/IN1 1 Enables global open-load detection in serial mode 0 = Open-load detection disabled unless enabled by serial interface 1 = Open-load detection enabled for all high-side mode switches CRC/IN3 1 Enables CRC generation and error detection of SPI data 0 = CRC disabled 1 = CRC enabled X = Don't care www.maximintegrated.com Maxim Integrated 15 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Thermal Shutdown Protection Thermal overload circuitry constantly monitors each switch/driver and a global thermal shutdown circuit monitors average chip temperature. When a local thermal shutdown condition occurs for one of the drivers, it is disabled while the others continue to operate. When the local temperature falls to below the activation threshold (TC_SD - TC_SD_HYS), that driver automatically re-enables. A global thermal shutdown does not disable the O_ outputs but prevents any channel from re-enabling itself until the global temperature sensor is below the limit. The FAULT output is asserted when any thermal shutdown condition occurs. In addition, F_ bits are set for channels that are in thermal shutdown in the SPI SDO data. Overload and Short-Circuit Protection The device protects each O_ output against overload and short-circuit conditions while operating in push-pull and high-side mode. In high-side mode, the device actively limits each channel's output current to 1.7A. As long as no thermal shutdown occurs, this current limiting condition persists continuously. In push-pull mode, the device limits the load current to 300mA/500mA (typ). Overload faults are detected when an O_ output is in push-pull mode and an overcurrent condition forces the output voltage to above 1V (for O_ = low) or below (VDD - 1V) (for O_ = high) for more than the blanking time 90s (typ). When the cause of the output voltage level mismatch is removed, the driver resumes normal operation. POR and UVLO Conditions The MAX14900E features undervoltage lockout (UVLO) and power-on reset (POR) circuitry on its power supply inputs to ensure that the device is in a known state on power-up or when there is a droop on one of the supplies. If either VL or V5 falls to below its POR threshold, the device goes into its reset state and all configuration settings are lost. www.maximintegrated.com When VDD or V5 is below its UVLO threshold, all O_ outputs are disabled and the 80A open-load detection current sources are turned off. The device resumes normal operation when the UVLO condition is removed. As long as VL and V5 stay above their POR thresholds, the SPI interface remains active and configuration settings are not affected. In 16-bit serial mode when a UVLO is present, a series of all ones in the serial SDO status/fault read back bits reports this condition. FAULT Output The global FAULT output asserts when a fault condition is detected on any O_ output. The types of fault conditions reported by FAULT are thermal shutdown, open-load (if enabled), and overload protection (in push-pull mode only). The global FAULT is not initiated in a UVLO condition. Thermal shutdown faults are detected when the internal temperature of any driver exceeds the thermal shutdown threshold (TC_SD). The fault is cleared when the temperature falls to below the activation threshold (TC_SD - TC_SD_HYS). Open-load faults are detected when the voltage at an O_ output in high-side mode with the HS switch turned off is above the detection threshold of 7V. This happens when the O_ output is not connected to any external load and the 80A pullup current charges the node. A brief openload condition can occur after an HS switch is turned off and the load has not discharged capacitance yet. In push-pull mode, if the voltage level at an O_ output differs from the programmed value for longer than the 90s (typ) blanking time due to overcurrent, the driver is turned off for the 11ms (typ) retry time. During the retry period, the FAULT output is asserted and the fault bit is set for that driver in the serial data. The fault is cleared after the fault condition is removed at the end of the current retry period (11ms). Maxim Integrated 16 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Serial Controller Interface and status information is sampled and stored in the internal SPI shift register and the SDO output becomes active. This data is clocked out of SDO on each falling CLK edge while new SDI data is sampled and stored in the shift register on each rising CLK edge. When CS transitions high at the end of the SPI cycle, the current data in the SPI shift register is latched into the MAX14900E and the new configuration and/or setting data changes the driver states. Figure 6 illustrates the sampling of internal signals dependent on CS transitions. The MAX14900E can be configured, controlled and/or monitored on a per-channel basis via its SPI interface (see Table 1). Daisy-chaining multiple MAX14900E devices is supported to reduce the required number of CS and/ or isolator pins. Figure 5 shows an example of daisychaining two MAX14900E devices. Daisy-chaining operates both with 8-bit and 16-bit serial data: S16/IN8 = X. The MAX14900E uses SPI mode 0 with CPOL = 0 and CPHA = 0. When the CS input transitions low, diagnostics SCLK MAX14900E CLK C MOSI SDI CS MAX14900E CLK D A T A B I T S S H I F T R E G D I A G N S T C SDO SDI CS D A T A B I T S S H I F T R E G D I A G N S T C SDO CS MISO Figure 5. Daisy-Chained MAX14900E Devices with 8-Bit Serial Mode CS DIAGNOSTICS /STATUS LATCHED OUTPUT PREVIOUS STATE NEW STATE Figure 6. Internal Sampling Events Timing Diagram www.maximintegrated.com Maxim Integrated 17 MAX14900E Octal, High-Speed, Industrial, High-Side Switch 8-Bit Serial Mode with Setting and Monitoring In serial mode with 8-bit setting and 8-bit monitoring (SRIAL = high, S16/IN8 = low, CNFG/IN7 = low), the SPI shift register is 8 bits long (Figure 7). The DO_ bits set the state of the respective O_ output (Table 4). The F_ bits report fault information of the respective O_ output (Table 7). 8-Bit Serial Mode with Configuration and Monitoring In serial mode with 8-bit configuration and 8-bit monitoring (SRIAL = high, S16/IN8 = low, CNFG/IN7 = high), the SPI shift register is 8 bits long (Figure 8). The C_ bits configure push-pull/high-side mode for the respective O_ output (Table 5). The F_ bits report fault information for the respective O_ output (Table 7). CS CLK DO8 SDI SDO Hi-Z F8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 F7 F6 F5 F4 F3 F2 F1 C7 C6 C5 C4 C3 C2 C1 F7 F6 F5 F4 F3 F2 F1 Figure 7. Serial Timing in 8-Bit Setting Serial Mode CS CLK C8 SDI SDO Hi-Z F8 Figure 8. Serial Timing in 8-Bit Configuration Serial Mode www.maximintegrated.com Maxim Integrated 18 MAX14900E Octal, High-Speed, Industrial, High-Side Switch 16-Bit Serial Mode with 8-Bit Setting/8-Bit Configuration In serial mode with 8-bit setting/8-bit configuration and 16-bit monitoring (SRIAL = high, S16/IN8 = high, CNFG/ IN7 = low), the SPI shift register is 16 bits long (Figure 9). The DO_ bits set the state of the respective O_ output and the C_ bits configure push-pull/high-side mode (Table 4 and Table 5). The F_ and S_ bits report the status information for each channel (Table 8). Parallel Mode/16-Bit Serial Mode with 16-Bit Configuration In parallel and serial mode with 16-bit serial configuration and 16-bit monitoring (SRIAL = low or SRIAL = high, S16/ Table 4. Serial Setting Truth Table Setting, Configuration, and Monitor Bit Definitions Table 3 to Table 8 define the effects of the setting, configuration, and monitoring bits. If PUSHPL = high, then all outputs are configured as push-pull mode regardless of C_. Table 5. 8-Bit Serial Configuration Truth Table O_ STATE DO_ IN8 = high, CNFG/IN7 = high), the SPI shift register is 16 bits long (Figure 10). The C1_ and C0_ bits configure push-pull/high-side mode and open-load detection for each respective channel (Table 6). The F_ and S_ bits report the status information for each channel (Table 8). PUSH-PULL OPERATION HIGH-SIDE OPERATION C_ O_ CONFIGURATION 0 Low Off 0 High-side mode 1 High On 1 Push-pull mode CS CLK SDI SDO Hi-Z DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 C8 C7 C6 C5 C4 C3 C2 C1 F8 F7 F6 F5 F4 F3 F2 F1 S8 S7 S6 S5 S4 S3 S2 S1 Figure 9. 16-Bit Serial Timing with 8-Bit Setting/8-Bit Configuration CS CLK SDI SDO Hi-Z C18 C17 C16 C15 C14 C13 C12 C11 C08 C07 C06 C05 C04 C03 C02 C01 F8 F7 F6 F5 F4 F3 F2 F1 S8 S7 S6 S5 S4 S3 S2 S1 Figure 10. 16-Bit Serial Timing with 16-Bit Configuration www.maximintegrated.com Maxim Integrated 19 MAX14900E Octal, High-Speed, Industrial, High-Side Switch 16-Bit Serial Configuration Open-load detection is only available for outputs configured in high-side mode. If PUSHPL = high, then all outputs are configured as push-pull mode regardless of the C_ bits. In serial modes, if OL/IN1 = high, then all outputs that are configured as high side will have open-load detect on, regardless of the C1_ bits. 8-Bit Serial Diagnostics If a driver is configured in push-pull mode, then a fault means that an overload or a thermal shutdown is present on that channel. If the driver is configured in highside mode, then a fault means that an overtemperature condition is detected. If open-load detection is enabled in high-side mode, then the F_ bit is set when either an open-load (only possible with the high-side switch off) or an overtemperature is detected. In a UVLO condition, eight F_ bits are logic one. 16-Bit Serial Diagnostics Logic-level status (S_bits) detection is only valid when no fault is present. Each S_ bit in normal (no fault) operating condition reports whether or not the O_ voltage is above (= 1) or below (= 0) 7V (typ). When all F_ and S_ bits are logic one, a UVLO condition is present. Table 6. 16-Bit Serial Configuration Truth Table C1_ C0_ O_ CONFIGURATION 0 0 High-side mode, open-load detect off 0 1 Push-pull mode 1 0 High-side mode, open-load detect on 1 1 Push-pull mode Table 7. 8-Bit Diagnostics Truth Table F_ O_ CONDITION 0 No fault present 1 Fault (overload, open load, or UVLO) present Table 8. 16-Bit Serial Diagnostics Truth Table F_ S_ O_ STATUS 0 0 No fault detected, logic state of O_ is low 0 1 No fault detected, logic state of O_ is high 1 0 Fault detected, logic state not defined 1 1 UVLO detected www.maximintegrated.com CRC Error Checking on Serial Interface In serial mode (SRIAL = high), CRC error detection can be enabled by setting CRC/IN3 high to minimize incorrect operation due to noise on the SDI/SDO/CLK signals. With CRC error detection enabled, the MAX14900E detects errors on the SDI data that it receives from the controller and it calculates a CRC on the SDO data that it sends to the controller and appends this check byte to the SDO data. This ensures that both the SPI data sent and received by the MAX14900E has a low likelihood of undetected errors. The check byte appended to all 8-bit/16-bit SDO data by the MAX14900E contains a 7-bit frame check sequence (FCS). This FCS is based on the CRC generator polynomial x7 + x5 + x4 + x2 + x + 1. The CRC initialization condition is 0x7F. The MAX14900E in turn expects a check byte appended to all 8-/16-bit SDI data that it receives containing a FCS based on the same polynomial (Figure 11). The controller should calculate the 7 FCS bits (CRI_) on the 8-/16-bit data including the logic 1 in the first position of the check byte. Thus the CRC is calculated on 9 or 17 bits. CRI1 is the LSB of the FCS. The MAX14900E verifies this received CRC. If the MAX14900E detects CRC errors on the received SDI data, then it ignores this data and does not change its configuration and/or output setting. Instead, the CERR/IN4 output is asserted and the ERR bit is set in the check byte that it appends to the 8-/16-bit SDO diagnostic/status data that it sends back to the controller during the following serial communication cycle (Figure 12). ERR is the error feedback bit that is sent back to the controller to signal that a CRC error was detected on the CS CLK SDI 1 CRI7 CRI6 CRI5 CRI4 CRI3 CRI2 CRI1 Figure 11. CRC Check Byte Expected From Controller CS CLK SDO ERR CRO7 CRO6 CRO5 CRO4 CRO3 CRO2 CRO1 Hi-Z Figure 12. CRC Check Byte Sent by MAX14900E Maxim Integrated 20 MAX14900E Octal, High-Speed, Industrial, High-Side Switch previous SDI data reception. Note that ERR is delayed by one SPI cycle, i.e., it indicates that a CRC error was detected in the previous SPI data cycle. The CERR/IN4 output is immediately set active when a CRC error is detected, allowing the controller to resend the last SDI data or take other action. The CRO_ bits are the CRC bits that the MAX14900E calculates on the 8-/16-bit diagnostics and/or status data plus the ERR bit i.e., the output FCS is calculated on 9/17 bits. This allows the controller to detect errors on the SDO data received from the MAX14900E. Applications Information Driving Inductive Loads In high-side mode, when the high-side switch turns off, an inductive load will cause the O_ voltage to swing negative in order to continue sourcing the load's inductive current while the inductor field collapses. The internal diodes support turn-off of inductive loads of up to 1.5H and currents of up to 1.9A. Driving Lamp Loads Lamp loads are incandescent lamps where the filament resistance is strongly dependent on the filament's temperature. The initial startup current is high because a cold filament has a very low resistance. The MAX14900E will reliably turn on 15W lamps over the operating temperature range. Driving Capacitive Loads When charging/discharging purely capacitive loads with a push-pull driver, the driver dissipates power that is proportional to switching frequency. The power can be estimated by PD ~ C x VDD2 x f, where C is the load capacitance, VDD is the supply voltage, and f is the switching frequency. For example, in an application with a 1nF load and 100kHz switching frequency, each driver dissipates 130mW at VDD = 36V. When driving purely capacitive loads consider a maximum capacitance of around 10nF. Multiple SPI Devices on Shared Bus The SDO output is high impedance when CS is logichigh to allow connecting multiple devices in parallel on a shared SPI bus with the SDO lines connected together. When SDO is high impedance, an internal 200k pulldown resistor is enabled to pull SDO to GND weakly. Paralleling of Outputs In high-side mode, multiple outputs can be connected together in parallel to achieve higher load currents. The total load current should be shared equally between these high-side switches that are operated in parallel. This is achieved by having identical trace resistances for all the PCB tracks from the O_ pins to the common star www.maximintegrated.com connection point. This is particularly important, since the on-resistance of each high-side switch is low: 85m (typ). Board Layout High-speed switches require proper layout and design procedures for optimum performance. Ensure that powersupply bypass capacitors are placed as close as possible to the device. Connect all VDD pins to a VDD plane. Ensure that all VDD pins have no more than 10m between them. In this case a 1F capacitor should be placed to the ground plane as close to the VDD pins as possible. In the case low resistance paths are not possible between the VDD pins, bypass each pin to GND via a 100nF capacitor. A suppressor/TVS diode should be used between VDD and GND to clamp high-surge transients on the VDD supply input and surges from the O_ outputs. The standoff voltage should be higher than the maximum operating voltage of the equipment while the breakdown voltage should be around 40V. As long field supply cables can generate large voltage transients on the VDD supply due to large di/dt, it is recommended to add a large capacitor on VDD at the point of field supply entry. Capacitance should be as large as possible, but 47F electrolytic capacitor is recommended as a minimum. High ESD Protection Electrostatic discharge (ESD)-protection structures are incorporated on all pins to protect against electrostatic discharges up to 2kV Human Body Model (HBM) encountered during handling and assembly. All O_ outputs are further protected against ESD up to 15kV (HBM) without damage, when the part is operative in the application circuit with a 1F bypass capacitor on VDD and a suppressor/TVS diode. In order to achieve even higher ESD levels, connect external diodes from each output to GND and to VDD as described in the Surge Protection section. Surge Protection The MAX14900E O_ pin is tolerant to 600V/(42 + 0.5F) 1.2s/50s surge testing, when only using a TVS diode on VDD and without protection diodes on the O_ pins. It achieved over 1.5kV/(42 + 0.5F) IEC610004-5 surge testing when using the Typical Operating Circuit. The silicon diodes on O_ must have low forward voltage diodes that support the surge currents, like MURA205T3G. A surge-suppressor diode on the VDD supply must have low output impedance at the high surge currents. The SM30TY is suitable for this. Place all diodes and the VDD capacitor as close to the MAX14900E pins as possible. Maxim Integrated 21 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Typical Operating Circuit 24V 24V 36V TVS 47F 1F 24V 5V STEP-DOWN VDD SRIAL MAX15062 O1 V5 10k O2 O3 FAULT SDI MAX14900E 02 24V EN 100nF 01 24V VL 03 24V O4 04 24V CS O5 CLK 3.3V VDDA O6 VDDB CONTROLLER O7 SDO ISOLATION MAX14850 GPIO 56k REXT AGND GND PUSHPL 5V GNDA 06 24V CNFG VDDA SPI 05 24V PGND 07 24V O8 08 24V GNDB 36V TVS 1F 24V VDD V5 VL O1 SRIAL 24V 09 EN SDI O2 CNFG FAULT O3 MAX14900E O4 CS O6 SDO 56k www.maximintegrated.com REXT AGND 24V O7 PUSHPL PGND O8 11 12 24V O5 CLK 10 24V 24V 13 14 24V 24V 15 16 Maxim Integrated 22 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Ordering Information Chip Information TEMP RANGE (C) PINPACKAGE MAX14900EAGM+CKT -40 to +125 48 QFN-EP** MAX14900EAGM+TCKT -40 to +125 48 QFN-EP** MAX14900EAGM+CKH -40 to +125 48 TQFN-EP** MAX14900EAGM+TCKH -40 to +125 48 TQFN-EP** PART PROCESS: BiCMOS +Denotes a lead(Pb)-free/RoHS-compliant package. T =Tape and reel. **EP = Exposed pad. www.maximintegrated.com Maxim Integrated 23 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 48 QFN K4877+1 21-100009 90-100003 48 TQFN T4877+6 21-0144 90-0130 www.maximintegrated.com Maxim Integrated 24 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 25 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 26 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 27 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 28 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 29 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated 30 MAX14900E Octal, High-Speed, Industrial, High-Side Switch Revision History REVISION NUMBER REVISION DATE 0 3/13 Initial release 1 6/14 Added new features 2 11/14 Changed current limit and added TQFN package option 3 1/15 Updated General Description, Benefits and Features, Ordering Information, and Package Information sections 4/15 Updated Functional Diagram and Maximum Power Dissipation in the Absolute Maximum Ratings section, corrected mislabeled axis and symbols in Typical Operating Characteristics, and added the Paralleling of Outputs section under Applications Information 4 PAGES CHANGED DESCRIPTION -- 1, 4, 5, 7, 9, 10, 12, 14, 15, 17-21 1-3, 13, 16, 20-23 1, 23-30 1-2, 4, 10-11, 13, 15-18, 21 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2015 Maxim Integrated Products, Inc. 31