AMIS-30521 - AMI Semiconductor, Inc.

AMIS-30521 Micro-stepping Motor Driver Data Sheet

1.0 Introduction

The AMIS-30521 is a micro-stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and an

SPI interface with an external microcontroller. The AMIS-30521 contains a current-translation table and takes the next micro-step

depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The chip provides a

so-called “speed and load angle” output. This allows the creation of stall detection algorithms and control loops based on load-angle to

adjust torque and speed. It is using a proprietary PWM algorithm for reliable current control.

The AMIS-30521 is implemented in I2T100 technology, enabling both high-voltage analog circuitry and digital functionality on the same

chip. The chip is fully compatible with the automotive voltage requirements.

The AMIS-30521 is ideally suited for general-purpose stepper motor applications in the automotive, industrial, medical, and marine

environment.

2.0 Key Features

• Dual H-Bridge for 2-phase stepper motors

• Programmable peak-current up to 1.6A using a 5-bit current DAC

• On-chip current translator

• SPI interface

• Speed and load angle output

• Seven step modes from full-step up to 32 micro-steps

• Fully integrated current-sense

• PWM current control with automatic selection of fast and slow decay

• Low EMC PWM with selectable voltage slopes

• Active fly-back diodes

• Full output protection and diagnosis

• Thermal warning and shutdown

• Compatible with 5V and 3.3V microcontrollers

3.0 Ordering information

Table 1: Ordering Information

Part No. Package Peak Current Temp. Range Ordering Code

Tubes Ordering Code

Tapes

AMIS-30521 ANA NQFP-32 (7 x 7mm) 1600mA -40°C…..125°C 0C521-001-XTD 0C521-001-XTP

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

4.0 Block Diagram

Temp.

Sense

SPI OTP

Timebase

POR

CLK

NXT

SLA

DIR

ERR Band-

gap

Load

Angle

AMIS-30521

Logic &

Registers

Chargepump

CLR

PC20070322.1

VBB

I-sense

EMC

I-sense

EMC

VDD

GND

MOTXP

MOTXN

MOTYP

MOTYN

CPN CPP VCP

Figure 1: Block Diagram AMIS-30521

5.0 Pin Description

Table 2: Pin List and Description

Name Pin Description

DO 31 SPI data output

VDD 32 Logic Supply Input (needs external decoupling capacitor)

GND 1 Ground, heat sink

DI 2 SPI data in

CLK 3 SPI clock input

NXT 4 Next micro-step input

DIR 5 Direction input

ERRB 6 Error Output

SLA 7 Speed Load Angle Output

CPN 9 Negative connection of charge pump capacitor

CPP 10 Positive connection of charge pump capacitor

VCP 11 Charge-pump filter-capacitor

CLR 12 “Clear” = Chip Reset input

CSB 13 SPI chip select input

VBB 14 High Voltage Supply Input

MOTYP 15, 16 Negative end of phase Y coil output

GND 17, 18 Ground, heat sink

MOTYN 19, 20 Positive end of phase Y coil output

MOTXN 21, 22 Positive end of phase X coil output

GND 23, 24 Ground, heat sink

MOTXP 25, 26 Negative end of phase X coil output

VBB 27 High Voltage Supply Input

/ 8, 28, 30 No Function (to be left open in normal operation)

TST0 29 Test pin (to be tied to ground in normal operation) input

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

910111213141516

32 31 30 29 28 27 26 25

CPN

ERR

MOTXP

GND GND

MOTXP

MOTYN

MOTYP

CLK

VDD

CLR

DIR

NXT

SLA

AMIS-30521

PC20070309.2

GND

MOTYN

MOTXN

MOTYP

VBB

TSTO

CPP

VCP

VBB

Figure 2: Pin Out AMIS-30521

5.1 Package Thermal Characteristics

The NQFP is designed to provide superior thermal performance, and using an exposed die pad on the bottom surface of the package

partly contributes to this. In order to take full advantage of this thermal performance, the PCB must have features to conduct heat away

from the package. A thermal grounded pad with thermal vias can achieve this. With a layout as shown in Figure 3: PCB Ground Plane

Layout Condition, the thermal resistance junction – to – ambient can be brought down to a level of 30°C/W.

Figure 3: PCB Ground Plane Layout Condition

NQFP-32

PC20041128.2

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

6.0 Electrical Specification

6.1 Absolute Maximum Ratings

Stresses above those listed in table below may cause immediate and permanent device failure. It is not implied that more that one of

these conditions can be applied simultaneously.

Table 3: Absolute Maximum Ratings

Symbol Parameter Min. Max. Units

VBB Analog DC supply voltage (1) -0.3 +40 V

VDD Logic supply voltage -0.3 +7.0 V

Tstrg Storage temperature -55 +160 °C

Tamb Ambient temperature under bias -50 +150 °C

VESD Electrostatic discharges on component level (2) -2 +2 kV

Notes:

(1) For limited time <0.5s.

(2) Human body model (100pF via 1.5 kΩ, according to JEDEC EIA-JESD22-A114-B).

6.2 Recommend Operation Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the

chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of

time may affect device reliability.

Table 4: Operating Ranges

Symbol Parameter Min. Max. Unites

VBB Analog DC supply +6 +30 V

VDD Logic supply voltage 4.75 5.25 V

Iddd Dynamic current (1) 18 mA

Ta Ambient temperature VBAT≤+18 -40 +125 °C

Ta Ambient temperature VBAT≤+29 -40 +85 °C

Tj Junction temperature +160 °C

Notes:

(1) Dynamic current is with oscillator running, all analogue cells active. All outputs unloaded, no floating inputs.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

6.3 DC Parameters

The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents

flowing in the circuit are defined as positive.

Table 5: DC Parameters

Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit

Supply Inputs

VBB Nominal operating supply range 6 30 V

Ibat VBB Total current consumption Unloaded outputs 8 mA

Vdd VDD Logic supply voltage 4.75 5 5.25 V

Power-on-Reset (POR)

VDDH Internal POR comparator threshold VDD rising 4.0 4.25 4.4 V

VDDL VDD Internal POR comparator threshold VDD falling 3.68 V

Motordriver

IMDmax,Peak Max current through motor coil in

normal operation 1600 mA

IMDmax,RMS Max RMS current through coil in normal

operation 800 mA

IMDabs Absolute error on coil current -10 10 %

IMDrel Error on current ratio Icoilx / Icoily -7 7 %

Vbb = 12V, Tj = 27 °C 0.45 0.56 Ω

RHS On-resistance high-side driver,

CUR[4:0] = 0...31 Vbb = 12V, Tj = 160 °C 0.94 1.25 Ω

Vbb = 12V, Tj = 27 °C 0.45 0.56 Ω

RLS3 On-resistance low-side driver,

CUR[4:0] = 23...31 Vbb = 12V, Tj = 160 °C 0.94 1.25 Ω

Vbb = 12V, Tj = 27 °C 0.90 1.2 Ω

RLS2 On-resistance low-side driver,

CUR[4:0] = 16...22 Vbb = 12V, Tj = 160 °C 1.9 2.5 Ω

Vbb = 12V, Tj = 27 °C 1.8 2.3 Ω

RLS1 On-resistance low-side driver,

CUR[4:0] = 9...15 Vbb = 12V, Tj = 160 °C 3.8 5.0 Ω

Vbb = 12V, Tj = 27 °C 3.6 4.5 Ω

RLS0 On-resistance low-side driver,

CUR[4:0] = 0...8 Vbb = 12V, Tj = 160 °C 7.5 10 Ω

IMpd

MOTXP

MOTXN

MOTYP

MOTYN

Pull-down current HiZ mode 0.5 mA

Logic Inputs

Ileak Input leakage

(3) Tj = 160 °C 1 µA

VinL Logic low threshold 1.5 V

VinH

DI, CLK

NXT, DIR

CLR, CSB Logic high threshold 3.5 V

Rpd CLR

TST0 Internal pull-down resistor 120 300 kΩ

Thermal Warning and Shutdown

Ttw Thermal warning 138 145 152 °C

Ttsd

(1) (2) Thermal shutdown Ttw + 20 °C

Charge Pump

6V< VBB < 15V 2 * VBB – 2.5 V

Vcp Output voltage 15V < VBB < 30V VBB+12.5 VBB+14 VBB+15.5 V

Cbuffer

VCP

External buffer capacitor 180 220 470 nF

Cpump CPP CPN External pump capacitor 180 220 470 nF

Notes:

(1) No more than 100 cumulated hours in life time above Ttw.

(2) Thermal shutdown and low temperature warning are derived from thermal warning.

(3) Not valid for pins with internal pull-down resistor.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

6.4 A C Parameters

The AC parameters are given for VBB and temperature in their operating ranges.

Table 6: AC Parameters

Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit

Internal Oscillator

fosc Frequency of internal oscillator 3.6 4 4.4 MHz

Motordriver

PWM frequency 20.8 22.8 24.8 kHz

fPWM Double PWM frequency

Frequency depends only on

internal oscillator 41.6 45.6 49.6 kHz

fj PWM Jitter frequency tbd Hz

MOTxx

PWM Jitter depth tbd % fPWM

EMC[1:0] = 00 150 V/µs

EMC[1:0] = 01 100 V/µs

EMC[1:0] = 10 50 V/µs

Tbrise MOTxx turn-on voltage slope, 10% to 90%

EMC[1:0] = 11 25 V/µs

EMC[1:0] = 00 150 V/µs

EMC[1:0] = 01 100 V/µs

EMC[1:0] = 10 50 V/µs

Tbfall MOTxx turn-off voltage slope, 90% to 10%

EMC[1:0] = 11 25 V/µs

Digital Outputs

TH2L DO

ERRB Output fall-time from VinH to VinL Capacitive load 400pF and pull-

up resistor of 1.5 kΩ 50 ns

Charge Pump

fCP CPN CPP Charge pump frequency 250 kHz

TCPU MOTxx Start-up time of charge pump Spec external components

CLR Function

TCLR CLR Hard reset duration time 20 90 µs

6.5 SPI Timing

Table 7: SPI Timing Parameters

Symbol Parameter Min. Typ. Max. Unit

tCLK SPI clock period 1 µs

tCLK_HIGH SPI clock high time 100 ns

tCLK_LOW SPI clock low time 100 ns

tSET_DI DI set up time, valid data before rising edge of CLK 50 ns

tHOLD_DI DI hold time, hold data after rising edge of CLK 50 ns

tCSB_HIGH CSB high time 2.5 µs

tSET_CSB CSB set up time, CSB low before rising edge of CLK 100 ns

tSET_CLK CLK set up time, CLK low before rising edge of CSB 100 ns

DI VALID

CLK

tSET_CSB

PC20070608.1

tCLK

tCLK_HI tCLK_LO

tSET_DI tHOLD_DI

tSET_CLK

0,2 VCC

0,8 VCC

0,2 VCC

0,8 VCC

Figure 4: SPI Timing

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

7.0 Typical Application Schematic

AMIS-30521

PC20070604.11

VCP

CPP

CPN

CLR

ERR

GND

CLK

NXT

DIR

MOTXP

MOTXN

MOTYP

MOTYN

220 nF

100 nF

VBAT

VDD VBB

VBB

100 nF

220 nF

100 µF

C2C3

100 nF

SLA

µC

VDD

Figure 5: Typical Application Schematic AMIS-30521

Table 8: External Components List and Description

Component Function Typ. Value Tolerance Unit

C1 VBB buffer capacitor (1) 100 -20 +80% µF

C2, C3 V

BB decoupling block capacitor 100 -20 +80% nF

C4 VDD buffer capacitor 220 +/- 20 % nF

C5 V

DD buffer capacitor 100 +/- 20% nF

C6 Charge pump buffer capacitor 220 +/- 20% nF

C7 Charge pump pumping capacitor 220 +/- 20% nF

C8 Low pass filter SLA 1 +/- 20% nF

R1 Low pass filter SLA 5.6 +/- 1% kΩ

D1 Optional reverse protection diode e.g. 1N4003

Notes:

(1) Low ESR < 1Ohm.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

8.0 Functional Description

8.1 H-Bridge Drivers

A full H-bridge is integrated for each of the two stator windings. Each H-bridge consists of two low-side and two high-side N-type

MOSFET switches. Writing logic ‘0’ in bit <MOTEN> disables all drivers (high-impedance). Writing logic ‘1’ in this bit enables both

bridges and current can flow in the motor stator windings.

In order to avoid large currents through the H-bridge switches, it is guaranteed that the top- and bottom-switches of the same half-

bridge are never conductive simultaneously (interlock delay).

A two-stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly,

when excessive voltage is sensed across the transistor, the transistor is switched-off.

In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is

defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for

slope control (Table 25: SPI Control Parameter Overview EMC[1:0]).

The power transistors are equipped with so-called “active diodes”: when a current is forced trough the transistor switch in the reverse

direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of

the transistor instead of through the inherent parasitic drain-bulk diode of the transistor.

Depending on the desired current range and the micro-step position at hand, the Rdson of the low-side transistors will be adapted such

that excellent current-sense accuracy is maintained. The Rdson of the high-side transistors remain unchanged, see Table 5: DC

Parameters for more details.

8.2 PWM Current Control

A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a

digital regulation loop. This loop then generates a PWM signal, which turns on/off the H-bridge switches. The switching points of the

PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter

can be added (Table 14: SPI Control Register 1). The PWM frequency will not vary with changes in the supply voltage. Also variations

in motor-speed or load-conditions of the motor have no effect. There are no external components required to adjust the PWM

frequency.

8.2.1. Automatic Forward and Slow-Fast Decay

The PWM generation is in steady-state using a combination of forward and slow-decay. The absence of fast-decay in this mode,

guarantees the lowest possible current-ripple “by design”. For transients to lower current levels, fast-decay is automatically activated to

allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are

required for operation.

Icoil

Forward & Slow Decay Forward & Slow Decay

Fast Decay & Forward

Actual value

Set value

TPWM

PC20070604.1

Figure 6: Forward and Slow/Fast Decay PWM

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

8.2.2. Automatic Duty Cycle Adaptation

Incase the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the

requested average current in the coils. This process is completely automatic and requires no additional parameters for operation. The

over-all current-ripple is divided by two if PWM frequency is doubled (Table 14: SPI Control Register 1).

Actual value

Duty Cycle

< 50% Duty Cycle >50% Duty Cycle < 50%

Icoil

Set value

TPWM PC20070604.2

Figure 7: Automatic Duty Cycle Adaptation

8.3 Step Translator

8.3.1. Step Mode

The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL, and input

pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode.

One out of seven possible stepping modes can be selected through SPI-bits SM[2:0] (Table 26: SPI Control Parameter Overview

SM[2:0]) After power-on or hard reset, the coil-current translator is set to the default 1/32 micro-stepping at position ‘0’. Upon changing

the step mode, the translator jumps to position 0* of the corresponding stepping mode. When remaining in the same step mode,

subsequent translator positions are all in the same column and increased or decreased with 1. Table 10: Circular Translator Table lists

the output current versus the translator position.

As shown in Figure 8 the output current-pairs can be projected approximately on a circle in the (Ix,Iy) plane. There is, however, one

exception: uncompensated half step. In this step mode the currents are not regulated to a fraction of Imax but are in all intermediate

steps regulated at 100 percent. In the (Ix,Iy) plane the current-pairs are projected on a square. Table 9: Square Translator Table for

Umcompensated Half StepSM[2:0] = 101 lists the output current versus the translator position for this case.

Table 9: Square Translator Table for Umcompensated Half StepSM[2:0] = 101

Stepmode ( SM[2:0] ) % of Imax

101

Uncompensated Half-Step Coil x Coil y

0* 0 100

1 100 100

2 100 0

3 100 -100

4 0 -100

5 -100 -100

6 -100 0

7 -100 100

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Table 10: Circular Translator Table

Stepmode ( SM[2:0] ) % of Imax Stepmode ( SM[2:0] ) % of Imax

000 001 010 011 100 110 000 001 010 011 100 110

1/32 1/16 1/8 1/4 1/2 FS Coil x Coil y 1/32 1/16 1/8 1/4 1/2 FS Coil x Coil y

‘0’ 0* 0* 0* 0* - 0100 64 32 16 84 - 0-100

1 - - - - - 3.5 98.8 65 - - - - - -3.5 -98.8

2 1 - - -- 8.1 97.7 66 33 - - - - -8.1 -97.7

3 - - - - - 12.7 96.5 67 - - - - - -12.7 -96.5

4 2 1 - -- 17.4 95.3 68 34 17 -- - -17.4 -95.3

5 - - - - - 22.1 94.1 69 - - - - - -22.1 -94.1

6 3 - - -- 26.7 93 70 35 - - - - -26.7 -93

7 - - - - - 31.4 91.8 71 - - - - - -31.4 -91.8

8 4 2 1 -- 34.9 89.5 72 36 18 9- - -34.9 -89.5

9 - - - - - 38.3 87.2 73 - - - - - -38.3 -87.2

10 5 - - -- 43 84.9 74 37 - - - - -43 -84.9

11 - - - - - 46.5 82.6 75 - - - - - -46.5 -82.6

12 6 3 - -- 50 79 76 38 19 -- - -50 -79

13 - - - - - 54.6 75.5 77 - - - - - -54.6 -75.5

14 7 - - -- 58.1 72.1 78 39 - - - - -58.1 -72.1

15 - - - - - 61.6 68.6 79 - - - - - -61.6 -68.6

16 8 4 2 1 1 65.1 65.1 80 40 20 10 5 3 -65.1 -65.1

17 - - - - - 68.6 61.6 81 - - - - - -68.6 -61.6

18 9 - - -- 72.1 58.1 82 41 - - - - -72.1 -58.1

19 - - - - - 75.5 54.6 83 - - - - - -75.5 -54.6

20 10 5 - -- 79 50 84 42 21 -- - -79 -50

21 - - - - - 82.6 46.5 85 - - - - - -82.6 -46.5

22 11 - - -- 84.9 43 86 43 - - - - -84.9 -43

23 - - - - - 87.2 38.3 87 - - - - - -87.2 -38.3

24 12 6 3 -- 89.5 34.9 88 44 22 11 - - -89.5 -34.9

25 - - - - - 91.8 31.4 89 - - - - - -91.8 -31.4

26 13 - - -- 93 26.7 90 45 - - - - -93 -26.7

27 - - - - - 94.1 22.1 91 - - - - - -94.1 -22.1

28 14 7 - -- 95.3 17.4 92 46 23 -- - -95.3 -17.4

29 - - - - - 96.5 12.7 93 - - - - - -96.5 -12.7

30 15 - - -- 97.7 8.1 94 47 - - - - -97.7 -8.1

31 - - - - - 98.8 3.5 95 - - - - - -98.8 -3.5

32 16 8 4 2 - 100 096 48 24 12 6 - -100 0

33 - - - - - 98.8 -3.5 97 - - - - - -98.8 3.5

34 17 - - -- 97.7 -8.1 98 49 - - - - -97.7 8.1

35 - - - - - 96.5 -12.7 99 - - - - - -96.5 12.7

36 18 9 - -- 95.3 -17.4 100 50 25 -- - -95.3 17.4

37 - - - - - 94.1 -22.1 101 - - - - - -94.1 22.1

38 19 - - -- 93 -26.7 102 51 - - - - -93 26.7

39 - - - - - 91.8 -31.4 103 - - - - - -91.8 31.4

40 20 10 5 -- 89.5 -34.9 104 52 26 13 - - -89.5 34.9

41 - - - - - 87.2 -38.3 105 - - - - - -87.2 38.3

42 21 - - -- 84.9 -43 106 53 - - - - -84.9 43

43 - - - - - 82.6 -46.5 107 - - - - - -82.6 46.5

44 22 11 - -- 79 -50 108 54 27 -- - -79 50

45 - - - - - 75.5 -54.6 109 - - - - - -75.5 54.6

46 23 - - -- 72.1 -58.1 110 55 - - - - -72.1 58.1

47 - - - - - 68.6 -61.6 111 - - - - - -68.6 61.6

48 24 12 6 3 2 65.1 -65.1 112 56 28 14 7 0* -65.1 65.1

49 - - - - - 61.6 -68.6 113 - - - - - -61.6 68.6

50 25 - - -- 58.1 -72.1 114 57 - - - - -58.1 72.1

51 - - - - - 54.6 -75.5 115 - - - - - -54.6 75.5

52 26 13 - -- 50 -79 116 58 29 -- - -50 79

53 - - - - - 46.5 -82.6 117 - - - - - -46.5 82.6

54 27 - - -- 43 -84.9 118 59 - - - - -43 84.9

55 - - - - - 38.3 -87.2 119 - - - - - -38.3 87.2

56 28 14 7 -- 34.9 -89.5 120 60 30 15 - - -34.9 89.5

57 - - - - - 31.4 -91.8 121 - - - - - -31.4 91.8

58 29 - - -- 26.7 -93 122 61 - - - - -26.7 93

59 - - - - - 22.1 -94.1 123 - - - - - -22.1 94.1

60 30 15 - -- 17.4 -95.3 124 62 31 -- - -17.4 95.3

61 - - - - - 12.7 -96.5 125 - - - - - -12.7 96.5

62 31 - - -- 8.1 -97.7 126 63 - - - - -8.1 97.7

63 - - - - - 3.5 -98.8 127 - - - - - -3.5 98.8

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Uncompensated Half Step

SM[2:0] = 101

1/4th micro step

SM[2:0] = 011

Step 1

Start = 0

PC20070604.5

Step 2

Step 3

Start = 0

Step 2

Step 1

Step 3

Figure 8: Translator Table: Circular and Square

8.3.2. Direction

The direction of rotation is selected by means of following combination of the DIR input pin and the SPI-controlled direction bit

<DIRCTRL>. (Table 14: SPI Control Register 1)

8.3.3. NXT Input

Changes on the NXT input will move the motor current one step up/down in the translator table. Depending on the NXT-polarity bit

<NXTP> (Table 14: SPI Control Register 1), the next step is initiated either on the rising edge or the falling edge of the NXT input.

DIR

NXT

PC20070609.1

VALID

tNXT_HI tNXT_LO

tDIR_SET tDIR_HOLD

0,5 VCC

Figure 9: NXT-input Timing Diagram

Table 11: Timing Table NXT Pin

Symbol Parameter Min. Typ. Max. Unit

tNXT_HI NXT minimum, high pulse width 2 µs

tNXT_LO NXT minimum, low pulse width 2

µs

tDIR_SET NXT hold time, following change of DIR 500 µs

tDIR_HOLD NXT hold time, before change of DIR 500

µs

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

8.3.4. Translator Position

The translator position can be read in Table 30: SPI Status Register 3. This is a 7-bit number equivalent to the 1/32th micro-step from

Table 10: Circular Translator Table. The translator position is updated immediately following a NXT trigger.

NXT

Update

Translator Position

Update

Translator Position

PC20070604.4

Figure 10: Translator Position Timing Diagram

8.3.5. Synchronization of Step Mode and NXT Input

When step mode is re-programmed to another resolution (Table 13: SPI Control Register 0), then this is put in effect immediately upon

the first arriving “NXT” input. If the micro-stepping resolution is increased (see Figure 11) then the coil currents will be regulated to the

nearest micro-step, according to the fixed grid of the increased resolution. If however the micro-stepping resolution is decreased, then it

is possible to introduce an offset (or phase shift) in the micro-step translator table.

If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset

is zero and micro-stepping is proceeds according to the translator table.

If the translator position is not shared both by the old and new resolution setting, then the micro-stepping proceeds with an offset

relative to the translator table (See Figure 10 right hand side).

DIR

NXT1

NXT2

NXT3

NXT4

Halfstep

endpos

1/4th step

Change from lower to higher resolution

startpos

PC20070604.6

DIR

NXT1

NXT2

NXT3

DIR

endpos

Halfstep

1/8th step

Change from higher to lower resolution

startpos

Figure 11: NXT-Step Mode Synchronization

Left: Change from lower to higher resolution. The left-hand side depicts the ending half-step position during which a new step mode

resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the micro-step position.

Right: Change from higher to lower resolution. The left-hand side depicts the ending micro-step position during which a new step mode

resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the half-step position.

Note:

It is advised to reduce the micro-stepping resolution only at micro-step positions that overlap with desired micro-step positions of the new resolution.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

8.4 Programmable Peak- Current

The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter

"CUR[4:0]" (Table 13: SPI Control Register 0). Whenever this parameter is changed, the coil-currents will be updated immediately at

the next PWM period. More information can be found in Table 24: SPI Control Parameter Overview CUR[4:0].

8.5 Speed and Load Angle Output

The SLA-pin provides an output voltage that indicates the level of the Back-e.m.f. voltage of the motor. This Back-e.m.f. voltage is

sampled during every so-called "coil current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding in

total four zero-current observation points per electrical period.

VBEMF

ZOOM

VBB

VCOIL

Voltage Transient

Micro-step

Micro-step Coil Current Zero Crossing

Current Decay

Zero Current

PC20070604.7

ICOIL

VBEMF

Figure 12: Principle of Bemf Measurement

Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior.

As this transient is not always desired in application software, two operating modes can be selected by means of the bit <SLAT> (see

"SLA-transparency" in Table 15: SPI Control Register 2). The SLA pin shows in "transparent mode" full visibility of the voltage transient

behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If the bit

“SLAT” is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin. Because the

transient behavior of the coil voltage is not visible anymore, this mode generates smoother Back e.m.f. input for post-processing, e.g.

by software.

In order to bring the sampled Back e.m.f. to a descent output level (0 to 5V), the sampled coil voltage VCOIL is divided by 2 or by 4. This

divider is set through an SPI bit <SLAG>. (Table 15: SPI Control Register 2)

Table 12: Parameter Table SLA Pin

Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit

Vout Output voltage range 0.5 4.5 V

Voff Output offset the SLA pin 0.2V < Vsla < Vdd - 0,2V -20 20 mV

Rout Output resistance SLA pin 1 kΩ

Cload Load capacitance SLA pin 50 pF

Gsla

SLA

Gain of SLA pin = VBEMF / VCOIL SLAG=0

SLAG=1 0,5

0,25

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals that

define together with SLAT the sampling and hold moments of the coil voltage.

PWMsh

Icoil=0

SLAT

SLA-pin

SLAT=0 => SLA-pin is not "transparent" during

VBEMF sampling @ Coil Current Zero Crossing.

SLA-pin is updated when leaving current-less state.

SLAT=1 => SLA-pin is "transparent" during

VBEMF sampling @ Coil Current Zero

Crossing. SLA-pin is updated "real-time".

last sample

is retained retain last sample

previous output is kept at SLA pin

buf

Ssh Sh

Csh

SLAT

NOT(Icoil=0)

Icoil=0

PWMsh

SLA-pin

VCOIL div2

div4

VBEMF

PC20070604.8

VCOIL

Figure 13: Timing Diagram of SLA-pin

8.6 Warning, Error Detection and Diagnostics Feedback

8.6.1. Thermal Warning and Shutdo wn

When junction temperature rises above TTW, the thermal warning bit <TW> is set (Table 27: SPI Status Register 0). If junction

temperature increases above thermal shutdown level, then the circuit goes in “thermal shutdown” mode (<TSD>) and all driver

transistors are disabled (high impedance) (Table 29: SPI Status Register 2). The conditions to reset flag <TSD> is to be at a

temperature lower than TTW and to clear the <TSD> flag by reading it using any SPI read command.

8.6.2. Over-Current Detection

The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current

detection threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the

integrated circuit. Each driver transistor has an individual detection bit in the Table 28: SPI Status Register 1 and Table 29: SPI Status

Register 2 (<OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clean the status bits to reactivate

the drivers.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

8.6.3. Open Coil Detection

Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle is

detected for longer than 200ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI

status register is set (<OPENX> or <OPENY>). (Table 27: SPI Status Register 0)

8.6.4. Charge Pump Failure

The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If supply voltage

is too low or external components are not properly connected to guarantee Rdson of the drivers, then the bit <CPFAIL> is set in the

Table 27: SPI Status Register 0. Also after power-on-reset the charge pump voltage will need some time to exceed the required

threshold. During that time <CPFAIL> will be set to “1”.

8.6.5. Error Output

This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination

of:

NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL>

8.7 CLR pin (=Hard Reset)

Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30521, the input CLR needs to be

pulled to logic 1 during minimum time given by TCLR. (Table 6: AC Parameters) This reset function clears all internal registers without

the need of a power-cycle. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains

active. Logic 0 on CLR pin resumes normal operation again.

8.8 Sleep Mode

The bit <SLP> in Table 15: SPI Control Register 2 is provided to enter a so-called “sleep mode”. This mode allows reduction of current-

consumption when the motor is not in operation. The effect of sleep mode is as follows:

• The drivers are put in HiZ

• All analog circuits are disabled and in low-power mode

• All internal registers are maintaining their logic content

• NXT and DIR inputs are forbidden

• SPI communication remains possible (slight current increase during SPI communication)

• Reset of chip is possible through CLR pin

• Oscillator and digital clocks are silent, except during SPI communication

Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start-up time is needed for the charge pump to stabilize. After this

time, NXT commands can be issued.

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

9.0 SPI interface

The serial peripheral interface (SPI) is used to allow external microcontroller (MCU) to communicate with the device. The implemented

SPI block is flexible enough to interface directly with numerous microcontrollers from several manufacturers. AMIS-30521 acts always

as a slave and it can’t initiate any transmission. The operation of the device is configured and controlled by means of SPI registers,

which are observable for read and/or write from the master.

9.1 SPI Transfer Format and Pin Signals

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK)

synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO signal is the output from the slave,

and DI signal is the output from the master. A slave select line (CSB) allows individual selection of a slave SPI device in a multiple-

slave system. The CSB line is active low. If AMIS-30521 is not selected, DO is in high impedance state and it does not interfere with

SPI bus activities. Since AMIS-30521 always clocks data out on the falling edge and samples data in on rising edge of clock, the MCU

SPI port must be configured to match this operation. SPI clock idles low between the transferred bytes.

The diagram below is both a master and a slave timing diagram since CLK, DO and DI pins are directly connected between the master

and the slave.

8 7 6 5 4 3 2 1

MSB 65432 1 LSB

CLK (Idles Low)

DI (From Master)

DO (From Slave)

CSB

(1)

Note (1): MSB of data stored on the new address (see Transfer packet). The internal

data-out shift buffer of AMIS-30521 is updated with new content only at the last (every

eighth) falling edge of the CLK signal.

Figure 14: Timing Diagram of an SPI Transfer

9.2 Transfer Packet

Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more 8-bit characters (bytes).

MSB LSB

Command and Address

MSB LSB

Data byte

Cmd2 Cmd1 Cmd0 Addr4 Addr3 Addr2 Addr1 Addr0 Data7 - Data0

The first byte contains command and SPI Register address and will be sent upfront of the packet to indicate to AMIS-30521 the chosen

There are two possible commands for the master in normal operation mode of AMIS-30521:

• READ from SPI register: Cmd2 = 0

• WRITE to SPI register: Cmd2 = 1

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

WRITE command executed for read-only register will not affect the register and the device operation. In case of READ command the

data byte is optional. If a byte is transmitted after READ command it is also interpreted as a command (see examples below).

If the master reads data from a status register (SPI Status Register Description), then the most significant bit (Data 7) represents a

parity of Data6 to Data0 bits. If the number of logical ones in the data is odd then the parity bit equals 1. If the number of logical ones

is even then the parity bit equals 0. This is a simple mechanism to protect against noise and to verify the correct transmission operation

and the consistency of the status data. If a parity check error occurs, the master could initiate an additional READ command to obtain

the status again.

The CSB line is active low and may remain low between each successive READ commands. There is only one exception of this rule: if

error condition is latched in status register (SPI Status Register Description) and the master needs to clear the status bits then exactly

after READ command of a latched status register CSB line should go from low to high. This is explained in the following note:

Note: The status registers and ERRB pin (SPI Status Register Description) are updated by the internal system clock

only when CSB line is high. It is recommended to keep the CSB line high always when the SPI bus is idle.

If the master sends WRITE command, then the incoming data will be stored in the corresponding register only if CSB goes from low to

high. The writing to the register is only enabled if exactly 16 bits are transmitted within one transfer packet. If more or less clock pulses

are counted within one packet the complete packet is ignored.

AMIS-30521 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. After POR the initial

address is unknown. The following examples illustrate communication sessions between the master and AMIS-30521:

Read

Data

Write

DataA

DataC

DataB

Read

DataB

CSB

Master

305xx

ddrA

ddr

ddrA

ddr

Last Addr

Da ta C is w ritten in Ad drB on

rising edge of CSB

Read

ddr

DataC

ddr

Figure 15: Example SPI Transfer

In this example, the master reads first the status from AddrA and then writes control byte in AddrB. After write operation the master

could initiate a read back command in order to verify the data just written. Note that the first verification read operation returns the old

content of AddrB, the second read command returns the new AddrB data.

Note: The internal data out shift buffer of AMIS-30521 is updated with the content of the selected SPI register only at

the last (every eighth) falling edge of the CLK signal (SPI Transfer Format and Pin Signals). As a result, new data for

transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out

might represent old data.

This rule also applies when the master device wants to initiate an SPI transfer to read the status registers. Because the internal system

clock updates the status registers only when CSB line is high, the first read out byte might represent an old status (see Figure 16 and

Figure 17 below).

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Read

Data

Read

StatusA

CSB

Master

305xx

Status

Last

Add

Read

StatusA

Read

StatusB

Status

Status Status

Status Registers are updated

Figure 16: Example SPI Transfer

The last case illustrates data polling from several registers of the SPI register bank:

CSB

Read Read Read

Master

ddrA

ddrB

ddrC

Data Data

Data

305xx

ddrA

Last Addr

ddrB

Figure 17: Example SPI Transfer

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

9.3 SPI Control Registers

All SPI control registers have Read/Write access and default to "0" after power-on or hard reset.

Table 13: SPI Control Register 0

Control Register 0 (CR0)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

01h

Data SM[2:0] CUR[4:0]

Where:

R/W Read and Write access

Reset: Status after power-On or hard reset

SM[2:0]: Step mode

CUR[4:0]: Current amplitude

Table 14: SPI Control Register 1 Control Register 1 (CR1)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

02h

Data DIRCTRL NXTP - - PWMF PWMJ EMC[1:0]

Where:

R/W Read and Write access

Reset:: Status after power-on or hard reset

DIRCTRL Direction control

NXTP NEXT polarity

PWMF PWM frequency

PWMJ PWM jitter

EMC[1:0] EMC slope control

Table 15: SPI Control Register 2 Control Register 2 (CR2)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

03h

Data MOTEN SLP SLAG SLAT - - - -

Where:

R/W Read and Write access

Reset: Status after power-On or hard reset

MOTEN Motor enable

SLP Sleep

SLAG Speed load angle gain

SLAT Speed load angle transparency

Table 16: SPI Control Parameter Overview SLAT

Symbol Description Status Behavior

<SLAT> = 0 SLA is transparent

SLAT Speed Load Angle Transparency bit <SLAT> = 1 SLA is NOT transparent

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Table 17: SPI Control Parameter Overview SLAG

Symbol Description Status Value

<SLAG> = 0 Gain = 0.5

SLAG Speed Load Angle Gain setting <SLAG> = 1 Gain = 0.25

Table 18: SPI Control Parameter Overview PWMF

Symbol Description Status Value

<PWMF> = 0 fPWM = 22.8kHz

PWMF Enables doubling of the PWM frequency <PWMF> = 1 fPWM = 45.6kHz

Table 19: SPI Control Parameter Overview PWMJ

Symbol Description Status Behavior

<PWMJ> = 0 Jitter disabled

PWMJ Enables jittery PWM <PWMJ> = 1 Jitter enabled

Table 20: SPI Control Parameter Overview SLP

Symbol Description Status Behavior

<SLP> = 0 Active mode

SLP Enables sleep mode <SLP> = 1 Sleep mode

Table 21: SPI Control Parameter Overview MOTEN

Symbol Description Status Value

<MOTEN> = 0 Drivers disabled

MOTEN Activates the motor driver outputs <MOTEN> = 1 Drivers enabled

Table 22: SPI Control Parameter Overview DIRCTRL

Symbol Description Status Value

<DIRCTRL> = 0 CW motion

<DIR> = 0 <DIRCTRL> = 1 CCW motion

<DIRCTRL> = 0 CCW motion

DIRCTRL Controls the direction of rotation

(in combination with logic level on input DIR) <DIR> = 1 <DIRCTRL> = 1 CW motion

Table 23: SPI Control Parameter Overview NXTP

Symbol Description Status Value

<NXTP> = 0 Trigger on rising edge

NXTP Selects if NXT triggers on rising or falling edge <NXTP> = 1 Trigger on falling edge

CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.

Table 24: SPI Control Parameter Overview CUR[4:0]

Index CUR[4:0] Current (mA) Index CUR[4:0] Current (mA)

0 0 0 0 0 0 30 10 1 0 0 0 0 365

1 0 0 0 0 1 60 11 1 0 0 0 1 400

2 0 0 0 1 0 90 12 1 0 0 1 0 440

3 0 0 0 1 1 100 13 1 0 0 1 1 485

4 0 0 1 0 0 110 14 1 0 1 0 0 535

5 0 0 1 0 1 120 15 1 0 1 0 1 595

6 0 0 1 1 0 135 16 1 0 1 1 0 650

7 0 0 1 1 1 150 17 1 0 1 1 1 725

8 0 1 0 0 0 160 18 1 1 0 0 0 800

9 0 1 0 0 1 180 19 1 1 0 0 1 885

A 0 1 0 1 0 200 1A 1 1 0 1 0 970

B 0 1 0 1 1 220 1B 1 1 0 1 1 1070

C 0 1 1 0 0 240 1C 1 1 1 0 0 1190

D 0 1 1 0 1 270 1D 1 1 1 0 1 1300

E 0 1 1 1 0 300 1E 1 1 1 1 0 1450

F 0 1 1 1 1 325 1F 1 1 1 1 1 1600

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

EMC[1:0] Adjusts the dV/dt of the PWM voltage slopes on the motor pins.

Table 25: SPI Control Parameter Overview EMC[1:0]

Index EMC[1:0] Slope (V/µs) Remark

0 0 0 150 Turn-on and turn-off voltage slope 10% to 90%

1 0 1 100 “

2 1 0 50 “

3 1 1 25 “

SM[2:0] Selects the micro-stepping mode.

Table 26: SPI Control Parameter Overview SM[2:0]

Index SM[2:0] Step Mode Remark

0 0 0 0 1/32 Micro-step

1 0 0 1 1/16 Micro-step

2 0 1 0 1/8 Micro-step

3 0 1 1 ¼ Micro-step

4 1 0 0 ½ Uncompensated half-step

5 1 0 1 ½ Compensated half-step

6 1 1 0 Full Full step

7 1 1 1 N/A For future use

9.4 SPI Status Register Description

All four SPI status registers have Read Access and are default to "0" after power-on or hard reset.

Table 27: SPI Status Register 0 Status Register 0 (SR0)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

04h

Data PAR TW CPfail - OPENX OPENY - -

Where:

R Read only mode access

Reset Status after power-pn or hard reset

PAR Parity check

TW Thermal warning

Cpfail Charge pump failure

OPENX Open Coil X detected

OPENY Open Coil Y detected

Remark: Data is not latched

Table 28: SPI Status Register 1 Status Register 1 (SR1)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

05h

Data PAR OVCXPT OVCXPB OVCXNT OVCXNB - - -

Where:

R Read only mode access

Reset Status after power-on or hard reset

PAR Parity check

OVXPT Over-current detected on X H-bridge: MOTXP terminal, top transistor

OVXPB Over-current detected on X H-bridge: MOTXP terminal, bottom transistor

OVXNT Over-current detected on X H-bridge: MOTXN terminal, top transistor

OVXNB Over-current detected on X H-bridge: MOTXN terminal, bottom transistor

Remark: Data is latched

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Table 29: SPI Status Register 2 Status Register 2 (SR2)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

06h

Data PAR OVCYPT OVCYPB OVCYYNT OVCYNB TSD - -

Where:

R Read only mode access

Reset Status after power-on or hard reset

PAR Parity check

OVCYPT Over-current detected on Y H-bridge: MOTYP terminal, top transistor

OVCYPB Over-current detected on Y H-bridge: MOTYP terminal, bottom transistor

OVCYNT Over-current detected on Y H-bridge: MOTYN terminal, top transistor

OVCYNB Over-current detected on Y H-bridge: MOTYN terminal, bottom transistor

TSD Thermal shutdown

Remark: Data is latched

Table 30: SPI Status Register 3 Status Register 3 (SR3)

Address Structure

Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Access R R R R R R R R

Reset 0 0 0 0 0 0 0 0

07h

Data PAR MSP[6:0]

Where:

R Read only mode access

Reset Status after power-pn or hard reset

PAR Parity check

MSP[6:0] Translator micro-step position

Remark: Data is not latched

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

Table 31: SPI Status Flags Overview

Flag Mnemonic Length

(bit) Related SPI Register Comment Reset State

Charge pump failure CPFail 1 SPI Status Register 0

‘0’ = no failure

‘1’ = failure: indicates that the charge pump does

not reach the required voltage level. Note 1

‘0’

Micro-step position MSP[6:0] 7 SPI Status Register 0 Translator micro-step position ‘0000000’

OPEN Coil X OPENX 1 SPI Status Register 0 ‘1’ = Open coil detected ‘0’

OPEN Coil Y OPENY 1 SPI Status Register 0 ‘1’ = Open coil detected ‘0’

OVer Current on X

H-bridge; MOTXN

terminal; Bottom tran.

OVCXNB 1 SPI Status Register 1

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at bottom transistor XN-terminal

‘0’

OVer Current on X

H-bridge; MOTXN

terminal; Top transist.

OVCXNT 1 SPI Status Register 1

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at top transistor XN-terminal

‘0’

OVer Current on X

H-bridge; MOTXP

terminal; Bottom tran.

OVCXPB 1 SPI Status Register 1

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at bottom transistor XP-terminal

‘0’

OVer Current on X

H-bridge; MOTXP

terminal; Top transist.

OVCXPT 1 SPI Status Register 1

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at top transistor XP-terminal

‘0’

OVer Current on Y

H-bridge; MOTYN

terminal; Bottom tran.

OVCYNB 1 SPI Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at bottom transistor YN-terminal

‘0’

OVer Current on Y

H-bridge; MOTYN

terminal; Top transist.

OVCYNT 1 SPI Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at top transistor YN-terminal

‘0’

OVer Current on Y

H-bridge; MOTYP

terminal; Bottom tran.

OVCYPB 1 SPI Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at bottom transistor YP-terminal

‘0’

OVer Current on Y

H-bridge; MOTYP

terminal; Top transist.

OVCYPT 1 SPI Status Register 2

‘0’ = no failure

‘1’ = failure: indicates that over current is

detected at top transistor YP-terminal

‘0’

Thermal shutdown TSD 1 SPI Status Register 2 ‘0’

Thermal warning TW 1 SPI Status Register 0 ‘0’

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

10.0 Package Outline

Dimensions:

Dim Min Nom Max Unit

A 0.8 0.9 mm

A1 0 0.02 0.05 mm

A2 0.576 0.615 0.654 mm

A3 0.203 mm

b 0.25 0.3 0.35 mm

C 0.24 0.42 0.6 mm

D 7 mm

D1 6.75 mm

E 7 mm

E1 6.75 mm

e 0.65 mm

J 5.37 5.47 5.57 mm

K 5.37 5.47 5.57 mm

L 0.35 0.4 0.45 mm

P 45 Degree

R 2.185 2.385 mm

Notes :

2 Dimensions apply to plated terminal and are measured between 0.2 and

0.25 mm from terminal tip.

3 The pin #1 indication must be placed on the top surface of the package

by using indentation mark or other feature of package body.

4 Exact shape and size of this feature is optional

5 Applied for exposed pad and terminals. Exclude embedding part of

exposed pad from measuring.

6 Applied only to terminals

7 Exact shape of each corner is optional

7x7 NQFP

Figure 18: NQFP-32: No Lead Quad Fl at Pack; 32 Pins; Body Size 7x7mm (AMIS Reference: NQFP -32)

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AMIS-30521 Micro-stepping Motor Driver Data Sheet

11.0 Soldering

11.1 Introduction to Soldering Surface Mount Packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS “Data

Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for

all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards (PCB) with

high population densities. In these situations re-flow soldering is often used.

11.2 Re-flow Soldering

Re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the PCB by

screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for re-flowing; for

example, infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on the heating method. Typical re-

flow peak temperatures range from 215 to 260°C. The top-surface temperature of the packages should preferably be kept below 230°C.

11.3 Wave Soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or PCBs with a high component density, as

solder bridging and non-wetting can present major problems. To overcome these problems, the double-wave soldering method was

specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

• Larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the PCB;

• Smaller than 1.27mm, the footprint longitudinal axis must be parallel to the transport direction of the PCB. The footprint must

incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45º angle to the transport direction of the PCB. The

footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen

printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is four seconds

at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

11.4 Manual Soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to the flat

part of the lead. Contact time must be limited to 10 seconds at up to 300°C.

When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C.

Table 32: Soldering Process

Soldering Method

Package Wave Re-flow(1)

BGA, SQFP Not suitable Suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS Not suitable (2) Suitable

PLCC (3) , SO, SOJ Suitable Suitable

LQFP, QFP, TQFP Not recommended (3) (4) Suitable

SSOP, TSSOP, VSO Not recommended (5) Suitable

Notes:

(1) All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size

of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For

details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.”

(2) These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved, and as solder may

stick to the heatsink (on top version).

(3) If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder

thieves downstream and at the side corners.

(4) Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages with a

pitch (e) equal to or smaller than 0.65mm.

(5) Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65mm; it is definitely not suitable for packages with a

pitch (e) equal to or smaller than 0.5mm.

AMI Semiconductor – June 2007, M-20683-001

www.amis.com

AMIS-30521 Micro-stepping Motor Driver Data Sheet

12.0 Company or Product Inquiries

For more information about AMI Semiconductor’s products or services visit our Web site at http://www.amis.com.

13.0 Document History

Table 33: Revision History

Version Date Modification

0.1 18-jan-06 initial draft

0.2 24-jan-06 draft : changed PWM description, added SLA pin description, changed POR and WD paragraphs.

0.3 9-feb-06 CEN->CENB, NXT pin timing, SPI I/F, 30521 section 8.5, 8.6,8.7, 30522 section 8.4,8.5

0.4 9-mar-06 updated pin-out & added drawing, CENB->CLR, ERR->ERRB, removed SWP bits, updated SPI bits, added

package details

0.5 22-mar-06 Renamed CS -> CSB, Swapped pins CLR and CSB

0.6 24-may-06 Updated pins, AC&DC tables, SLA specs, SM[2:0] decoding

1.0 2-june-07 Final version

Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory,

implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of

merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI

Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high

reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such

AMI Semiconductor – June 2007, M-20683-001