ICE2PCS02 - Infineon Technologies AG

CCM-PFC

ICE2PCS02

ICE2PCS02G

Standalone Power Factor

Correction (PFC) Controller in

Continuous Conduction Mode

(CCM) with Input Brown-Out

Protection

N e v e r s t o p t h i n k i n g .

Version 2.4, 22 Mar 2010

Power Management & Supply

Edition 2010-03-22

Published by

Infineon Technologies AG

81726 München, Germany

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CCM-PFC

Revision History: 2010-03-22 Datasheet

Previous Version: V2.3

Page Subjects(major changes since last version)

18&19 Package outline dimension changed

CCM-PFC

ICE2PCS02

ICE2PCS02G

Version 2.4 3 22 Mar 2010

Type Package

ICE2PCS02 PG-DIP-8

ICE2PCS02 PG-DSO-8

Standalone Power Factor Correction (PFC)

Controller in Continuous Conduction Mode

(CCM) with Input Brown-Out Protection

ICE2PCS02

PG-DIP-8

ICE2PCS02G

PG-DSO-8

Product Highlights

• Leadfree DIP and DSO Package

• Wide Input Range

• Direct sensing, Input Brown-Out Detection

• Optimized for applications which require fast Startup

• Output Power Controllable by External Sense Resistor

• Fast Output Dynamic Response during Load Jumps

• Trimmed, internal fixed Switching Frequency (65kHz)

Features

• Ease of Use with Few External Components

• Supports Wide Input Range

• Average Current Control

• External Current and Voltage Loop Compensation

for Greater User Flexibility

• Trimmed internal fixed Switching Frequency

(65kHz+5% at 25oC)

• Direct sensing, Input Brown-Out Detection

with Hysteresis

• Short Startup(SoftStart) duration

• Max Duty Cycle of 95% (at 25oC)

• Trimmed Internal Reference Voltage (3V+2% at

25oC)

• VCC Under-Voltage Lockout

• Cycle by Cycle Peak Current Limiting

• Output Over-Voltage Protection

• Open Loop Detection

• Soft Overcurrent Protection

• Enhanced Dynamic Response

• Fulfills Class D Requirements of IEC 1000-3-2

Description

The ICE2PCS02/G is a 8-pin wide input range controller

IC for active power factor correction converters. It is de-

signed for converters in boost topology, and requires few

external components. Its power supply is recommended

to be provided by an external auxiliary supply which will

switch on and off the IC.

The IC operates in the CCM with average current control,

and in DCM only under light load condition. The switching

frequency is trimmed and fixed internally at 65kHz. Both

current and voltage loop compensations are done exter-

nally to allow full user control.

There are various protection features incorporated to en-

sure safe system operation conditions. The internal refer-

ence is trimmed (3V+2%) to ensure precise protection and

output control level.

85 ... 265 VAC EMI-Filter

Voltage Loop

Compensation

Protection Unit

Fixed

Oscillator

Current Loop

Compensation

PWM Logic

Driver

ICE2PCS02 /GCCM PFC

VCC

Auxiliary Supply VOUT

Typical Application

Ramp

Generator

ICOMP

VSENSE

VCOMP

ISENSE GND

Nonlinear

Gain

GATE

VINS Brown-out

CCM-PFC

ICE2PCS02/G

Version 2.4 4 22 Mar 2010

1 Pin Configuration and Functionality .............................5

1.1 PinConfiguration..............................................5

1.2 PinFunctionality ..............................................5

2 Representative Block diagram ..................................6

3 Functional Description ........................................7

3.1 General .....................................................7

3.2 PowerSupply ................................................7

3.3 Start-up .....................................................7

3.4 SystemProtection.............................................8

3.4.1 Input Brown-Out Protection (IBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4.2 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.3 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.4 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.5 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5 Fixed Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6 AverageCurrentControl.......................................10

3.6.1 CompleteCurrentLoop......................................10

3.6.2 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.3 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.4 NonlinearGainBlock .......................................10

3.7 PWMLogic .................................................11

3.8 VoltageLoop................................................11

3.8.1 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8.2 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.9 OutputGateDriver ...........................................11

4 Electrical Characteristics .....................................13

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 OperatingRange.............................................13

4.3 Characteristics ..............................................14

4.3.1 SupplySection ............................................14

4.3.2 PWMSection .............................................14

4.3.3 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.4 CurrentLoopSection .......................................15

4.3.5 VoltageLoopSection .......................................16

4.3.6 DriverSection .............................................17

5 Outline Dimension ..........................................18

Version 2.4 5 22 Mar 2010

CCM-PFC

ICE2PCS02/G

Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration

Figure 1 Pin Configuration (top view)

1.2 Pin Functionality

GND (Ground)

The ground potential of the IC.

ICOMP (Current Loop Compensation)

Low pass filter and compensation of the current control

loop. The capacitor which is connected at this pin

integrates the output current of OTA2 and averages the

current sense signal.

ISENSE (Current Sense Input)

The ISENSE Pin senses the voltage drop at the

external sense resistor (R1). This is the input signal for

the average current regulation in the current loop. It is

also fed to the peak current limitation block.

During power up time, high inrush currents cause high

negative voltage drop at R1, driving currents out of pin

3 which could be beyond the absolute maximum

ratings. Therefore a series resistor (R2) of around

220Wis recommended in order to limit this current into

the IC.

VINS (Brown-out Sense Input)

This VINS pin senses a filtered input voltage divider

and detects for the input voltage Brown-out condition.

A Brown-out condition of VINS<0.71V, shuts down the

IC. The IC turns on at VINS>1.5V.

VSENSE (Voltage Sense/Feedback)

The output bus voltage is sensed at this pin via a

resistive divider. The reference voltage for this pin is

3V.

VCOMP (Voltage Loop Compensation)

This pin provides the compensation of the output

voltage loop with a compensation network to ground

(see Figure 2).

VCC (Power Supply)

The VCC pin is the positive supply of the IC and should

be connected to an external auxiliary supply. The

operating range is between 11V and 26V. The turn-on

threshold is at 11.8V and under voltage occurs at 11V.

There is no internal clamp for a limitation of the power

supply.

GATE

The GATE pin is the output of the internal driver stage,

which has a capability of 1.5A instantaneous source

and 2.0A instantaneous sink current.

Its gate drive voltage is internally clamped at 15.0V

(typically).

Pin Symbol Function

1 GND IC Ground

2 ICOMP Current Loop Compensation

3 ISENSE Current Sense Input

4 VINS Brown-out Sense Input

5 VCOMP Voltage Loop Compensation

6 VSENSE VOUT Sense (Feedback) Input

7 VCC IC Supply Voltage

8 GATE Gate Drive Output

Package PG-DIP-8 / PG-DSO-8

GATEGND

ICOMP

ISENSE

VCC

VSENSE

VINS VCOMP

CCM-PFC

ICE2PCS02/G

Representative Block diagram

Version 2.4 6 22 Mar 2010

2 Representative Block diagram

Figure 2 Representative Block diagram

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 7 22 Mar 2010

3.1 General

The ICE2PCS02/G is a 8 pin control IC for power factor

correction converters. It comes in both DIP and DSO

packages and is suitable for wide range line input

applications from 85 to 265 VAC. The IC supports

converters in boost topology and it operates in

continuous conduction mode (CCM) with average

current control.

It is a design derivative from the ICE2PCS01/G with the

differences in the supporting functions, namely the

input brown-out detection and internal fixed switching

frequency 65kHz.

The IC operates with a cascaded control; the inner

current loop and the outer voltage loop. The inner

current loop of the IC controls the sinusoidal profile for

the average input current. It uses the dependency of

the PWM duty cycle on the line input voltage to

determine the corresponding input current. This means

the average input current follows the input voltage as

long as the device operates in CCM. Under light load

condition, depending on the choke inductance, the

system may enter into discontinuous conduction mode

(DCM) resulting in a higher harmonics but still meeting

the Class D requirement of IEC 1000-3-2.

The outer voltage loop controls the output bus voltage.

Depending on the load condition, OTA1 establishes an

appropriate voltage at VCOMP pin which controls the

amplitude of the average input current.

The IC is equipped with various protection features to

ensure safe operating condition for both the system

and device.

3.2 Power Supply

An internal under voltage lockout (UVLO) block

monitors the VCC power supply. As soon as it exceeds

11.8V and both voltages at pin 6 (VSENSE) >0.6V and

pin 4 (VINS) >1.5V, the IC begins operating its gate

drive and performs its Startup as shown in Figure 3.

Figure 3 State of Operation respect to VCC

If VCC drops below 11V, the IC is off. The IC will then

be consuming typically 300mA, whereas consuming

10mA during normal operation.

The IC can be turned off and forced into standby mode

by pulling down the voltage at pin 6 (VSENSE) to lower

than 0.6V. In this standby mode, the current

consumption is reduced to 300mA. Other condition that

can result in the standby mode is when a Brown-out

condition occurs, ie pin 4 (VINS) <0.71V.

3.3 Start-up

Figure 4 shows the operation of voltage loop’s OTA1

during startup. The VCOMP pin is pull internally to

ground via switch S1 during UVLO and other fault

conditions (see later section on “System Protection”).

During power up when VOUT is less than 83% of the

rated level, OTA1 sources an output current, maximum

30mA into the compensation network at pin 5 (VCOMP)

causing the voltage at this pin to rise linearly. This

results in a controlled linear increase of the input

current from 0A thus reducing the stress on the

external component.

Figure 4 Startup Circuit

As VOUT has not reached within 5% from the rated

value, VCOMP voltage is level-shifted by the window

detect block as shown in Figure 5, to ensure there is

fast boost up output voltage.

When VOUT approaches its rated value, OTA1’s

sourcing current drops and so does the level shift of the

window detect block is removed. The normal voltage

loop then takes control.

VCC

(VVSENSE > 0.6 V)

AND (VVINS > 1.5 V)

11.8 V

11.0V

OFF Start

Up Open loop/

Standby

Normal

Operation

IC's

State OFF

Normal

Operation

(VVSENSE < 0.6 V)

OR (VVINS < 0.8 V) (VVSENSE > 0.6 V)

AND(VVINS > 1.5 V)

VCOMP

VSENSE

OTA1 3V

ICE2PCS02/G

protect

R3 + R4

R4 x VOUT )

(

3 Functional Description

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 8 22 Mar 2010

Figure 5 Startup with controlled maximum current

3.4 System Protection

The IC provides several protection features in order to

ensure the PFC system in safe operating range:

• VCC Undervoltage Lockout (UVLO)

• Input Brown-out Detection (IBOP)

• Soft Over Current Control (SOC)

• Peak Current Limit (PCL)

• Open-Loop Detection (OLP)

• Output Over-Voltage Protection (OVP)

After the system is supplied with the correct level of

VCC and VIN, the system will enter into its normal mode

of operation. Figure 6 shows situation when these

protections features are active, as a function of the

output voltage VOUT.

An activation of the UVLO, IBOP and OLP results in the

internal fault signal going high and brings the IC into the

standby mode.

As the function of UVLO has already described in the

earlier “Power Supply” section, the following sections

continue to describe the functionality of these

protection features.

Figure 6 Protection Features

3.4.1 Input Brown-Out Protection (IBOP)

Brown-out occurs when the input voltage VIN falls below

the minimum input voltage of the design (i.e. 85V for

universal input voltage range) and the VCC has not

entered into the VCCUVLO level yet. For a system without

IBOP, the boost converter will increasingly draw a

higher current from the mains at a given output power

which may exceed the maximum design values of the

input current.

ICE2PCS02/G provides a new IBOP feature whereby it

senses directly the input voltage for Input Brown-Out

condition via an external resistor/capacitor/diode

network as shown in Figure 7. This network provides a

filtered value of VIN which turns the IC on when the

voltage at pin 4 (VINS) is more than 1.5V. The IC enters

into the standby mode when VINS goes below 0.71V.

The hysteresis prevents the system to oscillate

between normal and standby mode. Note also that VIN

needs to at least 20% of the rated VOUT in order to

overcome OLP and powerup the system.

Figure 7 Input Brown-Out Protection (IBOP)

av(IIN)

VOUT

VOUT =rated

95%rated

Window Detect Normal Control

Max Vcomp current

83%rated

VCOMP

Level-shifted VCOMP

VOUT

PCL / SOC

20%

100%

OLP OLP

108%

OVP

VOUT,Rated

UVLO / IBOP

Supply

Current

Output

ICE2PCS02/G

85 ... 265 VAC

Vin C1

D2 ... D5

VINS

1.5V

0.71V

Brown-Out Detection R8

R9C6

brown-out

3.5V

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 9 22 Mar 2010

3.4.2 Soft Over Current Control (SOC)

The IC is designed not to support any output power

that corresponds to a voltage lower than -0.75V at the

ISENSE pin. A further increase in the inductor current,

which results in a lower ISENSE voltage, will activate

the Soft Over Current Control (SOC). This is a soft

control as it does not directly switch off the gate drive.

It acts on the nonlinear gain block to result in a reduced

PWM duty cycle.

Figure 8 SOC and PCL Protection as function of

VISENSE

The rated output power with a minimum VIN (VINMIN) is

Due to the internal parameter tolerance, the maximum

power with VINMIN is

3.4.3 Peak Current Limit (PCL)

The IC provides a cycle by cycle peak current limitation

(PCL). It is active when the voltage at pin 3 (ISENSE)

reaches -1.04V. This voltage is amplified by OP1 by a

factor of -1.43 and connected to comparator C2 with a

reference voltage of 1.5V as shown in Figure 9. A

deglitcher with 300ns after the comparator improves

noise immunity to the activation of this protection.

Figure 9 Peak Current Limit (PCL)

3.4.4 Open Loop Protection (OLP)

Whenever VSENSE voltage falls below 0.6V, or

equivalently VOUT falls below 20% of its rated value, it

indicates an open loop condition (i.e. VSENSE pin not

connected) or an insufficient input voltage VIN for

normal operation. In this case, most of the blocks within

the IC will be shutdown. It is implemented using

comparator C3 with a threshold of 0.6V as shown in the

IC block diagram in Figure 2.

3.4.5 Over-Voltage Protection (OVP)

Whenever VOUT exceeds the rated value by 5%, the

over-voltage protection OVP is active as shown in

Figure 6. This is implemented by sensing the voltage at

pin VSENSE with respect to a reference voltage of

3.15V. A VSENSE voltage higher than 3.15V will

immediately reduce the output duty cycle, bypassing

the normal voltage loop control. This results in a lower

input power to reduce the output voltage VOUT. A

VSENSE voltage higher than 3.25V will immediately

turn off the gate, thereby preventing damage to bus

capacitor.

3.5 Fixed Switching Frequency

ICE2PCS02/G has an internally fixed switching

frequency as opposed to the ICE2PCS01/G which can

be externally set. This frequency is trimmed to 65kHz

with an accuracy ±5% at 25oC.

VISENSE

-0.61V -0.75V -1.04V

Normal

Operation

SOC PCL

POUT(rated)

IC’s

State

POUT(max)

POUT rated( ) VINMIN 0.61

R1 2×

-------------------

´=

POUT max( ) VINMIN 0.75

R1 2×

-------------------

´=

ISENSE

ICE2PCS02/G

IINDUCTOR OP1

1.43x

Current Limit

300ns

Deglitcher

Turn Off

Driver

1.5V

Full-wave

Rectifier

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 10 22 Mar 2010

3.6 Average Current Control

3.6.1 Complete Current Loop

The complete system current loop is shown in Figure

10.

Figure 10 Complete System Current Loop

It consists of the current loop block which averages the

voltage at pin ISENSE, resulted from the inductor

current flowing across R1. The averaged waveform is

compared with an internal ramp in the ramp generator

and PWM block. Once the ramp crosses the average

waveform, the comparator C1 turns on the driver stage

through the PWM logic block. The Nonlinear Gain block

defines the amplitude of the inductor current. The

following sections describe the functionality of each

individual blocks.

3.6.2 Current Loop Compensation

The compensation of the current loop is done at the

ICOMP pin. This is the OTA2 output and a capacitor C3

has to be installed at this node to ground (see Figure

10). Under normal mode of operation, this pin gives a

voltage which is proportional to the averaged inductor

current. This pin is internally shorted to 4.2V in the

event of standby mode.

3.6.3 Pulse Width Modulation (PWM)

The IC employs an average current control scheme in

continuous conduction mode (CCM) to achieve the

power factor correction.

Assuming the voltage loop is working and output

voltage is kept constant, the off duty cycle DOFF for a

CCM PFC system is given as

From the above equation, DOFF is proportional to VIN.

The objective of the current loop is to regulate the

average inductor current such that it is proportional to

the off duty cycle DOFF, and thus to the input voltage

VIN. Figure 11 shows the scheme to achieve the

objective.

Figure 11 Average Current Control in CCM

The PWM is performed by the intersection of a ramp

signal with the averaged inductor current at pin 5

(ICOMP). The PWM cycle starts with the Gate turn off

for a duration of TOFFMIN (400ns typ.) and the ramp is

kept discharged. The ramp is then allowed to rise after

TOFFMIN expires. The off time of the boost transistor

ends at the intersection of the ramp signal and the

averaged current waveform. This results in the

proportional relationship between the average current

and the off duty cycle DOFF.

Figure 12 shows the timing diagrams of TOFFMIN and the

PWM waveforms.

Figure 12 Ramp and PWM waveforms

3.6.4 Nonlinear Gain Block

The nonlinear gain block controls the amplitude of the

regulated inductor current. The input of this block is the

ICE2PCS02/G

Vout

Gate

Driver

From

Full-wave

Retifier

GATE

OTA2

ICOMP

4.2V

Current Loop

Compensation

Current Loop

Nonlinear

Gain

1.0mS

+/-50uA (linear range)

C3 S2

Fault

ISENSE

PWM

Comparator

PWM Logic

Input From

Voltage Loop

voltage

proportional to

averaged

Inductor current

DOFF

VIN

VOUT

--------------=

ave(I

) at ICOMP

ramp profile

GATE

drive

TOFFMIN

400ns

VCREF(1)

VRAMP

PWM

ramp

released

PWM cycle

(1) VCREF is a function of VICOMP

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 11 22 Mar 2010

voltage at pin VCOMP. This block has been designed

to support the wide input voltage range (85-265VAC).

3.7 PWM Logic

The PWM logic block prioritizes the control input

signals and generates the final logic signal to turn on

the driver stage. The speed of the logic gates in this

block, together with the width of the reset pulse TOFFMIN,

are designed to meet a maximum duty cycle DMAX of

95% at the GATE output.

In case of high input currents which result in Peak

Current Limitation, the GATE will be turned off

immediately and maintained in off state for the current

PWM cycle. The signal Toffmin resets (highest priority,

overriding other input signals) both the current limit

latch and the PWM on latch as illustrated in Figure 13.

Figure 13 PWM Logic

3.8 Voltage Loop

The voltage loop is the outer loop of the cascaded

control scheme which controls the PFC output bus

voltage VOUT. This loop is closed by the feedback

sensing voltage at VSENSE which is a resistive divider

tapping from VOUT. The pin VSENSE is the input of

OTA1 which has an accurate internal reference of 3V

(±2%). Figure 14 shows the important blocks of this

voltage loop.

3.8.1 Voltage Loop Compensation

The compensation of the voltage loop is installed at the

VCOMP pin (see Figure 14). This is the output of OTA1

and the compensation must be connected at this pin to

ground. The compensation is also responsible for the

soft start function which controls an increasing AC input

current during start-up.

Figure 14 Voltage Loop

3.8.2 Enhanced Dynamic Response

Due to the low frequency bandwidth of the voltage loop,

the dynamic response is slow and in the range of about

several 10ms. This may cause additional stress to the

bus capacitor and the switching transistor of the PFC in

the event of heavy load changes.

The IC provides therefore a “window detector” for the

feedback voltage VVSENSE at pin 6 (VSENSE).

Whenever VVSENSE exceeds the reference value (3V)

by +5%, it will act on the nonlinear gain block which in

turn affect the gate drive duty cycle directly. This

change in duty cycle is bypassing the slow changing

VCOMP voltage, thus results in a fast dynamic

response of VOUT.

3.9 Output Gate Driver

The output gate driver is a fast totem pole gate drive. It

has an in-built cross conduction currents protection and

a Zener diode Z1 (see Figure 15) to protect the external

transistor switch against undesirable over voltages.

The maximum voltage at pin 8 (GATE) is typically

clamped at 15V.

SL1

SL2

Peak Current

Limit

Current Loop

PWM on signal

Toffmin

385ns

Current

Limit Latch

PWM on

Latch

HIGH =

turn GATE on

VCOMP

VSENSE

OTA1 3V

VIN

Av(IIN)Nonlinear

Gain

ICE2PCS02/G

Vout

Gate Driver

Current Loop

PWM Generation

From

Full-wave

Retifier

GATE

CCM-PFC

ICE2PCS02/G

Functional Description

Version 2.4 12 22 Mar 2010

Figure 15 Gate Driver

The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive

is internally pull low to maintain the off state.

GATE

External

MOS

VCC

Gate Driver

PWM Logic

HIGH to

turn on LV

* LV: Level Shift

ICE2PCS02/G

CCM-PFC

ICE2PCS02/G

Electrical Characteristics

Version 2.4 13 22 Mar 2010

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit.

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VCC -0.3 25 V

VINS Voltage VVINS -0.3 9.5 V 3)

VINS Current IINS -1 35 uA

ICOMP Voltage VICOMP -0.3 5 V

ISENSE Voltage VISENSE -20 5 V 2)

ISENSE Current IISENSE -1 1 mA Recommended R2=220W

VSENSE Voltage VVSENSE -0.3 5 V

VSENSE Current IVSENSE -1 1 mA R3>400kW

VCOMP Voltage VVCOMP -0.3 5 V

GATE Voltage VGATE -0.3 17 V Clamped at 15V(typ)

if driven internally.

Junction Temperature Tj-40 150 °C

Storage Temperature TS-55 150 °C

Thermal Resistance

Junction-Ambient for PG-DSO-8 RthJA (DSO) - 185 K/W PG-DSO-8

Thermal Resistance

Junction-Ambient for PG-DIP-8 RthJA(DIP) - 90 K/W PG-DIP-8

ESD Protection VESD - 2 kV Human Body Model1)

1) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kWseries resistor)

2) Absolute ISENSE current should not be exceeded

3) Absolute VINS current should not be exceeded

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VCC VCCUVLO 25 V

Junction Temperature TJCon -40 125 °C

CCM-PFC

ICE2PCS02/G

Electrical Characteristics

Version 2.4 14 22 Mar 2010

4.3 Characteristics

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range TJfrom – 40 °C to 125°C.Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of VCC =18V is assumed for test condition.

4.3.1 Supply Section

4.3.2 PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

VCC Turn-On Threshold VCCon 11.4 11.8 12.7 V

VCC Turn-Off Threshold/

Under Voltage Lock Out VCCUVLO 10.4 11.0 11.7 V

VCC Turn-On/Off Hysteresis VCChy 0.65 0.8 1.4 V

Start Up Current

Before VCCon

ICCstart - 450 1100 mAVVCC=VVCCon -0.1V

Operating Current with active GATE ICCHG - 10 13 mA CL= 4.7nF

Operating Current during Standby ICCStdby - 700 1300 mAVVSENSE= 0.5V

VICOMP= 4V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Fixed Oscillator Frequency fSW 58 65 70 kHz

Max. Duty Cycle DMAX 92 95 98.5 %

Min. Duty Cycle DMIN 0 % VVCOMP= 0V, VVSENSE= 3V

VICOMP= 4.3V

Min. Off Time TOFFMIN 270 400 770 ns VVSENSE= 3V

VISENSE= 0.1V

CCM-PFC

ICE2PCS02/G

Electrical Characteristics

Version 2.4 15 22 Mar 2010

4.3.3 System Protection Section

4.3.4 Current Loop Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Open Loop Protection (OLP)

VSENSE Threshold VOLP 0.55 0.6 0.65 V

Peak Current Limitation (PCL)

ISENSE Threshold VPCL -1.16 -1.04 -0.95 V

Soft Over Current Control (SOC)

ISENSE Threshold VSOC -0.75 -0.68 -0.61 V

Output Over-Voltage Protection (OVP) VOVP 3.1 3.25 3.4 V

Input Brown-out Protection (IBOP)

High to Low Threshold VVINSL 0.64 0.71 0.77 V

Input Brown-out Protection (IBOP)

Low to High Threshold VVINSH 1.46 1.50 1.57 V

Input Brown-out Protection (IBOP)

VINS Bias Current IVIN0V -1 -0.2 1 mAVVINS= 0V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

OTA2 Transconductance Gain GmOTA2 0.8 1.0 1.3 mS At Temp = 25°C

OTA2 Output Linear Range1)

1) The parameter is not subject to production test - verified by design/characterization

IOTA2 - ± 50 - mA

ICOMP Voltage during OLP VICOMPF 3.9 4.2 - V VVSENSE= 0.5V

CCM-PFC

ICE2PCS02/G

Electrical Characteristics

Version 2.4 16 22 Mar 2010

4.3.5 Voltage Loop Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

OTA1 Reference Voltage VOTA1 2.92 3.00 3.08 V measured at VSENSE

OTA1 Transconductance Gain GmOTA1 26 39 51 mS

OTA1 Max. Source Current

Under Normal Operation IOTA1SO 18 30 38 mAVVSENSE= 2V

VVCOMP= 3V

OTA1 Max. Sink Current

Under Normal Operation IOTA1SK 21 30 41 mAVVSENSE= 4V

VVCOMP= 3V

Enhanced Dynamic Response

VSENSE High Threshold

VSENSE Low Threshold VHi

VLo

3.09

2.76 3.18

2.85 3.26

2.94 V

VSENSE Input Bias Current at 3V IVSEN5V 0 - 1.5 mAVVSENSE= 3V

VSENSE Input Bias Current at 1V IVSEN1V 0 - 1 mAVVSENSE= 1V

VCOMP Voltage during OLP VVCOMPF 0 0.2 0.4 V VVSENSE= 0.5V

IVCOMP= 0.5mA

CCM-PFC

ICE2PCS02/G

Electrical Characteristics

Version 2.4 17 22 Mar 2010

4.3.6 Driver Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

GATE Low Voltage VGATEL - - 1.2 V VCC =10V

IGATE = 5 mA

- 1.5 V VCC =10V

IGATE =20 mA

- 0.4 - V IGATE = 0 A

- - 1.0 V IGATE = 20 mA

-0.2 0 - V IGATE = -20 mA

GATE High Voltage VGATEH - 14.8 - V VCC = 25V

CL= 4.7nF

- 14.8 - V VCC = 19V

CL= 4.7nF

7.8 9.2 - V VCC =VVCCoff + 0.2V

CL= 4.7nF

GATE Rise Time tr- 60 - ns VGate = 2V ...12V

CL= 4.7nF

GATE Fall Time tf- 50 - ns VGate = 12V ...2V

CL= 4.7nF

GATE Current, Peak,

Rising Edge IGATE -1.5 - - A CL= 4.7nF1)

1) Design characteristics (not meant for production testing)

GATE Current, Peak,

Falling Edge IGATE - - 2.0 A CL= 4.7nF1)

CCM-PFC

ICE2PCS02/G

Outline Dimension

Version 2.4 18 22 Mar 2010

5 Outline Dimension

PG-DIP-8 Outline Dimension

CCM-PFC

ICE2PCS02/G

Outline Dimension

Version 2.4 19 22 Mar 2010

PG-DSO-8 Outline Dimension

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Ansprüchen in der bestmöglichen

Weisegerechtwerden.Esgehtunsalso

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