ISD2575P - Nuvoton Technology

1–79

Information Storage Devices, Inc.

FEATURES

• Easy-to-use single-chip voice Record/

Playback solution

• High-quality, natural voice/audio

reproduction

• Manual switch or microcontroller compati-

ble Playback can be edge- or level-

activated

• Single-chip durations of

32*, 40*, 48*, 64*

60, 75, 90, and 120 seconds

• Directly cascadable for longer durations

• Automatic Power-Down (Push-Button

Mode)

– Standby current 1

A (typical)

• Zero-power message storage

– Eliminates battery backup circuits

• Fully addressable to handle multiple

messages

• 100-year message retention (typical)

• 100,000 record cycles (typical)

• On-chip clock source

• No algorithm development required

• Single +5 volt power supply

• Available in die form, DIP, SOIC, and

TSOP packaging

• Industrial temperature (-40

C to +85

versions available

ISD2500 Series

Single-Chip Voice Record/Playback Devices

32-*, 40-*, 48-*, 64-*

, 60-, 75-,

90-, and 120-Second Durations

ISD2500 SERIES SUMMARY

Part

Number Duration

(Seconds) Input Sample

Rate (KHz) Typical Filter

Pass Band (KHz)

ISD2560 60 8.0 3.4

ISD2575 75 6.4 2.7

ISD2590 90 5.3 2.3

ISD25120 120 4.0 1.7

ISD2532* 32 8.0 3.4

ISD2540* 40 6.4 2.7

ISD2548* 48 5.3 2.3

ISD2564* 64 4.0 1.7

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–80

-1

GENERAL DESCRIPTION

Information Storage Devices' ISD2500 Chip-

Corder

Series provides high-quality, single-chip

Record/Playback solutions for 32- to 120-second

messaging applications. The CMOS devices

include an on-chip oscillator, microphone pream-

plifier, automatic gain control, antialiasing filter,

smoothing filter, speaker amplifier, and high den-

sity multi-level storage array. In addition, the

ISD2500 is microcontroller compatible, allowing

complex messaging and addressing to be

achieved.

Recordings are stored in on-chip nonvolatile mem-

ory cells, providing zero-power message storage.

This unique, single-chip solution is made possible

through ISD's patented multilevel storage technol-

ogy. Voice and audio signals are stored directly

into memory in their natural form, providing high-

quality, solid-state voice reproduction.

DETAILED DESCRIPTION

Speech/Sound Quality

The ISD2500 Series includes devices offered at

4.0, 5.3, 6.4, and 8.0 KHz sampling frequencies,

allowing the user a choice of speech quality

options. Increasing the duration within a product

series decreases the sampling frequency and

bandwidth, which affects sound quality. Please

refer to the ISD2500 Series Summary table on

page 1-79 to compare filter pass band and product

durations.

The speech samples are stored directly into on-

chip nonvolatile memory without the digitization

and compression associated with other solutions.

Direct analog storage provides a very true, natural

sounding reproduction of voice, music, tones, and

sound effects not available with most solid-state

digital solutions.

Duration

To meet end system requirements, the ISD2500

Series offers single-chip solutions at

32*, 40*, 48*,

*, 60, 75, 90, and 120 seconds. Parts may also

be cascaded together for longer durations.

ISD2560/75/90/120 DEVICE BLOCK DIAGRAM

Advance information: ISD2532/40/48/64 devices.

Amp

Pre-

Amp

VCCA VCCD A0 A2 A3 A4 A5 A7 A8 A9A6 OVF P/R CE EOMPD

XCLK

ANA IN

ANA OUT

MIC

MIC REF

AGC

Decoders

480 K Cell

Nonvolatile

Multilevel Storage

Array Amp

AUX IN

SP+

SP–

VSSA VSSD A1

TimingInternal Clock

Power Conditioning Address Buffers Device Control

Analog Transceivers

Sampling Clock

Mux

Automatic

Gain Control

(AGC)

5-Pole Active

Antialiasing Filter

5-Pole Active

Smoothing Filter

Product Data Sheets

ISD2500 Series

1–81

EEPROM Storage

One of the benefits of ISD’s ChipCorder technol-

ogy is the use of on-chip nonvolatile memory,

providing zero-power message storage. The mes-

sage is retained for up to 100 years typically

without power. In addition, the device can be re-

recorded typically over 100,000 times.

Microcontroller Interface

In addition to its simplicity and ease of use, the

ISD2500 Series includes all the interfaces neces-

sary for microcontroller-driven applications. The

address and control lines can be interfaced to a

microcontroller and manipulated to perform a vari-

ety of tasks, including message assembly,

message concatenation, predefined fixed mes-

sage segmentation, and message management.

Programming

The ISD2500 Series is also ideal for playback-only

applications, where single or multiple messages

are referenced through buttons, switches, or a

microcontroller. Once the desired message config-

uration is created, duplicates can easily be

generated via an ISD programmer.

PIN DESCRIPTIONS

Voltage Inputs (V

CCA

, V

CCD

)

To minimize noise, the analog and digital circuits in

the ISD2500 Series devices use separate power

busses. These voltage busses are brought out to

separate pins and should be tied together as close

to the supply as possible. In addition, these sup-

plies should be decoupled as close to the package

as possible.

Ground Inputs (V

SSA

, V

SSD

)

The ISD2500 Series of devices utilizes separate

analog and digital ground busses. These pins

should be connected separately through a low-

impedance path to power supply ground.

Power Down Input (PD)

When not recording or playing back, the PD pin

should be pulled HIGH to place the part in a very

low power mode (see I

specification). When

OVF pulses LOW for an overflow condition, PD

should be brought HIGH to reset the address

pointer back to the beginning of the Record/Play-

back space. The PD pin has additional

functionality in the M6 (Push-Button) Operational

ISD2532/40/48/64

* DEVICE BLOCK DIAGRAM

Advance information: ISD2532/40/48/64 devices.

Amp

Pre-

Amp

VCCA VCCD A0 A2 A3 A4 A5 A7 A8A6 OVF P/R CE EOMPD

XCLK

ANA IN

ANA OUT

MIC

MIC REF

AGC

Decoders

256 K Cell

Nonvolatile

Multilevel Storage

Array Amp

AUX IN

SP+

SP–

VSSA VSSD A1

TimingInternal Clock

Power Conditioning Address Buffers Device Control

Analog Transceivers

Sampling Clock

Mux

Automatic

Gain Control

(AGC)

5-Pole Active

Antialiasing Filter

5-Pole Active

Smoothing Filter

Product Data Sheets

ISD2500 Series

1–82

-1

SSD

SSA

OVF

CE

PD

EOM

XCLK

P/R

V 

NC

A0/M0

A1/M1

A2/M2

A3/M3

A4/M4

A5/M5

A6/M6

ANA OUT

ANA IN

AGC

MIC REF

MIC

V

SP–

NC

SP+

V

AUX IN

A9

A8

CCD CCA

ISD2560/75/90/120

TSOP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17



1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SSD

SSA

A0/M0

A1/M1

A2/M2

A3/M3

A4/M4

A5/M5

A6/M6

A7

A8

A9

AUX IN

V 

SP+

V

P/R

XCLK

EOM

PD

CE

OVF

ANA OUT

ANA IN

AGC

MIC REF

MIC

V

SP–

CCD

CCA

ISD2560

ISD2575

ISD2590

ISD25120

DIP/SOIC

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

Mode described later in the Operational Mode

section.

Chip Enable Input (CE)

The CE pin is taken LOW to enable all Playback

and Record operations. The address inputs and

Playback/Record input (P/R) are latched by the

falling edge of CE. CE has additional functionality

in the M6 (Push-Button) Operational Mode

described later in the Operational Mode section.

Playback/Record Input (P/R)

The P/R input is latched by the falling edge of the

CE pin. A HIGH level selects a Playback cycle

while a LOW level selects a Record cycle. For a

Record cycle, the address inputs provide the start-

ing address and recording continues until PD or

CE is pulled HIGH or an overflow is detected (i.e.

the chip is full). When a Record cycle is terminated

by pulling PD or CE HIGH, an End-Of-Message

(EOM) marker is stored at the current address in

memory. For a Playback cycle, the address inputs

provide the starting address and the device will

play until an EOM marker is encountered. The

device can continue past an EOM marker in an

operational mode, or if CE is held LOW in address

mode. (See page 1-85 for more Operational

Modes).

End-Of-Message / RUN Output (EOM)

A nonvolatile marker is automatically inserted at

the end of each recorded message. It remains

there until the message is recorded over. The

EOM output pulses LOW for a period of T

EOM

the end of each message.

In addition, the ISD2500 Series has an internal

detect circuit to maintain message integrity

should V

fall below 3.5V. In this case, EOM

goes LOW and the device is fixed in Playback-only

mode.

When the device is configured in Operational

Mode M6 (Push-Button Mode), this pin provides an

active-HIGH RUN signal, indicating the device is

currently recording or playing. This signal can con-

veniently drive an LED for a visual indicator of a

Record or Playback operation in process.

Overﬂow Output (OVF)

This signal pulses LOW at the end of memory

space, indicating the device has been filled and the

message has overflowed. The OVF output then fol-

lows the CE input until a PD pulse has reset the

device. This pin can be used to cascade several

ISD2500 devices together to increase Record/

Playback durations.

ISD2560/75/90/120 DEVICE PINOUTS

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–83

SSD

SSA

OVF

CE

PD

EOM

XCLK

P/R

V 

NC

A0/M0

A1/M1

A2/M2

A3/M3

A4/M4

A5/M5

A6/M6

ANA OUT

ANA IN

AGC

MIC REF

MIC

V

SP–

NC

SP+

V

AUX IN

A8

A7

CCD CCA

ISD2532/40/48/64

TSOP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17



1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SSD

SSA

A0/M0

A1/M1

A2/M2

A3/M3

A4/M4

A5/M5

A6/M6

NC

A7

A8

AUX IN

V 

SP+

V

P/R

XCLK

EOM

PD

CE

OVF

ANA OUT

ANA IN

AGC

MIC REF

MIC

V

SP–

CCD

CCA

ISD2532

ISD2540

ISD2548

ISD2564

DIP/SOIC

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

Microphone Input (MIC)

The microphone input transfers its signal to the on-

chip preamplifier. An on-chip Automatic Gain Con-

trol (AGC) circuit controls the gain of this

preamplifier from -15 to 24 dB. An external micro-

phone should be AC coupled to this pin via a series

capacitor. The capacitor value, together with the

internal 10 K ohm resistance on this pin, deter-

mines the low-frequency cutoff for the ISD2500

Series passband. See ISD's

Application Notes and

Design Manual

in this book for additional informa-

tion on low-frequency cutoff calculation.

Microphone Reference Input (MIC REF)

The MIC REF input is the inverting input to the

microphone preamplifier. This provides a noise-

canceling or common-mode rejection input to the

device when connected to a differential

microphone.

Automatic Gain Control Input (AGC)

The AGC dynamically adjusts the gain of the

preamplifier to compensate for the wide range of

microphone input levels. The AGC allows the full

range of whispers to loud sounds to be recorded

with minimal distortion. The “attack” time is deter-

mined by the time constant of a 5 K

Ω

internal

resistance and an external capacitor (C2 on the

schematic on page 1-100) connected from the

AGC pin to V

SSA

analog ground. The “release”

time is determined by the time constant of an

external resistor (R2) and an external capacitor

(C2) connected in parallel between the AGC Pin

and V

SSA

analog ground. Nominal values of

470 K

Ω

and 4.7

F give satisfactory results in

most cases.

Analog Output (ANA OUT)

This pin provides the preamplifier output to the

user. The voltage gain of the preamplifier is deter-

mined by the voltage level at the AGC pin.

Analog Input (ANA IN)

The analog input pin transfers its signal to the chip

for recording. For microphone inputs, the ANA

OUT pin should be connected via an external

capacitor to the ANA IN pin. This capacitor value,

together with the 3.0 K

Ω

input impedance of ANA

IN, is selected to give additional cutoff at the low-

frequency end of the voice passband. If the

desired input is derived from a source other than a

microphone, the signal can be fed, capacitively

coupled, into the ANA IN pin directly.

External Clock Input (XCLK)

The external clock input for the ISD2500 devices

has an internal pull-down device. These devices

are configured at the factory with an internal sam-

pling clock frequency centered to

1% of

ISD2532/40/48/64

* DEVICE PINOUTS

Advance information: ISD2532/40/48/64 devices.

1–84

Product Data Sheets

ISD2500 Series

-1

specification. The frequency is then maintained to

a variation of

2.25% over the entire commercial

temperature and operating voltage ranges. The

internal clock has a

5% tolerance over the indus-

trial temperature and voltage range. A regulated

power supply is recommended for industrial tem-

perature range parts. If greater precision is

required, the device can be clocked through the

XCLK pin as follows:

These recommended clock rates should not be

varied because the antialiasing and smoothing fil-

ters are fixed, and aliasing problems can occur if

the sample rate differs from the one recom-

mended. The duty cycle on the input clock is not

critical, as the clock is immediately divided by two.

THE

XCLK

NOT

USED

THIS

INPUT

MUST

CON-

NECTED

GROUND

Speaker Outputs (SP+/SP-)

All devices in the ISD2500 Series include an on-

chip differential speaker driver, capable of driving

50 milliwatts into 16

Ω

from AUX IN (12.2 mW from

memory).

The speaker outputs are held at V

SSA

levels during

record and power down. It is therefore not possible

to parallel speaker outputs of multiple ISD2500

devices or the outputs of other speaker drivers.

NOTE

Connection of speaker outputs in parallel

may cause damage to the device.

A single output may be used alone (including a

coupling capacitor between the SP pin and the

speaker). These outputs may be used individually

with the output signal taken from either pin. Using

the differential outputs results in a 4:1 improve-

ment in output power.

NOTE

Never ground or drive an unused speaker

output.

Auxiliary Input (AUX IN)

The Auxiliary Input is multiplexed through to the

output amplifier and speaker output pins when

is HIGH, P/R is HIGH, and Playback is currently

not active or if the device is in Playback overflow.

When cascading multiple ISD2500 devices, the

AUX IN pin is used to connect a Playback signal

from a following device to the previous output

speaker drivers. For noise considerations, it is sug-

gested that the auxiliary input not be driven when

the storage array is active.

Address/Mode Inputs (Ax/Mx)

The Address/Mode Inputs have two functions

depending on the level of the two Most Significant

Bits (MSB) of the address (A8 and A9 for the

ISD256075/90/120 devices, and A7 and A8 for the

ISD2532/40/48/64*

devices).

If either or both of the two MSBs are LOW, the

inputs are

ALL

interpreted as address bits and are

used as the start address for the current Record or

Playback cycle. The address pins are inputs only

and do not output internal address information as

the operation progresses. Address inputs are

latched by the falling edge of CE.

If both MSBs are HIGH, the Address/Mode Inputs

are interpreted as Mode bits according to the

Operational Mode table on page 1-85. There are

six operational modes (M0..M6) available as indi-

Part

Number Sample Rate Required Clock

ISD2560 8.0 KHz 1024 KHz

ISD2575 6.4 KHz 819.2 KHz

ISD2590 5.3 KHz 682.7 KHz

ISD25120 4.0 KHz 512 KHz

ISD2532* 8.0 KHz 1024 KHz

ISD2540* 6.4 KHz 819.2 KHz

ISD2548* 5.3 KHz 682.7 KHz

ISD2564* 4.0 KHz 512 KHz

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–85

cated in the table. It is possible to use multiple

operational modes simultaneously. Operational

Modes are sampled on each falling edge of CE,

and thus Operational Modes and direct addressing

are mutually exclusive.

OPERATIONAL MODES

The ISD2500 Series is designed with several built-

in operational modes that provide maximum func-

tionality with minimum additional components.

These are described in detail below. The opera-

tional modes use the address pins on the ISD2500

devices, but are mapped outside the valid address

range. When the two Most Significant Bits (MSBs)

are HIGH (A8 and A9 for the ISD2560/75/90/120

devices, and A7 and A8 for the

ISD2532/40/48/64*

devices), the remaining address signals are inter-

preted as mode bits and not as address bits.

Therefore, operational modes and direct address-

ing are not compatible and cannot be used

simultaneously.

There are two important considerations for using

operational modes. First, all operations begin ini-

tially at address 0, which is the beginning of the

ISD2500 address space. Later operations can

begin at other address locations, depending on the

operational mode(s) chosen. In addition, the

address pointer is reset to 0 when the device is

changed from Record to Playback, Playback to

Record (except M6 mode), or when a Power-Down

cycle is executed.

Second, Operational Modes are executed when

CE goes LOW and the two MSBs are HIGH. This

Operational Mode remains in effect until the next

LOW-going CE signal, at which point the current

address/mode levels are sampled and executed.

OPERATIONAL MODES DESCRIPTION

The Operational Modes can be used in conjunction

with a microcontroller, or they can be hard-wired to

provide the desired system operation.

M0 — Message Cueing

Message Cueing allows the user to skip through

messages, without knowing the actual physical

addresses of each message. Each CE LOW pulse

causes the internal address pointer to skip to the

next message. This mode should be used for

NOTE:

An asterisk (*) indicates additional operational modes which can be used simultaneously with the given mode.

Mode

Control Function Typical Use Jointly Compatible*

M0 Message cueing Fast-forward through messages M4, M5, M6

M1 Delete EOM markers Position EOM marker at the end of the last

message M3, M4, M5, M6

M2 Not applicable Reserved N/A

M3 Looping Continuous playback from Address 0 M1, M5, M6

M4 Consecutive address-

ing Record/Play multiple consecutive

messages M0, M1, M5

M5 CE level-activated Allows message pausing M0, M1, M3, M4

M6 Push-button control Simpliﬁed device interface M0, M1, M3

OPERATIONAL MODES TABLE

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–86

-1

Playback only, and is typically used with the M4

Operational Mode.

M1 — Delete EOM Markers

The M1 Operational Mode allows sequentially

recorded messages to be combined into a single

message with only one EOM marker set at the end

of the final message. When this operational mode

is configured, messages recorded sequentially are

played back as one continuous message.

M2 — Unused

When operational modes are selected, the M2 pin

should be LOW.

M3 — Message Looping

The M3 Operational Mode allows for the auto-

matic, continuously repeated playback of the

message located at the beginning of the address

space. A message

CAN

completely fill the ISD2500

device and will loop from beginning to end without

OVF going LOW.

M4 — Consecutive Addressing

During normal operations, the address pointer will

reset when a message is played through to an

EOM marker. The M4 Operational Mode inhibits

the address pointer reset on EOM, allowing mes-

sages to be played back consecutively.

M5 — CE-Level Activated

The default mode for ISD2500 devices is for CE to

be edge-activated on Playback and level-activated

on Record. The M5 Operational Mode causes the

CE pin to be interpreted as level-activated as

opposed to edge-activated during Playback. This

is specifically useful for terminating Playback oper-

ations using the CE signal.

In this mode, CE LOW begins a Playback cycle, at

the beginning of the device memory. The Playback

cycle continues as long as CE is held LOW. When

CE goes HIGH, Playback will immediately end. A

new CE LOW will restart the message from the

beginning unless M4 is also HIGH.

M6 — Push-Button Mode

The ISD2500 Series of devices contain a Push-

Button operational mode. The Push-Button mode

is used primarily in very low-cost applications and

is designed to minimize external circuitry and com-

ponents, thereby reducing system cost. In order to

configure the device in Push-Button operational

mode, the two most significant address bits must

be HIGH, and the M6 mode pin must also be

HIGH. A device in this mode always powers down

at the end of each Playback or Record

cycle after CE goes HIGH.

When this operational mode is implemented, sev-

eral of the pins on the device have alternate

functionality:

CE Pin (START/PAUSE)

In Push-Button Operational Mode, CE acts as a

LOW-going pulse-activated START/PAUSE sig-

nal. If no operation is currently in progress, a LOW-

going pulse on this signal will initiate a Playback or

a Record cycle according to the level on the P/R

pin. A subsequent pulse on the CE pin, before an

End-Of-Message is reached in Playback or an

overflow condition occurs, will cause the device to

pause. The address counter is not reset, and

another CE pulse will cause the device to continue

the operation from the place where it was paused.

PD Pin (STOP/RESET)

In push-button Operational Mode, PD acts as a

HIGH-going pulse-activated STOP/RESET signal.

When a Playback or Record cycle is in progress

and a HIGH-going pulse is observed on PD, the

Pin Name Alternate Functionality in

Push-Button Mode

CE Start/Pause Push-Button

(LOW pulse-activated)

PD Stop/Reset Push-Button

(HIGH pulse activated)

EOM Active-HIGH Run Indicator

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

1–87

current cycle is terminated and the address pointer

is reset to address 0, the beginning of the message

space.

EOM Pin (RUN)

In Push-Button Operational Mode, EOM becomes

an active-HIGH RUN signal which can be used to

drive an LED or other external device. It is HIGH

whenever a Record or Playback operation is in

progress.

Recording in Push-Button Mode

The PD pin should be LOW, usually using a

pulldown resistor.

The P/R pin is taken LOW.

The CE pin is pulsed LOW. Recording

starts, EOM goes HIGH to indicate an oper-

ation in progress.

The CE pin is pulsed LOW. Recording

pauses, EOM goes back LOW. The internal

address pointers are not cleared, but an

EOM marker is stored in memory to point to

the message end. The P/R pin may be

taken HIGH at this time. Any subsequent

CE would start a playback at address 0.

The CE pin is pulsed LOW. Recording

starts at the next address after the previous

set EOM marker. EOM goes back HIGH.

NOTE

If the M1 operational mode pin is also

HIGH, the just previously written EOM bit

is erased, and recording starts at that

address.)

When the recording sequences are fin-

ished, the final CE pulse LOW will end the

last Record cycle, leaving a set EOM

marker at the message end. Recording may

also be terminated by a HIGH level on PD,

which will leave a set EOM marker.

Playback in Push-Button Mode

The PD pin should be LOW.

The P/R pin is taken HIGH.

The CE pin is pulsed LOW. Playback starts,

EOM goes HIGH to indicate an operation in

progress.

If the CE pin is pulsed LOW or an EOM

marker is encountered during an operation,

the part will pause. The internal address

pointers are not cleared, and EOM goes

back LOW. The P/R pin may be changed at

this time. A subsequent Record operation

would not reset the address pointers and

the recording would begin where Playback

ended.

CE is again pulsed LOW. Playback starts

where it left off, with EOM going HIGH to

indicate an operation in progress.

Playback continues as in steps 4 and 5 until

PD is pulsed HIGH or overflow occurs.

If in overflow, pulling CE LOW will reset the

address pointer and start Playback from the

beginning. After a PD pulse, the part is reset

to address 0.

NOTE

Push-button mode can be used in con-

junction with modes M0, M1, and M3.

Good Audio Design Practices

ISD products are very high-quality single-chip

voice Recording and Playback systems. To ensure

the highest quality voice reproduction, it is impor-

tant that good audio design practices on layout and

power supply decoupling be followed. See the

ISD

Application Notes and Design Manual

in this book

for details.

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–88

-1

ISD1000A COMPATIBILITY

The ISD2500 Series of devices is designed to pro-

vide upward compatibility with the ISD1000A

family. When designing with the ISD2500 Series,

the following differences should be noted.

Addressing

The ISD2560/75/90/120 devices have 480K stor-

age cells designed to provide 60 seconds of

storage at a sampling rate of 8.0 KHz. This is

approximately four times the storage of the

ISD1000A family. To enable the same addressing

resolution, two additional address pins have been

added. The address space of each device is divis-

ible into 300 increments with valid addressing from

00 to 13F Hex. Some higher addresses are

mapped into the Operational Modes. All other

addresses are invalid.

The ISD2532/40/48/64 devices have 256K storage

cells designed to provide 32 seconds of storage at

a sampling rate of 8.0 KHz. This is twice the

amount of storage of the ISD1000A family. To

enable the same addressing resolution, one addi-

tional address pin has been added. The address

space of each device is divisable into 320 incre-

ments with valid addressing from 00 to 13F Hex.

Overﬂow

The ISD1000A Series combined two functions on

the EOM pin: end-of-message indication and over-

flow. The ISD2500 separates these two functions.

Pin 25 (PDIP package) remains as EOM, but out-

puts only the EOM signal indication. Pin 22 (PDIP

package) becomes OVF and pulses LOW only

when the device reaches its end of memory, or is

“full.” This change allows easy message cueing

and addressability across device boundaries. This

also means that the M2 operational mode found in

the ISD1000A family is not implemented in the

ISD2500 Series.

Push-Button Mode

The ISD2500 Series includes an additional Opera-

tional Mode called Push-Button mode. This

provides an alternative interface to the Record and

Playback functions of the part. The CE and PD

pins become redefined as edge-activated “push-

buttons.” A pulse on CE initiates a cycle, and if

triggered again, pauses the current cycle without

resetting the address pointer (i.e., a Start or Pause

function). PD stops any current cycle and resets

the address pointer to the beginning of the mes-

sage space (i.e., a Stop and Reset function).

Additionally, the EOM pin functions as an active-

HIGH run indicator, and can be used to drive an

LED indicating a Record or Playback operation is

in progress. Devices in the Push-Button mode can-

not be cascaded.

Looping Mode

The ISD2500 Series can loop with a message that

completely fills the memory space.

NOTE

Additional descriptions of ISD2500 device

functionality and application examples are

provided in the ISD Application Notes and

Design Manual in this book.

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

1–89

A0-A9

CE



MIC

ANA IN

TCE

TPDH TPDS TPDR

TSET

THOLD

OVF



TPUD

Don't Care

TSET

P/R

TOVF

Playback

A0-A9

CE



TCE

TSET

THOLD

SP+/–

OVF

EOM

TPUD TEOM

Don't Care

TSET

P/R

TPDH TPDS TPDP

TOVF

TIMING DIAGRAMS

Record

Advance information: ISD2532/40/48/64 devices.

1–90

Product Data Sheets

ISD2500 Series

-1

ABSOLUTE MAXIMUM RATINGS

(PACKAGED PARTS)

NOTE: Stresses above those listed may cause permanent

damage to the device. Exposure to the absolute

maximum ratings may affect device reliability.

Functional operation is not implied at these

conditions.

Condition Value

Junction temperature 150° C

Storage temperature range –65° C to +150° C

Voltage applied to any pin (VSS – 0.3 V) to

(VCC + 0.3 V)

Voltage applied to any pin

(Input current limited to ±20 mA) (VSS – 1.0 V) to

(VCC + 1.0 V)

Lead temperature (soldering –

10 seconds) 300° C

VCC - VSS – 0.3 V to + 7.0 V

OPERATING CONDITIONS

(PACKAGED PARTS)

NOTES: 1. Case temperature.

2. V

= V

CCA

= V

CCD.

3. V

= V

SSA

= V

SSD

Condition Value

Commercial operating

temperature range(1) 0° C to +70° C

Industrial operating

temperature range(1) –40° C to +85° C

Supply voltage (VCC)(2) +4.5 V to +5.5 V

Ground voltage (VSS)(3) 0 V

DC PARAMETERS (PACKAGED PARTS)

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage 0.4 V IOL = 4.0 mA

VOH Output High Voltage VCC–0.4 V IOH = – 10 µA

VOH1 OVF Output High Voltage 2.4 V IOH = – 1.6 mA

VOH2 EOM Output High Voltage VCC–1.0 VCC–0.8 V IOH = – 3.2 mA

ICC VCC Current (Operating) 25 30 mA REXT = ∞ (3)

ISB VCC Current (Standby) 1 10 µA(3)

IIL Input Leakage Current +1 µA

IILPD Input Current HIGH w/Pull

Down 130 µAForce VCC (4)

REXT Output Load Impedance 16 ΩSpeaker Load

RMIC Preamp In Input Resistance 4 9 15 KΩMIC and MIC REF Pins

RAUX AUX INPUT Resistance 5 11 20 KΩ

Advance information: ISD2532/40/48/64 devices.

1–91

Product Data Sheets ISD2500 Series

NOTES: 1. Typical values @ T

= 25

C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.

Not all specifications are 100% tested.

3. V

CCA

and V

CCD

connected together.

4. XCLK pin only.

AC PARAMETERS (PACKAGED PARTS)

RANA IN ANA IN Input Resistance 2.3 3 5 KΩ

APRE1 Preamp Gain 1 21 24 26 dB AGC = 0.0 V

APRE2 Preamp Gain 2 –15 5 dB AGC = 2.5 V

AAUX AUX IN/SP+ Gain 0.98 1.0 V/V

AARP ANA IN to SP+/- Gain 21 23 26 dB

RAGC AGC Output Resistance 2.5 5 9.5 KΩ

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

FSSampling —

ISD2532*

Frequency —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

8.0

6.4

5.3

4.0

8.0

6.4

5.3

4.0

KHz

(7)

FCF Filter Pass Band —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

3.4

2.7

2.3

1.7

3.4

2.7

2.3

1.7

KHz

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point (3) (8)

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

DC PARAMETERS (PACKAGED PARTS) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

1–92

Product Data Sheets

ISD2500 Series

-1

TREC Record —

ISD2532*

Duration —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

58.1

56.5

72.6

70.7

87.1

116.1

32.0

40.0

48.0

64.0

60.0

75.0

90.0

120.0

62.0

63.8

77.5

79.7

93.0

123.9

sec

Commercial Operation

Industrial Operation

Commercial Operation

Industrial Operation

Commercial Operation

TPLAY Playback —

ISD2532*

Duration —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

58.1

56.5

72.6

70.7

87.1

116.1

32.0

40.0

48.0

64.0

60.0

75.0

90.0

120.0

62.0

63.8

77.5

79.7

93.0

123.9

sec

(7)

Commercial Operation(7)

Industrial Operation(7)

Commercial Operation(7)

Industrial Operation(7)

Commercial Operation(7)

TCE CE Pulse Width 100 nsec

TSET Control/Address Setup Time 300 nsec

THOLD Control/Address Hold Time 0 nsec

TPUD Power-Up Delay —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

24.1

23.5

30.2

29.3

36.2

48.2

25.0

31.3

37.5

50.0

25.0

31.3

37.5

50.0

27.8

28.5

34.3

35.2

40.8

53.6

msec

Commercial Operation

Industrial Operation

Commercial Operation

Industrial Operation

Commercial Operation

TPDR PD Pulse —

ISD2532*

Width Record —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

31.25

37.5

50.0

31.25

37.5

50.0

msec

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

AC PARAMETERS (PACKAGED PARTS) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

1–93

Product Data Sheets ISD2500 Series

NOTES: 1. Typical values @ T

= 25

C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.

Not all specifications are 100% tested.

3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).

4. From AUX IN; if ANA IN is driven at 50 mV p-p, the P

OUT

=12.2 mW, typical.

5. With 5.1 K

Ω

series resistor at ANA IN.

6. T

PDS

is required during a static condition, typically overflow.

7. Sampling Frequency and Playback Duration can vary as much as

2.25% over the commercial

temperature range and voltage range and

5% over the industrial temperature and voltage range.

For greater stability, an external clock can be utilized (see Pin Descriptions).

8. Filter specification applies to the antialiasing filter and the smoothing filter.

TPDP PD Pulse —

ISD2532*

Width Play —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

12.5

15.625

18.75

25.0

12.5

15.625

18.75

25.0

msec

TPDS PD Pulse Width Static 100 nsec (6)

TPDH Power Down Hold 0 nsec

TEOM EOM Pulse Width —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

12.5

15.625

18.75

25.0

12.5

15.625

18.75

25.0

msec

TOVF Overﬂow Pulse Width 6.5 µsec

THD Total Harmonic Distortion 1 2 % @ 1 KHz

POUT Speaker Output Power 12.2 50 mW REXT = 16 Ω (4)

VOUT Voltage Across Speaker Pins 2.5 V p–p REXT = 600 Ω

VIN1 MIC Input Voltage 20 mV Peak-to-Peak (5)

VIN2 ANA IN Input Voltage 50 mV Peak-to-Peak

VIN3 Aux Input Voltage 1.25 V Peak-to-Peak;

REXT = 16 Ω

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

AC PARAMETERS (PACKAGED PARTS) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

1–94

Product Data Sheets

ISD2500 Series

-1

TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE

(PACKAGED PARTS)

-40 25 70 85

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-40

1.2

1.0

0.8

0.6

0.4

0.2

-40

025 70 8525 70 85

-40 25 70 85

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

5.5 V olts 4.5 V olts

Operating Current (mA)

Temperature (C)

Standby Current (µA)

Temperature (C)

Percent Change (%)

Temperature (C)

Percent Distortion (%)

Temperature (C)

TOTAL HARMONIC DISTORTION OSCILLATOR STABILITY

RECORD MODE OPERATING CURRENT (I

)STANDBY CURRENT (I

)

Advance information: ISD2532/40/48/64 devices.

1–95

Product Data Sheets ISD2500 Series

ABSOLUTE MAXIMUM RATINGS (DIE)

NOTE: Stresses above those listed may cause permanent

damage to the device. Exposure to the absolute

maximum ratings may affect device reliability.

Functional operation is not implied at these

conditions.

Condition Value

Junction temperature 150° C

Storage temperature range –65° C to +150° C

Voltage applied to any pad (VSS – 0.3 V) to

(VCC + 0.3 V)

Voltage applied to any pad

(Input current limited to

+ 20 mA)

(VSS – 1.0 V) to

(VCC + 1.0 V)

VCC - VSS – 0.3 V to + 7.0 V

OPERATING CONDITIONS (DIE)

NOTES: 1. V

= V

CCA

= V

CCD

2. V

= V

SSA

= V

SSD

Condition Value

Commercial operating

temperature range 0° C to +50° C

Supply voltage (VCC)(1) +4.5 V to +6.5 V

Ground voltage (VSS)(2) 0 V

DC PARAMETERS (DIE)

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage 0.4 V IOL = 4.0 mA

VOH Output High Voltage VCC–0.4 V IOH = – 10 µA

VOH1 OVF Output High Voltage 2.4 V IOH = – 1.6 mA

VOH2 EOM Output High Voltage VCC–1.0 VCC–0.8 V IOH = – 3.2 mA

ICC VCC Current (Operating) 25 30 mA REXT = ∞ (3)

ISB VCC Current (Standby) 1 10 µA(2)

IIL Input Leakage Current +1 µA

IILPD Input Current HIGH w/Pull

Down 130 µAForce VCC (4)

REXT Output Load Impedance 16 ΩSpeaker Load

RMIC Preamp In Input Resistance 4 9 15 KΩMIC and MIC REF Pads

RAUX AUX INput Resistance 5 11 20 KΩ

RANA IN ANA IN Input Resistance 2.3 3 5 KΩ

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets

ISD2500 Series

1–96

-1

NOTES: 1. Typical values @ T

= 25

C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.

Not all specifications are 100% tested.

3. V

CCA

and V

CCD

connected together.

4. XCLK pad only.

AC PARAMETERS (DIE)

APRE1 Preamp Gain 1 21 24 26 dB AGC = 0.0 V

APRE2 Preamp Gain 2 – 15 5 dB AGC = 2.5 V

AAUX AUX IN/SP+ Gain 0.98 1.0 V/V

AARP ANA IN to SP+/- Gain 21 23 26 dB

RAGC AGC Output Resistance 2.5 5 9.5 KΩ

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

FSSampling —

ISD2532*

Frequency —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

8.0

6.4

5.3

4.0

8.0

6.4

5.3

4.0

KHz

(7)

FCF Filter Pass Band —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

3.4

2.7

2.3

1.7

3.4

2.7

2.3

1.7

KHz

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point

(3) (8)

3 dB Roll-Off Point (3) (8)

TREC Record —

ISD2532*

Duration —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

58.1

72.6

87.1

116.1

32.0

40.0

48.0

64.0

60.0

75.0

90.0

120.0

62.0

77.5

93.0

123.9

sec

Commercial Operation

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

DC PARAMETERS (DIE) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

1–97

TPLAY Playback —

ISD2532*

Duration —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

58.1

72.6

87.1

116.1

32.0

40.0

48.0

64.0

60.0

75.0

90.0

120.0

62.0

77.5

93.0

123.9

sec

(7)

Commercial Operation(7)

TCE CE Pulse Width 100 nsec

TSET Control/Address Setup Time 300 nsec

THOLD Control/Address Hold Time 0 nsec

TPUD Power-Up Delay —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

24.1

30.2

36.2

48.2

25.0

31.3

37.5

50.0

25.0

31.3

37.5

50.0

27.8

34.3

40.8

53.6

msec

Commercial Operation

TPDR PD Pulse —

ISD2532*

Width Record —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

31.25

37.5

50.0

31.25

37.5

50.0

msec

TPDP PD Pulse —

ISD2532*

Width Play —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

12.5

15.625

18.75

25.0

12.5

15.625

18.75

25.0

msec

TPDS PD Pulse Width Static 100 nsec (6)

TPDH Power Down Hold 0 nsec

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

AC PARAMETERS (DIE) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

1–98

Product Data Sheets

ISD2500 Series

-1

NOTES: 1. Typical values @ T

= 25

C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.

Not all specifications are 100% tested.

3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).

4. From AUX IN; if ANA IN is driven at 50 mV p-p, the P

OUT

=12.2 mW, typical.

5. With 5.1 K

Ω

series resistor at ANA IN.

6. T

PDS

is required during a static condition, typically overflow.

7. Sampling Frequency and Playback Duration can vary as much as

2.25% over the commercial temperature range

and voltage range. For greater stability, an external clock can be utilized (see Pin Descriptions).

8. Filter specification applies to the antialiasing filter and the smoothing filter.

TEOM EOM Pulse Width —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

12.5

15.625

18.75

25.0

12.5

15.625

18.75

25.0

msec

TOVF Overﬂow Pulse Width 6.5 µsec

THD Total Harmonic Distortion 1 3 % @ 1 KHz

POUT Speaker Output Power 12.2 50 mW REXT = 16 Ω (4)

VOUT Voltage Across Speaker Pins 2.5 V p–p REXT = 600 Ω

VIN1 MIC Input Voltage 20 mV Peak-to-Peak (5)

VIN2 ANA IN Input Voltage 50 mV Peak-to-Peak

VIN3 Aux Input Voltage 1.25 V Peak-to-Peak;

REXT = 16 Ω

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

AC PARAMETERS (DIE) – CONTINUED

Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

1–99

TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE (DIE)

02550

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1.0

0.8

0.6

0.4

0.2

0255002550

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

02550

6.5 V olts 5.5 V olts 4.5 V olts

Operating Current (mA)

Temperature (C)

Standby Current (µA)

Temperature (C)

Percent Change (%)

Temperature (C)

Percent Distortion (%)

Temperature (C)

TOTAL HARMONIC DISTORTION OSCILLATOR STABILITY

RECORD MODE OPERATING CURRENT (I

)STANDBY CURRENT (I

)

Advance information: ISD2532/40/48/64 devices.

1–100

Product Data Sheets

ISD2500 Series

-1

SSD

SSA

A0

A1

A2

A3

A4

A5

A6

(NC*)



(A7*)



(A8*)



CE

PD

P/R

EOM

OVF

XCLK

V 

V 

V 

V 

SP+

SP–

AUX IN

ANA IN

ANA OUT

MIC REF**

MIC

AGC

CCD

CCA

16 Ω

SPEAKER

1

2

3

4

5

6

7

8

9

10



23

24

27

25

22

28

16



12

13



14

15

11

20



21



18

17



ELECTRET

MICROPHONE

0.1 µF

22 µF

PLAYBACK/RECORD

POWER DOWN

CHIP ENABLE

ISD2500 (PDIP/SOIC)

0.1 µF0.1 µF

0.1 µF

4.7 µF

470 KΩ

1 KΩ

R110 KΩ

220 µF

100 KΩ

C6C7C8

5.1 KΩ

10 KΩ

ISD2500 APPLICATION EXAMPLE – DESIGN SCHEMATIC

APPLICATION EXAMPLE – BASIC DEVICE CONTROL

Control Step Function Action

1 Power up chip and select Record/Playback mode 1. PD = LOW, 2. P/R = As desired

2 Set message address for Record/Playback Set addresses A0–A9

3A Begin Playback P/R = HIGH, CE = Pulsed LOW

3B Begin Record P/R = LOW, CE = LOW

4B End Playback

End Record Automatic

PD or CE = HIGH

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are

indicated.

** If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In this case,

pin 18 must not be tied to any other signal or voltage. Additional design example schematics are provided in the

Application Notes and Design Manual in this book.

Advance information: ISD2532/40/48/64 devices.

1–101

Product Data Sheets ISD2500 Series

Advance information: ISD2532/40/48/64 devices.

APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS

Part Function Comments

R1 Microphone power supply

decoupling Reduces power supply noise

R2 Release time constant Sets release time for AGC

R3, R5 Microphone biasing resistors Provides biasing for microphone operation

R4 Series limiting resistor Reduces level to prevent distortion at higher supply

voltages.

R6 Series limiting resistor Reduces level to high supply voltages

C1, C5 Microphone DC–blocking capacitor

Low-frequency cutoff Decouples microphone bias from chip. Provides single-

pole low-frequency cutoff and common mode noise

rejection.

C2 Attack/Release time constant Sets attack/release time for AGC

C3 Low-frequency cutoff capacitor Provides additional pole for low-frequency cutoff

C4 Microphone power supply

decoupling Reduces power supply noise

C6, C7, C8 Power supply capacitors Filter and bypass of power supply

In this simplified block diagram of a microcontroller

application, the Push-Button mode and message

cueing are used. The microcontroller is a 16-pin

version with enough port pins for buttons, an LED,

and the ISD2500 Series device. The software can

be written to use three buttons: one each for play

and record, and one for message selection.

Because the microcontroller is interpreting the but-

tons and commanding the ISD2500 device,

software can be written for any functions desired in

a particular application.

NOTE

ISD does not recomend connecting

address lines directly to a microprocessor

bus. Address lines should be externally

latched.

EXPLANATION

1–102

Product Data Sheets

ISD2500 Series

-1

Advance information: ISD2532/40/48/64 devices.

ISD2500 APPLICATION EXAMPLE – MICROCONTROLLER/ISD2500 INTERFACE

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the

ISD2560/75/90/120 devices are indicated.

SSD

SSA

CCD

CCA

A0

A1

A2

A3

A4

A5

A6

(NC*)



(A7*)

A9 (A8*)

CE

PD

P/R

EOM

OVF

XCLK

1

2

3

4

5

6

7

8

9

10



23

24

27

25

22

28

16



12

13



14

15

11

20



21



18

17



OSC1

OSC2

RESET

IRQ

V

V

PB0

PB1

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

ISD2500 (PDIP/SOIC)

MC68HC705K1A

RUN

S2 MSG

PLAY S3

RECORD

TBD

Product Data Sheets ISD2500 Series

1–103

Advance information: ISD2532/40/48/64 devices.

APPLICATION EXAMPLE – PUSH-BUTTON CONTROL

Control Step Function Action

1 Select Record/Playback mode P/R = As desired

Begin Playback

Begin Record

P/R = HIGH

CE = Pulsed LOW

P/R = LOW

CE = Pulsed LOW

3 Pause Record or Playback CE = Pulsed LOW

End Payback

End Record

Automatic at EOM marker or

PD = Pulsed HIGH

ISD2500 APPLICATION EXAMPLE – PUSH-BUTTON

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the

ISD2560/75/90/120 devices are indicated.

** For more details, please refer to the ISD Application Notes and Design Manual.

SSD

SSA

A0

A1

A2

A3

A4

A5

A6

(NC*)



(A7*)



(A8*)



CE

PD

P/R

EOM

OVF

XCLK

V 

V 

V 

V 

SP+

SP–

AUX IN

ANA IN

ANA OUT

MIC REF

MIC

AGC

CCD

CCA

16 Ω

SPEAKER

1

2

3

4

5

6

7

8

9

10



23

24

27

25

22

28

16



12

13



14

15

11

20



21



18

17



LS1

0.1 µF

100 KΩ

START/PAUSE

STOP/RESET

PLAYBACK/RECORD

C5

22 µF

C4

0.1 µFC1

0.1 µF

ISD2500 (PDIP/SOIC)

5.1 KΩ

RELECTRET

MICROPHONE

0.1 µF

4.7 µF

470 KΩ

10 KΩ

220 µF10 KΩ

Product Data Sheets

ISD2500 Series

1–104

-1

Advance information: ISD2532/40/48/64 devices.

APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS

PUSH-BUTTON PARAMETERS

Part Function Comments

R2 Release time constant Sets release time for AGC

R4 Series limiting resistor Reduces lev el to prev ent distortion at

higher supply voltages

R6, R7 Pull-up and pull-down resistors Deﬁnes static state of inputs

C1, C4, C5 Power supply capacitors Filters and bypass of power supply

C2 Attack/Release time constant Sets attack/release time for AGC

C3 Low-frequency cutoff capacitor Provides additional pole for low-

frequency cutoff

Symbol Characteristic Min Typ (1) Max Units Conditions

TCE CE Pulse Width [Start/Pause] 300 nsec

TSET Control/Address Setup Time 300 nsec

TPUD Power-Up Delay —

ISD2532*

—

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

31.25

37.25

50.0

31.25

37.25

50.0

msec

TPD PD Pulse Width [Stop/Reset] 300 nsec

TRUN CE to EOM HIGH 25 400 nsec

TPAUSE CE to EOM LOW 50 400 nsec

TDB CE HIGH —

ISD2532*

Debounce —

ISD2540*

—

ISD2548*

—

ISD2564*

— ISD2560

— ISD2575

— ISD2590

— ISD25120

105

135

105

135

105

135

160

215

105

135

160

215

msec

Product Data Sheets ISD2500 Series

1–105

Advance information: ISD2532/40/48/64 devices.

A0-A9

CE

(Start/Pause)



TPD

PD

(Stop/Reset)

MIC ANA IN

OVF

EOM

(Run)

TSET

TRUN

TPUD

TSET

P/R TSET TSET

TSET

TCE

TPAUSE

TCE TCE

TPUD

(1) (2) (3) (4, 5)

TDB TDB

(6, 7) (8)

TDB

Notes:

"Start" "Pause" "Stop""Start"



A0-A9

CE

(Start/Pause)



TPD

PD

(Stop/Reset)

SP+/–

OVF

EOM

(Run)

TSET

TRUN

TSET

P/R TSET TSET

TSET

TCE

TPAUSE

TCE TCE

TPUD TPUD

(1)Notes: (2) (3) (4, 5)

TDB TDB

(6, 7) (8)

TDB

"Start" "Pause" "Stop""Start"

TIMING DIAGRAMS

Push-Button Mode Record

Push-Button Mode Playback

NOTES: 1. A9, A8, and A6 = 1 for push-button operation.

2. The first CE LOW pulse performs a Start function.

3. The part will begin to play or record after a power-up delay T

PUD

4. The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of

CE and pause.

5. The second CE LOW pulse, and every even pulse thereafter, performs a Pause function.

6. Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling

edge of CE, which would restart an operation. In addition, the part will not do an internal power down until

CE is HIGH for the TDB time.

7. The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function.

8. At any time, a HIGH level on PD will stop the current function, reset the address counter, and power down

the device.

Product Data Sheets

ISD2500 Series

1–106

-1

Advance information: ISD2532/40/48/64 devices.

2 = 2nd Generation

5 = 5 Volts

Duration:

32 = 32 Seconds*

40 = 40 Seconds*

48 = 48 Seconds*

64 = 64 Seconds*

60 = 60 Seconds

75 = 75 Seconds

90 = 90 Seconds

120 = 120 Seconds

ORDERING INFORMATION

Part Number Part Number Part Number Part Number

ISD2560E ISD2575E ISD2590E ISD25120P

ISD2560EI ISD2575EI ISD2590P ISD25120X

ISD2560P ISD2575P ISD2590S

ISD2560PI ISD2575PI ISD2590T

ISD2560S ISD2575S ISD2590X

ISD2560SI ISD2575SI

ISD2560T ISD2575T

ISD2560TI ISD2575TI

ISD2560X ISD2575X

ISD25 _ _ _ _

Special Temperature Field:

Blank = Commercial Packaged (0˚C to +70˚C)

or Commercial Die (0˚C to +50˚C)

I = Industrial (-40˚C to +85˚C)

Package Type:

E = 28-Lead 8x13.4-mm Thin Small Outline Package

(TSOP)

P = 28-Lead 0.600-Inch Plastic Dual In-Line Package

(PDIP)

S = 28-Lead 0.300-Inch Small Outline Integrated Circuit

(SOIC)

T = 32-Lead 8x20-mm Thin Small Outline Package

(TSOP)

X = Die

Product Number Descriptor Key

When ordering ISD2500 Series devices, please refer to the following valid part numbers.

For the latest product information, access ISD’s worldwide website at http://www.isd.com.