LC2MOS
Precision Quad SPST Switches
ADG411/ADG412/ADG413
Rev. C
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Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
44 V supply maximum ratings
±15 V analog signal range
Low on resistance (< 35 Ω)
Ultralow power dissipation (35 µW)
Fast switching times
tON < 175 ns
tOFF < 145 ns
TTL-/CMOS-compatible
Plug-in replacement for DG411/DG412/DG413
APPLICATIONS
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
GENERAL DESCRIPTION
The ADG411, ADG412, and ADG413 are monolithic CMOS
devices comprising four independently selectable switches.
They are designed on an enhanced LC2MOS process which
provides low power dissipation yet gives high switching speed
and low on resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
The ADG411, ADG412, and ADG413 contain four independent
SPST switches. The ADG411 and ADG412 differ only in that
the digital control logic is inverted. The ADG411 switches are
turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG412. The ADG413
has two switches with digital control logic similar to that of the
ADG411 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when on,
and each has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
All switches exhibit break-before-make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.
PRODUCT HIGHLIGHTS
1. Extended signal range
The ADG411, ADG412, and ADG413 are fabricated on an
enhanced LC2MOS, giving an increased signal range which
extends fully to the supply rails.
2. Ultralow power dissipation
3. Low RON
4. Break-before-make switching
This prevents channel shorting when the switches are
configured as a multiplexer.
5. Single-supply operation
For applications where the analog signal is unipolar, the
ADG411, ADG412, and ADG413 can be operated from a
single-rail power supply. The parts are fully specified with a
single 12 V power supply and remain functional with single
supplies as low as 5 V.
FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG411
SWITCHES SHOWN FOR A LOGIC 1 INPUT
00024-001
Figure 1. ADG411
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG412
SWITCHES SHOWN FOR A LOGIC 1 INPUT
00024-002
Figure 2. ADG412
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG413
SWITCHES SHOWN FOR A LOGIC 1 INPUT
00024-003
Figure 3. ADG413
ADG411/ADG412/ADG413
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................7
Termi no log y .......................................................................................9
Applications..................................................................................... 10
Test Circuits ..................................................................................... 11
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
11/04—Rev. B to Rev. C
Format Updated..................................................................Universal
Change to Package Drawing (Figure 23)..................................... 13
Changes to Ordering Guide .......................................................... 14
7/04—Rev. A to Rev. B
Changes to ORDERING GUIDE .....................................................5
Updated OUTLINE DIMENSIONS ...............................................11
ADG411/ADG412/ADG413
Rev. C | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = –15 V ± 10%, VL = 5 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 1.
B Version T Version
Parameter +25°C −40°C to +85°C +25°C −55°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
DD to VSS V
RON 25 25 Ω typ VD = ±8.5 V, IS = −10 mA;
35 45 35 45 Ω max VDD = +13.5 V, VSS = −13.5 V
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source OFF Leakage IS (OFF) ±0.1 ±0.1 nA typ
VD = +15.5 V/−15.5 V,
VS = −15.5 V/+15.5 V;
±0.25 ±0.25 ±0.25 ±20 nA max Figure 15
Drain OFF Leakage ID (OFF) ±0.1 ±0.1 nA typ VD = +15.5 V/−15.5 V,
VS = −15.5 V/+15.5 V;
±0.25 ±5 ±0.25 ±20 nA max Figure 15
Channel ON Leakage ID, IS (ON) ±0.1 ±0.1 nA typ VD = VS = +15.5 V/−15.5 V;
±0.4 ±10 ±0.4 ± 40 nA max Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 V min
Input Low Voltage, VINL 0.8 0.8 V max
Input Current
IINL or IINH 0.005 0.005 µA typ VIN = VINL or VINH
±0.5 ±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 110 110 ns typ RL = 300 Ω, CL = 35 pF;
175 175 ns max VS = ±10 V; Figure 17
tOFF 100 100 ns typ RL = 300 Ω, CL = 35 pF;
145 145 ns max VS = ±10 V; Figure 17
Break-Before-Make Time Delay,
tD (ADG413 Only)
25 25 ns typ
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = 10 V; Figure 18
Charge Injection 5 5 pC typ
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Figure 19
OFF Isolation 68 68 dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 20
Channel-to-Channel Crosstalk 85 85 dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 21
CS (OFF) 9 9 pF typ f = 1 MHz
CD (OFF) 9 9 pF typ f = 1 MHz
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V;
Digital inputs = 0 V or 5 V
IDD 0.0001 0.0001 µA typ
1 5 1 5 µA max
ISS 0.0001 0.0001 µA typ
1 5 1 5 µA max
IL0.0001 0.0001 µA typ
1 5 1 5 µA max
1 Temperature ranges are as follows: B versions: −40°C to +85°C; T versions: −55°C to +125°C.
2 Guaranteed by design; not subject to production test.
ADG411/ADG412/ADG413
Rev. C | Page 4 of 16
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 2.
B Version T Version
Parameter +25°C −40°C to + 85°C +25°C −55°C to +125°C Unit Test Conditions/Comments
ANALOG SIGNAL RANGE 0 V to VDD 0 V to VDD V
RON 40 40 Ω typ 0 < VD = 8.5 V, IS = −10 mA;
80 100 80 100 Ω max VDD = 10.8 V
LEAKAGE CURRENTS VDD = 13.2 V
Source OFF Leakage IS (OFF) ±0.1 ±0.1 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V;
±0.25 ±5 ±0.25 ±20 nA max Figure 15
Drain OFF Leakage ID (OFF) ±0.1 ±0.1 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V;
±0.25 ±5 ±0.25 ±20 nA max Figure 15
Channel ON Leakage ID, IS (ON) ±0.1 ±0.1 nA typ VD = VS = 12.2 V/1 V;
±0.4 ±10 ±0.4 ±40 nA max Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 V min
Input Low Voltage, VINL 0.8 0.8 V max
Input Current
IINL or IINH 0.005 0.005 µA typ VIN = VINL or VINH
±0.5 ±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 175 175 ns typ RL = 300 Ω, CL = 35 pF;
250 250 ns max VS = 8 V; Figure 17
tOFF 95 95 ns typ RL = 300 Ω, CL = 35 pF;
125 125 ns max VS = 8 V; Figure 17
Break-Before-Make Time
Delay, tD (ADG413 Only)
25 25 ns typ
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +10 V; Figure 18
Charge Injection 25 25 pC typ VS = 0 V, RS = 0 Ω, CL = 10 nF;
Figure 19
OFF Isolation 68 68 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 20
Channel-to-Channel Crosstalk 85 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 21
CS (OFF) 9 9 pF typ f = 1 MHz
CD (OFF) 9 9 pF typ f = 1 MHz
CD, CS (ON) 35 35 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V;
Digital inputs = 0 V or 5 V
IDD 0.0001 0.0001 µA typ
1 5 1 5 µA max
IL0.0001 0.0001 µA typ
1 5 1 5 µA max VL = 5.25 V
1 Temperature ranges are as follows: B versions:−40°C to +85°C; T versions: −55°C to +125°C.
2 Guaranteed by design; not subject to production test.
Table 3. Truth Table (ADG411/ADG412)
ADG411 In ADG412 In Switch Condition
0 1 ON
1 0 OFF
Table 4. Truth Table (ADG413)
Logic Switch 1, 4 Switch 2, 3
0 OFF ON
1 ON OFF
ADG411/ADG412/ADG413
Rev. C | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameters Ratings
VDD to VSS 44 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
VL to GND −0.3 V to VDD + 0.3 V
Analog, Digital Inputs1VSS − 2 V to VDD + 2 V or
30 mA, whichever
occurs first
Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle max)
100 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Extended (T Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
CERDIP Package, Power Dissipation 900 mW
θJA Thermal Impedance 76°C/W
Lead Temperature, Soldering (10 s) 300°C
PDIP, Power Dissipation 470 mW
θJA Thermal Impedance 117°C/W
Lead Temperature, Soldering (10 s) 260°C
SOIC Package, Power Dissipation 600 mW
θJA Thermal Impedance 77°C/W
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 115°C/W
θJC Thermal Impedance 35°C/W
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
________________________________________
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG411/ADG412/ADG413
Rev. C | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00024-004
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN2
D2
S2
V
DD
V
L
S3
D3
IN3
ADG411/
ADG412/
ADG413
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 9, 16 IN1–IN4 Logic Control Input.
2, 7, 10, 15 D1–D4 Drain Terminal. Can be an input or output.
3, 6, 11, 14 S1–S4 Source Terminal. Can be an input or output.
4 VSS Most Negative Power Supply Potential in Dual Supplies. In single supply applications, it may be
connected to GND.
5 GND Ground (0 V) Reference.
12 VLLogic Power Supply (5 V).
13 VDD Most Positive Power Supply Potential.
ADG411/ADG412/ADG413
Rev. C | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
50
0
10
20
30
40
–20 20
VDD = +5V
VSS = –5V
VDD = +10V
VSS = –10V VDD = +12V
VSS = –12V
TA = 25°C
VL = +5V
VDD = +15V
VSS = –15V
100–10
00024-005
VD OR VS– DRAIN OR SOURCE VOLTAGE (V)
RON (Ω)
Figure 5. On Resistance as a Function of VD (VS) Dual Supplies
50
0
10
20
30
40
–20 –15 –10 –5 0 5 10 15 20
85°C
25°C
00024-006
VD OR VS– DRAIN OR SOURCE VOLTAGE (V)
RON (Ω)
VDD = +15V
VSS = –15V
VL = +5V
125°C
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures
10
1
0.1
0.01
0.001
100 1k 10k 100k 1M 100M
00024-007
FREQUENCY (Hz)
LEAKAGE CURRENT (nA)
I
D
(OFF)
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
V
D
= ±15V
V
S
= ±15V I
S
(OFF)
I
D
(ON)
Figure 7. Leakage Currents as a Function of Temperature
50
0
10
20
30
40
02
V
DD
= +10V
V
SS
= 0V
T
A
= 25°C
V
L
= +5V
V
DD
= +15V
V
SS
= 0V
15105
00024-008
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE (V)
R
ON
(
Ω
)
0
V
DD
= +5V
V
SS
= 0V
V
DD
= +12V
V
SS
= 0V
Figure 8. On Resistance as a Function of VD (VS) Single Supply
100m
10m
1m
100µ
10µ
1µ
100n10 100 1k 10k 100k 1M 10M
00024-009
FREQUENCY (Hz)
I
SUPPLY
(A)
I+, I–
I
L
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
4 SW
1 SW
Figure 9. Supply Current vs. Input Switching Frequency
0.04
–0.04
–0.02
0
0.02
–20 20100–10
00024-010
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE (V)
LEAKAGE CURRENT (nA)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
V
L
= +5V I
D
(ON)
I
S
(OFF)
I
D
(OFF)
Figure 10. Leakage Currents as a Function of VD (VS)
ADG411/ADG412/ADG413
Rev. C | Page 8 of 16
120
40
60
80
100
100 10M1M100k10k1k
00024-011
FREQUENCY (Hz)
OFF ISOLATION (dB)
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 11. Off Isolation vs. Frequency
110
60
70
80
90
100
100 10M1M100k10k1k
00024-012
FREQUENCY (Hz)
CROSSTALK (dB)
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 12. Crosstalk vs. Frequency
ADG411/ADG412/ADG413
Rev. C | Page 9 of 16
TERMINOLOGY
RON
Ohmic resistance between D and S.
IS (OFF)
Source leakage current with the switch OFF.
ID (OFF)
Drain leakage current with the switch OFF.
ID, IS (ON)
Channel leakage current with the switch ON.
VD (VS)
Analog voltage on terminals D, S.
CS (OFF)
OFF switch source capacitance.
CD (OFF)
OFF switch drain capacitance.
CD, CS (ON)
ON switch capacitance.
tON
Delay between applying the digital control input and the output
switching on.
tOFF
Delay between applying the digital control input and the output
switching off.
tD
OFF time or ON time measured between the 90% points of
both switches, when switching from one address state to
another.
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an OFF switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ADG411/ADG412/ADG413
Rev. C | Page 10 of 16
APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold
capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG411/ADG412/ADG413
minimizes this droop due to its low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 µV/µs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches are at the same potential, they have a differential effect
on the op amp AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the ±10 V
input range. Both the acquisition and settling times are 850 ns.
00024-013
+15V
–15V
2200pF
R
C
75
Ω
C
C
1000pF
C
H
2200pF
V
OUT
ADG411
ADG412
ADG413
SW2
SW1
S
S
D
D
+15V +5V
–15V
AD845
+15V
–15V
V
IN
AD711
Figure 13. Fast, Accurate Sample-and-Hold
ADG411/ADG412/ADG413
Rev. C | Page 11 of 16
TEST CIRCUITS
SD
V
S
R
ON
= V1/I
DS
I
DS
V1
00024-014
Figure 14. On Resistance
SD
V
S
V
D
I
S
(OFF) I
D
(OFF)
A A
00024-015
Figure 15. Off Leakage
SD
V
S
V
D
I
D
(ON)
A
00024-016
Figure 16. On Leakage
S
+15V +5V
0.1µF 0.1µF
V
DD
V
L
IN
V
S
GND V
SS
R
L
300Ω
C
L
35pF
V
OUT
0.1µF
–15V
t
ON
t
OFF
3V
50% 50%
50% 50%
3V
90% 90%
V
IN
V
IN
V
OUT
ADG411
ADG412
00024-017
D
Figure 17. Switching Times
S1 D1
+15V +5V
0.1µF 0.1µF
V
DD
V
L
IN1, IN2
V
S1
GND V
SS
R
L1
300Ω
C
L1
35pF
V
OUT1
0.1µF
–15V
V
S2
V
OUT2
R
L2
300Ω
C
L2
35pF
S2
V
IN
D2
t
D
t
D
3V
50% 50%
90%
V
IN
V
OUT1
V
OUT2
90%
90%
90%
0V
0V
0V
00024-018
Figure 18. Break-Before-Make Time Delay
ADG411/ADG412/ADG413
Rev. C | Page 12 of 16
+15V +5V
V
DD
V
L
IN
V
S
GND V
SS
C
L
10nF
V
OUT
–15V
R
S
3V
V
IN
V
OUT
∆
V
OUT
Q
INJ
= C
L
× ∆V
OUT
00024-019
SD
Figure 19. Charge Injection
+15V +5V
0.1µ
F 0.1
µ
F
V
DD
V
L
IN
V
S
GND V
SS
R
L
50
Ω
V
OUT
0.1
µ
F
–15V
V
IN
00024-020
SD
Figure 20. Off Isolation
S
+15V +5V
0.1µF 0.1µF
V
DD
V
L
V
S
GND V
SS
50Ω
NC
0.1µF
–15V
V
IN1
V
IN2
D
R
L
50Ω
V
OUT
CHANNEL-TO-CHANNEL
CROSSTALK = 20 ×LOG V
S
/V
OUT
00024-021
D
S
Figure 21. Channel-to-Channel Crosstalk
ADG411/ADG412/ADG413
Rev. C | Page 13 of 16
OUTLINE DIMENSIONS
16
18
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005
(0.13)
MIN
0.098 (2.49)
MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX 0.840 (21.34) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 22. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AC
16 9
8
1
4.00 (0.1575)
3.80 (0.1496)
10.00 (0.3937)
9.80 (0.3858)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8°
0°
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
× 45°
Figure 23. 16-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
16
18
9
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AC
Figure 25. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
ADG411/ADG412/ADG413
Rev. C | Page 14 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG411BN −40°C to +85°C P-DIP N-16
ADG411BR −40°C to +85°C SOIC R-16A
ADG411BR-REEL −40°C to +85°C SOIC R-16A
ADG411BR-REEL7 −40°C to +85°C SOIC R-16A
ADG411BRZ1−40°C to +85°C SOIC R-16A
ADG411BRZ-REEL1−40°C to +85°C SOIC R-16A
ADG411BRZ-REEL71−40°C to +85°C SOIC R-16A
ADG411BRU −40°C to +85°C TSSOP RU-16
ADG411BRU-REEL −40°C to +85°C TSSOP RU-16
ADG411BRU-REEL7 −40°C to +85°C TSSOP RU-16
ADG411BRUZ1−40°C to +85°C TSSOP RU-16
ADG411BRUZ-REEL1−40°C to +85°C TSSOP RU-16
ADG411BRUZ-REEL71−40°C to +85°C TSSOP RU-16
ADG411TQ −55°C to +125°C CERDIP Q-16
ADG411BCHIPS DIE
ADG412BN −40°C to +85°C P-DIP N-16
ADG412BR −40°C to +85°C SOIC R-16A
ADG412BR-REEL −40°C to +85°C SOIC R-16A
ADG412BR-REEL7 −40°C to +85°C SOIC R-16A
ADG412BRZ1−40°C to +85°C SOIC R-16A
ADG412BRZ-REEL1−40°C to +85°C SOIC R-16A
ADG412BRZ-REEL71−40°C to +85°C SOIC R-16A
ADG412BRU −40°C to +85°C TSSOP RU-16
ADG412BRU-REEL −40°C to +85°C TSSOP RU-16
ADG412BRU-REEL7 −40°C to +85°C TSSOP RU-16
ADG412BRUZ1−40°C to +85°C TSSOP RU-16
ADG412BRUZ-REEL1−40°C to +85°C TSSOP RU-16
ADG412BRUZ-REEL71−40°C to +85°C TSSOP RU-16
ADG412TQ −55°C to +125°C CERDIP Q-16
ADG412TCHIPS DIE
ADG413BN −40°C to +85°C P-DIP N-16
ADG413BR −40°C to +85°C SOIC R-16A
ADG413BR-REEL −40°C to +85°C SOIC R-16A
ADG413BRZ1−40°C to +85°C SOIC R-16A
ADG413BRZ-REEL1−40°C to +85°C SOIC R-16A
ADG413BRUZ1−40°C to +85°C TSSOP RU-16
ADG413BRUZ-500RL71−40°C to +85°C TSSOP RU-16
ADG413BRUZ-REEL1−40°C to +85°C TSSOP RU-16
ADG413BRUZ-REEL71−40°C to +85°C TSSOP RU-16
1 Z = Pb-free part.
ADG411/ADG412/ADG413
Rev. C | Page 15 of 16
NOTES
ADG411/ADG412/ADG413
Rev. C | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00024–0–11/04(C)
