M29W040-100NZ5TR - STMicroelectronics

AI02074

A0-A18

DQ0-DQ7

VCC

M29W040

VSS

Figure 1. LogicDiagram

M29W040

4 Mbit (512Kb x8, Uniform Block)

Low Voltage Single Supply Flash Memory

NOT FOR NEW DESIGN

M29W040 is replacedby the M29W040B

2.7Vto 3.6VSUPPLYVOLTAGE for

PROGRAM,ERASE and READ OPERATIONS

FASTACCESS TIME:100ns

BYTE PROGRAMMING TIME: 12µs typical

ERASETIME

– Block: 1.5 sec typical

– Chip: 2.5 sec typical

PROGRAM/ERASECONTROLLER(P/E.C.)

– ProgramByte-by-Byte

– Data Polling and Togglebits Protocolfor

P/E.C.Status

MEMORYERASE in BLOCKS

– 8 UniformBlocks of 64 KByteseach

– Block Protection

– MultiblockErase

ERASE SUSPENDand RESUME MODES

LOWPOWER CONSUMPTION

– Read mode: 8mAtypical (at 12MHz)

– Stand-by mode: 20µAtypical

– AutomaticStand-by mode

POWER DOWNSOFTWARE COMMAND

– Power-down mode: 1µAtypical

100,000PROGRAM/ERASECYCLES per

BLOCK

20YEARS DATARETENTION

– Defectivity below 1ppm/year

ELECTRONICSIGNATURE

– Manufacturer Code: 20h

– Device Code: E3h

A0-A18 Address Inputs

DQ0-DQ7 Data Input / Outputs

E Chip Enable

G Output Enable

W Write Enable

VCC Supply Voltage

VSS Ground

Table 1. Signal Names

PLCC32 (K) TSOP32 (N)

8 x 20mm

November 1999 1/31

This is informationon a product still in productionbut not recommendedfor new designs.

TSOP32 (NZ)

8 x 14mm

DQ0

A4 A3

A13

A10

DQ7

A14

A11 G

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A17

A16

A12

A18

VCC

A15

AI02076

M29W040

(Normal)

16 17

VSS

Figure 2B. TSOP Pin Connections

AI02075

A17

A13

A10

DQ5

DQ0

DQ1

DQ2

DQ3

DQ4

A16

DQ7

A12

A14

A18

VCC

M29W040

A15

A11

DQ6

VSS

Figure 2A. LCC Pin Connections

DQ0 A7

A4A3

A2 A6

A13

A10 A8

DQ7 A14

A11G

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6 A17

A16

A12

A18

VCC

A15

AI02077

M29W040

(Reverse)

16 17

VSS

Figure 2C. TSOP Reverse Pin Connections DESCRIPTION

The M29W040 is a non-volatile memory that may

be erased electrically at the block level, and pro-

grammed Byte-by-Byte.

The interface is directly compatible with most mi-

croprocessors. PLCC32,TSOP32(8 x 20mm)and

TSOP32(8 x 14mm)packagesare available.Both

normal and reverse pin outs are available for the

TSOP32(8 x 20mm) package.

Organisation

TheFlashMemoryorganisationis512Kx8bitswith

Address lines A0-A18 and Data Inputs/Outputs

DQ0-DQ7. Memory control is provided by Chip

Enable, Output Enable and Write Enable Inputs.

Erase and Program are performed through the

internal Program/Erase Controller (P/E.C.).

Data Outputs bitsDQ7 and DQ6 provide polling or

toggle signals during Automatic Program or Erase

to indicate the Ready/Busy state of the internal

Program/EraseController.

MemoryBlocks

Erasure of the memory is in blocks. There are 8

uniform blocks of 64 Kbytes each in the memory

address space. Each block can be programmed

and erased over 100,000 cycles. Each uniform

2/31

M29W040

Symbol Parameter Value Unit

TAAmbient Operating Temperature(3) –40 to 85 °C

TBIAS TemperatureUnder Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or OutputVoltages –0.6 to 5 V

VCC Supply Voltage –0.6 to 5 V

VA9 (2) A9 Voltage –0.6 to 13.5 V

Notes: 1. Except for therating ”Operating Temperature Range”, stresses above those listedin theTable ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other

conditions above those indicated in the Operating sections of this specificationis notimplied. Exposureto Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltagemay undershootto –2V during transition and for less than 20ns.

3. Depends on range.

Table2. AbsoluteMaximumRatings (1)

block may separately be protected and unpro-

tected against program and erase. Block erasure

may be suspended,while data is read from other

blocks of the memory, and then resumed.

Bus Operations

Seven operationscan be performed bythe appro-

priate bus cycles, Read Array, Read Electronic

Signature,OutputDisable,Standby,ProtectBlock,

Unprotect Block, and Write the Command of an

Instruction.

Command Interface

Command Bytes can be written to a Command

Interface(C.I.) latch to performReading (from the

Array or Electronic Signature), Erasure or Pro-

gramming. For added data protection, command

executionstarts after 4 or 6 commandcycles. The

first, second, fourth and fifth cycles are used to

input a code sequenceto the Command Interface

(C.I.). Thissequenceisequal for allP/E.C.instruc-

tions. Command itself and its confirmation - if it

applies - are given on the third and fourth or sixth

cycles.

Instructions

Eight instructions are defined to perform Reset,

Read Electronic Signature, Auto Program, Block

Auto Erase, Chip Auto Erase, Block Erase Sus-

pend, BlockErase Resumeand PowerDown. The

internalProgram/EraseController(P/E.C.)handles

all timingand verificationof theProgramandErase

instructionsandprovidesData Polling,Toggle,and

Statusdata toindicatecompletionof Programand

EraseOperations.

Instructionsare composed of up to six cycles.The

first twocyclesinput a codesequenceto theCom-

mand Interface which is common to all P/E.C.

instructions (see Table 7 for Command Descrip-

tions). The third cycle inputs the instructionset up

command instruction to the Command Interface.

SubsequentcyclesoutputSignature,BlockProtec-

tion or the addressed data for Read operations.

For addeddata protection,the instructionsfor pro-

gram,and blockor chiperase require furthercom-

mand inputs. For a Programinstruction,the fourth

command cycle inputs the address and data to be

programmed. For an Erase instruction (block or

chip),the fourthand fifthcyclesinputa furthercode

sequence before the Erase confirm command on

the sixth cycle. Byte programming takes typically

12µs while erase is performedin typically1.5 sec-

ond.

Erasureof a memory block maybe suspended,in

order to read data from another block, and then

resumed.Data Polling, Toggleand Errordata may

be read at any time,including during the program-

ming or erase cycles, to monitor the progress of

the operation.Whenpower is firstappliedor ifVCC

fallsbelowVLKO,thecommandinterfaceis resetto

ReadArray.

3/31

M29W040

Operation E G W DQ0 - DQ7

Read VIL VIL VIH Data Output

Write VIL VIH VIL Data Input

Output Disable VIL VIH VIH Hi-Z

Standby VIH X X Hi-Z

Note: X=V

IL or VIH

Table3. Operations

Code E G W A0 A1 A6 A9 Other

Addresses DQ0 - DQ7

Manufact. Code VIL VIL VIH VIL VIL VIL VID Don’t Care 20h

Device Code VIL VIL VIH VIH VIL VIL VID Don’t Care E3h

Table4. ElectronicSignature

Code E G W A0 A1 A6 A16 A17 A18 Other

Addresses DQ0 - DQ7

Protected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 01h

Unprotected Block VIL VIL VIH VIL VIH VIL SA SA SA Don’t Care 00h

Note: SA= Address of block being checked

Table5. BlockProtectionStatus

DEVICEOPERATION

Signal Descriptions

AddressInputs (A0-A18). Theaddress inputs for

thememory arrayarelatchedduring a writeopera-

tion. The A9 address input is used also for the

Electronic Signatureread and BlockProtect veri-

fication. When A9 is raised to VID, either a Read

Manufacturer Code, Read Device Code or Verify

BlockProtectionisenableddependingonthecom-

bination of levelson A0, A1 and A6. When A0, A1

and A6areLow,the ElectronicSignatureManufac-

turer codeis read,when A0is High and A1and A6

are Low,the Device code is read, and when A1 is

High and A0 and A6 are low, the BlockProtection

Status with protect/unprotectalgorithm is read for

the blockaddressed byA16, A17, A18.

Data Input/Outputs(DQ0-DQ7). Thedata inputis

a byteto be programmed or a commandwrittento

the C.I. Both are latched when Chip Enable E and

WriteEnableW areactive.The dataoutput isfrom

the memory Array, the Electronic Signature, the

Data Polling bit (DQ7), the Toggle Bit (DQ6), the

Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-

puts are valid when Chip Enable E and Output

EnableG are active.The outputis highimpedance

when the chip is deselected or the outputs are

disabled.

Chip Enable (E). The Chip Enable activates the

memory control logic, input buffers, decoders and

senseamplifiers.EHighdeselectsthememoryand

reduces the power consumption to the standby

level. E can also be used to control writing to the

command registerand to the memoryarray, while

W remains at a low level. Addresses are then

latchedon thefallingedgeofEwhiledataislatched

on the rising edge of E. The Chip Enable must be

forcedto VID during Block Unprotect operations.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. G must be forced to VID level during

BlockProtect and Block Unprotectoperations.

WriteEnable(W). Thisinputcontrolswritingto the

CommandRegisterandAddressandDatalatches.

Addressesare latchedonthefallingedgeofW,and

Data Inputs are latched on the rising edge of W.

VCC Supply Voltage. The power supply for all

operations(Read, Programand Erase).

VSS Ground. VSS is the reference for all voltage

measurements.

4/31

M29W040

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

RST (3,9) Read Array/

Reset

1+ Addr. (2,6) XRead Memory Array until a new write cycle is initiated.

Data F0h

3+ Addr. (2,6) 5555h 2AAAh 5555h Read MemoryArray until a new write

cycle isinitiated.

Data AAh 55h F0h

RSIG (3) Read

Electronic

Signature 3+ Addr. (2,6) 5555h 2AAAh 5555h Read Electronic Signature until a new

write cycle is initiated. See Note 4.

Data AAh 55h 90h

RBP (3) Read Block

Protection 3+ Addr. (2,6) 5555h 2AAAh 5555h Read Block Protection until a new write

cycle is initiated. See Note 5.

Data AAh 55h 90h

PG Program 4 Addr. (2,6) 5555h 2AAAh 5555h Program

Address Read Data Pollingor Toggle Bit

until Program completes.

Data AAh 55h A0h Program

Data

BE Block Erase 6 Addr. (2,6) 5555h 2AAAh 5555h 5555h 2AAAh Block

Address Additional

Block (7)

Data AAh 55h 80h AAh 55h 30h 30h

CE Chip Erase 6 Addr. (2,6) 5555h 2AAAh 5555h 5555h 2AAAh 5555h Note 8

Data AAh 55h 80h AAh 55h 10h

ES Erase

Suspend 1Addr. (2,6) XRead until Toggle stops, then read all the data needed from any

uniform block(s) not being erased then Resume Erase.

Data B0h

ER Erase

Resume 1Addr. (2,6) XRead Data Polling or Toggle Bit until Erase completes or Erase

is suspended another time

Data 30h

PD (10) Power

Down 1Addr. (2,6) 5555h Puts the memory in Power Down mode where power

consumption is reducedto typically less than 1µA

Data 20h

Notes: 1. Command not interpreted in this table will default to read array mode.

2. X = Don’tCare.

3. The first cycle of the RST,RBP or RSIG instruction is followedby read operations to read memory array,Status Register or

Electronic Signature codes. Any number of read cycles can occur after one command cycle.

4. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0at VIH andA1, A6 atVIL will output

Device code.

5. Protection Address: A0, A6 at VIL,A1atV

IH and A16,A17, A18within the uniform block to be checked, will outputthe

Block Protectionstatus.

6. Address bits A15-A18 are don’tcare forcoded address inputs.

7. Optional, additional blocks addresses must be entered within a 80µs delay afterlast write entry, timeout status can be verified

through DQ3 value. When full command is entered,read Data Polling or Toggle bit until Erase is completed or suspended.

8. Read Data Polling or Togglebit until Erase completes.

9. Await time of 5µs is necessary after a Reset command, if the memory is in a Block Erase or PowerDown status, before

starting any operation.

10. Writing an RST command to theP/E.C. is mandatory prior to any new operationwhen the memory is in Power Down mode.

Table6. Instructions (1)

5/31

M29W040

MemoryBlocks

The memoryblocks of the M29W040are shownin

Figure3. Thememoryarrayis dividedin 8 uniform

blocks of 64 Kbytes. Each block can be erased

separately or any combination of blocks can be

erased simultaneously.The BlockErase operation

is managedautomaticallyby theP/E.C.Theopera-

tion can be suspended in order to read from any

other block,and thenresumed.

Block Protectionprovides additionaldata security.

Each uniformblock can beseparatelyprotectedor

unprotectedagainstProgramorErase.BringingA9

and G to VID initiatesprotection,whilebringingA9,

G and E to VID cancels the protection. The block

affected during protection is addressed by the in-

puts on A16, A17, and A18. Unprotect operation

affectsall blocks.

Operations

Operations are defined as specific bus cycles and

signals which allow Memory Read, Command

Write,Output Disable, Standby,Read Status Bits,

Block Protect/Unprotect, Block Protection Check

and ElectronicSignatureRead. Theyare shownin

Tables3, 4, 5.

Read. Read operations are used to output the

contents of the Memory Array, the Status Register

or the Electronic Signature. Both Chip Enable E

and OutputEnable G must be low in order to read

the output of the memory. The Chip Enable input

alsoprovidespowercontroland shouldbe usedfor

deviceselection.OutputEnable shouldbe usedto

gatedataontotheoutputindependentofthedevice

selection.The data read dependson the previous

commandwritten to the memory (seeinstructions

RST and RSIG, and StatusBits).

Write.WriteoperationsareusedtogiveInstruction

Commandsto the memory or to latchinput datato

be programmed.Awriteoperationis initiatedwhen

Chip Enable E is Low and Write Enable W is Low

with OutputEnableG High. Addressesare latched

onthefallingedgeof WorEwhicheveroccurslast.

CommandsandInputDataarelatchedon therising

edge of W or E whicheveroccursfirst.

OutputDisable.Thedataoutputsare highimped-

ance when the OutputEnable G is High with Write

EnableW High.

Standby. The memory is in standby when Chip

Enable E is High and Program/Erase Controller

P/E.C. is Idle. The power consumptionis reduced

to the standby level and the outputs are high im-

pedance, independent of the Output Enable G or

WriteEnable W inputs.

Automatic Standby. After150ns of inactivity and

when CMOS levels are driving the addresses,the

chip automaticallyenters a pseudo standby mode

where consumption is reduced to the CMOS

standby value, while outputs are still driving the

bus.

Power Down. When the PD commandis written

to the P/E.C. the memory enters a power down

statuswhere the power consumptionis reducedto

ICC6 (typicallyless than 1.0µA).

Electronic Signature. Two codes identifying the

manufacturer andthedevicecanbe read fromthe

memory,themanufacturer’scodeforSTMicroelec-

tronics is 20h, and the device code is E3h for the

M29W040. These codes allow programming

equipment or applicationsto automatically match

theirinterfacetothecharacteristicsof theparticular

manufacturer’s product. TheElectronicSignature

is output by a Read operation when the voltage

applied to A9 is at VID and address inputs A1 and

A6 are at Low. The manufacturer code is output

when the Address input A0 is Low and the device

codewhen thisinputis High.OtherAddressinputs

are ignored. The codes are output on DQ0-DQ7.

This is shown in Table4.

The ElectronicSignature can alsobe read, without

raisingA9 to VID by givingthe memorythe instruc-

tion RSIG (see below).

6/31

M29W040

64K Bytes Block

AI01362B

7FFFFh

6FFFFh

5FFFFh

4FFFFh

3FFFFh

2FFFFh

1FFFFh

0FFFFh

TOP

ADDRESS

70000h

60000h

50000h

40000h

30000h

20000h

10000h

00000h

BOTTOM

ADDRESS

A18

1 64K Bytes Block

64K Bytes Block

A17

A16

001

000

Figure 3. MemoryMap and Block Address Table

Hex Code Command

10h Chip Erase Confirm

20h Power Down

30h Block Erase Resume/Confirm

50h Reserved

80h Set-up Erase

90h Read Electronic Signature/

Block Protection Status

A0h Program

B0h Erase Suspend

F0h Read Array/Reset

Table7. Commands

Block Protection. Each uniform block can be

separately protected against Program or Erase.

Block Protectionprovides additionaldata security,

as it disablesall programor eraseoperations.This

mode is activated when both A9 and G are set to

VID and the block address is applied on A16-A18.

Block Protection is programmed using a Presto F

programlikealgorithm.Protectionisinitiatedonthe

edgeofWfallingto VIL.Thenafteradelayof100µs,

the edge of W rising to VIH ends the protection

operation.Protectionverify is achievedbybringing

G, E andA6 to VIL while W is at VIH and A9 at VID.

Undertheseconditions,readingthedataoutputwill

yield 01h if the block defined by the inputs on

A16-A18 is protected. Any attempt to program or

erase a protected block will be ignored by the

device.

Any protected block can be unprotected to allow

updating of bit contents. All blocks must be pro-

tected before an unprotect operation. Block Un-

protect is activated when A9, G and E are at VID.

The addressesinputs A6, A12, A16 mustbe main-

tainedatVIH.BlockUnprotectisperformedthrough

a Presto F Erase like algorithm. Unprotect is initi-

ated by the edge of W falling to VIL. After a delay

of 10ms, the edge of W rising to VIH will end the

unprotection operation. Unprotect verify is

achieved by bringing G and E to VIL while A6 and

W are at VIH and A9 at VID. In these conditions,

reading the output data will yield 00h if the block

defined by the inputs on A16-A18 has been suc-

cessfullyunprotected.AllcombinationsofA16-A18

mustbeaddressedin orderto ensurethatallof the

8 uniform blocks have been unprotected. Block

ProtectionStatusis shownin Table 5.

7/31

M29W040

Instructions and Commands

The Command Interface (C.I.) latches commands

written to the memory. Instructions are made up

from one or more commands to perform Read

Array/Reset, Read Electronic Signature, Power

Down, Block Erase, Chip Erase, Program, Block

Erase Suspend and Erase Resume. Commands

are made of address and data sequences. Ad-

dresses are latched on the falling edge of W or E

and data is latched on the rising of W or E. The

instructionsrequire from 1 to 6 cycles, the first or

first three of which are always write operations

used to initiatethecommand.Theyarefollowed by

either furtherwrite cyclesto confirmthe first com-

mand orexecutethe commandimmediately. Com-

mand sequencing must be followed exactly. Any

invalid combination of commands will reset the

device to Read Array. The increased number of

cycles has been chosen to assure maximum data

security.Commands are initialised by two preced-

ingcodedcycleswhichunlocktheCommandInter-

face.In addition,for Erase,command confirmation

is againpreceededby the two coded cycles.

P/E.C. statusis indicatedduring commandexecu-

tionby DataPollingonDQ7,detectionofToggleon

DQ Name Logic Level Definition Note

7Data

Polling

’1’ Erase Complete Indicates the P/E.C. status, check during

Program or Erase, and on completion

before checking bits DQ5 for Program or

Erase Success.

’0’ Erase on going

DQ Program Complete

DQ Program on going

6 Toggle Bit

’-1-0-1-0-1-0-1-’ Erase or Program ongoing Successive read output complementary

data on DQ6 while Programming or Erase

operations are going on.DQ6 remain at

constant level when P/E.C. operations are

completed or Erase Suspend is

acknowledged.

’-0-0-0-0-0-0-0-’ Program (’0’ on DQ6)

Complete

’-1-1-1-1-1-1-1-’ Erase or Program

(’1’ on DQ6) Complete

5 Error Bit ’1’ Program or Erase Error This bit is set to ’1’if P/E.C. has exceded

the specified time limits.

’0’ Program or Erase on going

4’1’

’0’

3Erase

TimeBit

’1’ Erase TimeoutPeriod Expired P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES). An additional block to be erased in

parallel can be entered to the P/E.C.

’0’ Erase Timeout Period on

going

2 Reserved

1 Reserved

0 Reserved

Note: Logic level ’1’ isHigh, ’0’ is Low.-0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

Table8. StatusRegister

DQ6, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mandexecutionwillautomaticallyoutputthosefour

bits.TheP/E.C. automaticallysetsbitsDQ3,DQ5,

DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and

DQ4) are reserved for future use and should be

masked.

Data Polling bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

DuringErase operation,it outputsa ’0’. After com-

pletionof the operation,DQ7 willoutput thebit last

programmed or a ’1’ after erasing. Data Polling is

valid only effectiveduringP/E.C. operation,that is

after the fourth W pulse for programming or after

the sixth W pulse for Erase. It must be performed

at theaddressbeingprogrammedor at anaddress

within the block being erased. If the byte to be

programmedbelongstoaprotectedblockthecom-

mand is ignored. If all the blocks selected for era-

sure are protected, DQ7 will set to ’0’ for about

100µs, and then return to previous addressed

memory data. See Figure 9 for the Data Polling

flowchart and Figure 10 for the Data Polling wave-

forms.

8/31

M29W040

AI01417

1.5V

Figure 4. AC TestingInputOutput Waveform

AI01968

0.8V

OUT

CL= 30pF or 100pF

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Figure 5. AC TestingLoad Circuit

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6 pF

OUT Output Capacitance VOUT =0V 12 pF

Note: 1. Sampled only,not 100% tested.

Table10. Capacitance(1) (TA=25°C, f =1 MHz)

Input Rise and Fall Times ≤10ns

Input Pulse Voltages 0 to3V

Input and Output Timing Ref. Voltages 1.5V

Table9. AC MeasurementConditions

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC1 Supply Current (Read) E = VIL,G=V

IH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 0.2 mA

ICC3 Supply Current (Standby) CMOS E = VCC ±0.2V 50 µA

ICC4 Supply Current (Program or Erase) Byte Program,

Block Erase 20 mA

ICC5 Supply Current Chip Erase in progress 40 mA

ICC6 Power Down Current E = VCC ±0.2V 5 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage IOL = 2mA 0.45 V

VOH Output High Voltage CMOS IOH = –100µAV

CC –0.4 V

IOH = –2.0mA 0.85 VCC V

VID A9 Voltage(Electronic Signature) 11.5 12.5 V

IID A9 Current (Electronic Signature) A9 = VID 50 µA

VLKO Supply Voltage (Erase and

Program lock-out) 1.9 2.2 V

Table11. DC Characteristics

(TA=0 to 70°C, –20 to 85°C or –40 to85°C; VCC = 2.7Vto 3.6V)

9/31

M29W040

Symbol Alt Parameter Test Condition

M29W040

Unit

-100 -120

VCC = 3.3V±0.3V

CL= 30pF VCC = 3.3V±0.3V

Min Max Min Max

tAVAV tRC Address Validto Next Address Valid E = VIL,G=V

IL 100 120 ns

tAVQV tACC Address Valid to Output Valid E = VIL,G=V

IL 100 120 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 00ns

ELQV (2) tCE Chip Enable Low to Output Valid G = VIL 100 120 ns

tGLQX (1) tOLZ Output Enable Low to Output

Transition E=V

IL 00ns

GLQV (2) tOE Output Enable Low to Output Valid E = VIL 40 50 ns

tEHQX tOH Chip Enable High to Output

Transition G=V

IL 00ns

EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 20 30 ns

tGHQX tOH Output Enable High to Output

Transition E=V

IL 00ns

GHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 20 30 ns

tAXQX tOH Address Transition to Output

Transition E=V

IL,G=V

IL 00ns

Notes: 1. Sampled only,not 100% tested.

2. G may be delayed by up to tELQV -t

GLQV afterthe falling edge of E without increasing tELQV.

Table12A. Read AC Characteristics

(TA=0 to 70°C, –20 to 85°C or –40 to85°C)

Toggle bit (DQ6). When Programming operations

are in progress, successive attempts to read DQ6

will output complementary data. DQ6 will toggle

following toggling of either G or E when G is low.

The operation is completed when two successive

reads yield the same output data. The next read

will output the bit last programmed or a ’1’ after

erasing. Thetogglebitis validonlyeffectiveduring

P/E.C. operations, that is after the fourth W pulse

for programming or after the sixth W pulse for

Erase. If the byte to be programmedbelongs to a

protectedblockthe commandwillbeignored.If the

blocksselectedforerasureareprotected,DQ6will

toggle for about 100µs and then return back to

Read. See Figure 11 for Toggle Bit flowchart and

Figure 12 for ToggleBit waveforms.

Error bit (DQ5). This bit is set to ’1’ by the P/E.C

when there is a failure ofbyte programming, block

erase, or chip erase that results in invalid data

being programmedin thememoryblock.In caseof

error in block erase or byte program, the block in

which the error occured or to which the pro-

grammed byte belongs,must be discarded. Other

blocksmaystill beused.Errorbitresetsafter Reset

(RST) instruction. In case of success,the error bit

will set to ’0’ during Program or Erase and to valid

data afterwrite operation is completed.

Erase Timer bit (DQ3). Thisbit is set to ’0’ by the

P/E.C. when the last Block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 80 to 120µs, DQ3 returns

backto ’1’.

Coded Cycles. The two coded cycles unlock the

Command Interface.They are followed by a com-

mand input or a comand confirmation. The coded

cycles consist of writing the data AAh at address

5555hduringthefirstcycleanddata55hataddress

2AAAh during the second cycle. Addresses are

latched on the falling edge of W or E while data is

latched on the rising edge of W or E. The coded

cycles happen on first and second cycles of the

commandwrite or on the fourth and fifth cycles.

10/31

M29W040

Symbol Alt Parameter Test Condition

M29W040

Unit

-150 -200

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V

Min Max Min Max

tAVAV tRC Address Valid to Next Address

Valid E=V

IL,G=V

IL 150 200 ns

tAVQV tACC Address Valid to Output Valid E = VIL,G=V

IL 150 200 ns

tELQX (1) tLZ Chip Enable Low to Output

Transition G=V

IL 00ns

ELQV (2) tCE Chip Enable Low to Output Valid G = VIL 150 200 ns

tGLQX (1) tOLZ Output Enable Low to Output

Transition E=V

IL 00ns

GLQV (2) tOE Output Enable Low to Output

Valid E=V

IL 55 70 ns

tEHQX tOH Chip Enable High to Output

Transition G=V

IL 00ns

EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 40 50 ns

tGHQX tOH Output Enable High to Output

Transition E=V

IL 00ns

GHQZ (1) tDF Output Enable High to Output

Hi-Z E=V

IL 40 50 ns

tAXQX tOH Address Transition to Output

Transition E=V

IL,G=V

IL 00ns

Notes: 1. Sampled only,not 100% tested.

2. G may be delayed by up to tELQV -t

GLQV afterthe falling edge of E without increasing tELQV.

Table12B. Read AC Characteristics

(TA=0 to 70°C, –20 to 85°C or –40 to85°C)

Read Array/Reset(RST) instruction. The Reset

instruction consists of one write operation giving

the command F0h. It can be optionally preceded

by thetwo coded cycles.Await stateof5µs before

readoperationsisnecessaryif theResetcommand

is appliedduring an Erase or PowerDown opera-

tion.

Read Electronic Signature (RSIG) instruction.

Thisinstructionusesthetwocodedcyclesfollowed

by one write cycle giving the command 90h to

address5555h for commandsetup. Asubsequent

read will output the manufacturercode, the device

code or the Block Protection status depending on

the levels of A0, A1, A6, A16, A17 and A18. The

manufacturer code, 20h, is output when the ad-

dresses lines A0, A1 and A6 are Low, the device

code, E2h is output when A0 is High with A1 and

A6 Low.

Read Block Protection (RBP) instruction. The

useofReadElectronicSignature(RSIG)command

also allows access to the Block Protection status

verify. After givingthe RSIGcommand, A0 and A6

are set to VIL with A1 at VIH, while A16, A17 and

A18 define the block of the block to be verified. A

read in theseconditions willoutput a 01hif blockis

protectedand a 00h if blockis not protected.

ThisRead BlockProtectionis the onlyvalid way to

check the protection status of a block. Neverthe-

less,it mustnot beusedduringthe blockprotection

phase as a method to verify the Block Protection.

Please refer to Block Protectionparagraph.

PowerDown (PD)instruction. ThePower Down

instructionuses one write cycle to put thememory

into a power down mode where currentconsump-

tion is typically reduced to less than 1.0µA. Once

in this state, a Reset (RST) command must be

written to the P/E.C. prior to any operation.

11/31

M29W040

AI01363B

tAVAV

tAVQV tAXQX

tELQX

tEHQZ

tGLQV

tGLQX

tGHQX

VALID

A0-A18

DQ0-DQ7

tELQV

VALID

ADDRESS VALID

AND CHIP ENABLE OUTPUT ENABLE DATA VALID

tEHQX

tGHQZ

Figure 6. ReadMode AC Waveforms

Note: Write Enable (W) = High

12/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-100 -120

VCC = 3.3V±0.3V

CL= 30pF VCC = 3.3V±0.3V

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 100 120 ns

tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High 45 50 ns

tDVWH tDS Input Validto Write Enable High 45 50 ns

tWHDX tDH Write Enable High to Input Transition 0 0 ns

tWHEH tCH WriteEnable High to Chip Enable High 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 25 30 ns

tAVWL tAS Address Valid to Write Enable Low 0 0 ns

tWLAX tAH WriteEnable Low to Address Transition 45 50 ns

tGHWL Output Enable High to Write Enable Low 0 0 ns

tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs

tWHQV1 (1) Write Enable High to Output Valid (Program) 12 12 µs

tWHQV2 (1) Write Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns

Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =t

WHQ7V +t

Q7VQV.

Table 13A. Write AC Characteristics,WriteEnable Controlled

(TA=0 to 70°C, –20 to 85°C or –40 to85°C)

ChipErase(CE)instruction.Thisinstructionuses

six write cycles. The Erase Set-up command 80h

is written to address5555h on thirdcycleafter the

two coded cycles. The Chip Erase Confirm com-

mand10hiswrittenataddress5555honsixthcycle

after anothertwo coded cycles. If the secondcom-

mand given is not an eraseconfirm or if thecoded

cycles are wrong, the instruction aborts and the

deviceisreset to ReadArray.It isnot necessaryto

program the array with 00h first as the P/E.C. will

automaticallydo this before erasing to FFh. Read

operations after the sixth rising edge of W or E

output the status register bits. During the execu-

tion of the erase by the P/E.C.the memorywill not

acceptany instruction.

Readof DataPolling bit DQ7returns’0’, then’1’on

completion. The Toggle Bit DQ6 toggles during

erase operation and stops when erase is com-

pleted. After completion the Status Register bit

DQ5 returns ’1’ if there has been an Erase Failure

because the erasure has not been verified even

after the maximum number of erase cycles have

been executed.

13/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-150 -200

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V

Min Max Min Max

tAVAV tWC Address Validto Next Address Valid 150 200 ns

tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High 65 80 ns

tDVWH tDS Input Validto Write Enable High 65 80 ns

tWHDX tDH Write Enable High to Input Transition 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 35 35 ns

tAVWL tAS Address Validto WriteEnable Low 0 0 ns

tWLAX tAH Write Enable Low to Address Transition 65 65 ns

tGHWL Output Enable High to Write Enable Low 0 0 ns

tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs

tWHQV1 (1) Write Enable High to Output Valid(Program) 12 12 µs

tWHQV2 (1) Write Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns

Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =t

WHQ7V +t

Q7VQV.

Table13B. Write AC Characteristics,Write Enable Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Block Erase (BE) instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 5555h

onthirdcycleafterthetwocodedcycles.The Block

Erase Confirm command 30h is written on sixth

cycle after another two coded cycles. During the

input of the second command an address within

theblockto be erasedis givenandlatchedintothe

memory. Additional Block Erase confirm com-

mands and block addresses can be written sub-

sequentlyto erase other blocks in parallel,without

further coded cycles. The erase will start after the

Erase timeout period (see Erase Timer Bit DQ3

description). Thus, additional Block Erase com-

mandsmustbe givenwithinthisdelay.Theinputof

a newBlockErasecommandwillrestartthetimeout

period. The status of the internal timer can be

monitoredthroughthe levelofDQ3, ifDQ3is’0’the

Block Erase Command has been given and the

timeout is running, if DQ3 is ’1’, the timeout has

expired and the P/E.Cis erasingthe block(s).

DuringErasetimeout,anycommanddifferentfrom

30h will abortthe instruction and reset the device

to readarraymode. Itis notnecessaryto program

the block with 00h as the P/E.C. will do this auto-

matically before erasing to FFh. Read operations

after the sixth rising edge of W or E output the

statusregister bits.

DuringtheexecutionoftheerasebytheP/E.C.,the

memoryaccepts onlythe ES(EraseSuspend)and

RST (Reset) instructions. Data Polling bit DQ7

returns’0’ while the erasure is in progress and ’1’

whenit hascompleted.The ToggleBitDQ6toggles

during the erase operation. It stops when erase is

completed. After completion the Status Register

bit DQ5 returns ’1’ if there has been an Erase

Failure becauseerasure has not completedeven

after the maximum number of erase cycles have

beenexecuted. In this case,it will be necessaryto

input a Reset (RST) to the command interface in

order to reset the P/E.C.

14/31

M29W040

AI01365B

A0-A18

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

WRITE CYCLE

tDVWH

tWLWHtGHWL

Figure 7. WriteAC Waveforms, W Controlled

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

Program (PG) instruction. The memory can be

programmed Byte-by-Byte. This instruction uses

four write cycles. The Program command A0h is

written on the thirdcycle after two codedcycles. A

fourth write operation latches the Address on the

falling edge of W or E and the Data to be written

on its rising edge and startsthe P/E.C. During the

execution of the programby the P/E.C., the mem-

ory willnot acceptanyinstruction.Readoperations

output the status bits after the programming has

started. The status bits DQ5,DQ6 andDQ7 allow

a checkofthestatusoftheprogrammingoperation.

Memoryprogrammingis madeonly by writing’0’in

place of ’1’ in a Byte.

Erase Suspend (ES) instruction. The Block

Eraseoperationmaybe suspended bythisinstruc-

tion which consists of writing the command B0h

withoutanyspecificaddresscode.Nocodedcycles

are required.Itallowsreadingof datafromanother

block while erase is in progress. Erasesuspend is

accepted only during the Block Erase instruction

executionand defaultsto readarraymode. Writing

thiscommandduringErasetimeoutwill,inaddition

to suspending the erase, terminate the timeout.

TheToggleBitDQ6stopstogglingwhentheP/E.C.

issuspended. ToggleBitstatusmustbemonitored

at anaddressout oftheblockbeingerased.Toggle

Bit will stop togglingbetween 0.1µs and 15µs after

the Erase Suspend(ES) command has been writ-

ten.

The M29W040 will then automaticallyset to Read

Memory Array mode. When erase is suspended,

Read from blocks being erased will output invalid

data, Read from block not being erased is valid.

During the suspension the memory will respond

only to Erase Resume (ER) and Reset (RST) in-

structions. RST command will definitively abort

erasure and result in the invalid data in the blocks

being erased.

EraseResume(ER)instruction. IfanEraseSus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

codedcycles.

15/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-100 -120

VCC = 3.3V±0.3V

CL= 30pF VCC = 3.3V±0.3V

Min Max Min Max

tAVAV tWC Address Validto Next Address Valid 100 120 ns

tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High 45 50 ns

tDVEH tDS Input Validto Chip Enable High 45 50 ns

tEHDX tDH Chip Enable High to Input Transition 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low 25 30 ns

tAVEL tAS Address Validto ChipEnable Low 0 0 ns

tELAX tAH Chip Enable Low to Address Transition 45 50 ns

tGHEL Output Enable High Chip Enable Low 0 0 ns

tVCHWL tVCS VCC Highto WriteEnable Low 50 50 µs

tEHQV1 (1) Chip Enable High to Output Valid(Program) 12 12 µs

tEHQV2 (1) Chip Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns

Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =t

WHQ7V +t

Q7VQV.

Table 14A. Write AC Characteristics,Chip Enable Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

PowerUp

ThememoryCommandInterfaceis resetonpower

up to ReadArray. EitherEor W must be tiedto VIH

during Power-up to allow maximum security and

the possibilityto writea commandonthe firstrising

adge ofE or W. Anywritecycleinitiationis blocked

when VCC is belowVLKO.

Supply Rails

Normal precautionsmust be taken for supplyvolt-

age decoupling, each device in a system should

havetheVCC rail decoupledwith a1.0µF capacitor

close to the VCC and VSS pins. The PCB trace

widths should be sufficient to carry the VCC pro-

gramand erasecurrents required.

16/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-150 -200

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 150 200 ns

tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High 65 80 ns

tDVEH tDS Input Valid to Chip Enable High 65 80 ns

tEHDX tDH Chip Enable High to Input Transition 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low 35 35 ns

tAVEL tAS Address Valid to Chip Enable Low 0 0 ns

tELAX tAH Chip Enable Low to Address Transition 65 65 ns

tGHEL Output Enable High Chip Enable Low 0 0 ns

tVCHWL tVCS VCC High to Write Enable Low 50 50 µs

tEHQV1 (1) Chip Enable High to Output Valid (Program) 12 12 µs

tEHQV2 (1) Chip Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns

Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =t

WHQ7V +t

Q7VQV.

Table 14B. Write AC Characteristics,Chip EnableControlled

(TA=0 to 70°C, –20 to 85°C or –40 to 85°C)

17/31

M29W040

AI01366B

A0-A18

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

WRITE CYCLE

tDVEH

tELEHtGHEL

Figure 8. WriteAC Waveforms, E Controlled

Note: Address are latched on thefalling edgeof E, Data is latched on the rising edge of E.

18/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-100 -120

VCC = 3.3V±0.3V

CL= 30pF VCC = 3.3V±0.3V

Min Max Min Max

tWHQ7V1 (2) Write Enable Highto DQ7Valid

(Program, W Controlled) 12 12 µs

tWHQ7V2 (2) Write Enable Highto DQ7Valid

(Block Erase, W Controlled) 1.5 30 1.5 30 sec

tEHQ7V1 (2) Chip Enable High to DQ7 Valid

(Program, E Controlled) 12 12 µs

tEHQ7V2 (2) Chip Enable High to DQ7 Valid

(Block Erase, E Controlled) 1.5 30 1.5 30 sec

tQ7VQV Q7 Validto Output Valid(Data Polling) 45 50 ns

tWHQV1 Write Enable Highto Output Valid

(Program) 12 12 µs

tWHQV2 Write Enable Highto Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tEHQV1 Chip Enable High to Output Valid

(Program) 12 12 µs

tEHQV2 Chip Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

Notes: 1. All other timings are defined in Read AC Characteristics table.

2. tWHQ7V is the Program or Erase time.

Table15A. Data Pollingand Toggle Bit ACCharacteristics(1)

(TA=0 to 70°C, –20 to 85°C or –40 to 85°C)

19/31

M29W040

Symbol Alt Parameter

M29W040

Unit

-150 -200

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V

Min Max Min Max

tWHQ7V1 (2) Write Enable High to DQ7 Valid

(Program, W Controlled) 12 12 µs

tWHQ7V2 (2) Write Enable High to DQ7 Valid

(Block Erase, W Controlled) 1.5 30 1.5 30 sec

tEHQ7V1 (2) Chip EnableHigh to DQ7 Valid

(Program, E Controlled) 12 12 µs

tEHQ7V2 (2) Chip EnableHigh to DQ7 Valid

(Block Erase, E Controlled) 1.5 30 1.5 30 sec

tQ7VQV Q7 Validto Output Valid(Data Polling) 55 70 ns

tWHQV1 Write Enable High to Output Valid

(Program) 12 12 µs

tWHQV2 Write Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

tEHQV1 Chip Enable High to Output Valid

(Program) 12 12 µs

tEHQV2 Chip Enable High to Output Valid

(Block Erase) 1.5 30 1.5 30 sec

Notes: 1. All other timingsare defined in Read AC Characteristics table.

2. tWHQ7V is the Program or Erase time.

Table 15B. Data Polling and Toggle Bit AC Characteristics(1)

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

20/31

M29W040

AI01364B

A0-A18

DQ7

IGNORE

VALID

DQ0-DQ6

BYTE ADDRESS (WITHIN BLOCKS)

DATA OUTPUT VALID

tAVQV

tEHQ7V

tGLQV

tWHQ7V

VALID

tQ7VQV

DQ7

DATA POLLING (LAST) CYCLE DATA VERIFY

READ CYCLE

DATA POLLING

READ CYCLES

LAST CYCLE

OF PROGRAM

OR ERASE

tELQV

Figure 9. DataPollingDQ7 AC Waveforms

Notes: 1. All other timings are as a normal Read cycle.

2. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.

3. tWHQ7V is the Programor Erase time.

4. During erasing operation Byte address must be within Block being erased.

21/31

M29W040

READ DQ5 &

DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369

DQ7

DATA YES

YES

DQ5

DQ7

DATA YES

Figure 10. DataPolling Flowchart

READ

DQ5 & DQ6

START

READ DQ6

FAIL PASS

AI01370

DQ6

TOGGLE NO

YES

DQ5

YES

DQ6

TOGGLE

Figure 11. Data Toggle Flowchart

Parameter M29W040 Unit

Min Typ Max

Chip Program (Byte) 6 sec

Chip Erase (Preprogrammed) 2.5 30 sec

Chip Erase 8.5 sec

Block Erase (Preprogrammed) 1.5 30 sec

Block Erase 2 sec

Byte Program 12 2200 µs

Program/Erase Cycles (per Block) 100,000 cycles

Table 16. Program,Erase Times and Program,Erase Endurance Cycles

(TA= 0 to 70°C; VCC = 2.7V to 3.6V)

22/31

M29W040

AI01367

A0-A18

DQ6

DQ0-DQ5,

tAVQV

STOP TOGGLE

LAST CYCLE

OF PROGRAM

OF ERASE

VALID

VALIDIGNORE

DQ7

DATA TOGGLE

READ CYCLE READ CYCLE

tWHQV

tEHQV

tELQV

tGLQV

DATA

TOGGLE

READ CYCLE

Figure 12. DataToggle DQ6 AC Waveforms

Note: All other timings are as a normal Read cycle.

23/31

M29W040

BLOCK ADDRESS

on A16, A17, A18

AI01368D

G, A9 = VID,

E=V

n=0

Wait 4µs

Wait 100µs

W=V

G=V

READ DQ0 at PROTECTION

ADDRESS: A0, A6 = VIL,A1=V

and

A16, A17, A18 DEFINING BLOCK

A9 = VIH

++n

=25

START

FAIL

PASS YES

DQ0

YES

A9 = VIH

Wait 4µs

Figure 13. BlockProtection Flowchart

24/31

M29W040

PROTECT

ALL BLOCKS

AI01371E

A6, A12, A16 = VIH

E, G, A9 = VIH

DATA

E, G, A9 = VID

Wait 4µs

W=V

E, G = VIH

READ at UNPROTECTION

ADDRESS: A1, A6 = VIH,A0=V

and

A16, A17, A18 DEFINING BLOCK

(see Note 1)

Wait 10ms

Wait 4µs

00h

INCREMENT

BLOCK

n=0

Wait 4µs

W=V

++n

= 1000

START

FAIL

YES

YESNO

PASS

NO LAST

SECT.

YES

Figure 14. BlockUnprotecting Flowchart

Note: 1. A6 is kept atVIH during unprotection algorithm in order tosecure best unprotectionverification. During all otherprotection status

reads, A6 must be kept at VIL.

25/31

M29W040

ORDERINGINFORMATION SCHEME

Note: 1. This speed is obtainedwith a supply voltage range of VCC = 3.3V

±0.3Vand a loadcapacitance at 30pF.

M29W040 is replaced by the new version M29W040B

Device are shipped from the factory with the memory content erased (to FFh).

Fora listofavailableoptions(Speed,Package,etc...)orfor furtherinformationonanyaspect of thisdevice,

please contactthe STMicroelectronics Sales Office nearest to you.

Operating Voltage

W 2.7V to 3.6V

Speed

-100 (1) 100ns

-120 120ns

-150 150ns

-200 200ns

Package

K PLCC32

N TSOP32

8 x 20mm

NZ TSOP32

8 x 14mm

Temp. Range

1 0 to 70 °C

5 –20 to 85 °C

6 –40 to 85 °C

Option

R Reverse

Pinout

TR Tape & Reel

Packing

Example: M29W040 -120 N 1 TR

26/31

M29W040

PLCC

Ne E1 E

D2/E2 e

0.51 (.020)

1.14 (.045)

Symb mm inches

Typ Min Max Typ Min Max

A 2.54 3.56 0.100 0.140

A1 1.52 2.41 0.060 0.095

A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495

D1 11.35 11.56 0.447 0.455

D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595

E1 13.89 14.10 0.547 0.555

E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N32 32

Nd 7 7

Ne 9 9

CP 0.10 0.004

Drawing is not to scale.

PLCC32 - 32 lead Plastic Leaded Chip Carrier,rectangular

27/31

M29W040

TSOP-a

N/2

DIE

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.007

A2 0.95 1.05 0.037 0.041

B 0.15 0.27 0.006 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N32 32

CP 0.10 0.004

Drawing is not to scale.

TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm

28/31

M29W040

TSOP-b

N/2

DIE

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.17 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.15 0.27 0.006 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 – – 0.020 – –

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N32 32

CP 0.10 0.004

Drawing is not to scale.

TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm

29/31

M29W040

TSOP-a

N/2

DIE

LA1 α

Drawing is not to scale.

TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm

Symb mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 13.80 14.20 0.543 0.559

D1 12.30 12.50 0.484 0.492

E 7.90 8.10 0.311 0.319

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N32 32

CP 0.10 0.004

30/31

M29W040

Information furnished is believed to be accurate and reliable. However,STMicroelectronics assumes no responsibility for the consequences

of use ofsuch informationnor forany infringementof patentsor other rights of thirdparties which may result from itsuse. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

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