CLRC66302HN,157 - NXP Semiconductors

1. General description

CLRC663, the high performance multi-protocol NFC frontend.

The CLRC663 multi-protocol NFC frontend IC supports the following operating modes

•Read/write mode supporting ISO/IEC 14443A/MIFARE

•Read/write mode supporting ISO/IEC 14443B

•Read/write mode supporting JIS X 6319-4 (comparable with FeliCa1 (see

Section 20.5) scheme)

•Passive initiator mode according to ISO/IEC 18092

•Read/write mode supporting ISO/IEC 15693

•Read/write mode supporting ICODE EPC UID/ EPC OTP

•Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

The CLRC663’s internal transmitter is able to drive a reader/writer antenna designed to

communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional

active circuitry. The digital module manages the complete ISO/IEC 14443A framing and

error detection functionality (parity and CRC).

The CLRC663 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,

MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The CLRC663

supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.

The CLRC663 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer

communication scheme except anticollision. The anticollision needs to be implemented in

the firmware of th e ho st co nt ro ller as well as in th e uppe r lay er s.

The CLRC663 is able to demodulate and decode FeliCa coded signals.The FeliCa

receiver part provides the demodulation and decoding circuitry for FeliCa coded signals.

The CLRC663 handles the FeliCa framing and error detection such as CRC. The

CLRC663 supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.

The CLRC663 is supporting the P2P passive initiator mode in accordance with

ISO/IEC 18092.

The CLRC663 supp o rts the vicinity prot oco l acc ordin g to ISO/I EC1 56 9 3, EPC UID and

ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.

The following host interfaces are supported:

CLRC663

High performance NFC reader solution

Rev. 4.0 — 29 October 2015

171140 Product data sheet

COMPANY PUBLIC

1. In the following the word FeliCa is used for JIS X 6319-4

Product data sheet

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171140 2 of 136

NXP Semiconductors CLRC663

High performance NFC reader solution

•Serial Peripheral Interface (SPI)

•Serial UART (s imilar to RS232 with voltage levels dependent on pin voltage supply)

•I2C-bus interface (two versions are implemented: I2C and I2CL)

The CLRC663 supports the connection of a secure access module (SAM). A dedicated

separate I2C interface is imple mented for a connection of the SAM. The SAM can be used

for high secure key storage and acts as a very performant crypto coprocessor. A

dedicated SAM is available for connection to the CLRC663.

2. Features and benefits

Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE

Crypto 1 intellectual property licensing rights

High performance multi-protocol NFC fronten d for transfer speed up to 848 kbit/s

Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B and FeliCa

P2P passive initiator mode in accor dance with ISO/IEC 18092

Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC

Class-1 HF

Supports MIFARE Classic encryption by hardware in read/write mode

Allows to read MIFARE Ultralight, MIFARE Classic 1K, MIFARE Classic 4K, MIFARE

DESFire EV1, MIFARE DESfireEV2 and MIFARE Plus cards

Low-Power Card Detection

Compliance to “EMV con tactless prot ocol specificatio n V2.3. 1 ” on RF lev el can be

achieved

Antenna connection with minimum number of external components

Supported host interfaces:

SPI up to 10 Mbit/s

I2C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus

RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin

voltage supply

Separate I2C-bus interface for connection of a secure access module (SAM)

FIFO buffer with size of 512 byte for highest transaction performance

Flexible and efficient power saving modes including hard power down, standby and

low-power card detection

Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz

crystal

3 V to 5.5 V power su pp ly

Up to 8 free programmable input/output pins

Typical operating distance in read/write mode for communication to a

ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and

tuning

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

3. Quick reference data

[1] VDD(PVDD) must always be the same or lower voltage than VDD.

[2] Ipd is the sum of all supply currents

[3] IDD(TVDD) depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2.

[4] Typical value: Assumes the usage of a complementary driver configuration and an antenna matched to 40  between pins TX1, TX2 at

13.56 MHz.

4. Ordering information

[1] Delivered in one tray

[2] Delivered in five trays

[3] Delivered on reel with 6000 pieces

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 5 5.5 V

VDD(PVDD) PVDD supply voltage [1] 35V

DD V

VDD(TVDD) TVDD supply voltage 3 5 5.5 V

Ipd power-down current PDOWN pin pulled HIGH [2] - 8 40 nA

IDD supply current - 17 20 mA

IDD(TVDD) TVDD supply current [3][4] - 100 250 mA

Tamb ambient temperature 25 +25 +85 C

Tstg storage temperature no supply voltage applied 40 +25 +100 C

Table 2. Orderi ng informatio n

Type number Package

Name Description Version

CLRC66301HN/TRAYB[1] HVQFN32 plastic thermal enhanced very thin quad flat package; no

leads; MSL2, 32 terminals + 1 central ground; body 5  5

 0.85 mm

SOT617-1

CLRC66301HN/TRAYM[2]

CLRC66302HN/TRAYB[1] plastic thermal enhanced very thin quad flat package; no

leads; MSL1, 32 terminals + 1 central ground; body 5  5

 0.85 mm

SOT617-1

CLRC66302HN/TRAYBM[2]

CLRC66302HN/T/R[3]

Product data sheet

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171140 4 of 136

NXP Semiconductors CLRC663

High performance NFC reader solution

5. Block diagram

The analog interface ha ndles the modulation an d demodulation of the antenna signals for

the contactless interface.

The contactless UART manages the protocol dependency of the contactless interface

settings managed by the host.

The FIFO buffer ensures fast and convenient data transfer between host and the

contactless UART.

The register bank contains the settings for the analog and digital functionality.

6. Pinning information

Fig 1. Simplified bloc k diagram of the CLRC663

001aaj627

HOST

ANTENNA FIFO

BUFFER

ANALOG

INTERFACE CONTACTLESS

UART SERIAL UART

SPI

C-BUS

(1) Pin 33 VSS - heatsink connection

Fig 2. Pinning configuration HVQFN32 (SOT617-1)

001aam004

heatsink

Transparent top view

TX1

(1)

DVDD

VDD

TVDD

SIGOUT XTAL1

SIGIN XTAL2

TCK PDOWN

TMS CLKOUT

TDI SCL

TDO SDA

AVDD

AUX1

AUX2

RXP

RXN

VMID

TX2

TVSS

IRQ

IF3

IF2

IF1

IF0

IFSEL1

IFSEL0

PVDD

817

718

619

520

421

322

223

124

terminal 1

index area

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

6.1 Pin description

[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

Table 3. Pin description

Pin Symbol Type Description

1 TDO O test data output for boundary scan interface

2 TDI I test data input boundary scan interface

3 TMS I test mode select boundary scan interface

4 TCK I test clock boundary scan interface

5 SIGIN I Contactless communication interface output.

6 SIGOUT O Contactless communication interface input.

7 DVDD PWR digital power supply buffer [1]

8 VDD PWR power supply

9 AVDD PWR analog power supply buffer [1]

10 AUX1 O auxiliary outputs: Pin is used for analog test signal

11 AUX2 O auxiliary outputs: Pin is used for analog test signal

12 RXP I receiver input pin for the received RF signal.

13 RXN I receiver input pin for the received RF signal.

14 VMID PWR internal receiver reference voltage [1]

15 TX2 O transmitter 2: delivers the modulated 13.56 MHz carrier

16 TVSS PWR transmitter ground, supplies the output stage of TX1, TX2

17 TX1 O transmitter 1: delivers the modulated 13.56 MHz carrier

18 TVDD PWR transmitter voltage supply

19 XTAL1 I crystal oscillator input: Input to the inverting amplifier of the oscillator. This is pin is also the

input for an externally generated clock (fosc = 27,12 MHz)

20 XTAL2 O crystal oscillator output: output of the inverting amplifier of the oscillator

21 PDOWN I Power Down

22 CLKOUT O clock output

23 SCL O Serial Clock line

24 SDA I/O Serial Data Line

25 PVDD PWR pad power supply

26 IFSEL0 I host interface selection 0

27 IFSEL1 I host interface selection 1

28 IF0 I/O interfac e pi n , mul t ifunction pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L

29 IF1 I/O interface pin, multifunction pin: Can be assigned to host interface SPI, I2C, I2C-L

30 IF2 I/O interfac e pi n , mul t ifunction pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L

31 IF3 I/O interfac e pi n , mul t ifunction pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L

32 IRQ O interrupt request: output to signal an interrupt event

33 VSS PWR ground and heatsink connection

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Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

7. Functional description

Fig 3. Detailed block diag ram of the CLRC663

001aam005

I2C,

LOGICAL

FIFO

512 Bytes

REGISTERS

STATEMACHINES

EEPROM

8 kByte

SPI

SAM interface

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

DVDD

POR

ADC PLLLFO

RX OSCTX

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

AVDD

RNG

ANALOGUE FRONT-END

BOUNDARY

SCAN

IF0

IFSEL0

IFSEL1

IF1

IF2

IF3

TCK

TDI

TMS

TDO

RESET

LOGIC PDOWN

I2C

RS232

SPI

host interfaces

INTERRUPT

CONTROLLER

IRQ SIGIN

TIMER0..3

CRC

TIMER4

(WAKE-UP

TIMER)

SIGPRO

CODEC

DECOD

CL-

COPRO

SIGIN/

SIGOUT

CONTROL

SIGOUT VMID RXN

RXP

TX1

TX2

XTAL1

XTAL2

SDA

SCL

VDD

VSS

PVDD

TVDD

TVSS

AUX1

AUX2

AVDD

DVDD

CLKOUT

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

7.1 Interrupt controller

The interrupt controller handles the enabling/disabling of interrupt requests. All of the

interrupts can be configured by firmware. Additionally, the firmware has possibilities to

trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0

and IRQ1 are implemented, accompanied by tw o 8- bit inter ru p t enab le re gisters IRQ0En

and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt

controller registers is implemented.

The CLRC663 indicates certain events by setting bit IRQ in the register Status1Reg and

additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the

host using its interrupt handling capabilities. This allows the implementation of efficient

host software.

Table 4. shows the available interrupt bit s, the corr esponding sou rce and th e condition for

its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in

underflows.

The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state

changes from send ing data to transmitting the end of the frame pattern, the transmitter

unit sets the interrupt bit automatically.

The bit RxIRQ in register IRQ0 indicates an in terrupt when the end of the received data is

detected.

The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the

command register changes to idle.

The register WaterLevel defines both - minimum and maximum warning levels - counting

from top and from bottom of the FIFO by a single value.

The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that

means the FIFO data number has reached the top level as configured by the register

Wa terLevel and bit WaterLevelExtBit.

The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that

means the FIFO data number has reached the bottom level as configured by the register

WaterLevel.

The bit ErrIRQ in register IRQ0 indicates an error detected by the cont actless UART

during receive. This is indicated by any bit set to logic 1 in register Error.

The bit LPCDIRQ in register IRQ0 indicates a card detected.

The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcar rie r by the

contactless UART during receiving.

The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt

source when enabled.

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

7.2 T imer module

Timer module overview

The CLRC663 implement s five timers. Four timers -T imer0 to T i mer3 - have an input clock

that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from

the 27.12 MHz quartz) or to be the under flow event o f the fifth T imer (Timer4). Each tim er

implements a counter register which is 16 bit wide. A reload value for the counter is

defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo. The

fifth timer Timer4 is intended to be used as a wakeup timer and is connected to the

internal LFO (Low Frequency Oscillator) as input clock source.

The TControl reg iste r allows the glo b al start and stop of eac h of the fo ur time rs Timer0 to

T i mer3. Additio nally, this register indicate s if one o f the time rs is running o r stopped . Each

of the five timers implements an individual configuration register set defin ing timer reload

value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,

T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.

T0Control).

The external host may use these timers to manage timing relevant tasks. The timer unit

may be used in one of the following configurations:

•Time-out counter

•Watch-dog counter

•Stop watch

•Programmable one -shot timer

•Periodical trigger

Ta ble 4. Interrupt sources

Interrupt bit Interrupt source Is set automatically, when

Timer0IRQ Timer Unit the timer register T0 CounterVal underflows

Timer1IRQ Timer Unit the timer register T1 CounterVal underflows

Timer2IRQ Timer Unit the timer register T2 CounterVal underflows

Timer3IRQ Timer Unit the timer register T3 CounterVal underflows

TxIRQ Transmitter a transmitted data stream ends

RxIRQ Receiver a received data stream ends

IdleIRQ Command Register a command execution finishes

HiAlertIRQ FIFO-buffer pointer the FIFO data number has reached the top level as

configured by the register WaterLevel

LoAlertIRQ FIFO-buffer pointer the FIFO data number has reached the bottom level as

configured by the register WaterLevel

ErrIRQ contactless UART a communication error had been detected

LPCDIRQ LPCD a card was detected when in low-power card detection

mode

RxSOFIRQ Receiver detection of a SOF or a subcarrier

GlobalIRQ all interrupt sources will be set if another interrupt request source is set

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NXP Semiconductors CLRC663

High performance NFC reader solution

The timer unit can be used to measure the time interval between two events or to indicate

that a specific event has occurred after an elapsed time. The timer register content is

modified by the timer unit, which can be used to generate an interrupt to allow an host to

react on this event.

The counter value of the timer is available in the registers T(x)CounterValHi,

T(x)CounterValLo. The content of these registers is decremented at each timer clock.

If the counter value has reached a value of 0000h and the interrupts are enabled for this

specific timer, an interrupt will be generated as soon as the next clock is received.

If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit

Timer(x)IRQ can be set and reset by the host controlle r. Depending on the configuration,

the timer will stop counting at 0000h or restart with the value loaded from registers

T(x)ReloadHi, T(x)ReloadLo.

The counting of the timer is indicated by bit TControl.T(x)Running.

The timer can be started by setting bits TControl.T(x)Running and

TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and

clearing TControl.T(x)Running.

Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful

if dedicated protocol requirements need to be fulfilled.

7.2.1 Timer modes

7.2.1.1 Time-Out- and Watch-Dog - Co un t er

Having configured the timer by setting register T(x)ReloadValue and st ar tin g the coun ting

of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit

decrement s the T(x)CounterValue Register beginning with the configured start event. If

the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received

from the card), the timer unit stops (no interrupt is generated).

If no stop event occurs, the timer unit continues to decrement the counter registers until

the content is zero and generates a timer interrupt request at the next clock cycle. This

allows to indicate to a ho st that the even t di d not occur du rin g th e con figur ed time inter val .

7.2.1.2 Wake-up timer

The wake-up Timer4 allows to wakeup the system from standby after a predefined time.

The system can be configured in such a wa y t hat it is entering the standby mode again in

case no card had been detected.

This functionality ca n be use d to imple m en t a low-power card detection (LPCD). For the

low-power card detection it is recommended to set T4Control.T4AutoWakeUp and

T4Control.T4AutoRestart, to activate the Timer4 and autom at ically set the syst em in

standby. The internal low frequency oscillator (LFO) is then used as input clock for this

Timer4. If a card is detected the host-communication can be started. If bit

T4Control.T4AutoW a keUp is not set, the CLRC663 will not enter the standby mode again

in case no card is detected but stays fully powered.

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NXP Semiconductors CLRC663

High performance NFC reader solution

7.2.1.3 Stop watch

The elapsed time between a configured st art- and stop event may be measured by the

CLRC663 timer unit. By setting the registers T(x)ReloadVa lueHi, T(x)reloadValueLo the

timer starts to decrement as soon as activated. If the configured stop event occu rs, the

timers stops decrement ing . Th e ela psed time between start and stop event can then be

calculated by the host dependent on the timer inte rval TTimer:

(1)

If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,

the performed time measurement according to the formula ab ove is not correct.

7.2.1.4 P rogra mma bl e on e -s hot time r

The host configures the interrupt and the timer, starts the timer and waits for the interrupt

event on pin IRQ. After the configured time the interrupt request will be raised.

7.2.1.5 Periodical trigger

If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt

request will be indicated periodically after every elapsed timer period.

7.3 Contactless interface unit

The contactless in terface unit of the CLRC663 supp ort s the following read /write oper ating

modes:

•ISO/IEC14443A/MIFARE

•ISO/IEC14443B

•FeliCA

•ISO/IEC15693/ICODE

•ICODE EPC UID

•ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

A typical system using the CLRC663 is using a microcontroller to implement the higher

levels of the contactless communication protocol and a power supply (battery or external

supply).



Timervaluevalue TTimerTreloadT *







Fig 4. Read/write mode

001aal996

BATTERY/POWER SUPPLY

reader/writer

MICROCONTROLLER

READER IC ISO/IEC 14443 A CARD

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NXP Semiconductors CLRC663

High performance NFC reader solution

7.3.1 ISO/IEC14443A/MIFARE functionality

The physical level of the communication is shown in Figure 5.

The physical p arameters are described in Table 5.

The CLRC663 connection to a host is required to manag e the complete

ISO/IEC 14443 A/MIFARE prot ocol . Figure 6 shows the data co ding and framing

according to ISO/IEC 14443A /MIFARE.

(1) Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s

(2) Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed

106 kbit/s to 848 kbit/s

Fig 5. ISO/IEC 14443 A/MIFARE read/write mode communication diagram

(1)

(2)

001aam268

ISO/IEC 14443 A CARD

ISO/IEC 14443 A

READER

Table 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication

direction Signal type Transfer speed

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Reader to card (send

data from the CLRC663

to a card)

fc = 13.56 MHz

reader side

modulation 100 % ASK 100% ASK 100% ASK 100% ASK

bit encoding modified Miller

encoding modified Miller

encoding

bit rate [kbit/s] fc / 128 fc / 64 fc / 32 fc / 16

Card to reader

(CLRC663 receives

data from a card)

card side

modulation subcarrier load

modulation

subcarrier

frequency fc/16fc/16fc /16fc/16

bit encoding Manchester

encoding BPSK BPSK BPSK

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NXP Semiconductors CLRC663

High performance NFC reader solution

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A

part 3 and handles parity generation internally according to the transfer speed.

Fig 6. Data coding and framing acco r din g to ISO/IEC 14443 A

001aak585

ISO/IEC 14443 A framing at 106 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start even

parity

start bit is 0

burst of 32

subcarrier clocks even parity at the

end of the frame

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NXP Semiconductors CLRC663

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7.3.2 ISO/IEC14443B functionality

The physical level of the communication is shown in Figure 7.

The physical p arameters are described in Table 6.

The CLRC663 connected to a host is required to manage the complete ISO/IEC 14443 B

protocol. The following Figure 8 “SOF and EOF according to ISO/IEC 14443 B” shows the

ISO/IEC 14443B SOF and EOF.

(1) Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s

(2) Card to reader , Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s

to 848 kbit/s

Fig 7. ISO/IEC 14443 A/MIFARE read/write mode communication diagram

(1)

(2)

001aal997

ISO/IEC 14443 B CARD

ISO/IEC 14443 B

READER

Table 6. Communication overview for ISO/IEC 14443 B reader/writer

Communication

direction Signal type Transfer speed

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Reader to card (send

data from the CLRC663

to a card)

fc = 13.56 MHz

reader side

modulation 10 % ASK 10 % ASK 10 % ASK 10 % ASK

bit encodin g NRZ NRZ NRZ NRZ

bit rate [kbit/s] 128 / fc 64 / fc 32 / fc 16 / fc

Card to reader

(CLRC663 receives

data from a card)

card side

modulation subcarrier load

modulation

subcarrier

frequency fc/16 fc/16 fc /16 fc /16

bit encoding BPSK BPSK BPSK BPSK

Fig 8. SOF and EOF according to ISO/IEC 14443 B

001aam270

UNMODULATED (SUB)

CARRIER

Start of Frame (SOF)

sequence

9.44 µs

''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''1'' ''1'' DATA

LAST CHARACTER UNMODULATED (SUB)

CARRIER

End of Frame (EOF)

sequence

9.44 µs

''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''

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NXP Semiconductors CLRC663

High performance NFC reader solution

7.3.3 FeliCa functionality

The FeliCa mode is the general reader/writer to card communication scheme according to

the FeliCa specification. The communication on a physical level is shown in Figure 9.

The physical p arameters are described in Table 7.

The CLRC663 needs to be connected to a dedicated host to be able to support the

complete FeliCa protocol.

7.3.3.1 FeliCa framing and coding

To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)

and 2 bytes sync bytes (B2h, 4Dh) are sent to synchronize the receiver.

The following Len byte indicates the le ngth of the sent data bytes plus the LEN byte itself.

The CRC calculation is done according to the FeliCa definitions with the MSB first.

To transmit data on the RF interface, the host controller has to send the Len- and data-

bytes to the CLRC663's FIFO-buffer. The preamble and the sync bytes are generated by

the CLRC663 automatically and must not be written to the FIFO by the host controller.

The CLRC663 performs internally the CRC calculation and adds the result to the data

frame.

Fig 9. FeliCa read/write co mmuni c ati on dia gram

Ta ble 7. Communication overview for FeliCa reader/writer

Communication

direction Signal type Tr ansfer speed FeliCa FeliCa higher transfer

speeds

212 kbit/s 424 kbit/s

Reader to card (send

data from the CLRC663

to a card)

fc = 13.56 MHz

reader side

modulation 8 % to 30 % ASK 8 % to 30 % ASK

bit encoding Manchester encoding Manchester encoding

bit rate fc/64 fc/32

Card to reader (CLRC663

receives data from a

card)

card side load

modulation Loadmodulation, Loadmodulation,

bit encoding Manchester encoding Manchester encoding

001aam271

FeliCa READER

(PCD)

FeliCa CARD

(PICC)

1. PCD to PICC 8-30 % ASK

Manchester Coded,

baudrate 212 to 424 kbaud

2. PICC to PCD, > Loadmodulation

Manchester Coded,

baudrate 212 to 424 kbaud

Table 8. FeliCa framing and coding

Preamble (Hex.) Sync

(Hex.) Len n-Data CRC

00 00 00 00 00 00 B2 4D

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7.3.4 ISO/IEC15693 functionality

The physical p arameters are described in Table 9.

[1] Fast inventory (page) read command only (ICODE proprietary command).

Table 9. Communication overview for ISO/IEC 15693 reader /writer reader to label

Communication

direction Signal type Transfer speed

fc / 8192 kbit/s fc / 512 kbit/s

Reader to label (send

data from the

CLRC663 to a card)

reader side

modulation 10 % to 30 % ASK or

100 % ASK 10 % to 30 % ASK 90 %

to 100 % ASK

bit encoding 1/256 1/4

data rate 1,66 kbit/s 26,48kbit/s

Table 10. Communication overview for ISO/IEC 15693 reader/writer label to reader

Communication

direction Signal type Transfer speed

6.62 (6.67) kbit/s 13.24

kbit/s[1] 26.48

(26.69) kbit/s 52.96 kbit/s

Label to reader

(CLRC663

receives data

from a card)

fc = 13.56 MHz

card side

modulation not supported not supported single (dual)

subcarrier

load

modulation

ASK

single

subcarrier

load

modulation

ASK

bit length

(s) - - 37.76 (37.46) 18.88

bit encoding - - Manchester

coding Manchester

coding

subcarrier

frequency

[MHz]

--fc/32

(fc / 28) fc / 32

Fig 10. Data coding according to ISO/IEC 15693. standard mode reader to label

001aam272

pulse

modulated

carrier

~9.44 μs

01 2 3 4

~18.88 μs

. 2 . . . ..... . . . . . . . . . 22..... 2 2

25555

5~4,833 ms 3245

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7.3.5 EPC-UID/UID-OTP functionality

The physical p arameters are described in Table 11.

Data coding and framing accordin g to EPC global 13.56 MHz ISM (industrial, scientific

and medical) Band Class 1 Radio Frequency Identification Tag Interface Specification

(Candidate Recommendation, Version 1.0.0).

7.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF functionality

The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this docume nt. Fo r a

detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1

HF standard.

7.3.6.1 Data encoding ICODE

The ICODE protocols have mainly three dif ferent methods of data encoding:

•“1” out of “4” codin g sch e me

•“1” out of “256” coding scheme

•“Return to Zero” (RZ) coding scheme

Data encoding for all three coding schemes is done by the ICODE generator.

The supported EPC Class-1 HF modes are:

•2 pulse for 424 kbit subcarrier

•4 pulse for 424 kbit subcarrier

•2 pulse for 848 kbit subcarrier

•4 pulse for 848 kbit subcarrier

7.3.7 ISO/IEC 18092 mode

The CLRC663 supports Passive Initiator Communication mode at the transfer speeds

106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.

•Passive communication mode means th at the t arget answers to an initiator comm and

in a load modulation scheme. The initiator is active in terms of generatin g the RF field.

•Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092

communication.

Table 11. Communication overview for EPC/UID

Communication

direction Signal type Transfer sp eed

26.48 kbit/s 52.96 kbit/s

Reader to card (send

data from the

CLRC663 to a card)

reader side modulation 10 % to 30 % ASK

bit encoding RTZ

bit length 37 .76 s

Card to reader

(CLRC663 receives

data from a card)

card side modulation single subcarrier load

modulation

bit length 18.88 s

bit encoding Manchester coding

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•Target: responds to initiator command either in a load modulation scheme in Passive

communication mode or using a self generated and self modu lated RF fie ld for Active

Communication mode.

7.3.7.1 Passive communication mode

Passive communication mode means that the t arget answers to an initiato r command in a

load modulation scheme. The initiator is active meaning generating the RF field.

The cont actless UART of CLRC663 and a dedicated ho st controller are required to ha ndle

the ISO/IEC 18092 passive initiator protocol.

Fig 11. Passive communication mode

Ta ble 12. Communication overview for Passive communica tion mode

Communication

direction 106 kbit/s 212 kbit/s 424 kbit/s

Initiator target According to

ISO/IEC 14443A

100 % ASK, Modified

Miller Coded

According to FeliCa, 8 % to 30 % ASK

Manchester Coded

Target initiator According to

ISO/IEC 14443A subcarrier

load modulation,

Manchester Coded

According to FeliCa, > 12 % ASK

Manchester Coded

host NFC INITIATOR

powered to

generate RF field

1. initiator starts communication

at selected transfer speed

2. targets answers using

load modulated data

at the same transfer speed

host

NFC TARGET

powered for

digital processing

001aan217

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7.3.7.2 ISO/IEC 18092 framing and codi n g

The ISO/IEC 18092 framing and coding in Passive communication mod e is defined in the

ISO/IEC 18092 standard.

7.3.7.3 ISO/IEC 18092 protocol support

The ISO/IEC 18092 proto col is not described in this do cumen t. For a det aile d explan ation

of the protocol, refer to the ISO/IEC 18092 standard.

7.4 Host interfaces

7.4.1 Host interface configuration

The CLRC663 supports direct interfacing of various host s a s th e SPI, I2C, I2CL and serial

UART interface type. The CLRC663 resets its interface and checks the current host

interface type automatically having performed a power-up or resuming from power down.

The CLRC663 identifies the host interface by the means of the logic levels on the control

pins after the Cold Reset Phase. This is done by a combination of fixed pin

connections.The following table shows the possible configurations defined by

IFSEL1,IFSEL0:

7.4.2 SPI interface

7.4.2.1 General

Table 13. Framing and coding overview

Transfer speed Framing and Coding

106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme

212 kbit/s According to the FeliCa scheme

424 kbit/s According to the FeliCa scheme

Table 14. Connection scheme for detecting the different interface types

Pin Pin Symbol UART SPI I2C I2C-L

28 IF0 RX MOSI ADR1 ADR1

29 IF1 n.c. SCK SCL SCL

30 IF2 TX MISO ADR2 SDA

31 IF3 PAD_VDD NSS SDA ADR2

26 IFSEL0 VSS VSS PAD_VDD PAD_VDD

27 IFSEL1 VSS PAD_VDD VSS PAD_VDD

Fig 12. Conne c tion to host with SPI

001aal998

READER IC

IF1

SCK

IF0

MOSI

IF2

MISO

IF3

NSS

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The CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has to

be generated by the master. Data communication from the master to the slave uses the

Line MOSI. Line MISO is used to send data back from the CLRC663 to the master.

A serial peripheral interface (SPI compatible) is supported to enable high speed

communication to a host. The implemented SPI compatible interface is according to a

standard SPI interface. The SPI comp atible interface can handle data speed of up to 10

Mbit/s. In the communication with a host CLRC663 acts as a slave r eceiving data fro m the

external host for register settings and to send and receive data relevant for the

communication on the RF interface.

NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,

the interface is disabled and reset. Between every SPI command the NSS must go to

logical high to be able to start the next command read or write.

On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line

shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling

edge. The sa me is valid for th e MISO line. Dat a is provided by the CLRC663 on the falling

edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.

7.4.2.2 Read data

To read out data from the CLRC663 by using the SPI compatible interface the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Remark: The Most Significant Bit (MSB) has to be sent first.

7.4.2.3 Write data

To write data to the CLRC663 using the SPI interface the following byte order has to be

used. It is possible to write more than one byte by sending a single address byte

(see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

Remark: The Most Significant Bit (MSB) has to be sent first.

7.4.2.4 Addres s by t e

The address byte has to fulfil the foll owing format:

The LSB bit of the first byte defines the used mode. To read data from the CLRC663 the

LSB bit is set to logic 1. To write data to the CLRC663 the LSB bit has to be cleared. The

bits 6 to 0 define the address byte.

Table 15. Byte Orde r for MOSI and MISO

byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1

MOSI address 0 address 1 address 2 …….. address n 00h

MISO X data 0 data 1 …….. data n  1 data n

Table 16. Byte Orde r for MOSI and MISO

byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1

MOSI address 0 data 0 data 1 …….. data n 1data n

MISO X X X …….. X X

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NOTE: When writing the sequence [addre ss byte][data0][data1][data2]..., [data0] is written

to address [address byte], [data1] is written to address [address byte + 1] and [data2] is

written to [address byte + 2].

Exception: This auto incremen t of the address byte is not performed if data is written to

the FIFO address

7.4.2.5 Timing Specification SPI

The timing condition for SPI interface is as follows:

Remark: To send more bytes in one dat a stream the NSS signal must be LOW during the

send process. To send more than one dat a stream the NSS signal must be HIGH between

each data stream.

Table 17. Address byte 0 register; address MOSI

76543210

address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read)

0 (write)

MSB LSB

Table 18. Timing conditions SPI

Symbol Parameter Min Typ Max Unit

tSCKL SCK LOW time 50 - - ns

tSCKH SCK HIGH time 50 - - ns

th(SCKH-D) SCK HIGH to data input hold time 25 - - ns

tsu(D-SCKH) data input to SCK HIGH set-up time 25 - - ns

th(SCKL-Q) SCK LOW to data output hold time - - 25 ns

t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns

tNSSH NSS HIGH time 50 - - ns

Fig 13. Connection to host with SPI

aaa-016093

tSCKL

tNSSH tSCKH tSCKL

tsu(D-SCKH) th(SCKH-D)

th(SCKL-Q)

t(SCKL-NSSH)

SCK

MOSI

MISO

MSB

LSB

NSS

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7.4.3 RS232 interface

7.4.3.1 Selection of the transfer speeds

The internal UART interface is compatible to a RS232 serial interface. The levels supplied

to the pins are between VSS and PVDD. To achieve full compatibility of the voltage levels

to the RS232 specification, a RS232 level shifter is required.

Table 20 “Selectable transfer speeds” describes examples for different transfer speeds

and relevant register settings. The resulting transfer speed error is less than 1.5 % for all

described transfer speeds. The default transfer speed is 115.2 kbit/s.

To change the transfer speed, the host controller has to write a value for the new transfe r

speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set

the transfer speed in the SerialSpeedReg.

Table 19 “Settings of BR_T0 and BR_T1” describes the settings of BR_T0 and BR_T1.

The selectab le transfer speeds as shown are calculated according to the following

formulas:

if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2(BR_T0 1)

Remark: Transfer speeds above 1228.8 kBits/s are not supported.

Table 19. Settings of BR_T0 and BR_T1

BR_T001234567

factor BR_T011248163264

range BR_T1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64

Ta ble 20. Selectable transfer speed s

Transfer speed (kbit/s) Serial SpeedReg Transfer speed accuracy (%)

(Hex.)

7.2 FA 0.25

9.6 EB 0.32

14.4 DA 0.25

19.2 CB 0.32

38.4 AB 0.32

57.6 9A 0.25

115.2 7A 0.25

128 74 0.06

230.4 5A 0.25

460.8 3A 0.25

921.6 1C 1.45

1228.8 15 0.32

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7.4.3.2 Framing

Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is used

during transmission.

Read dat a: To read out dat a using the UAR T interface the flow described below has to be

used. The first send byte defines both the mode itself and the addr ess.The Trigger on pin

IF3 has to be set, otherwise no read of data is possible.

Writ e d ata:

To write data to the CLRC663 using the UART interface the following sequence has to be

used.

The first send byte defines both, the mode itself and the address.

Ta ble 21. UART fr aming

Bit Length Value

Start bit (Sa) 1 bit 0

Data bits 8 bit Data

Stop bit (So ) 1 bit 1

Table 22. Byte Orde r to Read Data

Mode byte 0 byte 1

RX address -

TX - data 0

Fig 14. Example for UART Read

001aam298

A0 A1Sa A2 A3

RX A4 A5 A6 RD/

NWR So

DATA

ADDRESS

D1Sa D2 D3 D4 D5 D6 D7 So

Table 23. Byte Orde r to Write Data

Mode byte 0 byte 1

RX address 0 data 0

TX address 0

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Remark: Data can be sent before address is received.

7.4.4 I2C-bus interface

7.4.4.1 General

An Inter IC (I2C) bus interfac e is sup po r ted t o enab le a low cost, low pin count serial bus

interface to the host. The impl emented I2C interface is mainly implemented accor ding the

NXP Semiconductors I2C interface specification, rev. 3.0, June 2007. The CLRC663 can

act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode

plus.

The following features defined by the NXP Semiconductors I2C interface specification,

rev. 3.0, June 2007 are not supported:

•The CLRC663 I2C interface does not stretch the clock

•The CLRC663 I2C interface does no t support the general call. This means that the

CLRC663 does not support a software reset

•The CLRC663 does not support the I2C device ID

•The implemented interface can o nly act in slave mode. Therefore no clock g eneration

and access arbitration is implemented in the CLRC663.

•High speed mode is not supported by the CLRC663

The voltag e level on the I2C pins is not allowed to be higher than PVDD.

SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.

Both lines SDA and SCL are set to HIGH level if no data is transmitte d. Data on the

I2C-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in

the fast mode+.

Fig 15. Example diagram for a UART write

001aam299

A0 A1Sa A2 A3

RX A4 A5 A6 RD/

NWR

ADDRESS

A1Sa A2 A3 A4 A5 A6 RD/

NWR

DATA

D1Sa D2 D3 D4 D5 D6 D7 So

Fig 16. I2C-bus interf ace

001aam000

READER IC

SDA

SCL

PULL-UP

NETWORK

PULL-UP

NETWORK

MICROCONTROLLER

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If the I2C interface is selected, a spike suppression according to the I2C interface

specification on SCL an d SDA is aut oma tica lly act iva ted .

For timing requ ire m en ts refer to Table 250 “I2C-bus timing in fast mode and fast mode

plus”

7.4.4.2 I2C Data validity

Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state

or LOW state of the data line shall only change when the clock signal on SCL is LOW.

7.4.4.3 I2C START and STOP conditions

To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions

are defined.

A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is

HIGH.

A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is

HIGH.

The master always gener ates the START and ST OP co nditions. The bus is considered to

be busy after the START condition. The bus is consider ed to be free again a certain time

after the STOP condition.

The bus stays busy if a repea ted START (Sr) is generated instead of a STOP condition. In

this respect, the ST AR T (S) and repeated ST AR T (Sr) conditions are functionally identical.

Therefore, the S symbol will be used as a generic term to represent both the START and

repeated START (Sr) conditions.

Fig 17. Bit transfer on the I2C-bus.

001aam300

data line stable;

data valid

change

of data

allowed

SDA

SCL

Fig 18. START and STOP conditions

001aam301

START condition

SCL

SDA

SCL

SDA

STOP condition

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7.4.4.4 I2C byte format

Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB

first, see Figure 18 “START and STOP conditions”. The number of transmitted bytes

during one data transfer is unrestricted but shall fulfil the read/write cycle format.

7.4.4.5 I2C Acknowledge

An acknowledge at the end of one dat a byte is mandatory. The acknowledge-r elated clock

pulse is generated by the ma ster. The transmitter of data, either master or slave, releases

the SDA line (HIGH) during the acknowledge clock pulse . The receiver shall pull down the

SDA line during the acknowledge clock pulse so that it remains stable LOW during the

HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer, or a

repeated START (Sr) condition to start a new transfer.

A master-receiver shall indicate the en d of dat a to the slave- transm itter by not generating

an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter

shall release the dat a line to allow the master to gene rate a ST OP (P) or repe ated START

(Sr) condition.

Fig 19. Acknowledge on the I2C- bus

Fig 20. Data transfer on the I2C- bus

001aam302

clock pulse for

acknowledgement

SCL FROM

MASTER

DATA OUTPUT

BY RECEIVERER

DATA OUTPUT

BY TRANSMITTER

289

acknowledge

START

condition

not acknowledge

001aam303

MSB acknowledgement

signal from slave acknowledgement

signal from receiver

clock line held low while

interrupts are serviced

byte complete,

interrupt within slave

12789 12 9

ACK ACK

3 - 8 Sr

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7.4.4.6 I2C 7-bit addressing

During the I2C-bus addressing pr ocedur e, the fir st by te after the STAR T conditio n is used

to determine which slave will be selected by the master.

Alternatively the I2C address can be configured in the EEPROM. Several address

numbers are reserved for this purpose. During device configuration, the designer has to

ensure, that no collision with these reserved addresses in the system is possible. Check

the corresponding I2C specification for a complete list of reserved addresses.

For all CLRC66 3 devices the uppe r 5 bits o f the d evice bus addr ess are re served b y NXP

and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address can be

freely configured by the customer in order to prevent collisions with other I2C devices by

using the interface pins (refer to Table 14) or the value of the I2C address EEPROM

7.4.4.7 I2C-register write access

To write data from the host controller via I2C to a specific register of the CLRC663 the

following frame format shall be used .

The read/write bit shall be set to logic 0.

The first byte of a frame indicates the device address according to the I2C rules. The

second byte indicates the register address followed by up to n-da ta bytes. In case the

address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register

address. This enables for exampl e a fast FIFO access.

7.4.4.8 I2C-register read access

To read out data from a specific register ad dress of the CL RC66 3 th e h ost contro ller shall

use the proc ed ur e :

First a write access to the specific register address has to be perfor med as indicated in the

following frame:

The first byte of a frame indicates the device address according to the I2C rules. The

second byte indicates the register address. No data bytes are added.

The read/write bit shall be logic 0.

Having performed this write access, the read access starts. The host sends the device

address of the CLRC663. As an answer to this device addr ess the CLRC663 responds

with the content of the addressed register. In one frame n-data bytes could be read using

the same register address. The address pointing to the register is incremented

automatically (exception: FIFO register address is not incremented automatically). This

enables a fast transfer of register content. The address pointer is incremented

automatically and data is read from the locations [address], [address+1], [address+2]...

[address+(n-1)]

Fig 21. First byte following the START procedure

001aam304

Bit 6 Bit 5 Bit 4

slave address

Bit 3 Bit 2 Bit 1 Bit 0 R/W

MSB LSB

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In order to support a fast FIFO data transfer, the address pointer is not incremented

automatically in case the address is poin ting to the FIFO.

The read/write bit shall be set to logic 1.

7.4.4.9 I2CL-bus interface

The CLRC663 provides an additional interface option for connection of a SAM. This

logical interface fulfills the I2C specification, but the rise/fall timings will not be compliant to

the I2C standard. The I2CL interface uses standard I/O pads, and the communication

speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of

I2C. The SCL levels are generated by the host in push/pull mode. The RC663 does not

stretch the clock. During the high period of SCL the status of the line is maintained by a

bus keeper.

The address is 01010xxb, where the last two bits of the address can be defined by the

application. The definition of this bits can b e done by two options. With a pin, where the

higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the

EEPROM configuration in Section 7.7.

Fig 22. Register read and write access

001aam305

Ack

(W) Ack 0SA I2C slave address

A7-A0

Frontend IC register

address A6-A0 Ack

DATA

[7..0]

[0..n]

Ack

(W) Ack

Optional, if the previous access was on the same register address

Read Cycle

Write Cycle

0SA I2C slave address

A7-A0

Frontend IC register

address A6-A0

(R) AckSA

sent by master

sent by slave

I2C slave address

A7-A0 Ack

DATA

[7..0]

[0..n]

0..n

Nack

DATA

[7..0]

Table 24. Timing parameter I2CL

Parameter Min Max Unit

fSCL 05MHz

tHD;STA 80 - ns

tLOW 100 - ns

tHIGH 100 - ns

tSU;SDA 80 - ns

tHD;DAT 050ns

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The pull-up resistor is not required for the I2CL interface. Instead, a on chip buskeeper is

implemented in the CLRC663 for SDA of the I2CL interface. This protoco l is intended to be

used for a point to point connection of devices over a short distance and does no t support

a bus capability.The driver of the pin must force the line to the desired logic voltage. To

avoid that two drivers are pushing the line at the same time following regulations must be

fulfilled:

SCL: As there is no clock stretching, the SCL is always under control of the Master.

SDA: The SDA line is shared between master and slave. Therefore the master and the

slave must have the control over the own driver enable line of the SDA pin. The following

rules must be followed:

•In the idle phase the SDA line is driven high by the master

•In the time between st art and stop condition the SDA line is driven by maste r or slave

when SCL is low. If SCL is high the SDA line is not driven by any device

•To keep the value on the SDA line a on chip buskeeper structure is implemented for

the line

7.4.5 SAM interface

7.4.5.1 SAM functionality

The CLRC663 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM

(Secure Access Module) in a very convenient way into applications (e.g. a proximity

reader).

The SAM can be connected to the microcontroller to operate like a cryptographic

co-processor. For any cryptographic task, the microcontroller requests a operation from

the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface

to the connected reader IC.

The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient

way to reduce the protocol overhead. In this system configuration, the SAM is integrated

between the microprocessor and the reader IC, connected by one interface to the reader

IC and by another interface to the microcontroller. In this application the microcontroller

accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using an

I2C interface. The I2C SAM address is always defined by EEPROM register . Default value

is 0101100. As the SAM is directly communicating with reader IC, the communication

overhead is reduced. In this configuration, a performance boost of up to 40% can be

achieved for a transaction time.

The MIFARE SAM supports applications using MIFARE cards. For multi application

purposes an architecture conn ecting the micro controller additionally dire ctly to the reader

IC is recommended. This is possible by connecting the CLR C6 63 on on e int er fa ce (SAM

Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/T1AR1070) and by

connecting the microcontroller to the S2C or SPI interface.

tSU;DAT 020ns

tSU;STO 80 - ns

tBUF 200 - ns

Table 24. Timing parameter I2CL

Parameter Min Max Unit

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7.4.5.2 SAM connection

The CLRC663 provides an interface to connect a SAM dedicated to the CLRC663. Both

interface options of the CLRC663, I2C, I2CL or SPI can be used for this purpose. The

interface option of the SAM itself is configured by a host command sent from the host to

the SAM.

The I2CL interface is intended to be used as connection between two IC’s over a short

distance. The protocol fulfills the I2C specification, but does support a single device

connected to the bus only.

The SPI block for SAM connection is identical with the SPI host interface block.

The pins used for the SAM SPI are described in Table 25.

7.4.6 Boundary scan interface

The CLRC663 provides a boundary scan interface according to the IEEE 1149.1. This

interface allows to test interconnections without using physical test probes. This is done

by test cells, assigned to each pin, which override the functionality of this pin.

To be able to program the test cells, the following commands are supported:

Fig 23. I2C interface enables convenient MIFARE SAM integration

µC

Reader

T=1 I2C

I2C

aaa-002963

SAM

AV2.6

READER

Table 25. SPI SAM connectio n

SPI functionality PIN

MISO SDA2

SCL SCL2

MOSI IFSEL1

NSS IFSEL0

Ta ble 26. Bo undary scan command

Value

(decimal) Command Parameter in Parameter out

0 bypass - -

1 preload data (24) -

1 sample - data (24)

2 ID code (default) - data (32)

3 USER code - data (32)

4Clamp - -

5HIGH Z - -

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The S tandard IEEE 1149.1 describes the four basic blocks necessary to use this interface:

Test Access Port (TAP), TAP controller, TAP instruction register, TAP data register;

7.4.6.1 Interface signals

The boundary scan inte rfa ce imp lem e nts a four line inte r fac e be tw ee n th e chip an d the

environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test

Data Input (TDI) and on e output Test Data Output (TDO). TCK and TMS are broadcast

signals, TDI to TDO generate a serial line called Scan path.

Advantage o f this technique is that inde pendent of the number s of boundary sca n devices

the complete path can be handled with four signal lines.

The signals TCK, TMS are directly connected with the boundary scan controller. Because

these signals are responsible for the mode of the chip, all boun dary scan devices in one

scan path will be in the same boundary scan mode.

7.4.6.2 Test Clock (TCK)

The TCK pin is the input clock for the module. If this clock is provided, the test logic is able

to operate independent of any other system clocks. In addition, it ensures that multiple

boundary scan controllers that are daisy-chained together can synchronously

communicate serial test data between components. During normal operation, TCK is

driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for

extended periods of time. While TCK is stopped at 0 or 1, the state of the bou ndary scan

controller does not change and data in the Instruction and Data Registers is not lost.

The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking

occurs if the pin is not driven from an external source.

7.4.6.3 Tes t Mo d e Sel ec t (T M S )

The TMS pin selects the next state of the boundary scan controller. TMS is sampled on

the rising edge of TCK. Depending on the current boundary scan state and the sampled

value of TMS, the next state is entered. Because the TMS pin is sampled on the rising

edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the

falling edge of TCK.

Holding TMS high for five consecutive TCK cycles drives the boundary scan controller

state machine to the Test-Logic-Reset state. When the boundary scan controller enters

the Test-Logic-Reset state, the Instruction Register (IR) resets to the defaul t instruc tio n,

IDCODE. Therefore, this sequence can be used as a reset mechanism.

The internal pull-up resistor on the TMS pin is enabled.

7 extest data (24) data (24)

8 interface on/off interface (1) -

9 register access read address (7) data (8)

10 register access write address (7) - data (8) -

Ta ble 26. Bo undary scan command

Value

(decimal) Command Parameter in Parameter out

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7.4.6.4 Test Data Input (TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI

is sampled on the rising edge of TCK and, depending on the current TAP state and the

current instruction, presents this data to the proper shift register chain. Because the TDI

pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on

TDI to change on the falling edge of TCK.

The internal pull-up resistor on the TDI pin is enabled.

7.4.6.5 Test Data Output (TDO)

The TDO pin provides an output stream of serial information from the IR chain or the DR

chains. The value of TDO depends on the current TAP state, the current instruction, and

the data in the chain being accessed. In order to save power when the port is not being

used, the TDO pin is placed in an inactive drive state when not actively shifting out data.

Because TDO can be connected to the TDI of another controller in a daisy-chain

configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the

falling edge of TCK.

7.4.6.6 Data register

According to the IEEE1149.1 standard there are two types of data register defined:

bypass and boundary sca n

The bypass register enable the possibility to bypass a device when part of the scan

path.Serial dat a is allowed to be tra nsferred through a device from the TDI pin to the TDO

pin without affecting the operation of the device.

The boundary scan register is the scan-chain of the boundary cells. The size of this

7.4.6.7 Boundary sc an ce ll

The boundary scan cell opens the possibility to control a hardware pin independent of its

normal use case. Basically the cell can only do one of the following: control, output and

input.

7.4.6.8 Boundary sc an path

This chapter shows the boundary scan path of the CLRC663.

Fig 24. Boundary scan cell path structure

001aam306

TAP

LOGIC

TAP

IC1 IC2

TCK TMS

TDO

Boundary scan cell

TDI

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Refer to the CLRC663 BSDL file.

7.4.6.9 Boundary Scan Description Language (BSDL)

All of the boundary scan devices ha ve a un ique bo und ary structur e which is ne ce ssary to

know for operating the device. Important components of this language are:

•available test bus signal

•compliance pins

•command register

•data register

•boundary scan structure (number and types of the cells, their function and the

connection to the pins.)

The CLRC663 is using the cell BC_8 for the IO-Lines. The I2C Pin is using a BC_4 cell.

For all pad enable lines the cell BC1 is used.

The manufacturer's identification is 02Bh.

•attribute IDCODEISTER of CLRC663: entity is "0001" and -- version

Ta ble 27. Boundary scan path of the CLRC663

Number (decimal) Cell Port Function

23 BC_1 - Control

22 BC_8 CLKOUT Bidir

21 BC_1 - Control

20 BC_8 SCL2 Bidir

19 BC_1 - Control

18 BC_8 SDA2 Bidir

17 BC_1 - Control

16 BC_8 IFSEL0 Bidir

15 BC_1 - Control

14 BC_8 IFSEL1 Bidir

13 BC_1 - Control

12 BC_8 IF0 Bidir

11 BC_1 - Control

10 BC_8 IF1 Bidir

9 BC_1 - Control

8BC_8IF2Bidir

7 BC_1 IF2 Output2

6BC_4IF3Bidir

5 BC_1 - Control

4 BC_8 IRQ Bidir

3 BC_1 - Control

2 BC_8 SIGIN Bidir

1 BC_1 - Control

0 BC_8 SIGOUT Bidir

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•"0011110010000010b" and -- part number (3C82h)

•"00000010101b " and -- manufacturer (02Bh)

•"1b"; -- mandatory

The user code data is coded as followed:

•product ID (3 bytes)

•version

These four bytes are stored as the first four bytes in the EEPROM.

7.4.6.10 Non-IEEE1149.1 commands

Interface on/off: With this command the host/SAM interface can be deactivated and the

Read and Write command of the boundary scan interface is activated. (Data = 1). With

Update-DR the value is taken over.

Shifting the DR is shifting in a new address. With Update-DR this address is taken over

into the actual address.

the DR. The data is copied into the internal register at the given address.

7.5 Buffer

7.5.1 Overview

An 512 8-bit FIFO buffer is implemented in the CLRC663. It buffers the input and output

data stream between the host and the internal state machine of the CLRC663. Thus, it is

possible to handle data streams with lengths of up to 512 bytes without taking timing

constraints into account. The FIFO can also be limited to a size of 255 byte. In this case all

the parameters (FIFO length, Watermark...) require a single byte only for definition. In

case of a 512 byte FIFO length the definition of this values requires 2 byte s.

7.5.2 Accessing the FIFO buffer

When the -Controller starts a command, the CLRC663 may, while the command is in

progress, access the FIFO-buffer according to that command. Physically only one

FIFO-buffer is implemented, which can be used in input and output direction. Therefore

the -Controller has to take care, not to access the FIFO buffer in a way that corrupts the

FIFO data.

7.5.3 Controlling the FIFO buffer

Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be

reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits

are set to logic 0, the actually stored bytes are not accessible any more and the FIFO

buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)

again.

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7.5.4 Status Information about the FIFO buffer

The host may obtain the following data about the FIFO-buffers status:

•Number of bytes already stored in the FIFO-buffer. Writing increments, reading

decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl

•Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according

to the value of the water level in register WaterLevel (Register 02h bit [2], Register

03h bit[7:0])

•Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl

according to the value of the water level in register WaterLevel (Register 02h bit [2],

•FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was

already full: ErrIRQ in register IRQ0.

WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and

LoAlert (counting from the FIFO bottom). The CLRC663 can generate an interrupt signa l

if:

•LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert

in the register FIFOControl change s to 1.

•HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert

in the register FIFOControl change s to 1.

The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register WaterLevel)

or less can be stored in the FIFO-buffer. It is generated according to the following

equation:

(2)

The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less

are actually stored in the FIFO-buffer. It is generated according to the following equation:

(3)

HiAlert FiFoSize FiFoLength–WaterLevel=

LoAlert FIFOLength WaterLevel=

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7.6 Analog interface and contactless UART

7.6.1 General

The integrated cont actless UAR T supports the external host online with framing and error

checking of the protocol requirements up to 848 kbit/s. An external circuit can be

connected to the communication interface pins SIGIN and SIGOUT to modulate and

demodulate the data.

The cont actless UART handles th e protocol requirement s for the commun ication schemes

in co-operation with the host. T he pr otocol handlin g it self gen erates bit- and b yte-orien ted

framing and handles error detection like Parity and CRC according to the different

contactless communication schemes.

The size, the tuning of the antenna, and the supply voltage of the output drivers have an

impact on the achievable field strength. The operating distance between reader and card

depends additionally on the type of card use d.

7.6.2 TX transmitter

The signal delivere d on pin TX 1 an d pin TX2 is the 13.5 6 MHz carrie r mo d ula te d by an

envelope signal for energy and data transmission. It can be used to drive an antenna

directly, using a few passive components for matching and filtering, see Section 13

“Application information”. The signal on TX1 and TX2 can be configur ed by the register

DrvMode, see Section 8.8.1 “TxMode”.

The modulation index can be set by the TxAmp.

Following figure shows the general relations during modulation

Note: When changing the continuous ca rrier amplitude, the residual ca rrier amplitude also

changes, while the modulation index re mains the same.

Fig 25. General dependenc e s of modulation

001aan355

time

influenced by set_clk_mode envelope

TX ASK100

1: Defined by set_cw_amplitude.

2: Defined by set_residual_carrier.

TX ASK10

(1)

(2)

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The registers Section 8.8 and Section 8.10 control the data rate, the framing during

transmission and the setting of the antenna driver to support the requirements at the

different specified modes and transfer speeds.

Table 28. Settings for TX1 and TX2

TxClkMode

(binary) Tx1 and TX2 output Remarks

000 High impedance -

001 0 output pulled to 0 in an y case

010 1 output pulled to 1 in an y case

110 RF high side push open drain, only high side (push) MOS supplied

with clock, clock pa rity defined by invtx; low side

MOS is off

101 RF low side pull open drain, only low side (pull) MOS supplied

with clock, clock parity defined by invtx; high

side MOS is off

111 13.56 MHz clock derived

from 27.12 MHz quartz

divided by 2

push/pull Operation, clock polarity defined by

invtx; settin g for 10% modulation

Table 29. Setting residual carrier and modulation index by TXamp.set_r esidual_carrier

set_residual_carrier (decimal) residual carrier [%] modulation inde x [%]

0990.5

1981.0

2962.0

3943.1

4914.7

5895.8

6877.0

7867.5

8858.1

9848.7

10 83 9.3

11 82 9.9

12 81 10.5

13 80 11.1

14 79 11.7

15 78 12.4

16 77 13.0

17 76 13.6

18 75 14.3

19 74 14.9

20 72 16.3

21 70 17.6

22 68 19.0

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Note: At VDD(TVDD) <5 V and residua l carrier settings <50%, the accuracy of the

modulation index may be low in dependency of the antenna tuning impedance

7.6.2.1 Overshoot protection

The CLRC663 provides an overshoot protection for 100% ASK to avoid overshoots during

a PCD communication. Therefor e two timers ov ershoo t_t1 and overshoot_t2 can be used .

During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is

provided to the output driver. Followed by an amplitude denoted by set_residual_car rier

bits with the duration of over sh oot_ t2 .

23 65 21.2

24 60 25.0

25 55 29.0

26 50 33.3

27 45 37.9

28 40 42.9

29 35 48.1

30 30 53.8

31 25 60.0

Table 29. Setting residual carrier …continuedand modu lation index by

set_residual_carrier (decimal) residual carrier [%] modulation inde x [%]

Fig 26. Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d.

001aan356

2.50 3.03 3.56 4.10

time (μs)

7.0

5.0

(V)

3.0

1.0

-1.0

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7.6.2.2 Bit generator

The default coding of a data stream is done by using the Bit-Generator. It is activated

when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Ge nerator

encodes the dat a stream byte-wise and can apply the following encoding steps to each

data byte.

1. Add a start-bit of specified type at beginning of every byte

2. Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,

only full bits are supported

3. Add a parity-bit of a specified type

4. TxFirstBits (skips a given number of bits at the beginning of the first byte in a frame)

5. TxLastBits (skips a given number of bits at the end of the last byte in a frame)

6. Encrypt data-bit (MIFARE encryption)

TxFirstBits a nd TxLastBit s can be used at th e same time. If on ly a single da ta byte is sent,

it must be ensured that the range of TxFirstBits and TxLastBits do not overlap. It is not

possible to skip more than 8 bit of a single byte! ( (8 - TxFirstBits) + (8 - TxLastBits) ) < 8

By default, dat a bytes are always treate d LSB first. To make use of a MSB first coding, the

TxMSBFirst in the register CLCON1 needs to be set.

7.6.3 Receiver circuitry

7.6.3.1 General

The CLRC663 features a versatile quadrature receiver architecture with fully differential

signal input at RXP and RXN. It can be configured to achieve optimum performance for

reception of various 13.56 MHz based protocols.

For all processing units various adjustments can be made to obtain optimum

performance.

Fig 27. Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d

-1.0 1234

1.0

3.0

5.0

(V)

7.0

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7.6.3.2 B lo c k diag ra m

Figure 28 shows the block diagram of the receiver circuitry. The receiving process

includes several steps. First the quadrature demodulation of the carrier signal of

13.56 MHz is done. Several tuning steps in this circuit are possible.

The receiver can also be operated in a single ended mode. In this case the

Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP and

RXN need to be connected together and will provide a single ended signal to the receiver

circuitry.

When using the receiver in a single ende d mode the receiver sensitivity is d ecreased and

the achievable reading dist ance might be r educed, comp ared to the fu lly diff erential mode .

The quadrature- demodulator uses two different clocks, Q-clock and I-clock, with a phase

shift of 90 between them. Both re sulting baseband signals are amplified, filtered, digitized

and forwarded to a correlation circuitry.

The typical application is intended to implement the Fully dif ferential mode and will deliver

maximum reader /writer distance. The Quasi differential mode can be used together with

dedicated antenna topologies that allow a reduction of matching components at the cost

of overall reading performance.

Fig 28. Block diagram of receiver circuitry

Table 30. Co nfiguration for single or differential receiver

Mode rcv_rx_single pins RXP and RXN

Fully differential 0 provide differential signal from

differential antenna by separate

rx-coupling branches

Quasi differential 1 connect RXP and RXN together

and provide single ended signal

from antenna by a single

rx-coupling branch

001aan358

13.56 MHz

I/O CLOCK

GENERATION

I-clks

Q-clks

clk_27 MHz

TIMING

GENERATION

ADC

DATA

Adc_data_readyclk_27 MHz

mixer mix_out_i_p

2-stage BBA

mix_out_i_n

out_i_p

out_i_n

rx_p

rx_n

rx_p

rx_n

mixer

mix_out_q_p

2-stage BBA

mix_out_q_n

out_q_p

out_q_n

rcv_gain<1:0>

rcv_hpcf<1:0>

fully/quasi-differential

rcv_gain<1:0>

rcv_hpcf<1:0>

rx_p

rx_n

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During low power card detection the DC levels at the I- and Q-channel mixer outputs are

evaluated. This re qu ir es th at mixe rs ar e dir ec tly con n ec te d to th e ADC. This can be

configured by setting the bit Rx_ADCmode in register Rcv (38h).

7.6.4 Active antenna concept

Two main blocks are implemented in the CLRC663. A digital circuitry, comprising state

machines, coder and decoder logic and an analog cir cuitry with the modulator and

antenna drivers, receiver and amplification circuitry. For exa m ple , th e inte r fa ce be tween

these two blocks can be configured in the way, that the interfacing signals may be routed

to the pins SIGIN and SIGOUT. The most important use of this topology is the active

antenna conc e pt where th e dig i tal and the ana l og bloc ks ar e separat ed . This op en s th e

possibility to connect e.g. an additional digital block of another CLRC663 device with a

single analog antenna front-end.

The Table 31 and Table 32 describe the n ecessary reg ister config uration fo r the use case

active antenna concept.

The interface between these two blocks can be configured in the way, that the interfacing

signals may be routed to the pins SIGIN and SIGOUT (see Figure 30 “Overview

SIGIN/SIGOUT Signal Routing”).

This topology supports, that some parts of the analog part of the CLRC663 may be

connected to the digital part of another device.

The switch SigOutSel in registe rSigOut can be used to measur e signals. This is especially

important during the design In phase or for test purposes to check the transmitted and

received data.

Fig 29. Block diagram of the active Antenna concept

Ta ble 31. Register configuration of CLRC663 ac tive antenna concept (DIGITAL)

SigOut.SigOutSel 0100 TxEnvelope

Rcv.SigInSel 10

11 Receive over SigIn (ISO/IEC14443A)

Receive over SigIn (Generic Code)

DrvCon.TxSel 00 Low (idle)

Ta ble 32. Register configuration of CLRC663 active antenna concept (Antenna)

SigOut.SigOutSel 0110

0111 Generi c Code (Manchester)

Manchester with Subcarrier (ISO/IEC14443A)

Rcv.SigInSel 01 Internal

DrvCon.TxSel 10 External (SigIn)

RxCtrl.RxMultiple 1 RxMultiple on

001aam307

SIGIN

SIGINSIGOUT

SIGOUT

READER IC

(DIGITAL)

READER IC

(ANTENNA)

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However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.

An external active antenna circuit can be connected to the digital circuit of the CLRC663.

SigOutSel has to be configured in that way that the signal of the internal Miller Coder is

sent to SIGOUT pin (SigOutSel = 4). SigInSel h as to be configured to receive Manchester

signal with sub-carrier from SIGIN pin (SigInSel = 1).

It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate

filter and matching circuit) and at the same time an active antenna to the pins SIGOUT

and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a

single host processor.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

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Fig 30. Overview SIGIN/SIGOUT Sign al Routi ng

001aam001

CODER SIGOUTSel[4:0]

Sigpro_in_sel

[1:0]

SIGOUT

SIGIN

TX bit stream

DIGITAL MODULE ANALOG MODULE

RX bit stream

0, 1

tri-state

LOW

HIGH

TX envelope

TX active

S3C signal

RX envelope

8RX active

RX bit signal

DECODER

SUBCARRIER

DEMODULATOR

TxCon.TxSel

[1:0]

No_nodulation

TX envelope

RFU

SIGIN

tri-state

internal analog block

SIGIN over envelope

SIGIN generic

MODULATOR DRIVER

TX2

TX1

RXN

RXP

DEMODULATOR

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7.6.5 Symbol generator

The symbol generato r is used to cr eate variou s protocol symbols. These can be e. g. SOF

or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol

symbols like the CS symbol as used by the ICODE EPC protocol.

Symbols are defined by means of the symbol de finition registers and the mode registers.

Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a

maximum patter n length of 16 bit and feature a burst length of up to 256 bit s of either logic

“0” or logic “1”. The Symbol2 and Symbol3 are limited to 8 bit pattern length and do not

support a burs t.

The definition of symbol patterns is done by writing the bit sequence of the pattern to the

appropriate register. The last bit of the pa ttern to be sent is located at the LSB of the

TxSym32Len) the definition of the symbol pattern is completed. All other bits at

bit-position higher than the symbol length in the definition register are ignored. (Example:

length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pa ttern, bit5

is sent first)

Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0,

Symbol1 and Symbol2 can be sent be fore dat a p acket s, Symbol1, Symbol2 an d Symbol3

can be sent after data packets. Each symbol is defined by a set of registers. Symbols are

configured by a p air of registers. Symbol0 and Symbo l1 share the same configuration and

Symbol2 and Symbol3 share the same configur ation. The configuration includes setting of

bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the

envelope type.

7.7 Memory

7.7.1 Memory overview

The CLRC663 implements three different memories: EEPROM, FIFO and Registers.

At startup, the initialization of the registers which define the behavior of the IC is

performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and

section2, register reset) in to the r egister s. The behavior of the CLRC663 can be chang ed

by executing the command LoadProtocol, which copies a selected default protocol from

the EEPROM (read only EEPROM section4, register Set Protocol area) into the registers.

The read/write EEPROM section2 can be used to store any user data or predefined

"LoadRegister" into the internal registers.

The FIFO is used as Input/Out buffer and is able to improve the performance of a system

with limited interface speed.

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7.7.2 EEPROM memory organization

The CLRC663 has implemented a EEPROM non-volatile memory with a size of 8 kB.The

EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be programmed at

a time. Defined purposes had been assigned to specific memory areas of the EEPROM,

which are called Sections. Five sections 0..4 with different purpose do exist.

The following figure show the structure of the EEPROM:

Table 33. EEPROM memory organization

Section Page Byte

addresses Access

rights Memory content

0 0 00 to 31 r product information and configuration

32 to 63 r/w product configuration

1 1 to 2 64 to 191 r/w register reset

2 3 to 95 192 to 6143 r/w free

3 96 to 111 6144 to 7167 w MIF ARE key

4 112 to 128 7168 to 8191 r Register Set Protocol (RSP)

Fig 31. Sector arrangement of the EEPROM

001aan359

Production and configSection 0:

FreeSection 2:

MIFARE key area (MKA)Section 3:

RSP-Area for TXSection 4_TX:

RSP-Area for RXSection 4_RX:

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7.7.2.1 Product information and configuration - Page 0

The first EEPROM page includes production data as well as configuration information.

ProductID: Identifier for this CLRC663 product, only address 01h shall be evaluated for

identifying the Product CLRC663, address 00h and 02h shall be ignored by software.

Version: This register indicates the version of the EEPROM initialization data during

production. (Identification of the Hardware version is available in the register 7Fh, not in

the EEPROM V e rsion address. The hardware information in register 7Fh is hardwired and

therefore independent from any EEPROM configuration.)

Unique Identifier: Unique number code for this device

Manufacturer Data: This data is programmed during production. The content is not

intended to be used by any application and might be not the same for different devices.

Therefore this content needs to be considered to be undefined.

I2C-Address: T wo possibilities exist to define the address of the I2C interface. This can be

done either by configuring the pins IF0, IF2 (address is th en 10101xx, xx is defined by the

interface pins IF0, IF2) or by writing value into the I2C add re ss area. The selection , which

of this 2-information pin configuration or EEPROM content - is used as I2C-address is

done at EEPROM address 21h (Interface, bit4)

Interface: This section describes the interface byte configuration.

Table 34. Production area (Page 0)

Address

(Hex.) 0 1 2 3 4 5 6 7

00 ProductID Version Unique Identifier

08 Unique Identifier Manufacturer

Data

10 ManufacturerData

18 ManufacturerData

Table 35. Product ID overv iew of CLRC663 family

Address 01h Product ID

CLRC663 01h

MFRC631 C0h

MFRC630 80h

SLRC610 20h

Table 36. Configuration area (Page 0)

Address

(Hex.) 0 1 2 3 4 5 6 7

20 I2C_Address Interface I2C SAM_Address DefaultProtRx DefaultProtTx - TxCRCPreset

28 RxCRCPreset - - - - - -

30 -

38 -

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I2C_SAM_Address: The I2C SAM Address is always defined by the EEPROM content.

The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)

and for the RX registers (8 bytes).

TxCrcPreset: The data bits are send by the analog module and are automatically

extended by a CRC.

Table 37. Inter face byte

Bit 7 6 5 4 3 2 1 0

I2C_HSP - - I2C_Addre ss Boundary Scan Host

access rights r/w RFU RFU r/w r/w - - -

Ta ble 38. Interface bits

Bit Symbol Description

7 I2C_HSP when cleared, the high speed mode is used

when set, the high speed+ mode is used (default)

6, 5 RFU -

2C_Address when cleared, the pins are used (default)

when set, the EEPROM is used

3 Boundary

Scan when cleared, the boundary scan interface is ON (default)

when set, the boundary scan is OFF

2 to 0 Host 000b - RS232

001b - I2C

010b - SPI

011b - I2CL

1xxb - pin selection

Table 39. Tx and Rx arrangements in the register set protocol area

Section

Section 4 TX Tx0 Tx1 TX2 Tx3

Section 4 TX Tx4 Tx5 TX6 TX7

Section 4 Rx RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7

Section 4 Rx RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15

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7.7.3 EEPROM initialization content LoadProtocol

The CLRC663 EEPROM is initialized at production with values which are used to reset

certain register s of the CLRC663 to default settings by copying the EEprom conten t to the

registers. Only registers or bits with “read/write” or “dynamic” access rights are initialized

with this default values copied from the EEPr om.

Note that the addresses used for copying reset values from EEprom to registers are

dependent on the configured protocol and can be changed by the user.

The register reset values are configuration pa rameters used after startup of the IC. They

can be changed to modify the default behavior of the device. In addition to this register

reset values, is the possibility to load settings for various user implemented protocols.The

load protocol command is used for this purpose.

Table 40. Register reset valu es (Hex.) (Page0)

Address 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F)

Function Product ID Version Unique Identifier

00 XX see table 34 XX XX XX XX XX XX

Function Unique Identifier Factory trim

value

08 XX XX XX XX XX XX XX XX

Function TrimLFO Factory trim values

10 XX XX XX XX XX XX XX XX

Function Factory trim values

18.... XX XX XX XX XX XX XX XX

Factory trim values

....38XXXXXXXXXXXXXXXX

Table 41. Register reset valu es (Hex.)(Page1 and page 2)

Address 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F)

Command HostCtrl FiFoControl WaterLevel FiFoLength FiFoData IRQ0 IRQ1

40 40 00 80 05 00 00 00 00

IRQ0En IRQ1En Error Status RxBitCtrl RxColl TControl T0Control

48 10 00 00 00 00 00 00 00

T0ReloadHi T0ReloadLo T0Counter

ValHi T0Counter

ValLo T1Control T1ReloadHi T1ReloadLo T1Counter

ValHi

50 00 80 00 00 00 00 80 00

T1Counter

ValLo T2Control T2ReloadHi T2ReloadLo T2Counter

ValHi T2Counter

ValLo T3Control T3ReloadHi

58 00 00 00 80 00 00 00 00

T3ReloadLo T3Counter

ValHi T3Counter

ValHi T4Control T4ReloadHi T4ReloadLo T4Counter

ValHi T4Counter

ValLo

60 80 00 00 00 00 80 00 00

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DrvMode TxAmp DrvCon Txl TxCRC

Preset RxCRC

Preset TxDataNum TxModWith

68 86 15 11 06 18 18 08 27

TxSym10

BurstLen TxWaitCtrl TxWaitLo FrameCon RxSofD RxCtrl RxWait RxThres

hold

70 00 C0 12 CF 00 04 90 3F

Rcv RxAna RFU SerialSpeed LFO_trimm PLL_Ctrl PLL_Div LPCD_QMi

78 12 0A 00 7A 80 04 20 48

LPCD_

QMax LPCD_IMin LPCD

_result_I LPCD

_result_Q PadEn PadOut PadIn SigOut

80 12 88 00 00 00 00 00 00

TxBitMod RFU TxDataCon TxDataMod TxSymFreq TxSym0H TySym0L TxSym1H

88 20 xx 04 50 40 00 00 00

TxSym1L TxSym2 TxSym3 TxSym10Le

ngth TxSym32Le

ngth TxSym32Bu

rstCtrl TxSym10M

od TxSym32M

90 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x50

RxBitMod RxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod RXCorr FabCal

98 0x02 0x00 0x00 0x01 0x00 0x08 0x08 0xB2

Table 41. Register reset valu es (Hex.)(Page1 and page 2) …continued

Address 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F)

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7.8 Clock generation

7.8.1 Crystal oscillator

The clock applied to the CLRC663 act s as time basis for gener ation of the carr ier sent ou t

at TX and for the quadrature mixer I and Q clock generation as well as for the coder and

decoder of the synchronous system. Therefore stability of the clock frequency is an

important factor for proper performance. To obtain highest pe rformance, clo ck jitter ha s to

be as small as possible. This is best achieved by using the internal oscillator buffer with

the recomme nde d circuitry.

7.8.2 IntegerN PLL clock line

The CLRC663 is able to provide a clock with configurable frequency at CLKOUT from

1 MHz to 24 MHz (PLL _C trl an d PL L_ DIV) . There it can serve as a clock source to a

microcontroller which avoids the need of a second crystal oscillator in the reader system.

Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.

Two dividers are determining the outp ut frequ ency. First a feedback integer-N divider

configures th e VC O fr eq ue n cy to be N fin/2 (control signal pll_set_divfb). As supported

Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be

23 fin / 2 (312 MHz), 27 fin / 2 (366 MHz) and 28 fin / 2 (380 MHz).

The VCO frequency is divided by a factor which is defined by the output divider

(pll_set_divout). Table 43 “Divid er values for selected frequencies using the integerN PLL”

shows the accuracy achieved for various frequencies (integer multiples of 1 MHz and

some typical RS232 frequen cies) and the divider ratios to be used. The register bit

ClkOutEn enables the clock at CLKOUT pin.

The following formula can be us ed to calculate the output frequency:

Fig 32. Quartz connection

Ta ble 42. Crystal requirements recommendations

Symbol Parameter Conditions Min Typ max Unit

fxtal crystal frequency - 27.12 - MHz

fxtal/fxtal relative crystal

frequency variation 250 - +250 ppm

ESR equivalent series

resistance -50100

CLload capacitance - 10 - pF

Pxtal crystal power

dissipation -50100W

001aam308

27.12 MHz

XTAL1 XTAL2

READER IC

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fout = 13.56 MHz PLLDiv_FB /PLLDiv_Out

7.8.3 Low Frequency Oscillator (LFO)

The Low-Frequency ( LFO) is implemented to drive a wake-up counter (WUC). This wakes

up the system in regular time intervals and eases the design of a reader that is regularl y

polling for card presence or implements a low-power card detection.

The LFO is trimmed during production to run at 16 kHz. Unless a high accuracy of the

LFO is required by the application and the device is operated in an environment with

changing ambient temperatures, trimming of the LFO is not required. For a typical

application making use of the LFO for wake up fr om power down, th e trim value set dur ing

production can be used. Optional trimming to achieve a higher accuracy of the 16 kHz

LFO clock is supported by a digital state machine which compares LFO-clock to a

reference clo ck. As refe re nc e clockfrequency the 13.56 MHz crystal clock is available.

Table 43. Divider values for selected frequencies using the integerN PLL

Frequency [MHz] 468101220241.84323.6864

PLLDiv_FB 2327232823282328 28

PLLDiv_Out 78 61 39 38 26 19 16 206 103

accuracy [%] 0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01 0.01

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7.9 Power management

7.9.1 Supply concept

The CLRC663 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD

(Transmitter Power Supply). These three voltages are indep endent from each other.

To connect the CLRC663 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be at

a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at

TVDD will result in a higher field strength.

Independent of the voltage it is recommended to buffer these supplies with blocking

capacitances close to the terminals of the package. VDD and PVDD are recomm ended to

be blocked with a capacitor of 10 0 nF min, TVDD is recommended to be blocked with 2

capacitors, 100 nF parallel to 1.0 F

AVDD and DVDD are not supply input pins. They are output pins and shall be connected

to blocking capacitors 470 nF each.

7.9.2 Power reduction mode

7.9.2.1 Power-down

A hard power-down is enable d with HIGH level on pin PDOWN. This turn s off the internal

1.8 V voltage regulators for the analog and digital core supply as well as the oscillator. All

digital input buffers are separated from the input pads and clamped internally (except pin

PDOWN itself). The output pins are switched to high impedance. HardPowerDown is

performing a reset of the IC. All registers will be reset, the Fifo will be cleared.

To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This will

start the internal start-up sequence .

7.9.2.2 Standby mode

The standby mode is entered immediately after setting the bit PowerDown in the register

Command. All internal current sinks are switched off. Voltage references and voltage

regulators will be set into stand-by mode.

In opposition to the power-down mode, the digit al input buffers are not separated by the

input pads and keep their functionality. The digital output pins do not change their state.

During standby mode, all registers values, the FIFO’s content and the configuration itself

will keep its current content.

To leav e the standby mod e th e bit Pow er Do w n in the regis te r Com m an d is cleared . Th is

will trigger the internal start-up sequence. The reader IC is in full operation mode again

when the internal start-up sequence is finalized (the typical duration is 15 us).

A value of 55h must be sent to the CLRC663 usin g the RS232 interface to leave the

standby mode. This is must at RS232, but cannot be used for the I2C/SPI interface. Then

read accesses shall be performed at address 00h until the device returns the content of

this address. The return o f the content of address 00h indicates that the device is ready to

receive further commands and the internal start-up sequence is finalized.

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7.9.2.3 Modem off mode

When the ModemOff bit in the register Control is set the antenna transmitter and the

receiver are switc hed off.

To leave the modem off mode clears the ModemOff bit in the register Control.

7.9.3 Low-Power Card Detection (LPCD)

The low-power card detection is an energy saving mod e in which the CLRC663 is not fully

powered permane ntly.

The LPCD works in two phases. First th e standby phase is controlled by the wake-up

counter (WUC), which defines the duration of the st andby of the CLRC663. Second phase

is the detection-phase. In this phase the values of the I and Q channel are detected and

stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time period can be

handled with Timer3. The value is compared with the min/max values in the registers

(LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the limits, a

LPCDIRQ is raised.

After the command LPCD the standby of the CLRC663 is activated, if selected. The

wake-up Timer4 can activate the system after a given time. For the LPCD it is

recommended to set T4AutoWakeUp and T4AutoRest art, to st art the timer a nd then go to

standby. If a card is detected the communication can be started. If T4AutoWakeUp is not

set, the IC will not enter Standby mode in case no card is detected.

7.9.4 Reset and start-up time

A 10 s constant high level at the PDOWN pin starts the internal reset procedure.

The following figure shows the internal voltage regulator:

When the CLRC663 has finished the reset phase and the oscillator has entered a stable

working condition the IC is ready to be used. A typical duration before the IC is ready to

receive commands after the reset had been released is 2.5ms.

Fig 33. Internal PDown to voltage regulator logic

001aan360

PVDD

PDown

GLITCH

FILTER

INTERNAL VOLTAGE

REGULATOR

1.8 V

AVDD

DVDD

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7.10 Command set

7.10.1 General

The behavior is determined by a state machine capable to perform a certain set of

commands. By writing a command-code to the command register the command is

executed.

Argument s and/or data necessary to process a command, are exchanged via the FIFO

buffer.

•Each command that needs a certain number of arguments will start processing only

when it has received the correct number of arguments via the FIFO buffer.

•The FIFO buf fer is not cleared automatically at command start. It is recommended to

write the command arg uments and/or the dat a bytes into the FIFO buf fer and st art the

command af terwards.

•Each command may be stopped by the host by writing a new command code into the

command register e.g.: the Idle-Command.

7.10.2 Command set overview

Table 44. Comman d set

Command No. Parameter (bytes) Short description

Idle 00h - no action, cancels current command execution

LPCD 01h - low - power card detection

LoadKey 02h (keybyte1),(keybyte2), (keybyte3),

(keybyte4), (keybyte5),(keybyte 6); reads a MIFARE key (size of 6 bytes) from FI FO buffer

ant puts it into Key buffer

MFAuth ent 03h 60h or 61h, (block address), (card

serial number byte0),(card serial

number byte1), (card serial number

byte2),(card serial number byte3);

performs the MIFARE standard authentication

AckReq 04h - performs a query, an Ack and a Req-Rn for ISO/IEC

18000-3 mode 3/ EPC Class-1 HF

Receive 05h - activates the receive circuit

Transmit 06h bytes to send: byte 1, byte2,.... transmits data from the FIFO buffer

Transceive 07h bytes to send: byt e 1, byte2,.... transmits data from the FIFO buffer and automatically

activates the receiver after transmission finished

WriteE2 08h addressH, addressL, data; gets one byte from FIFO buffer and writes it to the

internal EEPROM

WriteE2Page 09h (page Address), data0, [data1

..data63]; gets up to 64 bytes (one EEPROM p a ge) from the FIFO

buffer and writes it to the EEPROM

ReadE2 0Ah addressH, address L, length; reads data from the EEPROM and copies it into the

FIFO buffer

LoadReg 0Ch (EEPROM addressH), (EEPROM

addressL), RegAdr, (number of

reads data from the internal EEPROM and initializes the

CLRC663 registers. EEPROM address needs to be

within EEPROM sector 2

LoadProtocol 0Dh (Protocol number RX), (Proto col

number TX); reads data from the internal EEPROM and initializes the

CLRC663 registers needed for a Protocol change

LoadKeyE2 0Eh KeyNr; copies a key from the EEPROM into the key buffer

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7.10.3 Command functionality

7.10.3.1 Idle command

Command (00h);

This command indicates that the CLRC663 is in idle mode. This command is also used to

terminate the actual command.

7.10.3.2 LPCD command

Command (01h);

This command performs a low-power card detection and/or an automatic trimming of the

LFO. After wakeup from standby, the values of th e sampled I and Q channels are

compared with the min/max threshold values in the registers. If it exceeds the limits, an

LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected.

7.10.3.3 Load key command

Command (02h), Parameter1 (key byte1),..., Parameter6 (key byte6);

Loads a MIFARE Key (6 bytes) for Authentication from the FIFO into the crypto unit.

Abort condition: Le ss th an 6 bytes written to the FIFO .

7.10.3.4 MFAuthent command

Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2

(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number

byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3) ;

This command handles the MIFARE authentication in Reader/Writer mode to ensure a

secure communication to any MIFARE classic card.

When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is

an access to the FIFO, the bit WrErr in the Error register is set.

This command terminates automatically when the MIFARE card is authenticated and the

bit MFCrypto 1On is set to logic 1.

This command does not terminat e automatically, when the card does not answer,

therefore the timer should be initialized to automatic mode. In this case, beside the bit

IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication

processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if the

authentication was successful. The Crypto1On is always valid.

In case there is an error during authentication, the bit ProtocolErr in the Error register is

set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.

StoreKeyE2 0Fh KeyNr, byte1,byte2, byte3, byte4,

byte5,byte6; stores a MIFARE key (size of 6 bytes) into the EEPROM

ReadRNR 1Ch - Copies bytes from the Random Number generator into

the FIFO until the FiFo is full

Soft Reset 1Fh - resets the CLRC663

Table 44. Comman d set …continued

Command No. Parameter (bytes) Short description

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7.10.3.5 AckReq command

Command (04h);

Performs a Query (Full command must be written into the FIFO); a Ack and a ReqRn

command. All answers to the command will be written into the FIFO. The error flag is

copied after the answer into the FIFO.

This command terminates automatically and the then active state is idle.

7.10.3.6 Receive command

Command (05h);

The CLRC663 activates the receiver path and waits for any data stream to be received,

according to its register settings. The registers must be set before starting this command

according to the used proto col and antenn a configuration. Th e correct settings have to be

chosen before starting the command.

This command terminates automatically when the received data stream ends. This is

indicated either by the end of frame pattern or by the length byte depending on the

selected framing and speed.

Remark: If the bit RxMultiple in the RxModeReg register is set to log ic 1, the Receiv e

command does not terminate au tomatically. It has to be terminated by activating any other

command in the CommandReg register (see Section 8.17.6 “RxMod”).

7.10.3.7 Transmit command

Command (06h); data to transmit

The content of the FIFO is transmitted immediately after starting the command. Before

transmitting the FIFO all relevant registers have to be set to tr ansmit data.

This command terminates automatically when the FIFO gets empty. It can be terminated

by any other command written to the command re gister.

7.10.3.8 Transceive command

Command (07h); data to transmit

This command transmits data from FIFO buffer and automatically activates the receiver

after a transmission is finished.

Each transmission process starts by writing th e command into CommandReg.

Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will

never leave the receiving state, because the receiving will not be cancelled automatically.

7.10.3.9 WriteE2 command

Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data);

This command writes one byte into the EEPROM. If the FIFO contains no data, the

command will wait until the data is available.

Abort condition: Address-parameter outside of allowed range 0x00 – 0x7F.

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7.10.3.10 W riteE2PAGE command

Command (09h), Parameter1 (page address), Parameter2..63 (data0, data1...data63);

This command writes up to 64 bytes into the EEPROM. The addresses are not allowed to

wrap over a p age border. If this is the case, this additional data be ignored and stays in the

fifo. The programming starts after 64 bytes are read from the FIFO or the FIFO is em pty.

Abort condition: Insufficient parameters in FIFO; Page address parameter outside of

range 0x00 – 0x7F.

7.10.3.11 ReadE2 command

Command (0Ah), Paramete r1 (addressH), Parameter2 (addressL), Parameter3 (length);

Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the

address 1FFFh, the read operation continues from address 0000h.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

7.10.3.12 LoadReg command

Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL),

Parameter3 (RegAdr), Parameter 4 (number);

Read a defined number of bytes from the EEPROM and copies the value into the Register

set, beginning at the given address RegAdr.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

7.10.3.13 LoadProtocol command

Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);

Reads out the EEPROM Regi ster Set Protocol Area and overwrites the content of the Rx-

and Tx- related registers. These registers are important for a Protocol selection.

Abort condition: Insufficient parameter in FIFO

Table 45. Pred efined protocol overview RX[1]

Protocol

Number

(decimal)

Protocol Receiver speed

[kbits/s] Receiver Coding

00 ISO/IEC14443 A 106 Manchester SubC

01 ISO/IEC14443 A 212 BPSK

02 ISO/IEC14443 A 424 BPSK

03 ISO/IEC14443 A 848 BPSK

04 ISO/IEC14443 B 106 BPSK

05 ISO/IEC14443 B 212 BPSK

06 ISO/IEC14443 B 424 BPSK

07 ISO/IEC14443 B 848 BPSK

08 FeliCa 212 Manchester

09 FeliCa 424 Manchester

10 ISO/IEC15693 26 SSC

11 ISO/IEC15693 52 SSC

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[1] For more protocol details please refer to Section 7 “Functional description”.

12 ISO/IEC15693 26 DSC

13 EPC/UID 26 SSC

14 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF 212 2/424

15 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF 106 4/424

16 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF 424 2/848

17 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF 212 4/848

Table 46. Pred efined protocol overview TX[1]

Protocol

Number

(decimal)

Protocol Transmitter speed

[kbits/s] Transmitter Coding

00 ISO/IEC14443 A 106 Miller

01 ISO/IEC14443 A 212 Miller

02 ISO/IEC14443 A 424 Miller

03 ISO/IEC14443 A 848 Miller

04 ISO/IEC14443 B 106 NRZ

05 ISO/IEC14443 B 212 NRZ

06 ISO/IEC14443 B 424 NRZ

07 ISO/IEC14443 B 848 NRZ

08 FeliCa 212 Manchester

09 FeliCa 424 Manchester

10 ISO/IEC15693 26 1/4

11 ISO/IEC15693 26 1/4

12 ISO/IEC15693 1,66 1/256

13 EPC/UID 53 Unitray

14 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF based on Tari value,

ASK, PIE

15 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF based on Tari value,

ASK, PIE

16 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF based on Tari value,

ASK, PIE

17 ISO/IEC 18000-3 mode 3/

EPC Class-1 HF based on Tari value,

ASK, PIE

18 RFU

Table 45. Pred efined protocol overview RX[1]

Protocol

Number

(decimal)

Protocol Receiver speed

[kbits/s] Receiver Coding

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7.10.3.14 LoadKeyE2 comman d

Command (0Eh), Parameter1 (key number);

Loads a MIFARE key for authentication from the EEPROM into the crypto 1 unit.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE key area.

7.10.3.15 S toreKeyE2 command

Command (0Fh), Paramete r1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),

Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7

(keybyte6);

S tores MIFARE Keys into the EEPROM. The key number parameter indicates the first key

(n) in the MKA that will be written. If more than one MIFARE Key is available in the FIFO

then the next key (n+1) will be written until the FIFO is empty. If an incomplete key (less

than 6 bytes) is written into the FIFO, this key will be ignored and will remain in the FIFO.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;

7.10.3.16 GetRNR command

Command (1Ch);

This command is reading Random Numbers from the random number generator of the

CLRC663. The Random Numbers are copied to the FIFO until the FIFO is full.

7.10.3.17 SoftReset command

Command (1Fh);

This command is performing a sof t reset. T riggered by this comman d all the default values

for the register setting will be read from the EEPROM and copied into the register set.

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8. CLRC663 registers

8.1 Register bit behavior

Depending on the functionality o f a register, the access conditions to the register can vary.

In principle, bits with same behavior are grouped in common registers. The access

conditions are described in Table 47.

Table 47. Behavior of register bits and their designation

Abbreviation Behavior Description

r/w read and write These bits can be written and read via the host interface. Since

they are used only for control purposes, the content is not

influenced by the state machines but can be read by internal state

machines.

dy dynamic These bits can be written and read via the host interface. They

can also be written automatically by internal state machines, for

example Command register changes its value automatically after

the execution of the command.

r read only These register bits indicates hold values which are determined by

internal states only.

w write on l y Reading these register bi ts always returns zero.

RFU - These bits are reserved for future use and must not be chan ged.

In case of a required write access, it is recommended to write a

logic 0.

Table 48. CLRC663 registers overview

Address Register name Function

00h Command Starts and stops command execution

01h HostCtrl Host control register

02h FIFOControl Control register of the FIFO

03h WaterLevel Level of the FIFO underflow and ove rflow warning

04h FIF OLength Length of the FIFO

05h FIFOData Data In/Out exchange register of FIFO buffer

06h IRQ0 Interrupt register 0

07h IRQ1 Interrupt register 1

08h IRQ0En Interrupt enable register 0

09h IRQ1En Interrupt enable register 1

0Ah Error Error bits showing the error status of the last command execution

0Bh Status Contains status of the communication

0Ch RxBitCtrl Control register for anticollision adjustments for bit oriented protocols

0Dh RxColl Collision position register

0Eh TControl Control of Timer 0..3

0Fh T0Control Control of Timer0

10h T0ReloadHi High register of the reload value of Timer0

11h T0ReloadLo Low registe r of th e reload value of Timer0

12h T0CounterValHi Counter value high re gister of Timer0

13h T0CounterValLo Counter value low register of Timer0

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14h T1Control Control of Timer1

15h T1ReloadHi High register of the reload value of Timer1

16h T1ReloadLo Low register of the reloa d value of Timer1

17h T1CounterValHi Counter value high re gister of Timer1

18h T1CounterValLo Counter value low register of Timer1

19h T2Control Control of Timer2

1Ah T2ReloadHi High byte of the reload value of Timer2

1Bh T2ReloadLo Low byte of the reload value of Timer2

1Ch T2CounterValHi Counter value high byte of Timer2

1Dh T2CounterValLo Counter value low byte of Timer2

1Eh T3Control Control of Timer3

1Fh T3ReloadHi High byte of the reload value of Timer3

20h T3ReloadLo Low byte of the reload value of Timer3

21h T3CounterValHi Counter value high byte of Timer3

22h T3CounterValLo Counter value low byte of Timer3

23h T4Control Control of Timer4

24h T4ReloadHi High byte of the reload value of Timer4

25h T4ReloadLo Low byte of the reload value of Timer4

26h T4CounterValHi Counter value high byte of Timer4

27h T4CounterValLo Counter value low byte of Timer4

28h DrvMod Driver mode register

29h TxAmp Transmitter amplifier register

2Ah DrvCon Driver configuration register

2Bh Txl Transmitter register

2Ch TxCrcPreset Transmitter CRC control register, preset value

2Dh RxCrcPreset Receiver CRC control register, preset value

2Eh TxDataNum Transmitter data number register

2Fh TxModWidth Transmitter modulation width register

30h TxSym10BurstLen Transmitter symbol 1 + symbol 0 burst length register

31h TXWaitCtrl Transmitter wait control

32h TxWaitLo Transmitter wait low

33h FrameCon Transmitter frame control

34h RxSofD Receiver start of frame detection

35h RxCtrl Receiver control register

36h RxWait Receiver wait register

37h RxThreshold Receiver threshold register

38h Rcv Receiver register

39h RxAna Receiver analog register

3Ah RFU -

3Bh SerialSpeed Serial speed register

3Ch LFO_Trimm Low-power oscillator trimming register

Table 48. CLRC663 registers overview …continued

Address Register name Function

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3Dh PLL_Ctrl IntegerN PLL control register, for microcon troller clock output adjustment

3Eh PLL_DivOut IntegerN PLL control register, for microcon troller clock output adjustment

3Fh LPCD_QMin Low-power card detection Q channel minimum threshold

40h LPCD_QMax Low-power card detection Q channel maximum threshold

41h LPCD_IMin Low-p ower card detection I channel minimum threshold

42h LPCD_I_Result Low-power card detection I channel result register

43h LPCD_Q_Resul t Low-power card detection Q channel result register

44h PadEn PIN enable register

45h PadOut PIN out register

46h PadIn PIN in register

47h SigOut Enables and controls the SIGOUT Pin

48h TxBitMod Transmitter bit mode register

49h RFU -

4Ah TxDataCon Transmitter data configuration register

4Bh TxDataMod Transmitter data modulation register

4Ch TxSymFreq Transmitter symbol frequency

4Dh TxSym0H Transmitter symbol 0 high register

4Eh TxSym0L Transmitter symbol 0 low register

4Fh TxSym1H Transmitter symbol 1 high register

50h TxSym1L Transmitter symbol 1 low register

51h TxSym2 Transmitter symbol 2 register

52h TxSym3 Transmitter symbol 3 register

53h TxSym10Len Transmitter symbol 1 + symbol 0 length register

54h TxSym32Len Transmitter symbol 3 + symbol 2 length register

55h TxSym10BurstCtrl Transmitter symbol 1 + symbol 0 burst control register

56h TxSym10Mod Transmitter symbol 1 + symbol 0 modulation register

57h TxSym32Mod Transmitter symbol 3 + symbol 2 modulation register

58h RxBitMod Receiver bit modulation register

59h RxEofSym Receiver end of frame symbol register

5Ah RxSyncValH Receiver synchronisation value high register

5Bh RxSyncValL Receiver synchronisation value low register

5Ch RxSyncMod Receiver synchronisation mode register

5Dh RxMod Receiver modulati on reg i ste r

5Eh RxCorr Receiver correlation regist er

5Fh FabCal Calibration register of the receiver, calibratio n performed at production

7Fh Version Version and subversion register

Table 48. CLRC663 registers overview …continued

Address Register name Function

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8.2 Command configuration

8.2.1 Command

Starts and stops command execution.

8.3 SAM configuration register

8.3.1 HostCtrl

Via the HostCtrl Register the interface access right can be controlled

Ta ble 49. Comm and register (address 00h)

Bit 7 6 5 4 3 2 1 0

Symbol Standby Modem

Off RFU Command

Access

rights dy r/w - dy

Ta ble 50. Command bits

Bit Symbol Description

7 Standby Set to 1, the IC is entering power-down mode.

6 ModemOff Set to logic 1, the receiver and the transmitter circuit is powering down.

5RFU -

4 to 0 Command Defines the actual command for the CLRC663.

Table 51. HostCtrl register (address 01h);

Bit 7 6 5 4 3 2 1 0

Symbol RegEn BusHost BusSAM RFU SAMInterface SAMInterface RFU RFU

Access

rights dy r/w r/w - r/w r/w - -

Ta ble 52. HostCtrl bits

Bit Symbol Description

7 RegEn If this bit is set to logic 1, the register HostCtrl_reg can be changed at

the next regist er access. The next write access clears this bit

automatically.

6 BusHost Set to logic 1, the bus is controlled by the host. This bit cannot be set

together with the bit BusSAM. This bit can only be set if the bit RegEn

is previously set.

5 BusSAM Set to logic 1, the bus is controlled by the SAM. This bit cannot be set

together with BusHost. This bit can only be set if the bit RegEn is

previously set.

4RFU -

3 to 2 SAMInte rface 0h:SAM Interface switch ed off

1h:SAM Interface SPI active

2h:SAM Interface I2CL active

3h:SAM Interface I2C active

1 to 0 RFU -

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8.4 FIFO configuration register

8.4.1 FIFOControl

FIFOControl defines the characteristics of the FIFO

8.4.2 WaterLevel

Defines the leve l for FIFO under- and overflow warning level s.This register is exten ded by

1 bit in FIFOControl in case the 512-byte FIFO mode is activated by se tting bit

FIFOControl.FIFOSize.

Table 53. FIFOControl register (address 02h);

Bit 7 6 5 4 3 2 1 0

Symbol FIFOSize HiAlert LoAlert FIFOFlush RFU WaterLevel

ExtBit FIFOLengthExtBits

Access

rights r/w r r w - r/w r

Ta ble 54. FIFOControl bits

Bit Symbol Description

7 FIFOSize Set to logic 1, FIFO size is 255 bytes;

Set to logic 0, FIFO size is 512 bytes.

It is recommended to change the FIFO size onl y, when the FIFO

content had been cleared.

6 HiAlert Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following equation:

HiAlert = (FIFOSize - FIFOLength) <= WaterLevel

5 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following conditions:

LoAlert =1 if FIFOLength <= WaterLevel

4 FIFOFlush Set to logic 1 clears the FIFO buffer. Reading this bit will always

return 0

3RFU -

2 WaterLevelExtBit Defines the bit 8 (MSB) for the waterlevel (extension of register

WaterLevel). This bit is only evaluated in the 512-byte FIFO mode.

Bits 7..0 are defined in register WaterLevel.

1 to 0 FIFOLengthExtBits Defines the bit9 (MSB) a nd bit8 for the FIFO length (extension of

FIFOLength). These two bits are only evaluated in the 512-byte

FIFO mode, The bits 7..0 are defined in register FIFOLength.

Table 55. WaterLevel register (address 03h);

Bit 76543210

Symbol WaterLevelBits

Access

rights r/w r/w r/w r/w r/w r/w r/w r/w

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Ta ble 56. WaterLevel bits

Bit Symbol Description

7 to 0 WaterLevelBits Sets a level to indicate a FIFO-buffer state which can be read from

bits HighAlert and LowAlert in the FifoControl. In 512-byte FIFO

mode, the register is extended by bit WaterLevelExtBit in the

FIFOControl. This functionality can be used to avoid a FIFO buffer

overflow or underflow:

The bit HiAlert bit in FIFO Control is read logic 1, if the number of

bytes in the FIFO-buffer is equal or less than the number defined by

the waterlevel configuration.

The bit LoAlert bit in FIFO control is read logic 1, if the number of

bytes in the FIFO buffer is equal or less than the number defined by

the waterlevel configuration.

Note: For the calculation of HiAle rt and LoAlert see register

description of these bits (Section 8.4.1 “FIFOControl”).

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8.4.3 FIFOLength

Number of bytes in the FIFO buffer. In 512-byte mode this register is extended by

FIFOControl.FifoLength.

8.4.4 FIFOData

In- and output of FIFO buffer. Contrary to any read/write access to other addresses,

reading or writing to the FIFO address does not increment the address pointer. Writing to

the FIFOData r egister increment s, reading decrement s the number of bytes presen t in the

FIFO.

8.5 Interrupt configuration registers

The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid

the unintended modification of bits.

The mechanism of changing register contents requires the following consideration:

IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on

the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets the

corresponding bit. With this register the application can modify the interr upt status which

is maintained by the CLRC663.

Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written

to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7.

Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt

request register

Table 57. FIFOLength register (add ress 04h); reset value: 00h

Bit 76543210

Symbol FIFOLength

Access

rights dy

Table 58. FIFOLength bits

Bit Symbol Description

7 to 0 FIFOLength Indicates the number of bytes in the FIFO buffer . In 512-byte mode this

decrements the number of available bytes in the FIFO.

Table 59. FIFOData register (address 05h);

Bit 7 6 5 4 3 2 1 0

Symbol FIFOData

Access

rights dy dy dy dy dy dy dy dy

Ta ble 60. FIFOData bits

Bit Symbol Description

7 to 0 FIFOData Data input and output port for the internal FIFO buffer . Refer to Section

7.5 “Buffer”.

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8.5.1 IRQ0 register

Interrupt request register 0.

8.5.2 IRQ1 register

Interrupt request register 1.

Table 61. IRQ0 reg ister (address 06h); reset value: 00h

Bit 7 6 5 4 3 2 1 0

Symbol Set Hi AlertIRQ Lo

AlertIRQ IdleIRQ TxIRQ RxIRQ ErrIRQ RxSOF

IRQ

Access

rights wdydydy dy dy dydy

Ta ble 62. IRQ0 bits

Bit Symbol Description

7 Set 1: writing a 1 to a bit position 6..0 sets the interrupt request

0: Writing a 1 to a bit position 6..0 clears the interrupt re quest

6 HiAlerIRQ Set, when bit HiAlert in register Status1Reg is set. In oppositio n to HiAlert,

HiAlertIRQ stores this event.

5 LoAlertIRQ Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,

LoAlertIRQ stores this event.

4 IdleIRQ Set, when a command terminates by itself e.g. when the Command changes

its value from any command to the Idle command. If an unknown command

is started, the Command changes its content to the idle state and the bit

IdleIRQ is set. Starting the Idle command by the Controller does not set bit

IdleIRQ. .

3 TxIRQ Set, when data transmission is completed, which is immediately after the last

bit is sent.

2 RxIRQ Set, when the receiver detects the end of a data stream.

Note: This flag is no indication that the received data stream is correct. The

error flags have to be evaluated to get the status of the reception.

1 ErrIRQ Set, when the one of the following errors is set:

FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.

0 RxSOFlrq Set, when a SOF or a subcarrier is detected.

Table 63. IRQ1 register (address 07h)

Bit 7 6 5 4 3 2 1 0

Symbol Set GlobalIRQ LPCD_IRQ Timer4IRQ Timer3IRQ Timer2IRQ Timer1IRQ Timer0IRQ

Access

rights wdydydy dy dy dydy

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8.5.3 IRQ0En register

Interrupt re qu es t en ab le re gister for IRQ0. This register allows to define if an interrupt

request is processed by the CLRC663.

Ta ble 64. IRQ1 bits

Bit Symbol Description

7 Set 1: writing a 1 to a bit position 5..0 sets the interrupt request

0: Writing a 1 to a bit position 5..0 clears the interrupt re quest

6 GlobalIRQ Set, if an enabled IRQ occurs.

5 LPCD_IRQ Set if a card is detected in Low-power card detection sequence.

4 Timer4IRQ Set to logic 1 when Timer4 has an underflow.

3 Timer3IRQ Set to logic 1 when Timer3 has an underflow.

2 Timer2IRQ Set to logic 1 when Timer2 has an underflow.

1 Timer1IRQ Set to logic 1 when Timer1 has an underflow.

0 Timer0IRQ Set to logic 1 when Timer0 has an underflow.

Table 65. IRQ0En register (address 08h)

Bit 7 6 5 4 3 2 1 0

Symbol IRQ_Inv Hi AlertIRQEn LoAlertIRQEn IdleIRQEn TxIRQEn RxIRQEn ErrIRQEn RxSOFIRQE

Access

rights r/w r/w r/w r/w r/w r/w r/w r/w

Ta ble 66. IRQ0 En bits

Bit Symbol Description

7 IRQ_Inv Set to one the signal of the IRQ pin is inverted

6 Hi AlerIRQEn Set to logic 1, it allows the High Alert interrupt Request (indicated by the

bit HiAlertIRQ) to be propagated to the GlobalIRQ

5 Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the

bit LoAlertIRQ) to be propagated to the GlobalIRQ

4 IdleIRQEn Set to logic 1, it allows the Idle interrupt request (indicated by the bit

IdleIRQ) to be propagated to the GlobalIRQ

3 TxIRQEn Set to logic 1, it allows the transmitter interrupt request (indicated by the

bit TxtIRQ) to be propagated to the GlobalIRQ

2 RxIRQEn Set to logic 1, it allows the receiver interrupt re quest (indicated by the bit

RxIRQ) to be propagated to the GlobalIRQ

1 ErrIRQEn Set to logic 1, it allows the Error interrupt request (ind icated by the bit

ErrorIRQ) to be propagated to the GlobalIRQ

0 RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit

RxSOFIRQ) to be propagated to the GlobalIRQ

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8.5.4 IRQ1En

Interrupt request enable register for IRQ1.

Table 67. IRQ1EN register (address 09h);

Bit 7 6 5 4 3 2 1 0

Symbol IRQPushPul

lIRQPinEn LPCD_IRQE

nTimer4IRQE

nTimer3IRQE

nTimer2IRQE

nTimer1IRQE

nTimer0IRQE

Access

rights r/w r/w r/w r/w r/w r/w r/w r/w

Table 68. IRQ1EN bits

Bit Symbol Description

7 IRQPushPull Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as

OpenDrain pin

6 IRQPinE N Set to logic 1, it allows the global interrupt request (indicated by the bit

GlobalIRQ) to be propagated to the interrupt pin

5 LPCD_IR QEN Set to logic 1, it al lows the LPCDinterrupt request (indicated by the bit

LPCDIRQ) to be propagated to the GlobalIRQ

4 Timer4IRQEn Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit

Timer4IRQ) to be propagated to the GlobalIRQ

3 Timer3IRQEn Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit

Timer3IRQ) to be propagated to the GlobalIRQ

2 Timer2IRQEn Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit

Timer2IRQ) to be propagated to the GlobalIRQ

1 Timer1IRQEn Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit

Timer1IRQ) to be propagated to the GlobalIRQ

0 Timer0IRQEn Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit

Timer0IRQ) to be propagated to the GlobalIRQ

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8.6 Contactless interface configuration registers

8.6.1 Error

Error register.

Table 69. Err or register (address 0Ah)

Bit 7 6 5 4 3 2 1 0

Symbol EE_Err FiFoWrErr FIFOOvl MinFrameErr NoDataErr CollDet ProtErr IntegErr

Access

rights dy dy dy dy dy dy dy dy

Ta ble 70. Error bits

Bit Symbol Description

7 EE_Err An error appeared during the last EEPROM command. For

details see the descriptions of the EEPROM commands

6 FIFOWrErr Data was written into the FIFO, during a transmission of a possible CRC,

during "RxWait", "Wait for data" or "Receiving" state, or during an

authentication command. The Flag is cleared when a new CL command is

started. If RxMultiple is active, the flag is cleared after the error flags have

been written to the FIFO.

5 FIFOOvl Dat a is written into the FIFO when it is already full. The data that is already in

the FIFO will remain untouched. All data that is written to the FIFO after this

Flag is set to 1 will be ignored.

4Min

FrameErr A valid SOF was received, but afterwards less then 4 bits of data were

received.

Note: Frames with less than 4 bits of dat a are automatically discarded and the

RxDecoder stays enabled. Furthermore no RxIRQ is set. The same is valid for

less than 3 Bytes if the EMD suppression is activated

Note: MinFrameErr is automatically cleared at the start of a receive or

transceive command. In case of a transceive command, it is cleared at the

start of the receiving phase ("Wait for data" state)

3 NoDataErr Data should be sent, but no data is in FIFO

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8.6.2 Status

Status register.

2 CollDet A collision has occurred. The position of the first collision is shown in the

Note: CollDet is automatically cleared at the start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.

1 ProtErr A protocol error has occurred. A protocol error can be a wrong stop bit, a

missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of

received data bytes. When a protocol error is detected, data reception is

stopped.

Note: ProtErr is automatically cleared at start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: When a pr ot oco l erro r occurs th e last received data byte is not written

into the FIFO.

0 IntegErr A data integ r i ty erro r ha s be e n de t ect ed . Possible cause can be a wrong

parity or a wrong CRC. In case of a data integrity error the reception is

continued.

Note: IntegErr is automatically cleared at start of a Receive or Transceive

command. In case of a Transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: If the NoColl bit is set, also a collision is setting the IntegErr.

Ta ble 70. Error bits

Bit Symbol Description

Table 71. Status register (address 0Bh)

Bit 76543210

Symbol - - Crypto1On - - ComState

Access

rights RFU RFU dy RFU RFU r

Table 72. Status bits

Bit Symbol Description

7to 6 - RFU

5 Crypto1On Indicates if the MIFARE Crypto is on. Clearing this bit is switching the

MIFARE Crypto off. The bit can only be set by the MFAuthent command.

4to3 - RFU

2 to 0 ComState ComState shows the status of the transmitter and receiver state machine:

000b ... Idle

001b ... TxWait

011b ... T ransmitting

101b ... RxWait

110b ... Wait for data

111b ... Receiving

100b ... not used

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8.6.3 RxBitCtrl

Receiver control register.

Table 73. RxBitCtrl reg ister (address 0Ch);

Bit 7 6 5 4 3 2 1 0

Symbol ValuesAfterColl RxAlign NoColl RxLastBits

Access

rights r/w r/w r/w r/w r/w w w w

Table 74. RxBitCtrl bits

Bit Symbol Description

7 ValuesAfter

Coll If cleared, every received bit after a collision is replaced by a zero. This

function is needed for ISO/IEC14443 anticollision

6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position

length for the first bit received to be stored. Further received bits are

stored at the following bit positions.

Example:

RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second

received bit is stored at bit position 1.

RxAlign = 1h - the LSB of the received bit is stored at bit 1, the second

received bit is stored at bit position 2.

RxAlign = 7h - the LSB of the received bit is stored at bit 7, the second

received bit is stored in the following byte at positi on 0.

Note: If RxAlign = 0, data is received byte-oriented, otherwise

bit-oriented.

3 NoColl If this bit is set, a collision will result in an IntegErr

2 to 0 RxLastBits Defines the number of valid bits of the last data byte received in

bit-oriented communications. If zero the whole byte is valid.

Note: These bits are set by the RxDecoder in a bit-oriented

communication at the end of the communication. They are reset at start

of reception.

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8.6.4 RxColl

Receiver collision register.

Table 75. RxColl register (address 0Dh);

Bit 7 6 5 4 3 2 1 0

Symbol CollPosValid CollPos

Access

rights rr

Table 76. RxColl bits

Bit Symbol Description

7 CollPos

Valid If set to 1, the value of CollPos is valid. Otherwise no collision is detected or

the position of the collision is out of the range of bits CollPos.

6 to 0 CollPos These bits show the bit position of the first detected collision in a received

frame (only da ta bits are interprete d ) . Co l l P os can only be displa ye d fo r the

first 8 bytes of a data stream.

Example:

00h indicates a bit collision in the 1st bit

01h indicates a bit collision in the 2nd bit

08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)

3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)

These bits shall only be interpreted in Passive communication mode at 10 6

kbit/s or ISO/IEC 14443A/MIFAR E reader /writer mode or

ISO/IEC 15693/ICODE SLI read/write mode if bit CollPosValid is set.

Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is included

in the CollPos.

Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is the

last bit of that UID byte). The CollPos = 7h in this case.

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8.7 T imer configuration registers

8.7.1 TControl

Control register of the timer section.

The TControl implements a special functionality to avoid the not intended modification of

bits.

Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified.

Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4

8.7.2 T0Control

Control register of the Timer0.

Table 77. TCon trol register (address 0Eh )

Bit 7 6 5 4 3 2 1 0

Symbol T3Running T2Running T1Running T0Running T3Start

StopNow T2Start

StopNow T1Start

StopNow T0Start

StopNow

Access

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Table 78. TControl bits

Bit Symbol Description

7 T3Running Indicates Timer3 is running.If the bit T3startStopNow is set/reset, this

bit and the timer can be started/stopped

6 T2Running Indicates Timer2 is running. If the bit T2startStopNow is set/reset, this

bit and the timer can be started/stopped

5 T1Running Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this

bit and the timer can be started/stopped

4 T0Running Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this

bit and the timer can be started/stopped

3T3StartStop

Now The bit 7 of TControl T3Runni ng can be modified if set

2T2StartStop

Now The bit 6of TCon tro l T2Running can be modifie d if set

1T1StartStop

Now The bit 5of TCon tro l T1Running can be modifie d if set

0T0StartStop

Now The bit 4 of TControl T0Runni ng can be modified if set

Table 79. T0Contro l register (address 0Fh);

Bit 7 6 5 4 3 2 1 0

Symbol T0StopRx - T0Start T0AutoRestart - T0Clk

Access

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8.7.2.1 T0ReloadHi

High byte reload valu e of the Timer0.

8.7.2.2 T0ReloadLo

Low byte reload value of th e Timer0.

Table 80. T0Contro l bits

Bit Symbol Description

7 T0S topRx If set, the timer stops immediately after receiving the first 4 bits. If

cleared the timer does not stop automatically.

Note: If LFO Trimming is selecte d by T0Start, this bit has no effect.

6- RFU

5 to 4 T0Start 00b: Th e timer is not started automati cally

01b: The timer starts automatically at the end of the transmission

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

3 T0AutoRestart 1: the timer automatically restarts its count-down from T0ReloadValue,

after the counter value has reached the value zero.

0: the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2- RFU

1 to 0 T0Clk 00b: The timer input clock is 13.56 MHz.

01b: The timer input clock is 211,875 kHz.

10b: The timer input clock is an underflow of Timer2.

11b: The timer input clock is an underflow of Timer1.

Table 81. T0Relo adHi register (address 10h);

Bit 7 6 5 4 3 2 1 0

Symbol T0Reload Hi

Access

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Table 82. T0ReloadHi bits

Bit Symbol Description

7 to 0 T0ReloadHi Defines the high byte of the reload value of the timer. With the start

event the timer loads the value of the registers T0ReloadValHi,

T0ReloadValLo. Changing this register affects the timer only at the

next start event.

Table 83. T0Relo adLo register (address 11h);

Bit 7 6 5 4 3 2 1 0

Symbol T0ReloadLo

Access

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8.7.2.3 T0CounterValHi

High byte of the counter value of Timer0.

8.7.2.4 T0CounterValLo

Low byte of the counter value of Timer0.

8.7.2.5 T1Control

Control register of the Timer1.

Table 84. T0ReloadLo bits

Bit Symbol Description

7 to0 T0ReloadLo Defines the low byte of the reload value of the timer. With the start

event the timer loads the value of the T0ReloadV alHi, T0ReloadValLo.

Changing this register affects the timer only at the next start event.

Table 85. T0CounterValHi register (address 12h)

Bit 7 6 5 4 3 2 1 0

Symbol T0CounterValHi

Access

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Ta ble 86. T0 CounterValHi bits

Bit Symbol Description

7to0 T0Counter

ValHi High byte value of the Timer0.

This value shall not be read out during reception.

Table 87. T0Co unterValLo register (address 13h)

Bit 7 6 5 4 3 2 1 0

Symbol T0CounterValLo

Access

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Ta ble 88. T0CounterValL o bits

Bit Symbol Description

7 to 0 T0CounterValLo Low byte value of the T imer0.

This value shall not be read out during reception.

Table 89. T1Contro l register (address 14h);

Bit 7 6 5 4 3 2 1 0

Symbol T1StopRx - T1Start T1AutoRestart - T1Clk

Access

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8.7.2.6 T1ReloadHi

High byte (MSB) reload value of the Timer1.

8.7.2.7 T1ReloadLo

Low byte (LSB) reload value of the Timer1.

Table 90. T1Contro l bits

Bit Symbol Description

7 T1S topRx If set, the timer stops after receiving the first 4 bits. If cleared, the timer

is not stopped automatically.

Note: If LFO trimming is selected by T1start, this bit has no effect.

6- RFU

5 to 4 T1Start 00b: Th e timer is not started automati cally

01b: The timer starts automatically at the end of the transmission

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

3 T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T1ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2- RFU

1 to 0 T1Clk 00b: The timer input clock is 13.56 MHz

01b: The timer input clock is 211,875 kHz.

10b: The timer input clock is an underflow of Timer0

11b: The timer input clock is an underflow of Timer2

Table 91. T0Relo adHi register (address 15h )

Bit 7 6 5 4 3 2 1 0

Symbol T1ReloadHi

Access

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Table 92. T1ReloadHi bits

Bit Symbol Description

7 to 0 T1Rel oadHi Defines the high byte reload value of the Timer 1. With the start event

the timer loads the value of the T1Reloa dValHi and T1ReloadValLo.

Changing this register affects the Timer only at the next start event.

Table 93. T1ReloadLo register (address 16h)

Bit 7 6 5 4 3 2 1 0

Symbol T1ReloadLo

Access

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8.7.2.8 T1CounterValHi

High byte (MSB) of the counter value of byte Timer1.

8.7.2.9 T1CounterValLo

Low byte (LSB) of the counter value of byte Timer1.

8.7.2.10 T2Control

Control register of the Timer2.

Ta ble 94. T1 ReloadValLo bits

Bit Symbol Description

7 to 0 T1Rel oadLo Defines the low byte of the reload value of the Timer1. Changing this

Table 95. T1CounterValHi register (address 17h)

Bit 7 6 5 4 3 2 1 0

Symbol T1CounterValHi

Access

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Ta ble 96. T1 CounterValHi bits

Bit Symbol Description

7 to 0 T1Counter

ValHi High by te of th e current value of the Timer1.

This value shall not be read out during reception.

Table 97. T1Co unterValLo register (address 18h)

Bit 7 6 5 4 3 2 1 0

Symbol T1CounterValLo

Access

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Ta ble 98. T1CounterValL o bits

Bit Symbol Description

7 to 0 T1Counter

ValLo Low byte of the current value of the counter 1.

This value shall not be read out during reception.

Table 99. T2Co ntro l register (address 19h)

Bit 7 6 5 4 3 2 1 0

Symbol T2StopRx - T2Start T2AutoRestart - T2Clk

Access

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8.7.2.11 T2ReloadHi

High byte of the reload value of Timer2.

8.7.2.12 T2ReloadLo

Low byte of the reload value of Timer2.

Table 100. T2Control bits

Bit Symbol Description

7 T2StopRx If set the timer stops immediately after receiving the first 4 bits. If

cleared indicates, that the timer is not stopped automatically.

Note: If LFO Trimming is selecte d by T2Start, this bit has no effect.

6- RFU

5 to 4 T2Start 00 b: The timer is not started automatically.

01b: The timer starts automatically at the end of the transmission.

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge).

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

3 T2AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T2ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops. The bit

Timer2IRQ is set to logic 1 when the timer underflows

2- RFU

1 to 0 T2Clk 00b: The timer input clock is 13.56 MHz.

01b: The timer input clock is 212 kHz.

10b: The timer input clock is an underflow of Timer0

11b: The timer input clock is an underflow of Timer1

Table 101. T2ReloadHi reg ister (address 1Ah)

Bit 7 6 5 4 3 2 1 0

Symbol T2ReloadHi

Access

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Table 102. T2Reload bi ts

Bit Symbol Description

7 to 0 T2ReloadHi Defines the high byte of the reload value of the Timer2. With the start

event the timer load the value of the T2ReloadValHi and

T2ReloadValLo. Changing this register affects the timer only at the

next start event.

Table 103. T2ReloadL o re gister (address 1Bh)

Bit 7 6 5 4 3 2 1 0

Symbol T2ReloadLo

Access

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8.7.2.13 T2CounterValHi

High byte of the coun te r re gis te r of Timer2.

8.7.2.14 T2CounterValLoReg

Low byte of the current value of Timer 2.

8.7.2.15 T3Control

Control register of the Timer 3.

Table 104. T2ReloadL o bits

Bit Symbol Description

7 to 0 T2ReloadLo Defines the low byte of the reload value of the Timer2. With the start

event the timer load the value of the T2ReloadValHi and

T2RelaodV aLo. Changing this register affects the timer only at the next

start event.

Table 105. T2CounterValHi register (address 1Ch)

Bit 7 6 5 4 3 2 1 0

Symbol T2CounterValHi

Access

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Table 106. T2CounterValHi bits

Bit Symbol Description

7 to 0 T2Counter

ValHi High byte current counter value of Timer2.

This value shall not be read out during reception.

Table 107. T2CounterValLo register (address 1Dh)

Bit 7 6 5 4 3 2 1 0

Symbol T2CounterValLo

Access

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Table 108. T2CounterValLo bits

Bit Symbol Description

7to0 T2Counter

ValLo Low byte of the current counter value of Timer1Timer2.

This value shall not be read out during reception.

Table 109. T3Control register (address 1Eh)

Bit 7 6 5 4 3 2 1 0

Symbol T3StopRx - T3Start T3AutoRestart - T3Clk

Access

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8.7.2.16 T3ReloadHi

High byte of the reload value of Timer3.

8.7.2.17 T3ReloadLo

Low byte of the reload value of Timer3.

Table 110. T3Control bits

Bit Symbol Description

7 T3S topRx If set, the timer stops immediately after receiving the first 4 bits. If

cleared, indicates that the timer is not stopped automatically.

Note: If LFO Trimming is selecte d by T3Start, this bit has no effect.

6- RFU

5 to 4 T3Start 00b - timer is not started automatically

01b - timer starts automatically at the end of the transmission

10b - timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b - timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

3 T3AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T3ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2- RFU

1 to 0 T3Clk 00b - the timer input clock is 13.56 MHz.

01b - the timer input clock is 211,875 kHz.

10b - the timer input clock is an underflow of Timer0

11b - the timer input clock is an underflow of T i mer1

Table 111. T3ReloadHi register (address 1F h);

Bit 7 6 5 4 3 2 1 0

Symbol T3ReloadHi

Access

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Table 112. T3ReloadHi bits

Bit Symbol Description

7 to 0 T3ReloadHi Defines the high byte of the reload value of the Timer3. With the start

event the timer load the value of the T3ReloadValHi and

T3ReloadValLo. Changing this register affects the timer only at the

next start event.

Table 113. T3ReloadLo register (address 20h)

Bit 7 6 5 4 3 2 1 0

Symbol T3ReloadLo

Access

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8.7.2.18 T3CounterValHi

High byte of the curr en t co un te r valu e the 16 -b it Timer3.

8.7.2.19 T3CounterValLo

Low byte of the current counter value the 16-bit Timer3.

8.7.2.20 T4Control

The wake-up timer T4 activates the system after a given time. If enabled, it can start the

low power card detection function.

Table 114. T3Reloa dLo bits

Bit Symbol Description

7 to 0 T3ReloadLo Defines the low byte of the reload value of T imer3. With the start event

the timer load the value of th e T3ReloadValHi and T3RelaodValLo.

Changing this register affects the timer only at the next start event.

Table 115. T3CounterValHi register (address 21h)

Bit 7 6 5 4 3 2 1 0

Symbol T3CounterValHi

Access

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Ta ble 116. T3CounterValHi bits

Bit Symbol Description

7 to 0 T3Counter

ValHi High byte of the current counter value of Timer3.

This value shall not be read out during reception.

Table 117. T3CounterValLo register (address 22h )

Bit 7 6 5 4 3 2 1 0

Symbol T3CounterValLo

Access

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Ta ble 118. T3Cou nterValLo bits

Bit Symbol Description

7 to 0 T3Counter

ValLo Low byte current counter value of Timer3.

This value shall not be read out during reception.

Table 119. T4Control register (address 23h)

Bit 7 6 5 4 3 2 1 0

Symbol T4Running T4Start

StopNow T4Auto

Trimm T4Auto

LPCD T4Auto

Restart T4AutoWakeUp T4Clk

Access

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8.7.2.21 T4ReloadHi

High byte of the relo ad valu e of the 16 -b it tim er 4.

8.7.2.22 T4ReloadLo

Low byte of the reload value of the 16-bit timer 4.

Table 120. T4Control bits

Bit Symbol Description

7 T4Running Shows if the timer T4 is running. If the bit T4S tartStopNow is set, this

bit and the timer T4 can be started/stopped.

6T4Start

StopNow if set, the bit T4Running can be changed.

5 T4AutoTrimm If set to one, the timer activates an LFO trim ming procedure when it

underflows. For the T4AutoTrimm function, at least one timer (T0 to

T3) has to be configured properly for trimming (T3 is not allowed if

T4AutoLPCD is set in parallel).

4 T4AutoLPCD If set to one, the timer activates a low-power card detection

sequence. If a card is detected an interrupt request is raised and the

system remains active if enabled. If no card is detected the CLRC663

enters the Power down mode if enabled. The timer is automatically

restarted (no gap). Time r 3 is used to specify the time where the RF

field is enabled to check if a card is present. Therefor you may not

use Timer 3 for T4AutoTrimm in parallel.

3 T4AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T4ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops. The bit

Timer4IRQ is set to logic 1 at timer underflow.

2 T4AutoWak eUp If set, the CLRC663 wakes up automati cally, when the timer T4 has

an underflow. This bit has to be set if the IC should enter th e Power

down mode after T4AutoTrimm and/or T4AutoLPCD is finished and

no card has been detected. If the IC should stay active after one of

these procedures this bit has to be set to 0.

1 to 0 T4Clk 00b - the timer input clock is the LFO clock

01b - the timer input clock is the LFO clock/8

10b - the timer input clock is the LFO clock/16

11b - the timer input clock is the LFO clock/32

Table 121. T4ReloadHi reg ister (address 24h)

Bit 7 6 5 4 3 2 1 0

Symbol T4ReloadHi

Access

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Table 122. T4ReloadHi bits

Bit Symbol Description

7 to 0 T4ReloadHi Defines high byte of the for the reload value of timer 4. With the start

event the timer 4 loads the T4ReloadV a l. Changing this register affects

the timer only at the next start event.

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8.7.2.23 T4CounterValHi

High byte of the counter value of the 16-bit timer 4.

8.7.2.24 T4CounterValLo

Low byte of the counter value of the 16-bit timer 4.

Table 123. T4ReloadLo re gister (address 25h)

Bit 7 6 5 4 3 2 1 0

Symbol T4ReloadLo

Access

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Table 124. T4ReloadL o bits

Bit Symbol Description

7 to 0 T4ReloadLo Defines the low byte of the reload value of the timer 4. With the start

event the timer loads the value of the T4ReloadVal. Changing this

Table 125. T4CounterValHi register (address 26h)

Bit 7 6 5 4 3 2 1 0

Symbol T4CounterValHi

Access

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Table 126. T4CounterValHi bits

Bit Symbol Description

7 to 0 T4CounterValHi High byte of the current counter value of timer 4.

Table 127. T4CounterValLo register (address 27h)

Bit 7 6 5 4 3 2 1 0

Symbol T4CounterValLo

Access

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Table 128. T4CounterValLo bits

Bit Symbol Description

7 to 0 T4Co unterValLo Low byte of the current counter value of the timer 4.

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8.8 Transmitter configuration registers

8.8.1 TxMode

8.8.2 TxAmp

With the set_cw_amplitude register output power can be traded off against power supply

rejection. Spending more headroom leads to better power supply rejection ration and

better accuracy of the modulation degree.

With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register

overrides the settings made by set_cw_amplitude.

Table 129. DrvMode register (address 28h)

Bit 7 6 5 4 3 2 1 0

Symbol Tx2Inv Tx1Inv - - TxEn TxClk Mode

Access

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Table 130. DrvMode bits

Bit Symbol Description

7 Tx2Inv Inverts transmitter 2 at TX2 pin

6 Tx1Inv Inverts transmitter 1 at TX1 pin

5RFU

4- RFU

3 TxEn If set to 1 both tran smitter pins are enabled

2 to 0 TxClkMode Transmitter clock settings (see 8.6.2. Tab le 27). Codes 011b and

0b110 are not supported. This register defines, if the output is

operated in open drain, push-pull, at high impedance or pulled to a fix

high or low level.

Table 131. TxAmp register (address 29h )

Bit 7 6 5 4 3 2 1 0

Symbol set_cw_amplitude - set_residual_carrier

Access

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Ta ble 132. TxAmp bits

Bit Symbol Description

7 to 6 set_cw_amplitude Allows to reduce the output amplitude of the transmitter by a fix

value.

Four different preset values that are subtracted from TVDD can

be selected:

0: TVDD -100 mV

1: TVDD -250 mV

2: TVDD -500 mV

3: TVDD -1000 mV

5RFU -

4 to 0 set_residual_ carrier Set the residual carrier percentage. refer to Section 7.6.2

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8.8.3 TxCon

8.8.4 Txl

Table 133. TxCon reg ister (address 2Ah)

Bit 7 6 5 4 3 2 1 0

Symbol OvershootT2 CwMax TxInv TxSel

Access

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Table 134. TxCon bits

Bit Symbol Description

7 to 4 OvershootT2 Specifies the length (number of carrier clocks) of the additional

modulation for overshoot prevention. Refer to Section 7.6.2.1

“Overshoot protection”

3 Cwmax Set amplitude of continuous wave carrier to the maximum.

If set, set_cw_amplitude in Regist er TxAmp has no influence on the

continuous amplitude.

2 TxInv If set, the resulting modulation signal defined by TxSel is inverted

1 to 0 TxSel Defines which signal is used as source for modulation

00b ... no modulation

01b ... TxEnvelope

10b ... SigIn

11b ... RFU

Table 135. Txl register (address 2Bh)

Bit 7 6 5 4 3 2 1 0

Symbol OvershootT1 tx_set_iLoad

Access

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Table 136. Txl bits

Bit Symbol Description

7 to 4 OvershootT1 Overshoot value for Timer1. Refer to Section 7.6.2.1 “Overshoot

protection”

3 to 0 tx_set_iLoad Factory trim value, sets the expe cted Tx load current. This value is

used to control the modulation index in an optimized way dependent

on the expected TX load current.

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8.9 CRC configuration registers

8.9.1 TxCrcPreset

Remark: User defined CRC preset values can be configured by EEprom (see

Section 7.7.2.1, Table 36 “Configuration area (Page 0)”).

Table 137. TXCrcPreset register (address 2Ch)

Bit 7 6 5 4 3 2 1 0

Symbol RFU TXPresetVal TxCRCtype TxCRCInvert TxCRCEn

Access

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Table 138. TxCrcPreset b its

Bit Symbol Description

7RFU -

6 to 4 TXPresetVal Specifies the CRC preset value for transmission (see Table 139).

3 to 2 TxCRCtype Defines whic h type of CRC (CRC8/CRC16/CRC5) is calculated:

•00h -- CRC5

•01h -- CRC8

•02h -- CRC16

•03h -- RFU

1 TxCRCInvert if set, the resulting CRC is inverted and attached to the data frame

(ISO/IEC 3309)

0 TxCRCEn if set, a CRC is appended to the data stream

Table 139. T ransmitter CRC preset value configuration

TXPresetVal[6...4] CRC16 CRC8 CRC5

0h 0000h 00h 00h

1h 6363h 12h 12h

2h A671h BFh -

3h FFFEh FDh -

4h---

5h---

6h User defined User defined User defined

7h FFFFh FFh 1Fh

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8.9.2 RxCrcCon

Table 140. RxCrcCon register (address 2Dh)

Bit 7 6 5 4 3 2 1 0

Symbol RxForceCRCWrite RXPresetVal RXCRCtype RxCRCInvert RxCRCEn

Access

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Ta ble 141. RxCrcCo n bits

Bit Symbol Description

7 RxForceCrc

Write If se t, the received CRC byte(s) are copied to the FIFO.

If cleared CRC Bytes are only checked, but not copied to th e FI FO.

This bit has to be always set in case of a not byte aligned CRC (e.g.

ISO/IEC 18000-3 mode 3/ EPC Class-1HF)

6 to 4 RXPresetVal Defines the CRC preset value (Hex.) for transmission. (see Table 142).

3 to 2 RxCRCtyp e Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:

•00h -- CRC5

•01h -- CRC8

•02h -- CRC16

•03h -- RFU

1 RxCrcInvert If set, the CRC check is done for the inverted CRC.

0 RxCrcEn If set, the CRC is checked and in case of a wrong CRC an error flag is

set. Otherwise the CRC is calculated but the error flag is not modified.

Table 142. Receiver CRC pres et value configuration

RXPresetVal[6...4] CRC16 CRC8 CRC5

0h 0000h 00h 00h

1h 6363h 12h 12h

2h A671h BFh -

3h FFFEh FDh -

4h---

5h---

6h User defined User defined User defined

7h FFFFh FFh 1Fh

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8.10 Transmitter configuration registers

8.10.1 TxDataNum

8.10.2 TxDATAModWidth

Transmitter data modulation width register

Table 143. TxDataNum register (address 2Eh)

Bit 7 6 5 4 3 2 1 0

Symbol RFU RFU- RFU- KeepBitGrid DataEn TxLastBits

Access

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Ta ble 144. TxDataNum bits

Bit Symbol Description

7to5 RFU -

4 KeepBit Grid If set, th e time between consecutive transmissions starts is a multiple

of one ETU. If cleared, consecutive tran smissions can even start

within one ETU

3 DataEn If cleared - it is possible to send a single symbol pattern.

If set - data is sent.

2 to 0 TxLastBits Defines how many bits of the last data byte to be sent. If set to 000b all

bits of the last dat a byte are sent .

Note - bits are skipped at the end of the byte.

Example - Data byte B2h (sent LSB first).

TxLastBits = 011b (3h) => 010 b (LSB first) is sent

TxLastBits = 110b (6h) => 010011b (LSB first) is sent

Table 145. TxDataModWidth register (address 2Fh)

Bit 7 6 5 4 3 2 1 0

Symbol DModWidth

Access

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Ta ble 146. TxDataModWidth bits

Bit Symbol Description

7 to 0 DModWidth Sp ecifies the length of a pulse for sending data with enabl ed pulse

modulation. The length is given by the number of carrier clocks + 1.

A pulse can never be longer than from the start of the pulse to the end

of the bit. The starting position of a pulse is given by the setting of

TxDataMod.DPulseType. Note: This register is only used if Mi ller

modulation (ISO/IEC 14443A PCD) is used. The settings are also

used for the modulation width of start and/or stop symbols.

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8.10.3 TxSym10BurstLen

If a protocol requ ire s a burst (an unmodula te d s ubc a rr ier ) th e len gt h ca n be def ine d with

this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.

Table 147. TxSym10Bu rstLen register (address 30h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU Sym1Burst Len RFU Sym0Burst Len

Access

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Ta ble 148. TxSym10 BurstLen bits

Bit Symbol Description

7RFU -

6 to 4 Sym1BurstLen Specifies th e number of bits issued for symb o l 1 bu rst . Th e 3 bi ts

encodes a range from 8 to 256 bit:

00h - 8bit

01h - 16bit

02h - 32bit

04h - 48bit

05h - 64bit

06h - 96bit

07h - 128bit

08h - 256bit

3RFU -

2 to 0 Sym0BurstLen Specifies th e number of bits issued for symb o l 1 bu rst . Th e 3 bi ts

encodes a range from 8 to 256 bit:

00h - 8bit

01h - 16bit

02h - 32bit

03h - 48bit

04h - 64bit

05h - 96bit

06h - 128bit

07h - 256bit

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8.10.4 TxWaitCtrl

Table 149. TxWaitCtrl register (address 31h); reset value: C0h

Bit 7 6 5 4 3 2 1 0

Symbol TxWaitStart TxWaitEtu TxWait High TxStopBitLength

Access

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Table 150. TXWaitCtrl bits

Bit Symbol Description

7 TxWaitStart If cleared, the TxWait time is starting at the End of the send data

(TX).

If set, the TxWait time is starting at the End of the received data

(RX).

6 TxWaitEtu If cleared, the TxWait time is TxWait 16/13.56 MHz.

If set, the TxWait time is TxWait 0.5 / DBFreq (DBFreq is the

frequency of the bit stream as defined by TxDataCon).

5 to 3 TxWait High Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.

2 to 0 TxStopBitL ength Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to

be send:

0h: no stop-bit, no EGT

1h: 1 stop-bit, no EGT

2h: 1 stop-bit + 1 EGT

3h: 1 stop-bit + 2 EGT

4h: 1 stop-bit + 3 EGT

5h: 1 stop-bit + 4 EGT

6h: 1 stop-bit + 5 EGT

7h: 1 stop-bit + 6 EGT

Note: This is only valid for ISO/IEC14443 Type B

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8.10.5 TxWaitLo

8.11 FrameCon

Table 151. TxWaitLo register (address 32h)

Bit 7 6 5 4 3 2 1 0

Symbol TxWaitLo

Access

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Ta ble 152. TxWaitLo bits

Bit Symbol Description

7 to 0 TxWaitLo Defines the minimum time between receive and send or between two

send data streams

Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl

See also TxWaitEtu and TxWaitStart.

Table 153. FrameCon register (address 33h)

Bit 7 6 5 4 3 2 1 0

Symbol TxParityEn RxParityEn - - StopSym StartSym

Access

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Ta ble 154. FrameC on bits

Bit Symbol Description

7 TxParityEn If se t, a parity bit is calculated and appended to each byte

transmitted.

6 RxParityEn If set, the parity calculation is enabled. The parity is not transferred to

the FIFO.

5 to 4 - RFU

3 to 2 StopSym Defines whi ch symbol is sent as stop-symbol:

•0h: No symbol is sent

•1h: Symbol0 is sent

•2h symbol1 is sent

•3h Symbol2 is sent

1 to 0 StartSym Defines which symbol is sent as start-symbol:

•0h: No Symbol is sent

•1h: Symbol0 is sent

•2h: Symbol1 is sent

•3h: Symbol2 is sent

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8.12 Receiver configuration registers

8.12.1 RxSofD

8.12.2 RxCtrl

Table 155. RxSofD regist er (address 34h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU SOF_En SOFDetected RFU SubC_En SubC_Detected SubC_Present

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Ta ble 156. RxSofD bits

Bit Symbol Description

7 to 6 RFU -

5 SOF_En If set and a SOF is detected an RxSOFIRQ is raised.

4 SOF_Detected Shows that a SOF is or was detected. Can be cleared by SW.

3RFU -

2 SubC_En If set and a subcarrier is detected an RxSOFIRQ is raised.

1 SubC_Detected Shows that a subcarrier is or was detected. Can be cleared by SW.

0 SubC _ Present Shows that a subcarrier is curren tl y detected.

Table 157. RxCtrl register (address 35h)

Bit 7 6 5 4 3 2 1 0

Symbol RxAllowBits RxMultiple RxEOFType EGT_Check EMD_Sup Baudrate

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Ta ble 158. RxCtrl bits

Bit Symbol Description

7 RxAllowBits If set, data is written into FIFO even if CRC is enabled, and no

complete byte has been received.

6 RxMultiple If set, RxMultiple is activated and the receiver will not terminate

automatically (refer Section 7.10 .3.6 “Receive command”).

If set to logic 1, at the end of a received data stream an error byte is

added to the FIFO. The error byte is a copy of the Error register.

5 RxEOFType 0: EOF as defined in the RxEOFSymbolReg is expected.

1: ISO/IEC14443B EOF is expected.

Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the

RxEOFSymbol R e g di sa b les th e EOF che ck.

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8.12.3 RxWait

Selects internal receiver settings.

4 EGT_Check If set to 1, the EGT is checked and if it is too long

a protocol error is set. (This is only valid for ISO/IEC14443 Type B).

3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error

occurs within the first three bytes, these three bytes are assumed to be

EMD, ignored and the FIFO is reset. A collision is treated as an error

as well If a valid SOF was received, the EMD_Sup is set and a frame

of less than 3 bytes had been received. RX_IRQ is not set in this EMD

error cases. If RxForceCRCWrite is set, the FIFO should not be read

out before three bytes are written into.

2 to 0 Baudrate Defines the baud rate of the receiving signal.

2h: 26 kBd

3h: 52 kBd

4h: 106 kBd

5h: 212 kBd

6h: 424 kBd

7h: 847 kBd

all remaining values are RFU

Ta ble 158. RxCtrl bits

Bit Symbol Description

Table 159. RxWait register (address 36h)

Bit 76543210

Symbol RxWaitEtu RxWait

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Table 160. RxWait bits

Bit Symbol Description

7 RXWaitEtu If set to 0, the RxWait time is RxWait 16/13.56 MHz.

If set to 1, the RxWait time is RxWait (0.5/DBFreq).

6 to 0 RxWait Defines the time after sending, where every input is ignored.

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8.12.4 RxThreshold

Selects minimum threshold level for the bit decode r.

8.12.5 Rcv

Table 161. RxThresh old register (address 37h)

Bit 76543210

Symbol MinLevel MinLevelP

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Ta ble 162. RxThreshold bits

Bit Symbol Description

7 to 4 MinLevel Defines the MinLevel of the reception.

Note: The MinLevel should be higher than the noise level in the system.

3 to 0 MinLevelP Defines the MinLevel of th e phase shift detector unit.

Table 163. Rcv regis te r (address 38h)

Bit 7 6 5 4 3 2 1 0

Symbol Rcv_Rx_single Rx_ADCmode SigInSel RFU CollLevel

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Ta ble 164. Rcv bits

Bit Symbol Description

7 Rcv_Rx_single Single RXP Input Pin Mode;

0: Fully Differential

1: Quasi-Differential

6 Rx_ADCmode Defines the operation mode of the Analog Digital Converter (ADC)

0: normal recepti o n mode for ADC

1: LPCD mode for ADC

5 to 4 SigInSel Defines input for the signal processing unit:

0h - idle

1h - internal analog block (RX)

2h - signal in over envelope (ISO/IEC14443A)

3h - signal in over s3c-generic

3 to 2 RFU -

1 to 0 CollLevel Defines the strength of a signal to be interpreted as a collisio n:

0h - Collision has at least 1/8 of signal strength

1h - Collision has at least 1/4 of signal strength

2h - Collision has at least 1/2 of signal strength

3h - Collision detection is switched off

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8.12.6 RxAna

This register allows to set the gain (rcv_gain) and high p ass corner frequencies

(rcv_hpcf).

Table 165. RxAna register (address 39h)

Bit 7 6 5 4 3 2 1 0

Symbol VMid_r_sel RFU rcv_hpcf rcv_gain

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Table 166. RxAna bits

Bit Symbol Description

7, 6 VMid_r_sel Factory trim value, needs to be 0.

5, 4 RFU

3, 2 rcv_hpcf The rcv_hpcf [1:0] signals allow 4 different settings of the base band

amplifier high pass cut-off frequency from ~40 kHz to ~300 kHz.

1 to 0 rcv_gain With rcv_gain[1:0] four different gain settings from 30 dB and 60 dB

can be configured (differential output voltage/differential input voltage).

Table 167. Effect of gain and highpass corner register settings

rcv_gain

(Hex.) rcv_hpcf

(Hex.) fl (kHz) fU (MHz) gain (dB20) bandwith

(MHz)

03 00 38 2,3 60 2,3

03 01 79 2,4 59 2,3

03 02 150 2,6 58 2,5

03 03 264 2,9 55 2,6

02 00 41 2,3 51 2,3

02 01 83 2,4 50 2,3

02 02 157 2,6 49 2,4

02 03 272 3,0 41 2,7

01 00 42 2,6 43 2,6

01 01 84 2,7 42 2,6

01 02 157 2,9 41 2,7

01 03 273 3,3 39 3,0

00 00 43 2,6 35 2,6

00 01 85 2,7 34 2,6

00 02 159 2,9 33 2,7

00 03 276 3,4 30 3,1

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8.13 Clock configuration

8.13.1 SerialSpeed

This register allows to set speed of the RS232 interface. The default speed is set to

9,6kbit/s. The transmission speed of the interface can be changed by modifying the

entries for BR_T0 and BR_T1. The transfer speed can be calculated by using the

following formulas:

BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 1)

The framing is implemented with 1 startbit, 8 databits and 1 stop bit. A parity bit is not

used. Transfer speeds above 1228,8 kbit/s are not supported.

Table 168. SerialSpeed register (address3Bh); reset value: 7Ah

Bit 7 6 5 4 3 2 1 0

Symbol BR_T0 BR_T1

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Table 169. SerialSpeed bits

Bit Symbol Description

7 to 5 BR_T0 BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR _T0 1)

4 to 0 BR_T1 BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR _T0 1)

Ta ble 170. RS232 spe ed settings

Transfer speed (kbit/s) SerialSpeed register content (Hex.)

7,2 FA

9,6 EB

14,4 DA

19,2 CB

38,4 AB

57,6 9A

115,2 7A

128,0 74

230,4 5A

460,8 3A

921,6 1C

1228,8 15

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8.13.2 LFO_Trimm

8.13.3 PLL_Ctrl Register

The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages

exist to create the ClkOut signal from the 27,12MHz input. In the first stage the 27,12Mhz

input signal is multiplied by the value defined in PLLDiv_FB and divided by two, and the

second stage divides this frequency by the value defined by PLLDIV_Out.

Table 171. LFO_Trim register (address 3Ch)

Bit 7 6 5 4 3 2 1 0

Symbol LFO_trimm

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Table 172. LFO_Trim bits

Bit Symbol Description

7 to 0 LFO_trimm Trimm value. Refer to Section 7.8.3 “Low Frequency Oscillator (LFO)”

Note: If the trimm value is increased, the frequency of the oscillator

decreases.

Table 173. PLL_Ctrl re gister (address3Dh)

Bit 7 6 5 4 3 2 1 0

Symbol ClkOutSel ClkOut_En PLL_PD PLLDiv_FB

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Table 174. PLL_Ctrl regis t er bits

Bit Symbol Description

7 to 4 CLkOutSel •0h - pin CLKOUT is used as I/O

•1h - pin CLKOUT shows the output of the analog PLL

•2h - pin CLKOUT is hold on 0

•3h - pin CLKOUT is hold on 1

•4h - pin CLKOUT shows 27.12 MHz from the crystal

•5h - pin CLKOUT shows 13.56 MHz derived from the crystal

•6h - pin CLKOUT shows 6.78 MHz derived from the crystal

•7h - pin CLKOUT shows 3.39 MHz derived from the crystal

•8h - pin CLKOUT is toggled by the Timer0 overflow

•9h - pin CLKOUT is toggled by the Timer1 overflow

•Ah - pin CLKOUT is toggl ed by the Timer2 overflow

•Bh - pin CLKOUT is toggl ed by the Timer3 overflow

•Ch...Fh - RFU

3 ClkOut_En Enables the clock at Pin CLKOUT

2 PLL_PD PLL power down

1-0 PLLDi v _FB PLL feedback di vider (see table 174)

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8.13.4 PLLDiv_Out

Table 175. Setting of feedback divider PLLDiv_FB [1:0]

Bit 1 Bit 0 Division

0 0 23 (VCO frequency 31 2Mhz)

0 1 27 (VCO frequency 366MHz)

1 0 28 (VCO frequency 380Mhz)

1 1 23 (VCO frequency 31 2Mhz)

Table 176. PLLDiv_Out register (address 3Eh)

Bit 7 6 5 4 3 2 1 0

Symbol PLLDiv_Out

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Table 177. PLLDiv_Out bits

Bit Symbol Description

7 to 0 PLLDiv_Out PLL output divider factor; Refer to Section 7.8.2

Table 178. Setting for the output divider ratio PLLDi v_Out [7:0]

Value Division

0RFU

1RFU

2RFU

3RFU

4RFU

5RFU

6RFU

7RFU

10 10

... ...

253 253

254 254

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8.14 Low-power card detection configuration registers

The LPCD registers contain the settings for the low-power card detection. The setting for

LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers

LPCD_QMin, LPCD_QMax and LPCD_IMin each.

8.14.1 LPCD_QMin

8.14.2 LPCD_QMax

8.14.3 LPCD_IMin

Table 179. LPCD_QMin register (address 3Fh)

Bit 7 6 5 4 3 2 1 0

Symbol LPCD_IMax.5 LPCD_IMax.4 LPCD_QMin

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Table 180. LPCD_QMin bits

Bit Symbol Description

7, 6 LPCD_IMax Defines the highest two bits of the higher border for the LPCD. If the

measurement value of the I channel is higher than LPCD_IMax, a

LPCD interrupt request is indicated by bit IRQ0.LPCDIRQ.

5 to 0 LPC D_QMin Defines the lower border for the LPCD. If the measurement value of

the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is

indicated by bit IRQ0.LPCDIRQ.

Table 181. LPCD_QMax regis t er (address 40h)

Bit 7 6 5 4 3 2 1 0

Symbol LPCD_IMax.3 LPCD_IMax.2 LPCD_QMax

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Ta ble 182. LPCD_QMa x bi ts

Bit Symbol Description

7 LPCD_IMax.3 Defines the bit 3 of the high border for the LPCD. If the measurement

value of the I channel is higher than LPCD IMax, a LPCD IRQ is

raised.

6 LPCD_IMax.2 Defines the bit 2 of the high border for the LPCD. If the measurement

value of the I channel is higher than LPCD IMax, a LPCD IRQ is

raised.

5 to 0 LPCD_QMax Defines the high border for the LPCD. If the measurement value of

the Q channel is higher than LPCD QMax, a LPCD IRQ is raised.

Table 183. LPCD_IMin register (address 41h)

Bit 7 6 5 4 3 2 1 0

Symbol LPCD_IMax.1 LPCD_IMax.0 LPCD_IMin

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8.14.4 LPCD_Result_I

8.14.5 LPCD_Result_Q

8.15 Pin configuration

8.15.1 PinEn

Table 184. LPCD_IMin bits

Bit Symbol Description

7 to 6 LPCD_IMax Defines lowest two bits of the higher border for the low-power card

detection (LPCD). If the measurement value of the I channel is higher

than LPCD IMax, a LPCD IRQ is raised.

5 to 0 LPC D_IMin Defines the lower border for the ow power card detection. If the

measurement value of the I channel is lower than LPCD IMin, a LPCD

IRQ is raised.

Table 185. LPCD_Result_I reg is te r (add ress 42h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU- RFU- LPCD_Result_I

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Table 186. LPCD_I_Result bits

Bit Symbol Description

7 to 6 RFU -

5 to 0 LPCD_Result_I Shows the result of the last low-power card detection (I-Channel).

Table 187. LPCD_Result_Q register (address 43h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU LPCD_IRQ_C

lr LPCD_Reslult_Q

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Ta ble 188. LPCD_Q_Result bits

Bit Symbol Description

7RFU -

6 LPCD_IRQ_Clr If set no LPCD IRQ is raised any more until the next low-power

card detection procedure. Can be used by software to clear the

interrupt source.

5 to 0 LPCD_Result_Q Shows the result of the last ow power card detection (Q-Channel).

Table 189. PinEn register (address 44h)

Bit 7 6 5 4 3 2 1 0

Symbol SIGIN_EN CLKOUT_EN IFSEL1_EN IFSEL0_EN TCK_EN TMS_EN TDI_EN TMDO_EN

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8.15.2 PinOut

Ta ble 190. PinEn b its

Bit Symbol Description

7 SIGIN_EN Enables the output functionality on SIGIN (pin 5). The pin is then used

as I/O.

6 CLKOUT_EN Enables the output functionality of the CLKOUT (pin 22). Th e pin is

then used as I/O. The CLKOUT function is switched off.

5 IFSEL1_EN Enables the output functionality of the IFSEL1 (pin 27). The pin is then

used as I/O.

4 IFSEL0_EN Enables the output functionality of the IFSEL0 (pin 26). The pin is then

used as I/O.

3 TCK_EN Enables the output functionality of the TCK (pin 4) of the boundary

scan interface. The pin is then used as I/O. If the boundary scan is

activated in EEPROM, this bit has no function.

2 TMS_EN Enables the output functionality of the TMS (pin 2) of the boundary

scan interface. The pin is then used as I/O. If the boundary scan is

activated in EEPROM, this bit has no function.

1 TDI_EN Enables the output functionality of the TDI (pin 1) of the boundary scan

interface. The pin is then used as I/O. If the boundary scan is activated

in EEPROM, this bit has no function.

0 TDO_EN Enables the output functionality of the TDO(pin 3) of the boundary

scan interface. The pin is then used as I/O. If the boundary scan is

activated in EEPROM, this bit has no function.

Table 191. PinOut register (address 45h)

Bit 7 6 5 4 3 2 1 0

Symbol SIGIN_OUT CLKOUT_OUT IFSEL1_OUT IFSEL0_OUT TCK_OUT TMS_OU

TTDI_OUT TDO_OUT

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Ta ble 192. PinOut bits

Bit Symbol Description

7 SIGIN_OUT Output buffer of the SIGIN pin

6 CLKOUT_OUT Output buffer of the CLKOUT pin

5 IFSEL1_OUT Output buffer of the IFSEL1 pin

4 IFSEL0_OUT Output buffer of the IFSEL0 pin

3 TCK_OUT Output buffer of the TCK pin

2 TMS_OUT Output buffer of the TMS pin

1 TDI_OUT Output buffer of the TDI pin

0 TDO_OUT Output buffer of the TDO pin

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8.15.3 PinIn

8.15.4 SigOut

Table 193. PinIn register (address 46h)

Bit 7 6 5 4 3 2 1 0

Symbol SIGIN_IN CLKOUT_IN IFSEL1_IN IFSEL0_IN TCK_IN TMS_IN TDI_IN TDO_IN

Access

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Ta ble 194. PinIn bits

Bit Symbol Description

7 SIGIN_IN Input buffer of the SIGIN pin

6 CLKOUT_IN Input buffer of the CLKOUT pin

5 IFSEL1_IN In put buffer of the IFSEL1 pin

4 IFSEL0_IN In put buffer of the IFSEL0 pin

3 TCK_IN Input buffer of the TCK pin

2 TMS_IN Input buffer of the TMS pin

1 TDI_IN Input buffer of the TDI pin

0 TDO_IN Input buffer of the TDO pin

Table 195. SigOut register (address 47h)

Bit 7 6 5 4 3 2 1 0

Symbol Pad

Speed RFU SigOutSel

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Ta ble 196. SigOut bits

Bit Symbol Description

7 PadS peed If set, the I/O pins are supporting a fast switching mode.The fast mode

for the I/O’s will increase the peak current consumption of the device,

especially if multiple I/Os are switching at the same time. The power

supply needs to be designed to deliver this peak currents.

6 to 4 RFU -

3 to 0 SIGOutSel 0h, 1h - The pin SIGOUT is 3-state

2h - The pin SIGOUT is 0

3h - The pin SIGOUT is 1

4h - The pin SIGOUT shows the TX-enve lope

5h - The pin SIGOUT shows the TX-active signal

6h - The pin SIGOUT shows the S3C (generi c) signal

7h - The pin SIGOUT shows th e RX-envelope

(only valid for ISO/IEC 14443A, 106 kBd)

8h - The pin SIGOUT shows the RX-a ctive signal

9h - The pin SIGOUT shows th e RX-bit signal

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8.16 Protocol configuration registers

8.16.1 TxBitMod

8.16.2 TxDataCon

Table 197. TxBitMod register (address 48h)

Bit 7 6 5 4 3 2 1 0

Symbol TxMSBFirst RFU TxParity

Type RFU TxStopBitType RFU TxStartBitType TxStartBitEn

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Ta ble 198. TxBitMod bits

Bit Symbol Description

7 TxMSBFirst If set, data is interpreted MSB first for data transmission. If cleared,

data is interpreted LSB first.

6RFU -

5 TxParityType Defines the type of the p arity bit. If set to 1, odd parity is calculated,

otherwise even parity is calculated.

4RFU -

3 TxStopBitType Defines the type of the stop-bit (0b: logic zero / 1b: logic one).

2RFU -

1 TxStartBitType Defines the type of the start-bit (0b: logic zero / 1b: logic one).

0 TxStartBitEn If set to 1, a start-bit will be sent.

Table 199. TxDataCon (address 4Ah)

Bit 7 6 5 4 3 2 1 0

Symbol DCodeType DSCFreq DBFreq

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8.16.3 TxDataMod

Ta ble 200. TxDataCon bits

Bit Symbol Description

7 to 4 DCodeType Specifies the type of encoding of data to be used:

0h - no special coding

1h - collider datastream is decoded

2h - RFU 3h - RFU

4h - return to zero code - pulse at first position

5h - return to zero code - pulse at 2nd position

6h - return to zero code - pulse at 3rd position

7h - return to zero code - pulse at 4th position

8h - 1 out of 4 coding

9h - 1 out of 256 code (range 0 - 255) [ICODE SLI]

Ah - 1 out of 256 code (range 0 - 255; 00h is encoded with no

modulation, value 256 not used) [ICODE 1]

Bh - 1 out of 256 code (range 0 - 255; 00h is encoded with a pulse on

last position) [I Code quite value]

Ch- Pulse internal encoded (PIE) [ISO/IEC 1800 0-3 mode 3/ EPC

Class-1HF]

Dh - RFU

Eh - RFU

Fh - RFU

3 DSCFreq Specifies the subcarrier frequency of the used envelope.

0h - 424 kHz

1h - 848 kHz

Note: This setting is only relevant, if an envelope is used which

involves a subcarrier, e.g. Manchester with subcarrier coding.

2 to 0 DBFreq Specifies the frequency of the bit stream:

0h - RFU

1h - RFU

2h - 26 kHz

3h - 53 kHz

4h - 106 kHz

5h - 212 kHz

6h - 424 kHz

7h - 848 kHz

Table 201. TxDataMod register (address 4Bh)

Bit 7 6 5 4 3 2 1 0

Symbol Frame step DMillerEn DPulseType DInvert DEnvType

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8.16.4 TxSymFreq

Ta ble 202. TxDataMod bits

Bit Symbol Description

7 Framestep If set to 1, at every start of transmission, each byte of data is sent in a

separate frame. SOF and EOF is appended to the data byte according

to the framing settings. After one byte is transmitted, the TxEncoder

waits for a new start trigger to continue with the next byte (trigger is

generated automatically). If set to 0, transmission is done in the used

way, wh ere after a start trigger all data bytes are sent and the framing

is done for the complete data stream only once.

6 DMillerEn If set, pulse modulation is applied according to modified miller code.

Note: This bit is intended to be set if DPulseType is 1h.

5 to 4 DPulseType Specifies which type of pulse modulation is selected.

0h - no pulse modulation

1h - pulse starts at beginning of bit

2h - pulse starts at beginning of second bit half

3h - pulse starts at beginning of third bit quarter

Note: If DMillerEn is set, DPulseType must be set to 1h.

3 DInvert If set the envelope of data is inverted.

2 to 0 DEnvType Specifies the type of envelope used for transmission of data packets.

The selected envelope type is applied to the pseudo bit stream.

0h - Direct output

1h - Manchester code

2h - Manchester code with subcarrier

3h - BPSK

4h - RZ (pulse of half bit length at beginning of second half of bit)

5h - RZ (pulse of half bit length at beginning of bit)

6h - RFU

7h - RFU

Table 203. TxSymFreq (address 4Ch)

Bit 7 6 5 4 3 2 1 0

Symbol S32SCFreq S32BFreq S10SCFreq S10BFreq

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8.16.5 TxSym0

The two Registers TxSym0H an d TxSym0L create a 16-bit register that contains the

pattern for Symbol0.

Ta ble 204. TxSymFreq bits

Bit Symbol Description

7 S32SCFreq Specifies the frequency of the subcarrier of symbol2 and symbol3:

0b ... 424 kHz

1b ... 848 kHz

6 to 4 S32BFreq Specifies the frequency of the bit stream of symbol2 and symbol3:

000b ... RFU

001b ... RFU

010b ... 26 kHz

011b ... 53 kHz

100b ... 106 kHz

101b ... 212 kHz

110b ... 424 kHz

111b ... 848 kHz

3 S10SCFreq Specifies the frequency of the subcarrier of symbol0 and symbol1:

0b ...424 kHz

1b ...848 kHz

2 to 0 S10BFreq Specifies the frequency of the bit stream of symbol0 and symbol1:

000b ... RFU

001b ... RFU

010b ... 26 kHz

011b ... 53 kHz

100b ... 106 kHz

101b ... 212 kHz

110b ... 424 kHz

111b ... 848 kHz

Table 205. TxSym0H (address 4Dh)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol0_H

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Ta ble 206. TxSYM0 H bits

Bit Symbol Description

7 to 0 Symbol0H Higher 8 bits of symbol definition for Symbol0.

Table 207. TxSym0L (address 4Eh)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol0_L

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Table 208. TxSYM0L bits

Bit Symbol Description

7 to 0 Symbol0_L Lower 8 bits of symbol definition for Symbol0.

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8.16.6 TxSym

The two Registers TxSym1H an d TxSym1L create a 16 bit register that contains the

pattern for Symbol1.

8.16.7 TxSym2

8.16.8 TxSym3

Table 209. TxSym1H (address 4Fh)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol1_H

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Ta ble 210. TxSym1H bits

Bit Symbol Description

7 to 0 Symbol1_H Higher 8 bits of symbol definition for Symbol1.

Table 211. TxSym1L (address 50h)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol1_L

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Ta ble 212. TxSym1L bits

Bit Symbol Description

7 to 0 Symbol1_L Lower 8 bits of symbol definition for Symbol1.

Table 213. TxSYM2 (address 51h)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol2

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Ta ble 214. TxSym2 b its

Bit Symbol Description

7 to 0 Symbol2 Symbol definition for Symbol2.

Table 215. TxSym3 (address 52h)

Bit 7 6 5 4 3 2 1 0

Symbol Symbol3

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Ta ble 216. TxSym3 b its

Bit Symbol Description

7 to 0 Symbol3 Symbol definition for Symbol3.

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8.16.9 TxSym10Len

8.16.10 TxSym32Len

8.16.11 TxSym10BurstCtrl

Table 217. TxSym10Len (address 53h)

Bit 7 6 5 4 3 2 1 0

Symbol Sym1Len Sym0Len

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Ta ble 218. TxSym10Len bits

Bit Symbol Description

7 to 4 Sym1Len Specifies th e number of valid bits of the symbol definition of Symbol1.

The range is from 1 bit (0h) to 16 bits (Fh).

3 to 0 Sym0Len Specifies th e number of valid bits of the symbol definition of Symbol0.

The range is from 1 bit (0h) to 16 bits (Fh).

Table 219. TxSym32Len (address 54h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU Sym3Len RFU Sym2Len

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Ta ble 220. TxSym32Len bits

Bit Symbol Description

7RFU -

6 to 4 Sym3Len Specifies th e number of valid bits of the symbol definition of Symbol3.

The range is from 1-bit (0h) to 8-bits (7h).

3RFU -

2 to 0 Sym2Len Specifies th e number of valid bits of the symbol definition of Symbol2.

The range is from 1-bit (0h) to 8-bits (7h).

Table 221. TxSym10BurstCtrl reg ister (address 55h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU Sym1BurstType Sym1BurstOnly Sym1BurstEn RFU Sym0Burst

Type Sym0BurstO

nly Sym0Burst

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Table 222. TxSym10BurstCtrl bits

Bit Symbol Description

7RFU -

6 Sym1BurstType Specifies the type of the burst of Symbol1 (logical zero / logical

one).

5 Sym1BurstOnly If set to 1 Symbol1 consists only of a burst and no symbol

pattern.

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8.16.12 TxSym10Mod Reg

4 Sym1BurstEn Enables the burst of symbol 1 of the length defined in

TxSym10BurstLen.

3RFU -

2 Sym0BurstType Specifies the type of the burst of symbol 0 (logical zero / logical

one).

1 S ym0BurstOnly If set to 1, symbol 0 consists only of a burst and no symbol

pattern.

0 Sym0BurstEn Enables the burst of symbol 0 of the length defined in

TxSym10BurstLen.

Table 222. TxSym10BurstCtrl bits …continued

Bit Symbol Description

Table 223. TxSym10Mod register (address 56h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU S10MillerEn S10PulseType S10Inv S10EnvType

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Table 224. Tx Sym10Mod bits

Bit Symbol Description

7RFU -

6 S10MillerEn If se t, pulse modulation is applied according to modified miller code.

Note: This bit shall be set only if S10PulseType is set to 1h.

5 to 4 S10PulseType Specifies which type of pulse modulation is selected:

0h - no pulse modulation

1h - pulse starts at beginning of bit

2h - pulse starts at beginning of second bit half

3h - pulse starts at beginning of third bit quarter

3 S10Inv If set. the output of Symbol0 and Symbol1 is inverted.

2 to 0 S10EnvType Specifies the type of envelope used for transmission of Symbol0 and

Symbol1. The pseudo bit stream is logically combined with the

selected envelope type.

0h - Direct output

1h - Manchester code

2h - Manchester code with subcarrier

3h - BPKSK

4h - RZ return zero, pulse of half bit length at beginning of second half

of bit

5h - RZ return zero, pulse of half bit length at beginning of second half

of bit

6h - RFU

7h - RFU

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8.16.13 TxSym32Mod

8.17 Receiver configuration

8.17.1 RxBitMod

Table 225. TxSym32Mod register (address 57h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU S32MillerEn S32PulseType S32Inv S32EnvType

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Table 226. Tx Sym32Mod bits

Bit Symbol Description

7RFU -

6 S32MillerEn If se t, pulse modulation is applied according to modified miller code.

Note: This bit shall be set only if S32PulseType is set to 1h.

5 to 4 S32PulseType Specifies which type of pulse modulation is selected:

0h - no pulse modulation

1h - pulse starts at beginning of bit

2h - pulse starts at beginning of second bit half

3h - pulse starts at beginning of third bit quarter

3 S32Inv If set. the output of Symbol2 and Symbol3 is inverted.

2 to 0 S32EnvType Specifies the type of envelope used for transmission of symbol 0 and

symbol 1. The bit stream is logically combined with the selected

envelope type.

0h - Direct output

1h - Manchester code

2h - Manchester code with subcarrier

3h - BPSK

4h - RZ return zero, pulse of half bit length at beginning of second half

of bit)

5h - RZ return zero, pulse of half bit length at beginning of bit)

6h to 7h RFU

Table 227. RxBitMod (address 58h)

Bit 7 6 5 4 3 2 1 0

Symbol RFU RFU RxStopOnInvPar RxStopOnLength RxMSBFirst RxStopBitEn RxParityType RFU

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8.17.2 RxEofSym

Table 228. RxBitMod bits

Bit Symbol Description

7 to 6 RFU -

5 RxStopOnInvPar If set to 1, inverse parity bit is a stop condition.

4 RxS topOnLength If set to 1, data reception stops when the number of received

bytes reach the defined frame length. The value for the frame

length is taken from the first data-byte received.

3 RxMSBFirst If set t o 1, data bytes are interpreted MSB fi rst for data

reception, which means data is converted at the CLCoPro

interface. If this bit is set to 0, data is interpreted LSB first.

2 RxStopBitEn If set, a stop-bit is expected and will be checked and

extracted from data stream. Additionally on detection of a

stop-bit a reset signal for the demodulator is generator to

enable a re-synchronization of the demodulator. If the

expected stop-bit is incorrect, a frame error flag is set and the

reception is aborted.

Note: A stop bit is always considered to be a logic 1

1 RxParityType Defines which type of the parity-bit is calculated:

If cleared: Even parity

If set: Odd parity

0RFU -

Table 229. RxEofSym (address 59h)

Bit 7 6 5 4 3 2 1 0

Symbol RxEOFSymbol

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Table 230. RxEOFSym bits

Bit Symbol Description

7 to 0 RxEOF

Symbol This value defines the pattern of the EOF symbol with a maximum

length of 4 bit. Every tuple of 2 bits of the RxEOFSymbol encodes one

bit of the EOF symbol. A 00 tuple closes the symbol. In this way

symbols with less than 4 bits can be defined, starting with the bit0 and

bit1. The leftmost active symbol pattern is processed first, which

means the pattern is expected first. If the bit0 and bit1 are both zero,

the EOF symbol is disabled. The follo wing mapping is defined:

0h - no symbol bit

1h - zero value

2h - one value

3h - collision

Example:

1Dh: Zero-Collision-Zero

E8h: No symbol because two LSBits are zero

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8.17.3 RxSyncValH

8.17.4 RxSyncValL

8.17.5 RxSyncMod

Table 231. RxSyncValH register (address5Ah)

Bit 7 6 5 4 3 2 1 0

Symbol RxSyncValH

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Ta ble 232. RxSyncValH bits

Bit Symbol Description

15 to 0 RxSyncValH Defines the high byte of the St art Of Frame (SOF) p attern, which must

be in front of the receiving data.

Table 233. RxSyncValL register (address 5Bh)

Bit 7 6 5 4 3 2 1 0

Symbol RxSyncValL

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Ta ble 234. RxSyncValL bits

Bit Symbol Description

7 to 0 RxSyncValL Defines the low byte of the Start Of Frame (SOF) Pattern, which must

be in front of the receiving data.

Table 235. RxSyncMode register (address 5Ch)

Bit 7 6 5 4 3 2 1 0

Symbol SyncLen SyncNegEdge LastSyncHalf SyncType

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Table 236. RxSyncMod bits

Bit Symbol Description

7 to 4 SyncLen Defines how many Bits of registers RxSyncValH and RxSyncValL are

valid. For ISO/IEC 14443B set to 0.

3 SyncNegEdge Is used for SOF with no correlation peak. The first negative edge of the

correlati on is used for defin i n g th e bi t grid.

2 LastSyncHalf The last Bit of the Sync mo de has on ly half of the length compared to

all other bits. (ISO/IEC 18000-3 mode 3/ EPC Class-1HF).

1 to 0 SyncType 0: all 16 bits of SyncVal are interpreted as burst.

1: a nibble of bits is interpreted as one bit in following way:

{data, coll} data = zero or one; coll = 1 means a collision on this bit.

Note: if Coll = 1 the value of data is ignored.

2: the synchronisation is done at every start bit of each byte (type B)

3: RFU

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8.17.6 RxMod

8.17.7 RxCorr

Table 237. RxMod regist er (address 5Dh)

Bit 7 6 5 4 3 2 1 0

Symbol RFU RFU PreFilter RectFilter SyncHigh CorrInv FSK BPSK

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Table 238. RxMod bits

Bit Symbol Description

7 to 6 - RFU

5 PreFilter If set 4 samples are combined to one data. (average).

4 RectFilter If set, the ADC-values are changed to a more rectangular wave shape.

3 SyncHigh Defines if the bit grid is fixed at maximum (1) or at minimum (0) value

of the correlation.

2 CorrInv Defines a lo gical for Manchester coding:

0: subcarrier / no subcarrier.

1 FSK If set to 1, the demodula tion scheme is set to FSK.

0 BPSK If set to 1, the modulation scheme is BPSK.

Table 239. RxCorr register (address 5Eh)

Bit 7 6 5 4 3 2 1 0

Symbol CorrFreq CorrSpeed CorrLen RFU

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Ta ble 240. RxCorr bits

Bit Symbol Description

7, 6 CorrFreq 0h - 212 kHz

1h - 424 kHz

2h - 848 kHz

3h - 848 kHz

5, 4 CorrSpeed Defines the number of clocks used for one correlation.

0h - ISO/IEC 14443

1h - ICODE 53 kBd, FeliCa 424 kBd

2h - ICODE 26 kBd, FeliCa 212 kBd

3h - RFU

3 CorrL en Define s the length of the correlation data. (64 or 32 values).

If set the lengths of the correlation data is 32 values. (ISO/IEC 18000-3

mode 3/ EPC Class-1HF, 2 Pulse Manchester 848 kHz subcarrier).

2 to 0 RFU -

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8.17.8 FabCali

8.18 Version register

8.18.1 Version

Table 241. FabCali regis ter (address 5Fh)

Bit 7 6 5 4 3 2 1 0

Symbol FabCali

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Table 242. FabCali bits

Bit Symbol Description

7 to 0 FabCali Fabrication calibration of the receiver.

NOTE: do not change boot val ue.

Table 243. Version register (address 7Fh)

Bit 7 6 5 4 3 2 1 0

Symbol Version SubVersion

Access

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Table 244. Version bits

Bit Symbol Description

7 to 4 Version Includes the version of the CLRC663 sili con.

3 to 0 SubVersion Include s the subversion of the CLRC663 silicon .

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9. Limiting values

10. Recommended operating conditions

[1] VDD(PVDD) must always be the same or lower than VDD.

11. Thermal characteristics

12. Characteristics

Table 245. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +5.5 V

VDD(PVDD) PVDD supply voltage 0.5 +5.5 V

VDD(TVDD) TVDD supply voltage 0.5 +5.5 V

Vi(RXP) input voltage on pin RXP 0.5 +2.0 V

Vi(RXN) input voltage on pin RXN 0.5 +2.0 V

Ptot total power dissipation per package - 1125 mW

VESD(HBM) electrostatic discharge voltage Human Body Model (HBM);

1500 , 100 pF;

JESD22-A114-B

- 2000 V

VESD(CDM) electrostatic discharge voltage Charge Device Model (CDM); - 500 V

Tj(max) maximum junction

temperature - 150 °C

Table 246. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 5 5.5 V

VDD(TVDD) TVDD supply voltage [1] 355.5V

VDD(PVDD) PVDD supply voltage 3 5 5.5 V

Tamb ambient temperature 25 - +85 C

Table 247. Thermal characteristics

Symbol Parameter Conditions Package Typ Unit

Rth(j-a) thermal resistance from junction to

ambient in still air with exposed pin soldere d on a

4 layer JEDEC PCB HVQFN32 40 K/W

Table 248. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Input characteristics I/O Pin Characteristics IF3-SDA in I2C configuration

ILI input leakage curren t output disable d - 2 100 nA

VIL LOW-level input voltage 0.5 - +0.3VDD(PVDD) V

VIH HIGH-level input voltage 0.7VDD(PVDD) -V

DD(PVDD) + 0.5 V

VOL LOW-level output voltage IOL = 3 mA - - 0 .3 V

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IOL LOW-level output current VOL = 0.4 V; Standard

mode, Fast mode 4-- mA

VOL = 0.6 V; Standard

mode, Fast mode 6-- mA

tf(o) output fall time Standard mode, Fast

mode, CL< 400 pF --250ns

Fast mode +; CL< 550 pF - - 120 ns

tSP pulse width of spikes that

must be suppressed by

the input filter

0-50 ns

Ciinput capacitance - 3.5 5 pF

CLload capacitance Standard mode - - 400 pF

Fast mode - - 550 pF

tEER EEPROM data retention

time Tamb = +55 °C10--year

NEEC EEPROM endurance

(number of programming

cycles)

under all operating

conditions 5 x 105 - - cycle

Analog and digital supply AVDD,DVDD

VDDA analog supply voltage internal generated voltage,

buffered 1.7 1.8 1.9 V

VDDD digital supply voltage internal generated voltage,

buffered 1.7 1.8 1.9 V

CLload capacitance AVDD 220 470 - nF

CLload capacitance DVDD 220 470 - nF

Current consumption

Istb standby current Standby bit = 1 - 3 6 A

IDD supply current modem on - 17 20 mA

modem off - 0.45 0.5 mA

IDD(TVDD) TVDD supply current - 100 250 mA

I/O pin characteristics SIGIN, SIGO UT, CLKOUT, IFSEL0,

IFSEL1, TCK, TMS, TDI, TDO, IRQ, IF0, IF1, IF2, SCL2, SDA2

ILI input leakage curren t output disable d - 50 500 nA

VIL LOW-level input voltage 0.5 - 0.3VDD(PVDD) V

VIH HIGH-level input voltage 0.7VDD(PVDD) -V

DD(PVDD) + 0.5 V

VOL LOW-level output voltage IOL = 4 mA,

VDD(PVDD) =5.0V --0.4V

IOL = 4 mA,

VDD(PVDD) =3.3V --0.4V

VOH HIGH-level output voltage IOL = 4 mA,

VDD(PVDD) =5.0V 4.6 - - V

IOL = 4 mA,

VDD(PVDD) =3.3V 2.9 - - V

Ciinput capacitance - 2.5 4.5 pF

Table 248. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit

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[1] Ipd is the total current for all supplies.

[2] IDD(PVDD) depends on the overall load at the digital pins.

[3] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.

[4] During typical circuit operation, the overall current is below 100 mA.

[5] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz.

Pull-up resistance for TCK, TMS, TDI, IF2

Rpu pull-up resistance 50 72 120 K

Pin characteristics AUX 1, AUX 2

Vooutput voltage 0 - 1.8 V

CLload capacitance - - 400 pF

Pin characteristics RXP, RXN

Viinput voltage 0 - 1.8 V

Ciinput capacitance 2 3.5 5 pF

Vmod(pp) modulation voltage Vmod(pp) =V

i(pp)(max) Vi(pp)

(min)

-2.5- mV

Vpp signal on RXP, RXN - - 1.65 V

Pins TX1 and TX2

Vooutput voltage Vss(TVSS) -V

DD(TVDD) V

Rooutput resistance - 1.5 - 

Current consumption

Ipd power-down current ambie nt temp = 25°C - 8 40 nA

ambient temp = 85°C - 200 400 nA

Istby standby current ambient temp = 25°C [1] -36 A

ILPCD LPCD sleep current [1] -36 A

IDD supply current - 17 20 mA

modem off; transceiver off - 0.45 0.5 mA

IDD(PVDD) PVDD supply current no load on digital pin [2] --10A

IDD(TVDD) TVDD supply current [3][4][5] - 100 200 mA

Clock frequency Pin CLKOUT

fclk clock frequency configured to 27.12 MHz - 27.12 - MHz

clk clock duty cycle - 50 - %

Crystal oscillator

Vo(p-p) peak-to-peak output

voltage pin XTAL1 - 1 - V

Viinput voltage pin XTAL1 0 - 1.8 V

Ciinput capacitance pin XTAL1 - 3 - pF

Typical input requirements

fxtal crystal frequency - 27.12 - MHz

ESR equivalent series

resistance -50100

CLload capacitance - 10 - pF

Pxtal crystal power dissipation - 50 100 W

Table 248. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit

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12.1 T iming characteristics

Remark: To send more bytes in one dat a stream the NSS signal must be LOW during the

send process. To send more than one dat a stream the NSS signal must be HIGH between

each data stream.

Fig 34. Pin RX input voltage

001aak012

VMID

0 V

Vmod

Vi(p-p)(max) Vi(p-p)(min)

13.56 MHz

carrier

Table 249. SPI timing characteristics

Symbol Parameter Conditions Min Typ Max Unit

tSCKL SCK LOW time 50 - - ns

tSCKH SCK HIGH time 50 - - ns

th(SCKH-D) SCK HIGH to data input hold

time SCK to changing MOSI 25 - - ns

tsu(D-SCKH) data input to SCK HIGH

set-up time changing MOSI to SCK 25 - - ns

th(SCKL-Q) SCK LOW to data output

hold time SCK to changing MISO - - 25 ns

t(SCKL-NSSH) SCK LOW to NSS HIGH

time 0--ns

tNSSH NSS HIGH time before communication 50 - - ns

Ta ble 250. I2C-bus timing in fast mode and fast mo de plus

Symbol Parameter Conditions Fast mode Fast mode

Plus Unit

Min Max Min Max

fSCL SCL clock frequency 0 400 0 1000 kHz

tHD;STA hold time (repea ted) START

condition after this period,

the first clock pulse

is generated

600 - 260 - ns

tSU;STA set-up time for a repeated

START condition 600 - 260 - ns

tSU;STO set-up time for STOP condition 600 - 260 - ns

tLOW LOW period of the SCL clock 1300 - 500 - ns

tHIGH HIGH period of the SCL clock 600 - 260 - ns

tHD;DAT data hold time 0 900 - 450 ns

Product data sheet

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High performance NFC reader solution

tSU;DAT data set-up time 100 - - - ns

trrise time SCL signal 20 300 - 120 ns

tffall time SCL signal 20 300 - 120 ns

trrise time SDA and SCL

signals 20 300 - 120 ns

tffall time SDA and SCL

signals 20 300 - 120 ns

tBUF bus free time between a STOP

and START condition 1.3 - 0.5 - s

Fig 35. Timing for fast and standard mode devices on the I2C-bus

Ta ble 250. I2C-bus timing in fast mode and fast mode plus …continued

Symbol Parameter Conditions Fast mode Fast mode

Plus Unit

Min Max Min Max

001aaj635

SDA

SCL

tLOW tf

tSP tr

tHD;STA tHD;DAT

tHD;STA

trtHIGH

tSU;DAT

SSrPS

tSU;STA tSU;STO

tBUF

Product data sheet

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High performance NFC reader solution

13. Application information

A typical application diagram using a complementary antenna con nection to the CLRC663

is shown in Figure 36.

The antenna tuning and RF part matching is described in the application note Ref. 1 and

Ref. 2.

13.1 Antenna design description

The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a

matching circuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5 and

C4 = C6;), and the antenna itself. The receiving circuit component values needs to be

designed for operation with the CLRC663 . A reuse of dedicated antenna designs done fo r

other products without adaptation of component values will result in degraded

performance.

For a more detailed information about designing and tuning the antenna, please refer to

the relevant ap plic at ion not es :

•MICORE reader IC family; Directly Matched Antenna Design, Ref. 1 and

•MIFARE (14443A) 13.56 MHz RFID Proximity Antennas, Ref. 2.

Fig 36. Typical application antenna circuit diagram

001aam269

VDD PVDD

MICRO-

PROCESSOR

host

interface

TVDD

XTAL1 XTAL2

RXN

VMID

TX1

TVSS

TX2

82518

VSS

33 20

28-31

PDOWN

IRQ

DVDD

AVDD

12 RXP

READER IC

L0 C1 Ra

CRXN

CRXP

Cvmid

27.12 MHz

antenna

Lant

Product data sheet

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High performance NFC reader solution

13.1.1 EMC low pass filter

The MIFARE system operates at a frequency of 13.56 MHz. This frequency is derived

from a quartz oscillator to clock the CLRC663 and is also the basis for driving the antenna

with the 13.56 MHz energy carrier. This will not only cause emitted power at 13.56 MHz

but will also emit power at higher harmonics. The international EMC regulations define the

amplitude of the emitted power in a broad frequency range. Thus, an appropriate filtering

of the output signal is necessary to fulfil these regulations.

Remark: The PCB layout has a major influence on the overall per formance of the filter.

13.1.2 Antenna matching

Due to the impedance transformation of the given low pass filter, the antenna coil has to

be matched to a cer t ain imp edance. The matching element s C1 and C2 can be estimate d

and have to be fine tuned depending on the design of the antenna coil.

The correct impedance matchi ng is important to provide the optimum performance. The

overall quality factor has to be considered to guarantee a proper ISO/IEC 14443

communication scheme. Environmental influences have to be considered as well as

common EMC design rules.

For details refer to the NXP application notes.

13.1.3 Receiving circuit

The internal receiving concept of the CLRC663 makes use both side-bands of the

sub-carrier load modulat ion of the card response via a dif ferential receivin g concept (RXP,

RXN). No external filtering is required.

It is recommended to use the internally generated VMID potential as the input potential of

pin RX. This DC voltag e level of VMID has to be coupled to the Rx- pins via R2 and R4. To

provide a stable DC reference voltage capacitances C4, C6 has to be connected between

VMID and ground. Refe r to Figure 36

Considering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 and

R2 as well as R3 + C5 and R4 has to be designe d. Dependin g on the an tenna coil design

and the impedance matching the volt age at the antenna coil var ies from antenna design to

antenna design. Therefore the recommended way to design the receiving circuit is to use

the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned

application note, and adjust the voltage at the RX-pins by varying R1(= R3) within the

given limits.

Remark: R2 and R4 are AC-wise connected to ground (via C4 and C6).

Product data sheet

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High performance NFC reader solution

13.1.4 Antenna coil

The precise calculation of the antenna coils’ inductance is not practicable but the

inductance can be estimated using the following formula. We recommend designing an

antenna either with a circular or rectangular shape.

(4)

•I1 - Length in cm of one turn of the conductor loop

•D1 - Diameter of the wire or width of the PCB conductor respectively

•K - Antenna shape factor (K = 1,07 for circular anten nas and K = 1,47 for square

antennas)

•L1 - Inductance in n H

•N1 - Number of turns

•Ln: Natural logarithm function

The actual values of the antenna inductance, resistance, and capacitance at

13.56 MHz depen d on var iou s paramete rs su ch as:

•antenna construction (Type of PCB)

•thickness of conductor

•distance between the windings

•shielding layer

•metal or ferrite in the near environment

Therefore a measurement of those parameters under real life conditions, or at least a

rough measurement and a tuning procedure is highly recommended to guarantee a

reasonable performance. For details refer to the above men tioned application notes.

L1 2=I1I1

------

ln K–





N118



Product data sheet

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High performance NFC reader solution

14. Package outline

Fig 37. Package outline SOT617-1 (HVQFN32)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 5.1

4.9

3.25

2.95

5.1

4.9 3.25

2.95

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT617-1 MO-220- - - - - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT617-1

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

916

32 25

terminal 1

index area

terminal 1

index area

01-08-08

02-10-18

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

Detailed package information can be found at

http://www.nxp.com/package/SOT617-1.html.

15. Handling information

Moisture Sensitivity Level (MSL) evaluation has been performed according to

SNW-FQ-225B re v.04/07/07 (JEDEC J-STD-020C). MSL for this p ackage is level 2 which

means 260 C convection reflow temperature.

For MSL2:

•Dry pack is required.

•1 year out-of-pack floor life at maximum ambient temperature 30 C/ 85 % RH.

For MSL1:

•No dry pack is required.

•No out-of-pack floor live spec. required.

16. Packing information

Fig 38. Packing information 1 tray

001aaj740

strap 46 mm from corner

tray

chamfer

PIN 1

chamfer

PIN 1

printed plano box

ESD warning preprinted

barcode label (permanent)

barcode label (peel-off)

QA seal

Hyatt patent preprinted

The straps around the package of

stacked trays inside the plano-box

have sufficient pre-tension to avoid

loosening of the trays.

In the traystack (2 trays)

only ONE tray type* allowed

*one supplier and one revision number.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

Fig 39. Packing information 5 tray

aaa-004952

PQ-label (permanent) bag

strap 46 mm from the corner

dry-agent

ESD warning preprinted

PQ-label (permanent)

dry-pack ID preprinted

strap

QA seal

relative humidity indicator

tray

preprinted:

recycling symbol

moisture caution label

ESD warning

manufacturer bag info

chamfer

printed plano box

PIN 1

PLCC52

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

Fig 40. Tray det ai ls

1.55

3.00

(0.30)

16.60±0.08+7°/S SQ.

1.20

0.56

3.32

(14.40+5°/S SQ.)

(1.45)

1.10

2.50

(0.64)

0.35

aaa-004949

AL AL AM AM

section BC-BC

scale 4:1

vacuum cell

section BD-BD

scale 4:1

section BA-BA

scale 4:1

detail AC

scale 20:1 section AJ-AJ

scale 2:1

section AR-AR

scale 2:1

section AL-AL

scale 5:1

section AK-AK

scale 5:1

section AM-AM

scale 4:1

section AN-AN

scale 4:1

end lock side lock

12.80-5°/S SQ.

14.20±0.08+10°/S SQ.

13.85±0.08+12°/S SQ.

BA C

0.50

BA C

0.50

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

Fig 41. Packin g in formation Reel

aaa-004950

tape

guard band

circular sprocket holes

opposite the label side of reel

cover tape

carrier tape

enlongated

circular

enlongated

PIN1 has to be

in quadrant 1

QA seal

preprinted ESD warning

PQ-label

dry-pack ID preprinted

(permanent)

product orientation

in carrier tape

product orientation ONLY for turned

products with 12nc ending 128

HOW TO SECURE LEADER END TO THE GUARD BAND,

HOW TO SECURE GUARD BAND

unreeling direction

(see: HOW TO SECURE)

PIN1

PIN1 PIN1

BGA

bare die BGA

bare die for SOT505-2

ending 125

for SOT765

ending 125

PIN1 PIN1 PIN1

PIN1 PIN1

QFP QFP

PLCCSO SO

(HV)QFN

(HV)SON

(H)BCC

(HV)QFN

(HV)SON

(H)BCC

see: ASSY REEL + LABELS

ASSY REEL + LABELS

label side embossed

ESD logo

embossed

ESD logo

tape

printed plano-box

Ø 330x12/16/24/32 (hub 7’’)

Ø 330x16/24/32/44 (hub 4’’)

Ø 330x44 (hub 6’’)

Ø 180x12/16/24

tapeslot

label side

trailer

leader

leader : lenght of trailer shall be 400 mm min.

and covered with cover tape

circular sprocket hole side

guard band

trailer : lenght of trailer shall be 160 mm min.

and covered with cover tape

tape

(with pull tabs on both ends)

guard band

lape double-backed

onto itself on both ends

Product data sheet

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NXP Semiconductors CLRC663

High performance NFC reader solution

17. Abbreviations

Ta ble 251. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

BPSK Binary Phase Shift Keying

CRC Cyclic Redundancy Check

CW Continuous Wave

EGT Extra Guard Time

EMC Electro Magnetic Compatibility

EMD Electro Magnetic Disturbance

EOF End Of Frame

EPC Electronic Product Code

ETU Elementary Time Unit

GPIO General Purpose Input/Output

HBM Human Body Model

I2C Inter-Integrated Circuit

IRQ Interrupt Request

LFO Low Frequency Oscillator

LPCD Low-Power Card Detection

LSB Least Significant Bit

MISO Mast er In Slave Out

MOSI Master Out Slave In

MSB Most Significant Bit

NRZ No t Return to Zero

NSS Not Slave Select

PCD Proximity Coupling Device

PLL Phase-Locked Loop

RZ Return To Zero

RX Receiver

SAM Secure Access Module

SOF Start Of Frame

SPI Serial Peripheral Interface

SW Software

TT imer Timing of the clk period

TX Transmitter

UART Universal Asynchronous Receiver Transmitter

UID Unique IDentification

VCO Voltage Controlled Oscil lator

Product data sheet

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High performance NFC reader solution

18. References

[1] Application note — MFRC52x Reader IC Family Directly Matc hed Antenna

Design

[2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity

Antennas

[3] BSDL File — Boundary scan description language file of the CLRC663

Product data sheet

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High performance NFC reader solution

19. Revision history

Table 252. Revision his tory

Document ID Release date Data sheet status Change notice Supersedes

CLRC663 v.4.0 20151029 Product data sheet - CLRC663 v.3.9

Modifications: •Table 248 “Characteristics”

–AVDD and DVDD min and max values added

–IDD(TVDD) max value updated to 250 mA

•Table 245 “Limiting values”: ITVDD max value updated to 270 mA

CLRC663 v.3.9 20150722 Product data sheet - CLRC663 v.3.8

Modifications: •Section 1 “General description”: updated

•Section 2 “Features and benefits”: updated

•Figure 13 “Connection to host with SPI”: updated

•Figure 22 “Register read and write access”: updated

CLRC663 v.3.7 20140204 Product data sheet - CLRC663 v.3.6

Modifications: •PVDD, TVDD data updated

•Information on FIFO size corrected

•Typing error corrected in description for LPCD

•WaterLevel and FIFOLength updated in register ove r view description

•WaterLevel and FIFOLength updated in register FIFOControl

•Waterlevel Register updated

•FIFOLength Register updated

•Section 8.15.2 “PinOut”: Pin Out register description corrected

CLRC663 v.3.6 20130910 Product data sheet - CLRC663 v.3.5

Modifications: •Update of EEPROM content (Table 40)

CLRC663 v.3.5 20120905 Product data sheet - CLRC663 v.3.4

Modifications: •Section 4 “Ordering information”: updated

•Section 16 “Packing information”: Figures added

•General update

CLRC663 v.3.4 20120717 Product data sheet - CLRC663 v.3.3

Modifications: •Table 46 “Predefined protocol overview TX[1]”: typo corrected

CLRC663 v.3.3 20120402 Product data sheet - CLRC663 v.3.2

Modifications: •Description of SAM support added

•General update

CLRC663 v.3.2 <tbd > Product data sheet - CLRC663 v.3.1

Modifications: •General update

•Specification status changed into “Product data sheet”

CLRC663 v.3.1 20110926 Preliminary data sheet - CLRC663 v.3.0

Modifications: •Specification status reversed from “Product data sheet” into “Preliminary data sheet”

CLRC663 v.3.0 20110919 Product data sheet - CLRC663 v.2.0

Product data sheet

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High performance NFC reader solution

Modifications: •Section 5 “Ordering information”: updated

•Section 8 “Functional description”. Section 9 “CLRC663 registers”: updated

•Section 8.7.2.1 “Product information and configu ration - Page 0”: updated

•Section 8.10.2 “Command set overview”: updated

•Table 18 “Command overview”, Table 57 “FIFOData register (address 05h);”Table 156

“RxCtrl bits”: updated

•Table 246 “Characteristics”: update d

CLRC663 v.2.0 20110615 Preliminary data sheet - CLRC663 v.1.0

Modifications: •General update

CLRC663 v.1.0 20110308 Ob jective data sheet - -

Table 252. Revision his tory …continued

Document ID Release date Data sheet status Change notice Supersedes

Product data sheet

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High performance NFC reader solution

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support , life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environment al

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with their

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessa ry

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property right s.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specifica tion.

Product data sheet

COMPANY PUBLIC Rev. 4.0 — 29 October 2015

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NXP Semiconductors CLRC663

High performance NFC reader solution

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It is neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifi cations, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semi conductors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-English (translated ) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

20.4 Licenses

20.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP Semi conductors N.V.

MIFARE — is a trademark of NXP Semiconductors N.V.

MIFARE Ultralight — is a trademark of NXP Semicon ductors N.V.

DESFire — is a trademark of NXP Semiconductors N.V.

MIFARE Plus — is a trademark of NXP Semiconductors N.V.

ICODE and I-CODE — are trademarks of NXP Semiconductors N.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

This NXP Semiconductors IC is I SO/IEC 14443 T ype B

software enabled and is licensed under Innovatron’s

Contactless Card p atents license for ISO/IEC 144 43 B.

The license includes the right to use the IC in systems

and/or end-user equipment.

RATP/Innovatron

Technology

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that co mplies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and IS O/IEC 21481

does not convey an implied license under any patent right infringed by

implementation of any of those standar ds. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other produ cts,

whether hardware or software.

Product data sheet

COMPANY PUBLIC Rev. 4.0 — 29 October 2015

171140 134 of 136

continued >>

NXP Semiconductors CLRC663

High performance NFC reader solution

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 6

7.1 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . 7

7.2 Timer module . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.1 Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.1.1 Time-Out- and Watch-Dog-Counter . . . . . . . . . 9

7.2.1.2 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.1.3 Stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.2.1.4 Programmable one-shot timer . . . . . . . . . . . . 10

7.2.1.5 Periodical trigger. . . . . . . . . . . . . . . . . . . . . . . 10

7.3 Contactless interface unit . . . . . . . . . . . . . . . 10

7.3.1 ISO/IEC14443A/MIFARE functionality . . . . . . 11

7.3.2 ISO/IEC14443B functionality . . . . . . . . . . . . . 13

7.3.3 FeliCa functionality . . . . . . . . . . . . . . . . . . . . . 14

7.3.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 14

7.3.4 ISO/IEC15693 functionality . . . . . . . . . . . . . . 15

7.3.5 EPC-UID/UID-OTP functionality. . . . . . . . . . . 16

7.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.3.6.1 Data encoding ICODE . . . . . . . . . . . . . . . . . . 16

7.3.7 ISO/IEC 18092 mode . . . . . . . . . . . . . . . . . . . 16

7.3.7.1 Passive communication mode . . . . . . . . . . . . 17

7.3.7.2 ISO/IEC 18092 framing and coding . . . . . . . . 18

7.3.7.3 ISO/IEC 18092 protocol support. . . . . . . . . . . 18

7.4 Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 18

7.4.1 Host interface configuration . . . . . . . . . . . . . . 18

7.4.2 SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.4.2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.4.2.2 Read data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.4.2.3 Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.4.2.4 Address byte. . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.4.2.5 Timing Specification SPI. . . . . . . . . . . . . . . . . 20

7.4.3 RS232 interface . . . . . . . . . . . . . . . . . . . . . . . 21

7.4.3.1 Selection of the transfer speeds. . . . . . . . . . . 21

7.4.3.2 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.4 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 23

7.4.4.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.4.4.2 I2C Data validity . . . . . . . . . . . . . . . . . . . . . . . 24

7.4.4.3 I2C START and STOP conditions. . . . . . . . . . 24

7.4.4.4 I2C byte format . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4.4.5 I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . 25

7.4.4.6 I2C 7-bit addressing. . . . . . . . . . . . . . . . . . . . 26

7.4.4.7 I2C-register write access . . . . . . . . . . . . . . . . 26

7.4.4.8 I2C-register read access . . . . . . . . . . . . . . . . 26

7.4.4.9 I2CL-bus interface . . . . . . . . . . . . . . . . . . . . . 27

7.4.5 SAM interface . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4.5.1 SAM functionality . . . . . . . . . . . . . . . . . . . . . . 28

7.4.5.2 SAM connection. . . . . . . . . . . . . . . . . . . . . . . 29

7.4.6 Bounda ry scan interface . . . . . . . . . . . . . . . . 29

7.4.6.1 Interface signals. . . . . . . . . . . . . . . . . . . . . . . 30

7.4.6.2 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . 30

7.4.6.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . 30

7.4.6.4 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . 31

7.4.6.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . 31

7.4.6.6 Data register . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.4.6.7 Boundary scan cell. . . . . . . . . . . . . . . . . . . . . 31

7.4.6.8 Boundary scan path. . . . . . . . . . . . . . . . . . . . 31

7.4.6.9 Boundary Scan Descri ption Language

(BSDL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.4.6.10 Non-IEEE1149.1 commands . . . . . . . . . . . . . 33

7.5 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5.2 Accessing the FIFO buffer . . . . . . . . . . . . . . . 33

7.5.3 Controlling the FIFO buffer . . . . . . . . . . . . . . 33

7.5.4 Status Information about the FIFO buffer. . . . 34

7.6 Analog interface and contactless UART . . . . 35

7.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.6.2 TX transmitter . . . . . . . . . . . . . . . . . . . . . . . . 35

7.6.2.1 Overshoot protection . . . . . . . . . . . . . . . . . . . 37

7.6.2.2 Bit generator . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.6.3 Receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 38

7.6.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.6.3.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 39

7.6.4 Active antenna concept . . . . . . . . . . . . . . . . . 40

7.6.5 Symbol generator. . . . . . . . . . . . . . . . . . . . . . 43

7.7 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.7.1 Memory overview. . . . . . . . . . . . . . . . . . . . . . 43

7.7.2 EEPROM memory organization. . . . . . . . . . . 44

7.7.2.1 Product information and configuration

- Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.7.3 EEPROM initialization content LoadProtocol. 47

7.8 Clock generation . . . . . . . . . . . . . . . . . . . . . . 49

7.8.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 49

7.8.2 IntegerN PLL clock line . . . . . . . . . . . . . . . . . 49

7.8.3 Low Frequency Oscillator (LFO) . . . . . . . . . . 50

7.9 Power management. . . . . . . . . . . . . . . . . . . . 51

7.9.1 Supply concept . . . . . . . . . . . . . . . . . . . . . . . 51

7.9.2 Power reduction mode. . . . . . . . . . . . . . . . . . 51

7.9.2.1 Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . 51

Product data sheet

COMPANY PUBLIC Rev. 4.0 — 29 October 2015

171140 135 of 136

continued >>

NXP Semiconductors CLRC663

High performance NFC reader solution

7.9.2.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 51

7.9.2.3 Modem off mode. . . . . . . . . . . . . . . . . . . . . . . 52

7.9.3 Low-Power Card Detection (LPCD) . . . . . . . . 52

7.9.4 Reset and start-up time . . . . . . . . . . . . . . . . . 52

7.10 Command set . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.10.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.10.2 Command set overview . . . . . . . . . . . . . . . . . 53

7.10.3 Command functionality. . . . . . . . . . . . . . . . . . 54

7.10.3.1 Idle command. . . . . . . . . . . . . . . . . . . . . . . . . 54

7.10.3.2 LPCD command . . . . . . . . . . . . . . . . . . . . . . . 54

7.10.3.3 Load key command . . . . . . . . . . . . . . . . . . . . 54

7.10.3.4 MFAuthent command . . . . . . . . . . . . . . . . . . . 54

7.10.3.5 AckReq command . . . . . . . . . . . . . . . . . . . . . 55

7.10.3.6 Receive command . . . . . . . . . . . . . . . . . . . . . 55

7.10.3.7 Transmit command. . . . . . . . . . . . . . . . . . . . . 55

7.10.3.8 Transceive command . . . . . . . . . . . . . . . . . . . 55

7.10.3.9 WriteE2 command . . . . . . . . . . . . . . . . . . . . . 55

7.10.3.10 WriteE2PAGE command . . . . . . . . . . . . . . . . 56

7.10.3.11 ReadE2 command . . . . . . . . . . . . . . . . . . . . . 56

7.10.3.12 LoadReg command . . . . . . . . . . . . . . . . . . . . 56

7.10.3.13 LoadProtocol command . . . . . . . . . . . . . . . . . 56

7.10.3.14 LoadKeyE2 command . . . . . . . . . . . . . . . . . . 58

7.10.3.15 StoreKeyE2 command . . . . . . . . . . . . . . . . . . 58

7.10.3.16 GetRNR command . . . . . . . . . . . . . . . . . . . . . 58

7.10.3.17 SoftReset command. . . . . . . . . . . . . . . . . . . . 58

8 CLRC663 registers. . . . . . . . . . . . . . . . . . . . . . 59

8.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 59

8.2 Command configuration . . . . . . . . . . . . . . . . . 62

8.2.1 Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3 SAM configuration register . . . . . . . . . . . . . . . 62

8.3.1 HostCtrl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.4 FIFO configuration register. . . . . . . . . . . . . . . 63

8.4.1 FIFOControl . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4.2 WaterLevel . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4.3 FIFOLength . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.4.4 FIFOData . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.5 Interrupt configuration registers . . . . . . . . . . . 65

8.5.1 IRQ0 register . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.5.2 IRQ1 register . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.5.3 IRQ0En register . . . . . . . . . . . . . . . . . . . . . . . 67

8.5.4 IRQ1En . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.6 Contactless interface configuration registers . 69

8.6.1 Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.6.2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.6.3 RxBitCtrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.6.4 RxColl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.7 Timer configuration registers . . . . . . . . . . . . . 73

8.7.1 TControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.7.2 T0Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.7.2.1 T0ReloadHi. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.7.2.2 T0ReloadLo . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.7.2.3 T0CounterValHi . . . . . . . . . . . . . . . . . . . . . . . 75

8.7.2.4 T0CounterValLo. . . . . . . . . . . . . . . . . . . . . . . 75

8.7.2.5 T1Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.7.2.6 T1ReloadHi . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.7.2.7 T1ReloadLo . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.7.2.8 T1CounterValHi . . . . . . . . . . . . . . . . . . . . . . . 77

8.7.2.9 T1CounterValLo. . . . . . . . . . . . . . . . . . . . . . . 77

8.7.2.10 T2Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.7.2.11 T2ReloadHi . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.7.2.12 T2ReloadLo . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.7.2.13 T2CounterValHi . . . . . . . . . . . . . . . . . . . . . . . 79

8.7.2.14 T2CounterValLoReg . . . . . . . . . . . . . . . . . . . 79

8.7.2.15 T3Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.7.2.16 T3ReloadHi . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.7.2.17 T3ReloadLo . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.7.2.18 T3CounterValHi . . . . . . . . . . . . . . . . . . . . . . . 81

8.7.2.19 T3CounterValLo. . . . . . . . . . . . . . . . . . . . . . . 81

8.7.2.20 T4Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.7.2.21 T4ReloadHi . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.7.2.22 T4ReloadLo . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.7.2.23 T4CounterValHi . . . . . . . . . . . . . . . . . . . . . . . 83

8.7.2.24 T4CounterValLo. . . . . . . . . . . . . . . . . . . . . . . 83

8.8 Transmitter configuration registers. . . . . . . . . 84

8.8.1 TxMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.8.2 TxAmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.8.3 TxCon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.8.4 Txl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.9 CRC configuration registers. . . . . . . . . . . . . . 86

8.9.1 TxCrcPreset. . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.9.2 RxCrcCon . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.10 Transmitter configuration registers. . . . . . . . . 88

8.10.1 TxDataNum . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.10.2 TxDATAModWidth . . . . . . . . . . . . . . . . . . . . . 88

8.10.3 TxSym10BurstLen . . . . . . . . . . . . . . . . . . . . . 89

8.10.4 TxWaitCtrl . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.10.5 TxWaitLo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.11 FrameCon . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.12 Receiver configuration registers . . . . . . . . . . 92

8.12.1 RxSofD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.12.2 RxCtrl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.12.3 RxWait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.12.4 RxThreshold. . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.12.5 Rcv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.12.6 RxAna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.13 Clock configuration . . . . . . . . . . . . . . . . . . . . 96

8.13.1 SerialSpeed . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.13.2 LFO_Trimm . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.13.3 PLL_Ctrl Register. . . . . . . . . . . . . . . . . . . . . . 97

8.13.4 PLLDiv_Out . . . . . . . . . . . . . . . . . . . . . . . . . . 98

NXP Semiconductors CLRC663

High performance NFC reader solution

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 October 2015

171140

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

8.14 Low-power card detection configuration

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.14.1 LPCD_QMin . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.14.2 LPCD_QMax . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.14.3 LPCD_IMin. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.14.4 LPCD_Result_I. . . . . . . . . . . . . . . . . . . . . . . 100

8.14.5 LPCD_Result_Q. . . . . . . . . . . . . . . . . . . . . . 100

8.15 Pin configuration. . . . . . . . . . . . . . . . . . . . . . 100

8.15.1 PinEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8.15.2 PinOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8.15.3 PinIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.15.4 SigOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.16 Protocol configuration registers . . . . . . . . . . 103

8.16.1 TxBitMod . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.16.2 TxDataCon . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.16.3 TxDataMod. . . . . . . . . . . . . . . . . . . . . . . . . . 104

8.16.4 TxSymFreq. . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.16.5 TxSym0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8.16.6 TxSym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8.16.7 TxSym2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8.16.8 TxSym3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8.16.9 TxSym10Len . . . . . . . . . . . . . . . . . . . . . . . . 108

8.16.10 TxSym32Len . . . . . . . . . . . . . . . . . . . . . . . . 108

8.16.11 TxSym10BurstCtrl . . . . . . . . . . . . . . . . . . . . 108

8.16.12 TxSym10Mod Reg . . . . . . . . . . . . . . . . . . . . 109

8.16.13 TxSym32Mod . . . . . . . . . . . . . . . . . . . . . . . . 110

8.17 Receiver configuration . . . . . . . . . . . . . . . . . 11 0

8.17.1 RxBitMod . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

8.17.2 RxEofSym. . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.17.3 RxSyncValH . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.17.4 RxSyncValL . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.17.5 RxSyncMod . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.17.6 RxMod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8.17.7 RxCorr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8.17.8 FabCali . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4

8.18 Version register . . . . . . . . . . . . . . . . . . . . . . . 114

8.18.1 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 11 5

10 Recommended operating conditions. . . . . . 115

11 Thermal characteristics . . . . . . . . . . . . . . . . 115

12 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11 5

12.1 Timing characteristics. . . . . . . . . . . . . . . . . . 118

13 Application information. . . . . . . . . . . . . . . . . 120

13.1 Antenna design description . . . . . . . . . . . . . 120

13.1.1 EMC low pass filter. . . . . . . . . . . . . . . . . . . . 121

13.1.2 Antenna matching. . . . . . . . . . . . . . . . . . . . . 121

13.1.3 Receiving circuit . . . . . . . . . . . . . . . . . . . . . . 121

13.1.4 Antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 122

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 123

15 Handling information . . . . . . . . . . . . . . . . . . 124

16 Packing information . . . . . . . . . . . . . . . . . . . 124

17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 128

18 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 129

19 Revision history . . . . . . . . . . . . . . . . . . . . . . 130

20 Legal information . . . . . . . . . . . . . . . . . . . . . 132

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . 132

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 132

20.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

20.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 133

21 Contact information . . . . . . . . . . . . . . . . . . . 133

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:

CLRC66302HN,118 CLRC66302HN,157 CLRC66302HN,151