Preliminary Specification
Supersedes PNX1300 data of 2001 Oct 12
File unde r INTEG RATE D CIRCUITS, TR1
2002 Feb 15
INTEGRATED CIRCUITS
PNX1300 Series
Medi a Processor s
2002 Feb 15
Philips Se m ico nductors P reli minary Spe cifi ca t ion
Media Processors PNX1300 Series
PNX 1300 Series Data Book
Foreword
Table of Content s
1Pin List
2Overview
3DSPCPU Architecture
4Custom O perations for Mu ltimedia
5Cache Architecture
6Video In
7Enhanced V ideo Out
8Audio In
9Audio Out
10 SPDIF Out
11 PCI Interface
12 SD R AM Me mo ry Sy st e m
13 System Boot
14 Image Coprocessor
15 Variable Length Decoder
16 I2C Interface
17 Synchronous S eria l Interface
18 JTAG Functional Specification
19 On-Chip S emaph ore Assist Device
20 Arbiter
21 Power Managem ent
22 PCI - XIO Bus Functional Specifica tion
ADSPCPU Operations
BMMIO Register S ummary
CEndian-ness
Index
Preliminary Specification
2001 Phi lips Electronics North America Corporation
All rig hts reserved.
See Terms and Conditions on the next page.
2002 Feb 15
TERMS AND CONDITIONS
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes,
without notice, in the products, including circuits, standard cells, and/or software, described or contained
herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or
liability for the use of any of these products, conveys no license or title under a ny pat ent , co pyrigh t , o r most
work right to these products, an d makes no repres entations or warranties that these pr oducts are free from
pat e nt , copyr i ght , or mos t w ork ri ght inf rin ge me nt, unle ss oth erw i se spec if ie d. Appl ic at ions tha t ar e de sc rib ed
herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIF E SU PPO R T APPLICATI ONS
Philips Semiconductors and Philips Electronics North America Corporation products are not designed for use
in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips
Electronics North America Corporation product can reasonably be expected to result in a personal injury.
Phi lips Semico nductors and Philips E lectronics N or th Amer ica C or poration cu stomers using or s elling Philips
Semiconductors and Philips Electronics North America Corporation products for use in such applications do
s o at t h eir own risk and a gre e t o fu ll y i nd emnif y Phil ips S e mi condu ct ors an d Phi l ips E le ct ron ic s No rth Amer ica
Corporation for any damages resulting from improper use or sale.
Phi li ps Se m ic ondu c t ors an d Phili ps Ele ctr on ic s Nor th Am erica C orporat i on re gis ter elig ib le c ir c u its u nd e r the
Semiconductor Chips Protection Act.
2001, 2002 Philips Electronics North America Corporation
All rights reserved.
Printed in U.S.A.
Business Line Media Processing, 811 E. Arques Avenue, Sunnyvale, CA 94088
DEFINITIONS
Data Sheet
Id en tifi c ati on Pr odu ct Status Defi n i tion
Obje ctive
Specification For mati ve or in
Design This data sheet contains the design target or goal specifications for product
development. Spec ifi cat ions may change in any manner without notic e.
Preliminary
Specification Preproduction
Product This data sheet contains preliminary data, and supplementary data will be pub-
lished at a later date. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the
best possible product.
Product
Specification Full
Production This data sheet contains Final Specifications. Philips Semiconductors reserves
the right to make changes at any time without notice, in order to improve the
design and supply the best possible product.
Terms and Conditions
PRELIMINARY INFORMATION 1
Foreword
The TriMedia PNX1300 Series is an enhanced version
of th e T M-1300 family of media processor.
The PNX1 300 Ser ies conta ins an u lt ra-h igh per forma nce
Ver y Lo ng In st ruct i on Word proces so r , as w ell a s a c om-
ple t e int e llig en t vi de o and audi o inpu t/ o utpu t su bsy stem.
The processor has an instruction set that is optimized for
process ing audio, vid eo and graphics. It incl udes power-
ful SIM D mult imedi a op erator s for eig ht- and 16-bit signal
datatypes as well as a full complement of 32-bit IEEE
compatible floating point operations.
The PNX1300 Series is intended as a multi-standard
programmable video, audio and graphics processor. It
can either be used standalone, or as an accelerator to a
gener al pur p ose pr o ces sor .
The architecture of the TriMedia family came about as
the result of many years of effort of many dedicated indi-
viduals. Going back in history, the origin of TriMedia was
laid by the LIFE-1 VLIW processor, designed by Junien
Labrousse and myself in 1987. Work continued after-
wards in Philips Research Labs, Palo Alto. My special
thanks go to the entire Palo Alto research team: Mike
Ang, Uzi Bar-Gadda, Peter Donovan, Martin Freeman,
Eino Jacobs, Beomsup Kim, Bob Law, Yen Lee, Vijay
Mehra, Pieter van der Meulen, Ross Morley, Mariette
Parekh, Bill Sommer, Artur Sorkin and Pierre Uszynski.
The Palo Alto period matured the architecture—we port-
ed a ll vi deo an d audio algo rithms that we could f ind to the
c ompil er /s imu la t or an d r e fine d t h e oper a tio n se t. In ad di-
ti on , we lear ne d how to g iv e t he arc hite ct ure a mar ke t di-
re ct io n. In May 1994 , Phil i ps manag em en t—i n par t ic ular
Cees-Jan Koomen, Eddy Odijk, Theo Claasen and Doug
Dunn—decided to develop TriMedia into a major Philips
Se miconduc t ors pr od u c t l ine.
Und er t he gu idan ce o f Ke ith F lag ler, t he T riMed ia team
was bu ilt. Al l of the m cont ribute d to ta ke this fr om a se t
of inte r es ting idea s to a r eliable and co mp etiti ve product
in a short period of time. The initial TriMedia team includ-
ed Fuad Abu Nofal, Karel Allen, Mike Ang, Robert Aqui-
no, Manju Asthana, Patrick de Bakker, Shiv Balakrish-
nan, Jai Bannur, Marc Berger, Sunil Bhandari, Rusty
Biesele, Ahmet Bindal, David Blakely, Hans Bouw-
meester, Steve Bowden, Robert Bradfield, Nancy
Breede, Shawn Brown, Sujay Chari, Catherine Chen,
Howen Chen, Yan-ming Chen, Yong Cho, Scott Clapper,
Matthew Clayson, Paul Coelho, Richard Dodds, Marc
Duranton, Darcia Eding, Aaron Emigh, Li Chi Feng, Keith
Fla gle r, Jean Gobert , Sergio Golom bek, Mike Gr imwo od,
Yudi Halim, Hari Hampapuram, Carl Hartshorn, Judy
Heider, Laura Hrenko, Jim Hsu, Eino Jacobs, Marcel
Janssens, Patricia Jones, Hann-Hwan Ju, Jayne Keith,
Bhushan Kerur, Ayub Khan, Keith Knowles, Mike Kong,
Ashok Krishnamurti, Yen Lee, Patrick Leong, Bill Lin,
Laura Ling, Chialun Lu, Naeem Maan, Nahid Mansipur,
Mike Maynard, Vijay Mehra, Jun Mejia, Derek Meyer,
Prabir Mohanty, Saed Muhssin, Chris Nelson, Stephen
Ness, Keith Ngo, Francis Nguyen, Kathleen Nguyen,
Derek Noonburg, Ciaran O’Donnel, Sang-Ju Park,
Ch arles P epli nski , Gene Pink ston , Marya m Piray ou, Par-
dha Potana, Bill Price, Victor Ramamoorthy, Babu Rao
Kandamilla, Ehsan Rashid, Selliah Rathnam, Margaret
Redmond, Donna Richardson, Alan Rodgers, Tilakray
Roychoudhury, Hani Salloum, Chris Salzmann, Bob
Seltzer, Ravi Selvaraj, Jim Shimandle, Deepak Singh,
Bill Sommer, Juul van der Spek, Manoj Srivastava, Ren-
ga Sundararajan, Ken-Sue Tan, Ray Ton, Steve Tran,
Cynthia Tripp, Ching-Yih Tseng, Allan Tzeng, Barbara
Ven delin , John Vivi t, Rud y Wang, Rogier West er, Wa yne
Wonchoba, Anthony Wong, Sara Wu, David Wyland,
Ken Xie, Vincent Xie, Bettina Yeung, Robert Yin, Charles
Yo un g, Grac e Y un , E le na Zela yeta an d V iv ia n Zh u.
Expert help and feedback was received from many. In
particular, I’d like to mention Kees van Zon of Philips
Eindhoven for the help with filtering-related issues, and
Craig Clapp of PictureTel for excellent feedback on all
aspec t s of the ar chi t ec t ure.
My s p ec ial tha nk s go to J o e Kost e lec . H e ma de m e un -
derstand that my ambitions could better be realized in
Ca lifor nia tha n in Europ e. Fur the rmor e, his visi on an d his
wisdom are credited with keeping this project alive and
gro w in g un til the ‘in v estm ent dec is ion.’
The vision of a universal media accelerator is credite d to
J aap de Hoog. Jaap, I wish you were here to see it come
to fruiti on .
–Ge r rit S la v en bu r g
Af te r th e i ni tia l T M- 100 0 pr o duc t, the TM -11 00 , TM-1 30 0
and now PNX1300 Series chips have been successfully
int egr ated in man y video and audio p roducts. It has been
my pleasure to have been invol ved in these des igns and
would like to thank the people involved in TM-1300 and
PNX1300 Series projects under the guidande of Cees
Hartgring and Simon Wegerif. The team included Karel
Allen, Tien-Cheng Bau, Jim Campbell, Anitamk Chan,
John Chang, Roel Coppoolse, Taufik Dakhil, Mitch Dani-
il, Nam Dao, Patrick Debaumarche, Thuy Duong, Tor-
sten Fink, Jan Grotenbreg, Mohammad Hafeez, Feng
Hao, Farah Jubran, Babu Rao Kandamalla, Aki Kaniel,
Yan -Li ng Li, Ying- Cha o L iu , N aee m Maa n, Do n Ma rsha l,
Thomas Meyer, Javed Mukarram, Long Nguyen, Tu
Nghiem, Elaine Out ler, Charles Peplinski, Duc T. Pham,
Thorwald Rabeler, Raquel Ruiz, Ensieh Saffari, Hani
Salloum, Wenyi Song, Stephen Tomasello, Tran Tung,
Maria F. Wangsahamidjaja, Chang-Ming Yang, Moham-
med I. Yousuf, Hui Zhang and Gerrit Slaven burg.
- Luis Lucas
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
2 PRELIMINARY INFORMATION
PRELIMINARY SPECIFICATION 3
Table of Contents
Foreword
1Pin List
1.1 PNX1300 Series versus TM-1300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Boundary Scan Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -1
1.3 I/O Circuit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.4 Signal Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.5 Power Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6 Pin Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.7 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.9 Parametric Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9.1 PNX1300/01/02/11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9.2 PNX1300/01/02 Operating Range and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9.3 PNX1311 Operating Range and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9.4 PNX1300/01/02/11 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9.5 PNX1300/01/02 DC/AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.9.6 PNX1311 DC/AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.9.7 PNX1300 Series Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.9.7.1 Power Consumption for Applications on PNX1300 Series . . . . . . . . . . . . . . . . . . . . . . 1-13
1.9.7.2 PNX 1300/0 1/02 DSPCP U Core Current and Power Consum ption . . . . . . . . . . . . . . . . 1-14
1.9.7.3 PNX1311 DSPCPU Core Current and Power Consumption Details . . . . . . . . . . . . . . . 1-14
1.9.7.4 PNX 1300/01/02 Current Consump tion For On-Chi p Peripherals . . . . . . . . . . . . . . . . . 1-15
1.9.7.5 PNX1311 Current Consumption For On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . 1-16
1.9.7.6 STRG3, STRG5 type I/O circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.9.7.7 NORM3 type I/O circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.9.7.8 WEAK5 type I/O circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.9.7.9 IICOD (I2c) type I/O circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.9.7.10 SDRAM interface timing for PNX1300/01/02/11 speed grades. . . . . . . . . . . . . . . . . . 1-18
1.9.7.11 PCI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.9.7.12 JTAG I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.9.7.13 I2C I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.9.7.14 Video In I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.9.7.15 Video Out I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.9.7.16 AudioIn I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.9.7.17 Audio Out I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.9.7.18 SSI I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
4 PRELIMINARY SPECIFICATION
2Overview
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 PNX1300 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 PNX1300 Chip Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.4 Brief Examples of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4.1 Video Decompression in a PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4.2 Video Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5 Introduction to PNX1300 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3
2.5.1 Internal ‘Data Highway’ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5.2 VLIW Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4
2.5.3 Video In Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5.4 Enhanced Video Out Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5.5 Image Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5.6 Variable-Length Decoder (VLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5.7 Audio In and Audio Out Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5.8 S/PDIF Out Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5.9 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5.10 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -6
2.6 New In PNX1300 (Versus TM-1300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 New In PNX1300 (Versus TM-1100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.8 New In PNX1300 (Versus TM-1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
3 DSPCPU Architecture
3.1 Basic Architecture Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.2 Basic DSPCPU Execution Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -2
3.1.3 PCSW Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.4 SPC and DPC—Source and Destination Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.5 CCCOUNT—Clock Cycle Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.6 Boolean Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -3
3.1.7 Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.8 Floating Point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.9 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.10 Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 Guarding (Conditional Execution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.2 Load and Store Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.3 Compute Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4 Special-Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.5 Control-Flow Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -6
Philips Semiconductors
PRELIMINARY SPECIFICATION 5
3.3 PNX1300 Instruction Issue Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 Memory and MMIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.2 The Memory Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.3 MMIO Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5 Special Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.2 EXC (Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.3 INT and NMI (Maskable and Non-Maskable Interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.3.1 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.3.2 Interrupt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.5.3.3 Device interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.5.3.4 Interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.5.3.5 Interrupt masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.5.3.6 Software interrupts and acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.5.3.7 NMI sequentialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.5.3.8 Interrupt source assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.6 PNX1300 to Host Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7 Host to PNX1300 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.9 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.9.1 Instruction Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.9.2 Data Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
4 Custom Operation s for Multimedia
4.1 Custom OperationS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Custom Operation Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Introduction to Custom Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.3 Example Uses of Custom Ops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2 Example 1: Byte-Matrix Transposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Example 2: MPEG Image Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4 Example 3: Motion-Estimation Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4.1 A Simple Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4.2 More Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
5 Cache Architecture
5.1 Memory System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 DRAM Aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.1 General Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.2 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
6 PRELIMINARY SPECIFICATION
5.3.3 Miss Processing Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.4 Replacement Policies, Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.5 Alignment, Partial-Word Transfers, Endian-ness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.6 Dual Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.7 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.8 Memory Hole and PCI Aperture Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.9 Non-cacheable Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.10 Special Data Cache Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.10.1 Copyback and invalidate operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.10.2 Data cache tag and status operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.10.3 Data cache allocation operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3.10.4 Data cache prefetch operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3.11 Memory Operation Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3.12 Operation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.13 MMIO Register References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.14 PCI Bus References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.15 CPU Stall Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.16 Data Cache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4.1 General Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -8
5.4.2 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4.3 Miss Processing Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4.4 Replacement Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4.5 Location of Program Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4.6 Branch Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -9
5.4.7 Coherency: Special iclr Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4.8 Reading Tags and Cache Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4.9 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4.10 Instruction Cache Initialization and Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5 LRU Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.5.1 Two-Way Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6.1 Example 1: Data-Cache/Input-Unit Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6.2 Example 2: Data-Cache/Output-Unit Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6.3 Example 3: Instruction-Cache/Data-Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5. 6.4 Ex amp le 4 : Ins t ru ction- Ca che/Inpu t- Un it Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6.5 Four-Way Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6.6 LRU Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.6.7 LRU Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.6.8 LRU for the Dual-Ported Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Philips Semiconductors
PRELIMINARY SPECIFICATION 7
5.7 Performance Evaluation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.8 MMIO Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
6 Video In
6.1 video in overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.2 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.3 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.4 Hardware and Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 Fullres Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4 Halfres Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.5 Raw Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.6 Message-Passing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.1 VI_DVALID in Message Passing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.7 Highway Latency and HBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
7 E nh an ced Vid eo Out
7.1 Enhanced Video Out Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.3 Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.4 Function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.4.1 Detailed Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4.2 Summary of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.5 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -2
7.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.7 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.8 Image Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.8.1 CCIR 656 Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.8.2 CCIR 656 Line Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.8.3 SAV and EAV Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.8.4 Video Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.8.5 CCIR 656 Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.9 Enhanced Video Out Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.9.1 Active Video Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.9.2 SAV and EAV Overlap Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.9.3 Control of Frame and Image Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.9.4 Horizontal and Frame Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.10 Genlock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.11 Data Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.12 Image Data Memory Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
8 PRELIMINARY SPECIFICATION
7.12.1 Video Image Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7. 12 .2 Planar Storage o f V ideo I mage Data i n Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.12.3 Graphics Overlay Image Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.13 Video Image Conversion Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 10
7.13.1 YUV 4:2:2 Interspersed to YUV 4:2:2 Co-sited Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.13.2 YUV 4:2:0 to YUV 4:2:2 Co-sited Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.13.3 YUV-2x Upscaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.13.4 Pixel Mirroring for Four-tap Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.14 EVO Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.15 Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.15.1 Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.15.2 Chroma Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.15.3 Programmable Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.16 MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.16.1 VO Status Register (VO_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.16.2 VO Control Register (VO_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.16.3 VO-Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.16.4 EVO Control Register (EVO_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.16.5 EVO-Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.17 Enhanced Video Out Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.17.1 Video Refresh Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.18 Frame and field timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.18.1 Recommended values for timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.18.2 Data-transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.18.3 Interrupts and Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.18.4 Latency and Bandwidth Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
7.18.5 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
7.19 DDS and PLL Filter Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
8 Au dio In
8.1 Audio In Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.3 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.3.1 PNX1300 Improved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.3.2 TM-1000 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.4 Clock System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.5 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.6 Memory Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 4
8.7 Audio In Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.8 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.9 Highway Latency and HBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Philips Semiconductors
PRELIMINARY SPECIFICATION 9
8.10 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.11 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
9 Au dio Out
9.1 Audio Out Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.3 Summary of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -2
9.4 Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.4.1 PNX1300 Standard Improved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.4.2 TM-1000 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.5 Clock System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.6 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -4
9.6.1 Serial Frame Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.6.2 I2S Serial Framing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.7 Codec Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.8 Memory Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -7
9.9 Audio Out Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.11 Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.12 powerdown and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.13 Highway Latency and HBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.14 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
10 SPD IF O ut
10.1 SPDIF Out Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-1
10.2 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 Summary of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3.1 SPDIF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3.2 Transparent DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.4 IEC-958 Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.5 IEC-958 Bit Cell and Pre-amble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.6 IEC-958 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.7 IEC-958 Memory Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.8 Sample Rate Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.9 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.10 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.11 DMA Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.13 Timestamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.14 MMIO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.15 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
10 PRELIMINARY SPECIFICATION
10.16 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.17 HBE and Highway Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.18 Literature References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
11 PCI Interface
11.1 PCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 PCI Interface as an Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 DSPCPU Single-Word Loads/Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 I/O Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.3 Configuration Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4 DMA Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3 PCI Interface as a Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4 Transaction Concurrency, Priorities, and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5 Registers Addressed in PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-3
11.5.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5.5 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.5.6 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.5.7 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.5.8 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.5.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-7
11.5.10 Built-In Self Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.5.11 Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.5.12 Subsystem ID, Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.13 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.16 Max_Lat, Min_Gnt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6 Registers in MMIO Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6.1 DRAM_BASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6.2 MMIO_BASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6.3 MMIO/DRAM_BASE updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.6.4 BIU_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.5 BIU_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.6 PCI_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6.7 PCI_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-1 2
11.6.8 CONFIG_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-1 2
11.6.9 CONFIG_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.6.10 CONFIG_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-1 3
Philips Semiconductors
PRELIMINARY SPECIFICATION 11
11.6.11 IO_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.6.12 IO_DATA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.6.13 IO_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.6.14 SRC_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.6.15 DEST_ADR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.6.16 DMA_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.6.17 INT_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.7 PCI Bus Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.7.1 Single-Data-Phase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.7.2 Multi-Data-Phase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.8 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8.1 Bus Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8.2 No Expansion ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8.3 No Cacheline Wrap Address Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8.4 No Burst for I/O or Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
11.8.5 Word-Only MMIO Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 17
12 SDRAM Mem or y System
12.1 New in PNX1300/01/02/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 PNX1300 Main Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.3 Main-Memory Address Aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.4 Memory Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.4.1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.4.2 SGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.5 Memory Granularity and Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.6 Memory System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.6.1 MM_CONFIG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.6.2 PLL_RATIOS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.7 Memory Interface Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2-5
12.8 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.8.1 Address Mapping in 32-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.8.2 Address Mapping in 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.9 Memory Interface and SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.10 On-Chip SDRAM Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.11 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.12 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.13 Output Driver Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.14 Signal Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.15 Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.15.1 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.15.2 Specific Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
12 PRELIMINARY SPECIFICATION
12.15.3 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.16 Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2-8
12.16.1 Main AC Parameter requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.17 Example Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.17.1 Block Diagrams for a 32-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.17.1.1 16-Mbit Devices or Less . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.17.1.2 64-Mbit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.17.1.3 128-Mbit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.17.1.4 256-Mbit Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.17.2 Block Diagrams for a 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
13 Syst em Boot
13.1 Boot Sequence Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Boot Hardware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 .1 Boot P roced u re Com mon to Bo th Auton om ous and H ost-Ass iste d Boo ts tra p . . . . . . . . . . . . 13-2
13.2 .2 Initia l D SPCPU Progra m Load fo r Auto nom ou s Boots tra p . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3-5
13.3 Host-Assisted Boot Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.1 Stage 1: PNX1300 System Boot Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.2 Stage 2: Host-System PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.3 Stage 3: PNX1300 Driver Executing on the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4 Detailed EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.5 EEPROM Access Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
14 Image Coprocessor
14.1 Image Coprocessor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2.2 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2.3 Image Size and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4-3
14.4 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.1 Image Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.1.1 YUV 4:2:2 Co-Sited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.1.2 YUV 4:2:2 Interspersed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.1.3 YUV 4:2:0 XY Interspersed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.1.4 YUV 4:1:1 Co-Sited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.4.2 Image Overlay Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.4.3 Alpha Blending Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.4.4 Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.5 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4-6
Philips Semiconductors
PRELIMINARY SPECIFICATION 13
14.5.2 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.5.3 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.5.4 YUV to RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.5.5 Overlay and Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.5.6 Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.5.7 Implementation Overview: Horizontal Scaling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.5.7.1 Loading the extra pixels in the filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.7.2 Mirroring pixels at the ends of a line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.7.3 Horizontal filter SDRAM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.8 Implementation Overview: Vertical Scaling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.5.8.1 Mirroring lines at the ends of an image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.8.2 Vertical filter SDRAM block timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.9 Horizontal Scaling and Filtering for RGB Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.9.1 YUV sequence counter in YUV 4:2:2 output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.9.2 PCI output block timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.6 Operation and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.6.1 ICP Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.6.2 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.6.3 ICP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
14.6.4 ICP Microprogram Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
14.6.5 ICP Processing Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
14.6.6 Priority Delay and ICP Minimum Bus Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
14.6.7 ICP Parameter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.6.8 Load Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.6.9 Horizontal Filter - SDRAM to SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- 22
14.6.9.1 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.6.9.2 Parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.6.9.3 Control word format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
14.6.10 Vertical Filter - SDRAM to SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
14.6.10.1 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
14.6.10.2 Parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
14.6.10.3 Control word format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
14.6.11 Horizontal Filter with RGB/YUV Conversion to PCI or SDRAM . . . . . . . . . . . . . . . . . . . . . . 14-25
14.6.11.1 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
14.6.11.2 Parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.6.11.3 Control word format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
15 Variable Length Decoder
15.1 VLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 VLD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.3 Decoding up to A slice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
14 PRELIMINARY SPECIFICATION
15.4 VLD Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.5 VLD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.5.1 Macroblock Header Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.5.2 Run-Level Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.6 VLD Time Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.7 MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.7.1 VLD Status (VLD_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.7.2 VLD Interrupt Enable (VLD_IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.7.3 VLD Control (VLD_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.8 VLD DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.8.1 DMA Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.8.2 Macroblock Header Output DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.8.3 Run-Level Output DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.9 VLD Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.9.1 VLD Command (VLD_COMMAND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.9.2 VLD Shift Register (VLD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.9.3 VLD Quantizer Scale (VLD_QS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.9.4 VLD Picture Info (VLD_PI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.10 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5-8
15.11 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.12 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5-8
15.13 Endian-ness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.14 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
16 I2C Interface
16.1 I2C Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Compared TO TM-1000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.3 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.4 I2C Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.4.1 IIC_AR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.4.2 IIC_DR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4.3 IIC_SR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.4.4 IIC_CR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.5 I2C Software Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6-5
16.6 I2C Hardware Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.6.1 Slave NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.7 I2C Clock Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
17 Synchronous Serial Interf ace
17.1 Synchronous Serial Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
Philips Semiconductors
PRELIMINARY SPECIFICATION 15
17.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.3.1 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.3.2 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.3 SSI Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.4 SSI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.4 SSI Transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.1 Setup SSI_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.2 Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.3 Interrupt and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.5 SSI Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5.1 Setup SSI_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5.2 Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5.3 Interrupt and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.6 Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.7 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-7
17.8 16-bit Endian-ness and Shift Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.9 SSI Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.9.1 Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.9.2 Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.10 MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.10.1 SSI Control Register (SSI_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.10.2 SSI Control/Status Register (SSI_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.11 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.12 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
18 JTAG Functional Specification
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2.2 PNX1300 JTAG Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3 Using JTAG for PNX1300 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3.1 JTAG Instruction and Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.2 JTAG Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.3 Example Data Transfer Via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.3.1 Transferring data to TriMedia via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.3.2 Transferring data from TriMedia via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.3.4 JTAG Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
19 On-Chip Semaphore Assist Device
19.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
16 PRELIMINARY SPECIFICATION
19.2 SEM Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.3 Constructing a 12-Bit ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.4 Which SEM to Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.5 Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
20 Arbiter
20.1 Arbiter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 Dual Priorities with Priority Raising Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.3 Round Robin Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.3.1 Weighted Round Robin Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.3.2 Arbitration Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.4 Arbiter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.5 Arbiter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.5.1 Latency Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0-5
20.5.2 Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.6 Extended Behavior Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.6.1 Extended Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.6.2 Extended Latency Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.6.3 Raising Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
21 Power Management
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 Entering and Exiting Global Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.3 Effect Of Global Power Down On Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.4 Detailed Sequence of Events For Global Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.5 MMIO Register POWER_DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1-2
21.6 Block Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
22 PCI-XIO External I/O Bus
22.1 Summary Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-1
22.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.3 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-5
22.4.1 PCI-XIO Bus Interface Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.4.1.1 Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.1.2 68K Bus I/O device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.1.3 x86/ISA Bus I/O device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.4.1.4 Multiple Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.5 XIO_CTL MMIO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Philips Semiconductors
PRELIMINARY SPECIFICATION 17
22.5.1 PCI_CLK Bus Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.5.2 Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.6 PCI-XIO Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.7 PCI-XIO Bus Controller Operation and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
A PNX1300/01/02/11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPCPU Op erations
A.1 Alphabetic Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Operation List By Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
alloc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
allocd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
allocr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
allocx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
asl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
asli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
asr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
asri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
bitand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
bitandinv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
bitinv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
bitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
bitxor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16
borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -17
carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
curcycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
dcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
dinvalid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
dspiabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
dspiadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
dspidualabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
dspidualadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
dspidualmul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
dspidualsub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-28
dspimul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-29
dspisub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30
dspuadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
dspumul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-32
dspuquadaddui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-33
dspusub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-34
dualasr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-35
PNX1300/01/ 02/11 Dat a Book Philips Semiconductors
18 PRELIMINARY SPECIFICATION
dualiclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-36
dualuclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-37
fabsval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-38
fabsvalflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-39
fadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-40
faddflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-41
fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-42
fdivflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 43
feql . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-44
feqlflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-45
fgeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-46
fgeqflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-47
fgtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-48
fgtrflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 49
fleq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-50
fleqflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-51
fles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-52
flesflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 53
fmul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-54
fmulflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-55
fneq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-56
fneqflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-57
fsign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-58
fsignflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-59
fsqrt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-60
fsqrtflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-61
fsub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-62
fsubflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-63
funshift1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 64
funshift2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 65
funshift3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 66
h_dspiabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-67
h_dspidualabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-68
h_iabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-69
h_st16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 70
h_st32d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 71
h_st8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-72
hicycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -73
iabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-74
iadd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-75
Philips Semiconductors
PRELIMINARY SPECIFICATION 19
iaddi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-76
iavgonep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -77
ibytesel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-78
iclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-79
iclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-80
ident . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-81
ieql . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-82
ieqli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-83
ifir16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-84
ifir8ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-85
ifir8ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-86
ifixieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 87
ifixieeeflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-88
ifixrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-89
ifixrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -90
iflip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-91
ifloat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-92
ifloatflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -93
ifloatrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 94
ifloatrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-95
igeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -96
igeqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-97
igtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-98
igtri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-99
iimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-100
ijmpf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-101
ijmpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-102
ijmpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-103
ild16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-104
ild16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-105
ild16r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-106
ild16x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-107
ild8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-108
ild8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-109
ild8r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-110
ileq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-111
ileqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-112
iles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-113
ilesi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-114
imax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-115
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imin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-116
imul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-117
imulm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-118
ineg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-119
ineq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-120
ineqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-121
inonzero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-122
isub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-123
isubi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-124
izero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-125
jmpf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-126
jmpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-127
jmpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-128
ld32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-129
ld32d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-130
ld32r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-131
ld32x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-132
lsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-133
lsli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-134
lsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-135
lsri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-136
mergedual16lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-137
mergelsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-138
mergemsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-139
nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-140
pack16lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-141
pack16msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-142
packbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-143
pref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-144
pref16x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-145
pref32x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-146
prefd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-147
prefr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-148
quadavg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-149
quadumax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-150
quadumin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-151
quadumulmsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-152
rdstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 153
rdtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-154
readdpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 155
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PRELIMINARY SPECIFICATION 21
readpcsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -156
readspc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-157
rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-158
roli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-159
sex16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-160
sex8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-161
st16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -16 2
st16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-163
st32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -16 4
st32d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-165
st8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-166
st8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -16 7
ubytesel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-168
uclipi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-169
uclipu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-170
ueql . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -17 1
ueqli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-172
ufir16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173
ufir8uu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 174
ufixieee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-175
ufixieeeflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-176
ufixrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-177
ufixrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-178
ufloat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-179
ufloatflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-180
ufloatrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-181
ufloatrzflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-182
ugeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-183
ugeqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-184
ugtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-185
ugtri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-186
uimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-187
uld16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-188
uld16d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 189
uld16r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-190
uld16x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 191
uld8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -19 2
uld8d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-193
uld8r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-194
uleq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A -19 5
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uleqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-196
ules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-197
ulesi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-198
ume8ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-199
ume8uu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 200
umin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-201
umul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-202
umulm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-203
uneq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-204
uneqi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-205
writedpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20 6
writepcsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-207
writespc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 208
zex16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-209
zex8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-210
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-212
B MMIO Register Summary
B.1 MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
C Endian-ness
C.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.2 Little and Big Endian Addressing Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C- 1
C.3 Test to Verify the Correct Operation of PNX1300 in Big and Little Endian Systems . . . . . . . . . . . . . . C-2
C.4 Requirement for the PNX1300 to Operate in Eithe r Little Endian or Big Endian Mode . . . . . . . . . . . . C -2
C.4.1 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.4.2 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
C.4.3 PNX1300 PCI Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
C.4.4 Image Coprocessor (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
C.4.5 Video In (VI) and Video Out (VO) Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
C.4.6 Audio In (AI), Audio-Out (AO), and SPDIF Out (SDO) Units . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
C.4.7 Variable Length Encoder (VLD) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
C.4.8 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8
C.4.9 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9
C.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C -9
C.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9
Index
PRELIMINARY SPECIFICATION 1-1
Pin List Chapt er 1
by John C hang, Wenyi Song, Thorwald Rabeler, Luis Lucas
1.1 PNX1300 SERIES VERSUS TM-1300
The following summarizes di fferences between TM- 1300 and PNX 1300/01/ 02/11:
• Lower core voltage for PNX1311 (2.2V core voltage) and therefore lower power consumption.
• DSPCPU speed of up to 200 MHz.
• SDR AM s p ee d of up t o 18 3 MH z .
• Support for 256 Mbit SDRAM organized in x16. The REFRESH counter must be changed. Refer for in Chapter 12,
“SDRAM Memory System” for details.
• Support for 16- and 32-bit Main Memory Interface.
• Simplified power supplies sequencing (see Section 1.9.4).
• Additional mode where VI_DATA[9:8] in message passing mode are not affected by the VI_DVALID signal.
• Bug fixed for PCI Special Cycles. PNX1300 Series discards PCI Special Cycles issued by some PCI chipsets.
• Auton omous boot bug in non 1:1 rati o is fix ed, r esulting i n 2KB boo t EEPR O M size for all C P U: SDRAM ratios.
In the document, ‘PNX1300 Series’ is used interchangebly with ‘PNX1300/01/02/11’, and it always refers to
PNX 1 30 0, PN X 1 30 1, P NX 1 3 02 and P N X13 11 products. A ny exce pt ion wi l l be not e d.
1 .2 B OU ND AR Y S CAN NO TI C E
PNX 130 0 Seri es i mple men ts fu ll IEEE 1149 .1 boundary s can. Any PNX1300 Series pin designated “IN” only (from a
functionality point of view) can become an output during boundary scan.
1.3 I/O CIRCUIT SUMMARY
PNX1300 Series has a total of 169 functional pins, excluding VDDQ, VSSQ, VREF_PCI and VREF_PERIPH and digital
power/ ground. PNX1300 Series uses the types of I/O circuits shown in the table below.
Fo r th e pin s wit h 5-V i np ut ca pab ility , the sp ec ia l pins VR EF_PCI or VREF_PE RI PH determine 3.3- or 5-V inp ut t o le r -
ance, as per the table in Section 1.6. The above pad types are used in th e modes list ed in th e following table.
Unused pins may remain floating, i.e. unconnected.
All p ins t hat dr iv e a cl ock sh ould d ri ve a serie s re s i sto r.
Pad Type Pa d Typ e Descri ption
PCI PCI2.1 compliant I/O, capable of using 3.3-V or 5-V PCI signaling conventions.
PCIOD PCI2.1 compliant Open Drain I/O, capable of using 3.3-V or 5-V PCI signaling conventions.
IICOD Open drain 3.3-V or 5-V I2C I/O (for I2C pins).
STRG3 3.3-V only low impedance I/O. Requires board level 27-33 ohm series terminator resistor to match 50 ohm
PCB trace.
NORM3 3.3-V only I/O circuit with regular drive strength and board trace matched drive impedance.
STRG5 3.3-V low impedance output, combined with 5-V tolerant input. If used as output, it requires a board level
27-33 ohm seri es termina tor resistor to match 50-ohm PCB trac e.
WEAK5 3.3-V regular impedance output, wi th slow rise/fall, combined with 5-V tolerant input.
Modes Description
IN Input only, except during boundary scan
OUT Output only, except during boundary scan
OD Open drain output - active pull low, no active drive high, requires external pull-up
I/O Output or input
I/OD Open drain output with input - active pull low, no active drive high, requires external pull-up
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-2 PRELIMINARY SPECIFICATION
1.4 SIGNAL PIN LIST
In the table below, a pin nam e ending in a ‘#’ designates an active-low signal (the a ctive state of the signal is a low
voltage level). All other signals have active-high polarity.
Pin Name BGA
Ball Pad
Type Mode Description
Main Clock Interface
TRI_CLKIN L20 NORM3 IN Main input clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to
2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x,
5/4, 4/3, 3/2 o r 2x the SDRAM clock frequency. Maximum re commended ppm level is
+/- 100 ppm or lower to improve jitter on generated clocks. Duty cycle should not
exceed 30/70% asymmetry.
The operating limits of the internal PLLs are:
• 27 MHz < Output of the SDR AM PLL < 200 MHz
• 33 MHz < Output of the CPU PLL < 266 MHz
These are not the speed grades of the chips, just the PLL limits.
VDDQ K20 N/A PWR Quiet VDD for the PLL subsystem. This pin should be supplied from VDD through a
low-Q series inductor. It should be bypassed for AC to VSSQ, using a dual capacitor
bypass (h i and low frequency AC bypass).
VSSQ L19 N/A GND Quiet VSS for the PLL subsystem. Should be AC bypassed to VDDQ, but should
otherwise be left DC floating. It is connected on-chip to VSS. No external coil or
other connection to board ground is needed, such connection would create a
ground loop.
Miscellaneous System Interface
TRI_RESET# G19 WEAK5 IN PNX1300/01/02/11 RESET input. This pin can be tied to the PCI RST# signal in PC I
bus systems. Upon releasing RESET, PNX1300/01/02/11 initiates its boot protocol.
BOOT_CLK T20 NORM3 IN Used for testing purposes. Must be connected t o TRI_CLKIN for normal operation.
TESTMODE P19 NORM3 IN Used for testing purposes. Must be connected to VSS for n or mal oper ation.
SCANCPU D20 NORM3 IN Used for testing purposes. Must be connected to VSS for nor mal oper ation.
RESERVED1 E19 NORM3 I/O Reserved pin. Has to be left unconnected for normal operation.
RESERVED2 D19 STRG5 I/O Reserved pin. Has to be left unconnected for normal operation.
VREF_PCI F2 N/A PWR VREF_PCI determines the mode of operation of the PCI pins listed in Section 1.6.
VREF _PCI must be connec ted to 5V for use in a 5-V PCI si gnaling environm ent or to
VSS (0 V) f or use in 3.3-V PCI signaling environment. The supply to this pin should be
AC bypassed and provide 40 mA of DC sink or source capability. Note that this pin
can not be directly connected to the PCI ‘I/O design ated power pins’ in a dual
voltage PCI plug-in card. Board level conversion circuitry is required.
VREF_PERIPH C18 N/A PWR VREF_PERIPH determines the mode of operation of the I/O pins listed in Section 1.6.
VREF_PERIPH should be connected to 5V if any of the listed I/O pins provided should
be 5-V input voltage capable. VREF_PERIPH should be connected to VSS (0-V) if all
listed I/O pins are 3.3 -V only inputs. The supply to this pin should be AC bypassed and
provide 40 mA of DC sink or source capability.
TRI_USERIRQ G20 WEAK5 IN General purpose lev el/edge interrupt input. Vectored interrupt source number 4.
TRI_TIMER_CLK H19 WEAK5 IN External general purpose clock source for timers. Max. 40 MHz.
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-3
Main Memory Interface
MM_CLK0
MM_CLK1 Y10
W10 STRG3 OU T SDRAM ou t p u t clock a t 2x or 3x TRI _ C LKI N fre q uency. Two ide nti ca l out p u ts are pro-
vide d to reliably dr i ve several small memory con figurations with out exter nal glue.
A series terminating resistor close to PNX1300/01/02/11 is required to reduce ringing.
For driving a 50-ohm trace, a resistor of 27 to 33 ohm is recommended. It is recom-
mended against using higher impedance traces in t he S DRA M signals.
MM_A00
MM_A01
MM_A02
MM_A03
MM_A04
MM_A05
MM_A06
MM_A07
MM_A08
MM_A09
MM_A10
MM_A11
MM_A12
MM_A13
W12
Y12
W11
Y11
Y9
W9
V9
Y8
W8
Y7
V12
Y13
W13
Y14
NORM3 OUT Main memory address bus; used for row and column addresses
WARNING: MM_A[13:11] DO NOT CONNECT DIRECTLY TO SDRAM A[13:11] pins.
Ref er to Chapter 12, “SDRAM Memory System” for accurate connection diagrams.
MM_DQ00
MM_DQ01
MM_DQ02
MM_DQ03
MM_DQ04
MM_DQ05
MM_DQ06
MM_DQ07
MM_DQ08
MM_DQ09
MM_DQ10
MM_DQ11
MM_DQ12
MM_DQ13
MM_DQ14
MM_DQ15
MM_DQ16
MM_DQ17
MM_DQ18
MM_DQ19
MM_DQ20
MM_DQ21
MM_DQ22
MM_DQ23
MM_DQ24
MM_DQ25
MM_DQ26
MM_DQ27
MM_DQ28
MM_DQ29
MM_DQ30
MM_DQ31
Y20
V18
W19
W20
U18
V19
V20
T18
W18
V17
Y18
W17
Y17
W16
Y16
V15
W7
Y6
W6
V6
Y5
W5
Y4
W4
V2
V3
W1
W2
Y1
Y2
W3
Y3
NORM3 I/O 32-bit data I/O bus.
T he Main Memory Interface u nit also supports a 16-bit I/O interface. Refer t o Chapter
12, “SDRAM Memo ry Syst em.”
MM_CKE0
MM_CKE1 Y19
U1 NORM3 O UT Clock enable output to SDRAMs. Two identica l o u t puts are provided in order to reli ably
drive several small memory configurations without external glue.
MM_CS0#
MM_CS1#
MM_CS2#
MM_CS3#
U2
U20
U3
U19
NORM3 OUT Chip select for DRAM rank n; active low
In P NX1300/01 /02/11 the chip sel ec ts pins may be used as addr es s pins to suppor t
the 256 Mbit SDRAM device organized in x16. Refer to Chapter 12, “SDRAM Memory
System.”
MM_RAS# W14 NORM3 OUT Row address strobe; active low
MM_C AS# Y15 NORM3 OUT Col umn addres s str obe; active low
MM_WE # W15 NORM3 OUT Write enable; active low
Pin Name BGA
Ball Pad
Type Mode Description
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-4 PRELIMINARY SPECIFICATION
MM_DQM0
MM_DQM1
MM_DQM2
MM_DQM3
T19
R18
V1
V4
NORM3 OUT MM_DQ Mask Enable; these are byte enable signals for the 32-bit MM_DQ bus
PCI Int erface (Note: curren t buf fer desig n allows dr ive/re ceive from either 3.3 or 5V PCI bus)
PCI_CLK T2 PCI IN All PCI input signals are sampled with respect to the rising edge of t his clock. All PCI
outputs are generated based on this clock. Clock is required for normal operation of
the PCI block.
PCI_AD00
PCI_AD01
PCI_AD02
PCI_AD03
PCI_AD04
PCI_AD05
PCI_AD06
PCI_AD07
PCI_AD08
PCI_AD09
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
T1
R3
R2
R1
P2
P1
N2
N1
M2
M1
L2
L1
K1
K2
J1
J2
D1
D3
C1
B2
B1
C2
C3
A1
A3
C4
B4
A4
A5
C6
B6
A6
PCI I/O Multiplexed address and data.
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
M3
J3
D2
B3
PCI I/O Multiplexed bus comma nds and byte enables. High for command, low for byte enable.
PCI_PA R H1 PCI I/O Even parity across AD and C/BE lines.
PCI_FRAME# E2 PCI I/O Sustained tri-state. Frame is driven by a master to indicate the beginning and duration
of an access.
PCI_IRDY# E1 PCI I/O Sustained tri-state. Initiator Ready indicates that the bus master is ready to complete
the curr ent data phase.
PCI_TRDY# F3 PCI I/O Sustained tri-state. Tar get Ready indicates that the bus target is ready to complete the
current data phase.
PCI_STOP# G2 PCI I/O Sustained tri-state. Indicates that the target is requesting that the master stop the cur-
rent transaction.
PCI_IDSEL A2 PCI IN Used as chip select during configuration read/write cycles.
PCI_DEVSEL# F1 PCI I/O Sustained tri-state. Indicates whether any device on the bus has been selected.
PCI_REQ# B7 PCI I/O Driven by PNX1300/01/02/11 as PCI bus master to request use of the PCI bus.
PCI_GNT# B5 PCI IN Indicates to PNX1300/01/02/11 t hat access to the bus has been granted.
PCI_PERR# G1 PCI I/O Sustained tri-state. Parity error generated/received by PNX1300/01/02/11.
PCI_SE RR# H2 PCI OD S ystem error. T his signal is asser ted when opera ting as t arget and detec ting an
addre ss par i ty error.
Pin Name BGA
Ball Pad
Type Mode Description
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-5
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
C9
A8
B8
A7
PCIOD
PCI
PCIOD
PCIOD
I/OD
I/O/OD
I/OD
I/OD
• Can operate as input (power up default) or output, as determined by direction con-
trol bits in PCI MMIO register INT_CTL.
• As input, a PCI_INT# pin can be used to receive PCI interrupt requests (normal
PCI use is active low, le vel sensitive mode, but the VIC can be set to treat these as
positive edge triggered mode). As input, a PCI_INT# pin can also be used as a
general interrupt request pin if not needed for PCI.
• As output, the value of a PCI_INT# can be programmed through PCI MMIO regis-
ters to generate interrupts f or other PCI masters.
• Whenever XIO bus functionality is active, PCI_INTB# is a push-pull CMOS I/O pin.
When the XIO bus is not active and regular PCI bus functionality is activated, then
PCI_INTB# has a PCI compatible open drain output.
JTAG Interface (debug access port and 1149.1 boundary sca n port)
JTAG_TDI F20 WEA K5 IN JTAG test data input
JTAG_TDO F18 WEA K5 I/O JTAG test data output. Th is pin can either drive a ctive low, high or float.
JTAG_T C K F1 9 W E A K5 IN JTAG test cl ock i nput
JTAG_TMS E20 W EAK5 IN JTAG test mode select inp ut
Video In
VI_CLK C20 STRG5 I/O • If configured as input (power up default): a positive transition on this incoming video
clock pin samples all other VI_DATA input signals below if VI_DVALID is HIGH. If
VI_DVALID is LOW, VI_DATA is ignored. Clock and data rates of up to 81 MHz are
supported. PNX1300 Series supports an additional mode where VI_DATA[9:8] in
message passing mode are not affected by the VI_DVALID signal, Section 6.6.1 on
page 6-12.
• If configured as output: programmable output clock to drive an external video A/D
converter. Can be programmed to emit integral dividers of DSPCPU_CLK.
If used as output, a board le vel 27-33 ohm series resistor is recommended to reduce
ringing.
VI_DVALID A17 WEAK5 IN VI_DVALID indicates that valid data is present on the VI_ DATA lines. If HIGH, VI_DATA
will be accepted on the next VI_CLK positive edge. If LOW, no VI_DATA will be sam-
pled. PNX1300 Series supports an additional mode where VI_DATA[9:8] in message
passing mode are not affected by the VI_DVALID signal, Section 6.6.1 on p age6-12.
VI_DATA0
VI_DATA1
VI_DATA2
VI_DATA3
VI_DATA4
VI_DATA5
VI_DATA6
VI_DATA7
D18
C19
B20
B19
A20
A19
C17
B18
WEAK5 IN CCIR656 style YUV 4:2:2 data from a digital camera, or general purpose high speed
data input pins. Sampled on VI_CLK if VI_DVALID HIGH.
VI_DATA8
VI_DATA9 A18
B17 WEAK5 IN Extension high speed data input bits to allow use of 10 bit video A/D converters in
raw10 modes. VI_DATA[8] serves as START and VI_DATA[9] as END message input in
message passing mode. Sampled on positive transitions of VI_CLK if VI_DVALID
HIGH. PNX1300 Series supports an additional mode where VI_DATA[9:8] in message
passing mode are not affected by the VI_DVALID signal, Section 6.6.1 on p age6-12.
I2C Interface
IIC_SDA R19 IICOD I/OD I2C serial data
IIC_SCL R20 IICOD I/OD I2C clock
Video Out
VO_DATA0
VO_DATA1
VO_DATA2
VO_DATA3
VO_DATA4
VO_DATA5
VO_DATA6
VO_DATA7
P20
N19
N20
M18
M19
M20
K19
J20
WEAK5 OUT CCIR656 style YUV 4:2:2 digital output data, or general purpose high speed data out-
put channel. Output changes on positive edge of VO_CLK.
Pin Name BGA
Ball Pad
Type Mode Description
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-6 PRELIMINARY SPECIFICATION
VO_IO1 J18 WEAK5 I/O This pin can function as HS output or as STMSG (Start Message) output.
• If set as H S outp ut, it outputs the h o rizontal sync signal
• In messa ge passing mode, this pin acts as STMSG output.
VO_IO2 H20 WEAK5 I/O This pin can function as FS (frame sync) input, FS output or as ENDMSG output.
• If set as FS input, it can be set to respond to positive or negative edge transitions.
• If the Video Out (VO) unit o perates in external sync mode and the selected transition
occurs, the VO unit sends two fields of video data. Note: this works only once after a
reset.
• In message passing mode, this pin acts as ENDMSG output.
VO_CLK J19 STRG 5 I/O The VO unit emits VO_DATA on a po sit ive edge of VO_CLK. VO_CLK c an be config-
ured as input (reset default) or output.
• If con figured as input: VO_CLK is received from exter nal display clock m aster cir-
cuitr y.
• If con figured as output, PNX 1300/0 1/02/1 1 emits a programmable clock frequency.
The emitted frequency can be set between approx. 4 and 81 MHz with a sub-Hertz
resolution. The clock generated is frequency accurate and has low jitter properties
due to a combination of an on-chip DDS (Direct Digital Sy nthesizer) and VCO/PLL.
If used as output, a board level 27-33 ohm series resistor is recommended to reduce
ringing.
Audio In (a lways acts a s r eceiver, but can be maste r o r sl ave for A/D timing)
AI_OSCLK B15 STRG3 OUT Over-sampling clock. This output can be prog rammed to emit any frequency up to 40
MHz with a sub-Hertz resolution. It is intended for use as the 256fs or 384fs over sam-
pling clock by ex ternal A/D subsystem. A board level 27-33 ohm series resistor is rec-
ommended to reduce ringing.
AI_SCK A16 STRG5 I/O • When the Audio In (AI) unit is programmed as a serial-interface timing slave
(power-up default), AI_SCK is an input. AI_SCK receives the serial bit clock from
the ex ternal A/D s ubs ystem. This clock is tre ated a s fully asyn chronous to the
PNX1300/01/02/11 main clock.
• When the AI unit is progr ammed as the serial-inter face timing master, AI_SCK is an
output. AI_SCK drives the serial clock for the external A/D subsystem. The fre-
quency is a programmable integral divisors of the AI_OSCLK frequency.
AI_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the
ser ial stream is variable. I f used as output , a boar d level 27-33 ohm se r ies res istor is
recommended to reduce ringing.
AI_SD C15 WEAK5 IN Serial data from external A/D subsystem. Data on this pin is sampled on positive or
negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL
register.
AI_WS B16 WEAK5 I/O • When the AI unit is programmed as the serial-interface timing slave (power-up
default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected
for AI_SD.
• When Audio In i s programmed as the serial-interface timing master, AI_WS acts as
an output. It is asserted on the opposite edge of the AI_SD sampling edge.
AI_WS is the word-select or frame-synchronization signal from/to the external A/D
subsystem.
Pin Name BGA
Ball Pad
Type Mode Description
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-7
Audio Out (alw ays acts as sender, but can be master or slave for D/A timing)
AO_OSCLK B14 STRG3 OUT Over sampling clock. This output can be programmed to emit any frequency up to 40
MHz, with a sub-Hertz resolution. It is intended for use as the 256 or 384fs over sam-
pling clock by the external D/A conversion su b system. A board level 2 7-3 3 oh m series
resistor is recommended to reduce ringing.
AO_SCK A14 STRG5 I/O • When the Audio Out (AO) unit is programmed to act as the serial interface timing
slav e (power up default), AO_SCK acts as input. It receives the Serial Clock from
the external audio D/A subsystem. The clock is treated as fully asynchronous to the
PNX1300/01/02/11 main clock.
• When the AO unit is programmed to act as serial interface timing master, AO_SCK
acts as output. It drives the serial clock for the extern al audio D/A subsys tem. The
clock frequency is a programmab le integral divisor of the AO_OSCLK frequency.
AO_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the
seri al stream is variable. I f used as output , a boar d level 27- 33 o h m series resisto r is
recommended to reduce ringing.
AO_SD1 B13 WEAK5 OUT Serial data to external stereo audio D/A subsystem fo r first 2 of 8 channels. The timing
of transitions on this output is determined by the CLOCK_EDGE bit in the AO_SERIAL
register, and can be on positive or negative AO_SCK edges.
AO_SD2 A13 WEAK5 OUT Serial data.
AO_SD3 C12 WEAK5 OUT Serial data.
AO_SD4 B12 WEAK5 OUT Serial data.
AO_WS A15 WEAK5 I/O • When the AO unit is programmed as the serial-interface timing slave (power-up
default) , AO_WS acts as an input. AO _WS is sampled on the opposite AO_SCK
edge at which AO_SDx are asserted.
• When the AO unit is programmed as serial-interface timing master, AO_WS acts as
an output. A O_WS is asserted on the same AO_SCK edge as AO_SDx.
AO_WS is the word-select or frame-synchronization signal from/to the external D/A
subsystem. Each audio channel receives 1 sample for every WS period.
S/PDIF Output (Output)
SPDO A12 STRG3 OUT Self cloc king serial data stream as per IEC958, with 1937 extensions. Note that the
low impedance output buffer requires a 27 to 33 ohm series terminator close to
PNX1 300/01/02/1 1 in order to match the board t race impedance . Th is seri es term ina -
tor can be/must be part of the voltage divider needed to create the co axial output
through the A C isolation transf ormer.
Synchronous Serial Interface (SSI) to an off-chip modem front-end
SSI_CLK B11 WEAK5 IN Clock signal of the synchronous serial interface to an off-chip modem analog frontend
or ISDN terminal adapter; provided by the receive channel of an external communica-
tion device.
SSI_RXFSX A11 WEAK5 IN Receive frame sync reference of the synchronous serial interface, provided by the
receive channel of an external communication device.
SSI_RXDATA A10 WEAK5 IN Receive serial data input; pro vided by the receive channel of an external communica-
tion device.
SSI_TXDATA B10 WEAK5 OUT Transmit serial data output; sent to the transmit channel of the external communication
device.
SSI_IO1 A9 WEAK5 I/O General purpose programmable I/O. Set to input on po wer up.
SSI_IO2 B9 WEAK5 I/O General purpose programmable I/O. Set to input on po wer up. Can also be pro-
grammed to function as the transmit channel frame synchronization reference output.
Pin Name BGA
Ball Pad
Type Mode Description
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-8 PRELIMINARY SPECIFICATION
1.5 POWER PIN LIST
VSS (ground) VCC (3.3V I/O supply) VDD (2.5V core supply)
C5
C16
D4
D5
D16
D17
E3
E4
E17
E18
T3
T4
T17
U4
U5
U16
U17
V5
V16
H8
H9
H10
H11
H12
H13
J8
J9
J10
J11
J12
J13
K8
K9
K10
K11
K12
K13
L8
L9
L10
L11
L12
L13
M8
M9
M10
M11
M12
M13
N8
N9
N10
N11
N12
N13
C7
C10
C11
C14
D6
D7
D10
D11
D14
D15
F4
F17
G3
G4
G17
G18
K3
K4
K17
K18
L3
L4
L17
L18
P3
P4
P17
P18
R4
R17
U6
U7
U10
U11
U14
U15
V7
V10
V11
V14
C8
C13
D8
D9
D12
D13
H3
H4
H17
H18
J4
J17
M4
M17
N3
N4
N17
N18
U8
U9
U12
U13
V8
V13
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-9
1.6 PIN REFERENCE VOLTAGE
With the exception of Open Drain mode outputs, outputs always drive t o a level determined by the 3.3-V I/O voltage.
VREF_PE RIPH and VREF_PCI purely determine input voltage clamping, not input signal thresholds or output levels.
VREF_PCI determined mode VREF_PERIPH determined mode SDRAM i/f (always 3.3-Volt mode)
PCI_AD00
PCI_AD01
PCI_AD02
PCI_AD03
PCI_AD04
PCI_AD05
PCI_AD06
PCI_AD07
PCI_AD08
PCI_AD09
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CLK
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_IDSEL
PCI_DEVSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
TRI_RESET#
TRI_USERIRQ
TRI_TIMER_CLK
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
VI_CLK
VI_DVALID
VI_DATA0
VI_DATA1
VI_DATA2
VI_DATA3
VI_DATA4
VI_DATA5
VI_DATA6
VI_DATA7
VI_DATA8
VI_DATA9
IIC_SDA
IIC_SCL
VO_IO1
VO_IO2
VO_CLK
AI_SCK
AI_SD
AI_WS
AO_SCK
AO_WS
SSI_CLK
SSI_RXFSX
SSI_RXDATA
SSI_IO1
SSI_IO2
RESERVED2
MM_CLK0
MM_CLK1
MM_A00
MM_A01
MM_A02
MM_A03
MM_A04
MM_A05
MM_A06
MM_A07
MM_A08
MM_A09
MM_A10
MM_A11
MM_A12
MM_A13
MM_DQ00
MM_DQ01
MM_DQ02
MM_DQ03
MM_DQ04
MM_DQ05
MM_DQ06
MM_DQ07
MM_DQ08
MM_DQ09
MM_DQ10
MM_DQ11
MM_DQ12
MM_DQM0
MM_DQM1
MM_DQM2
MM_DQM3
MM_DQ13
MM_DQ14
MM_DQ15
MM_DQ16
MM_DQ17
MM_DQ18
MM_DQ19
MM_DQ20
MM_DQ21
MM_DQ22
MM_DQ23
MM_DQ24
MM_DQ25
MM_DQ26
MM_DQ27
MM_DQ28
MM_DQ29
MM_DQ30
MM_DQ31
MM_CKE0
MM_CKE1
MM_CS0#
MM_CS1#
MM_CS2#
MM_CS3#
MM_RAS#
MM_CAS#
MM_WE#
Inputs always in 3.3-V mode O utput only pins
TRI_CLKIN
BOOT_CLK
TESTMODE
SCANCPU
RESERVED1
VO_DATA0
VO_DATA1
VO_DATA2
VO_DATA3
VO_DATA4
VO_DATA5
VO_DATA6
VO_DATA7
AI_OSCLK
AO_OSCLK
AO_SD1
AO_SD2
AO_SD3
AO_SD4
SSI_TXDATA
SPDO
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-10 PRELIMINARY SPECIFICATION
1.7 PACKAGE
1.8 ORDERING INFORMATION
To or der 143-MHz/2.5V product, part number is ‘PNX1300’, 12 nc product code 9352 7097 6557.
To or der 180-MHz/2.5V product, part number is ‘PNX1301’, 12 nc product code 9352 7097 9557.
To or der 200-MHz/2.5V product, part number is ‘PNX1302’, 12 nc product code 9352 7098 2557.
To or der 166-MHz/2.2V product, part number is ‘PNX1311’, 12 nc product code 9352 7098 5557.
1.27 24.13
A
A1E1
bA2
A2
A1
UNIT Dyek
mm 0.70
0.50
2.51 27.2
26.8
D1e1
24.1
23.9 27.2
26.8 24.1
23.9 4.2
3.8
∅ j
21.0
15.4
1.83
1.63
y1
0.90
0.60 0.2 0.15 0.25
DIMENSIONS (mm are the original dimensions)
Ew
0.2
v
0 10 20 mm
scale
SOT553-1
HBGA292: plastic, heatsink ball grid array package; 292 balls; body 27 x 27 x 1.75 mm
A
max.
detail X
y
y1C
e
e
e1
e1
∅ w
b
X
k
k
E1
∅ j
D
D1
E
C
M
AB
CD
EF
H
K
G
J
LM
NP
RT
UV
WY
2468101214161820
135791113151719
B
A
ball A1
index area
M
vA
M
vB
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-11
1.9 PARAMETRIC CHARACTERISTICS
1.9.1 PNX1300/01/02/11 Absolute Maximum Ratings
Permanent damage may occur if these conditions are exceeded
Notes: 1. VX in the 5V mode pin is either VREF_PCI or VREF_PERIPH, see Section 1.6.
2. JEDEC Standar d, June 2000
3. JEDEC Standar d, October 1997
1. 9. 2 PNX1 300/01/02 O perating Ran ge and Thermal Char acte ri stics
Functional operation, long-term reliability and AC/DC characteristics are guaranteed for the operating conditions below.
1.9.3 PNX1311 O perating Range and Thermal Characteristics
Functional operation, long-term reliability and AC/DC characteristics are guaranteed for the operating conditions below.
1.9.4 PNX1300/01/ 02/11 Pow er Supply Sequencing
Power application and power removal should obey the following rule:
VDD should never exceed VCC by m or e t h an 0.5 V
Permanent damage may occur if this rule is not observed.
Symbol Parameter Min. Max Units Notes
VDDMAX 2.5 -V cor e supply voltage (PNX1300/01 /02/11) - 0.5 3.5 V
VCCMAX 3.3-V I/O supply voltage -0.5 4.6 V
VI-5V DC input voltage on all 5-V pins -0.5 VX+0.5 V 1
VI-3.3V DC input voltage on all 3.3-V pins -0.5 VCC+0.3 V
Tstg St orage temp eratu re range -65 150 Deg. C
Tcase Operating case temperature range 0 120 Deg. C
HBMESD Human Body Model Electrostatic handling for all pins - -CLASS 1C 2
MMESD Machine Model Electrostatic handling for all pins - -CLA SS A 3
Symbol Parameter Minimum Typical Maximum Units
VDD PNX1300/01/02 Core supply voltage 2.375 2.50 2.625 V
VCC I/O supply voltage 3.135 3.30 3.465 V
Tcase Operating case temperature range 0 85 °C
Ψjt junction to case thermal resistance 3.8 °C/W
ϑja junction to ambient thermal resistance (natural convection) 15 °C/W
Symbol Parameter Minimum Typical Maximum Units
VDD PNX1311 Core supply voltage 2.090 2 .20 2. 3 10 V
VCC I/O supply voltage 3.135 3.30 3.465 V
Tcase Operating case temperature range 0 85 °C
Ψjt junction to case thermal resistance 3.8 °C/W
ϑja junction to ambient thermal resistance (natural convection) 15 °C/W
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-12 PRELIMINARY SPECIFICATION
1.9.5 PNX1300/01/02 DC/AC Characteristics
Notes: 1. VX for a 5V mode pin is either VREF_PCI or VREF_PERIPH, see Section 1.6.
1.9.6 PNX1311 DC/AC Charac teristics
Notes: 1. VX for a 5V mode pin is either VREF_PCI or VREF_PERIPH, see Section 1.6.
Symbol Parameter Condition/Notes Min. Max Units
VDD Core s upp l y vo l t ag e 2. 3 75 2. 6 25 V
VCC I/O supply voltage 3.135 3.465 V
IDD-typ Core sup ply current 200 MHz CPU o pera tion (Max. applicatio n) 14 00 mA
ICC-typ I/O supply curr ent 183 MHz SDRAM op eration (Max. applicat ion) 160 mA
IDD-pdn Core sup ply current CP U powe r down mode; 200 MH z 300 mA
ICC-pdn I/O supp ly current CPU power down mode; 183 MHz 50 mA
VIH-5v Input HIGH voltage for I/O-5 V Note 1. All I/O’s e xcept IICOD 2.0 VX+ 0.5 V
VIH-3.3v Input HIGH voltage for I/O-3.3 V All I/Os except IICOD 2.0 VCC + 0.3 V
VIL-5v Input LOW voltage for I/O-5 V All I/Os except IICOD -0.5 0.8 V
VIL-3.3v Input LOW voltage for I/O-3.3 V All I/Os except IICOD -0.3 0.8 V
IIL-5v Input leakage current for I/O-5 V 0 < VIN < 2.7V -70 70 uA
IIL--3.3v Input leakage current for I/O-3.3 V 0 < VIN < 2.7V -0 10 uA
CIN Input pin capacitance 8pF
Symbol Parameter Condition/Notes Min. Max Units
VDD Core supply voltage 2.090 2.310 V
VCC I/O supply voltage 3.135 3.465 V
IDD-typ Core sup ply current 166 MHz CPU o pera tion (Max. applicatio n) 1110 mA
ICC-typ I/O supply curr ent 166 MHz SDRAM operation (Max. ap pli cat ion) 145 mA
IDD-pdn Core sup ply current CP U powe r down mode; 166 MH z 215 mA
ICC-pdn I/O supply current CPU power down mode; 166 MHz 46 mA
VIH-5v Input HIGH voltage for I/O-5 V Note 1. All I/O’s e xcept IICOD 2.0 VX+ 0.5 V
VIH-3.3v Input HIGH voltage for I/O-3.3 V All I/Os except IICOD 2.0 VCC + 0.3 V
VIL-5v Input LOW voltage for I/O-5 V All I/Os except IICOD -0.5 0.8 V
VIL-3.3v Input LOW voltage for I/O-3.3 V All I/Os except IICOD -0.3 0.8 V
IIL-5v Input leakage current for I/O-5 V 0 < VIN < 2.7V -70 70 uA
IIL--3.3v Input leakage current for I/O-3.3 V 0 < VIN < 2.7V -0 10 uA
CIN Input pin capacitance 8pF
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-13
1.9.7 PNX1300 Series Power Consumpti on
The power consumption of PNX1300 Series is depen-
dent on the activity of the DSPCPU, the amo unt of pe-
ripherals being used, the frequency at which the system
is running as well as the loads on the pins.
The first section presents the power consumption for
known applications. The other power related sections
pre sen t t he m ax imu m p ower consu m ption . T hese m axi-
mum values are obtained with a ‘fake’ application that
turns on all the per ipherals and runs int ensive compute
on t h e C P U .
1.9.7.1 Power Consumption for
Applications on PNX1300 Series
The Table 1-1 and Table 1-2 present the power con-
sumption for two typical applications:
•The DVD playback includes video display using the
VO per i pheral and audi o s tr e amin g us ing AO periph-
eral. The bitstream is brought into the T M-1300 sys-
tem over the PCI peripheral. The VLD co-processor
is used to perform the bitstream parsing. The bit-
stream is not scrambled therefore the DVDD co-pro-
cessor is not used and it is turned off.
•The MPEG4 application includes video and audio
playback of an enocded CIF s tream. The bit stream
is brought into the PNX1300 system over the PCI
peripheral. The Video and Audio subsystems of the
PNX1300 were used to render the video a nd sound
from the decoded stream into the video monitor and
speakers.
•The H263 video conferencing application includes
the following steps. It captures a CCIR656 video
stream at 30 frames/second using the V I peripheral.
Th e in co m ing vi deo s t re am is d ow ns c al ed , on the fly,
to SIF resolution by VI. The captured frames are then
downscaled to a QSIF resolution using the ICP co-
pro c es so r. Th e re sul t in g Q SIF i m ag e is se nt ove r the
PCI bus via the ICP co-processor to a SVGA card
(PC monitor display) and encoded by the DSPCPU.
The resulting bitstream is then decoded by the
DSPCPU and displayed as a SIF image on the same
PC monitor (also using the ICP co- p rocessor). Al l the
encoding/decoding part is done in the YUV color
space. The display is in the RGB16 color space.
Software is not optimized.
Three main technics may be applied to reduce the ‘Out
of th e Box ’ power consumption.
•Turn off the unused peripherals. Refer to Section
21. 6 on p ag e2 1 -2.
•Run the system at the required speed, i.e. some
application may not require to run at the full speed
grade of the chip.
•Powerdown the system or the DSPCPU each time
the DSPC PU rea ch ed th e Idle tas k.
A more detailed description can be found in the applica-
tion no te ‘TM -130 0 Pow er Sa vin g F eatur es ’ available at
the following website:
http://www.semiconductors.philips.com/trimedia/
As previously mentioned the Table 1-1 and Table 1-2
show that the final power consumption for a realistic ap-
plication may be lower than the values reported in the
next section.
Based on these results and the following section, the
power consumption of PNX1300 Series, using an artifi-
c ial sce nari o depi ctin g an ext re mel y dem andi ng appl ic a-
tion, for commonly used speeds, is as f ollows:
•PNX 1 300/01/02 i s < 3. 4 W @ 166:133 MHz
•PNX 1 31 1 is < 2.9 W @ 1 66 : 13 3 MHz
•PNX 1 30 2 is < 4.0 W @ 2 00 : 13 3 MHz
Ta ble 1-1. Power Consumption of Exam ple Applications for PNX1 300/01 /02 (Vdd = 2.5V)
APPLICATIONS AFTER
POWER
OPTIMIZATIONS
WITHOUT
POWER
OPTIMIZATIONS
Optimizations
Unused
Peripherals
Turned Off
Syst em Speed
Adjustment Idle task power
management
DVD Playback 2.2 W 3.0 W @ 180 MHz 2.6 W @ 180 MHz 2.6 W @ 180 MHz 2.2 W @ 180 MHz
H.263 Vconf 1.7 W 2.9 W @ 166 MHz 2.7 W @ 166 MHz 1.9 W @ 111 MHz 1.7 W @ 111 MHz
Ta ble 1-2. Power Consumption of Exam ple Applications for PNX1311(Vdd = 2.2V)
APPLICATIONS AFTER
POWER
OPTIMIZATIONS
WITHOUT
POWER
OPTIMIZATIONS
Optimizations
Unused
Peripherals
Turned Off
Syst em Speed
Adjustment Idle task power
management
MPEG4 (CIF) A/V
Playback 1.2 W 2.5 W @ 166 MHz 2.1 W @ 166 MHz 1.3 W @ 70 MHz 1.2 W @ 70 MHz
H.263 Vconf 1.5 W 2.4 W @ 166 MHz 2.2 W @ 166 MHz 1.7 W @ 111 MHz 1.5 W @ 111 MHz
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-14 PRELIMINARY SPECIFICATION
1.9.7.2 PNX1300/01/02 DSPCPU Core Current and Power Consumption
Notes: 1. Consumption for PNX1300/01/02 is organized in several categories. The “Typ” column shows current consumption for a typ-
ical application with a CPI (Clocks Per Instruction) of 1.4. The “Max” column provides current consumption for an application
with a CPI of 1.1. The me asu rements we re tak en wi th all th e peripheral u nits turned on ( periphe rals run on a random da ta
pattern a t the specifi ed frequenc ies, except for VO which runs at 27 MHz) . This “Max” data repr esnts an app licati on that
heavily uses the DSPCPU and does not reflect a realistic application; it is used to determine peak currents. The “Typ” mea-
surements reflect real applications. The “Pwd” colu mn shows current cons ump tion w hen Glo bal Powerdown mode is acti-
vated. See Chap ter 21, “Power Management . ”
2. Standby rows indicate current consumption when DSPCPU is maintained under RESET (See Sect io n 11 .6. 5, “BIU_CTL
Register”), all peripherals turned off (i.e. not enabled) and all peripherals powered down (+ bpwd row).
3. Measurements accuracy is +/ - 5% . Me asu rem ents ar e done with Vdd set to 2. 5V and Vc c set to 3.3V.
4. Cur rents do n ot sc ale wit h fr equency unl ess the C PU to SDRAM r atio is ma intained. As an ex ample, the data for CP U to
SDRAM ratio 1:1 for 183:183 MHz can be calculated by using the data from the 143:143 MHz column, and scaling the cur-
rents by a fac tor of 1.2 79.
1.9.7.3 PNX1311 DSPCPU Core Current and Power Consumption Details
Notes: 1. Consumpti on for PNX1311 i s organized in seve ral categorie s. The “Typ” colum n sho ws current consump tion for a typi cal
application with a CPI (Clocks Per Inst ruct ion) of 1.4. The “Max” column provides current consumption for an application with
a CPI of 1.1. The measurements were taken with all the peripheral units turned on (peripherals run on a random data pattern
at the specified frequencies, except for VO which runs at 27 MHz). Thi s “Max” data represnts an application that heavily uses
the DSPCP U and does no t reflect a real istic applicati on; it is us ed to determin e peak currents . The “Typ” m easurements
reflect r eal applicati ons. Th e “Pwd” colum n sh ows current c onsumption wh en Global P owerdown m ode is activate d. See
Chapter 21, “Power Management.”
2. Standby rows indicate current consumption when DSPCPU is maintained under RESET (See Sect io n 11 .6. 5, “BIU_CTL
Register”), all peripherals turned off (i.e. not enabled) and all peripherals powered down (+ bpwd row).
3. Measurements accuracy is +/ - 5% . Me asu rem ents ar e done with Vdd set to 2. 2V and Vc c set to 3.3V.
4. C urrents do not scale with frequency unle ss the CPU to SDRAM ratio is maintain e d.
PNX1300
143:143 PNX1301
166:133 PNX1302
192:144 PNX1302
200:133
Symbol Current/Notes Pwd Typ Max Pwd Typ Max Pwd Typ Max Pwd Typ Max Units
PNX130x
(note 1) IDD 225 1125 1200 250 1200 1300 300 1380 1475 300 1400 1525 mA
ICC 40 125 135 40 120 135 40 130 135 36 125 130 mA
Total P owe r Dissipation 0.8 3.2 3.5 0.8 3.4 3.7 0.9 3.9 4.1 0.9 4.0 4.2 W
IDD , DSPCPU Only - 820 920 - 900 1030 - 1030 1200 - 1050 1250 m A
ICC , DSPCPU Only - 55 45 - 50 45 - 55 45 - 55 45 mA
Power DSPCPU Only - 2.2 2.5 - 2.4 2.7 - 2.8 3.1 - 2.8 3.3 W
PNX130x
(note 1,2) IDD , Standby - 550 - - 615 - - 720 - - 740 - mA
Power Standby - 1.5 - - 1.7 - - 1.9 - - 2.0 - W
IDD , Standby + bpwd - 405 - - 450 - - 525 - - 540 - m A
Power Standby + bpwd - 1.1 - - 1.2 - - 1.4 - - 1.5 - W
PNX1311
100:100 PNX1311
143:143 PNX1311
166:166 PNX1311
166:133
Symbol Current/Notes Pwd Typ Max Pwd Typ Max Pwd Typ Max Pwd Typ Max Units
PNX131x
(note 1) IDD 129 670 720 185 955 1025 215 1110 1200 200 1032 1100 mA
ICC 28 87 100 40 125 140 46 145 170 37 123 130 mA
Total P o wer Dissipation 0.4 1.8 1.9 0.5 2.5 2.7 0.6 2.9 3.2 0.6 2.7 2.9 W
IDD , DSPCPU Only - 490 550 - 700 785 - 815 915 - 756 880 mA
ICC , DSPCPU Only - 38 31 - 55 45 - 65 55 - 50 45 mA
Power DSPCPU Only - 1.2 1.3 - 1.7 1.9 - 2.0 2.2 - 1.8 2.1 W
PNX131x
(note 1,2) IDD , Standby - 325 - - 460 - - 535 - - 518 - mA
Power Standby - 0.8 - - 1.1 - - 1.3 - - 1.3 - W
IDD , Standby + bpwd - 240 - - 340 - - 395 - - 375 - mA
Power Standby + bpwd - 0.6 - - 0.9 - - 1.0 - - 0.9 - W
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-15
1.9.7.4 PNX1300/01/02 Current Consum ption For On-Chip Peripherals
Notes: 1. P wd. column for periph eral uni ts indicates current sa vings whe n block p o werdow n is act ivat ed compare d t o when it is idle.
See Chapter 21, “Power Management” for block powerdown activation.
2. Typ. column for peripheral units indicates current required when data pattern is random. The Max. column indicates current
ratings when data is switching from high to low level each cycle. Again that Max. column is to show peak current and does
not represent a real app licati on. For both columns the cur rent reported is the c urren t re quired b y the per iph eral as well as
the internal bus and MMI to tr ansfer the data to/ from th e peripher al unit.
3. Some currents are not reported due to the diff iculty to measure it or because they are not relevant. For example SSI current
is difficult to measure because it heavily involves the DSPCPU and thu s makes it almost impo s sible to separate the current
consumed by the SSI or the DSPCPU.
4. Measurements accuracy is +/ - 5% . Me asu rem ents ar e done with Vdd set to 2. 5V and Vcc set to 3.3V.
5. C urrents do not scale with frequency if t he CPU:SDRAM r atio are different. Same ratio must be used.
PNX1300
143:143 PNX1301
166:133 PNX1302
192:144 PNX1302
200:133
Symbol Current/Notes Pwd Typ Max Pwd Typ Max Pwd Typ Max Pwd Typ Max Units
VO
27 MH z IDD , running raw mode 50 28 39 55 29 38 65 16 26 72 27 36 mA
ICC , running raw mode - 9 17 - 12 17 - 12 17 - 12 17 mA
VO
81 MH z IDD , running raw mode -23 75 - 33 54 -30 58 -47 72 mA
ICC , running raw mode - 33 51 - 37 51 - 36 52 - 36 52 mA
VI
27 MH z IDD , running raw mode 6 8 18 6 6 18 7 8 18 7 6 18 mA
ICC , running raw mode - 7 14 - 6 14 - 8 15 - 9 15 mA
AO
44 KHz IDD , stereo 16-bit 2 3 1 1 3 1 1 3 4 5 3 3 mA
ICC , stereo 16-bit - 2 1 - 1 1 - 1 1 - 1 1 mA
AI
44 KHz IDD , stereo 16-bit 1 2 2 1 3 3 1 3 2 1 3 3 mA
ICC , stereo 16-bit - 1 1 - 1 1 - 1 1 - 1 1 mA
SPDIF
48 KHz IDD running PCM audio 2 3 2 2 3 1 3 3 3 4 2 2 mA
ICC running PCM audio - 3 3 - 2 2 - 2 2 - 2 2 mA
ICP IDD , mem. block move 61 95 176 67 95 170 80 105 188 86 106 184 mA
ICC , mem. block move - 28 28 - 27 54 - 30 61 - 29 59 mA
PCI
33 MH z IDD , DMA transfer - 37 83 - 34 80 - 32 83 - 40 53 mA
ICC , DMA transfer - 58 102 - 58 102 - 58 104 - 58 82 mA
VLD IDD 3 - -5 - -6 - -6 - -mA
ICC ------------mA
SSI
10 MH z IDD 4 - -5 - -6 - -6 - -mA
ICC ------------mA
DVDD IDD 18--21--24--24--mA
ICC ------------mA
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-16 PRELIMINARY SPECIFICATION
1.9.7.5 PNX1311 Current Consumption For On-Chip Peripherals
Notes: 1. The “Pwd” column for peripheral units indicates current savings when block powerdown is activated, compared to when it is
idle. See C hapter 21, “P ow er Management” for block powerdown acti vation .
2. The “Typ” column fo r peripher al units indic ates current r eq uired whe n data p atter n is random . The “Max” co lumn ind ica t e s
current ratings when data is switching from h igh to low level each cycle . Again that “Max” column is to sho w peak cu rrent
and does not represent a real application. For both columns the current reported is the current required by the peripheral as
well as the internal bus and MMI to transfer the data to/from the peripheral unit.
3. Some currents are not reported due to the diff iculty to measure it or because they are not relevant. For example SSI current
is difficult to measure because it heavily involves the DSPCPU and thu s makes it almost impo s sible to separate the current
consumed by the SSI or the DSPCPU.
4. Measurements accuracy is +/ - 5% . Me asu rem ents ar e done with Vdd set to 2. 2V and Vc c set to 3.3V.
5. C urrents do not scale with frequency if t he CPU:SDRAM r atio are different. Same ratio must be used.
PNX1311-100:100 PNX1311-143:143 PNX1311-166:166 PNX1311-166:133
Symbol Current/Notes Pwd Typ Max Pwd Typ Max Pwd Typ Max Pwd Typ Max Units
VO
27 MH z IDDL , running raw mode 33 17 23 47 25 33 56 29 38 48 24 31 mA
ICC , running raw mode - 8 12 - 12 17 - 14 20 - 25 17 mA
VO
81 MH z IDDL , running raw mode - 14 31 - 20 44 - 23 51 - 33 54 mA
ICC , running raw mode - 25 36 - 36 52 - 42 60 - 37 51 mA
VI
27 MH z IDDL , running raw mode 3 5 8 5 7 11 6 8 13 5 7 15 mA
ICC , running raw mode - 6 10 - 9 15 - 10 17 - 8 15 mA
AO
44 KHz IDDL , stereo 16-bit 4 2 1 6 3 2 7 3 2 1 2 2 mA
ICC , stereo 16-bit - 1 1 - 1 1 - 1 1 - 1 1 mA
AI
44 KHz IDDL , stereo 16-bit 1 1 1 1 2 2 1 2 2 1 2 3 mA
ICC , stereo 16-bit - 1 1 - 1 1 - 1 1 - 1 1 mA
SPDIF
48 KHz IDDL running PCM audio 2 2 1 3 3 2 3 3 2 2 2 2 mA
ICC running PCM audio - 1 1 - 2 2 - 2 2 - 2 2 mA
ICP IDDL , mem. blo ck move 40 55 101 57 79 144 66 92 167 60 76 136 mA
ICC , mem. block move - 19 38 - 27 55 - 31 64 - 26 54 mA
PCI
33 MH z IDDL , DMA transf e r - 17 36 - 25 51 - 29 59 - 20 50 mA
ICC , DMA transfer - 41 57 - 58 82 - 67 95 - 45 81 mA
VLD IDDL 3 - -4 - -5 - -4 - -mA
ICC ------------mA
SSI
10 MH z IDDL 2 - -3 - -3 - -4 - -mA
ICC ------------mA
DVDD IDDL 11--16--19--18--mA
ICC ------------mA
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-17
1.9.7.6 STRG3, STRG5 type I/O circui t
1.9.7.7 NORM 3 type I/O circuit
1.9.7.8 WEAK5 type I/O circuit
1.9.7.9 I ICOD (I2c) type I/O circui t
PNX1300/01/02/11
Symbol Parameter Condition/Notes Min. Nominal Max Units
VOH Output HIGH voltage IOUT = 16.0 mA 0.9VCC V
VOL Output LOW voltage IOUT = -16.0 mA 0.1VCC V
ZOH Output AC impedance HIGH level output state 11 ohm
ZOL Output AC impedance LOW level output state 11 ohm
trOutput rise time Test load of Figure 1-1.2.0ns
trOutput fall time Test load of Figure 1-1.2.0ns
PNX1300/01/02/11
Symbol Parameter Condition/Notes Min. Nominal Max. Units
VOH Output HIGH voltage IOUT = 8.0 mA 0.9VCC V
VOL Output LOW voltage IOUT = -8.0 mA 0.1VCC V
ZOH Output AC impedance HIGH level output state 23 ohm
ZOL Output AC impedance LOW level output state 23 ohm
trOutput rise time Test load of Figure 1-2.4.0ns
trOutput fall time Test load of Figure 1-2.4.0ns
PNX1300/01/02/11
Symbol Parameter Condition/Notes Min. Nominal Max. Units
VOH Output HIGH voltage IOUT = 6.0 mA 0.9VCC V
VOL Output LOW voltage IOUT = -6.0 mA 0.1VCC V
ZOH Output AC impedance HIGH level output state 33 ohm
ZOL Output AC impedance LOW level output state 33 ohm
trOutput rise time Test load of Figure 1-3.4.0ns
trOutput fall time Test load of Figure 1-3.4.0ns
Symbol Parameter Condition/Notes Min. Nominal Max. Units
VIL-IIC Input LOW voltage -0.5 1.0 V
VIH-IIC Input HIGH voltage VX is 3.3V or 5V depending
on VREF_PERIPH value 2.3 VX+0.5 V
VHYS Input Schmitt trigger hysteresis 0.25 V
VOL Output LOW voltage IOUT = -6.0 mA 0.6 V
tfOutput fall time 10 - 400 pF load 1.5 250 ns
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-18 PRELIMINARY SPECIFICATION
1.9.7.10 SDRAM interface timing for PNX1300/01/02/11 speed grades.
Notes: 1. For best high speed SDRAM operation, 50-ohm matched PCB traces are recommended for all MM_xxx signals.
Use 27-33 ohm series terminator resistors close to PNX1300/01/02/11 in the MM_CLK0 and MM_CLK1 line only.
2. Equal load circuit. MM_CLK0 and MM_CLK1 are matched output buffers.
3. The center of the two rising edges on MM_CLK0, MM_CLK1 are used as the clock reference point.
Propagation delay guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
Output hold time guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
4. MM_CLK0 is used as a reference clock.
Input setup time requirement is defined as data value 50% complete to 50% level on clock.
Input hold time requirement is defined as minimum time from 50% level on clock to 50% change on data.
1.9.7.11 PCI Bus timing
Th e fol lo w ing s pe c if i ca ti ons me et t h e PC I Spec ific ations , Re v. 2 . 1 for 33- M Hz bus op er a tio n.
Notes: 1. See the timing measurement condi tions in Figure 1-4.
2. Minim um ti mes are meas ur ed a t the p a ckage pin w ith the load cir cu it shown in Figure 1-8. Maximum ti mes are measure d
with the load circuit shown in Figure 1-6 and Figure 1-7.
3. REG# and GNT# a re poin t -to-p oint si gnal s and have diff erent input setup times. Al l other si gnals are bused.
4. See the ti ming measureme nt condi tions in Figure 1-5.
5. RST# is asserted and de-asserted asynchronously with respect to CLK.
6. All out put drivers are flo ated when RST# is active.
7. For the purpose of Active/Float timing measurements, the Hi-Z or ‘off’ state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
PNX1300
143 PNX1301
166 PNX1301
180 PNX1311
166 PNX1302
200 N
o
t
e
s
Symbol Parameter Min Max Min Max Min Max Min Max Min Max Units
fSDRAM MM_CLK frequency 143 166 166 166 183 MHz 1
TCS Skew between MM_CLK0, CLK1 0.05 0.05 0.05 0.05 0.05 ns 2
TPD Propagation delay of data, address, control 4.7 4.2 4.2 4.2 3.7 ns 3
TOH Output hold time of data, address and control 1.5 1.5 1.5 1.5 1.5 ns 3
TSU Input data setup time 0 0 0 0 0 ns 4
TIH Input data hold tim e 2.0 1.5 1.5 1.5 1. 5 ns 4
Symbol Parameter Min. Max Units Notes
Tval - PCI ( Bu s) Clk to sign al valid d elay, bu sed signal s 2 11 ns 1,2,3
Tval-PC I ( p tp) Clk to s ign al val id d elay, point-t o-poi nt si gnals 2 12 ns 1,2,3
Ton-PCI Float to active delay 2 ns 1
TOff-PCI Activ e to float delay 28 ns 1,7
Tsu-PCI Input setup time to CLK - b used signals 7 ns 3,4
Tsu-PCI (ptp) Input setup time to CLK - point-to-point signals 12 ns 3,4
Th-PCI Input hold time from CLK 0.21
1. PCI Clock skew between two PCI devices must be lower than 1.8ns instead of the 2 ns as specified in PCI
2.1 specification
ns 4
Trst-PCI Reset active time after power stable 1 ms 5
Trst-clk-PCI Reset active time after CLK stable 100 µs5
Trst-off-PCI Reset active to output float delay 40 ns 5,6,7
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-19
1.9.7.12 JTAG I/O timing
Notes: 1. See the timing measurement condi tions in Figure 1-10.
2. See the timin g measureme nt condition s in Figure 1-9.
1.9.7.13 I2C I/O timing
Notes: 1. See the timing measurement condi tions in Figure 1-11.
2. See the timin g measureme nt condition s in Figure 1-12.
3. See the timin g measureme nt condition s in Figure 1-13.
4. See the timin g measureme nt condition s in Figure 1-14.
5. See the timin g measureme nt condition s in Figure 1-15.
1.9.7.14 Video In I/O Timing
Notes: 1. See the timing measurement condi tions in Figure 1-16.
1.9.7.15 Video Out I/O Timing
Notes: 1. See the timing measurement condi tions in Figure 1-17.
2. See the timin g measureme nt condition s in Figure 1-18.
3. CLKOUT asserted, i.e. the VO unit is the source of VO_CLK
4. CLKOUT negated, i.e. the external world is the source of VO_CLK
Symbol Parameter Min. Max Units Notes
fJTAG-CLK JTAG clock fr equency 20 MHz
Tclk-TDO JTAG_T CK to JTAG_TDO valid de lay 2 10 ns 1
Tsu-TCK Input setup time to JTAG_TCK 3 ns 2
Th-TCK Input hold time from JTAG_ TCK 7 ns 2
Symbol Parameter Min. Max Units Notes
fSCL SCL clock frequency 400 kHz 1
TBUF Bus free time 1 µs2
Tsu-STA Start condition set up time 1 µs3
Th-STA Start condition hold time 1 µs3
TLOW SCL LOW time 1 µs1
THIGH SCL HIGH time 1 µs1
TfSCL and SDA fall time (Cb = 10-400 pF, from VIH-IIC to VIL-IIC) 20+0.1Cb 250 ns 1
Tsu-SDA Data setup time 100 ns 4
Th-SDA Data hold time 0 ns 4
Tdv-SDA SCL LOW to data out valid 0.5 µs5
Tdv-STO SCL HIGH to data out 1 ns 5
Symbol Parameter Min. Max Units Notes
fVI-CLK Video In clock frequency 81 MHz
Tsu-CLK Input setup time to VI_CLK 2 ns 1
Th-CLK Input hold time from VI_CLK 2 ns 1
Symbol Parameter Min. Max Units Notes
fVO-CLK Video Out clock frequency 81 MHz
TCLK-DV VO_CLK t o VO_DATA (o r VO _IO*) ou t 3 7. 5 ns 1,3
TCLK-DV VO_CLK t o VO_DATA (o r VO _IO*) ou t 3 7. 5 ns 1,4
Tsu-CLK VO_IO* setup time to VO _CLK 10 ns 2
Th-CLK VO_IO* hold time from VO_CLK 3 ns 2
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-20 PRELIMINARY SPECIFICATION
1.9.7.16 AudioIn I/O timing
Notes: 1. See the timing measurement condi tions in Figure 1-19.
2. The timing measurements are done with respect to the clock edge according to CLOCK_EDGE
3. SER _MAS TER asserte d, i.e. Au dio In is the source of AI_WS. See the t iming measurement condition in Figure 1-20.
1.9.7.17 Audio Out I/O timing
Notes: 1. See the timing measurement condi tions in Figure 1-21.
2. See the timin g measureme nt condition s in Figure 1-23.
3. The timing measurements are done with respect to the AO_SCK clock edge according to CLOCK_EDGE
4. PNX1300/01/02/11 is the serial interface master, i.e. AO_SCK, AO_WS are outputs
5. PNX1300/01/02/11 is serial interface slave, i.e. AO_SCK, AO_WS are inputs
6. See the timin g measureme nt condition s in Figure 1-22.
1.9.7.18 SSI I/O timing
Notes: 1. Interrupt latency limits SSI to a practical use at a bit rate of 1.5 Mbit/sec.
2. See the timin g measureme nt condition s in Figure 1-24.
3. See the timin g measureme nt condition s in Figure 1-25.
Symbol Parameter Min. Max Units Notes
fAI-SCK Audio In AI_SCK clock frequency 22 MHz
Tsu-SCK Input setup time to AI_SCK 3 ns 1,2
Th-SCK Input hold time from AI_SCK 2 ns 1,2
TSCK-WS AI_SCK to AI_WS 10 ns 3
Symbol Parameter Min. Max Units Notes
fAO-SCK Audio Out AO_SCK clock frequency 22 MHz
TSCK-DV AO_SCK to AO_SDx va lid 2 12 ns 1 ,3,4
TSCK-DV AO_SCK to AO_SDx va lid 2 12 ns 1 ,3,5
Tsu-SCK Input setup time to AO_SCK 4 ns 2,3,5
Th-SCK Input hold time from AO _S CK 2 ns 2 ,3,5
TSCK-WS AO _SCK to AO_WS 10 ns 3,4,6
Symbol Parameter Min. Max Units Notes
fSSI-CLK SSI_CLK clock fr equ ency 20 MHz 1
TCLK-DV SSI_CLK to data valid 2 12 ns 2
Tsu-CLK Input setup time to SSI_CLK 3 ns 3
Th-CLK Input hold time from SSI_CLK 2 ns 3
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-21
Figure 1-1. STRG3, STRG5 test load circuit
12 pF
Output
Buffer
rise/fall test point
2” true le ngth
50-ohm
30-ohm
PNX1300 pin
Figure 1-2. NORM3 test load circuit
30 pF
Output
Buffer
rise/fall test point
50-ohm
PNX1300 pin 2” true length
Figure 1-3. WEAK5 test load circuit
15 pF
Output
Buffer
rise/fall test point
50-ohm
PNX1300 pin 2” true length
V_test
T_on
T_off
V_trise
V_tfall
T_fval
T_rval
V_tl
V_th
CLK
Output
Tri-State
Delay
Output
Output
Delay
Figure 1-4 . PCI O utp ut Timi ng Mea sure ment Con-
ditions
inputs
V_test
V_tl
V_th
CLK
Input
Figure 1-5. PCI Input Timing Measurement Conditions
V_th
V_tl valid
V_test
V_test
T_h
T_su
V_max
10 pF
Figure 1-6. PCI Tval(max) Rising Edge
1/2 in. max
Output
25 Ω
Buffer
pin
10 pF
Figure 1-7. PCI Tval(max) Falling Edge
1/2 in. max
Output
25 Ω
Buffer
pin
Vcc
10 pF
Figure 1-8. PCI Tval(min) and Slew Rate
1/2 in. max
Output
1K Ω
Buffer
pin
1K Ω
Vcc
TCK
TDI, TMS
Figure 1-9. JTAG Input Timing
valid
Th_TCK
Tsu_TCK
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-22 PRELIMINARY SPECIFICATION
TCK
TDO
Figure 1-10. JTAG Output Timing
valid
Tclk_TDO
SCL
Figure 1-11. I2C I/O T iming
THIGH TLOW
Tr
Tf
SCL
SDA
Figure 1-12. I2C I/O T iming
TTBUF
SCL
SDA
Figure 1-13. I2C I/O T iming
Th_STA
Tsu_STA
SCL
SDA
Figure 1-14. I2C I/O T iming
valid
Th_SDA
Tsu_SDA
Figure 1-15. I2C I/O Timing
SCL
SDA valid
Tdv_STO
Tdv_SDA
VI_CLK
VI_DATA, VI_IO
Figure 1-16. VideoI n I/O Timing
valid
Th_CLK
Tsu_CLK
Figure 1-17. Video Out I/O Timing
VO_CLK
VO_DATA valid
TCLK_DV
VO_CLK
VO_IO
Figure 1-18. Video Out I/O Timing
valid
Th_CLK
Tsu_CLK
AI_SCK
AI_SD, AI_WS
Figure 1-19. Audio In I/O Timing
valid
Th_SCK
Tsu_SCK
Philips Semiconductors Pin List
PRELIMINARY SPECIFICATION 1-23
Figure 1-20. Audio In I/O Timing
AI_SCK
AI_WS valid
TSCK_WS
Figure 1-21. Audio Out I/O Timing
AO_SCK
AO_SDx valid
TSCK_DV
Figure 1-22. Audio Out I/O Timing
AO_SCK
AO_WS valid
TSCK_WS
AO_SCK
AO_WS
Figure 1-23. Audio Out I/O Timing
valid
Th_SCK
Tsu_SCK
Figure 1-24. SSI I/O Timing
SSI_CLK
SSI I/O valid
TCLK_DV
SSI_CLK
SSI_IO
Figure 1-25. SSI I/O Timing
valid
Th_CLK
Tsu_CLK
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
1-24 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 2-1
Overview Chapter 2
by Gert S lavenb urg
2.1 INTRODUCTION
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 is a successor to the TM-1300, TM-1100 a nd
TM-1000 media processors. For those familiar with the
TM- 13 0 0, the n ew f ea ture s s pe cifi c to the PNX1300 ar e
summarized in Section 2.6. For those familiar with the
TM-1100, the new fea tures specific to t h e PNX1300 ar e
summarized in Section 2.7. For those familiar with the
TM-1000, new features for the PNX1300 are summa-
rized i n Section 2.8.
2 .2 PNX 1300 FUND AME NTA LS
PNX1300 is a media processor for high-performance
multimedia ap plications that deal with high-quality video
and audio. Thes e ap pli cation s ca n range fr om low -co s t,
dedicated s ys tems su c h as vi de o phone s , vid eo ed i ti ng,
digital television, security systems or set-top boxes to re-
programmable, multipurpose plug-in cards for personal
computers. PNX1300 easily implements popular multi-
med ia st anda rds such as MPEG -1 and MPE G-2, bu t i t s
orientation around a powerful general-purpose CPU
(c alled th e D S PC P U) makes it capable of i mplementin g
a v ari et y of mu lt i medi a al go rit h ms, both o p en and pr opr i-
etary. PNX1300 is also easily configured in multiple pro-
cessor configurations for very high-end applications.
Mor e tha n ju st an integ rat e d mi crop roce ss or with u nus u-
al perip her als, t he P NX 1300 is a f luid c o mput er sy st em
controlled by a small real-time OS kernel running on a
very-long instruction word (VLIW) processor core.
PNX1300 contains a DSPCPU, a high-bandwidth inter-
nal bus, and internal bus-mastering DMA peripherals.
Sof twar e co mpa tibi lit y bet ween cu rre nt an d futur e Tri me-
di a pr oces sor family me mber s is at th e sour ce-cod e and
library API level; binary compatibility between family
members is not gu aranteed.
Def ini ng s oftw are c omp at ibili ty a t th e so urc e-co de l ev el
gives Phili ps the freedom to strike the optimum balance
between cost and performa nce for all chips in the f amily.
A powerful compiler and software development environ-
ment ensure that programmers never need to resort to
non-portable assembler programming. Programmers
use the library APIs and mult imedia o perations from C
and C++ source code.
PNX1300 is designed both for use as an accelerator in a
PC environment or as the sole CPU in cost-effective
st an dalone sy stem s. I n s t a ndalone s ystem applic at i ons,
the PNX1 300 ex tern al bus all ows fo r gluele ss con nect ion
of 8-bit wide ROM, EEPROM, or Flash memory for code
storage. The external bus also allows intermixing of
PC I2. 1 ma ster /sl av e p eri ph eral s a nd 8-bi t simpl e per ip h-
erals, such as UARTs and other 8-bit microprocessor pe-
ripherals. This powerful external bus architecture gives
system designers a variety of options to configure low-
cost, high-performance system solutions.
Because it is based on a general-purpose CPU,
PNX1300 can also serve as a multifunctional PC en-
hancement vehicle. Typically, a PC must deal with multi
st anda rd v i deo and a udio str eam s; and ap plic atio ns re -
quire both decompression and compression. While the
CPU chips used in PCs are becoming capable of low-
resolution, real-time video decompression, high-quality
decompression—not to mention compression—of stu-
dio-resolution video is still out of reach. Further, users
expect their systems to handle live video and audio with-
out sacrificing system responsiveness.
PNX1300 enhances a PC system by providing real-time
multimedia with the advantages of a special-purpose,
embedded solution—low cost and chip co unt—and the
advantages of a general-purpose processor—repro-
grammability. For PC applications, PNX1300 far sur-
passes the capabilities of fixed-function multimedia
chips.
Future media processor family members will have differ-
ent sets of inter faces appropriate for their intended use.
2.3 PNX1300 CHIP OVERVIEW
Key fe at ur es of P N X1 300 include:
•A very powerful, general-purpose VLIW processor
core (the DSPCPU) that coordinates all on-chip
activities. In addition to implementing the non-trivial
par ts o f multimed ia algorithms, the DSP CPU r uns a
sma ll re al -time oper atin g sys tem d ri ve n by int err upts
from the other units.
•Independent DMA-driven multimedia I/O units that
properly format data to make software media pro-
cessing efficient.
•DMA-driven multimedia coprocessors that operate
independently and in parallel with the DSPCPU to
perform operations specific to important multimedia
algorithms.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
2-2 PRELIMINARY SPECIFICATION
•A high-performance bus and memory system that
provide communication between PNX1300’s pro-
ce s sing units.
•A flexible external bus interface.
Figure 2-1 shows a PNX1300 block diagram. The bulk of
a PNX130 0 syste m consi sts of t he PNX 1300 micropro-
cessor itself, external synchronous DRAM (SDRAM),
and the ex ternal circ uitry needed to interface to incomin g
and/or outgoing v ideo and audio dat a str e am s and com -
muni cat ion line s. PNX13 00’s external peripheral bus can
gluelessly interface to PC! 2.1 components and/or 8-bit
microprocessor peripherals.
Figure 2-2 shows a possible minimally configured
PNX1300 system. A video input stream might come di-
rectly from a CCIR 656-compliant video camera chip in
YUV 4:2:2 format through a glueless interface in this
case. An analog c amera can be conne cted via a CCIR
656 interface chip (such as the Philips SAA7113H).
PNX1300 outputs a CCIR656 video stream to drive a
dedicated video monitor. Stereo audio input and up to 8-
channel audio output require only low-cost external ADC
and DAC. The operation o f the video and audio inter face
units i s highly customi zable through progra mmab le pa-
rameters.
The glueless PCI interface allows the PNX1300 to dis-
play video in a host PC’s video card . The Image Copro-
c essor (ICP) p rov id es disp lay su pp ort fo r liv e vid eo input
an arbitrary number of arbitrar ily o v erlapped windows.
PNX1300
Video In
Audio In
Audio Out
I2C Interface
VLD
Coprocessor
Video Out
Timers
Synchronous
Serial
Interface
Image
Coprocessor
VLIW
CPU 16K
D$
32K
I$
CCIR656 dig. video
YUV 4:2:2
up to 81 MHz (40 Mpix/sec)
Stereo digital a udio
8 and 16-bit data
I2S DC, up to 22 MHz AI_SCK
2/4/6/8 ch. digital audio
16 and 32-bit data
I2S DC, up to 22 MHz AO_SCK
I2C bus to
camera, etc.
Huf fman decoder
Slice-at-a-time
MP EG-1 & 2
CCIR656 digital video
YUV 4:2 :2
up to 81 MHz (40 Mpix/sec)
Analog modem or ISDN
front end
Down & up scaling
YUV → RGB
50 Mpix/sec
PCI-XIO Interface External bus
- PC!2.1 (32 bits, 33-MHz)
+ glueless 24A/8D slaves
SDRAM
Main Memory
Interface
DVDD
SPDIF Out
IEC958
up to 40 Mbit/sec
32-bit data
up to 572 MB/sec
Fig ur e 2-1 . PNX130 0 bloc k diagr a m.
Fi gure 2 -2. PNX 1300 syst em conn ecti ons. A mini mal
PNX1300 requires few supporting components.
PNX1300
CCIR656
digital video
2Mx32 SDRAM
ADC
stereo
audio in DAC 2 - 8 ch
audio out
CCIR656
dig. video
JTAG modem
front end
PCI and 8-bit peripheral bus
ROM
Philips Semiconductors Overview
PRELIMINARY SPECIFICATION 2-3
Finally, the Synchronous Serial Interface (S SI) requires
only an external ISDN or analog modem front-end chip
and phone line interface to provide remote communica-
tion support. It can be used to connect PNX1300-based
systems for video phone or videoconferencing applica-
tions, or it can be used f or general- purpose data commu -
ni ca tion in PC sy s tems .
The PNX1300 JTAG port allows a debugger on a host
system to access and control the state of a P NX1300 in
a target system. It also implements 1149.1 boundary
s can func tional ity.
2.4 BRIEF EXAMPLES OF OPERATION
Th e key to un der st anding PNX 1300 op eration is obse r v -
ing that the DSPCPU and peripherals are time-shared
and that communication between units is through
SDR A M memo ry. T he D SPCPU switches from one task
to the nex t; fir st it decom presses a video frame, then it
deco m pres ses a sl ice of the au dio str ea m, then back t o
video, etc. As necessary, the DSPCPU issues com-
mand s to t he peripher al func tio n units to orches trat e the ir
operation.
The DSPCPU can enlist the ICP and other coprocessors
to help with some of the straightforward, tedious tasks
associated with video processing. The ICP is very well
suit ed for arbi trar y s ize hori zo ntal and v er tica l vid eo re-
si zing and colo r s pace con ve rs i o n .
The DSP CPU can enlist the inpu t/output peripherals to
aut on om ou sl y re ceiv e or t rans mi t di git al video and au dio
dat a wi th min ima l C PU supe rv isio n. T he I /O un its have
been designed to interface to the outside world through
ind ustr y sta ndard au dio an d vide o in ter face s, whil e deli v-
ering or taking data in memory in formats suitable for
sof tware proces sing .
2.4.1 Video Decompression in a PC
An example PNX1300 implementation is as a video-de-
compression engine on a PCI card in a PC. In this case,
the PC does not need to know the PNX1300 has a pow-
e rful, gener al- pur pose C PU; r ath er, the PC just treats the
hardware on the PCI card as a ‘black-box’ engine.
Video decompression begins when the PC operating
system hand s the PNX 1300 a p oint er t o comp ressed vid-
e o da ta in th e PC ’s mem ory ( the de ta il s of th e comm un i-
cation protocol are handled by the software driver in-
stalled in the PC’s operating system).
The DSPCPU fetches data from the compres sed vid eo
stream via t he PCI bus, decompresses frames f rom the
video stream, and places them into local SDRAM. De-
compression may be aided by the VLD (variable-length
decoder) coprocessor unit, which implements Huffman
decoding and is controlled by the DSPCPU.
When a frame is ready fo r display, the DSPCP U giv es
the ICP a display command. The ICP then autonomously
fetches the decom p ressed f rame data from SDRAM and
transfers it over the PCI bus to the frame buffer in the
PC’s video display card. Alternately, video can be sent to
the graphics card using the VO unit.
2.4.2 Video Compression
Ano t her typi cal ap pl ic at i on for PNX13 00 is in vid eo com-
pression. In this case, uncompressed video is usually
s uppl ie d d ire ctly to the P NX1 30 0 syste m vi a th e V ideo I n
(VI) u nit. A cam e ra c hip conn ec t e d di r ec tl y to the VI uni t
supplies YUV data in 8-bit, 4:2:2 format. The VI unit sam-
ples the data from the camera chip and demultiplexes
the raw video to SDRAM in three separate areas, one
each for Y, U, and V.
When a comp lete video frame has be en read from the
camera chip by the VI unit, it interrupts the DSPCPU. The
DSPCPU compresses the video data in software (using
a set of powerful data-parallel multimedia operations)
and writes the compressed data to a separate area of
SDRAM.
The com pressed video data can now be transmitted or
stored in any of several ways. It can be sent to a host
sys t e m ov er the P CI bu s for arc h iv al on l ocal ma ss st o r-
age, or the h ost can t ransfer the compresse d video over
a network. The data can also be sent to a remote system
using the modem/ISDN interface to create, for example,
a video pho ne or vide oconfe r encing syst em.
Since the powerful, general-purpose DSPCPU is avail-
able, the compressed d a ta can be e n cr y p ted be f ore b e-
ing t ran s f erred for sec uri ty .
2.5 INTRODUCTION TO PNX1300 BLOCKS
Th e rem aind er o f this cha pte r pr ovid es a b rief i ntr oduc -
tio n t o the inter n al c om ponents of PNX 1 300.
2.5.1 Internal ‘Data Highway’ Bu s
Th e int ern al b us ( or da ta hi ghw ay) c onn ects all inter nal
bloc ks to g ether a nd prov ides acc ess to int ern al co nt rol/
s tatus re gisters of each block, external SDRAM, and the
ext erna l bus per iph era l chi ps. T he int ern al bu s co nsis ts
of separate 32-bit data and address buses. Transactions
on the bus us e a block-transfer protocol. On-chip peri ph-
eral units and coprocessors can be masters or slaves on
the bus.
Access to t he internal bus is controlled by a central arbi-
ter, which has a request line from each potential bus
master. The arbiter is programmable so that the arbitra-
tion algorithm can be tailored for different applications.
Peripheral units make requests to the arbiter for bus ac-
cess and, depending on the arbitration mode, bus band-
wid th i s allo ca te d to th e un it s in differ en t a mounts. Each
mode allocates bandwidth differently, but each mode
guarantees each unit a minimum bandwidth and maxi-
mum service latency. All unused bandwidth is allocated
to th e DSPC PU.
The b us a llocat ion me chan ism is one of the features of
PNX 1300 that make s it a tr ue real -time syste m instead of
just a highly integrated microprocessor with unusual pe-
ripherals.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
2-4 PRELIMINARY SPECIFICATION
2.5.2 VLIW Processor Core
The heart of PNX1300 is a powerful 32-bit DSPCPU
core. The DSPCP U impl ements a 32 -bit linear address
space and 128, fully general-purpose 32-bit registers.
The registers are not separated into ba nks; an y opera-
tion can use any register for any operand.
The P NX 1300 cor e uses a VL IW i ns tru ct io n-s et archi te c-
ture and is fully general-purpose. The VLIW instruction
leng th allow s f ive sim ult aneo us o perat io ns to b e is sued
ever y cl ock cyc le. Th ese operati ons can target a ny five
of th e 27 f u nc ti onal units in t h e DS PC PU, inc lu ding in t e -
ger and floating-point arithmetic units and data-parallel
multim edia o pe ra tion unit s .
Although the processor core runs a real-time operating
system to coordinate all activities in the PNX1300 sys-
tem, the core is not intended for true general-purpose
computer use. For example, the PNX1300 processor
core do es not impl emen t demand -p aged virt ual me mory,
mem ory addr ess tr an slati on , or 64 -b it flo ating poin t - a ll
essential features in a general-purpose computer sys-
tem.
PNX1300 uses a VL IW architec ture to maximize proces-
sor throughput at the lowest possible cost. VLIW archi-
te ctur es h ave p er forma nce e x ceed ing th a t of supe rs ca-
lar general-purpose CPUs without the cost and
complexity of a superscalar CPU implementation. The
har dware sa ved by elimi natin g supe rscala r logi c reduce s
cost and allows the integration of multimedia-specific
features that enhance the power o f the processor core.
The PNX1 300 oper atio n set in clud es al l trad iti onal mi cro-
pr oce ss or ope r atio ns . In ad dit io n, mu l timedia op era ti on s
are included that dramatically accelerate standard video
and audio compression and decompression algorithms.
As just one of the five operations issued in a single
PNX1300 instruction, a single ‘custom’ or ‘media’ op e ra-
tion can implement up to 11 traditional microprocessor
operations. These multimedia operations combined with
the VLIW architecture result in tremendous throughput
for multimedia applications.
The DSPCPU core is supported by separate 16-KB data
and 32-KB instruction caches. The data cache is dual-
por t ed to al lo w two si mul tan eo us acce sse s; both cache s
are 8-way set-associative with a 64- byte block siz e.
2.5.3 Video In Unit
The Video In (VI) unit interfaces directly to any CCIR 601/
656-compliant device that outputs 8-bit parallel, 4:2:2
YU V ti me-m ul tiple xe d dat a. S uch devices in clude direct
digital camera systems, which can connect gluelessly to
PNX1300 or through the standard CCIR 656 connector
with only the addition of ECL level converters. A single
c hip exter nal device can be used to co nvert to/from s e rial
D1 professional video. N on-CCIR-c ompliant devices can
use a digital video decoder chip, such as the Philips
SAA711 3 H, to i nte rfa ce to PN X 13 00 .
Th e V I unit d e multipl exes the c aptur ed Y UV d ata befo re
writing it into local PNX1300 SDRAM. Separate planar
data structures are maintained for Y, U, and V.
The VI unit can be programmed to perform on-the-fly
horizontal resolution subsampling by a factor of two if
need ed . Man y cam era sy st ems capt ure a 64 0-pix el /line
or 720-pixel/line image. With subsampling, direct conver-
sion to a 320-pixel/line or a 360-pixel/line image can be
performed with no DSPCPU intervention. Performing this
function during video input reduces initial storage and
bus bandwidth requirements for applications requiring
reduced resolution.
2.5.4 Enhanced Video Out Unit
The Enhanced Video Out (EVO) unit essentially per-
forms t he invers e fu nc ti on of the VI unit. EVO gene r at es
an 8-bit, CCIR656 digital video data stream that contains
a com posi ted v ideo and graphics overlay image. The vid-
eo image is taken from separate Y, U, and V planar data
structures in SDRAM. The graphics overlay is taken from
a pi xe l- p ack ed Y UV data str u c t ure in S DR A M . Com pos -
iting allows both alpha-blending and chroma keying.
The EVO uni t can al so upscal e t he vide o im age hor i zo n-
tally by a factor o f two to conv ert fro m CIF/ SIF to CC IR
601 reso lution. The overlay image, if enabled, is alway s
in full - pi xe l r es ol uti on.
Th e EV O un it is ca pa ble of pi xel em issi on r ates up to 40
Mpi x/sec and allow s full p rogr amm ing of a ho riz ontal an d
vertical fr ame/ fie ld str ucture. It is thu s cap able of refresh-
ing b oth i nterlaced and non-interlac ed (‘two f h’) vi deo di s-
plays with 4:3 or 16:9 or ot he r asp ect ra tios.
The samp le ra te f o r EV O u nit pi xe ls is in de pe nd en tly an d
dynamically programmable. The high-quality, on-chip
sample clock generator circuit allows the programmer
subtle control over the sampling frequency so that audio
and v ideo synchr onization can be achi eved in any sys-
tem configuration. When changing the sample frequen-
cy, the instantaneous phase does not change, which al-
lows sample frequency manipulation without introducing
audio or vid e o dis to r tio n.
2.5.5 Image Coprocessor
The ICP off-loads common image scaling or filtering
tasks from the DSPCPU. Although these tasks can be
eas il y pe r for me d by the DSP CP U, t hey a r e a po or use o f
the rel ativ el y e xpe ns iv e CP U reso urce . W hen pe r for me d
in parallel by the ICP, these tasks are performed effi-
ciently by simple hardware, which allows the DSPCPU to
co ntin ue w ith mo r e com plex task s.
The ICP can operate as ei ther a memo ry-t o-memory or a
memory-to -PCI coproces sor device.
In me mor y-t o -memo ry mod e, the ICP can per for m ei th er
horizontal or vertical image filtering and resizing. A high
quality algorithm is used (5-tap polyphase filter in each
direction). Filtering or scaling is done in either the hori-
zontal or vertical direction in one pass. Two invocat ions
of the ICP are required to filter or resize in both direc-
tions.
In memory-to-PCI mode, the ICP can perform horizontal
resizing followed by color-space conversion. For exam-
ple, ass ume an n × m pixe l arra y is t o be dis play ed in a
Philips Semiconductors Overview
PRELIMINARY SPECIFICATION 2-5
window on the PC video screen while the PC is running
a graphical user interface. The first step (if necessary)
would use the ICP in m emory-to-m emory mode to per-
form a vertical resizing. Th e second step would use the
ICP in memory-to-PCI mode to perform horizontal resiz-
ing and optional colorspace conversion from YUV to
RGB.
Wh il e send ing t he final, r e sampl ed and con ver te d pi xels
over the PCI bus to the video fra m e buff er, the ICP us es
a full, per-pixel occlusion bit mask—acce sse d i n de stin a-
tion coordinates—to dete r mine w hich pixe ls are a c t uall y
written to the graphics card frame buffer for d isplay. Co n-
ditioning the transfer with the bit mask allows PNX1300
to accommodate an arbitrary arrangement of overlap-
ping windows on the PC video screen.
Figure 2-3 illust rat e s a possi bl e di spl ay sit uati on and the
data structures in SDRAM that support ICP operation.
On the left, the PC video screen has four overlapping
windows. Two, Image 1 and Image 2, are being used to
display video generated by PNX1300. The right side
shows a concept ual view of SDRAM contents. Two data
s tru ctur e s ar e pr esent , one for Imag e 1 and the oth er for
Image 2. Figure 2-3 represents a point in time during
which the ICP is displaying Image 2.
Whe n the ICP is di spla ying an i mage ( i.e. , copy ing it f rom
SDRAM to a frame buffer), it maintains four pointers to
the SDRAM data structures . Three pointers locate the Y,
U, and V data arra ys, the fo urth lo c ate s the per-pix el oc -
clusion bit map. The Y, U, and V arrays are indexed by
source coordinates while the occlusion bit map is ac-
cessed with screen coordinates.
As the ICP generates pixels for display, it performs hori-
zonta l scaling and col orspace conversion. The final RGB
pixel value is then copied to the destination add ress in
th e s cre en ’s frame buffer only if the corresponding bit in
the occlu sion bit map is a ‘1’.
As shown in the conceptual diagram, the occlusion bit
map has a pattern of 1s and 0s corresponding to the
s hape o f t he visibl e ar e a of the des tin a t ion win do w i n the
frame buffer. When the a rrangement of windows on the
PC screen changes, modifications to the occlusion bit
map is perfor med by PNX 1300 or host resi dent sof tware.
It is important to note that there is no preset limit on the
numb er and size s o f win dows tha t c an be ha ndle d by t h e
ICP. The only limit is the available bandwidth. Thus, the
ICP can handle a few large windows or many small win-
dows. The ICP can sustain a transfer rate of 50 megapix-
els per second, which is more than enough to saturate
PCI when t ransferring images to video frame buffers.
2.5.6 Variable-Length Decoder (VLD)
The variable-length decoder (VLD) relieves the DSPCPU
of de codi ng Huff man-e ncode d video data stre ams. I t can
be used to help decode high bitrate MPEG-1 and MPEG-
2 vide o stre ams . T he low er bit rate of vide o c onfe ren cing
can be adequately handled by DSPCPU software with-
ou t c o pr o ce s so r .
The VLD is a memory-to-memory coprocessor. The
DSP CPU h a nd s th e V L D a p oi nter to a Huff m an -e nc od-
ed bit stream, and the VLD produces a tokenized bit
stream that is very convenient for the PNX1300 image
deco mp r essio n s of t ware t o use. The f o rm at of the ou t put
token stream is optimized for the MPEG-2 decompres-
sion software so that communication between the
DSPCPU and VLD is minimized.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1
1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PC Screen
Image 1
File Edit Format View
File Edit
FrameMaker 5
IMAGE 1
Calendar
In SDRAM
Image 2
Y
U
V
Y
U
V
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Image 1
Image 2
ICP
Figure 2-3. ICP - Windows on the PC screen an d data structures in SDRAM for two live video wi ndows.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
2-6 PRELIMINARY SPECIFICATION
2.5.7 Audio In and Audio Out Units
The Audio In (AI) and Audio Out (AO) units are similar to
the video units. They connect to most serial ADC and
DAC chips, and are programmable enough to handle
mos t se ria l bit p rotoc ol s. Thes e u ni ts c an tr an sfe r MS B
or LSB first and lef t or right channe l first.
The audi o sampl ing clock is driven by PNX1300 and is
s oft war e prog r am mab le with in a wide r ange. L ik e th e V O
unit, AI and AO sample rates are separately and dynam-
ically programmable. The high-quality on-chip sample
clock generator circuits allows the programmer subtle
control over the sampling frequency so that audio and
video synchronization can be achieved in any system
configuration. When changing the sample frequency, the
instantaneous phase does not change, which allows
sample frequency manipulation without introducing au-
dio or video distortion.
As with the video units, the audio-in and audio-out units
buffer incoming and outgoing audio data in SDRAM. The
audio-in unit buffers samples in either 8- or 16-bit format,
mono or s tereo. The audio-out un it transfers 16- or 32-bit
sampl e data f o r mono, ster e o or up to 8 a u di o c han nels
from memory to the exter nal DACs. Any manipulation or
mixing of sound data is performed by the DSPCPU since
this processing will require only a small fraction of its pro-
cessing capacity.
2.5.8 S/PDIF Out Unit
The Sony/Philips Digital Interface Out (SPDO) unit al-
lows output of a 1-bit high-speed serial data stream. The
pr imary ap pli cati on is ou tpu t of di git al au dio data in Sony/
Philips Digital Interface (S/PDIF) format to an external
ele ct r ic ally i solat e d t ran sf orm er . T he SP DO u ni t can als o
be used as a general purpose high-speed data stream
ou tput device s u c h as a U A R T.
The SPDO unit supports 2- channel PCM audio, one o r
more Dolby Digital six-channel data streams, or one or
more MPEG-1 or MPEG-2 audio streams (embedded
per Project 1937). It supports arbitrary programmable
sample rates independent of and asynchronous to the
AO unit samp le rat e.
2.5.9 Synchronous Serial Interface
The on-chip synchronous serial interface (SSI) is spe-
c ially d esig ned to int erfac e to h igh int egr ation anal og mo-
dem f ronten ds or IS DN f ron tend dev ice s. In t he analo g
modem case, all of the modem signal processing is per-
formed in the PNX1300 DSPCPU.
2.5.10 I2C Interf ace
The I2C bus is a 2-wire multi-master, multi-slave inter-
face capable of transmitting up to 400 kbit /s ec. PN X130 0
implem ents an I2C master for use in single master envi -
ron men t s only . This interface allow s PN X1300 t o config-
ur e and i nspe ct the s tat us of I2C peri pheral devi ces, suc h
as video decoders, video encoders and some camera
types.
2.6 NEW IN P NX1300 ( VERSUS TM-13 00)
PNX1300/01/02/11 offers the following improvements
over the TM-1300:
•Lower core voltage for PNX1311 (2.2V core voltage)
and therefore lower power consumption.
•DSPCPU speed of up to 200 MHz for PNX1302.
•Support for 256 Mbit SDRAM organized in x16. The
REFRESH counter must be changed. Refer for Sec-
tion 12.11, “Refresh” in Chapter 12, “SDRAM Mem-
ory System” for details.
•Su pp ort for 16 an d 32-bit M ain Me mo ry In te r face.
•Bu g fixes in V I m essa ge pa ssing mode.
•Additional VI mode where VI_DATA[9:8] in message
passing mode are not affected by the VI_DVALID
signal.
•PCI bu g fix on PCI S peci al Cy cles.
•Autonomous boot in non 1:1 ratio is fi xed.
2.7 NEW IN PNX1300 (VERSUS TM-1100)
In addition to the features described in Section 2.6
PNX1300 offers also the following improvements over
the TM-1100:
•no external MATCHOUT to MAT CHIN delay l ine.
•Video output speed improvement: up to 81 MHz.
•Video input speed impr ovement: up to 81 MHz.
•Prefetcheable SDRAM aperture to increase perfor-
mance. See Chapter 1 1, “PCI Interface.”
•Individual powerdown capability for each coproces-
sor (e.g. ICP, EVO, etc.).
•New AO coprocessor with four separate channels
and support of 16 or 32-bit samples. 8-bit samples
are no lon ge r s upp ort e d.
•New SPDO coprocessor (for output of SPDIF and
other 1-bit high-speed serial data streams)
2.8 NEW IN PNX1300 (VERSUS TM-1000)
In addition to the features described in Section 2.7
PNX1300 offers also the following improvements over
th e T M-1000 :
•New DSPCPU instructions. See Appendix A,
“PNX1300/01/02/11 DSPCPU Operations.”
•Video Output unit improvements (8-bit alpha blend-
ing, chroma keying, genlock). See Chapter 7,
“En ha nced V ide o O ut.”
•Capability to intermix PCI2.1 and 8-bit peripherals or
ROM/Flash memories on the external bus. See
Chapter 22, “PCI-XIO External I/O Bus.”
•An on-chip DVD authentication/descrambling copro-
cessor. Information available to DVD product devel-
opers on special request.
•Fu ll 11 49 .1 bo unda ry sca n.
•Improved PCI DMA read performance. See Chapter
11, “PCI Interf ace.”
•Improved clock generation with new DDS blocks.
PRELIMINARY SPECIFICATION 3-1
DSPCPU Architecture Chapter 3
by Ge rt Slavenburg, M arc el Janssens
3 .1 BAS IC ARCH IT ECTUR E CON CEP T S
In the document the generic PNX1300 product name
refers to PNX1300 Series, or the PNX1300/01/02/11
products.
This section documents the system programmer or
‘bare-machine’ view of the PNX1300 CPU (or D SPCPU).
3.1.1 Register Model
Figure 3-1 shows the DSPCPU’s 128 general purpose
reg is te r s, r0 ... r 12 7. In a d di t io n to the h ar d war e progr a m
counter, PC, there are 4 user-accessible special purpose
registers, PCSW, DPC (destination program counter),
SPC (source program counter), and CCCOUNT.
Table 3-1 li sts the r egis t e r s an d their pu rpos es.
Register r0 always contains the integer value '0', corre-
sponding to the boolean value 'FALSE' or the single-pre-
ci sion float ing poin t valu e +0 .0. R egis ter r1 alwa ys con -
tains the integer value '1' ('TRUE'). The programmer is
NOT allowed to write to r0 or r1.
Note: Wr i t in g t o r 0 or r 1 m ay cause reads from r0 or
r1 scheduled in adjacent clock cycles to return unpre-
dictable values. The standard assembler prevents/
forbids the use of r0 or r1 as a destination regi ster.
Reg is t e rs r 2 th r ou gh r127 ar e tru e general pu rpose reg-
isters; the hardware does not imply their use in any way,
though compiler or programmer conventions may assign
par t ic ular ro le s t o parti cu lar r egi st ers. The DPC and SPC
relate to interrupt and exception handling and are treated
in Sec tion 3.1.4, “SPC and DPC—Source and Destina-
tion Program Counter.” The PCSW (Program Control
and Status Word) register is treated in Section 3.1.3,
“PCSW Overview.” CCCOUNT, the 64-bit clock cycle
counter is treated in Section 3.1.5, “CCCOUNT—Clock
Cycle Counter.”
31 23 15 7 0
0 00
0 10
00000000000000000000000000000
00000000000000000000000000000
31 23 15 7 0
63 55 47 39
r0
r1
r2
r3
r126
r127
PC
PCSW
DPC
SPC
CCCOUNT
128 General-Purpose Registers
• r0 & r1 fixed
• r2–r127 v ari a ble
System Status & Control Registers
•
•
•
•
•
•
Fig ure 3-1. PNX1300 registers.
Table 3-1. DS PC PU register s
Register Size Details
r0 32 bits Always reads as 0x0; must not be used
as des tina tion of ope rations
r1 32 bits Always reads as 0x1; must not be used
as des tina tion of ope rations
r2–r127 32 bits 126 general-purpose registers
PC 32 bits Program co unter
PCSW 32 bits Program control & status word
DPC 32 bits Destina tion program counter; latches
target of taken branch that is interrupted
SPC 32 bits Source progr am counter; latches target
of taken branch that is not interrupted
CCCOUNT 64 bits Counts clock cycles sinc e rese t
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-2 PRELIMINARY SPECIFICATION
3.1. 2 Bas ic DSPCPU Execut ion Model
The DSPCPU issues one ‘long instruction’ every clock
cycle. Each instruction consists of several operations
(five operations for the PNX1300 microprocessor). Each
operation is comparable to a RISC machine instruction,
except that t he execution of an operation is conditional
upon the content of a general purpose register. Exam-
ples of oper ations are:
IF r10 iadd r11 r12 → r13
(if r10 true, add r11 and r12 and write sum in r13)
IF r10 ld32d(4) r15 → r16
(if r1 0 true, load 32 bits from m em[r15+4] i n t o r16)
IF r20 jmpf r21 r22
(if r20 true and r21 false, jump to address in r22)
Each operation has a s pe cific, known execution latency
i n c lo ck c y cl es . F o r e xa mpl e, iad d t ak e s 1 cyc le; thus th e
re sul t of an i a dd oper at ion star te d i n c lo ck cycle i is avai l-
able for use as an argument to operations issued in cycle
i+1 or l at er. The o ther o pera t ions i ss ued i n cy cle i can not
us e the result of ia dd. The ld32d operation has a latency
of 3 cycles. The result of an ld32d operation started in cy-
cle j is avai la bl e for use by other ope r ati ons issu ed in cy-
cle j+3 or later. Branches, such as the jmpf example
abo ve have three delay sl ots. This mean s that if a bra nch
operation in cycle k is take n, all op era t ions i n t he in stru c-
tions in cycle k+ 1, k + 2 and k+3 are still executed.
In the above examples, r10 and r20 control conditional
execution of the operations. Also known as ‘guarding’,
here r10 and r20 contain the oper a ti on ‘guard’. See Sec-
tio n 3. 2.1, “Gu ardin g ( C on di ti onal E x ec ut io n).”
Ce rtain restr ictions exi s t in the choice of what operat ions
can be packed into an instruction. For example, the
DSPCPU in PNX1300 allows no more than two load/
s tore class operati ons to be packed into a single instruc-
tion. Also, no more than five results (of previously started
operations) can be written during any one cycle. The
packing of operations is not normally done by the pro-
grammer. Instead, the instruct ion scheduler (See Philips
TriMedia SDE Reference Manual) takes care of convert-
ing the p ar a ll el inte r m edi ate format code into packed in-
structions ready for the assembler. The rules are formally
descr i be d in the machine descri ption file used by the in -
struction scheduler and other tools.
3.1.3 PCSW Overview
Figure 3-2 shows the PCS W re gi st er. The P NX1 30 0 val-
ue of PCSW on reset is 0x800. For compatibility, any un-
defined PCSW fields should never be modified.
Note that the DSPCPU architecture has no condition
codes or integer arithmetic status flags. Integer opera-
tions that generate out-of-range results deliver an opera-
tion specific bit pattern. For examples, see dspiadd in
Appe ndix A, “PNX1300/01/02/11 D SP CP U Operati on s . ”
Predicate operations exist that take the place of integer
status flags in a classical architecture. Multiword arith-
metic is supported by the ‘carry’ o p erat i on w hic h gene r -
ates a ‘0’ or ‘1’ depend ing on th e carry that would be gen-
erated if its arguments were summed.
FP-Related Fields.The IE EE mod e f ie ld deter mine s the
IEEE rounding mode of all fl oating p oint operations, with
the exception of a few floating point conversion opera-
ti on s t hat use f i xed r o un ding mode . For ex amp les, s ee if-
ixrz, ifloatrz, ifixrz, ifloatrz in Appendix A, “PNX1300/01/
02/ 1 1 D S P CP U Operat i on s . ”
The FP exception flags are ‘sticky bits’ that ar e s et as a
side e ffect of floating-point computations. E ach floating
poi nt op erati on can set one or mor e of the flag s if i t incurs
the corresponding exception. The flags can only be reset
by direct software manipulation of the PCSW (using the
write pcsw op erati on) . The bits have the meanings shown
in Table 3-2.
The FP exception trap enable bits deter mine which FP
exception flags invoke CPU exce ption handling. A n ex-
cept ion is requested i f the intersection of the exception
flags and trap enable flags is non-zero. The acceptance
and handling of exceptions is described in Section 3.5,
“Special Event Hand ling.”
BS X (Byt esex ). The DSPCPU has a switchable bytesex.
The BSX flag in the PCSW can be written by software.
Load/store operations observe little- or big-endian byte
ordering based on the current setting of BSX.
IEN (Interrupt Enable). The I EN fl ag di sables or en able s
interrupt processing for most interrupt sources. Only NMI
(n on-mas kable inte rrupt ) bypass es IEN. Th e accep tanc e
and handling of interrupts is described in S ection 3.5.3,
“IN T and N MI (M askab le an d Non -Mas kable Inte rrupt s). ”
MSE CS IEN BSX I EEE MODE OFZ IFZ INV OVF UNF INX DBZ
01234567891011121415
Misaligned store exce p tion
Count stalls (1 ⇒ Yes)
FP exception trap-enable bits
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW[31:16]
PCSW[15:0] UNDEF
Misaligned store
exceptio n tr ap enable Trap on first exit
FP exceptions
TRP
MSE TFE TRP
OFZ TRP
IFZ TRP
INV TRP
OVF TRP
UNF TRP
INX TRP
DBZ
1617181920212223252627283031
UNDEF UNDEFINED
13
WBE RSE
Write back error
Reserved exception
TRP
WBE TRP
RSE
Write back error trap enable Reserved exception
trap enabl e
29
PCSW = 0x800
after RES ET
Figure 3-2. PNX1300 PCSW (Program Control a nd Status Word) register format.
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-3
CS (Count Stalls). The CS flag determines the mode of
CCCOUNT, the 64 -bit clock cycle counter. If CS = ‘1’, the
cycle co unter increments on all clock cycles. If CS = ‘0’,
the clock cycle counter only increme nts on non -stall c y -
cl es. Se e al so Section 3.1.5, “CCCOUNT—Clock Cycle
Counter.” After RESET, CS is set to ‘1’.
MSE and TRPMSE (Misaligned-Store Exception). Th e
MSE bit will be set when the processor detects a store
ope r at ion t o an ad dre ss t hat is not ali gned . For example,
a 32-b it stor e ex ecu ted wi th a n ad dre ss t ha t is n ot a mul-
tiple of four will cause MSE to be set. The TRPMSE bit
enables the DSPCPU to raise misaligned address ex-
ceptions . An ex ce ption is requ ested if the inte r s e ct ion of
MSE and TRPMSE is non-zero. The acceptance and
handling o f excep t ions is de scribed in Section 3.5, “Spe-
cial E v ent H andli ng. ”
Unaligned load operations do not cause an exception,
because load oper ati ons c an be speculative (i.e. their re-
sult is th r o wn away).
Whe n the DSPCPU gene rate s an un aligne d add ress , the
low order address bit(s) (one bit in the case of a 16-bit
load, two bits for a 32-bit load) are forced to zero and the
load/s t or e is ex ec u t ed fro m this a lig ne d addr e s s.
WBE and TRP WBE (Write Back Error). The W BE fl ag
will be set whenever a program attempts to write back
more than 5 results simultaneously. Th is is indicative of
a programming error, likely caused by the scheduler or
assembler. The TRPWBE bit enables the corresponding
exception.
RSE, TRPRSE (Reserved Exception). RSE and TR-
PRSE are reserved for diagnostic purposes and not de-
scribed here.
TFE (Trap on First Exit). Th e TFE bit is a sup por t bit for
the debu gg er . The TFE bi t i s s et by the d eb ug ger pr ior t o
taking a (non-interruptible) jump to the application pro-
gram. On the next interruptible jump (the first interrupt-
ible jump in the application being debugged), an excep-
tion is requested because the TFE bit is set. The
acceptance and handling of exception processing is de-
scribed in Section 3.5, “Spec ial Even t Ha ndling .” It is the
responsibility of the exception handler software to clear
the TFE bit. The hardware does not clear or set TFE.
Corner-case note: Wh enev er a hard ware update (e.g. an
exception be ing raised) and a software update (through
writepcsw) of the PCSW coincide, t he new value of the
PCSW will be the value that is writ ten by the writepcsw
instruction, except for those bits that the hardware is cur-
ren tl y up dating ( which w i ll r efl ec t the h a r dwa r e val u e).
3.1.4 SPC and DPC—Source and
Destination Program Counter
The SPC and DPC registers are support registers for ex-
c epti on pro ces sing . T h e DPC is upda te d dur i ng every i n-
te rr uptible jump w ith the t a r get addr es s of t hat inter r upt -
ible jump. If an exception is taken at an interruptible
jump, the value in the DPC register can be used by the
exception hand ling routine as the ret urn address to re-
sume the program at the place of interruption.
The SPC register is updated during every interruptible
jump that is not interrupted by an exception. Thus on an
interrupted interruptible jump, the SPC register is not up-
dated. The SPC register allows the exception handling
ro utin e to det ermin e the start addre ss of t he decisi on tre e
(a block of uninterruptible, scheduled PNX1300 code)
that was executing when the exception was taken (see
also Se c tio n 3. 5 , “Special Event Handling”).
Corner-case note: Whe ne ver a hard w are up dat e (dur in g
an interruptible jump) and a software update (through
wri tedp c or writ espc) coi ncid e, the so ftware update takes
precedence.
3.1.5 CCCOUNT—Clock Cycle Counter
CCCOUNT is a 64-bit counter that counts clock cycles
since RESET. Cycle counting can occur in two modes,
depending on PCSW.CS. If PCSW.CS = ‘1’, the cycle
count increm ents on eve ry CPU clock cycle. If PCS W.CS
= ‘0’, the clock cycle count only increments on non-stall
CPU cycles.
CCCOUNT is implemented as a master counter/slave
register pair. The master 64-bit counter gets updated
continuously. The val ue of the CCCOUNT slave register
is updated with the current master cycle count during
successful interruptible jumps only. The cycles and hicy-
cles DSPCPU operations return the content of the 32
LSBs and 32 MS Bs, resp ectively , of the slave r egister .
Th is ens u re s th at t h e va lu e r et ur n ed by h ic ycle s and cy-
cles is coherent, as long as there is no intervening inter-
ru pt ib le jum p, whic h mak es thes e op er ati on s sui tab le for
64-bit high resolution timing from C source code pro-
gr ams. The curcycles DSPCPU operation returns the 32
LSB s of th e mas te r counter. The latter operation can be
use d for inst ruction cycle p recise timi ng. When used, it
must b e p rec is el y p lac ed, proba bl y at the ass emb ly code
level.
3.1.6 Boolean Representation
The bit pattern generated by boolean valued operat ions
(ileq, fleq etc.) is '00...00' (FALSE) or '00...01' (TRUE).
Wh en inter preting a bit pattern as a boolea n value, only
the LSB is taken into account, i.e. 'xx..x0' is interpreted
as FALS E an d 'xx ..x 1 ' is inter pre ted a s TR UE . In p ar t ic -
ular, where ver a gene ral purpose register is used as a
‘guard’, the LSB determines whether execution of the
guarded operation takes pl ace.
Tabl e 3 - 2 . PCSW FP exce ptio n flag d efi nitions
Flag Function
INV Standard IEEE invalid flag
OVF Standard IEEE overflow flag
UNF Standard IEEE underflow flag
INX Standard IEEE inexact flag
DBZ Standard IEEE divide-by-zero flag
OFZ ‘Output flushed to zero’ set if an operation caused a
denormalized result
IFZ ‘Input flushed to zero’ set if an operation was applied to
one or more denormalized operands
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-4 PRELIMINARY SPECIFICATION
3.1.7 Integer Representation
The architecture supports the notion of 'unsigned inte-
ger s' and 'sig ne d i nt eger s .' Sign ed in te ger s u se th e s tan-
dar d tw o ’s-complement representation.
Arithmetic on integers does not generate traps. If a result
is not representable, the bit pattern returned is operation
specific, as defined in the individual operation description
section. The typical cases are:
•Wrap around for regular add- and subtract-t yp e oper -
ations.
•Clamping against the minimum or maximum repre-
sentable value for DSP- type oper a t io ns.
•Returning the least significant 32-bit value of a 64-bit
result (e.g., integer/unsigned multiply).
3.1.8 Floating Point Representation
The PNX1300 architecture supports single precision (32-
bit) IEEE-7 54 fl oa ti ng po int ar it hmet ic .
All arithmetic conforms to the IEEE-754 standard in
flush-to-zero mode.
All floating point c o mpute op erati on s roun d ac cordin g t o
the current setting of the PCSW IEEE mode field. The
cur rent set ti ng of the field de t erm ine s r es ul t ro un di ng (t o
neare st, t o ze ro, to positiv e in finit y, to negative infinity).
Conversions from float to integer/unsigned ar e availab le
in two forms: a PCSW rounding-mode-observing form
and an ANSI-C-specific-rounding form. The ANSI-C-
specific form forces round to zero regardless of the
PCSW IEEE rounding mode. Conversion from integer/
unsigned to float always observes the IEEE rounding
mode.
Flo at ing poin t e xce pti on s ar e supp or ted wit h tw o m echa-
nis ms. Ea ch ind ivid ual floa tin g point op eration (e.g. fadd)
has a counterpart operation (faddflags) that computes
the exception flag values. These operations can be used
for pre ci se ex ce pt io n iden t if icat i on1. The second mech a-
nism uses the ‘sticky’ exception bits in the PCSW that
collect aggregate exception events. The PCSW excep-
tion bits can selectively invoke CPU exception handling.
See S ec tio n 3. 5 .2 , “EXC (Exceptions).”
Table 3-3 shows the representation choices that were
made in PNX1300’s floating point implementation.
3.1.9 Addressing Modes
The addressing modes shown in Table 3-4 are support-
ed by th e DS PCPU arch it ectu re (s tore o pe ratio ns al lo w
only dis placem ent mo de).
In these addressing modes, R[i] indicates one of th e gen -
er al purpos e regist ers. The scale fa ctor ap pli ed (1/2 /4) is
equal to the size of the item loaded or st ored, i.e. 1 for a
byte op erati on , tw o for a 16- bit op erati on and four f or a
32-bit operation. The range of valid 'i', 'j' and 'k' values
may d iffer be twee n impl em enta tion s of th e archi te cture ;
the min imum val ues for impl ementa tio n-dep enden t char-
act e r istics are sh ow n in Table 3-5.
Not e tha t th e as se m bl y co de sp ec if ie s the t ru e dis place -
ment, and not the value to be scaled. For example,
‘ld32d(–8) r3’ load s a 32 -b it value f r om ad dre ss (r 3 – 8) .
Thi s i s e nc ode d i n th e b in ar y o per at ion patt er n as a –2 in
the seven-bit field by the assembler. At runtime, the
scale factor four is applied to reconstruct the intended
displacement of –8.
3.1.10 Software Compatibility
The DSPCPU architecture expressly does not support
binary compatibility between family members. The ANSI
C c om piler e n s ur es t hat all fam ily mem bers are compat-
ible at t h e so ur c e- co de le v el .
1. This mechanism allows precise exception identification
in the context of our multi-issue microprocessor core—
where many floa ting point opera tions may i s sue s imu l-
taneously—at the expense of additional operations
generated by the compiler. It also allows the compiler to
issue compute operations speculatively and compute
except ions pr ec isely .
Table 3-3. Special Float Value Representation
Item Representation
+inf 0x7f800000
-inf 0xff800000
self generated qNaN 0xffffffff
result of operation
on any NaN argu-
ment
argument | 0x00400000 (forcing the
NaN to be quiet)
sig nalling NaN never generated by PNX13 00,
accepted as per IEEE-754
Table 3-4. Addre s sing Modes
Mode Suffix Applies to Name
R[i] + scaled(#j) d Load & Store Displacement
R[i] + R[k] r Load only Index
R[i] + scaled(R[k]) x Load only Scaled index
Table 3-5. Minim um values for im plementation-
dependent addressing mode components
Parameter Minimum Range
‘i’ and ‘k’0..127 (i.e., each implementation has at least 128
registers)
‘j’-64..63 (i.e., displacements will be at least 7 bits
long and signed)
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-5
3.2 INSTRUCTION SET OVERVIEW
3.2.1 Guarding (Conditional Execution)
In the PNX1300 architecture, all operations can be op-
tionally 'guarded'. A guarded operation executes condi-
tionally, depending on the value in the ‘guard' register.
For exa mple, a guarded add is written as:
IF R23 iadd R14 R10 → R13
This should be taken to mean
if R23 then R1 3 ← R14 + R10.
The ’if R23' clause controls the execution of the opera-
tio n ba se d on the LSB of R2 3. H en c e, depend ing on the
LSB of R23, R13 is either unchanged or set to contain
the integer sum of R1 4 and R10.
Gu ardin g app lies to al l DSP CPU ope ration s, ex cept ii mm
and uimm (load-immediate). It controls the effect on all
pr ogramme r-vi sibl e states of t he system, i.e. registe r val-
ues , memo ry cont ent, exc epti on rai sing an d device st ate.
3.2.2 Load and Store Operations
Memory is byte addressable. Loads and stores must be
‘natu rally alig ne d’, i.e. a 16-bit load or store must target
an ad dre ss th at is a m ultip le of 2. A 32 -bi t load or sto re
mus t ta rget an ad dres s that is a m ultip le of 4. The BS X
bit in the PCSW determines the byte order of loads and
stores. For example, see ld32 an d st32 in Appendix A,
“PNX1300/01/02/11 DSPCPU Operations.”
Only 32-bit load and store operations are allowed to ac-
c ess M MIO reg ist ers in th e MMI O add res s ap ert ur e (se e
Sec tio n 3.4, “Memory and MMIO”). The r esults are unde-
fined for other loads and stores. A load from a non-exis-
ten t MMI O re gister retu rns an undef ined res ult. A sto re to
a non-existent MMIO register times out and then does
not happen. There are no other side effects of an access
to a nonexistent MMIO register. The state of the BSX bit
has no effec t on the result of MMIO accesses.
Loads are allowed to be issued speculatively. Loads out-
side t he range of valid da ta memo ry addresses for the
active process return an implementation -dependent val-
ue a nd do n ot ge ner ate a n ex ce ptio n. Mi sali gn ed l oads
also return an implementation dependent value and do
not generate an exception.
If a pai r of mem ory op erati ons i nvolves one or mor e com-
mon b yt es in me mory , the ef f ect on the co mmon b yt es is
as defined in Table 3-6.
Table 3-4 shows the supported addressing modes. The
minimum values of implementation-dependent address-
ing-mode components are shown in Table 3-5.
Note: The index and scaled-index modes are not
allowed with store opcodes, due to the hardware
res triction that each operation have a t most 2 source
operand registers and 1 condition register. Stores
use 1 operand register for the value to be stored
leaving only 1 register to form an address.
Th e sca le factor a pplie d (1 /2/4) in the sc aled ad dressing
mod es is e qual to th e siz e of the i tem lo aded or st ored ,
i.e . 1 fo r a byte opera tion , 2 for a 1 6-b it oper atio n and 4
for a 32-bit operation.
Table 3-7 lists the available load and store mnemonics
fo r th e three ad dr e s si ng m od es.
Ex am ple us age of load and store op e ratio ns:
IF r10 ild16d(12) r12 → r13
If the LSB of r10 is set, load 16 bits starting at
address (r12+12) using the byte ordering indicated
in PCSW.BSX, sign-extend the value to 32 bits and
store the result in r13.
IF r10 st32d(40) r12 r13
If the LSB of r10 is set, store the 32-bit value from
r13 to the address (r12+40) using the byte ordering
ind ica te d in PCSW.BS X.
Table 3-6. Behavior of loads and stores with
coincident addresses
Condition Behavior
Tstore < Tload If a store is issued before a load, the value
loaded contains the new bytes.
Tload < Tstore If a load is issued bef ore a store, the value
loaded contains the old bytes.
Tstore1 < Tstore2 If store1 is issued before s tore2, the result-
ing value contains the bytes of store2.
Tstore = Tload If a load and store are issued in the same
clo ck cy cle, the result is UNDEFINED.
Tstore1 = Tstore2 If two stores are issued in the same clock
cycle, the resulting stored value is unde-
fined.
Table 3-7. Load a nd store mnemoni c s
Operation Displacement Index Scaled-
Index
8-bit signed load ild8d ild8r —
8-bit unsigned load uld8d uld8r —
16-bit signed load ild16d ild16r ild16x
16-bit unsigned load uld16d uld16r uld16x
32-bit load ld32d ld32r ld32x
8-bit store st8d ——
16-bit store st16d ——
32-bit store st32d ——
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-6 PRELIMINARY SPECIFICATION
3.2.3 Compute Operations
Compute operations are register-to-register operations.
The specified operation is performed on one or two
so urce reg iste rs and th e r esul t is w ri tten to th e des ti na-
tion register.
Immediate Operations. Immediate operations load an
immediate constant (specified in the opcode) and pro-
duce a res ult in the destination register.
Floating-Point Compute Operations. Floating-point
compute operations are register-to-register operations.
The specified operation is performed on one or two
so urce reg iste rs and th e r esul t is w ri tten to th e des ti na-
tion register. Unless otherwise mentioned all floating
poi nt operat i on s ob se rve t he roun di ng mod e bi ts def ine d
in the PCSW register. All floating-point operations not
ending in ‘flags’ update the PCSW exception flags. All
oper ati ons en ding in ‘flags’ com p ut e th e ex cep t io n f la gs
as if the operation were executed and return the flag val-
ues (in the same format as in the PCSW); the exception
fla gs in t he PC SW itself re main unchanged .
Multime dia O pe r ati ons. These special compute opera-
tions are like normal compute operations, but the speci-
fied operations are not usually found in general purpose
CPUs. These operations provide special suppor t for mu l-
timedia applicat ions.
3.2.4 Special-Register Operations
Sp ec ial regis t er op erati ons op erate on the spe cial re gis-
ters: PCSW, DPC, SPC and CCCOUNT.
3.2.5 Control-Flow Operations
Con t rol-flow operat i ons change the value of the pr og r am
counter. Conditional jumps test the value in a register
and, b as ed o n thi s v al ue , c han ge the pr og ram c oun t er t o
the address contained in a second register or continue
exec ution w ith the next in st r uction. Unc ond itional jum ps
al ways change the progr am co unter to the s pecified im -
med i a te ad dr e ss .
Control-flow operations can be interruptible or non-inter-
ruptible. Execut ion of an interruptible ju mp is th e onl y oc-
casion where PNX1300 allows special event handling to
take place (see Secti on 3.5, “Spe cial E v ent Ha ndli ng ”).
3.3 PNX1300 INSTRUCTION ISSUE RULES
The PNX 13 00 VL I W CPU al low s i ssu e of 5 oper a tio ns i n
each clock cycle according to a set of specific issue
rules. The issue rules impose issue time constraints and
a result writeback constraint . Any set of operations t hat
meets all constraints constitutes a legal PNX1300 in-
s tru ctio n. A mo re e xten si v e d es cript i on and a f e w sp eci a l
c ase issue rules and lim itations can be f ound in the Phi l-
ips TriMedia SDE documentation.
Is su e tim e c on str ai nts :
•an operation implies a need for a functional unit type
(as documented in Appendix A, “PNX1300/01/02/11
DSPCPU Operations.”)
•each operation requires an issue slot that has an
instance of the appropriate functional unit type
attached
FALU DSPMUL DSPMUL FALU DMEMSPEC
SHIFTER SHIFTER FCOMP DMEM DMEM
BRANCH BRANCH BRANCH
IFMUL IFMUL
DSPALU FTOUGH
(latency 17,
recovery 16)
DSPALU
ALU ALU ALU ALU ALU
CONST CONST CONST CONST CONST
issue slot 1 issue slot 2 issue slot 3 issue slot 4 issue slot 5
Figure 3-3. P NX1300 i ssue sl ots , functional units, and la tency.
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-7
•functional units should be ‘recovered’ from any pr ior
oper a tion is su es
Writeba ck constraint:
•No more than 5 results should be simultaneously
written to the register file at any point in time (write-
ba ck oc cu r s ‘latency’ cycles after issue)
Figure 3-3 shows all functional units of PN X1300, includ-
ing t he r e lation t o iss ue slo t s , and ea ch f unctiona l unit’s
latency (e.g. 1 for CONST, 3 for FALU, etc.). With the ex-
ception of FTOUGH, each functional unit can accept an
operation every clock cycle, i.e. has a recovery time of 1.
The binding of operations to functional unit types is sum-
marized in Table 3-8. In Appendix A, “PNX1300/01/02/
11 DSPCPU Operations”, each operation lists the pre-
cise functional unit and unit latency.
3.4 MEMORY AND MMIO
PNX1300 defines four apertures in its 32-bit address
space: the memory hole, the DRAM aperture, the MMIO
aperture and the PCI apertures (See Figure 3-4).The
memory hole covers addresses 0..0xff. The DRAM and
MMIO ap er t ures ar e de fine d by the v al ues in MM IO reg -
isters; the PCI apertures consist of every address that
does not fall in the other three apertures.
3.4.1 Memory Map
DRAM is mapped into an aperture extending from the
address in DRAM_BASE to the address in
DRAM_LIMIT. The maximum DRAM aperture size is 64
MB.
Th e MM IO ap ertur e is loc ated a t a ddres s MM IO_ BAS E
and is a fix e d 2-M B size.
In the defau l t operating mode, a ll m emo r y ac ces se s n ot
goi ng to eith er the hole, DRAM or MMI O spa ce are i nter -
preted as PCI accesses. This behavior can be overrid-
den as described in Section 5.3.8, “Memory Hole and
PCI Aperture Disable.”
The MMIO aperture and the DRAM aperture can be at
any naturally aligned location, in any order, but should
not overlap; if they do, the consequences are undefine d.
The values of DRAM_BASE, DRAM_LIMIT, and
MMIO_BASE are set during the boot process. In the
case of a PCI host assisted boot, the values are deter-
min ed b y t he host B IOS. In ca s e of sta ndal one b oot (i.e .,
PNX1300 is the PCI host), the values are taken from the
boot ROM. Re fer to Chapter 13, “System Boot” for de-
tails. DSPCPU update of DRAM_BASE and
MMIO_BASE is possible, but not recommended, see
Secti on 11.6.3, “MMIO/DRAM_BASE updates.”
3.4.2 The Memory Hole
The memory hole from address 0 to 0xff serves to protect
the system from performance loss due to speculative
loads. Due to the nature of C program references, most
speculative loads issued by the DSPCPU fall in the
ra nge co vered b y the hole. Acti vate d by de fault upon RE-
SET, the hole serves to ensure that these speculative
lo ad s d o N O T caus e P CI r e ad a cces s es and slow down
the system. The value returned by any data load from the
hole i s 0. The hole onl y pro te c t s loads. Store operations
in t he hole do caus e w rites to P CI , SD R A M or MM I O as
determined by the aperture base address values. If the
SDRAM ap ertur e ov erlaps the m emory h ole, the memory
hole is ignored.
The hole can be temporarily disabled through the
DC_LOCK_CTL register. This is described in Section
5.3.8, “Memory Hole and PCI A perture Disable.”
3.4.3 MMIO Memor y Ma p
Devices are controlled through memory-mapped device
re gi ster s, ref err ed t o a s MMIO reg iste r s. T o ensure com-
patibility with future devices, any undefined MMIO bits
should be ignored when read, and written as ‘0’s. Some
devices can autonomously access data memory (DMA)
and most devices can cause CPU i nterrupts.
The 2-MB MMIO aperture is initially located at address
0xEFE00000 on RESET; it is relocated by the PCI BIOS
Table 3-8. Functional unit operations
unit ty pe operati on category
const immediate operations
alu 32-bit arithmetic, logical, pack/unpack
dspalu dual 16-bit, quad 8-bit multimedia arithmetic
dspmul dual 16-bit and quad 8-bit multimedia multiplies
dmem loads/stores
dmemspec cache coherency, cache control, prefetch
shifter multi-bit shift
branch control flow
falu floating poi nt arithme tic & conversions
ifmul 32-bit integer and floating point multiplies
fcomp single cycle floating point compares
ftough iterative floating point sq uare root and division
hole
256byte
0x0000 0000
PCI
MMIO_BASE
MMIO Ap ert ure
DRAM_LIMIT
DRAM_BASE
DRAM Aperture
0xFFFF FFFFF
PCI
2 MB
1 MB - 64 MB
PCI
Fig ur e 3-4 . PNX130 0 memor y m a p .
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-8 PRELIMINARY SPECIFICATION
for PC-hosted PNX1300 boards; its final location is de-
termined by the boot EEPROM for stand alone systems.
See Chapter 13, “System Boot” for more information.
Figure 3-5 gives a detailed overview of the MMIO mem-
ory m ap (a d dre ss e s use d a re of fs ets w ith respect to t he
MMIO base). The operating system on PNX1300 can
change MMIO_BASE by writing to the MMIO_BASE
MMI O location. User prog rams should no t attempt thi s.
Refer to the TriMedia SDE Reference Manual for the
standard method to acces s the device registers fro m C
lang uage device drivers.
Only 32-bit load and store operations are allowed to ac-
c ess MMIO regi ste rs in th e MMIO addr e ss ape r tur e. The
results are undefined for other load s and st ores. Reads
from non-existent MMIO re gisters return un defined val -
ues. Writes to nonexistent MMIO registers time out.
There are no side effects of accesses to nonexistent
MMIO regis ter s. Th e s t a te of t he PC SW B SX bit has no
effect on the result of MMIO accesses.
The Icache tag and LRU bit access aperture give the
DS PCPU re ad -on ly acces s t o t he Icac he stat us . Re f er t o
Secti on 5.4.8, “Reading Tags and Cache Status” for de-
tails.
The EXCVEC MMIO location is explained in Section
3.5.2, “EXC (Exceptions).” Secti on 3.5.3, “INT and NMI
(Maskable and Non-Maskable Interrupts),” describes
th e lo ca t io ns tha t deal w i th t h e se tup and h andli ng of in -
terrupts: ISETTING, IPENDING, ICLEAR, IMASK and
the interru pt ve ctors. Th e t imer MMIO loca tions are de-
scribed in Section 3.8, “Timers.” The instruction and
data breakpoint are described in Section 3.9, “Debug
Support.” The MMIO locations of each device are treat-
ed in the resp ectiv e dev ic e chap t e r s.
3.5 SPECIAL EVENT HANDLING
The PNX1300 microprocessor responds to the special
events sh o wn in Table 3-9, ordered by priority.
With the exception of RESET, which is enabled at all
times, the architecture of the DSPCPU allows special
event handling to begin only during an interrup tib le ju mp
operation (ijmpt , ijmpf or ijm pi) that succeeds (i.e., is a
taken jump). EXC, NMI and INT handling can be initiated
dur i ng handli ng of a n EXC or an INT, bu t only during suc-
ces sf ul in terrup tib le ju m ps .
0x00 0000
Reserved
for
Future Use
Reserved
for
Future Use
0x10 3800 JTAG interface
0x10 3400 I2C interface
0x10 3000 P CI interface
0x10 2C00 SSI interface
0x10 2800 VLD coprocessor
0x10 2400 Image coprocessor
0x10 2000 Audio Out
0x10 1C00 Audio In
0x10 1800 Video Out
0x10 1400 Video In
0x10 1000 Debug support
0x10 0C00 Timers
0x10 0800 Vectored interrupt controller
0x10 0400 MMIO base
0x10 0000 Main memory, cache control
0x1F FFFFF 0x10 1200 data breakpoints
0x10 1000 instruction breakpoints
0x10 0C60 systimer
0x10 0C40 timer3
0x10 0C20 timer2
0x10 0C00 timer1
0x10 08Fc intvec31
0x10 08F8 intvec30
0x10 0888 intvec2
0x10 0884 intvec1
0x10 0880 intvec0
0x10 0828 imask
0x10 0824 iclear
0x10 0820 ipending
0x10 081C isetting3
0x10 0818 isetting2
0x10 0814 isetting1
0x10 0810 isetting0
0x10 0800 excvec
0x10 0400 MMIO_BASE
0x10 0004 DRAM_LIMIT
0x10 0000 DRAM_BASE
0x01 0000 Icache tags & LRU (r/o)
Fig ure 3-5. Memory map of MMIO address space (addresses are offset from MMIO_BASE).
Table 3-9. Special Events and Event Vectors
Event Vector
RESET (Highest pr iori ty) vec tor to DRAM_BASE
EXC (A ll exceptions ) ve ctor to EXCVEC (programmable)
NMI,
INT (Non-maskable interrupt, maskable interrupt) use
the prog rammed vector (one of 32 vectors depend-
ing on the interrupt source)
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-9
The inst r uction schedul er uses inte r rupt i ble j ump s e xcl u-
sively for inter-decision tree jumps. Hence, within a deci-
sion tree, no special-event processing can be initiated. If
a tree-to-tree jump is taken, special-event processing is
allowed. Since the only registers live at this point (i.e.,
that contain useful data) are the global registers allocat-
ed by the A NS I C co mp iler , only a subse t of th e reg is ter s
need s to be preserved by the event ha ndlers. Refer to
the TriM edia SD E Refe ren ce Manu al for de tails on which
registers can be in use. The DSPCPU register state can
be described by the contents of this subset of general
purpose registers and the contents of the PCSW and the
DPC value (the targe t of t he inte r-tre e jump).
The prio rity resolution mechanism built into the DSPCPU
hardware dispatches the highest-priority, non-masked
special-event request at the time of a successful inter-
ruptible jump operation. In view of the simple, real-time-
oriented nature of the mechanisms provided, only limited
nesting of events should be allowed.
3.5.1 RESET
RESET is the highest priority special event. It is asserted
by external hardware or by the host CPU. PNX1300 will
respond to it at any time.
External hardware reset through the TRI_RESET# pin
initiates boot protocol execution as described in Chapter
13, “Sy st em Boo t.” Th is caus es the cu rr ent P C val ue to
be lost and instruction execution to start from address
DRAM_BASE.
A PCI host CPU can perform a PNX1300 DS PCPU- only
reset by an MMIO write to the BIU_CTL.SR and CR bits.
Such a reset does not cause a full boot, instead the
DSPCP U resume s exe cution fro m DRAM_BA SE.
3.5.2 EXC (Exceptions)
Th e DSPC PU en ters E XC sp ecia l-ev ent p roc ess ing un -
der the f o llo w in g co nd it i on s :
1. RESET is de-asserted.
2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
non- em pt y or P C S W.TFE is set.
3. A s uc c essf ul inter ruptible jum p is in the final jum p ex-
ecution stage.
DSPCPU hardware takes the following actions on the ini-
tia tion of E XC pro ces sing:
1. DPC is assigned the intended destination address of
the successful jump.
2. In stru ct ion pr oc e ss in g starts at EX CVEC.
Al l oth er act ion s are th e resp onsibi lit y of the E XC han dler
software. Note that no other special event processing will
ta ke plac e until the ha ndler de c ides t o exe cute an inter -
ruptible jump that succeeds.
3.5.3 INT and NMI (Maskable and Non-
Maskable Interrupts)
The on-chip Vectored Interrupt Controller (VIC) provides
32 I NT r equ est i nput hardw are line s. Th e in terru pt c on-
troller prioritizes and maps att ention requests from sev-
eral different peripherals onto successive INT requests
to th e DSPC PU.
INT special even t proces sing w ill oc cur under the fol low -
ing condition s:
1. RESET is de-asserted.
2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
emp t y an d PC SW. TF E is n ot s et.
3. The i ntersection of IPENDING a n d IM ASK is non-
empty.
4. Th e int er r upt is at level N MI or PCS W.IEN = 1.
5. A s uc c essful in terru ptible jump is in the final jump ex-
ecution stage.
DSPCPU hardware takes the following actions on the ini-
tiation of NMI or INT processing:
1. DPC gets assigned the intended destination address
of th e su cc es s f u l jum p.
2. In str u ctio n pr oc e ss in g starts at th e ap pr o priate in t e r-
rupt v ector.
All other actions are the responsibility of the INT handler
software. Note that no other special event processing will
ta ke plac e until the ha ndler de c ides t o exe cute an inter -
ruptible jump that succeeds.
3.5.3.1 Interrupt vectors
Each of the 32 interrupt so urces can be assigned an ar-
bitrary interrupt vector (the address of the first instruction
of the interrupt handler). A vector is set up by writing the
address to one of the MMIO locations shown in
Figure 3-6. The state of the MMIO vector locations is un-
defined after RESET. (Addresses of the MMIO vector
reg isters are off set with respect t o M MI O_BASE.)
Source 0 vector
INTVEC0 (r/w) Source 1 vector
INTVEC1 (r/w) Source 2 vector
INTVEC2 (r/w)
Source 30 v ector
INTVEC30 (r/w) Source 31 v ector
INTVEC31 (r/w)
•
•
•
•
•
•
0x10 0880
0x10 0884
0x10 0888
0x10 08F8
0x10 08FC
•
•
•
31 0
MMIO_BASE
offset:
Figure 3-6. Interrupt vector locations in MMIO address space.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-10 PRELIMINARY SPECIFICATION
Programmer’s note: See the Philips TriMedia Cookbook
(Book 2 of TriMedia SDE documentation) for information
on writing interrupt handlers.
3.5.3.2 I nterrupt modes
DSPCPU interrupt sources can be programmed to oper-
ate in either level-sensitive or edge-triggered mode. Op-
eration in edge-triggered or level-sensitive mode is de-
termined by a bit in the ISETTING MMIO locations
corresponding to the source, as defined in Figure 3-7.
On RESET, all ISETTING registers are cleared.
In edge -trigger ed mode, the le ading edg e of the sign al
on the device interrupt request line causes the VIC (Vec-
tored Interrupt Controller) to set the int errup t pen din g flag
corresponding to t he device s ource num ber. Note that,
for active high signals, the leading edge is the positive
edge, whereas for active low request signals (such as
PCI INTA#), the negative edge is the leading edge. Th e
interrupt remains pending until one of two events occurs:
•The VIC successfully dispatches the vector corre-
sponding to the source to the PNX1300 CPU, or
•PNX1300 CPU software clears the interrupt-pending
fla g by a di r ect w ri t e to the I C L EA R location.
No interrupt ac knowledge to ICLE AR is need ed for de-
v ices op er a ting in ed ge -tr igg er ed mod e, sin ce the vect or
dispatch clears t he IPENDING request. The device itself
may however need a device-specific interrupt acknowl-
edge to clear the requesting condition. Edge-triggered
mode is not recommended for devices that can signal
multiple simultaneous interrupt conditions. The on-chip
timers must be operate d in edge triggered mode.
In le vel-sens itiv e mo de, the device requ ests an i nterru p t
by asserting the VIC source request line. The device
hold s the req uest until the device interru pt ha ndler per-
fo r ms a device interrupt acknowledge. It is highly recom-
mended that a ll of f-chi p and on-chi p sou rces , wi th the ex-
ception of the timers, operate in level-sensitive mode.
3.5.3.3 Device interrupt acknowl edge
All devices capable of generating level-triggered inter-
rupts have interrupt acknowledge bits in their memory
mapped control registers for this purpose. An interrupt
acknowledge is performed by a store to such contr ol reg-
ister, with a ‘1’ in the bit position(s) corresponding to the
desired acknowledge flags.
Pr ogr amm ers n ot e: the store op er ation that per forms the
int e rru pt ack now le dge sho ul d b e iss ue d at least 2 cycle s
before the ( interruptible) jump that ends an interrupt han-
dler. This ensures that the same interrupt is not dis-
pa tc he d tw ic e du e t o reque st de- a ss e r tio n cloc k dela ys .
3.5.3.4 Interrupt priorities
Each interrupt source can be programmed to request
one out of eight levels of priorities. The highest priority
level (level 7) corresponds to requesting an NMI—an in-
terrupt that cannot be masked by the DSPCPU PC-
SW.IEN bit. The other levels request regular interrupts,
th at ca n be ma sked a s a grou p b y th e PC SW .IEN fl ag.
Level s ix r e prese nts the hi ghes t prio r ity no r m al in t errupt
level and level zero represents the lowest. Refer to
Figure 3-7 fo r deta il s of progra m mi ng the pri or i ty leve l.
Th e VIC arbi tra tes t he high est- pri orit y pe ndin g in terr upt
requ estor. Sources p rogrammed to reques t at the same
level are treated with a fixed priority, from source number
0 (highest) to 31 (lowest). At such time as the DSPC PU
is willing to process special events, the vector of highest
priority NMI source will be dispatched. If no NMI is pend-
ing, and the DSPCPU allows regular interrupts (PC-
SW.IEN is asserted), the vector of the highest priority
regular source is dispatched. Once a vector is dis-
pat c hed, the corr esp onding inter rupt pending f l ag is de-
asserted (edge trig gered mode sources only).
3.5.3.5 Interrupt masking
A single MMIO register (IMASK in Figure 3-8) allows
mas king of an arbitrary su bset of the interrup t sources.
Masking applies to both r egular as well as NMI level re-
questors. Masking is used by software to disable unused
devices and/or to implement nested interrupt handling. In
the latter case, each interrupt handler can stack the old
IMASK content for later restoration and insert a new
mask th at only a llow s th e in ter rup t s it is wi l li ng to handle.
For level-trigge red device handlers, IMASK should also
exclu de the devi ce itself t o preven t re pe ated ha ndler ac -
tivation.
Each interrupt source device typically has its own inter-
rupt enable flag(s) that determine whether certain key
MP31
ISETTING3 (r/w)0x10 081C 31 0
MMIO_BASE
offset:
ISETTING2 (r/w)0x10 0818
ISETTING1 (r/w)0x10 0814
ISETTING0 (r/w)0x10 0810
MP30 MP29 MP28 MP27 MP26 MP25 MP24
371115192327
Each MP Field:
0xxx sou rce ope ra t es in edge-tr iggered mode
1xxx sou rce ope rates in lev el-sensi tive mode
Each MP Field:
x111 NMI (highest) priority
x110 maskable level 6
...
x000 maskable level 0
MP23 MP22 MP21 MP20 MP19 MP18 MP17 MP16
MP15 MP14 MP13 MP12 MP11 MP10 MP9 MP8
MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
Figure 3-7. Interrupt mode and priority MMIO locations and formats.
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-11
device events lead to the request of an interrupt. In addi-
tion, the PCSW.IEN flag determines whether the
DSPCPU is willing to handle regular interrupts. Non
mas ka ble in t err u p ts ig nor e the s ta t e of thi s flag.
Al l thre e mecha nisms ar e necessa ry: the PC SW. IEN fla g
is used to implement critical sections of code during
which the RTOS (real-time operating system) is unable
to ha ndle re gu la r int erru pt s. The IMASK is u sed to al lo w
fu ll c on tr o l ov er int e rr up t hand ler nest ing . The de v ic e in -
terrupt flags set the operational mode of the device.
When RESET is asserted, IPENDING, ICLEAR, and
IMASK are set to all zeroes. (MMIO register addresses
shown in Figure 3-8 are offset addresses with respect to
MMIO_BASE.)
3.5.3.6 Sof tware interrupts and
acknowledgment
The IPENDING register shown in Figure 3-8 can be read
to ob serve the cur rentl y pend ing interr upts. Eac h bit rea d
depends on the mo de of the s o u r ce:
•For a level-sensitive source, a bit value corresponds
to the current state of the device interrupt request
line.
•For an edge-triggered interrupt, a ‘1’ is read if and
only if an interrupt request occurred and the corre-
sponding vec t o r h as not yet been di spatched.
Software can request an interrupt for sources operating
in edge-triggered mode. Writes to the IPENDING register
assert an interrupt request for all sources where a 1 oc-
curred in the bit position of the written value. The state of
sources where a 0 occurred in the written value is un-
changed. Writes have no effect on level-sensitive mode
so ur ces. The int er r up t re qu es t , if not ma ske d, w il l o ccu r
at t he next su ccess ful i nterrupt ible j ump. This diff ers f rom
the conventional software interrupt-like semantics of
many architectures. Any of the 32 sources can be re-
ques te d in s oftw are. I n n orma l ope rati on ho wev er, soft -
ware-requested interrupts should be limited to source
vectors not allocated for hardware devices. Note that an-
othe r PCI master can request interrupts by manipulating
the IPENDING location in the MMIO aperture. This is
useful for inter-processor communication.
Th e ICLE AR re gist er r eads th e s ame as t he IPE ND ING
register. Writes to the ICLEAR register serve to clear
pending flags for edge-triggered mode sources. All IP-
ENDIN G fl ags corr espon ding to b it posi tion s in whi ch ‘1’s
are written are cleared. IPENDING flags corresponding
to bit po siti ons in whi ch ‘0’s ar e w ri t te n a r e no t af fe ct ed.
Writes have no effect on level-sensitive mode sources.
Wh en a pe ndin g inte rru pt b it i s bei ng cl eared thro ugh a
write to the ICLEAR register at the same time that the
hardw are is tr ying to set that i nterru pt bit, t he hard ware
takes precedence.
3.5.3.7 NMI sequentiali zation
In most applications , it is desirable not to nest NMIs. The
NMI interrupt ha ndler can accomplish this by saving the
old IMASK content and clearing IMASK before the first
interruptible jump is executed by the NMI handler.
3.5.3.8 Interrupt source assignm ent
Table 3-10 shows the assignment of devices to interrupt
s ourc e nu mbe rs, as we ll as th e r ecomme nd ed oper a ting
mode (edge or level triggered). Note that there ar e a total
of 5 ext erna l pin s avai labl e to a sse rt i nter rupt reque sts .
The PCI INTA to INTD requests are asserted by active
low signal conventions, i.e. a zero level or a negative
edge asserts a request. The USERIRQ pin operates with
active h igh sign alling convent ions.
3.6 PNX1300 TO HOST INTERRUPTS
In sys tems w here PNX1300 i s operati ng in the presence
of a ho st CPU on P CI, PN X13 00 can generat e interr up ts
to the host, using any combination of the four PCI INTA#
to I N T D# pins. In a typ ical host system, on ly one of the se
pins needs to be wired to the PCI bus interrupt request
lin es. A ny unused p ins o f this gr oup are then avai lable f or
use as sof t ware program mable I / O p ins.
The INT_CTL register (see Figure 3-9) IEx bits, when
set, enable the open collector driver of the four
INTD#..INTA# pins. The INTx bits determine the output
value generated (if enabled). A ‘1’ in INTx causes the
corresponding PCI in terrupt pin to be asse rted (low IN-
Tx# p in ). T he ISx bits are read -on ly an d re fl ect th e cu r-
IMASK (r/w)0x10 0828 31 0
MMIO_BASE
offset: 723 15
ICLEAR (r/w)0x10 0824
IPENDING (r/w)0x10 0820
Each IMASK(i) bit:
On read or write, 0 ⇒ disallow source i interrupt request
On read or write, 1 ⇒ allow source i interrupt request
Each ICLEAR(i) bit:
On read, same as IPENDING(i)
On write, 1 ⇒ clear source i interrupt request
Each IPENDING(i) bit:
On read, 1 ⇒ source i interrupt req uest is pending
On write, 1 ⇒ software source i interrupt request
Figure 3-8. Interrupt controller request, clear, and mask MMIO registers.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-12 PRELIMINARY SPECIFICATION
re nt act ual st at e o f the pins . No te th at the pi ns h av e ne g-
ative logic (active low) polarity and are of the open
collector output type. Hence the pin voltage is low (ac-
tive ) whe n the log ical v alu e set or se en in the INT_ CTL
register is a ‘1’.
The assertion and de-assertion of host interrupts is the
res p on sibi lity of PN X1 300 so f twar e.
See also Section 11.6.17, “INT_CTL Re gister.”
3. 7 HOST TO P NX130 0 IN TER RUP TS
A host CPU can generate an interrupt to PNX1300 in
several ways:
•by a PCI MMIO write to IPENDING to assert the
HOSTCOMM interrupt (bit 28)
•by a ha r dwar e cir c u it that asser t s one o f the i n t err u pt
request pins TRI_USERIRQ, or INTA..INTD .
Th e firs t an d mo s t com m on m e t ho d requir e s no circ ui t ry
and leaves the interrupt pins available fo r othe r purp oses.
3.8 TIMERS
The DSPCPU contains four programmable timer/
counters, all with the same function. The first three
(TIMER1, TIMER2, TIMER3) are intended for general
use. The fourth timer/counter (SYSTIMER) is reserved
for use by the system software and should not be used
by applications.
Each timer has three registers as shown in Figure 3-10.
The MMIO r egis te r ad dr esse s sh own are o ffs et addre ss-
es with res p ec t t o the ti me r’s b as e address.
Each timer/counter can be set to count one of the event
types specified in Table 3-12. Note that the
DATABREAK event is special, in that the timer/counter
may increment by zer o, one or two in each clock cycle.
For all other event types, increments are by zero or one.
The CACHE1 and CACHE2 events serve as cache per-
fo rmanc e m onitor i ng supp or t. Th e ac t u al ev ent se le c t ed
for CACHE1 and CACHE2 is determined by the
MEM_EV ENTS MMIO register, see Section 5.7, “Perfor-
manc e E val ua tio n S upp ort .” If a PNX1300 pin signal (VI-
CLK, etc.) is selected as an event, positive-going edges
on t h e si gnal are counted.
Each timer increments its value until the modulus is
reached. On the clock cycle where the incremented val-
ue would equal or exceed the modulus, the value wraps
around to zero or one (in the case of an increment by
two), and an interrupt is generated as defined in
Table 3-10. The timer interrupt source mode should be
set as edge-sensitive. No software interrupt acknowl-
edge to the timer device is necessary.
Counting starts and continues as long as the run bit is
set.
Load in g a n ew modu lus does not aff ect t he con tents of
th e va lu e r eg is t e r . If a s tor e o p e r a t ion t o e ither the m od -
ulus or value register results in value and modulus being
th e s ame , no in te rrup t will b e gene rat ed. If the ru n b it i s
s et, the next value will be modulus+1 or modulus+ 2, and
Table 3-10. Interrupt source assignments
SOURCE
NAME SRC
NUM MODE SOURCE DESCRIPTION
PCI INTA 0 level PCI_INTA# pin signal
PCI INTB 1 level PCI_INTB# pin signal
PCI INTC 2 level PCI_INTC# pin signal
PCI INTD 3 level PCI_INTD# pin signal
TRI_US ERIR Q 4 either exter nal general-pur pose
pin
TIMER1 5 edge general-purpose timer
TIMER2 6 edge general-purpose timer
TIMER3 7 edge general-purpose timer
SYSTIMER 8 edge reserved for debugger
VIDEOIN 9 level video in block
VIDEOOUT 10 lev el video out block
AUDIO IN 11 level audio in block
AUDIO OUT 12 level audio out block
ICP 13 level image coproces sor
VLD 14 level VLD coprocessor
SSI 15 level SSI interface
PCI 16 level PCI BIU (DMA, etc.; see
Table 11-14 for possible
inter rupt cau ses)
IIC 17 level I2C interface
JTAG 18 le vel JTAG in t erfa ce
t.b.d. 19..24 reserved for future dev ices
SPDO 25 level SPDO bl ock
t.b.d. 26..27 reserved for future devices
HOSTCOM 28 edge (software) host communica-
tion
AP P 29 e dge (soft war e) app lic at ion
DEBUGGER 30 edge (software) debugger
RT O S 31 edge (software) RT OS
Figure 3-9. Host interrupt control register
31 0
MMIO_BASE
offset:
0x10 3038 371115192327
INT_CTL (r/w)
IS[D:A] IE[D:A] INT[D:A]
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-13
the cou nter w ill have to loop around before a n interrupt is
generated.
A modulus value of zero causes a wrap-around as if the
modulus value wa s 232.
On RESE T, the TC TL re gister s ar e cl ear e d, and the val-
ue of the TMODULUS and TVALUE registers is unde-
fined.
3.9 DEBUG SUPPORT
Thi s s ect ion descr i bes t he speci al de bug su pp ort off ere d
by the DS PCPU. Instructi on an d data br eakp oints can be
define d thro ugh a s et of registers in the MMI O register
space. When a breakpoint is matched, an event is gen-
erated that can be used as a t imer source (see Section
3.8, “Timers”). The timer TMODULUS has to be set to
gene ra te a D SP CPU i nt erru pt after the d esir ed num ber
of bre akp oint matc he s .
3.9.1 Instruction Breakpoints
The instruction-breakpoint control register is shown in
Figure 3-11. On RESET, the BICTL register is cleared.
(MMIO-register add r esses sh own are offset with respect
to M MI O_BASE.)
The instruction-breakpoint address-range registers are
shown in Figure 3-12. After RESET, the value of these
re gi ster s is unde fin ed . (MMI O- reg is ter addre sse s sho wn
are off set with respect t o MM I O_BASE.)
When the IC bit in the breakpoint control register is set to
‘1’, instruction breakpoints are activated. Any instruction
address issued by the PNX1300 chip is compared
against the low and high address-range values. The IAC
bit in the breakpoint cont rol register determines whether
the instruction address needs to be inside or out side of
the range defined by the low and high address-range
registers. A successful comparison takes place when ei-
ther:
• IAC = ‘0’ and low ≤ iaddr ≤ high, or
• IAC = ‘1’ and iaddr < low or iaddr > high.
On a successful comparison, an instruction breakpoint
eve nt i s gen erat ed, whi ch c an be used as a cl ock in pu t
to a ti mer. After counti ng the pr ogr a mmed number of in-
s tru ctio n b r ea kpoi nt even ts , th e t im er w ill gene r ate a n i n-
terrupt request.
Table 3-11. Timer base MMIO address
TIMER1 MMIO_BASE+0x10,0C00
TIMER2 MMIO_BASE+0x10,0C20
TIMER3 MMIO_BASE+0x10,0C40
SYSTIMER MMIO_BASE+0x10,0C60
Table 3-12. Timer source selections
Source Name Source
Bits
Value Source Description
CLOCK 0 CPU clock
PRESCALE 1 prescaled CPU clock
TRI_TIMER_CLK 2 e xternal clock pin
DATAB REA K 3 data bre akpoint s
INSTBREAK 4 instruction breakpoints
CACHE1 5 cache event 1
CACHE2 6 cache event 2
VI_CLK 7 video in clock pin
VO_CLK 8 video out clock pin
AI_WS 9 audio in word strobe pin
AO_W S 10 audio out word strobe pin
SSI_RXFSX 11 SSI receive frame sync pin
SSI_IO2 12 SSI transmit frame sync pin
—13-15 undefined
MODULUS
TMODULUS (r/w)031 0
Timer base offset:
TVALUE ( r/w)4
TCTL (r/w)8
371115192327
“PRESCALE”:
Prescale value is
2^PRESCALE, i.e.,
in the range [1..32768] “SOURCE” select:
see table Table 3-12
VALUE
PRESCALE SOURCE “RUN” bit:
0 Timer stopped
1 Timer running
R
Figure 3-10 . Timer register definitio ns.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-14 PRELIMINARY SPECIFICATION
3.9.2 Data Breakpoint s
The data-breakpoin t a ddress-range and comp are-value
re gist ers are s hown in Figure 3-13. After RESET, the val-
ue of the data breakpoint registers is undefined. (MMIO-
register addresses shown are offset with respect to
MMIO_BASE.)
The data-breakpoint control register is shown in
Figure 3-14. On RESET, the BDCTL register is cleared.
(The register address shown is offset with respect to
MMIO_BASE.)
When the DC bits in the data breakpoint control register
are not set to ‘0’, data breakpoints are activated. When
the valu e of th e DC bi ts is ‘1’ or ‘3’, any data address from
load op erati on s (if the B L b it is set) an d/or sto re op era -
tions (if the BS bit is set) is su ed by th e DSP C PU is co m -
pared against the low and high address-range values.
The DAC bit in the breakpoi nt control re gister det ermine s
whether data addresses need to be inside or outside of
the range defined by the low and high address-range
registers. A successful comparison occu rs when either:
•DAC = ‘0’ and low ≤ daddr ≤ high, or
•DAC = ‘1’ and daddr < low or daddr > high.
31 0
MMIO_BASE
offset: BICTL (r/w)0x10 1000 371115192327
‘IAC’ Instruction address co ntrol:
0 Breakpoint if address inside range
1 Breakpoint if address outside range ‘IC’ Ins tr uct ion c ontrol bi t:
0 Disable instruction breakpoints
1 Enable instruction breakpoints
IC
Fig ur e 3-1 1 . I n st ruct io n- b r ea kpoi nt co ntr ol r eg ist er.
Address Range Start
BINSTLOW (r/w)0x10 1004 31 0
MMIO_BASE
offset:
BINSTHIGH (r/w)0x10 1008
371115192327
Address Range End
Fig ur e 3-1 2 . I n st ruct io n- b r ea kpoi nt ad dress - rang e regist e r s.
BDATAALOW (r/w)0x10 1030 31 0
MMIO_BASE
offset:
BDATAAHIGH (r/w)0x10 1034
BDATAVAL (r/w)0x10 1038
BDATAMASK (r/w)0x10 103C
Addr ess R ange Start 371115192327
Addr ess R ange End
Data Breakpoint Value
Data Breakpoint Value Mask
Fig ur e 3-1 3 . D a t a-br ea kp o in t addr e ss - rang e an d valu e- compar e reg i ster s.
31 0
MMIO_BASE
offset: BDCTL (r/w)0x10 1020 371115192327
‘DVC’ Data Val ue Con trol:
0 Breakpoint if data equal
1 Breakpoint if data not equal
DCBS BL
‘BS’ Break on Store:
0 Don’t check data stores
1 Do check data stores
‘DAC’ Data Addr es s Control:
0 Breakpoint if address inside range
1 Breakpoint if address outside range
‘BL’ Break on Load:
0 Don’t check data loads
1 Do check data loads
‘DC’ Data Control:
0 No che cking
1 Check data addresses
2 Check data values
3 Check data value and add r esses
Figure 3-14 . Da ta-breakpoin t control register.
Philips Semiconductors DSPCPU Architec ture
PRELIMINARY SPECIFICATION 3-15
Note that this comparison works for all addresses re-
gardless of the aperture to which they belong. When the
value of the DC bits is ‘2’ or ‘3’, any data value from load
operations (if the BL bit is set) a nd/or s tore operatio ns (if
the BS b it is set) issued by the PNX1300 CPU is co m-
pared against the value in the BDATAVAL register. Only
the bits for which the corresponding BDATAMASK regis-
ter bits are set to ‘1’ will be used in the comparison. The
DVC bit in the breakpoint control register determines
whether the data value needs to be equal or not equal to
the comparison value. A successful comparison occurs
when either of t he following are true:
•DVC = ‘0’ and (data & BDATAMASK) = (BDATAVAL
& BDATAMASK).
•DV C = ‘1’ and (data & BDATAMASK) != (BDATAVAL
& BDATAMASK).
Note: use a no nzer o datamask or the result is undefined.
When a successful comparison h as t aken p lace, a da ta
breakp oint event is gen erated, whi ch can be used as a
clock input to a timer. A fter counting the set n umber of
data breakpoint events, the timer will generate an inter -
rupt request.
When the v alue of the DC bits is ‘3’, a data breakpoint
event is generated if and only if a successful comparison
occurs on both address and data simultaneously.
No te that up t o tw o d ata b r eakp oi nt even ts can occur per
cloc k cycle, due to the dual load/sto re capability o f the
CPU a nd data cache.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
3-16 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 4-1
Custom Operations for Multimedia Chapter 4
by Ge rt Slavenburg, P ie ter v.d. Meul en, Y ong Cho, Sang-Ju Park
4.1 CUSTOM OPERATIONS OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
Custom operations in the PNX1300 DSPCPU architec-
ture are specialized, high-function operations designed
to dram atic ally imp rov e pe rfo rmanc e in imp ort ant m ult i-
med ia appl icati ons . Wh en prope r ly in c orpo rate d into ap-
plic at ion so urce c ode, cu stom op erati ons en ab le an a p-
plication to take advantage of the highly parallel
PNX1300 microprocessor implementation. Achieving a
similar performance increase through other means—
e.g., executi ng a highe r number of traditional micropro-
cessor instructions per cycle—would be prohibitively ex-
pensive for PNX1300’s lo w - cos t t ar get applic ations .
Custom operations are simple to understand and consis-
ten t in thei r d efi ni tio n, but thei r unus ua l fu nc t ions ma ke it
difficult for automatic code generation algorithms to use
them effectively. Consequently, custom operations are
inserted into source code by the programmer. To make
this pr ocess as pai nless as possible, custo m oper ation
syntax is consistent with the C programming language,
and, just as with all other operations generated by the
co m piler , t he s cheduler ta kes c a re of r egi s ter allocation,
oper ation pac king, and flow an al ysis .
4.1.1 Custom Operation Motivation
For both general-purpose and embedded microproces-
sor - b as ed appl ication s, pro gram ming in a high -l evel lan -
guage is desirable. To effectively support optimizing
compilers and a simple programming model, certain mi-
cr opro ces sor ar ch itec ture feat ures are need ed, su ch as
a large, linear address space, general-purpose registers,
and register-to-register operations that directly support
the manipulation of linear address pointers. A common
choice in microprocessor architectures is 32-bit linear
addresses, 32-bit registers, and 32-bit integer opera-
tions. PNX1300 is such a microprocessor archit ecture.
Fo r the data mani pulation in m any algorit h ms, ho w ever,
32- bi t data and op er a tion s ar e wa stef u l of exp en sive s il -
icon resources. Important mult imed ia applications, such
as the decompression of MPEG video streams, spend
s ignific ant amo unts of e x ecuti on time dealing with eight-
bit data items. Using 32-bit operations to manipulate
small dat a it ems ma kes ineff icient us e of 32-b it execu tio n
har dwar e in th e impl emen tatio n. If t hese 32-bi t reso urces
could be used instead to operate on four eight-bit data
items simultaneously, performance would be improved
by a si gn ific ant fac to r with only a tin y inc rease in imp le -
mentation cost.
Getting the highest execution rate from standard micro-
processor resources is one of the motivations behind
custom operations in PNX1300. A range of custom oper-
ations is p rovided that each processes—simultaneous-
ly—four 8-bit or two 16-bit data items. There is little cost
difference between a standard 32-bit ALU and one t hat
can process either one pair of 32-bit operands or four
pairs of eight-bit operands, but there is a big perfor-
mance difference for PNX1300’s target applications.
PNX1300’s custom operat ions go beyond simply makin g
the best use of standard resources. Some custom oper-
ati on s co mbin e se ve ral sim pl e op era tio ns. The se co mb i-
nat io ns are ta i lo red sp ec if i call y to the needs of imp ort an t
multimedia applications. Some high-function custom op-
erations eliminate conditional branches, which helps the
scheduler make effective use of all five operation slots i n
eac h PN X13 00 i n stru cti on. F il ling up al l fiv e sl ots is es-
peciall y imp ortant in the inner loops of comp utational in-
tens iv e multim ed ia ap pl ic ations .
In short, custom operations help PNX1300 reach its
goals of extremely high multimedia performance at the
low est pos sible cost .
4.1.2 Introduction to Custom Operations
Table 4-1 an d Table 4-2 co ntain tw o lis tings of the cus -
tom operations available in the PNX1300 architecture.
Table 4-1 groups the custom operations by type of func-
ti on w hile Table 4-2 list s th e op era tion s by op eran d si ze.
For more detailed information abo ut the custo m opera-
tions, Appe ndix A , “PNX1300/01/02/11 DSPCPU Opera-
tions.”
Some operations exist in several versions that differ in
the treat ment of the ir op erands and results, and the mne-
monics for these versions make it easy to select the ap-
propriate operation. For example, the sum of products
operations all have “fir” in their mnemonics; the prefix
and suffix of the mnemonic expresses the treatment of
the operands and result. The ifir8ii operation treats both
of its operands as signed (ifir8ii) and produces a signed
result (ifir 8i i). T h e ifi r 8i u op er a ti on tr e at s its fir s t operand
as signed (ifir8iu), the second as unsigned (ifir8i u), a nd
produces a signed result (ifir8iu). The ume8ii operation
implements an eight-bit motion-estimation; it treats both
operands as signed but produces an unsigned result.
The operations beginning with “dsp” implement a clip-
ping (sometimes called saturating) function before stor-
PNX1300/01/ 02/11 Data Book Philips Semiconductors
4-2 PRELIMINARY SPECIFICATION
ing the result(s) in the destination register. Otherwise,
th eir naming f o llow s t h e rules gi ven abov e w here ap pr o-
pr iate . For e xampl e, th e dspu quadaddu i operat ion im ple-
ments four 8-bit additions; it treats the first operand of
each addition as unsigned, the second operand as
signed, and produces an unsigned result for each addi-
tio n. Eac h r e su lt, which is co m pute d wi t h no l o ss of p re-
cision , is clipped into the representable range of a byte
(0..255).
T able 4-1. Key Multimedia Custom Operations Listed
by Func t ion Ty pe
Function Custom Op Description
DSP
absolute
value
dspiab s Clipped si gned 32-bit absolute
value
dspidualabs Dual clipped absolute values of
signed 16-bit halfwords
Shift dualasr dual-16 arithmetic shift right
Clip dualiclipi dual-16 clip signed to signed
dualuclipi dual-16 clip signed to unsigned
Min,max quadumax Unsigned bytewise quad max
quadumin Unsigned bytewise quad min
DSP add dspiad d Clipped signed 32- bit add
dspuadd Clipped unsigned 32-bit add
dspidu alad d D ual clipped add of signed 16-
bit halfwords
dspuquadaddui Quad clipped add of unsigned/
signed bytes
DSP
multiply ds pimul Clipped si gned 32-bit multi ply
dspumul Clipped uns ign ed 32-bit multi -
ply
dspidu almul D ual clipped multip ly of signe d
16-bit halfwords
DSP
subtract dspisub Clipped signed 32- bit subt ract
dspusu b C lipped uns ign ed 32-bit sub -
tract
dspidualsub Dual clipped subtract of signed
16-bit halfwords
Sum of
products ifir16 Si gned sum of produ cts of
signed 16-bit halfwords
ifir8ii Signed sum of produ cts of
signed bytes
ifir8iu Signed sum of products of
signed/unsigned bytes
ufir16 Unsigned sum of products of
unsigned 16-bit halfwords
ufir8uu Unsigned sum of products of
unsigned bytes
Merge,
pack mer gedu al16ls b Merge dual-16 lea st-s ignific ant
bytes
mergel sb Merge least-signi ficant bytes
mergem sb Merge mos t-signifi cant bytes
pack16lsb Pack least-s igni fic ant 16-bit
halfwords
pack16msb Pack most- significant 16 -bit
halfwords
packbytes Pack least-s igni ficant bytes
Byte
averages quadavg Unsigned byte-wise quad aver-
age
Byte
multiplies quadumulmsb Unsigned quad 8-bit multiply
most significant
Motion
estima-
tion
ume8ii Unsigned sum of absolute val-
ues of signed 8-bit differences
ume8uu Unsigned sum of absolute val-
ues of unsigned 8-bit differ-
ences
Tab le 4 -2. K ey Multi med ia Cus tom Ope rations Liste d
by Operand Size
Op. Size Custom Op Description
32-bit dspiabs Clipped signed 32-bit abs value
dspiadd Clipped signed 32-bit add
dspuadd Clipped unsigned 32-bit add
dspimul Clipped signed 32-bit multiply
dspumul Clipped un signed 32-bit multi -
ply
dspisub Clipped signed 32-bit subtract
dspusub Clipped uns igned 32-bit sub-
tract
16-bit mergedual16lsb Merge dual-16 least-significant
bytes
dualasr dual-16 arithmetic shift right
dualiclipi dual-16 clip signed to signed
dualuclipi dual-16 clip signed to unsigned
dspidualmul Dual clipped multiply of signed
16-bit halfwords
dspidualabs Dual clipped absolute values of
signed 16-bit halfwords
dspidualadd Dual clipped add of signed 16-
bit halfwords
dspidualsub Dual clipped subtract of signed
16-bit halfwords
ifir16 Signed sum of products of
signed 16-bit halfwords
ufir16 Unsigned sum of products of
unsigned 16-bit halfwords
pack16lsb Pack le ast-s ignifican t 16-bit
halfwords
pack16msb Pack most-si gni fic ant 16-b it
halfwords
Philips Semiconductors Custom Operations for Multimedia
PRELIMINARY SPECIFICATION 4-3
4.1.3 Exam ple Uses of Custom Ops
The next three sectio ns illu str ate th e adva ntages of us ing
c ustom operations. Also, the more complex examples il-
lustrate how custom operations can be integrated into
application code by providing listings of C-language pro-
gram fragments. The examples progress in complexity
from simple to intricate; the most interesting examples
are tak en fr o m ac tual mu lt i m ed ia c odes , suc h as MP EG
decompression.
4.2 EXAMPLE 1: BYTE-MATRIX
TRANSPOSITION
The goal of this example is to provide a simple, introduc-
tory illustration of how custom operations can significant-
ly increase processing s peed in small kernels of applica-
tions. As in most uses of custom operations, the power
of custom operations in this case comes from their ability
to oper a te on mult iple data item s in p a ra llel.
Imagine that our task is to transpose a packed, 4-by-4
matrix of bytes i n memory; the matrix might, for example,
cont ai n 8-bit pix el va lues . Figure 4-1 illustrates both the
organ iza tion of the m atrix in m emo ry and the ta sk to be
performed in standard mathematical notation.
Performing this operation with traditional microprocessor
instructions is straight forward but time consuming. One
way to perform the manipulation is to perform 12 load-
byte instructions (since only 12 of t he 16 bytes need to
be r epos itione d) a nd 12 stor e-by te in struct ion s that pl ace
the byte s ba ck in memo ry i n t heir ne w po si tion s. Ano th er
way would be to perform four load-word inst ru cti ons, re-
position the bytes in registers, and then perform four
store-word instructions. Unfortunately, repositioning the
bytes in registers would require a large number of in-
structions to properly shift and mask the bytes. Perform-
ing the 24 loads and stores makes implicit use of the
shift ing an d maski ng ha rdwa re in t he load /sto re uni ts an d
thus yields a shorter instruction sequence.
The problem with performing 24 loads and stores is that
loads and stores are inherently slow operations because
they must access at least the cache and possibly slower
layers in the memory hierarchy. Further, performing byte
loads and stores when 32-bit word-wide accesses run
just as fast wastes the power of the cache/memory inter-
fa ce . We w ou l d p refer a fas t algori t hm tha t takes full ad-
vantage of c ac he / m em o ry ba ndw id th whil e no t requ ir i ng
an ino r di na te nu mb e r of by te- m an ip ul at i on i ns tr u ction s .
PNX1300 has instructions that merge and pack bytes
and 16-bit halfwords directly and in parallel. Four of
these instructions can be applied in this case to speed up
the manipulation of bytes that are packed into words.
Figure 4-2 shows the application of these instructions to
the byte-matrix t ranspos ition problem, and the left side of
Figure 4-3 shows a list of the operations needed to im-
plement the matrix transpose. When assembled into ac-
tual PNX1300 instructions, these custom operations
wo ul d be pa cke d as ti ght ly as de pe nden ci es al lo w, up to
fiv e operat i ons per i ns t ruction.
Note that a programmer would not need to program at
this level (PNX1300 assembler). The matrix transpose
would be expressed just as efficiently in C-language
source code, as shown on the right side of Figure 4-3.
The low-level code is shown here for illustration purpos-
es only.
The first sequence of four load-word operations in
Figure 4-3 brings the packed words of the input matrix
into registers R10, R11, R12, and R13. The next se-
quenc e o f four m erge operations produces intermediate
results into registers R14, R15, R16, and R17. The next
s equence of four pack operatio ns could then replace the
original operands or place the transposed matrix in sep-
ar at e re gi ster s if the or iginal m a trix o pe rand s were n eed-
8-bit quadumax Unsigned bytewise quad max
quadumin Unsigned bytewise quad min
dspuquadaddui Quad clipped add of unsigned/
signed bytes
ifir8ii Signed sum of products of
signed bytes
ifir8iu Signed sum of products of
signed/unsigned bytes
ufir8uu Unsigned sum of products of
unsigned bytes
mergel sb Me rge lea st-si gnific ant bytes
mergems b Merge mos t- signifi cant bytes
packbytes Pack le ast-s ignificant bytes
quadavg Unsigned byte-wise quad aver-
age
quadumulmsb Unsigned quad 8-bit multiply
most significant
ume8ii Unsigned sum of absolute val-
ues of signed 8-bit differences
ume8uu Unsigned sum of absolute val-
ues of unsigned 8-bit differ-
ences
T able 4-2. Key Multimedia Custom Operations Listed
by Operand Size
Op. Size Custom Op Description 31 0
a
e
i
m
b
f
j
n
c
g
k
o
d
h
l
p
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Row Major Column Major
Transpose
a b c d
e f g h
i j k l
m n o p
31 0
a e i m
b f j n
c g k o
d h l p
Transpose
n+0:
n+4:
n+8:
n+12:
Memory
Location
Figure 4-1. Byte-matrix transposition. Top shows
byte matrices pa cked into memory word s; bottom
sh ow s ma th e ma ti c al ma t ri x repr es ent at io n .
PNX1300/01/ 02/11 Data Book Philips Semiconductors
4-4 PRELIMINARY SPECIFICATION
ed for further computations (the PNX1300 opt imizing C
compil er perf orms thi s analysi s aut omati call y). In this ex-
amp le, the tra nspose matrix is placed in registers R1 8,
R19, R20, and R21. The final four store-word operations
put the transposed matrix back into memory.
Thus, us ing the PNX130 0 cus tom operations, the byte-
matrix transposition requires four load-word operations
and four store-word operations (the minimum possible)
and eight register-to-register data-manipulation opera-
tions. The result is 16 operations, or byte-matrix transpo-
sition at the rate of one operation per byte.
While the adva ntage of the custo m-operation-based al-
gor i thm ove r the brute- fo rce code that uses 24 load- and
store-byte instruct ion seems to be only eight operations
(a 33% reduction), the advantage is actually much great-
er . Fir st , usin g cus to m ope rat i ons, the numb er of me mo-
ry references is reduced from 24 to eight (a factor of
three). Since memory references are slower than r egis-
ter -to- regi ster o pera tions (su ch as the cu stom ope ratio ns
in this example), the reduction in memory references is
significant.
Further, the ability of the PNX1300 VLIW compilation
system to exploit the performance potential of the
PNX 130 0 mic rop roce sso r h ardw are is en hanc ed by t he
custom-operation-based code. This is because it is eas-
ier for the compilation system to produce an optimal
schedule (arrangement) of the code when the number of
memo r y ref ere nce s is in balance w ith the number of reg-
ister-to-register operations. The PNX1300 CPU (like all
high-performance microprocessors) has a limit on the
num be r of me mory re fer ence s that can be processed i n
a singl e cy c le ( t wo is the c ur re nt lim it) . A long s e qu ence
of cod e that cont ains on ly memory references can result
in empty operation slots in the long PNX1300 instruc-
tions. Empty operation slots waste the performance po-
te nti al of the PN X1 300 hardw are.
As this ex ample ha s sho w n, car eful use of custom oper-
ations has the potential t o not only reduce t he absolute
number of operations needed to perform a computation
but can also help th e com pila tion sy stem pr oduc e co de
that fully exploits the performance potential of the
PNX1300 CPU.
4.3 EXAMPLE 2: MPEG IMAGE
RECONSTRUCTION
The com plete MPEG vi deo deco ding algo rithm is com-
posed of many different phases, each with computational
int ensi ve kern els. One imp ortan t kerne l deal s with re con-
structing a single image frame given that the forward-
and backward-predicted frames and the inverse discrete
cosine transform (IDCT) results have already been com-
puted. This kernel provides an excellent opportunity to il-
lustrate of the power of PNX1300’s specia lized custom
operators.
In the code f ragm ents that follo w, th e b ackwa r d-p re dic t-
ed block is assumed to have been computed into an ar-
ray back[], the forward-predicted block is assumed to
have been computed into forward[], and the IDCT results
are assumed to have been computed into idct[].
a
e
i
m
b
f
j
n
c
g
k
o
d
h
l
p
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Row Major Column Major
mergemsb
mergemsb
a e b f
i m j n
mergelsb
mergelsb
c g d h
k o l p
pack16msb
pack16lsb
pack16msb
pack16lsb
Fig ure 4-2. Application of merge and pack instructions to the byte-matrix trans position of Figure 4-1.
ld32d(0) r100 → r10
ld32d(4) r100 → r11
ld32d(8) r100 → r12
ld32d(12) r100 → r13
mergemsb r10 r11 → r14
mergemsb r12 r13 → r15
mergelsb r10 r11 → r16
mergelsb r12 r13 → r17
pack16msb r14 r15 → r18
pack16lsb r14 r15 → r19
pack16msb r16 r17 → r20
pack16lsb r16 r17 → r21
st32d(0) r101 r18
st32d(4) r101 r19
st32d(8) r101 r20
st32d(12) r101 r21
char matrix[4][4];
.
.
.
int *m = (int *) matrix;
temp0 = MERGEMSB(m[0], m[1]);
temp1 = MERGEMSB(m[2], m[3]);
temp2 = MERGELSB(m[0], m[1]);
temp3 = MERGELSB(m[2], m[3]);
m[0] = PACK16MSB(temp0, temp1);
m[1] = PACK16LSB(temp0, temp1);
m[2] = PACK16MSB(temp2, temp3);
m[3] = PACK16LSB(temp2, temp3);
.
.
.
Figure 4-3. On the left is a complete list of operations to perform the byte-matrix transposition of Figure 4-1
and Figure 4-2. On the left is an equivalent C-language fragment.
Philips Semiconductors Custom Operations for Multimedia
PRELIMINARY SPECIFICATION 4-5
A straightforward coding of the reconstruction algori thm
migh t lo ok as shown in Figure 4-4. This implementation
s hare s ma ny o f the undesi r able properties of the first ex-
ample of byte-matrix transposition. The code accesses
memory a byte at a time instead of a word at a time,
which wastes 75% of the available bandwidth. Also, in
light of the many quad-byte-parallel operations intro-
duced in Se ction 4.1.2, “Introduction to Custom Opera-
tions,” it seems inefficient to spend three separate addi-
tions and one shift to process a single eight-bit pixel.
Perhaps even more unfortunate for a VLIW processor
lik e P NX1 300 is th e br anc h- i nten si ve co de that perfo r ms
th e sa turat ion test in g; el imin ating th ese bran ches cou ld
rea p a si gn if i ca nt pe r fo r m an ce gain.
Since MPEG decoding is the kind of task for which
PNX1300 was created, there are two custom opera-
tions—quadavg and dsp uquadad dui—that exactly fit this
impor ta nt M PE G k ernel (and othe r ker n els). Thes e c us-
tom operations process four pairs of 8-bit pixel values in
parallel. In addi tion, ds puquadaddui perf o r ms saturat io n
tests in hardware, which eliminates any need to execute
explic it tests an d br an c he s.
For readers familiar with the details of MPEG algorithms,
the use of eight-bit IDCT values later in this example may
be confusin g. The s t a ndard MPE G im plem entation cal ls
for nine-bit IDCT values, but extensive analysis has
shown that values outside the range [–128..127] oc cur
so rarely that they can be considered unimportant. Pur-
suant to this observation, the IDCT values are clipped
into th e eigh t-bit ran ge [ –128..127] with saturating arith-
metic before the frame reconstruction code runs. The as-
sumption that this saturation occurs permits some of
PNX1300’s custom ope rat ions to ha ve clea n, sim ple def-
initions.
The first step in seeing how custom operations can be of
v alue in this case, is to unroll the loop by a fa ctor o f four.
The unrolled c ode is shown in Figure 4-5. This creates
c ode that is par all e l wit h r espec t t o th e fo ur pix el comp u-
tat i on s. As i t is easi l y se en in th e c od e, the four g rou ps of
computations (one group per pixel) do not depend on
each other.
Af ter so me ex pe rien ce is g aine d wi t h c usto m op era t io ns,
it is not nece ssary to unroll loop s to discover s ituations
whe r e cu stom oper ations are use f ul . Often , a good pro-
grammer with knowledge of the function of the custom
ope r atio ns can see by si mple in spect io n op port u ni ties to
ex ploit custom oper atio ns.
To u nd ers ta nd how q uada vg and dspuquadaddui can be
used in this code, we exam ine t he f u nction of these cus -
to m op erations .
The quad av g c ust om oper a tio n p er for ms pixe l a ve rag in g
on four pairs of pixels in parallel. Formally, the operatio n
of qu ad av g is a s follo w s:
quadavg rscr1 rsrc2 -> rdest
tak es ar gu ments in re gi ster s rsr c 1 an d rsr c2 , and it com-
put es a resul t in to reg ist er rd est. r src1 = [ab cd], rsrc 2 =
[wxyz], a nd rdest = [pqrs] where a, b, c, d, w, x, y, z, p, q,
r, and s are all unsigned eight-bit values. Then, quadavg
c omputes the output vector [pqrs] as follows:
p = (a + w + 1) >> 1
q = (b + x + 1) >> 1
r = (c + y + 1) >> 1
s = (d + z + 1) >> 1
The pixel averaging in Figure 4-5 is evident in the first
st atem ent of eac h of the fo u r g r oups of st a tements. The
rest of the code—addi ng idct[i] value an d perform ing the
saturation test—can be performed by the dspuquadad-
dui oper a tio n. F o rm ally , its fu nc t io n is a s fol lo w s:
dspuquadaddui rsrc1 rsrc2 -> rdest
tak es ar gu ments in re gi ster s rsr c 1 an d rsr c2 , and it com-
putes a result into register rdest. rsrc1 = [efgh], rsrc2 =
[stuv], and rdest = [ijkl] where e, f , g, h, i, j, k, and l are
unsigned 8-bit values; s, t, u, and v are signed 8-bit val-
ues. Then, dspuquadaddui computes the output vector
[ijkl] as follows:
i = uclipi(e + s, 255)
j = uclipi(f + t, 255)
k = uclipi(g + u, 255)
l = uclipi(h + v, 255)
The uclipi operation is defined in this case as it is for the
separate PNX1300 operation of the same name de-
scribed in Appendix A, “PNX1300/01/02/11 DSPCPU
Operations,”. Its definition is as follows:
void reconstruct (unsigned char *back,
unsigned char *forward,
char *idct,
unsigned char *destination)
{
int i, temp;
for (i = 0; i < 64; i += 1)
{
temp = ((back[i] + forward[i] + 1) >> 1) + idct[i];
if (temp > 255)
temp = 255;
else if (temp < 0)
temp = 0;
destination[i] = temp;
}
}
Figure 4-4. Straightforward code for MPEG frame reconstruction.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
4-6 PRELIMINARY SPECIFICATION
uclipi (m, n)
{
if (m < 0) return 0;
else if (m > n) return n;
else return m;
}
To make is easier to see how these operations can sub-
sume all the code in Figure 4-5, Figure 4-6 shows the
same code rearranged to group the related functions.
Now it should be clear that the quadavg operation can re-
place the first four lines of the loop assuming that we can
get the individual 8-bit elements of the back[] and for-
ward [] ar ra ys pos iti on ed correct ly into the by te s of a 32 -
bit word . That , of co urse , is ea sy: si mply align the byte ar -
ra ys on word bo unda r ies and ac ce ss t he m wit h wor d (in-
teger) pointers.
Similarly, it should now be clear that the dspuquadaddu i
operation can replace the remaining code (except, of
cour se , f or sto rin g the r esul t i nto the de stin ation [] ar ray )
as s uming, as above, th at the 8-bit elemen ts are aligned
and pa cked into 32 - bit word s.
Figure 4-7 shows the new code. The arrays are now ac-
cessed in 32 -bit (i nt- sized) ch unks, t he lo op iter ation co n-
trol has been modified to reflect the ‘four-at-a-time’ op er -
at ion s , and th e quad avg and dspuquadaddui o p e ra ti on s
have replaced the bulk of the loop code. Finally,
Figure 4-8 shows a more compact expression of the loop
code, eliminating the temporary variable. Note that
PNX1300 C compiler does the optimization by itself.
Again, note that the code in Figure 4-7 and Figure 4-8
assumes that the character arrays are 32-bit word
ali gned and pa dded if ne cessa ry to f ill an integra l numb er
of 32 -bit wo r d s.
The original code required three additions, one shift, two
tests, three loads, and one store per pixel. The new code
using cu stom o pe r at ions requi r es o nl y tw o cu stom o per -
ations, three loads, and one store for four pixels, which is
more than a factor of six impr ovement. The a ctual perfo r-
mance improvement can be even greater depending on
how we ll the c ompi le r is abl e t o deal with t he b r anc hes i n
the original version of the code, which depends in part on
the surrounding code. Reducing the number of branches
almos t alwa ys improves th e chance s of realizing m axi-
mum performance on the PNX1300 CPU.
The code in Figure 4-8 illustr ate s sev er al aspe cts of us -
ing custom operat i ons in C -language sou r ce c ode. F i r st,
the custom operations re quire no speci al dec larations or
syntax; they appear to be simple function calls. Second,
the re i s no need to explici tly sp eci fy reg ister assignments
for sources, destinations, and intermediate results; the
compil er and s chedu ler ass ign reg iste rs for custom oper -
ati o ns ju st as the y woul d for bui lt- i n la ng uag e oper a tion s
such as integer addition. Third, the scheduler packs cus-
tom oper ation s int o PNX13 00 VL IW ins truct ions as ef fec-
tively as it packs operations generated by the compiler
for native language constructs.
Thus, although the burden of making effective use of
custom operations falls on the programmer, that burden
consi sts o nly of dis c ov er i ng the op por tu nitie s for ex pl oit-
ing t h e op er a ti ons an d then co ding the m us ing s tand ar d
C-language notation. The compiler and scheduler take
ca re of t h e r es t .
void reconstruct (unsigned char *back,
unsigned char *forward,
char *idct,
unsigned char *destination)
{
int i, temp;
for (i = 0; i < 64; i += 4)
{
temp = ((back[i+0] + forward[i+0] + 1) >> 1) + idct[i+0];
if (temp > 255) temp = 255;
else if (temp < 0) temp = 0;
destination[i+0] = temp;
temp = ((back[i+1] + forward[i+1] + 1) >> 1) + idct[i+1];
if (temp > 255) temp = 255;
else if (temp < 0) temp = 0;
destination[i+1] = temp;
temp = ((back[i+2] + forward[i+2] + 1) >> 1) + idct[i+2];
if (temp > 255) temp = 255;
else if (temp < 0) temp = 0;
destination[i+2] = temp;
temp = ((back[i+3] + forward[i+3] + 1) >> 1) + idct[i+3];
if (temp > 255) temp = 255;
else if (temp < 0) temp = 0;
destination[i+3] = temp;
}
}
Figure 4-5. MPEG frame reconstruc tion code using PNX1300 custom operations; compare with Figure 4-4.
Philips Semiconductors Custom Operations for Multimedia
PRELIMINARY SPECIFICATION 4-7
4.4 EXAMPLE 3: MOT ION-ESTIMATION
KERNEL
Another part of the MPEG coding algorithm is motion es-
timation. The purpose of motion estimation is to reduce
the cost of storing a frame of video by expressing the
c ontents o f the frame in terms of adjacent frames. A giv-
en f ram e is re duc ed to sm all b lo cks , an d a subs eque n t
frame is represented by specifying how these small
blocks ch ange po sition and appearance; us ually, storing
the difference information is cheaper than storing a
whole block. For example, in a video sequence where
the camera pan s across a sta tic scene, some frames can
be exp ress ed simply as dis placed versions of t heir pre-
decessor frames. To create a subsequent frame, most
blocks are simply displaced relative to the output screen.
The code in this example is for a match-cost calculat ion,
a small kernel of the c omple te motion-estim ation code.
As wi th t h e pr ev io us e x am pl e, t h is code p r ov ides an ex-
celle nt examp le of how to trans form so urce co de to make
the best use of PNX1300’s cu stom o per at ions .
void reconstruct (unsigned char *back,
unsigned char *forward,
char *idct,
unsigned char *destination)
{
int i, temp0, temp1, temp2, temp3;
for (i = 0; i < 64; i += 4)
{
temp0 = ((back[i+0] + forward[i+0] + 1) >> 1);
temp1 = ((back[i+1] + forward[i+1] + 1) >> 1);
temp2 = ((back[i+2] + forward[i+2] + 1) >> 1);
temp3 = ((back[i+3] + forward[i+3] + 1) >> 1);
temp0 += idct[i+0];
if (temp0 > 255) temp0 = 255;
else if (temp0 < 0) temp0 = 0;
temp1 += idct[i+1];
if (temp1 > 255) temp1 = 255;
else if (temp1 < 0) temp1 = 0;
temp2 += idct[i+2];
if (temp2 > 255) temp2 = 255;
else if (temp2 < 0) temp2 = 0;
temp3 += idct[i+3];
if (temp3 > 255) temp3 = 255;
else if (temp3 < 0) temp3 = 0;
destination[i+0] = temp 0;
destination[i+1] = temp1;
destination[i+2] = temp2;
destination[i+3] = temp3;
}
}
Figure 4-6. Re-grouped code of Figure 4-5.
void reconstruct (unsigned char *back,
unsigned char *forward,
char *idct,
unsigned char *destination)
{
int i, temp;
int *i_back = (int *) back;
int *i_forward = (int *) forward;
int *i_idct = (int *) idct;
int *i_dest = (int *) destination;
for (i = 0; i < 16; i += 1)
{
temp = QUADAVG(i_back[i], i_forward[i]);
temp = DSPUQUADADDUI(temp, i_idct[i]);
i_dest[i] = temp;
}
}
Figur e 4-7. Using the custom operation dspquadaddui to speed up the loop of Figure 4-6.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
4-8 PRELIMINARY SPECIFICATION
Figure 4-9 shows the or igi n al sou rce co de for th e ma tc h-
c ost loop. Unlik e the pre vious example, the code is not a
self-contained function. Somewhere early in the code,
the arrays A[][] and B[][] are declared; somewhere be-
tw ee n tho se de cl ara ti on s an d the lo op of in terest, the ar-
ray s are f illed w ith da t a.
4.4.1 A Simple Transf ormation
First, we will look at the simplest way to use a PNX1300
custom operation.
We start by noticing that the computation in the loop of
Figure 4-9 involves the absolute value of the difference
of two unsigned characters (bytes). By now, we are fa-
mili ar with the fact that PNX1300 includes a number of
operations that process all four bytes in a 32-bit word si-
multaneously. Since the match-cost calculation is funda-
mental to the MPEG algorithm, it is not surprising to find
a custom op er a tio n—ume8uu—that implements this op-
eration exactly.
To understand how ume8uu can be used in this case, we
need to tra nsfo rm th e cod e as in t he previ ous exa mple.
Though the steps are presented here in detail, a pro-
grammer with a even a little experience can often per-
fo rm thes e t ran sfor m a t io ns b y vi sual insp ection.
To us e a cus to m ope rat i on tha t proce sse s 4 pi xel val ue s
simultaneously, we first need to create 4 parallel pixel
computations. Figure 4-10 s how s the lo op of Figure 4-9
unrolled by a factor of 4. Unfortunately, the code in the
unrolled loop is not parallel because each line depends
on the one above it. Figure 4-11 shows a more parallel
version of the code from Figure 4-10. By simply giving
each computation its own cost variable and then sum-
ming the costs all at once, each cost computation is com-
pletely independent.
void reconstruct (unsigned char *back,
unsigned char *forward,
char *idct,
unsigned char *destination)
{
int i;
int *i_back = (int *) back;
int *i_forward = (int *) forward;
int *i_idct = (int *) idct;
int *i_dest = (int *) destination;
for (i = 0; i < 16; i += 1)
i_dest[i] = DSPUQUADADDUI(QUADAVG(i_back[i], i_forward[i]), i_idct[i]);
}
Figure 4- 8. Final v ersion of the frame -reconst ruction code.
unsigned char A[16][16];
unsigned char B[16][16];
.
.
.
for (row = 0; row < 16; row += 1)
{
for (col = 0; col < 16; col += 1)
cost += abs(A[row][col] – B[row][col]);
}
Figu re 4-9. Matc h-cos t loop for MPEG motion estimation .
unsigned char A[16][16];
unsigned char B[16][16];
.
.
.
for (row = 0; row < 16; row += 1)
{
for (col = 0; col < 16; col += 4)
{
cost += abs(A[row][col+0] – B[row][col+0]);
cost += abs(A[row][col+1] – B[row][col+1]);
cost += abs(A[row][col+2] – B[row][col+2]);
cost += abs(A[row][col+3] – B[row][col+3]);
Figure 4-10. Unrolled, bu t not paral lel, version of the loop from Figure 4-9.
Philips Semiconductors Custom Operations for Multimedia
PRELIMINARY SPECIFICATION 4-9
Excluding the array accesses, the loop body in
Figure 4-11 is now recognizable as the function per-
formed by the ume8uu custom operation: the sum of 4
absolute values of 4 differences. To use the ume8uu op-
eration, however, the code must access the arrays with
32-bit word pointers instead of with 8-bit byte pointers.
Figure 4-13 shows the loop recoded to access A[][] and
B[][] as one-dimensional instead of two-dimensional ar-
rays. We take advantage of our knowledge of C-lan-
guage array storage conventions to perform this code
transformation. Recodi ng to use one-dimensio nal arr ays
prepares t he code for transformation to 32-bit array ac-
cesses.
(F rom he r e on, unti l t he final code is show n, th e dec la ra-
tions of t he A and B arrays will be omitted from the code
fragments for the sake of brevity.)
Figure 4-14 shows the loop of Figure 4-13 recoded to
us e ume 8u u. Once a ga in taki ng adva nt age o f our kno w l-
edge of the C-languag e arra y storage conventi ons, the
one-dimensional byte array is now accessed as a one-di-
mensional 32-bit-word array. The declarations of the
pointer s I A an d I B as p ointer s to i nt eg er s is th e k e y, but
also notice that the multiplier in the expression for row
off set has be en sca led fr om 16 t o 4 to a ccoun t for the fact
that there are 4 bytes in a 32-bit word.
Of co ur se, si nce we are no w usin g on e-di mens iona l a r-
rays to access the pixel data, it is natural to use a single
for loop instead of two. Figure 4-12 shows this stream-
lined version of the code without the inner loop. Since C-
language arrays are stored as a linear vector of value s,
we can simply increase the number of iterations of the
outer loop fr om 1 6 to 64 to trave rse the entire ar r ay .
The recoding and us e of the ume8uu operation has re-
sult ed in a substantial im provemen t in the perfo rmance
of the match-cost loop. In the original version, the code
executed 1280 operations (including loads, adds, sub-
tracts, and absolute values); in the restruct ured version,
there are only 256 operations—128 loads, 64 ume8uu
operations, and 64 additions. This is a factor of five re-
duction in t h e numb e r of operatio ns e xecuted. Also, the
unsigned char A[16][16];
unsigned char B[16][16];
.
.
.
for (row = 0; row < 16; row += 1)
{
for (col = 0; col < 16; col += 4)
{
cost0 = abs(A[row][col+0] – B[row][col+0]);
cost1 = abs(A[row][col+1] – B[row][col+1]);
cost2 = abs(A[row][col+2] – B[row][col+2]);
cost3 = abs(A[row][col+3] – B[row][col+3]);
cost += cost0 + cost1 + cost2 + cost3;
Figure 4-11. Parallel version of Figure 4-10.
Figure 4-12. The loop of Figure 4-14 with the inner
loop eliminated.
unsigned int *IA = (unsigned int *) A;
unsigned int *IB = (unsigned int *) B;
for (i = 0; i < 64; i += 1)
cost += UME8UU(IA[i], IB[i]);
Figure 4-13. The loop of Figure 4-11 recoded with one-dimensional array accesses.
unsigned char A[16][16];
unsigned char B[16][16];
.
.
.
unsigned char *CA = A;
unsigned char *CB = B;
for (row = 0; row < 16; row += 1)
{
int rowoffset = row * 16;
for (col = 0; col < 16; col += 4)
{
cost0 = abs(CA[rowoffset + col+0] – CB[rowoffset + col+0]);
cost1 = abs(CA[rowoffset + col+1] – CB[rowoffset + col+1]);
cost2 = abs(CA[rowoffset + col+2] – CB[rowoffset + col+2]);
cost3 = abs(CA[rowoffset + col+3] – CB[rowoffset + col+3]);
cost += cost0 + cost1 + cost2 + cost3;
PNX1300/01/ 02/11 Data Book Philips Semiconductors
4-10 PRELIMINARY SPECIFICATION
overhead of the inner loop has been eliminated, further
incr eas ing t h e perform anc e ad vantag e.
4.4.2 More Unrolling
The code transformations of the previous section
achieved impressive performance improvements, but
gi ven th e VLI W natur e of t he PNX 130 0 CPU, mo re can
be done to exploit PN X1300’s paralle lism .
The code in Figure 4-12 has a loop containing only 4 op-
erations (excluding loop overhead). Since PNX1300’s
branches have a 3-instruction delay and each instruction
can con t a in u p to 5 op e ratio ns, a fu ll y u tiliz ed mini mum -
sized loop can contain 16 operations (20 minus loop
overhead).
Th e PN X130 0 com p ila t i on sy stem pe rf or ms a w id e v ar i -
ety of powerful code transformation and scheduling opti-
mizations to ensure that the VLIW capabilities of the
CPU are exploited. It is still wise, however, to make pro-
gram parallelism explicit in source code when possible.
Explicit parallelism can only help the compiler produce a
fast running progra m.
To this end , we c an unroll the loop of Figure 4-12 some
number of times to create explicit parallelism and help
the compiler create a fast running loop. In this case,
where the number of iterations is a power-of-two, it
makes sense to unroll by a fac to r that is a power-of-two
to cr eate cl ea n co de.
Figure 4-15 shows the loop unrolled by a factor of eight.
The compiler can apply common sub-expression elimi-
nation and other optimizations to eliminate extraneous
operations in the array indexing, but, again, improve-
ment s in th e so urc e co de can on ly he lp the c omp i ler pro-
duce the best possible code and fastest-running pro-
gram.
Figure 4-16 sho ws one w ay t o mo dif y the code fo r si m-
pler arr ay indexing.
Figure 4-14. The loop of Figure 4-13 recoded with 32-bit array accesses and the ume8uu custom operation.
unsigned int *IA = (unsigned int *) A;
unsigned int *IB = (unsigned int *) B;
for (row = 0; row < 16; row += 1)
{
int rowoffset = row * 4;
for (col4 = 0; col4 < 4; col4 += 1)
cost += UME8UU(IA[rowoffset + col4], IB[rowoffset + col4]);
}
unsigned int *IA = (unsigned int *) A;
unsigned int *IB = (unsigned int *) B;
for (i = 0; i < 64; i += 8)
{
cost0 = UME8UU(IA[i+0], IB[i+0]);
cost1 = UME8UU(IA[i+1], IB[i+1]);
cost2 = UME8UU(IA[i+2], IB[i+2]);
cost3 = UME8UU(IA[i+3], IB[i+3]);
cost4 = UME8UU(IA[i+4], IB[i+4]);
cost5 = UME8UU(IA[i+5], IB[i+5]);
cost6 = UME8UU(IA[i+6], IB[i+6]);
cost7 = UME8UU(IA[i+7], IB[i+7]);
cost += cost0 + cost1 + cost2 +
cost3 + cost4 + cost5 +
cost6 + cost7;
}
Figure 4-15. Unrolled version of Figure 4-12. This
code ma ke s goo d use of PN X1 30 0 ’s VLIW capabili-
ties.
unsigned char A[16][16];
unsigned char B[16][16];
.
.
.
unsigned int *IA = (unsigned int *) A;
unsigned int *IB = (unsigned int *) B;
for (i = 0; i < 64; i += 8, IA += 8, IB +=
8)
{
cost0 = UME8UU(IA[0], IB[0]);
cost1 = UME8UU(IA[1], IB[1]);
cost2 = UME8UU(IA[2], IB[2]);
cost3 = UME8UU(IA[3], IB[3]);
cost4 = UME8UU(IA[4], IB[4]);
cost5 = UME8UU(IA[5], IB[5]);
cost6 = UME8UU(IA[6], IB[6]);
cost7 = UME8UU(IA[7], IB[7]);
cost += cost0 + cost1 + cost2 +
cost3 + cost4 + cost5 +
cost6 + cost7;
}
Figure 4-16. Code from Figure 4-15 with simplified
array in de x ca l c ula t ions.
PRELIMINARY SPECIFICATION 5-1
Cache Architecture Chapte r 5
by Eino Jacobs
5.1 MEMORY SYSTEM OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The high-performance video and audio throughput of
PNX1300 is implemented by its DSPCPU and autono-
mous I / O an d c o- proc es si ng u nits, bu t the foundatio n of
this processing is the PNX1300 memory hierarchy. To
get the full potential of the chip’s processing units, the
memory hierarchy must read and write data (and DSP
CPU instructions) fast enough to keep the units busy.
To meet the requirements of its target applications,
PNX1300’s memory hierarch y must satisf y the confli ct-
ing goals of low cost, simple system design (e.g., low
parts count), and high performance. Since multimedia
video streams can require relatively large temporary
storage, a significant amount of external DRAM is re-
quired. Minimizing the cost of bulk memory is important.
PNX1300’s memory system achieves a good compro-
mise between cost and performance by coupling sub-
stantial on-chip caches with a glueless interface to syn-
chronous DRAM (SDRAM). SDRAM provides higher
bandwidth than standard DRAM for only a small cost pre-
mium . A blo ck di agr am of the m emo ry sy ste m i s s how n
in Figure 5-1. SDRAM permits PNX1300 to use a nar-
rower and simpler interface than would be required to
achiev e sim ilar p er f or m anc e wit h stand ar d D R A M .
The separate on-chip data and instruction caches serve
only th e DSPC PU si nce the dat a a cces s pa tterns of the
aut o no mo us I/O an d grap hic s u ni t s e xh ib it litt l e o r no lo -
cali ty o f ref ere nce (th ey ac ces s eac h piec e of the m ulti -
media data s t ream only onc e in each operati on ) .
Without the caches, the CPU would not be able to
ach ieve i ts p erfor man ce pote nti al. S DRA M h as enou gh
band width to handle se rial stre ams of multimedia data,
but its bandwidth and latency are insufficient to satisfy
the CPU’s high rate of random data accesses and re-
peat ed instruction accesses.
Table 5-1 shows bandwidth parameters for the PNX1300
DSPCPU and the main-memory interface. Although 400
MB/s is a lot of bandwidth, it is clear that the SDRAM
alone cann ot k eep up w i th t h e CP U ’s maximum require-
ments for instructions and data. Luckily, multimedia algo-
ri thms res emb l e othe r comp ut er pr ogr a ms in term s of lo-
calit y of ref erence , so the on- chip caches typically supply
VLIW
CPU
Three
Branch
Units
Decompressor
32KB, 8-way
Instruction
Cache
Two
Memory
Units
16KB, 8-way
Data
Cache
Three sets, each has address,
opcode, condition, and guard
224 bits of decompressed
instruction
Two sets, each has a guard,
opcode, data, and two
addr ess component s
Main
Memory
Interface
SDRAM
Main
Memory
Inter nal data highway:
32-bit address, 32-bit
data
To on-chip
peripherals
Main- memo r y bus:
glueless, SDRAM
control with 32- bi t
data
Figure 5-1. The main components of the PNX1300 memory system.
Ta ble 5-1. 100 -MH z PNX1 300 me mo ry ba ndwidth
parameters
Magnitude Use
2800 MB/s Instruction bandwidth (224 bits/instruction)
800 MB/s Data bandwidth (two 32-b it memory ports)
400 MB/s Main-memory bandwidth (one 32-bit port)
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-2 PRELIMINARY SPECIFICATION
the majori ty of instructi ons an d dat a to the DS PCPU. The
wide paths to the caches are matched to the bandwidth
requirements of the DSPCPU.
To improve cache behavior and thus program perfor-
man ce , the c ach es ha ve a lo ckin g me chan ism . In addi -
tion, the instruction cache is coupled with an instruction
de co m pr e s si on un it. The co mpr e ss ed i n s tr u ct ion fo rm a t
impr ov es t he c ache hit rate and red uce s th e b us band -
width required between main memory and cache. In-
structions in main memory and cache use the com-
pre s se d f orm at.
PNX1300’s processing units access the external
SDRAM through the on-chip central “da ta highway” bus.
The highway consists of separate 32-bit address and
data bus es, a nd use of t he bus is mediated by the main-
memory interface unit. The main-memory inter face con-
tains the SDRAM controller and a central arbiter that de-
termines how much of the available SDRAM memory
bandwidth is al locate d to each unit . Unus ed bandwidth is
alw ays m ade av aila bl e to the V LIW CP U for c ach e ref ill
an d memory acc esses that bypass t he caches .
Table 5-2 gives a summary description of each compo-
nent of PN X1 300 ’s memory system.
5 .2 DRAM A PER TU RE
PNX1300 implements a 32-bit linear address space of
bytes. Within that address space, PNX1300 supports
several different apertures for specific purposes. The
DRAM aperture describes the part of the address space
into which the external SDRAM is mapped. SDRAM
must consist of a sing le, contiguous re gion of memo ry,
which is the most practical configuration for PNX1300
systems.
The location and size of the DRAM aperture is defined by
two registers, DRAM_BASE and DRAM_LIMIT. These
registers are both readable and writeable as MMI O reg-
ist ers and as P CI conf iguration s pace regi sters . The v iew
of the registers in MM IO sp ace is shown in Figure 5-2.
The view of the registers in PCI configuration space is
described in Ch ap ter 11 , “PCI Interface.” I n no rm al op er -
ation, the base addre ss regi sters a re assigne d once dur -
ing bo ot an d no t chan ge d when th e DSP CP U is runn in g.
Refer to Chapter 11, “PCI Interface,” and Chapter 13,
“System Bo ot,” for a description of this proces s.
DRAM_LIMIT must be set equal to DRAM_BASE plus
the actual size of SDRAM present. The amount of the
SDRAM is not required to be a power of 2, but it must be
a multiple of 64 KB. Note that the size of the aperture as
set in the PCI configuration space can be larger, be-
cause it must be a power of 2.
A memory operation will access SDRAM if its address
satisfies:
[DRAM_BASE] ≤ address < [DRAM_LIMIT]
Any address outside this range cannot access SDRAM.
When P NX1300 i s reset, D RAM_B ASE_FIE LD is se t t o
0x0 and DRAM_LIMIT is set to 0x0010 0000 (1-MB
DRAM aperture starting at address 0x0). The boot pro-
ce ss de scri bed in Chapter 1 3, “System Boo t,” ove rrides
th es e ini tial se t ti ng s .
Tab l e 5-2 . Summ ary of m emory syste m
characteristics
Unit Description
Branch units Branch units execute branch operati ons . Up to
three branch operations can be executed in
parallel, but the program must guarantee that
only one bran ch is taken.
Decompres-
sion uni t Instructions are stored in memory and in the
instruction cache in a space-saving, com-
pressed format. The decompression unit
expands instr uc tio ns to their full , 28-byte size
before they are issued to the CPU.
Instruction
cache The instruction cache holds 32 KB, is 8-way
set-associative, and has a 64-byte block size.
A miss in a block causes the entire block to be
read from SDRAM. The cache can sustain an
issue rate of one instruction per cycle on
cache hits.
Memory units Memor y units execute load and store op era-
tions. The data cache is dual ported to allow
the memory units to operate concurrently.
Data cache The data cache holds 16 KB, is 8-way set-
associati ve, has a 64- byte block size, and
implements a copy back, allocate-on-write pol-
icy. A miss in a block causes the entire block
to be read from SDRAM. The cache supports
memor y -mapped I/O through non-cac hea ble
address regions.
Data highway The on-chip data highway bus serves all on-
chip units. The highway has separate 32-bit
data and address buses. Bus bandwidth is
allocated by the highway arbiter according to
one of s everal modes.
Main-memory
interface The main-memory interface contains the data-
highway access ar biter, the SD RAM control-
ler, and MMIO logic.
SDRAM main
memory Exter nal SDRAM conn ects gl uelessly to
PNX1300 over the 32-bit main-memory bus.
31 0371115192327
DRAM_BASE (r/w)0x10 0000 DRAM_BASE_FIELD
DRAM_LIMIT (r/w)0x10 0004 DRAM_LIMIT_FIELD
0000000000000000
0000000000000000
MMIO_BASE
offset:
0000
Figure 5-2. Formats of the DRAM_BASE and DRAM_LIMIT registers.
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-3
5.3 DATA CACHE
The data cache serves only the DSPCPU and is con-
trolled by two memory units that execute the load and
store operations issued by the DSPCPU. The following
sections describe the data cache and its operation;
Table 5-3 summarizes the important characteristics for
easy refe ren c e.
5.3.1 General Cache Parameters
The PNX1300 data cache is 16 KB in size with a 64-byte
block size. Thus, it contains 256 blocks each with its own
address tag. The cache is 8-way set-associative, so
there are 32 sets, each containing 8 tags. A single valid
bi t is ass oc iat e d wi t h a bl oc k , so each block a nd associ -
ate d addre ss tag is ei ther en tirel y vali d in the cach e or in-
valid. O n a cac he m is s , 64 by te s a r e rea d f ro m S DR AM
to m ak e the en t i re block val id.
Each block also contains a dirty bit, which is set whenev-
er a write to the block occurs. Each set contains 10 bits
to support the hi erarchical LRU replacement policy.
The geometry of the data cache is available to software
by read in g the MM IO reg ist er DC _PA RAM S . Figure 5-3
shows the format of the DC_PARAMS register;
Table 5-4 lists its field values. The product of block size,
associativity, and number of sets gives the total cache
size (16 KB in this case).
5.3.2 Address Mapping
PNX1300 data addresses are mapped onto the data
cache storage structure as shown in Figure 5-4. A data
address is partitioned into four fields as described in
Table 5-5.
Tab l e 5-3 . Summ ary of data cach e c hara cter is t ic s
Characteristic PNX1300 Implementation
Cache si ze 16 KB
Cache assoc iativi ty 8-way set-associ ative
Block size 64 bytes
Va lid bits One va lid bit per 64-byte block
Dirty bits One dir ty bit per 64-byte block
Miss transfer order Miss transfers begin with the critical
word first
Replacement poli-
cies Cop yback, allocate on write, hierarchical
LRU
Endianness Either li ttle- or big-endian, determined
by P CSW b it
Por ts The cache is quasi d ual por ted; two
accesses can proceed concurrently if
they reference different banks (deter-
mined by bits [4:2] of the computed
addresses)
Alignment Access must be naturally aligned (32-bit
words on 32-bit boundaries, 16-bit half-
words on 16-bit boundaries); the appro-
priate number of LSBs of un-naturally
aligned addresses are set to zero.
For mis aligned stores, PCSW.M SE is
asserted to generate a n exception
Pa rtial word oper a-
tions The cache implements 8-bit and 16-bit
accesses with the same performance as
32-bit accesses
Operation latency Three cycles for both load and store
operations
Coh er ency enforce-
ment Sof twa r e uses s pecial operations to
enforce cache cohere ncy
Cache locking Up to 1/2 (four out of 8 blocks of each
set) of the cache contents can be
locked; granula r ity is 64-byte
Non-cacheable
region One non-ca che able ap e rture in the
DRAM address space is supported.
Table 5-4. DC_PARAMS field values
Field Name Value
BLOCK SIZE 64
ASSOCIATIVITY 8
NUMBER_OF_SETS 32
Table 5-5. Data address field partitioning
Field Address
Bits Purpose
Byte 1..0 B yte offset within a word for by te or half-
word accesses
Word 5..2 S ele cts one of the words in a set (one o f
16 words in the case of PNX1300)
Set 10..6 Selects one of the sets in the cache (one
of 32 in the case of PNX1300)
Tag 31..11 Compared against address tags of set
members
31 0371115192327
DC_PARAMS (r/o)0x10 001C ASSOCIATIVITY NUMBER_OF_SETS
MMIO_BASE
offset:
BLOCKSIZE
Figure 5-3. Format of the DC_PARAMS register.
0
Word ByteSetTag
31 12561011
Data Cache Address
Fig ur e 5-4 . D at a cac he addr es s par tit ioni n g.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-4 PRELIMINARY SPECIFICATION
5.3.3 Miss Processing Order
Wh en a miss occ urs, t he da ta cac he fil ls the blo ck c on-
taining the requested word from the critical word first.
The CPU is stalled until the fi rst word is transferred. The
bl oc k is then fill ed up w h ile t he C P U ke ep s running.
5.3.4 Replacement Policies, Coherency
The cache implements a copyback replacement policy
with one dirty bit per 64-byte block. Thus, when a miss
occurs and the block selected for replacement has its
dirty bit set, the dirty block must be written to main mem-
ory to pres erv e its m odifi ed co nte nts. On PNX 1300 , t he
dir ty blo ck i s wr itten to me mor y before the needed bloc k
is fetc he d.
Coherency is not maintained in any way by hardware be-
tween the data cache, the instruction cache, and main
memory. Sp ecial op erations are availa ble to imple ment
cache coherency in software. See Section 5.6, “Cache
Coherency,” for a discussion of coherency issues.
Write misses a re handle d with an alloca te-on-write poli-
cy—t he write that caused the miss stores its data in the
cache after the missing block is fetched into the cache.
The cache implements a hierarchical LRU replacement
algorithm to determine which of the eight elements
(blocks) in a set is replaced. The algorithm partitions the
eight set el em ents in to fo ur groups, eac h group w ith tw o
elements. The hierarchical LRU replacement victim is
determined by selecting the least-recently used group of
two ele men t s and t h en s electin g the lea st- recently us ed
elem en t in tha t gr oup. T his hi era rchi cal al go rithm yiel ds
performance close to full LRU but is simpler to imple-
ment.
See S e ctio n 5 . 5, “LRU Algorithm,” fo r a f u ll dis cus si on of
the LRU algo rithm.
5.3.5 Alignment, Pa rti al-Wor d Transfers,
Endian-ness
The cache implements 32-bit word, 16-bit half-word, and
8-bit byte transfers. All transfers, however, must be to
addresses that are naturally aligned; that is, 32-bit words
must be aligned on 32-bit boundaries, and 16-bit half-
words must be aligned on 16-bit boundaries.
Li ke ot her PNX1 300 pro cess ing u nit s, th e CP U ha s the
capability to use either big- or little-endian byte order. I t
is recommended that all units and the CPU run with the
same endian-ness. Detailed endian-ness description
can be foun d in Appe ndix C, “Endian-ness.”
5.3.6 Dual Ports
To allow two accesses to proceed in parallel, the data
cache i s quasi -dual porte d. The ca che is impleme nted as
eigh t banks of sin gle-port ed memo ry, but th e hardware
allow s ea c h ba nk to o p e rate independently. Thus, when
the addresses of two simultaneous access es select two
different banks, both accesses can complete simulta-
neou sly . B an k sele ctio n is det ermi ned by t he t hre e low -
order address bits [4..2] of each address. Thus, the
words in a 64-byte cache block are distributed among the
eight blocks, which prevents conflicts between two simul-
taneously issued accesses to adjacent words in a cache
block. The PNX1300 compiling system attempts to avoid
bank conflicts as much as possible.
The dual-ported cache can execute the load and store
opcodes (ild8d, uld8d, ild16d, uld16d, ld32d, h_st8d,
h_st16d, h_st32d, ild8r, uld8r, ild16r, uld16r, ld32r,
ild16x, uld16x, ld32x) in either or both of the two ports.
The special opcodes alloc, dcb, dinvalid, pref, rdtag and
rds ta tus c a n o nly b e ex ec uted in th e s ec ond po r t, not in
th e fi r s t port . Whe nev er any of thes e s pe cial opc od es is
issued in the second port, there should not be a concur-
ren t load or s tore op era tion i n the fi rst . This i s a spe cial
s cheduli ng constraint.
5.3.7 Cache Locking
Th e data cac he allo ws the co ntent s o f up to one-h alf of
it s bl oc ks to be locke d. Thus , on PNX1 30 0, up to 8 KB of
th e cac he c an be used as a hi gh- sp eed loc al data me m-
ory. Only four out of eight blocks in any set can be
locked.
A locked block is never chosen as a victim by the re-
placement algorithm; its contents remain undisturbed un-
til either (1) the block’s loc ked stat us is c hange d expl icit ly
by software, or (2) a dinvalid operation is executed that
tar ge ts the lock ed block.
Cache locking occurs only for the data in the address
range described by the MMIO registers
DC_LOCK_ADDR and DC_LOCK_SIZE. T he granulari-
ty of the address range is one 64-byte cache block. The
MMIO register DC_LO C K _ C T L contains the cach e- loc k-
ing enable bit DC_LOCK_ENABLE. Figure 5-5 shows
the layo ut o f the data-cache lock registers. Locking will
oc cur for an ad dre ss i f lock in g i s en abl ed an d bo th of the
following are true:
1. The address is greater than or equal to the value in
DC_LOCK_ADDR.
2. Th e ad d re ss i s les s th an the sum of the valu es i n
DC_LOCK_ADDR and DC_LOCK_SIZE.
Programmers (or compilers) must combine all data that
needs to be locke d into this single li near ad dress r an ge.
Setting DC _LOCK_ENABLE to ‘1’ causes the followi ng
sequenc e of events :
1. All blocks that are in cache locations that will be used
for locking are copied back t o main m emory ( if t hey
are dir t y) an d remove d f ro m t he cache.
2. All blocks in the lock range are fetched from main
memory into the cac he. I f any block in the lock range
was al r ea dy i n the c ac he, it’s first copied back into
main memory (if it’s dirt y ) an d invalidate d.
3. The LRU status of any set that contains lo cke d blocks
is set to t he in itializ atio n value.
4. Cache locking is activ ated so that the locked blocks
c annot be victims of the replacement alg orithm.
This sequence of events is triggered by writing ‘1’ to
DC_LOCK_ENABLE even if the enable is already set to
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-5
‘1’. Setting DC_LOCK_ENABLE to ‘0’ ca use s no acti on
except to allow the previously locked blocks to be re-
placement victims.
To program a new lock range, the following sequence of
oper a tion s is us e d:
1. Disable cache locking by writing ‘0’ to
DC_LOCK_ENABLE.
2. D ef ine a new lock r ange b y wr iting t o
DC_LOCK_ADDR and DC_LOCK_SIZE.
3. Enable c ac he lock ing by w ritin g ‘1’ to
DC_LOCK_ENABLE.
Dirty locked blocks can be written back to main memory
while locking is enabled by executing copyback opera-
tions in so ftw are.
Programmer’s note: Software should not execute din-
valid operations on a locked block. If it does, the block
will be remo ved fro m the cache, crea ting a ‘hole’ in the
lock range (and the data cache) tha t cannot be reused
unt il lock ing is d ea c ti vate d .
Cache loc king is di sabled by default whe n PNX1300 is
reset.
The RESERVE D field in DC_LOCK_CTL should be ig-
nor ed on reads an d written as all zeroes.
Lock ing shou ld not be enabled by PCI access es to the
MMIO registers.
5.3.8 Memory Hole and PCI Aper ture
Disable
Bits 6 and 5 in DC_LOCK_CTL comprise the
APERT URE_C ONTROL field. Th is fi eld can be us ed to
ch an g e the m emor y ma p a s se en by th e D SP CP U . The
hardware RESET value of the field corresponds to the
memory map as described in Section 3.4.1, “Memory
Map.”
5.3.9 Non-cacheable Region
The data cache s uppo rts one non-cacheable address re-
gio n wi thin th e DRAM addr ess spa ce apert ure. Th e bas e
address of this region is determined by the value in the
DRAM_CACHEABLE_LIMIT MMIO register, which is
shown in Figure 5-6. Since uncached memory opera-
tions always incur many stall cycles, the non-cacheable
region should be used sparingly.
A memory operation is non-cacheable if its target ad-
dre s s sati s fi e s :
[dram_cacheable_limit] <= address < [dram_limit]
Thus, the non-cacheable region is at th e h igh end of the
DRAM aperture. The format of the
DRAM_CACHEABLE_LIMIT register forces the size of
the non-cacheable region to be a multiple of 64 KB.
When PNX1300 is reset, DRAM_CACHEABLE_LIMIT is
s et equal to DR AM_L IM IT, whi ch r es ul ts in a zer o-l eng th
non- c a ch eable r eg io n.
Programmer’s note: When DRAM _CACHEABL E_LIMIT
is changed to enlarge the region that is non-cacheable,
software must ensure coherency. This is accomplished
by explicitly copying back dirty data (using dcb opera-
tions) and invalidating (using dinvalid operations) the
cache bl ock s in the pr e viou sly unlo cked r egi on.
DC_LOCK_ADDR (r/w)0x10 0014 DC_LOCK_ADDRESS
DC_LOCK_SIZE (r/w)0x10 0018 DC_LOCK_SIZE
000000
0 00000
31 0371115192327
DC_LOCK_CTL (r/w)0x10 0010 0000000000000000000000000
DC_LOCK_ENABLE
MMIO_BASE
offset:
00000000
000000000 000000000 0
APERTURE_CONTROL
reserved
65
Fig u re 5-5. F or mats of the regis ters i n charge of da t a-cache locking .
Table 5-6. Aperture control field
Value Memory map properties
00 (RE SE T) Normal operation memor y map (Section 3.4.1):
•loads to 0..0xff always return 0 and cause no
PCI read (memory hole is enabled)
•PCI aperture(s) are enabled
01 •loads to address 0..0xff cause a PCI read, i.e.
the memor y hol e is di sa bled
•PCI aperture(s) are enabled
10 PCI apertures are disabled for loads
•loads return a 0 and cause no PCI read
11 RESERVED for future extensions
31 0371115192327
DRAM_CACHEABLE_LIMIT
(r/w)
0x10 0008 DRAM_CACHEABLE_LIMIT_FIELD 0000000000000000
MMIO_BASE
offset:
Figure 5-6 Formats of the DRAM_CACHEABLE_LIMIT register.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-6 PRELIMINARY SPECIFICATION
5.3.10 Special Data Cache Operations
A program can exercise some control over the operation
of the data cache by executing special operations. The
special operations can cause the data cache to initiate
the copyback or invalidation of a block in the cache.
These operations are typically used by software to keep
the cache coherent with main memory.
In ad di ti o n, the re are s pe cial oper a t ions th at all ow a pr o-
gram to read tag and status information from the data
cache.
Specia l data cac he oper ations are always executed on
th e me mo ry po rt asso c ia t ed with is su e sl ot 5.
5.3.10.1 Copybac k and in validate op erations
The data cache controller recognizes a copyback and an
invalidate operation as shown in Table 5-7.
The dcb and dinvalid operations both compute a target
word address that is the sum of a register and seven-bit
offset. The offset can be in the range [–256..252] and
must be d ivisible by fou r.
dcb o perat ion. The dcb operation computes the target
address, and if the block containing the address is found
in t he data cac he, its con tent s are w rit ten back to ma in
memory if the block is both valid and dirty. If the block is
not present, not valid, or not dirty, no action results from
the dcb operation. If the dcb causes a copyback to occur,
the CPU is stalled until the copyback completes. If the
block is not in cache, the operation causes no stall cy-
cles. If the block is in cache but not dirty, the operation
causes 4 stall cycle s. If the blo ck i s dir ty, the d cb opera-
ti on caus es a writ eback an d take s at least 19 st all cycles.
The dcb operation clears the dirty bit but leaves a valid
copy of the written-back block in the cache.
dinvalid operation. The dinvalid operation computes
the target address, and if the block containing the ad-
dress is found in the data cache, its valid and dirty bits
are cleared. No copyback operation will occur even if the
block is valid and dirty prior to executing the dinvalid op-
eration. The CPU is stalled for 2 cycles, if the target block
is in the cache; otherwise, no stall cycles occur.
A dinvalid or dcb operation updates the LRU information
to least r ecently used in its set.
Programmer’s note: Software should not execute din-
valid operations on locked blocks; otherwise, a ‘hole’ is
created that cannot be reused until locking is deactivated.
5.3.10.2 Data cache tag and status
operations
The data cache controller recognizes two DSPCPU op-
erations for readin g cache s tatu s a s shown i n Table 5-8.
The rdtag and rdstatus operations both com pute a target
word address that is the sum of a register and scaled
s even-bit offset. The offs et must be divisi ble by four and
in the range [–256..252].
rdtag operation. The tar get addr es s com puted by r dtag
s elects the d at a cache block by specifying th e cache set
and set element directly. Address bits [10..6] specify the
c ache set (o ne of 32), and bit s [13..1 1] specify the set el-
em ent (one of eight). All other target address bits are ig-
nored. This operation causes no CPU stall cycles.
The result of the rdtag operation is a full 32-bit word with
the format show n in Figure 5-7.
rd sta tus ope ration . The tar get addre ss com pute d by rd-
status selects the data cache set by specifying the set
number directly. Address bits [10..6] specify the cache
s et (one of 32); all oth er target address bits are igno red.
This operation causes 1 CPU stall cycle.
Th e res ult o f the rd st atus ope rat ion is a full 32- bit word
wit h th e form a t show n in Figure 5-7. Se e Section 5.6.7,
“LRU Bit Definitions,” for a description of the LRU bits.
Table 5-7. Copyback and in validate operations
Mnemonic Description
dcb(offset) rsrc1 Data-cache copyback b lock . Causes
the block that contains the target
address to be copied back to main
memory if the block is valid and dir ty.
dinvalid(offset) rsrc1 Data-cache invalidate block. Causes
the block that contains the target
address to be invalidated. No copy-
back occurs ev en if the block is dirty.
Table 5-8. Cache read-status operations
Mnemonic Description
rdtag(offset) rsrc1 Read data-cache tag. The target
address selects a data-cache block
directly; the operation returns a 32-bit
result containing the 21-bit cache tag
and the valid bit.
rdstatus ( offset) rsrc1 Read data-cache statu s. The target
address selects a data-cache set
directly; the operation returns a 32-bit
result containing the set’s eight dirty
bits and ten LRU bits.
31 0371115192327
VALID
rdtag Result Format TAG
r d st atus Re su lt Fo r m a t LRUDIRTY00000000000
0000000000
000
Figure 5-7. Result formats for rdtag and rdstatus operations.
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-7
5.3.10.3 Data cache allocation operation
The data cache controller recognizes allocation opera-
ti ons as shown i n Table 5-9. T he al locati on op erati ons a l-
locate a block and set the status of this block to valid. No
dat a is fetc hed fro m ma in m emo ry. Th e all ocat ed b lock
is unde fi ne d aft er t hi s ope rat i on . The p rogr a mme r has t o
fill it w ith valid data by store operations. Allocation oper-
ations t o apertures other th an cach eable DRAM will be
discarded. Allocation of a non-dirty block causes 3 stall
cycles. Allocation of a di rty block will cause writeback of
thi s bl ock to th e S DRA M a nd ta ke at least 11 sta ll cy cles.
5.3.10.4 Data cache prefetch operation
The data cache controller recognizes prefetch opera-
tions as shown in Table 5-10. The prefetch operations
load a full cache block from memory concurrently with
other comp utation. If the prefetched block is already in
cache, no data is fetched from main memory. Prefetch
operations to other apertures than cacheable DRAM are
discarded. This operation is not guaranteed to execute ,
it will not exec ute if the cach e is al ready occupied with
two cache misses when the operation is issued. The
prefetch operations cause 3 stall cycles if there is no
copyback of a dirty block. If a dirty block is the target of
the prefetch, the dirty block will be written back to
SDRAM, and at le ast 11 stall cycles are taken.
5.3.11 Memory Operation Ordering
The PNX1 300 memory sy stem implemen ts tra dit ional or -
dering for memory operation s that are issued in different
clock cycles. That is, the effects of a memo r y operat io n
iss ued in cycle j occur bef ore the ef fects of a memor y op-
era ti on is s ue d in cy c le j+1.
For memor y opera tion s issued in t he same cycle , ho wev-
er, it is not possible to execute memory operations in a
traditional order. So long as the simultaneous memory
operations access different addresses (aliasing is not
possible in PN X 1 300), no problem s can occ u r. If t wo s i -
multaneous operations do access the same address,
however, PNX1300 behavior is undefined. Specifically,
two cases are possible:
1. When multiple values are written to the same address
in t he sa me cycle , the resulti ng value in memory is u n -
defined.
2. When a read and a wri te occur to the same address
in the same clock cy cle, th e value retur ned b y th e
read is undefined.
The behavior of simultaneous accesses to the same ad-
dress is undefined regardless of whether one or both
memory operations hit in the cache.
Hidden Memory System Concurrency. Some cache
operations may be overlapped with CPU execution. In
general, a program cannot determine in what order
cache mi sses wi ll com plet e nor can a pro gram deter min e
when and in what order copyback operations will co m-
plet e. A program can, however, enforce the completion
of copyback transactions to main memory because copy-
back and invalidate operations can complete only if
pe nd ing c opyba ck tr ansa ct ions for t he same bl ock have
comple ted. T hus, a prog ram can s ynchr onize to the c om-
pletion of a cop yba ck operation by di rt ying a b loc k, i ssu-
ing a c opyb ac k o pe r at io n f or the bloc k , and t h en i ss ui ng
an inv alidate o pe ra tion fo r the block.
Orde ring Of Spe cial M emory Opera tions . The follow-
ing are special memory operations:
1. Lo ads or st ores to MM I O addr e s se s.
2. N on -c ac hed load s or sto r es .
3. Any copy back or inva lidate ope rati o n.
4. Lo ad s or st ore s th a t caus e a P CI -bus a cc e ss.
The CPU is stalled until these special memory opera-
tions are completed; there is no overlap of CPU execu-
tion with these special memory operations. Thus, a pro-
grammer can assume that traditional memory operation
ordering applies to special memory operations. Note,
however, that ordering is undefined for two special mem-
ory operations issued in the same cycle.
Ta ble 5-9. Data cache allocation operations
Mnemonic Description
allo cd(offset) rsrc1 Data-cache allocate block with dis-
placement. Causes the block with
address (rsrc1+offset) &
(~( cache_ block_size - 1)) to be al lo-
cated and set valid.
allo cr rsrc1 rsrc2 Data-cache allocate block with index.
Cau ses the block with address
(rsrc1+rsrc2) & (~(cache_block_size -
1)) to be allocated and set valid.
allo cx rsrc1 rsrc2 Data-cache allocate block with scaled
index. Causes the block with address
(rsrc1 + 4 * rsrc2) &
(~( cache_ block_size - 1)) to be allo-
cated and set valid.
Table 5-10. Data cache prefetch o perations
Mnemonic Description
prefd(offset) rsrc1 Data-cache prefetch block with dis-
placement. Causes the block with
address (rsrc1+offset) &
(~( cache_ block_size - 1)) to be
prefetched
prefr rsrc1 rsrc2 Data-cache prefetch block with index.
Ca uses the block with address
(rsrc1+rsr c2) & (~(cache_block_si ze -
1)) to be prefetched.
pref1 6x rsrc1 rsrc2 Data-cache pre fetch block with scaled
16-bit index. Causes the block with
address (rsrc1 + 2 * rsrc2) &
(~( cache_ block_size - 1)) to be
prefetched.
pref3 2x rsrc1 rsrc2 Data-cache pre fetch block with scaled
32-bit index. Causes the block with
address (rsrc1 + 4 * rsrc2) &
(~( cache_ block_size - 1)) to be
prefetched.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-8 PRELIMINARY SPECIFICATION
5.3.12 Operati on Latency
Load and store operations have an operation latency of
th ree c yc le s, r e ga r dl es s of th e siz e of the da ta t ra ns f er .
5.3.13 MMIO Register References
Memory operations that reference MMIO registers are
not cache d, and the CPU is stalled until the MMIO refer -
ence completes. A MMIO register reference occurs when
an address is in the range:
[MMIO_BASE] ≤ address < ([MMIO_BASE] + 0x200000)
The size of the MMIO aperture is hardwired at 2 MB.
5.3.14 PCI Bus References
Any CPU memory operation that references an address
outside the SDRAM and MMIO address apertures is as-
su m ed to r eference a de vice or memor y on the PC I bus.
PCI-bus data transfers are not cached, and the CPU is
s talled until the PCI t r ansfer co mpletes.
5.3.15 CPU Stall Conditions
Th e dat a cach e caus es the C PU to st all wh en :
1. Any cache miss occu rs.
2. Two s imultaneo usly iss ued, cac heable m emory o per -
at ions need to acc ess the sa me cache bank (bank
conflict).
3. An access that references an address in the MMIO
apertu re is is s ue d.
4. An ac c es s to the PC I bus i s is su ed .
5. A n on -trivial co pyba ck or i nvali da te op er at ion is is -
sued.
6. An access to the non-cacheable region in the DRAM
apertu re is is s ue d.
5.3.16 Data Cache Initialization
When PNX1300 is reset, the data cache executes an ini-
tialization sequence. The cache asserts the CPU stall
sign al whil e it se que nti ally reset s all v alid an d dirty bi ts.
The cache de-asserts the stall signal after completing the
initialization sequence.
5 .4 IN STR UC TIO N CACHE
The instruction cache stores compressed CPU instruc-
tions; instructions are decompressed before being deliv-
ered to the CPU. T he following sections describe the in-
struction cache and its operation; Table 5-11
summarizes instruction-cache characteristics.
5.4.1 General Cache Parameters
The PNX1300 instruction cache is 32 KB in size w ith a
64- byte block si ze . Thus, t he ca che co n tain s 512 blocks
ea ch wi th i ts ow n ad dre ss t ag. The c ach e i s 8 -wa y s et-
associative, so there are 64 sets, each containing 8 tags.
A si ngle valid bi t is ass ociate d with a bloc k, so each block
and associated addr ess tag is either entirely valid or in-
va lid; o n a cac he mi ss, 6 4 by tes a re re ad fr om SD RAM
to m ake the enti re block valid.
The geometry of the instruction cache is available to soft-
ware by reading the MMIO register IC_PARAMS.
Figure 5-8 shows the format of the IC_PARAMS register;
Table 5-12 lists its field values.
The product of the block size, associativity, and number
of sets g ives t h e total cac he s ize ( 32 KB in this case).
5.4.2 Address Mapping
PNX1300 instruction addresses are mapped onto the
data cache storage structure as shown in Figure 5-9. An
instructi on a ddres s is p a rtiti oned into three fields as de-
scribed in Table 5-13
Table 5-11. Instruction cache charact eristics
Characteristic PNX1300 Implementation
Ca che size 32 K B
Ca che associativi ty 8-way set-associ ative
Block size 64 bytes
Valid bits One valid bi t per 64-byte blo ck
Replacement policy Hierarchical LRU (least-recently used)
among the eight blocks in a set
Operation latency Branch delay is three cycles
Coherency enforce-
ment Software uses a special operation to
enforce cache cohere ncy
Cache locking Up to 1/2 (four out of eight blocks of
each set) of the cache contents can be
locked; granularity is 64 b ytes
Table 5-12. IC_PARAMS field values
Field N am e Value
BLOCKSIZE 64
ASSOCIATIVITY 8
NUMBER_OF_SETS 64
31 0371115192327
IC_PARAMS (r/o)0x10 0020 ASSOCIATIVITY NUMBER_OF_SETS
MMIO_BASE
offset:
BLOCKSIZE
Figure 5-8. Format of the instruction-cache parameters register.
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-9
5.4.3 Miss Processing Order
When a miss occurs, the instruction cache starts filling
the requested block from the beginning of the block. T h e
DSPCP U is stalled until the en tire block is fetched a nd
st ore d in th e ca ch e.
5.4.4 Replacement Policy
The hierarchical LRU replacement policy implemented
by the instruction cache is identical to that implemented
by the da ta cach e. See Section 5.3.4, “Re placement Pol-
icies, Coherency,” for a description of the hierarchical
LRU algorithm.
5.4.5 Location of Program Code
All program code must first be loaded into SD R AM . The
instruction cache cannot fetch instructions from other
memories or devices. In particular, the cache cannot
fetch code from on-chip devices or over the PCI bus.
5.4.6 Branch Units
Th e ins t ruction cache is clo sely coupled to three branch
units. Each unit can accept a branch independently, so
th ree br anches ca n b e pro ces sed s imultan eous ly in t h e
same cycle.
Branches in PNX1300 are called ‘delayed branches’ be-
cause the effect of a successful (taken) branch is not
seen in the fl ow of co ntrol unti l som e numb er of cyc les a f-
ter th e s ucc ess f ul bra nch is ex ec ut ed. Th e numb er of cy-
cl es of l atency is calle d the br anch del a y. On PN X 1300 ,
the branch delay is th ree cycl es.
Although three branches can be executed simultaneous-
ly, correct operation of the DSPCPU requires that only
one branch be successful (taken) in any one cycle.
DSPCPU operation is undefined if more than one con-
current branch operation is successful.
Each branch unit takes four inputs from the DSPCPU:
the branch opcode, a guard bit, a branch condition, and
a branch target address. A branch is deemed successful
if and only if the opcode is a branch opcode, the guard bit
is TRUE (i.e., = 1), and the condition (determined by the
opcode ) is satisfied.
5.4.7 Coherency: Special iclr Operation
A progr am can exercise some cont rol over the operation
of th e i nstr u ct ion c ac he b y ex ec uting t he s pe ci al iclr op-
eration. This operation causes the instruction cache to
clear the valid bits for all blocks in the cache, including
locked blocks. The LRU replacement status of all bl ocks
is reset to its initial value. The CPU is stalled while iclr is
executing.
See Section 5.6, “Cache Coherency,” for fu r ther di scus-
si on o f coherenc y issu es.
5.4.8 Read ing Tags and Cache Stat us
The in struct ion cache supp orts r ead acce ss to i ts ta g and
s tatu s bits , but no t thr ough sp ecia l oper ation s as wit h th e
data cache. Since the instr uction cache and branch uni ts
can execute only resultless operations, access to the in-
st ructi on -cac he ta gs and stat us b its is impl emen ted us-
ing normal load operations executed by the DSPCPU
th at ref ere nce a sp ec ial r eg io n in th e MM IO ad dr e s s ap -
erture. The region is 64 KB long and starts at
MMIO_BASE. Instruction cache tags and status bits are
rea d-on ly; stor e op era t i on s to t h is re gi on have no e ffect .
MMIO operations to this special region are only allowed
by the D SP CPU, not b y any ot h er mas t er s of the on-chi p
data highway, such as external PCI initiators.
Programmer’s note: Tag and status information cannot
be read by PCI access, but only by DSPCPU access.
Tag and s tatus r ead cannot be sc hedu led in t he sa me cy-
cle with or one cycle after an iclr operation.
Reading A Tag And Valid Bit. To re ad th e tag an d valid
bit for a block in the in struction cache, a program can ex-
ecute a ld32 operation directed at the instruction-cache
region in the MMIO aperture. The top of Figure 5-10
shows the required format for the target address. The
most-s ignifican t 16 bi ts must b e equa l to MMIO _BASE ,
the least-significant 15 bits select the block (by naming
th e s et and se t mem ber) , a nd bit 1 5 mus t be set t o z e r o
to perform a tag read. Note that in PNX1300, valid set
numbers range from 0 to 63. Space to encode set num-
ber s 64 t o 511 is prov ided for future exte nsions.
A ld32 w ith an address as specified above returns a 32-
bit result with the format shown at the top of Figure 5-11.
Bi t 20 c ontains th e stat e of the va lid bi t, and the least-sig-
nif ican t 20 bits contain t he tag fo r the blo ck addr esse d by
the ld32.
Reading The LRU Bits. T o r ead th e L RU bits for a set in
th e in st r uc tio n c ac he , a prog r am ca n ex e cu te a l d3 2 op -
eration as above but using the address format shown at
the bo ttom of Figure 5-10. In thi s format , bit 15 i s set to
one to perform the read of the LRU bits, and the
tag_i_mux field is set to zeros because it is not needed.
Table 5-13. Instruction Address Field Partitioning
Field Address
Bits Purpose
Offs et 5..0 By te offset into a s et
Set 11..6 Selects one of the sets in the cache (one
of 64 in the case of PNX1300)
Tag 31..12 Compared against address tags of set
members
0
OffsetSetTag
31 561112
Instruction Cache
Address
Figure 5-9. Instruction-cache address partitioning.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-10 PRELIMINARY SPECIFICATION
Reading the LRU bits produces a 32-bit re sult with the
for mat shown at the bottom of Figure 5-11. The least-sig-
nif ican t ten b its contain t he stat e of the LR U bit s when the
ld32 was executed. See Section 5.6. 7, “L RU Bit Defini-
tions,” for a de s cr i ption of the LRU bits.
Note that the tag_i_mux and set fields in the address for-
mats of Figure 5-10 are larger than necessary for the in-
struction cache in PNX1300. These fields will allow fu-
ture implementations with larger instruction caches to
use a compatible mechanism for reading instruction
cache information. The tag_i_mux field can accommo-
date a cache of up to 16-way set-associativity, and the
set field can accommodate a cache with up to 512 sets.
For PNX1300, the following constraints of t he values of
these fields must be observed:
1. 0 ≤ tag_i_mux ≤ 7
2. 0 ≤ set ≤ 63
5.4.9 Cache Locking
Like the data cache, the in structio n cache allows up to
one-half of its blocks t o be locked. A locked block is nev-
er chosen as a victim by the replacement algorithm; its
contents remain undisturbed until the locked status is
c hange d e xp li ci t ly by sof tw are . T hus , on PNX1 30 0, up t o
16 K B of the ca ch e ca n b e us ed as a high-s pe e d inst ruc -
tion ‘ROM.’ Only four out of eight blocks in any set can be
locked.
The MMIO registers IC_LOCK_ADDR, IC_LOCK_SIZE,
and IC_LOCK_CTL—shown in Figure 5-12—ar e used to
define and enable instruction locking in the same way
that the similarly named data-cache locking registers are
used. Section 5.3.7, “Cache Locking,” descri be s th e de-
tails of cache locking; they are not repeated here.
Setting the IC_LOCK_ENABLE bit (in IC_LOCK_CTL) to
‘1’ c a us es th e follo w in g sequ enc e of ev en t s :
1. The ins t ruc t i on cac he invalid ates a ll block s in t h e
cache.
2. The ins t ruction cac he fe tc hes al l blocks in the lock
range (defined by IC_LOCK_ADDR and
IC_LOCK_SIZE) from main memory into the cache.
3. Cache locking is activ ated so that the locked blocks
c annot be victims of the replacement alg orithm.
The only diff erence betwe en this sequ ence and the ini -
tialization sequence for data-cache locking is that dirty
blocks (which cannot exist in the instruction cache) are
not writte n ba ck f irs t.
Programmer’s note: Programmers (or compilers) must
combine all instructions that need to be locked into the
si ng le li near in struction-lockin g ad dr e ss range.
The special iclr operation also removes locked blocks
from the cache. If blocks are locked in the instruction
cache, then instructi on cache l ocking shou ld be disabled
in software (by writing ‘0’ to I C_LOCK_CTL) before an
iclr operation is issued.
Lock ing shou ld not be enabled by PCI access es to the
MMIO register.
5.4.10 Instruction Cache Initialization and
Boot Sequence
Wh en PN X1 30 0 is res et, the i ns tr u c tion c ac he e xecute s
an initializ ation and p ro ces sor boot sequence. While re-
set is asserted, the instruction cache forces NOP opera-
tion to the DSPCPU, and the program counter is set to
the default value reset_vec tor. When reset is deassert-
ed, the initialization and boot sequence is as follows.
31 0371115192327
To Read Tag & Valid Bit
To Read LRU Bi ts SET
MMIO_BASE
10000
0
MMIO_BASE
TAG_I_MUX SET
00
00
Figure 5-10. Required address fo rmat for reading instructio n-cac he ta gs and status.
31 0371115192327
VALID
I-Cache Tag-Read Result F ormat
I-Cache Status-Read Result Format LRU00000000000
0000000000
000
0
00000000
TAG
Figure 5-11. Result formats for reads from the instruction-cache region of the MMIO aperture.
IC_LOCK_ADDR (r/w)0x10 0214 IC_LOCK_ADDRESS
IC_LOCK_SIZE (r/w)0x10 0218 IC_LOCK_SIZE
000000
000000
31 0371115192327
IC_LOCK_CTL (r/w)0x10 0210 000000000000000000000000000
IC_LOCK_ENABLE
MMIO_BASE
offset:
000000000
0000000000000000 00
reserved
Figure 5-12. Formats of the registers that control instructio n-cache locking.
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-11
1. The stall signal is asserted to prevent activity in the
DSPCPU an d data cache.
2. The valid bits for all blocks in the instruction cache are
reset.
3. At the c o mpletion of the block invalidation scan, the
stall signal to the DSPCPU and data cache are deas-
serted.
4. The DSPCPU begins normal operation with an in-
struction fetch from the address reset_vector.
Th e ini tia liza tion pro ces s ta ke s 51 2 cl ock cyc le s. Res et
sets reset_vector equal to DRAM_BASE so that program
execution starts at the initial value of DRAM_BASE. The
initial v alue of D RAM_BASE is determined as des cribed
in Section 5.2, “DRA M Aperture. ”
5.5 LRU ALGORITHM
When a cache miss occurs, the block containing the re-
quested da t a m ust be brought into the c ac he t o r epla ce
an existing cache block. The LRU algo rithm is responsi-
bl e for sele ct ing the re plac eme nt vi ctim b y s ele ctin g t he
least-rec ently -used block.
The 8-way set-associative caches implement a hierarchi-
c al LRU rep la ce men t algo r it hm a s fo ll ows. Ei gh t s et s a re
part itioned into fou r groups of two elem ents each. To se-
lect t h e LRU elem e nt :
•First, the LRU pair is selected out of the four pairs
using a fou r- way LRU algo r it h m.
•Second, the LRU element of the pair is selected
using a t wo- way LRU alg orit h m .
5.5.1 Two-Way Algorithm
The two-way LRU requires an administration of one bit
per pair of element s. On ev ery cache hi t to one of the tw o
blocks, the cache writes once to this bit (just a write, not
a read-modify-wri te). If the e ven-numb ered block is ac-
cessed, the LRU bit is set to ‘1’; if the odd-numbered
blo ck is acce ssed, the LR U bit is set to ‘0’. On a miss, the
cache replaces the LRU element, i.e. if the LRU bit is ‘0’,
the even numbered element will be replaced; if the LRU
bit is ‘1’, the odd num bered ele ment will be replaced.
5.6 CACHE COHERENCY
The PNX1300 hardware does not implement coherency
between the caches and main memory. Generalized co-
herency is the responsibility of software, which can use
the special ope rations dcb, dinvalid , and iclr to enforce
c ach e/ memory synchroni zation.
5.6.1 Exam ple 1: Data-Cache/Input-Unit
Coherency
Bef o re t he CPU co mma nds t he video -in unit to captu r e a
vi deo fra me , the C PU m ust b e sure that th e da ta cac he
contains no blocks that are in the address region that the
v ideo-in unit wil l use to store the input frame. If th e vide o-
in unit performs its input function to an address region
and the data cac he d oe s ho ld on e or m or e blo cks fr om
that region, any of the followi ng may happen:
•A miss in the dat a cache may cause a dirty block to
be copied back to the address region being used by
the video-in unit. If the video-in unit already stored
data in the blo c k, the write-ba ck will corrupt the frame
data.
•The CPU will read stale data from the cache instead
of from the block in main memory. Even though the
video-in unit stored new video data in the block in
main memory, the cache contents will be used
instea d be ca us e it is still vali d i n the c a che.
To prevent erroneous copybacks or the use of stale data,
the CPU must use dinvalid operations to invalidate all
blocks in the address region that will be used by the VI
unit.
5.6.2 Example 2: Data-Cache/Output-Unit
Coherency
Before the CPU commands the video-out unit to send a
frame of video, the CPU must be sure that all the data for
the frame has been written from the data cache to the re-
gion of mai n me mory th at the video-out unit will output.
Explicit action is necessary because the data cache—
with its copyback write policy—will hold an exclusive
c opy of the data until it is e ither replac ed by the LRU al-
gorithm or the CPU explicitly forces it to be copied back
to main memory.
Before an output command is issued to the video-out
unit , th e CPU mu st exec ut e dc b ope rat ions to for ce co-
herency between cache contents and main memory.
5.6.3 Exam ple 3: Instruction -Cache/Data-
Cache Coherency
If code prepared by a program running on t he C PU mu st
be subsequently executed, coherency between the in-
st ructi on an d dat a cac hes mu st be enfo rce d. This is a c-
co m plis h e d by a tw o- step proc es s:
1. Coherency between the data cache and main memo-
ry must be enforced since the instruction cache can
fetch instructions only from main memory.
2. Coherency between the instruction cache and main
memory is enforced by executing an iclr operation.
The CPU will now be able to fetch and execute the new
instructions.
5.6.4 Example 4: Instruction-Cache/Input-
Unit Coherency
When an input unit is used to load program code into
main memory, the iclr operation must be issued before
attempting to execute the new code.
5.6.5 Four-Way Algorithm
For administration of the four-way algorithm, the cache
maintains an upper-left tr iangular mat rix ‘R’ of 1-bit ele-
ments without the diagonal. R contains six bits (in gener-
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-12 PRELIMINARY SPECIFICATION
al, n×(n–1)/2 b it s fo r n-w a y L R U) . If set elem ent k i s re f-
ere nced, th e ca che s e ts ro w k to ‘1’ a nd column k to ‘0’:
R[k, 0..n–1] ← 1,
R[0..n–1, k] ← 0
The LRU element is the one for which the entir e row is ‘0’
(or empty) and the entire column is ‘1’ (or empty):
R[k, 0..n–1] = 0 and R[0..n–1, k] = 1
For a 4-way set-associative cache, this algorithm re-
quires six bits per set of four cache blocks. On every
cache hit, the LRU info is updated by setting three of the
six bits to ‘0’ or ‘1’, depending on the set element that
was accessed. The bits need only be written, no read-
modify-write is necessary. On a miss, the cache reads
the six LRU bits to determine the replacement block.
PNX1300 combines the two-way and four-way algo-
rit hms i nto an 8-w ay h ierar ch ical L RU algo rith m. A t otal
of te n a dmin is tra ti on bi ts a r e re qui red : six to m ai ntai n th e
four-way LRU plus four bits maintain the four two-way
LRUs.
The hierar chical algorit hm has performance close to full
eight-way LRU, but it requires far fewer bits—ten instead
of 28 bit s—and is much simpler to implement.
To update the LRU bit s on a cach e hit to e lemen t j ( with
0 <= j <= 7), the cache applies m = (j div 2) to the four-
way LRU administration and (j mod 2) is applied to the
two-way administration of pair m. To select a replace-
ment victim, the cache first determines the pair p from
the fou r- way LR U a nd then retr i eve s th e L RU bit q of pair
p. The overall LRU element is the p×2+q.
5.6.6 LRU Initialization
Re set cause s th e LRU ad mini st rat i on b its to in itia l iz ed t o
a legal state:
R[1,0] ← R[2,0] ← R[3,0] ← 1
R[2,1] ← R[3,1] ← R[3,2] ← 0
2_way[3] ← 2_way[2] ← 2_way[1] ← 2_way[0] ← 0
5.6.7 LRU Bit Definitions
The ten LRU bits per set are mapped as shown in
Figure 5-13. This is the format of the LRU field as re-
turned by the special operation rdstatus for the data
cache and a ld32 from MMIO space (see Section 5.4.8,
“Reading Tags and Cache Status”) for the instruction
cache.
5.6.8 LRU for the Dual-Ported Cache
For the PNX1300 dual-ported data cache, two memory
operations to the same set are possible in a single clock
cycle. To support this concurrency, two updates of the
LRU bits of a sing le s et mus t be pos s ib le .
The following rules ar e used by PNX1300:
1. LR U bi ts th at are ch ange d by e xa ctly one port recei ve
the value according to the algorithm described above.
2. LRU b its t h at are chan ge d b y bot h ports rece ive a va l-
ue a s i f the algorithm were first applied for the access
in port zero and then for the access in port one.
5.7 PERFORMANCE EVALUATION
SUPPORT
Th e cach es im plem ent su pp ort for p erf orma nce ev alua -
tion. Several events that occur in the caches can be
counted using the PNX1300 timer/counters, by selecting
the source CACHE1 and/or CACHE2, as described in
Section 3.8, “Timers.” Two different events can be
tracked simultaneously by using 2 timers.
The MMIO register MEM_EVENTS determines which
events are counted. See Figure 5-14 for the format of
MEM_EVENTS. Table 5-14 l ists the even ts that ca n be
tracked and the corresponding values for the
MEM_EVENTS fields. Event 1 selects the actual source
LRU bit 0
R[3,1] R[3,0]R[3,2]R[2,0]R[1,0] R[2,1]2_way[1] 2_way[0]2_way[3] 2_way[2] LRU bit 1LRU bit 2LRU bit 3LRU bit 4LRU bit 5LRU bit 6LRU bit 7LRU bit 8LRU bit 9
Figure 5-13. LRU bit definitions; 2_way[k] is the two-way LRU bit of pair k = (j div 2) for set element j.
31 0371115192327
MEM_EVENTS (r/w)0x10 000C 0Event2
MMIO_BASE
offset:
00000000000000000000000 Event1
Figure 5-14. Format of the memory_events MMIO register.
Philips Semiconductors Cache Architecture
PRELIMINARY SPECIFICATION 5-13
for the TIMER CACHE1 source. Event2 selects the
so urce for T IME R C A CHE 2.
If the memory bus is available:
•On re ad data cache miss the minimum waiting time is
12 SDRAM clock cycles, if critical word first is
granted by the Main Memory Interface (MMI). If not,
th en d ata ca che wai ts fr om 12 to 18 SD RAM cy cles
(16 SDRAM cycles are required to fetch 64 bytes
from SDRAM.
•On write data cache miss, the missing line needs to
be fetched, thus it implies the same SDRAM cycles
as a read data cache miss. If the victimized cache
li ne is di rt y, t he cach e li ne is c opie d back to m emo r y
after the read of the missing line is done and thus
does n ot add extr a sta ll c yc le s.
•Prefetch delay is the same as read data cache if
mem or y bu s is avail able. As a rem inde r th e pr efetch
may be d isc arded if th e data cache state machin e i s
“full”, and there is a 3 stall cycle penalty when the
prefetch is issued.
5.8 MMIO REGISTER SUMMARY
Table 5-15 lists t he MMI O regi sters t hat perta in to the o p-
eration of PNX1300’s inst ruction and data caches.
Tab l e 5-1 4. Track ab le c ache- p er for ma nce events
Encoding Event
0 No event counted
1 Instruction-cache misses
2 Instruction-cache stall cycles (including data-
cache stall cycles if both instruction-cache and
data-cach e are stalled simulta neously)
3 Data-cache bank conflicts
4 Data-cache read misses
5 Data-cache write misses
6 Data-cache stall cycles (that are not also instruc-
tion-cache stall cycles)
7 Data-cache cop yback to SDRAM
8 Copyback bu ffer full
9 Data-cache write miss with all fetch units occu-
pied
10 Data cache stream miss
11 Prefetch operation sta r ted and n o t discar ded
12 Prefetch operation discarded (because it hits in
the cache or there is no fetch unit available)
13 Prefetch operation discarded (because it hits in
the cache)
14–15 Reserved
Table 5-15. MM IO register summary
Name Description
DR AM_BASE Sets location of the DRAM apertur e
DR AM_LIMIT Set s size of t he DRAM aperture
DRAM_CACHEABLE
_LIMIT Divides DRAM aperture into cache-
able and no n-cacheable porti ons
MEM_EVENTS Selects which two events will be
counted by timer /counter s
DC_LOCK_CTL Data-cache locking enable and aper-
ture control
DC_LOCK_ADDR Sets low address of the data-cache
addre ss lock apertur e
DC_LOCK_SIZE Sets size of the data-cache address
lock aperture
DC_ PARA MS Read-only r egis ter wi th dat a-cache
paramet er infor mat ion
IC_ PARAMS Read-only r egis ter wi th instructi on-
cache parameter information
IC_LOCK_CTL Instruction-cache locking enable
IC_LOCK_ADDR Sets low address of the instruction-
cache address lock aperture
IC_LOCK_SIZE Sets size of the instruction-cache
addre ss lock apertur e
MMIO_BASE Sets location of the MMIO aperture
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
5-14 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 6-1
Video In Chapter 6
by Gert S lavenb urg
6.1 VIDEO IN OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The Video In (VI) un it provides the following functions:
•Digital video input from a digital camera or analog
camer a (us ing a vi deo dec o der ).
•High-bandwidth (81 MB/sec) raw input data channel.
•Direct 8-10 bit interface for video A/D converters at
up t o 81-MHz sample rate.
•Receiver port for PNX1300-to-PNX1300 unidirec-
tional message passing
The VI unit operates in one of the modes per Table 6-1.
Digital video input is in YUV 4:2:2 with 8-bit resolution
multiplexed in CCIR656 format1 from a digital camera or
CCIR656-capable video decoder (such as the Philips
SAA7111 or SAA7113), across an 8-bit-wide interface.
Resolutions up to CCIR601 are accepted at 50 or 60
fields per second. A programmable rectangular image is
captured from a video frame and written in pla nar fo rm at
to PNX1300 SDRAM. The video camera or decoder can
be programmed using the PNX1300 I2C bus. In fullres
capture mode, luminance (Y) and chrominance (U, V)
pass unmodified. In halfres capture mode, luminance
and ch rom ina nce ar e horiz ont all y deci mat ed by a fac to r
of two to convert to CIF-like resolution with YUV 4:2:2 or
MPE G sampl ing rul es. If ver tical subsampl ing on chr omi-
nan ce is de sir ed , it ca n be pe rfo rmed by soft w a re on the
DS PCPU or by the on-chip im age coprocessor (ICP).
Whe n o pe rat in g a s ra w inpu t da ta ch anne l, VI acc ep ts 8-
bit-wi de data. The operation mo de is raw8 capture. No
data selection or data interpretation is done. Data is writ-
ten in pa cked form, four byt es to a w ord, to local SDRAM .
Th ere is no h ard ware con trol ov er the r ate at wh ich the
source sends data. Instead, VI maintains two pointer/
counter registers to ensure that no data is lost when the
local SD R AM memory bu f fer f ills. D at a is accepted at the
clock of the sender. If desired, VI_CLK can be pro-
grammed as an o utput to drive the data tr ansfer a t a pro-
gra m ma ble r at e.
VI can accept raw data from up to 10-bit A/D converters,
at sampling rates up to 81 MHz. VI can operate in raw8,
raw10u, or r aw 10s ca ptur e mode for eight-bit, unsigned
10-bit or signed 10-bit data. In the 10-bit modes, data is
zero- or sign-extended to 16 bits an d stored in p acked
for m in loca l S DR AM. As wi th the raw8-capture mo de , VI
mai nt ai ns two p oi nter /co un t er re gist e rs to ensure tha t no
data is lost when the local SDRAM memory buffer fills.
Data is accepted at the externally set sampling rate. If
desired, VI_CLK can be programmed as an output to
serve as a progr ammable sampling clock.
VI can act as receiver from the Enhanced Video Out
(EVO) unit of another PNX1300. One EVO unit can
broadcast to multiple receiving VIs. In this message
passing mode, no data selection or data interpretation is
done. Each message of the sender is written as byte-
packed data to a separate local SDRAM memory buffer.
Message start and end is indicated by the sender. The
receiving VI will accept data until the sender indicates
message end or until the current memory buffer is full. If
the memory buffer fills before message end is encoun-
tered, the received data is truncated and an error condi-
tion is r ais ed.
6.1.1 Interface
Besides the VI-spe cific pins in Table 6-2, t he PN X1300
I2C interface is typically used to control the external cam-
era or video decoder.
Figure 6-1 through Figure 6-4 illustrate typical connec-
tions for commonly used external sources. Note that
VI_DVALID is only used in special circumstances, e.g.
when sending data through a channel that results in
cloc k pe r io ds bo th with a nd wi thout data tr an sfers.
Tabl e 6 -1 . VI un it mode sel ec tion .
Mode Function Explanation
0000 fullres capture YUV 4:2:2 capture, no decimation
0001 halfres capture YUV 4:2:2 capture, decimate by 2
0010 raw8 capture raw 8-bit data capture, pack 4
bytes to a word
0011 raw10s capture raw 10-bit data capture, sign
extend to 16 bits, pack 2 to a word
0100 raw10u capture raw 10-bit data capture, zero-
extend to 16 bits, pack 2 to a word
0101 message pas sing mes sage recep tion fr om EVO
0110
..
1111
Reserved
1. Refer to CCIR recommendation 656: interfaces for dig-
ital component video signals in 525-line and 625-line
television systems. Recommendation 656 is included in
the Philips Desktop Video Data Handbook.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-2 PRELIMINARY SPECIFICATION
6.1.2 Diagnostic Mode
The VI logic can be set to operate in diagnostic mode,
wh ic h c on ne cts th e i n pu ts of VI to the o utp ut s of the EV O
unit. This mode provides boot diagnostics with the ability
to verify major operational aspects of the chip before
handing contr ol t o an op e rating syste m .
Diagnostic mode is entered by writing a control word with
a ‘1’ in t he DIAG MODE bi t posi tion to the V I_CT L regi ster
(see Figure 6-11). The EVO unit has to be setup to pro-
vide a clock before starting DIAGMODE. After a VI s oft-
ware reset, the DIAGMODE bit has to be set back to ‘1’.
In diagnostic mode, the VI signals are exactly as shown
in Figure 6-2, exce pt that the inputs come from the on-
chip EVO uni t. Note that t he in puts are truly taken fr om
the PNX1 300 EV O exte rnal pi ns, i.e. if an e xter nal (boa rd
level) sour c e is dr ivi ng EVO pi ns , diagnos tic mode is not
ca pa b le of test i ng th e E VO u ni t.
Note that the diagnostic mode only controls an input mul-
tiplexe r. VI can be prog r ammed and operated in all usual
modes. The raw modes are particularly attractive for di-
agnostics purposes, since they allow VI to operate al-
most as an on-chip logi c a nal yze r.
6.1.3 Power Down and Sleepless
The VI uni t e nter s power down stat e whene ver PNX130 0
is put in global power down mode, except if the SLEEP-
LESS bit in VI_CTL is set. In the latter case, the block
continues DMA operation and will wake up the DSPCPU
whenever an interrupt is generated.
The EVO blo ck can be sepa r ate ly po wer e d dow n by se t-
ting a bi t in the BLO CK_P O WER _ DO WN regi st er. Re fe r
to Chapter 21, “Power Management.”
It is rec ommended that the EVO unit be stopped (by ne-
gating VI_CTL.CAPTURE_ENABLE) before block-level
power down is started, or that SLEEPLESS mode be
used when global power down is activated.
6.1.4 Hardware and Software Reset
Video In is reset by a PNX1300 hardware reset (pin
TRI_RESET#) or by a VI software reset. The latter is ac-
complished by writing a control word of 0x00080000 to
the VI_CTL register. After a software reset, allow for 5
video clock cycles delay before enabling VI capture.
Upon hardware or software reset, the VI_CTL,
VI_STATUS, and VI_CLOCK registers are set to all ’0’s.
The state of the other registers after RESET is unde-
Tabl e 6 - 2. VI un it interfac e p ins
VI_CLK I/O-5 •If configured as input (power up
default): a positive transition on this
incoming video clock pin samples
all othe r VI_DATA inpu t signals
below if VI_DVALID is HIGH. If
VI_DVALID is LOW, VI_DATA is
ignored. Clock and data rates of up
to 81 MHz are supported. PNX1300
supports an additional mode where
VI_DATA[9:8] in message passing
mode ar e not affected by the
VI_DVALID signal, Section 6.6.1.
•If configured as output: programma-
ble output clock to drive an external
video A/D converter. Can be pro-
grammed to emit integral dividers of
DSPCPU_CLK.
•See Section 6.2 for clock program-
ming details.
VI_DVALID IN-5 VI_DVALID indicates that valid data is
present on the VI_DATA lines. If HIGH,
VI_DATA will be accepted on the next
VI_CLK positive edge. If LOW, no
VI_DATA will be sampled. PNX1300
supports an additional mode where
VI_DATA[9:8] in message passing
mode are not affected by the
VI_DVALID signal, Section 6.6.1.
VI_DATA[7:0] IN-5 CCIR656 style YUV 4:2:2 data from a
digital camera, or general purpose
high speed data input pins. Sampled
on positive transitions of VI_CLK if
VI_DVALID HIGH.
VI_DATA[9:8] IN-5 Extension high speed dat a input bits to
allow use of 10-bit video A/D convert-
ers in raw10 modes. VI_DATA[8]
serves as START and VI_DATA[9] as
END message input in message pass-
ing mode. Sampled on positive transi-
tions of VI_CLK if VI_DVALID HIGH.
PNX 1300 supports an addit ion al mode
where VI_DATA[9:8] in message pass-
ing mode are not affected by the
VI_DVALID signal, Section 6.6.1.
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-3
fined. Note that the VI clock has to be present while ap-
plyi ng th e so ftware r eset.
DATA[7:0]
CLOCK
SDA, SCL GND Cable Connector
VI_DATA[7:0]
VI_DVALID
VI_CLK
VSS
SDA, SCL
PNX1300
logic ‘1’
VI_DATA[9:8]
GND
Termination &
Receivers
I2C bus 2
Figure 6-1. VI connected to an 8-bit CCIR656 digital camera.
VI_DATA[7:0]
VI_DVALID
VI_CLK
PNX1300 2
logic ‘1’
VI_DATA[8]
VI_DATA[9]
VO_DATA[7:0]
VO_CLK
(S TM S G ) V O _I O 1
( EN D MS G) VO _ I O2
PNX1300 1
Figure 6-2. VI unit connected to an EVO unit of another PNX1300.
VI_DATA[7:0]
VI_DVALID
VI_CLK
IIC_SCL
IIC_SDA
PNX1300
logic ‘1’
VI_DATA[9:8]
GND
VPO[15:8]
LLC
SCL
SDA
SAA7111
Analog video
1–2 S-VHS Y/C
1–4 CVBS
To other I2C devices
I2C bus
24.576 MHz
Figure 6-3. VI unit connected to a video decoder.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-4 PRELIMINARY SPECIFICATION
6.2 CLOCK GENERATOR
The VI block can operate in two distinct clocking mode s,
as controlled by the VI_CLOCK control register (see
Figure 6-11).
SELFCLOCK = 0: ‘External clocking mode’. Th is is the
most common mode of operation. In this mode, the
VI_CLK pin is an asynchronous clock input . All other in-
puts are sampled on positive edges of the VI_CLK clock
si gn al. On-chip syn chronize r s en sure r e liable as ynchro-
nous capture. This mode can be combined with DIAG-
MODE, in which case the EVO clock acts as the asyn-
chronous clock source. In external clocking mode, the
value of DIVIDER is ignored.
SELFCLOCK = 1: ‘Internal clocking mode”. This
mode is typi cally in tended for use with ex ternal A/ D co n-
verters or other sources that require a clock. In this
mode, VI_CLK is an output pin. Positive edges of
VI_C LK are us ed to sa mp le all oth e r inputs. The gener-
at ed cl ock freq uenc y ca n be pro gram med u sin g th e DI -
VIDER field in t he VI_CLOCK register.
On RESET, VI_CLOCK is set to zero, i.e. external cl oc k -
ing mode is the de fault wi t h D IV IDE R i gnored.
6.3 FULLRES CAPTURE MODE
In fu llres capture mode, the VI unit receives all three vid-
eo co mpon en ts Y, U , and V , as wel l as synchroni zat ion
information (SAV and EAV codes) on the VI_DATA[7:0]
pins in CCIR656 format. See Figure 6-8. The three video
components Y, U, and V are separated into three differ-
ent streams. Each component is written in packed form
into s epa rate Y, U, a nd V buffe rs in the SD RA M . This is
commonly called a planar format1 (see Figure 6-10).
Th e CC IR 6 56 s t a nd ard spec ifie s t h at the camera h as t o
obey the sampling rules illustrated in Figure 6-5. VI is ca-
pab le of chromi nanc e resam plin g, an d can produc e sam-
pl es in memo r y in t w o w a ys:
VI_CTL.SC=0. ‘Co-sited sampling’ places luminance
an d ch romi nanc e s ampl e s i n me m or y wi t h ou t any mo di -
fi cati on. Hen ce, a plan ar format resu lts with samp ling po-
si tion s as pe r c o-sited luminanc e and ch r om inanc e Y UV
4:2:2 convention.
VI_DATA[9:0]
VI_DVALID
VI_CLK
PNX1300
logic ‘1’
Analog video 10-bit Video A/D
Figure 6-4. VI connected to a 10-bit video A/D converter.
fVICLK fDSPCPU
DIVIDER
------------------------=
1. The planar fo rm at is most suitable as input to software
compres sion al gorithms.
Chromi nance (U,V)
samples Luminance
samples
Figure 6-5. Camera YUV 4:2:2 sampling (co-sited luminance/chrominance).
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-5
VI_CTL.SC=1: ‘Interspersed sampling’ serves to gen-
erate a sampling structure in memory where chromi-
nance samples are spatially midway between luminance
samples, as shown in Figure 6-6. This ‘interspersed’ for-
mat is suitable for use in MPEG-1 encoding.
Th e VI hardwa r e a pp lie s a (–1 13 5 –1)/16 filter as illus-
trated in Figure 6-6 to the chrominance samples before
writing them to memory. This filter computes chromi-
nance values at sample points midway between lumi-
nance samples1. Computed video data is clamped to
01h if the filter result is less than 01h and clamped to FFh
if greater than FFh. Interspersed data format is preferred
by some video compression standards. The MPEG-1
standard, for example, requires YUV 4:2:0 data with
chrominance sampling positions horizontally and verti-
call y midway betwee n luminan ce samp les. This can be
achieved from the horizontally interspersed sampling for-
YUV 4:2:2 CCIR656
input samples
abcdefghi jkl
abcdefghi jkl
Resampled sample
values
Yg'Yg
=
Uef U–c13Ue5UgUi
–++()16⁄=
Vef Vc
–13Ve5VgVi
–++()16⁄=
Figure 6-6. Chrominance re-sampling to achieve interspersed sampling.
Active area
abcdefghi jdcb zu zv zw zx zy zz zy zx zwzs zt
• • •
Figur e 6-7. Filtering at the e dge of the act ive area.
Preamble
11111111 00000000 00000000 1FVHPPPP
Timing reference code
Protection bits
(error corr ecti on)
H = 0 for SAV
H = 1 for EAV
V = 1 during field blanking
V = 0 elsewhere
F = 0 during field 1
F = 1 during field 2
Figure 6- 8. Format of CCIR656 SAV and EAV timing reference codes.
Captured Image
START_X
WIDTH
HEIGHT
START_Y
Pixel 0 Pixel M–1Line 0
Line N –1
Figure 6-9. VI capture parameters.
1. All filters perform full precision intermediate computa-
tions and saturation upon gener at in g t he res ult bits.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-6 PRELIMINARY SPECIFICATION
mat by ver ti cal su bsamp ling wit h a (1 1) / 2 o r more so-
phisticated filter. Vertical filtering can be performed in
softw are using the DSPCPU’s efficient multimedia oper-
at ions or by hardw are in the o n- c hip IC P .
The filtering process exercises special care at the left
and right edges of the active area of the CCIR656 data
stream, as defined by the SAV, EAV code positions. See
Figure 6-7. Since no pixels exist to the left of the first pix-
el or to the right of the last pixel, filt ering can result in ar-
tifacts. To minimize artifacts, the image is extended by
mir rori ng pi xels arou nd the le ft-mo st an d righ t-most pixe l.
Not e that the im ag e i s m i r ror e d a r ou n d pi x el ‘a’, the first
pixel after the SAV code and around pixel ‘zz’, the last
pixel before the EAV1 code. Pixel ‘a’ in Figure 6-7 is the
(chroma, luma) pair defined by the first three camera
byte s of th e U YVYUY V Y ... stream after SAV.
Refer to Figure 6-11 for an overview of the memory
mapped I/O (MMIO) registers that are used to control
and observe the operation of VI in fullres capture mode.
To ensure compatibility with future devices, any unde-
fi ned MMI O bit s should be igno red when r ead and w rit ten
as’0’s.
Upon har dware or software reset (Se ctio n 6. 1.4, “Hard-
ware and Software Reset”), the VI_CTL, VI_STATUS,
and VI_CLOCK registers are set to all zeros.
At any point in time, the V I _STATUS register fields (see
Figure 6-11) indicate the current camera status:
•CUR_X: The pixel index (0 to M–1) of the most
recently received camera pixel. CUR_X gets set to
zero for the first pixel following receipt of a SAV
code2, and incremented on every valid Y sample
rec e ived ther e aft er.
•CUR_Y: The line index (0 to N–1) within the current
field of the camera line that is currently being
received. CUR_Y gets set to zero upon receipt of a
nega ti ve ed ge of V, i.e., upon the first SAV code con-
taining V= 0 after one or more SAV codes containi ng
V=1. This is equiv alent to the first line after the end of
vertical retrace. CUR_Y gets incremented upon
ever y su cce ssive S AV code.
•FIELD2: Indicates whether the field currently being
received is a field1 or 2. This flag gets updated based
on the F field of every received SAV code. Note that
field1 is the ‘top’ field, i.e. the field cont ainin g the top-
most visible line. Field1 contains lines 1,3,5 etc.
Fi eld2 contains line s 2,4,6,8 etc.
Table 6-3 illustrates common digital camera standards
and th e num ber of act ive pix els per lin e, line s per f ie ld ,
and fields per second. Note that any source is accept-
able t o VI, as long as the maximum VI_ CLK rate is not
exceeded.
Figure 6-9 shows the details of an incoming field and the
captured image. The incoming field consists of N hori-
zontal li ne s , eac h li ne ha vi ng M p ix el s labeled 0 through
M–1. Lines are numbered from 0 through N–1. The ca p-
tu red im age i s a su bset of th e inc omi ng im age. I t is de-
fin ed b y t he captu r e par am e t e r s ( S T ART_ X, S T ART_Y ,
WIDTH, HEIGHT) held in the VI_CAP_START and
VI_CAP_SIZE MMIO registers (see Figure 6-11).
•START_ X: de f in es the start i ng pixel n um be r (X -coo r -
dinate of th e starting pixel) . START _ X mu s t be even,
and greater than or equal to ‘0’.
•START_ Y: de fin es th e s t a r ting li ne num b er ( Y-coo r di -
nat e of the st a rti ng p ix el). START_ Y must be grea te r
than or equal to ‘0’.
•WIDTH: Defines the width of the captured image in
pixels. WIDTH must be ev en.
•HEI GH T: Defi nes th e he ight of th e ca ptur e d im ag e in
lines.
Image capture starts after the following conditions are
met:
•VI_CTL.CAPTURE ENABLE is asserted.
•VI_STATUS.CAPTURE COMPLETE is de-asserted,
indicating that any previously captured image has
been acknowledged.
•CUR_Y = START_Y occurs.
Once image capture is started, H EIGHT ‘lines’ are cap-
tu red . Ea c h lin e ca pt ur e s tar t s if:
•The previous line capture, if any, is completed.
•CUR_X = STAR T_X
Onc e line c aptu re st arts, it co ntinu es f or 2* WIDT H p ixel
clocks3 in w hic h VI _DV ALID is as serte d, irresp e ctiv e of
the presenc e of one or mo re EAV codes.
Note that capture continues regardless of any horizontal
or vertical retrace and associated C UR_Y or CUR_X re-
set. Th is pro vides s pecial app lica tions w ith t he abil ity t o
capture information embedded inside the horizontal or
vertical blanking interval. If it is desirable to capture pix-
els in the horizontal blanking interval, a minimum time
separation of 1 µs is requ i red b etw ee n the l ast pixel ca p-
tured on line y and the first pixel captu red on line y+1. An
exc eptio n t o th is ru le is a ll ow e d if and on ly if t h e st or a ge
parameters below are chosen such that the last and first
1. EAV codes with multiple bit errors are accepted and en-
able the mirroring function.
2. Note that VI uses the SAV protection bits to implement
single error correction and double error d etection. An
SAV code with double error is ignored.
Table 6-3. Common video source parameters.
Video Source M
(# active pixels) N
(# active lines)
Field
Rate
(Hz)
CCIR601
50 Hz/625 lines 720 288 50
CCIR601
60 Hz/525 lines 720 240 60
square pixel
50 Hz/625 lines 768 288 50
square pixel
60 Hz/525 lines 640 240 60
3. Four clock s for each Cb,Y,Cr,Y group repr es enti ng tw o
lumina nce pixels
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-7
pixel end up in adjacent memory locations. Note that
blanking information capture only makes sense in fullres
mode with co-s ited sa mpli ng. Al l oth er mode s appl y filt er-
ing, which will distort the numeric sample values.
The captured image i s sto red in SD RAM at a lo cati on de-
fined by the storage parameters in MMIO registers
(Y_BASE_ADR, Y_DELTA, U_BASE_ADR, U_DELTA,
V_BASE_ ADR, V _DEL TA). Not e that th e ba se-address
registers force alignment to 64-byte boundaries (six
LSBs are always zero). T he default mem ory packing is
big-endian although little-endian packing is also support-
ed by setting the LITTLE_ENDIAN bit in the VI_ C TL reg -
ister.
•Y_BASE_ADR: The desired starting (byte) address
in SDRAM memory where the first Y (luminance)
sample of the captured image will be stored. This
address is forced to be 64-byte aligned (six LSBs
always ‘0’).
•Y_DELTA: The desired address difference between
the last sample of a line and the address of the first
sample on the next line. Note that the value of
Y_DELTA must be chosen so that all line-start
addr e s ses ar e 64-b yte aligned.
•U_BASE_ADR, U_DELTA, V_BASE_ADR,
V_ D ELTA: Sam e func t i on s a nd al ignm ent re st r i ctio ns
as above, but for chrominanc e-component sample s.
Horizontally-adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
sample s are pack ed into on e 32-bit wor d). Upon horizo n-
tal retrace, pixel storage addresses are incremented by
the corresponding DELTA to compute the starting byte
add r ess for th e ne xt lin e. Note t ha t DELT A is a 16-bi t u n-
signed quantity. This process continues until HEIGHT
lin es of WIDT H sa mple s ha ve been store d i n memo r y for
luminance (Y). For chrominance, HEIGHT lines of half
the WIDTH are stored1. See Figure 6-10.
Modifications to Y_BASE_ADR, U_BASE_ADR and
V_BASE_ ADR have n o ef fect until th e sta rt of nex t cap-
ture, i.e. VI hardware maintains a separate pointer to
track the current address. Modifications to Y_DELTA,
U_DELTA and V_DELTA do affect the next horizontal re-
trace. Hence, under normal circumstances, the DELTA
variables should not be changed during capture.
When capture is complete, i.e. any internal VI buffers
have been flushed and the entire captured image is in lo-
cal SDRAM, VI raises the STATUS register flag CAP-
TURE COMPLETE. If enabled in the VI_CTL register,
th is eve nt cause s a D SPCPU i nt e r r u pt to be r equ ested.
The programmer can determine whether the captured
image is a field1 or field2 by inspection of the FIELD2 flag
in VI_STATUS. Note tha t the FIELD2 flag changes at the
start of the vertical blanking interval of the next field.
The CAPTURE COMPLETE flag is cleared by writing a
word to VI_CTL with a ‘1’ in the CAPTURE COMPLETE
ACK bit position. This action has the following effect:
•it tells the hardware that a new Y,U, and V DMA buffer
is available (or the old one has been copied)
•it clears the CAPTURE COMPLETE flag
•it tells VI to capture the next image
The user can program t he Y_THRESHOLD field to gen-
erate pre-completion (or post-completion) interrupts.
Whenever CUR_Y reaches Y_THRESHOLD, the
THRESHOLD REACHED flag in the STATUS register is
set. If enabled in the VI_ CTL re gi ster, th is event causes
a DSPCPU interrupt request. The THRESHOLD
REACHED flag is cleared by writing a word to VI_CTL
with a ‘1’ in the THRESHOLD REACHED ACK bit posi-
tion. Note that, due to internal buffering in the VI u nit, it is
NOT gu ara nt ee d tha t all s ample s f rom l i ne s up to and i n-
1. Note that consecutive pixel components of each line
are sto red in cons ecutive memo ry addresses but con-
secutive line s need no t be in con secutive memor y ad-
dresses
WIDTH pixels
HEIGHT lines
pix0 pix1 pix2 pix
W–1
• • •
. . .
Y_BASE_ADR
WIDTH/2 pixels
HEIGHT lines
pix0 pix2 • • •
. . .
U_BASE_ADR
(Repeated for V_BASE_ADDR,
V_DELTA)
Y_DELTA
U_DELTA
Fig ure 6-10. VI YUV 4:2:2 planar memory format.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-8 PRELIMINARY SPECIFICATION
cluding CUR_Y have been written to local SDRAM upon
THRESHOLD REACHED. The implementation guaran-
te es a fixe d max imum tim e of 2 µs between raising the
interrupt and completion of all writes to SDRAM. The
THRESHOLD interrupt mech anism works regardless of
CAPTURE ENABLE. Hence , it can also be used to skip
a desired number of fields without constant DSPCPU
polling of VI_STATUS.
If VI i nter nal bu ffers ove rflow d ue to insu ffic ient intern al
data-highway bandwidth allocation, the HIGHWAY
BANDWIDTH ERROR condition is raised in the
VI _ST ATU S r eg is ter . If enab le d, this c auses assertion of
a VI interrupt request. Capture continues at the correct
mem ory addre ss as so on as t he intern al bu ffer s ca n be
written to memory, but one or more pixels may have
been lo st, an d the co rre spon di ng m emor y loc at ions are
not written. Th e HBE condition c an be cleared by wr iting
a ‘1’ to the HIGHWAY BANDWIDTH ERROR ACK b it i n
VI_CTL. Refer to Section 6.7, “Highway Latency and
HBE” for more information.
Any interrupt event of VI (CAPTURE COMPLETE,
THRESHOLD REACHED, HIGHWAY BANDWIDTH ER-
ROR) leads to the assertion of a single VI interrupt
(SOURCE 9) to the PNX1300 Vectored Interrupt Control-
ler. The interrupt handler routine should check the STA-
TU S re gister to dete rmine t he set of VI event s ass ociat ed
with the request. The vectored interrupt controller should
always be set to have VI (SOURCE 9) operate in level
sensitive mode. This ensures that each event is handled.
VI asserts the interrupt request line as long as one or
more enabled events are asserted. The interrupt handler
c lear s on e or mor e sel ec ted ev en ts by wr i ting a ‘1’ to the
cor resp on ding ACK f ie ld in V I_C TL. Th e cle ari ng of t he
las t eve nt leads t o immedi ate (nex t DSPC PU c lock e dge)
de- as s er tio n of the inte r rupt reque s t line t o the Vectored
Interrupt Controller. See Section 3.5.3, “INT and NMI
(Maska ble and Non-M askabl e Interrupts),” f or informa-
tion on how to program interrupt handler routines .
VI_STATUS (r )0x10 1400 31 0
MMIO_base
offset:
VI_CLOCK (r/w)0x10 1408
VI_CAP_START (r/w)0x10 140C
VI_CAP_SIZE (r/w)0x10 1410
CUR_Y(12) 371115192327
DIVIDER
START_Y
WIDTH
CUR_X(12)
FIELD2
Threshold reached Capture complete
VI_CTL (r/w)0x10 1404 Y_THRESHOLD MODE
Capture complete
INT enabl e
Threshold reached ACK
(write ‘1’ to ACK)
Ca pture comp lete ACK
Threshold reached
INT enable
SC (Sampling conventions)
0 ⇒ Co-sited
1 ⇒ Interspersed
Little endian
Capture enable
software RESET
DIAGMODE
SELFCLOCK
START_X
HEIGHT
VI_Y_BASE_ADR (r/w)0 x10 1414 Y_BASE_ADR
VI_U_BASE_ADR (r/w)0x10 1418 U_BASE_ADR
VI_V_BASE_ADR (r/w)0x10 141C V_BASE_ADR
VI_UV_DELTA (r/w)0 x10 1420 U_DELTA(16)
VI_Y_DELTA (r/w)0x10 1424 Y_DELTA(16)
V_DELTA(16)
HBE (highway bandwidth error)
HBE INT enable
Highway bandw i dth error ACK SLEEPLESS
000000
000000
000000
RESERVED
Figur e 6-11. YUV capture vie w of VI MMIO regis ters .
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-9
6.4 HALFRES CAPTURE MODE
Halfres capture mode is identical in operation to fullres
capture mode except that horizontal resolution is re-
duced by a factor of t wo on both lumi nance and chromi-
nance data.
Referring to Figure 6-9 and Figure 6-11, if VI is pro-
grammed to capture HEIGHT lines of WIDTH pixels in
WIDTH/2 pixel s
HEIGHT lines
pix0 pix1 pix2 pix
W/2–1
• • •
. . .
Y_BASE_ADR
WIDTH/4 pixe ls
HEIGHT lines
pix0 pix2 • • •
. . .
U_BASE_ADR
(Repeated for V_BASE_ADDR,
V_DELTA)
Y_DELTA
U_DELTA
Figur e 6-12 . V I halfr e s pla nar mem ory for mat.
YUV 4:2:2 CCIR656
input samples
abcdefgh i j k l
Halfres capture
sample results
Uf'3Uc
–19Ue19Ug3Ui
–++()32⁄=
Vf'3Vc
–19Ve19Vg3Vi
–++()32⁄=
Yh'3Ye
–19Yg32Yh19Yi3Yk
–+++()64⁄=
Figur e 6- 13. Half re s co- site d samp le captur e .
YUV 4:2:2 CCIR656
input samples
abcdefghi jkl
Halfres capture
sample results
Yg'3Yd
–19Yf32Yg19Yh3Yj
–++ +()64⁄=
Uf'3Uc
–19Ue19Ug3Ui
–++()32⁄=
Vf'3Vc
–19Ve19Vg3Vi
–++()32⁄=
Figure 6-14. Halfres interspersed sample capture.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-10 PRELIMINARY SPECIFICATION
halfres mode, the resulting captured planar data is as
shown in Figure 6-12. Note that WIDTH/2 luminance and
WIDTH/4 chrominance samples are captured. In this
mode, STA RT_X and WIDTH must be a multiple of f our.
Ho riz ont a l-r esol ut i on redu ct i on is per f orme d as shown i n
Figure 6-13 or Figure 6-14. The spatial sampling con-
ventions of the pixels in memory depends on the SC
(sa mp li ng co nv en ti on) bi t in t he VI_C TL r e gist er . Ass um-
ing that the camera sampling positions obey the conven-
tions shown in Figure 6-5, two possible spatial formats
are supported in memory:
•If SC=0, co-sited luminance and chrominance sam-
ples result as shown in Figure 6-13. This corre-
sponds to the standard YUV 4:2:2 sampling
conventions.
•If SC=1, interspersed chrominance samples result,
as shown in Figure 6-14. This form is (after vertical
su bsa mpli ng of t he chr oma c omp on ents ) id enti ca l to
the MPEG-1 sampling conventions. If vertical sub-
sampling is desired, it can either be performed in
s oftware on the DSPC PU or in ha rdware by the ICP.
The filtering process applies mirroring at the edge of the
act i ve v ideo area, as pe r Figure 6-7.
For b oth f i lter s , c omp ute d vi de o d ata is c la mpe d t o 01h if
result of the filter is less t han 01h and clampe d to F Fh if
greater than FFh.
6 .5 RAW CAP TU RE MO DES
All raw capture modes (raw8, raw10s and raw10u) be-
have similarly. VI_DATA information is captured at the
rate of the sender’s clock, without any interpret ation or
s tar t/st o p of capt u re on the ba si s of the data value s. An y
clock cycle in which VI_DVALID is asserted leads to the
capture of one data sample. Samples are 8 or 10 bits
long (raw8 versus raw10 modes). For t he 8-bit capture
mode , fou r sampl es are packed to a word. Fo r the 10- bit
capture modes, two 16-bit samples are packed to a
word. T he extension from 10 to 16 bits uses sign exten-
sion (raw10 s) or zero extensio n (raw 10u).
For 8-bit and 16-bit capture, successive captured values
are written to increasing memory addresses. For 16-bit
captur e, t he byte orde r wi th w hi ch the 16-b it da ta i s writ -
ten to memory is governed by the LITTLE ENDIAN bit.
The VI LI TTLE EN DIAN b it shou ld be set th e same as the
DSPCPU endianness (PCSW.BSX). This ensures that
the DSPCPU sees correct 16-bit data.
Figure 6-15 illustrates the ‘raw-mode’ view of the VI
MMI O re gisters. Figure 6-16 shows the major VI states
associated with raw-mode capture. The initial state is
reached on software or hardware re set as desc ribed in
Section 6.1.4, “Hardware and Software Reset”. Upon re-
set , all s tatus a nd c o nt ro l bits a r e s et to ‘0’. In particular,
CAPTURE_ENABLE is set to ‘0’ and no capture takes
place.
Once the software has programmed BASE1 and BASE2
(wit h the start addresses of t wo SDR AM buffer are as1)
21
VI_S TAT U S (r )0x10 1400 31 0
MMIO_BASE
offset:
VI_CLOCK (r/w)0x10 1408
VI_BASE1 (r/w)0x10 1414
VI_BASE2 (r/w)0x10 1418
371115192327
DIVIDER
BUF1ACTIVE
BUF2FULL BUF1FULL
VI_CTL (r/w)0x10 1404 MODE
BUF1FULL
ACK2
ACK1
BUF2FULL
Little endian Capture enable
software RESET
DIAGMODE
SELFCLOCK
BASE1
BASE2
VI_SIZE (r/w)0x10 141C SIZE (in samples)
OVERFLOW
(message mode only)
OVERRUN
ACK_OVF
ACK_OVR
OVF
OVR
Interrupt enables
Highway bandwidt h error
Highway bandw id th error
INT enabl e
Hi ghwa y b a ndwidt h error A CK SLEEPLESS
000000
000000
000000
RESERVED
31 15192327
VALID
Figure 6-15. Raw and message passing modes view of VI MMIO registers.
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-11
and SIZE (in numbe r of sa mples ), it is sa fe to en able ca p-
ture by setting CAPTURE_ENABLE. Note that SIZE is in
samples and must be a multiple of 64, hence setting a
minimum buffer size of 64 bytes for raw8 mode and 128
by tes for raw 10 modes. At th is point, buffer1 is the active
capture buffer. Data is captured in buffer1 until capture is
disabled or until SIZE samples have been captured. After
every sam p le, a ru nn in g a ddr es s po in ter is i nc r e me nt ed
by t he sam ple s ize (on e or t wo bytes ). I f S IZE sa mpl es
have bee n ca p tured, capture continues (wi thout missing
a sample) in buffer2. At the same time, BUF1FULL is as-
serted. This causes an interrupt on the DSPCPU, if en-
abled by BUF1FULL INT ERRUPT ENABLE.
Bu ff er2 is now th e ac tive capture buffe r a nd behav es as
described above. In normal operation , t he DSPCPU will
respond to the BUF1FULL event by assigning a new
BASE1 a nd (option ally ) SIZE an d performing a n ACK1.
If the DSPCPU fails to assign a new buffer1 and per-
forms an ACK1 before buffer2 also fills up, the OVER-
RUN condition is raised and capture stops. Capture con-
tinues upon receipt of an ACK1, ACK2, or both,
regardless of the OVERRUN state. The buffer in which
capture resumes is as indicated in Figure 6-16. The
OVERRUN condition is ‘sticky’ and ca n only be cl ear ed
by so ftware, by writ ing a ‘1’ to the ACK_OVR bit in the
VI_CTL regi ster.
If insufficient bandwidth is allocated from the internal
dat a high w ay, th e VI inte rnal buffers may overflow. This
leads to assertion of the HIGHWAY BANDWIDTH ER-
ROR condition. One or more data samples are lost. Cap-
ture resumes at the co rrect memory address as soon as
the internal buffe r is written to memory. The HBE error
con dit ion i s sti cky . It re mai ns as ser ted until it is cl eared
by writing a ‘1’ to HIGHWAY BANDWIDTH ERROR
ACK. Refer to Sect io n 6 .7, “Highway Latency and HBE.”
Note that VI hardware uses copies of the BASE and SIZE
registers once capture has started. Modifications of
BASE or SIZE, therefore, have no effect until the start of
the next use of the corresponding buffer.
Note also that the VI_BASE1 and VI_BASE2 addresses
mus t be 64- by te al ig ned ( the s ix L SBs a r e alway s ‘0’).
6.6 MESSAGE-PASSING MODE
In this mode, VI receives 8-bit message data over the
VI_DATA[7:0] pins. The message data is written in
packed form (four 8-bit message bytes per 32-bit word)
to SDRAM. Message data captur e starts on receipt of a
START event on VI_DATA[8]. Message data is received
until EndOf Messa ge (EOM) is received on VI_ DATA[9]
or the receive buffer is full. Note that the VI_SIZE MMIO
re gi ster de ter mi ne s the bu f fer siz e, and he nce maximu m
message length. It should not be changed without a VI
(soft) reset.
Figure 6-17 illu st r ates an e xam pl e of an 8-byt e m ess age
tr ansfer . The firs t byte (D0) is sample d on th e rising edge
of the VI_CLK clock after a valid START was sampled on
the preceding rising clock edge. The last byte (D7) is
1. SDRAM buf fers must start on a 64 -byte boundary.
ACTIVE = BU F2
BUF1FULL
ACTIVE = BU F1
ACTIVE = BU F 2
ACTIVE = BU F 1
BUF2FULL
BUF1FULL
BUF2FULL
raise OVERRUN*
* OVERRUN is a sticky fl ag. It is set but does not af-
fect operation . It can only b e cleared by software, by
writing a ‘1’ to AC K_OVR.
(See text in Section 6.5)
ACK1 & ~ACK2
ACK1 & ACK2
~ACK1 & ACK2
Buffer2 Full
Buffer1 Full
Buffer1
Full
ACK1
Buffer2
Full
ACK2
RESET
Figure 6-16 . VI raw mode ma jor states.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-12 PRELIMINARY SPECIFICATION
sampled on the rising clock edge where EOM is sampled
asserted.
Th e m es s ag e pas si ng mo de vi ew o f the VI MMIO regi s -
ters is shown in Figure 6-15. The major states are shown
in Figure 6-18. The operation is almost identical to the
operation in raw-capture mode, except that transitions to
another active buffer occur upon receipt of EOM rather
than on buffer full. OVERRUN is raised if the second
buf f er re ce ives a comp lete mes sag e be f ore a ne w buf fer
is assigned by the DSPCPU.
OVERFLOW is raised if a buffer is full and no EOM has
been received. If enabled, it causes a DSPCPU interrupt.
Since digital interconnection betwee n d evi ce s is r el ia ble ,
ov erflow is indica tive of a protocol error bet ween the two
PNX1300s involved in the exchange (failure to agree on
mess age si ze). D etectio n of overflow lea ds to tota l hal t of
capture of this message. Capture resumes in the next
buffer upon receipt of the next START event on
VI _DATA[ 8]. Th e OVERFLO W fl ag is st icky an d can only
be c le ar e d by wr i tin g a ‘1’ to ACK_ O VF.
Highway bandwidth error behavior in message passing
mode is identical to that of raw mode.
6.6.1 VI_DVALID in Message Passing Mode
PNX 130 0 offe rs a ne w mo de wher e the V I_D VAL ID p in
does not contro l th e s ampl in g o f the VI_ DATA[9:8 ] p i ns.
These pins are used for END and START of a message.
This new mode is controlled by a new field, VALID, in the
VI_CLOCK MMIO register. The default value after RE-
SET is ‘0’.
When VI_ C LOC K. VALID is se t to ‘0’ (t he RESET value)
th en PN X 1 300 behave s as in TM-1300 . In thi s c ase th e
START and END of messages are sampled only if the
VI_DVALID pin is HIGH.
When VI_CLOCK.VALID is set to ‘1’ then PNX1300 acti-
vates the new behavior. In this case the START and END
of messages are always sampled independently of the
state of th e VI_D V A LI D pin.
VI_CLOCK.VALID cannot be read back, therefore it al-
way s read 0.
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
XX D0 D1 D2 D3 D4 D5 D6 D7 XX XX
Start of
message
End of
message
Figur e 6- 17. VI message passing signal e xample.
ACTIVE = BU F 2
BUF1FULL
ACTIVE = BU F 1
ACTIVE = BUF2
AC TI VE = BUF1
BUF2FULL
BUF1FULL
BUF2FULL
raise OVERRUN*
* OVERRUN and OVERFLOW are sticky flags. They are set,
but do not affect operation. They can only be cleared by soft-
ware, by writing a ‘1’ to ACK_OVR or ACK_O VF.
(See text in Section 6.6)
ACK1 & ~ACK2
ACK1 & ACK2
~ACK1 & ACK2
EOM
EOM
EOM
ACK1
EOM
ACK2
RESET
No EOM ⇒ raise OVERFLOW*
(See text in Section 6.6)
No EOM ⇒ raise OVERFLOW*
(See text in Section 6.6)
Figure 6-18. VI message passing mode major states.
Philips Semiconductors Video In
PRELIMINARY SPECIFICATION 6-13
6.7 HIGHWAY LATENCY AND HBE
Refer to Chapter 20, “Arbiter,” for a descr ipt io n of the ar-
biter terminology used here. The VI unit uses internal
buffering before writing data to SDRAM. There are two
internal buffers, each 16 entries of 32 bits.
In fullres mode, each internal buffer is used for 128 Y
sample s, 64 U sa mple s, and 6 4 V samp les. Once the first
int erna l bu ffer is f ille d, 4 hi ghw ay tr an sact ions m ust oc -
cur before the second buffer fills completely. Hence, the
requirement for not losing samples is:
•4 requests must be served w ithin 256 VI cloc k c ycles.
For the typical CCIR601-resolution NTSC or PAL 27-
MHz VI clock rate, the latency requirement is 4 requests
in 9481 ns (25600/27). This can be used as one request
every 2370 ns or, with a PNX1300 SDRAM clock speed
of 10 0 MHz, eve ry 237 SDR AM clock cycle s. The one re-
ques t l atenc y is use d to de fine th e prio rity rais ing v alue
(see Section 20.6.3 on page20-8 ).
In halfres mode, the Y, U, and V decimation by 2 takes
place before writing to the internal buffers. So, the re-
quir e m en t for n ot lo os in g sam ples is :
•4 requests ser ved within 512 VI clock cycles.
For halfres subsampling, NTSC or PAL 27-MHz VI clock
rat e an d PNX130 0 SDR AM c lo ck s peed of 100 M H z, la -
te ncy is 4 re ques ts in 51 200/2 7 = 1896 2 ns (189 6 hi gh-
way clock cycles) or one request every 4740 ns (474
SDRAM clock cycles).
For raw 8 capt u re an d mes sag e pa ss in g mod es, each in-
te rnal b uf fer s tores 64 sam ples a t the incoming VI cloc k
rat e. The la tenc y requi r em e nt is one re qu es t se r ve d ev -
ery 64 VI cl oc k cycles .
For the raw10 capture modes, each internal buffer stores
32 s amples. Hence, the requirement for not losing sam-
pl es is one r e quest ser v ed ev er y 32 VI cl ock cyc les.
Fo r a 38-M H z d at a r a t e on the inco ming 10-bit s ampl e s
and a P N X 13 00 S DR AM c lo ck sp ee d of 1 00 M H z , high -
way latency should be set to guarantee less than 3200/
38 = 842 ns (84 SDRAM clock cycles) per clock cycle.
This cann ot be met if any other peripherals are enable d.
Table 6-4 summarizes the maximum allowed highway la-
ten cy (i n SDRAM c lo ck c ycl es ) ne ed ed to guar a ntee that
no sa mpl e s are l os t. The g ener al for mu la uses ‘F’ to rep-
resent the VI clock frequency (in MHz).
In fullres mode, bandwidth requirements (in bytes) per
vi de o line w ith acti ve image for V I is:
•Bfullr = ceil(WIDTH*2/256) * 4 * 64
ceil(X) function is the least int egral value greater than or
equal to X .
In ha lf res m od e, the band w id th is :
•Bhalfr = ceil(WIDTH*2/512) * 4 * 64
Raw8 mode and message passing mode bandwidth de-
pen ds on l y on VI clock sp ee d. For raw 10 mod e ea ch 10-
bit value counts as 2 bytes for bandwidth computations.
Tabl e 6-4 . VI hi ghw ay laten c y req u ir em ent s (27- M Hz
data ra te, 100-MHz PNX1300 highway clock)
Mode Max latency setting
(27 MHz, 100 MHz) Formula
full res capture 237 6 ,400/F
halfr es ca ptur e 474 12 ,800/F
raw8 237 6,400/F
raw10s 118 3,200/F
raw10u 118 3,200/F
mess age passin g 237 6 ,4 00/F
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
6-14 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 7-1
Enhanced Video Out Chapter 7
by Marc Duranto n, Dave Wyland, Gert S lavenb urg
7.1 ENHANCED VIDEO OUT SUMMARY
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The P NX1300 Enhanced Video Out (EVO) improves on
the design of the TM-1000 Video Out (VO) unit while
maintaining binary-compatibility. PNX1300 EVO is fully
backward compatible with TM-1100, and has been ex-
tended to support byte data rates up to 81-MHz and im-
prove the G enloc k mode. The summa ry of new EVO fea-
tu r es vers us TM - 1000 in c l ude s:
•Internal clock generator (DDS) has reduced jitt er
•Fu ll al ph a blending s up p o r ts 129 -levels
•Chroma ke ying
•Fr a me s ync hroniz at i on c an be internal ly o r ext ernally
gener ate d ( G en lo ck m od e )
•Ex terna l fr ame sync . follow s th e f ield numb er ge ne r-
at ed in the E AV/SAV code
•Programma ble YUV outp ut clippin g
•Data-valid signal generated in data-streaming mode
•In message passing mode, message length can
range from one word (4 bytes) up to 16 MB.
7.2 ABOUT THIS DOCUMENT
This chapter describes the PNX1300 EVO unit which ex-
te nd s a nd im prov es the d es ign o f the TM - 1000 VO u nit,
and consolidates the changes introduced in the TM-
1100. Please refer to the TM-1000 databook for a de-
scri pti on of the VO u ni t’s functionality .
7.3 BACKWARD COMPATIBILITY
The EVO is fu nction ally compa tibl e with the TM -1000 VO
unit. All TM-1000 VO features are supported exactly in
the same f ashion by th e PNX 1300 EV O. Soft ware wr itte n
for t he TM- 1 00 0 VO can cont ro l t he PNX 13 00 EV O wi th-
out modification (with the exception of the Genlock mode
which now requires EVO_CTL. GENLOCK to be set to 1
in additi on to VO _ C TL. SYNC_M AST ER = 0).
Al l new fe at u res (wit h resp ec t to TM-10 00 ) and im pr ov e-
ments are selectively enabled by setting bits in the
EVO_CTL MMIO register, described in Section 7.16.4. A
method to determine the existence of EVO registers is
gi ve n in Section 7.16.1.
The PNX1 300 EVO features are dis abled on hardware
reset in order to remain hardware-compatible with the
TM-1000 VO. So it is assumed throughout this chapter
that all new functions controlled by EVO_CTL are en-
abled by software. Any new software should use the new
EVO modes.
7.4 FUNCTION SUMMARY
The PNX1300 EVO generates and transmits continuous
di gital vide o im ag es. I t can co nn ect to an of f-chi p vid eo
subsystem such as a digital video encoder chip ( e.g., the
Philips SAA7125 DEN C digital encoder), a digital video
re cor der , or th e vide o in pu t of anot he r PN X13 00 t hro ug h
a CCIR 656-compatible byte-parallel video interface.
See Figure 7-1, Figure 7-2, and Figure 7-3.
The EVO can either supply video pixel clock and syn-
chronization signals to the external interface or synchro-
niz e t o sign als r e ce ived fro m t he exter na l in ter face (G en-
lock m ode).
PA L, NTSC , 16: 9 an d ot her vid eo fo rm at s in cl ud in g do u-
bl e pixe l-ra te, non -int erla ced vi de o forma ts a re su ppor t-
ed through programmable registers which control pixel
cl oc k fre qu e n c y an d vid eo fiel d or fr am e fo r m at.
Th e EV O ca n c omb ine a ba ckg rou nd vi deo i mag e fr om
SDRAM with a n option al foreg round graph ics over lay im-
age fr om SDR AM u sing 129 - leve l, pe r- pi xel alpha bl en d-
ing. The composite result is sent out as continuous vid-
eo. Video image data is taken from a planar memory
format, with separate Y, U and V planes in memory in
YUV 4:2:2 or 4:2:0 format. The optional graphics overlay
is taken from a pixel-packed Y U V 4:2:2+α data structure
in memory.
The EVO can also be used to stream continuous data
(da ta- st r ea m ing mo de) o r se nd un idir ec ti onal m es s ages
(message-passing mode) from one PNX1300 to another.
In data-streaming mode, the EVO generates a continu-
ous st r eam o f a rbitrary byte data using internal or exter-
nal cloc k ing. D ua l buff e rs al low con tinu o u s da ta s tr ea m -
ing in this mode by allowing the DSPCPU to set up a
buffer while another is being emptied by the EVO. Data-
valid signals are generated on VO_IO1 and VO_IO2 to
synchronize data streaming to other PNX1300 data re-
ceivers.
In message-passing mode, unidirectional messages can
be sent to the Video In (VI) port(s) of one or more
PNX1300s. Start and end-of-message signals are pro-
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-2 PRELIMINARY SPECIFICATION
vided to synchronize message passing to other
PNX1300 message receivers.
7.4.1 Detailed Feature Descriptions
Th e E V O provid es th e f o llo w in g ke y f u nc tions.
•Continuous d igital vid eo output of PAL or NT SC for-
mat data according to CCIR 601.
•Tr a nsm is sion of YUV 4: 2:2 co-sited pixel data ac r os s
a standard 8-bit parallel CCIR 6561 interface.
Embedded SAV and EAV synchronization codes and
separate sync control signals compatible with Philips
DENC encode rs are avail able.
•Supports the nominal PAL/NTSC data rate of 27
MB /s ec. ( 13. 5 Mp ix /sec .) , or any by t e da ta ra te up to
an 81-MHz EVO clock.
•Custom video formats can be programmed with
frames or fields of up to 4095 lines of up to 4095 pix-
els, subject only to the data rate limitation above.
•Support for video images in planar YUV 4:2:2 co-
sited, plana r YUV 4:2:2 interspersed , or plan ar YUV
4: 2:0 mem ory formats.
•Optional 129-level alpha blending. Graphics overlay
imag e is in pixel-p acked Y UV 4: 2:2 +α for mat , and is
alph a bl ende d on top o f t he vi deo im age. E ach p ixel
has a 1-bit alpha, which selects one of two global 8-
bit alpha values which provide 129 layers of transpar-
ency. Wi th ove rlay ena bled, the outp ut byte da ta rate
is limited to 45% of th e SDR AM clock, or up to an 81-
MHz EV O clock, whichever is smaller.
•Optional horizontal 2X upscaling of the video image
for di sp lay. The overl ay is alw ays in di s play for m a t.
•In data-streaming mode, the EVO acts as a high
bandwidth continuous-output data channel. The byte
data rate is limited to an 81-MHz EVO clock.
•In message-passing mode, the EVO can send mes-
sages from 1 word (4 byt es) up to 16 MB. The byte
data rate is limited to an 81-MHz EVO clock.
•For diagnostic purposes, EVO output data can be
internally looped back to the VI port. This is con-
trolled by the VI DIAGMODE bit.
7.4.2 Summary of Operation
The EVO normally supplies continuous video data to its
outputs. The EVO is programmed and started by the
PNX1300 DSPCPU. The EVO issues an interrupt to the
DSPCPU at the end of each transmitted field, and/or at a
pr ogramma ble v ert ical positi on in t he fi eld . The DS PCPU
upd ates the EVO vid eo ima ge data p ointer s with pointers
to the next field during the vertical blanking interval so as
to mai ntai n cont inuo us vid eo output . D uring vide o outpu t,
the EVO supplies embedded CCIR 656 SAV (Start Ac-
tive Vi deo) and EAV (End A ctive Video ) syn c code s and
optionally supplies horizontal and frame sync signals.
The EVO can eithe r su pply pi xel cl ock an d hori zontal an d
fra me timing si gnals o r it c a n l o c k t o ex te r n al tim ing s ig-
nals such as those supplied by a Philips SAA7125 DENC
digital encoder or similar sync source.
7.5 INTERFACE
Table 7-1 lists the interface pins of the EVO unit.
Figure 7-1, Figure 7-2, and Figure 7-3 illustrate typical
connections for commonly-used external devices that in-
terfac e to th e EVO.
The most common way to generate analog video is
shown in Figure 7-1. In this setup, an SAA7125 Digital
Encoder (DENC) can be programmed to derive sync ei-
ther from the VO_DATA stream EAV/SAV codes, or from
its RCV1/2 pins.
Figure 7-2 illus tr at e s how a byte-pa ral le l ECL - l ev el sta n-
dard CCIR 656 interface can be created. In certain pro-
fessional applications, serial D1 video is also used. In
that case, the EVO can be connected to a Gennum
GS9022 Digital Video Serializer or similar part (not
shown).
Figure 7-3 shows the EVO unit of one PNX1300 con-
nected to the VI unit of a second PNX1300.
1. Refer to CCIR recommendation 656: Interfaces for dig-
ital component video signals in 525 line and 625 line
television systems. Recommendation 656 is included in
the Philips Desktop Video Data Handbook.
PNX1300
VO_DATA[7:0]
(HS) VO_IO1
(FS) VO_IO2
VO_CLK SAA7125
MP[7:0]
RCV1
RCV2
LLC
Figure 7-1. EVO connected to a digital video encod-
er (DENC).
PNX1300
VO_DATA[7:0]
VO_CLK
8
1
16
2
TTL to ECL
CCIR 656
Subminiature
“D” Connector
Data A,B[7:0]
Clock A,B
Figur e 7-2 . EVO con ne cte d to a CCIR 656 vide o-
output connector.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-3
7.6 BLOCK DIAGRAM
Figure 7-4 show s a block d iagram of the E VO un it. It con-
s ists of a clock generator, a video frame timing generator
and an image or data generator. The image generator
produces either a CCIR 656 digital video data stream
with opt iona l YUV ov er lay or a c ontin uo us-d ata or mes -
sage-data stream. It also performs optional format con-
version and optional 2:1 horizontal scaling.
Th e frame timi ng gene rator provides programmable i m-
age timing including horizontal and vertical blanking,
SAV and EAV code in serti on , overla y sta rt and end t im -
ing, and horizontal and frame timing pulses. It also sup-
plies data-valid timing signals in data-streaming mode
and start-of-message and end-of-message timing sig-
nals i n message-passing mode. T he sync timing pulses
can be generated by the frame timing unit, or the frame
ti min g u ni t can be dri ve n b y ex ter na ll y-suppl ie d s ync tim-
ing pulses, when VO_CTL. SYNC_MASTER = 0 and
EVO_CTL. GENLOCK = 1.
The video clock generator produces a programmable
video clock. The video clock generator can supply the
vide o clock fo r the frame timin g generator and external
devices, or it can be driven by an e xternal cloc k signa l.
7.7 CLOCK SYSTEM
Po sitiv e edge s of VO _CLK drive al l EVO o utpu t e ven ts .
A block diagram of the EVO clock system is shown in
Figure 7-5. The EVO clock is either supplied externally or
internally generated by the EVO, as controlled by the
VO_CTL. CLKOUT bit. When CLKOUT = 0, the EVO
clock is supplied by an external source through the
VO_CLK pin as an input. This is the default mode, en-
tered at hardware reset. When CLKOUT = 1, an internal
clock generator supplies the EVO clock and drives the
VO_CLK pin as an output.
The internal clock generator system is a square wave Di-
rect Digital Synthesizer (DDS) which can be pro-
grammed to emit frequencies from 1 Hz to 50 MHz. The
output of the DDS is sent to a phase-locked loop filter
(PLL) which removes clock jitter from the DDS output
signal. Th e PLL can also be us ed to divide or double the
DD S fr eque ncy . The P LL V CO opera te s from 8- MHz to
Table 7-1. EVO unit interface pins
Signal Name Type Description
VO_DATA[7:0] OUT CCIR 656-style YUV 4:2:2 digital out-
put data, or general-purpose high
speed data output channel. Output
changes on positive edge of VO_CLK.
VO_IO 1 I/O-5 Horizontal Sync (HS) output or Star t
Message (STMSG) output. See
Figure 7-18.
VO_IO2 I/O-5 Frame Sync (FS) input, FS output or
ENDMSG output .
• If set as FS input, it can be set to
respond to positive or negative edge
transitions.
• If the EVO operates in Genlock mode
and the selected transition occurs,
the EV O sends two fields of video
data.
• In m essage-pass ing mode, this pin
acts as the ENDMSG o utput . See
Figure 7-18.
VO_CLK I/O-5 The EVO unit emits V O_DATA on a
positi ve edge of VO _CLK. VO_CLK
can be configured as an input (the
hardware reset default) or output.
• If configured as an input, VO_CLK is
received from external display-clock
master ci rcuitry.
• If configured as output, the PNX1300
emits a low-jitter clock freq uenc y
programmable between approx. 4
and 81 MHz.
PNX1300 A
VO_DATA[7:0]
(STMS G) V O_IO1
(ENDMS G) V O_IO2
VO_CLK
PNX1300 B
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
VI_DVALID
logic ‘1’
Figure 7-3. EVO unit connected to the VI unit of a
second PNX1300.
Vide o Frame
Timing
Generator
V i de o C l ock
Generator
Image Generator
Overlay Generator
Message/Data Generator
VO_IO1
(HS , S t art Msg, or
valid data pulse)
VO_IO2
(VS, End Msg, or
valid data level)
VO_CLK
VO_DATA[0:7]
SDRAM Highway
Figur e 7- 4. EVO uni t blo ck d iag r am.
Square-Wave DDS
FREQUENCY
PLL
Filter VO_CLK
VO_CLK Internal
(to Frame Timing Gen.)
CLKOUT9 × CPU Clock
03
Figure 7-5. EVO clock system.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-4 PRELIMINARY SPECIFICATION
90 MHz. The PLL is enabled and programmed as de-
scribed in Section 7.19.
DDS clock rate is set by the VO_CLOCK. FREQUENCY
field according to the equation shown in Figure 7-6. The
VO_ C LK fre qu en cy ca n be a divi der or mul t ipli er o f fDDS,
as determined by the PLL subsystem settings.
Low-jitter clock mode is automatically entered whenever
FREQUENCY[31] = 1. If FREQUENCY[31] = 0, the DDS
operates at 1/3 the rat e (for compa tibility with T M-1000
code), and FREQUENCY must be set as shown in
Figure 7-7.
The DDS synthesize r maximum jit ter can be c omputed
as follow s :
Example of jitter values can be found in Table 7-2.
7.8 IMAGE TIMIN G
The EVO emits a serial byte-data stream used by
CCIR 656 devices to generate a displayed image.
Figure 7-9 shows an NTSC-compatible, 525-line inter-
laced image. The field and line numbers are shown for
reference.
Interlaced images are generated by the display hardware
by controlling the ver tical ret race timin g. For ref erence,
Figure 7-8 sh ow s a tim ing diagram of NTSC- c om patible
interlaced frame timing illustrating the analog vertical re-
trace signal. The vertical retrace signal for the second
field begins in the middle of the horizontal line that ends
the fir st field. Th i s cau se s the f ir s t lin e of the second field
to be g in ha lfw ay a cro s s the di spla y scr ee n and t he l in e s
of t he se cond fi eld to be sc anned bet ween t he lines o f the
firs t field, resulti ng in an interlaced d isplay.
The analog timing required to generate the interlaced
signal is supp lied by the d isplay de vice. The CCIR 656
digital video signals generated by the EVO use frame
syn chr oniz atio n ti ming and do not ge ne rate an y ve rtica l
ret r ac e tim i ng .
7.8.1 CCIR 656 Pixel Timing
The EVO generates pixels according to CCIR 656 timing
in YU V 4:2 :2 co-si t ed forma t and out put s th es e pix el s a s
sh ow n in Figure 7-10. P ix els ar e gene ra ted in g roup s of
two, with four bytes per two pixels. Each pair of pixels
has two lumi nance bytes (Y0 , Y1) and on e pair of chr omi-
nance byte s (U 0, V0) arranged in the s equence shown.
The chrominance samples U0 and V0 are sampled spa-
tially co-sited with luminance sample Y0. For PAL or
NTSC video, pixels are generated at a nominal rate of
13. 5 Mp ix/s ec. (27 MB /sec .). P ix els ar e c lock ed ou t on
th e positive ed ge of V O_C LK.
7.8.2 CCIR 656 Line Timing
Th e C C IR 65 6 line timing is sh ow n in Figure 7-11. Each
lin e be gi ns wit h an EAV cod e, a blan ki ng int erva l an d an
SAV code, followed by the line of active video. The EAV
code in dic ates end o f act ive vid eo for the pre vio us li ne,
and the SAV code indicates start of active video for the
current line.
Table 7 -2. Jitter values for common DSPCPU MHz
fDSPCPU
(MHz) jitter
(nSec) fDSPCPU
(MHz) jitter
(nSec)
143 0.777 180 0.617
166 0.669 200 0.555
Figure 7-6. DDS low-jitter oscillator frequency.
FREQUENCY 231 fDDS 232
⋅
9fDSPCPU
⋅
-----------------------------+=
Figure 7-7. DDS slow speed oscillator frequency
FREQUENCY fDDS 232
⋅
3fDSPCPU
⋅
-----------------------------=
jitter 1
9fDSPCPU
⋅
-----------------------------=
1 19 20 262 263 282 525 1
One Frame
One Line
Field 2Field 1
Blanking BlankingActi v e Video Ac t ive Vide o
1/ 2 Lin e In ter l ac e O ffs et
Vertical
Sync
Video
Lines
Figure 7-8. Interlaced timing—NTSC analog sync. signals.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-5
7.8.3 SAV and EAV Codes
The End Active Video (EAV) and Start Active Video
(SAV) codes are issued at the start of each video line.
EAV an d SAV c odes hav e a fix ed form at: a 3- byte pre-
amb le of 0xFF , 0x 00, 0x00 fol lowed by the SAV o r EA V
c ode byte . T he EA V and S AV co de by te f orma t i s s how n
in Figure 7-12 for reference. The EAV and SAV codes
def ine t he st art an d end of th e horiz on tal bla nkin g inte r-
val, and they also indicate the current field number and
the vertical blanking interval.
Line 20
Line 21 Line 282
Line 283
Line 26 2
Line 26 3 Li ne 524
Line 525
Field1 Field2
Scan Direction
Displayed Image
F igur e 7 - 9 . In ter la ced di spl ay: 525- line, 60-Hz image .
U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4
Byte 0
Line S c an @ 27 MH z = 13. 5 Mpix /s ec.
VO_DATA[0:7]
VO_CLK
Y4
Figure 7-10. CCIR 656 pixel timing.
ES SEE
Blanking Active Vi deo Blanking Acti ve Vi de o
Line i Line i+1
SAV, EAV Codes YUV 4:2:2 pixels
Figure 7-11. CCIR 656 line timing.
Figure 7-12. Format of SAV and EAV timing codes.
Preamble
11111111 00000000 00000000 1FVHPPPP
Timing reference code
Protection bits
(err or correct i on)
H = 0 for SAV
H = 1 for EAV
V = 1 during field blanking
V = 0 elsewh ere
F = 0 during Field 1
F = 1 during Field 2
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-6 PRELIMINARY SPECIFICATION
Th e SAV and EAV code s ha ve a 4 - bi t pro te ction fiel d t o
ens ure va lid code s. T he EVO gen erate s thes e prote ction
bits as part of the SAV and EAV codes as defined by
CCIR 656. There are 8 possible valid SAV and EAV
codes shown with their correct protection bits in
Table 7-3. The EVO generates SAV and EAV sync
codes and inserts them into the video out data stream ac-
cording to the CCIR 656 specification under all condi-
ti on s, whet he r it is gen er ati n g or r ec ei vi ng horiz ontal and
frame timing information.
7.8.4 Video Clipping
SAV and EAV codes are ident ified by a 3 -byte pr ea mble
of 0xFF, 0x00 and 0x00. This combination must be
avoi de d in th e vid eo da ta out pu t by th e EVO to pre ven t
accidental ge neration of an invalid sync code. T he EVO
provides programmable maximum and minimum value
clipping on the video data to prevent this possibility. If
clippi ng is en abled, the EVO automaticall y clips th e re-
sulting image data as described in Section 7.15.3.
7.8.5 CCIR 656 Frame Timing
The interlaced frame timing defined by CCIR 656 is
show n in Table 7-4. Lines are numbered from 1 to 525
for 525-line, 60-Hz systems and from 1 to 625 for 625-
line, 50-Hz systems. The Field and Vertical Blanking col-
umns indicate whether the field and vertical blanking bits,
respec tively, a re set i n the SAV and E AV codes f or the
indicated lines. The 525 and 625 formats have similar
timing bu t differ in th eir line numb e ring.
7.9 ENHANCED VIDEO OUT TIMING
GENERATION
The EVO gener ates ti ming fo r fr ames, activ e vide o areas
within frames, images within the active video area, and
overlays within the image area. The relationship between
these four is shown in Figure 7-13. T he frame includes
the timing for both interlaced fields. Progressive scan, or
non-interlaced video, is accomplished by setting the tim-
ing parameter s such that t w o identic al s ucce s sive f i el ds
are gene rated.
7.9.1 Active Video Area
Shown in Figure 7-13, the ac tive video ar ea be gins a f ter
the horizontal and ve rtical blanking intervals and repre-
sents the pixels visible on the screen. The image area is
th e ac tual d ispl ayed i mag e w it h in the active video area .
It can be slightly smaller than the active video area to
avoid edge effects at the top, bottom and sides of the im-
age. The over l ay a rea is within the im ag e area.
The EVO uses counters to generate and control image
timing. The Frame Line Counter and Frame Pixel
Counter control the overall timing for the frame and de-
fine the total numb er of pixels per line, lines per frame,
and interlace timing, including horizontal and vertical
bl an king int e r v als.
Note that t he Frame Li ne Counter has a starting value of
one , no t zero, and it co unts fr om 1 to 52 5 or 62 5, consi s-
tent with CCIR 656 line numbering. The Image Line
Counter an d Image Pixel Counter de fine the visible im-
age with in th e fie ld.
Th e geom etry o f th e acti ve vid eo ar ea i s de fine d by th e
contents of several MMIO registers shown in
Figure 7-29. The VO_FRAME. FIELD_2_START field
defi nes the s ta r t li ne of Fi eld 2 . Fi el d 2 is ac tiv e w h en th e
Fi eld Li ne C ounte r co nten ts eq ual or exc eed t hi s val ue.
The active vid eo area is def ined by t he F1_V IDEO_LINE
and F2_VIDEO_LINE fields of the VO_FIELD register for
each field of the frame, and by the
VIDEO_PIXEL_START field of the VO_LINE register for
each line of the frame. The active video area begins
wh en the cont ents of th e Frame Li ne Cou nte r and Fr ame
Pixel Counter equals or exceeds these values.
Table 7-3. SAV and EAV codes
Code Binary Value F ield Vertical Blankin g
SAV 1000 0000 1
EAV 1001 1101 1
SAV 1010 1011 1 X
EAV 1011 0110 1 X
SAV 1100 0111 2
EAV 1101 1010 2
SAV 1110 1100 2 X
EAV 1111 0001 2 X
Table 7-4. CCIR 656 frame timing
Line Number F bit V bit Comments
525/60 625/50
1–3624–625 1 1 Vertical blanking for
Field 1, SAV/EAV
code still indicates
Field 2
4–19 1–22 0 1 Vertical blanking for
Field 1, change
SAV/ EAV cod e to
Field 1
20–263 23–310 0 0 Active video, Field 1
264–265 311–312 0 1 Vertical blanking for
Field 2, SAV/EAV
code still indicates
Field 1
266–282 313–335 1 1 Vertical blanking for
Field 2, change
SAV/ EAV cod e to
Field 2
283–525 336–623 1 0 Active video , Field 2
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-7
7.9.2 SAV and EAV Overlap Period
The CCIR 656-compliant 525/60 and 625/50 timing
specifications define an overlap period where the field
numbe r in the SAV an d EAV codes from Fi eld 1 persists
into the vertical blanking interval for Field 2, and the
codes for Field 2 persist into the vertical blanking interval
for Field 1. The F1_OLAP and F2_OLAP fields of the
VO _FI EL D register define these ov erl ap intervals.
F1_OLAP and F2_OLAP are small two’s complement
values in the range -8... +7. A positive value indicates
that the overlap extends into the current field, while a
negative value indicates that it extends backward into the
previous field. S ee Figure 7-31 for the effect of negative
and positive va lues.
During the overlap interval, the vertical blanking for the
next field has begun; however, the field number flag in
the SAV and EA V codes still shows the field number for
the previous field. The field number is updated to the cor-
rect field value at the end of the overlap interval.
F1_OLAP defines the overlap from Field 1 to Field 2.
This overlap occurs during the beginning of vertical
blanking for Field 2. The SAV and EAV codes continue
to show Field 1 during this overlap interval, and they
change to Field 2 at the end of the interval.
F2_OLAP defines the overlap from Field 2 to Field 1.
This overlap occurs during the beginning of vertical
blanking for Field 1. The SAV and EAV codes continue
to show Field 2 during this overlap interval, and they
change to Field 1 at the end of the interval.
7.9.3 Control of Frame and Image Counters
The frame and image counters have different start and
stop points. The frame counters begin in the vertical
bla nkin g inte rval of the f irst fiel d and the hor izon tal bl ank-
ing interval of the first line. They stop counting when they
re ach th e height and widt h valu es of the frame. When the
EVO gener at es f ram e tim ing , the fram e co un t er s are re-
set to their start values when they reach their stop val-
ues. When the EVO receives frame timing signals, the
fr ame co unter s cont inue counti ng until res et by the exter-
na l si gn al s.
The image are a is defined by VO_YTHR register fields
IMAGE_VOFF and IMAGE_HOFF. These values are
adde d t o the F 1_VID EO_ LIN E or F2 _VI DEO_L INE a nd
VIDEO_PIXEL_START values to define the starting line
and pixel, respectively, of the image area. The image
area is active when the contents of the Frame Line
Co un ter an d Fr ame Pixel Cou nter e qual or e xce ed thes e
values.
The Image Line C ounte r and Image Pixel Counter start
counting at the first active pixel in the image area and the
first active line in the image area, respectively. The im-
age c ou nters st art at zero and s top coun ting wh e n they
reach their image height and width values. The image
count ers are re set by fr ame cou nter val ues in dicati ng the
start of the image pixel in a line and the start of the image
line in a f iel d.
Th e imag e coun ter s defi ne the ac ti ve ima ge area o f the
fram e, the area of interest for image pr ocessing. This al-
lows the ov erlay start address to be defined relative to
the active image area, for example. When the EVO is not
sen ding out active pi xels from the imag e area, it sends
out blanking codes. The blanking c odes are 0x80, 0x10,
0x80, and 0x10 for each 2-pixel group in YUV 4:2:2 im-
age data format, as defined by CCIR 656 and shown in
Figure 7-10.
7.9.4 Horizontal and Frame Timin g S ignals
The EVO can sup pl y hor izo nta l and fram e timi ng sign al s
or receive a frame timing signal from an external source.
When VO_CTL. SYNC_MASTER = 1, the EVO gener-
ates horizontal and frame timing for the external video
device. When SYNC_MASTER = 0, the EVO operates in
Ge nloc k mod e an d a n exte r nal de vi ce , such as a D ENC,
must provide frame sync. This section describes EVO
oper ation w h en it is sync ma ster. S e e Section 7.10 for a
description of Genlock mode.
If SYNC_MASTER = 1, t he VO_IO1 signal generates a
horizontal timing signal, and the VO_IO2 signal gener-
ate s a fr ame timing sign al . When EVO_E NABLE = 1 an d
FIE LD_SYNC = 1, the VO_I O2 signal indicates the field
number (low = Field 1, high = Field 2), according to the
SAV/EAV field indication (bit[6]) as shown in Figure 7-14.
The VO_IO2 signal toggles just before the first byte of the
preamb le th at pro te cts the EAV co de a nd af ter the SA V
code. Non-interlaced output can be simulated by pro-
gramming the EVO to generate fields equivalent to the
desired frames. In this case, VO_IO2 indicates odd or
even frames.
Overlay
Image Area, Field 1
Vertical Blanking, Field 1
Horizontal
Blanking
Overlay
Image Area, Field 2
Vertical Blanking, Field 2
Horizontal
Blanking
Image V Offset
Image V Offset
Image H Offs et
Image H Offset
Image Width
Image Height
Frame
Active Video Area
Active Video Area
Start P i xel
Start
Line
Figure 7- 13. Acti ve Video Area and I mage Ar ea in re -
lation to vertical and horizontal bla nking in terv a ls.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-8 PRELIMINARY SPECIFICATION
The horizontal timing signal VO_IO1, shown in
Figure 7-15, corresponds to the horizontal-blanking in-
terva l. It is a ctive l ow fro m th e EAV co de a t the start of
the line to the SAV code at the start of active video for the
line.
7.10 GENLOCK MODE
In Gen lock mod e, the EVO is not synchroniz ation maste r
but receives frame timing signals on VO_IO2. The EVO
operates in Genlock mode when SYNC_MASTER = 0,
EVO_CTL. EVO_ENABLE = 1 and EVO_CTL. GEN-
LOCK = 1.
The active edge can be programmed using the VO_CTL.
VO_IO2_POS bit. T he initial transition of the frame tim-
ing sign al on VO_ IO2 cau s es the Frame Line Co unter t o
be set to the value in VO_FRAME. FRAME_PRESET.
After reaching FRAME_LENGTH, the Frame Line
Counter starts counting again from 1.
EVO_SLVDLY. SLAVE_DLY is typically used to com-
pensate for any delay in the frame timing source or inter-
nal pipe line synchronizat ion anywhere in a line. Inte rnal-
ly, the active edge of VO_IO2 is d elayed by SLAVE_DLY
VO_CLK clock cycles. Typically, it will allow FRAME_
PRE SET to be lo ad ed at the be ginn ing of a ne w li ne.
With correct values of SLAVE_DLY and
FRAME_PRESET loaded, the PNX1300 can generate
frames totally synchronized with the active edge of
VO_IO2. All the internal MMIO registers (except of
course VO_CTL) should be programmed with the same
values as for SYNC_M ASTER m ode. See Figure 7-16.
In Gen lock mo de, th e E VO i s fr ee-r unn ing a cco rdi ng to
the valu es pr ogramm ed in its i nter nal regis ters be fore th e
initial VO_IO2 active edge . Just after receiving the active
edge that will synchronize the EVO, output values may
be erroneous for sever al V O_C LK cycle s, but it i s gu ar-
anteed that th e nex t fram e will b e correct.
After the first synchronizing edge, if the next one hap-
pens according to the values programmed in the EVO
MMIO registers, no change will appear in the output tim-
ing of the EVO. If the active edge of VO_IO2 does not
match the programmed value, a new synchronization
phase is perfor m ed.
Typically, this is programmed as follows: SLAVE_DLY is
loaded w ith the number of clock cycle s for one video line
minus the number of delay cycles used by the EVO to
synchronize itself. FRAME_PRESET is programmed
with the value 2. With this programming, the active edge
of VO_IO2 will happen just before the first byte ( pream-
ble) of the first line.
Th e first a ctiv e edge of V O_I O2 is dela yed i ntern all y by
SLAVE_DLY VO_CLK cycles so that it appears internally
just before the start of the second line minus the internal
EV O p ipel in e de la y. Afte r thi s inte r nal pi pe li ne delay, the
line counter is loaded by FRAME_PRESET, ( ‘2’), and the
EVO start s sending data f or line 2.
For the next frame, if the internal EVO programming
matches the VO_IO2 timing, the EVO will appear to start
4 19 20 265 266 283 1 4
One Frame
One Line
Field 2Field 1
Blanking Blanking
Active Vi de o Ac tive Video
Vertical
Sync
Video
Lines
NTSC
PAL
263 264 282 525 3
Blanking Blanking
23 310 311 312 313 335 336 623 624 625 1
221
VO_IO2
Figure 7-14. EVO VO_IO2 timing in FIELD_SYNC mode.
Image Line: Image Width
Blanking
Image Width, Pixels
Field Width, Pixels
SAVEAV
VO_IO1
Image Data
EAV
Blanking
Figure 7-15. EVO VO_IO1 timing in FIELD_SYNC mode.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-9
the fi rs t byte of the fi rst lin e j us t afte r the V O _IO2 ac ti ve
signal.
7.11 DATA TRANSFER TIMING
In data-streaming and message-passing modes, the
EV O supp lie s a stream of 8-bi t data . No data sele ction or
dat a in te rpr e tat io n is do ne , an d dat a is tr ans fer red at th e
ra te of one b yte pe r VO _CL K. D ata is cloc ked out on the
positive edge of VO_CLK.
When data-streaming mode is enabled and
EVO_ENABLE = 1 and SYNC_STREAMING = 1, the
VO_IO2 si gnal in dicates a d ata-valid condit ion. Thi s s ig -
nal is as se rte d wh en the EV O st a rts outp ut tin g v al id data
(t ha t is , d at a -st ream in g m ode is e nab l ed and vi de o out is
ru nn in g), and is de- ass ert ed when data- str ea min g mod e
is disabled. As shown in Figure 7-17, th e data-valid sig-
nal on VO_IO2 is asser ted just bef ore the first valid byte
is present on VO_DATA[7:0], and is de-asserted just af-
ter the l ast valid byte was sent , or if an HBE error is si g-
nal ed . All tr an siti on s of VO_IO 2 oc cur on th e ris in g edg e
of VO_CLK. The VO_IO1 signal generates a pulse one
VO_CLK cycle before the first valid data is sent. The
transitions of VO_IO1 occur on the rising edge of
VO_CLK and last for one VO_CLK cycle.
In message-passing mode, the EVO issues signals on
VO_IO1 and VO_IO2 to indicate the start and end of
messages.
When message passing is started by setting VO_CTL.
VO_ENABLE, the EVO sends a Start condition on
VO_IO1. When the EVO has transferred the contents of
the buffer, it sends an End condition on VO_IO2, sets
BFR1_EMPTY, and interrupts the DSPCPU. The EVO
stops, and no further operation takes place until the
DSPCPU sets VO_ENABLE again to start another mes-
sag e, or un til t he DS CPU ini tiate s ot her EVO op era tion.
The timing for these signals is shown in Figure 7-18.
7.12 IMAGE DATA MEMORY FORMATS
7.12.1 Video Image Formats
The EVO accepts memory-resident video image data in
three formats: YUV 4:2:2 co-sited, YUV 4:2:2 inter-
spersed, and YUV 4:2:0. These formats are shown in
Figure 7-19 through Figure 7-21.
EAV
Image Data
EAV
Line 525/62 5
One Frame
VO_IO2
Delay SLAVE_DLY in VO_C LK cycles
Line 1 Line 2 Line FRAME_PRESET Line 525/6 25 Line 1
EAV
Line counter loaded by FRAME_PRESET
Figure 7-16. Genlock mode.
VO_DATA[7:0]
VO_IO2
VO_IO1
VO_CLK
XX XX D0 D1 D2 D3 D4 D5 Dk XX XX
DATA_VALID
Figure 7-17. Data-streaming valid data signals.
VO_DATA[7:0]
VO_IO1
VO_IO2
VO_CLK
XX D0 D1 D2 D3 D4 D5 D6 D7 XX XX
Star t of
message
End of
message
Figure 7- 18. Messag e-passing STAR T and END signa ls.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-10 PRELIMINARY SPECIFICATION
7.12. 2 Planar Storage of Video I mage Data i n
Memory
Video image data is stored in memory with one table for
each of the Y, U and V components. This is called planar
format. This is shown in Figure 7-22 for YUV 4: 2:2 image
dat a. T he EV O merg es by tes f rom ea ch of t he thr ee t a-
bles to generate the CCIR 65 6-compatible output data.
The U and V tables have the same number of lines but
half the number of pixels per line as the Y table. The
transfer is the same for YUV 4:2:0 format except the U
and V tables will be 1/4 the size of the Y table . The U and
V tables have the half the number of lines and half the
number of pixels per line as the Y table.
7.12.3 Graphics Overlay Image Format
Graphics overlay image data is stored in a pixel-packed
format in SDRAM. Grap hics images are stored in Y UV
4:2:2+alpha format . Figure 7-23 sho ws th is f ormat . The
YUV overlay area is always within the image output res-
olut i on . T h e EV O does no t upscal e t h e gr aphi cs o v erlay
image. If the EVO is upscaling the video image by 2 ×, the
graphics overlay must be provided in upscaled format.
Pixel data is a 16-bit data and follows endian-ness con-
v ention s bas ed on 16-b it dat a. Re fer to Appendix C, “En-
dian-ness” for details.
7.13 VIDEO IMAGE CONVERSION
ALGORITHMS
Th e m em o ry v id eo im ag e d ata f o rm ats are c on vert e d to
th e outp ut YUV 4:2 :2 co -sit ed fo rmat and opti onal ly up -
scaled 2× horizontally. The conversion algorithms are
det a ile d be lo w .
Chromi nance (U,V )
samples Luminance
samples
Figure 7-19. YUV 4:2:2 co-sited format.
Chromi nance (U,V)
samples Luminance
samples
Figure 7-2 0. YUV 4:2:2 int erspersed format.
Chrominance (U,V)
samples Luminance
samples
Fig ure 7-21. YUV 4:2:0 format.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-11
7.13.1 YUV 4:2:2 Interspersed to YUV 4:2:2
Co-sited Conversion
The EVO accepts data from SDR AM in eith er YUV 4:2:2
co-sited, YUV 4:2:2 interspersed, or YUV 4:2:0 inter-
s pers ed for m ats. If th e in pu t da ta i s in YUV 4: 2: 2 or YUV
4:2:0 interspersed format, interspersed-to-co-sited con-
version is performed to generate co-sited output. The
EVO us es a 4- t ap, ( –1, 5 , 13, –1)/16 filter to perform this
conversion on the U and V chroma data. Figure 7-24
shows an example of interspersed to co-sited conversion.
7.13.2 YUV 4:2:0 to YUV 4:2: 2 Co-sited
Conversion
YU V 4:2 :0 to YUV 4: 2 :2 co nv ersi o n is a var iat i on of YU V
4:2:2 interspersed-to-co-sited conversion. The YUV
4: 2:0 format has the U a nd V pix els pos it i oned be t ween
lines a s well as between pixels within each line . It al so
has half the number of U and V pixels compared to YUV
4:2:2 formats. The EVO converts YUV4:2:0 to YUV 4:2:2
co-sited by using the U and V chrominance pixel values
for bot h surrounding line s and converting the resulting U
and V pixels from interspersed to co-sited format. This is
shown in Figure 7-25. For true vertical re-sa mpling of U
and V , th e PN X13 00 I CP un it can be inv oke d on U and
V to conve rt from YUV 4:2:0 to YUV 4:2:2 interspersed.
7.13.3 YUV-2x Upscaling
In the YUV-2× modes, the EVO performs 2× horizontal
upsca lin g of the Y UV data fr o m SD R AM. No ve r ti cal up -
scaling is performed. The width of the result image
(IMAGE_WIDTH) should be an even number. Upscaling
is perf or m ed by 4-tap fil t eri ng . For all 3 memor y fo rmat s,
Y lumin ance d ata is up scale d usin g a (–3,19,19,–3)/32
filter to generate the missing output pixels. Output pixels
at the same location as the input pixels use the corre-
s ponding input pixel values, as shown in Figure 7-26.
The U and V chrominance values are generated in the
same way as th e Y lumi nanc e sig nal for 2× upscaling, as-
s uming that both the input and output use YUV 4 :2:2 co-
si te d c h r om in an c e c od i n g . Th e U an d V ou t p ut pi xels a t
the same l ocati on as t he U an d V inp ut pi xels use the cor-
responding input pixel values. The U and V output pixels
betw een the U and V i nput pi xels are g ener ated u sing the
(–3,19,19,–3)/32 filter, as shown in Figure 7-26.
If the input chroma is interspersed, a (–1,13,5,–1)/16 fi l -
ter i s use d t o ge nera t e the U and V out pu t pi xels th at are
dis pl ac ed by half a Y pix el from th e U and V in pu t pixel s,
and a ( –1,5,13,–1)/16 fil t er is us ed t o ge ner a te th e addi -
tional upscaled U and V output pix els that are displaced
by 1. 5 pixels from the U and V input pixels . This is shown
in Figure 7-27.
7.13.4 Pixel M irrori ng for Four-tap Filters
The EVO uses a 4- tap fil ter fo r ups caling an d for con ver t-
ing from interspersed to co-sited format. O ne extra pixel
is n eeded at the be ginning and two at t he end of each
line processed by this filter. These pixels are supplied
WIDTH pixe ls
HEIG HT lines
pix0 pix1 pix2 pix
W–1
• • •
Y_BASE_ADR
WIDTH/2 pixel s
HEIGHT lines
pix0 pix2 • • •U_BASE_ADR
(Repeated for
V_BASE_ADDR,
V_OFFSET)
Y_OFFSET
U_OFFSET
Figure 7-22. Image storage in planar memory format
for YUV 4 :2:2.
Fig ure 7-23. YUV 4:2:2+alpha overlay format.
OVERLAY_WIDTH pixels
OVERLAY_HEIGHT lines
pix0 pix1 pix2 pix
W–1
• • •
OL_BASE_ADR
OL_OFFSET
Y0 U0 Y1 V0
YUV 4: 2:2+α
αα
Chrominance (U,V)
samples Luminance
samples
Input Pixels: YUV
Output Pixels: YU’V’
Co-sited Chrominance Output:
U’,V’ = (–1,5,13,–1)/16×U,V
Figure 7-24. Y UV interspersed to co-sited conversion.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-12 PRELIMINARY SPECIFICATION
automatically by mirroring the first and last pixels of each
line. For example:
•Ou tput pix e l 1 use s in pu t pix e l 1 to gener ate its valu e.
(s am e loc a tio n, no fi ltering).
•Output pixel 2 uses pixels 1,1, 2 and 3 to generate its
value.
•Output pixel 3 uses pixel 2 to ge nerate it s value.
•Outpu t p ixel 4 pixel u se s pi xels 1, 2, 3 an d 4, etc.
Chro mi nance (U,V)
samples Luminance
samples
Input Pixels: YUV 4:2:0
Output Pixels: YU’V’ 4:2 :2
Co-sited Chrominance Output:
U’,V’ = (–1,5,13,–1)/16×U,V
Y0,0; U0,0; V0,0
Y0,0
U0,0; V0,0
Y0
Y1
Y2
Y3
U0, V0
U2, V2
Y0, U0, V0
Y1, U0, V0
Y2, U2, V2
Y3, U2, V2
Figure 7- 25. YUV 4 :2:0 to YUV 4:2:2 co-sited conver sion.
Chrominance (U,V)
samples Luminance
samples
Input Pixels: YUV
Output Pixels: Y’U’V’
Output Location Same
As Input Pixel: Y’U’V’ = Y UV Upscaled Luminance Output Between
Input Pixels: Y’ = (-3,19,19,- 3)/32×Y
Upscaled Chrominance Output Between
Input Pixels: U’,V’ = (-3,19,19,-3)/32 × U,V
Figure 7-26. 2x upscaling of Y pixels.
Chrominance (U,V)
samples Luminance
samples
Input Pixels: YUV
Output Pixels: Y’U’V’
Co-sited Chrominance Output
U’,V’ = (–1,13,5,–1)/16×U,V
Co-sited Chrominance Output
U’,V’ = (–1,5,13,–1)/16×U,V
Upscaled Luminance Output Same
As Input Pixel: Y’ = Y
Upscaled Luminance Output Between
Input Pixels: Y’ = ( -3,19,19,-3)/32 × Y
Figure 7-27. 2x upscaling of U and V with interspersed to co-sited conversion.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-13
•...
•Output pixel 2N–2 uses pixels N–2, N–1, N, and N–1
to ge ner ate i t s valu e.
•Output p ixel 2N–1 uses pixel N t o generate i ts va lue.
•Output pixel 2N uses pixels N–1, N, N, and N–1 to
gener ate its value.
Figure 7-28 s how s an exam ple of six pi xels ups cal ed to
12 pixels.
7.14 EVO OPERATING MODES
EVO operating modes belong to two groups as follows:
•Video-refresh modes
•Data-transfer modes
Data-transfer modes are further broken down into data-
streaming mode and me ssage-passing mode.
Th e opera ti ng mode i s set by the V O_CT L. M OD E field
and the VO_CTL. OL_EN (overlay enable) control bit.
The VO_CTL. MODE field determines video-refresh,
mes sage - p assi ng or d ata-s tream ing mod e. It f u rt her de -
fines the video i mage format and whether or not 2× hori-
zontal upscaling takes place. The OL_EN bit determines
whether a video-refresh mode has a graphics overlay
present. The modes are s hown in Table 7-5.
7.15 VIDEO PROCESSING
If en able d, the PNX 13 00 im plem e nts fun ction s for chro -
ma keying, alpha blending and programmabl e clippi ng,
as described in this section.
7.15.1 Alpha Blending
If enabled by setting EVO_ENABLE = 1 and
FULL_BLENDING = 1, the EVO provides full 129-layer
alpha bl ending of a background vi deo image wit h a fore-
gr ou nd g rap hi cs o verl ay ima ge . If ei th er bi t is 0 , the EVO
implements the cruder 25% step alpha blending resolu-
tio n o f th e T M-1000. A lpha blending can operate in con-
junction with chroma keying, as described in
Section 7.15.2.
Alpha blending combines a graphics overlay image with
the video image according to an alpha value provided
with each overlay pixel. The graphics overlay is taken
fr om a pixe l-p ac ked YUV 4 : 2:2+α data struc tur e i n m em-
ory . In th e YUV 4 :2:2+α format, each pixel has a single
α-bit su pplied as the LSB of t he U and V pixels . The U
byte LSB corresponds to the alpha for pixel Y0, the V
byte LSB for pixel Y1, respectively. When the α-bit is ‘0’,
the ALPHA_ZERO register supplies the actual 8-bit α
value. When the α-bit is ‘1’, the ALPHA_ONE register
supplies the 8-bit α val ue. In the YU V 4:2: 2 for m at, only
one set of U and V valu es is suppli ed for the two Y pixe ls,
Y0 and Y1. In this case, the alpha bit in U0 determines
the alpha value f or U, Y0 and V . The alpha blend bit in
V0 only sets the alpha value for Y1 and does n ot affect
the U or V values.
The EVO uses the 8-bit content of the selected alpha
blending register (ALPHA_ZERO or ALPHA_ONE) to
determine the amount by which the overlay plane is
mer ged wit h the imag e plane as follows . Th e le ast-si gni f-
ic ant 7 bits of the selected blending r egis ter encode 128
Table 7-5. EVO Operating Modes
Mode Function Explanation
Video-refresh modes
0 YUV 4:2:2C-1×YUV 4:2:2 co-sited, no scaling
1 YUV 4:2:2I-1×YUV 4:2:2 interspersed, no scaling
2 YUV 4:2:0-1×YUV 4:2:0, no scaling
3 Reserved
4 YUV 4:2:2C-2×YUV 4:2:2 co-sited, horizontal 2 ×
upscaling
5 YUV 4:2:2I-2×YUV 4:2:2 interspersed, horizontal
2× upscaling
6 YUV 4:2:0-2×YUV 4:2:0, horizontal 2× upscaling
7 Reserved
Data-transfer modes
8data
streaming c ontinuous tra nsm issi on of raw 8- bit
data with valid data pulse and level
timing signals
1
Input Pixels: Y
Output Pixels: Y’
23456
135791124681012
Y’=Y1 Y’=Y2 Y’=Y3 Y’=Y4 Y’=Y5 2N–1:
Y’=Y6
Y’=F(Y1,Y1,Y2,Y3)
Y’=F(Y1,Y2,Y3,Y4)
Y’=F(Y2,Y3,Y4,Y5)
Y’=F(Y3,Y4,Y5,Y6)
Y’=F(Y4,Y5,Y6,Y6)
2N:
Y’=F(Y5,Y6,Y6,Y5)
Figur e 7-28 . Mirrori ng pixels in 2 x u ps ca lin g.
9message
passing trans miss ion of raw 8-bit data with
ST MSG and END MS G timing sig -
nals
0xA
—
0xF
Reserved
Table 7-5. EVO Operating Modes
Mode Function Explanation
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-14 PRELIMINARY SPECIFICATION
blendi ng l ev els from 0 to 0 x 7 F. The M SB is u se d t o t urn
on blendi ng ( M SB = ‘0’) or to selec t the ov er lay plan e as
th e only outp ut ( MSB = ‘1’), s o all va lues betw een 0x80
and 0xFF select 100% overlay. Therefore, the total num-
ber of blending le vels is 129: 128 variable blending val-
ues f rom 0 to 0x 7F plus one ‘blending’ va lue fro m 0x 80
to 0xFF for 100% overlay. An alpha value of 0 selects
100% im age pl ane an d 0% o v e rl ay. Simi lar ly , a valu e of
0x40 selects 50% image and 50% overlay blending.
Th e eq uations f o r t he bl ending a re ill ustr a t e d below .
7.15.2 Chroma Keying
If the EV O_ENA BLE and KEY_ ENABLE bits are se t to
‘1’ in EVO_CTL the PNX1300 activates chroma keying.
Th e grap hi cs o verla y is tak en fro m a p ix el-pa cke d Y UV
4:2:2+α data structure in memory. The EVO_KEY regis-
ter provides the value which signifies full transparency
for the overlay. The overlay values (Y, U and V) are com-
par ed to t he va lues stor ed in bit -fiel ds of the EV O_K EY
register. EVO_KEY has three 8-bit fields: KEY_Y,
KEY_U a nd K EY_V, which s tore the values to be com-
par ed to the Y, U, an d V comp onents , res pectiv ely, of the
overlay for chroma keying. Bits that correspond to bits
set in M A S K_Y a nd M A SK_U V ar e ignored for th e com -
parison. When there is an exact match between the pixel
value and the v alue i n EV O _KEY ( dis r e gar di ng any bi ts
mas ked by MA SK_Y and MASK_UV), then the ov erlay
value is not present in the output stream, resulting in full
transparency.
The mask bits in EVO_MASK provide for varying de-
gre es of pre c isio n in the ch roma -k ey mat chin g proc ess .
The EVO_MASK. MASK_Y field can mask from 0 to 4
LSBs of the overlay Y component during the chroma key
process. For example, setting MASK_Y = 1 eliminates
the inf luence of the LSB of KEY_Y in the keying process.
This can be used to widen the range of key matching to
account for irregularities in the chroma-key video sign al.
Likewis e, EVO _MASK. MASK_UV is use d to m ask fr om
zero to four LSBs of the overlay U and V components
during the chroma key process. For example, setting
MASK_UV = 1 eliminates the influence of the LSB of
KEY_U a nd KEY_V in the keyi ng process.
7.15.3 Programmable Clipping
If EVO_CTL. CLIPPING_ENABLE = 1 the EVO performs
fully-compliant programmable clipping. Clipping is per-
for med as the l ast s tep of the video pipe lin e, aft er chrom a
k eying an d alp ha bl ending. I t is appli ed on ly on th e imag e
areas (Field 1 and Field 2) defined by IMAGE_WIDTH,
IMAGE_HEIGHT, IMAGE_VOFF and IMAGE_HOFF in-
side the Active Video Area. Blanking values are not
clipped.
The EVO_CLIP MMIO register stores four 8-bit fields
used to clip output components. The Y output compo-
nent is clipped between the values stored in
LOWER_CLIPY and HIGHER_CLIPY. A value less than
or equal t o LOWER_CLIPY is forced t o LOWER_CLIPY
and a va lu e great er tha n or equa l to H IGH ER _CLIP Y is
force d to HIGHER_ CLI PY.
The same behavior is implemented for U and V with the
values stored in the LOWER_CLIPUV and
HIGHER_CLIPUV fields.
This mode allows fully-compliant 16 to 235 Y clipping
and 16 to 240 Cb and Cr clipping to be programmed.
These a re the default values of the EVO_CLIP regis ter
after reset.
If CLIPPING_ENABLE = 0, the EVO clips Y, U and V be-
tw een th e def ault val ues 16 and 2 40, as i t is impl ement ed
in the TM-1000. When LOWER_CLIP{Y,UV} registers
are s et t o ‘0’ and HIGHER_CLIP{Y,UV} registers are set
to ‘255’, no clip ping is pe r formed .
7.16 MMIO REGISTERS
Th e MM IO register s are in two g roup s:
•VO registers — control basic VO functions (those
shared with the TM-1000 VO unit)
•EVO registers — control new EVO unit functions
(th os e new in TM -1100 / TM -130 0/P NX 1 30 0)
VO MMIO registers are shown in Figure 7-29. VO MMIO
register names are prefixed with “VO_”. Gen erall y, their
functionality is unchanged except where noted in the text
(see for instance, Section 7.16.1). The register fields a re
described in Table 7-6, Table 7-7 and Table 7-8. They
are discussed in section s7.16.1 through 7.18.1.
EVO MMIO registers are shown in Figure 7-30. EVO
MMIO register names are prefixed with “EVO_”. The
EVO_CTL register selectively enables new TM-
1100/TM-1300/PNX1300 functions. The register fields
ar e de scri be d i n Table 7-9 and Table 7-10. They a r e di s-
cu s se d in se c t io ns 7.16.4 and 7.16.5.
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read, and writ-
ten as ‘0’s.
if alpha[7] = 1 then
output[7:0] = overlay[7:0]
else output[7:0] = (alpha[6:0] · overlay[7:0] + (alpha[6:0] + 1) · image[7:0]) >> 7
(or) output[7:0] = (alpha[6:0] · (overlay[7:0] – image[7:0]) >> 7) + image[7:0]
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-15
VO_STATU S (r)0x10 1800
MMIO_BASE
offset:
VO_CLOCK (r/w)0x10 1808
VO_FRAME (r/w )0x10 180C
VO_FIELD (r/w)0x10 1810
FREQUENCY
FRAME_PRESET
F2_OLAP
VO_CTL (r/w)0x10 1804 MODE
FIELD_2_START
F2_VIDEO_LINE
VO_LINE (r/w)0x10 1814 VIDEO_PIXEL_START
VO_I MAGE (r /w)0x10 1818 IMAGE_HEIGHT
VO_YTHR (r/w)0x10 181C Y_THRESHOLD
VO_OLSTART (r/w)0x10 1820 OL_START_LINE
VO_OLHW (r/w)0x10 1824
OL_START_PIXEL
RESET
SLEEPLESS
CLKOUT
SYNC_MASTER
VO_IO1_POS
VO_IO2_POS
OL_EN
BFR1_ACK
BFR2_ACK
HBE_ACK
URUN_INTEN
YTR_INTEN
URUN_ACK
YTR_ACK
LTL_END
VO_ENABLE
31 0371115192327
VO_YADD (r/w)0x10 1828 Y_BASE_ADR or BFR1BASE_ADR
VO_UADD (r/w)0x10 182C U_BASE_ADR or BFR2BASE_ADR
VO_VADD (r/w)0x10 1830 V_BASE_ADR or SIZE1
VO_OLADD (r/w)0x10 1834 OL_BASE_ADR or SIZE2
VO_VU F (r/w)0x10 1838 U_OFFSET(16)
VO_YOLF (r/w)0x10 183C Y_OFFSET(16)
V_OFFSET(16)
31 0371115192327
FRAME_LENGTH
F1_VIDEO_LINEF1_OLAP
FRAME_WIDTH
IMAGE_WIDTH
IMAGE_VOFF IMAGE_HOFF
GLOBAL ALPHA 1
OVERLAY_HEIGHT OVERLAY_WIDTH
OL_OFFSET(16)
GLOBAL ALPHA 0
BFR2_INTEN
HBE_INTEN
BFR1_INTEN
CLOCK_SELECT
PLL_S
PLL_T
reserved
31 0371115192327
31 0
CUR_Y(12) 371115192327 CUR_X(12)
BFR1_EMPTY
BFR2_EMPTY
HBE
URUN
YTR
FIELD2
VBLANK
1
Indic ates EVO functionality
Fig ure 7-29. EVO MMIO registers.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-16 PRELIMINARY SPECIFICATION
7.16.1 VO Status Registe r (VO_STATUS)
The VO_STATUS register is a read-only register that
s hows the current status of the E VO. Its fields are shown
in Figure 7-29 and Table 7-6.
VO_ STATU S[4] is no w har d-wire d to ‘1’. Th is al low s sof t-
ware to d eter min e if t he un it is a n EV O un it (con taini ng
extra MMIO registers) or a TM-1000 VO unit, as follows.
In the TM-1000, this bit is a copy of the HBE flag
(VO_ STAT U S[5 ]). In the EVO unit, it is hard-w ire d to ‘1’.
Softw a re can us e this bi t to deter mine th e ty pe of (E ) VO
unit by clearing the HBE bit then reading
VO_ STATU S[4] . If t he bit remain s ‘1’, the unit is an EVO.
Table 7-6. VO_STATUS — status reg ister fields
Field Description
CUR_Y Current Y.
Image line index of the current line in the current field being output by the EVO. CUR_Y reflects the current state of
the Image Line Counter. CUR_X and CUR_Y form a single 24-bit output data byte counter (CUR_X is the counter
LSBs) when the EVO is in data-streaming or message-passing mode. This counter reflects the status of the SIZE
counter for the currently active buffer. The two LSBs of this counter are not valid for reading during transfers; only
the upper 22 bits (the word count) are valid.
CUR_X Current X.
Image pixel ind ex of the most-recently-output pixel. CUR_X reflects the current state of the Image Pixel Counter.
BFR1_EMPTY
BFR2_EMPTY Buffers 1 and 2 Empty.
These bits are valid in video-refresh, data-streaming and message-passing modes.
•In video-refresh modes, only Buffer 1 is used. BFR1_EMPTY indicates that the last byte of a field has been
transferred. It is actually raised at the completion of the transmission of the Overlap area of the field, as shown in
Figure 7-31. At this point, software should assign a new field of imagery to {Y,U,V}_BASE_ADR and perform a
BFR1_ACK. If BFR1_EMPTY is not cleared by BFR1_ACK before the active video area of the next field starts to
be emitted, the EVO sets the URUN bit.
•In data-streaming mode, BFR1_EMPTY and BFR2_EMPTY indicate that the last byte in their corresponding
buffer has been transferred . When BFR1_EMPTY or BFR2_EMPTY is set, transf er stops from the corresponding
buffer.
•In message passing mode, BFR1_EMPTY signals completion of message transmiss ion.
These bits cause an interrupt if their interrupt-enable bits are set. One interrupt per buffer is signaled.
HBE Highway B andw i dth Error.
HBE is set when the highway f ails to respond in time to a highwa y read request and data was not ready in time to be
set on EV O data lines. HBE can be set in both image- and data-transfer modes. HBE indicates insufficient band-
width was requested from the highway arbiter.
1 EVO unit indicator.
This bit allows software to determine if the unit is an EVO (containing extra MMIO registers) or a TM-1000 VO unit.
In the TM-1000, this bit is a copy of the HBE flag. In the EVO unit, it is hard-wired to ‘1’. Software can easil y deter -
mine the type of video output u nit by clearing the HBE bit then reading this bit.
YTR Y threshold.
In video-refresh modes, YTR indicates that the Image Line Counter value is equal to the Y_ THRESHO LD value in
VO_YTHR. The Y_THRESHOLD value can be set to provide an interrupt on any line in the valid image area.
URUN Underrun.
In video-refresh and data-streaming mode, this bit indicates that the CPU did not perform an acknowledge to indi-
cate updated address pointers for the next field or buffer in time for continuous image or data tr ansfer. URUN causes
an inter rup t if the corres pond ing interru pt-enable c ond ition is set.
•In video-refresh modes, URUN indicates that the SAV code marking beginning of active video has been gener-
ated without BFR1_ACK being set by the CPU. (Setting BFR1_ACK to ‘1’ clears BFR1_EMPTY). In this case,
video refresh continues with previous address pointers.
•In data-streaming mode, URUN indicates the last byte in the active buffer was transferred, and no BFR1_ACK or
BFR2_A CK occurred to enable the next buffer. In this case, transfer continues with previous address pointers.
FIELD2 Field 2 or Buffer 2 active.
•In data-streaming mode, FIELD2 = 0 when Buffer 1 is active; FIELD2 = 1 when Buffer 2 is active.
•In video- refr esh modes, FIELD2 indi cates that th e EVO i s acti vely sending out a video image for Field 2, as
defined by Figure 7-31.
VBLANK Vertical blanking.
Indicates that the EVO is in a vertical- blan king interval. VBLANK is asserted only in video-refresh modes.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-17
7.16.2 VO Control Register (VO_C TL)
Th e V O _C TL r e gi st er se ts the o per at in g m o de, enables
interrupts, clears interrupt flags, and initiates EVO oper-
ations. Its fields are unchanged from the TM-1000, as
shown in Figure 7-29 and Table 7-7, however the pre-
cise f unctiona lity i mplem ente d by a fi eld ma y be ch anged
if PNX1 300 fun ct io nali t y i s enab l ed b y s of tw are . It s ha rd-
ware reset value is 0x32400000 which sets
CLOCK_SELECT = 3, PLL_S = 1 and PLL_T = 1, and
all other bits to ‘0’. To ensure compatibility with future de-
v ices, any und efined MM IO bits should be ignored w hen
read, and written as ‘0’s.
Table 7-7. VO_CTL register fields
Field Description
RESET Software reset of the EVO.
The recommended software reset procedure is as follows.
•Write the desired VO_CTL state with the RESET bit set to ‘1’.
•Write the desired VO_CTL state word, this time with the RESET bit cleared to ‘0’. Both writes should have
VO_E NABL E s et t o 0 .
•Finally, enable the newly selected mode by setting VO_ENABLE. This step should be done last, as a separate
transaction.
Aft er a soft w are res et, 5 VO_CLK c lock cy c les a re required to stabilize the internal circuitry (before enabling EVO).
Note: A hardware reset clears the CLKOUT and SYNC_MASTER bits and puts VO_CLK, VO_IO1, and VO _IO2 in
the input state. This results in a VO_CTL value of 0x32400000. In contrast, a software reset does not change
device registers. So a software reset results in a state as specified by the VO_CTL word value written during the
above-descr ibed pr ocedur e.
SLEE PLESS Di sable power management.
If SLEEPLESS = 1, power-down of the EVO is prevented during global PNX1300 power-down.
CLOCK_SELECT Clock select.
00 — Select PLL VCO output as the VO_CLK source.
01 — Select PLL feedback loop divider output as VO_CLK source.
10 — Select PLL input divider output as VO_CLK source.
11 — Select DDS output directly as VO_CLK source, bypassing the PLL altogether. (Hardware reset default.)
PLL_S PLL input divider division ratio.
A value of k selects division by k+1. The hardware reset defaul t =1, causing division by 2.
PLL_T PLL feedback loop divid er division rati o.
A value of k selects division by k+1. The hardware reset defaul t =1, causing division by 2.
CLK OUT Clock output.
•When CLKOUT = 1, the EVO clock generator is enabled, and V O_CLK is an output.
•When CLKOUT = 0, VO_CLK is an input, and EVO clock is provided by the external device. (Hardware re set
default.)
SYN C _M AST ER Sync maste r.
•When set, VO_IO1 and VO_IO2 are outputs. In video-refresh modes, the EVO generates horizontal and frame
timing signals on VO_IO1 and VO_IO2 respectively. In message-passing mode and data-streaming mode, this
bit should always be set so that VO_IO1 and VO_IO2 generate START and END message signals respectively.
•When zero, VO_IO2 is an input. (Hardware reset default.) In video-refresh modes, VO_IO2 serves as the frame
time re ference. The act ive edge is selected by VO_IO2_POS.
VO_IO1_POS
VO_IO2_POS Polarity of VO_IOx_POS .
VO_IO 1_P OS currentl y has no functi on.
VO_IO 2_POS determines the input polar ity of VO_IO 2.
•When ‘0’, the corresponding input triggers on the negative (high-to-l ow) tra nsition of the input signal.
•When ‘1’, the input trigger s on the positi ve (low-to-hi gh) transitio n.
OL_EN Overlay Enable.
Enables the YUV overlay function in video-refresh modes.
MODE Major operating mo de.
Defines the video output major operating mode, as listed in Table 7-5 on page7-13 .
BFR1_ACK
BFR2_ACK Buff er 1 and Buffer2 acknowledge .
When active in data-transfer modes, writing a ‘1’ t o BFR1_ACK clears BFR1_EMPTY and enables Buf fer1 for
trans fer until BFR1_EMPT Y is set. Wr iting a ‘0’ to BFR1_ACK has no eff ect. BRF2_ACK operates similarly for
Buffer 2. Writing a ‘1’ to VO_ENABLE in data-streaming mode is the same a s w rit ing a ‘1’ to both BFR1_ACK and
BFR2_ACK, and enables both buffers 1 and 2 for transfer. Writing a ‘1’ to VO_ENABLE in message-passing mode
is the same as writing a ‘1’ to BFR1_ACK, and enables Buff er1 for transfer. BFR2_ACK is not used in message-
pass ing mode, since o nly Buffer1 is used .
HBE_ACK
URUN_ACK Acknowledge HBE or URUN.
Writing a ‘1’ to the se bits clear s the HB E or URUN flags and resets their cor r esp ondi ng inter r upt conditions.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-18 PRELIMINARY SPECIFICATION
7.16.3 VO-Related Registers
The VO-related registers and their fields are shown in
Table 7-8. Thei r fiel ds are unchanged from t he TM -1000,
however their function may vary depending upon the
PNX1300 features that are selectively enabled by
EVO_ CTL (s ee Section 7.16.4).
YTR_A CK Acknowledge Y threshold.
Writing a ’1’ to this bit clears the YTR flag and resets its interrupt condition. YTR signals the CPU to set new point-
ers for the next field. If YTR_ACK is not received by the time the active image area for the next field starts, the
URUN flag is set. Data transfer continues with the old pointer values.
BFR1_INTEN
BFR2_INTEN
HBE_INTEN
URUN_INTEN
YTR_INTEN
Enable interrupt conditions.
Enable corresponding interrupts to be generated when the BFR1_EMPTY, BFR2_EMPTY, HBE, URUN (under-
run/end of transfer), and YTR (end of field/buffer) flags are set, respectively.
Note: BFR2_INTEN, URUN_INTEN, YTR_INTEN must be 0 in message passing mode.
LTL_END Little-endian.
Specifies that data in SDRAM is stored in little-endian format. This only affects the overlay packed-image format
interpretation in video-refresh modes. Refer to Appendix C, “Endian-ness,” for details on byte ordering.
VO_ENABLE Enable the EVO to send image data or message data to its output.
Note: This bit should not be simultaneously asserted with the RESET bit. The correct sequence to reset and
enable the EVO is as follows.
•Set all VO_CTL control fields as desired, writing VO_CTL with RESET = 1, VO_ENABLE = 0.
•Retain all desired values of control fields, but rewrite VO_CTL with RESE T =0, VO_ENABL E =0.
•Finally, still re tain ing all des ir ed control fields, rewrite VO_ CTL w ith R ESET = 0, VO _ENAB LE = 1.
Settin g VO _ENABLE in video-r efresh modes sta rts the EVO sen din g image data beginning with the first pixel in
the image. Setting VO_ENABLE in data-streaming and message-passing modes st art s the EVO sending data
beginning with the first byte in Buffer 1. In video-refresh and data-streaming modes, VO_ENABLE remains set until
cleared by the CPU . In message-passing mode, V O_ENABLE is cleared when BFR1_EMPTY is set, indicating the
en d of message transfer.
Note: De-asserting VO_ENABLE in video-refresh modes causes SDRAM reads to stop , but sync framing and
BFR1_EMPTY generation and interrupts remain fully operational. The transmitted active image data is undefined
in this case. To fully halt video output, a software reset is required.
Table 7-7. VO_CTL register fields
Field Description
Table 7-8. VO register fIelds
Register Field Description
VO_CLOCK FREQUENCY VO_CLK frequency. See DDS equation in Figure 7-6, and PLL description in Section 7.19.
VO_FRAME FRAME_LENGTH Total number of lines per frame; the ending value of the Frame Line Counter; typically 525
or 625. Note: the Frame Line Counter counts from 1 to 525 or 625, consistent with
CCIR 656 line numbering.
FIELD_2_START Start line number in the Frame Line Counter; where the second field of the frame begins .
If non-interlaced pictures are desired, then the same value is programmed for Field 1 and
Field 2. Field 1 becomes F ram e1 and Field2 becomes Fr ame2 .
FRAME_PRESET Value loaded into the Frame Line Counter when frame timing edge i s r eceived on VO_IO2.
VO_FIELD F1_VIDEO_LINE Line number in the Frame Line Counter of the first active video line of Field1 of the frame .
F2_VIDEO_LINE Line number in the Frame Line Counter of the first active video line of Fiel d2 of the frame.
If non-interlaced pictures are desired, this is programmed to the same value as
F1_VIDEO_LINE
F1_OLAP Overlap of the SAV and EA V codes from Field 1 to Field 2. Ov erlap is defined as the delay
in lines from start of blanking fo r Field 2 until SAV and EAV codes for Fiel d2 are emitted.
Typical v alues are +2 for 525/60 and +2 for 625/50.
F2_OLAP Overlap in lines of the SAV and E AV code from Fiel d2 to Fiel d1. Ov erlap is defined as the
delay in lines from start of blanking for Field 1 until the SAV and EAV codes for Field 1 are
emitted. Typical values are +3 for 525/60 and –2 for 625/50. The negative value means
Field 1 blanking actually starts two lines before end of Fi eld2 of previous frame . This over-
lap is described in Table 7-4 on page7-6 , and illust rated in Figure 7-31.
VO_LINE FRAME_WIDTH Total line length in pixel s including blanking. Also the ending value for the Frame Pixel
Counter. Lines always begin with a horizontal blanking interval, and the image starts after
the blanking interval and runs to the end of the line.
VIDEO_PIXEL_START Pixel number in F rame Pixel Counter of starting pixel of active video area within the line.
Note: Must be even.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-19
VO_IM AGE IM AGE_HEIGHT Video Image height in lines.
IMAGE_WIDT H Video Image li ne (scaled) outpu t width in pixels. Must be even for upscaling by 2×.
VO_YTHR Y_THRESHOLD Threshold image line number in the Image Line Counter for the YTR interrupt.
Can be reprogrammed on a frame-by-frame basis.
IMAGE_VOFF Image vertical offset in lines from the top of the active video window.
IMAGE_HOFF Image horizontal offset in pixels from the start of the active video window.
VO_OLSTART OL_START_LINE Starting image line of YUV overlay within the image.
Zero indicates that the overlay starts at the same line as the image.
OL_START_PIXEL Starting image pixel of the YUV overlay within the image. ‘0’ indicates that the overlay
starts at same pixel as the image. Note: Must be even.
ALPHA_ONE Alpha blend value used for YUV 4:2:2+alpha format overlays when the alph a bit=1.
VO_OLHW OVERLAY_HEIGHT Height of the YUV overlay image in lines. Note: The height of the overlay should be chosen
such that it does not extend beyond the image area.
OVERLAY_WIDTH Width of the YUV overlay image in pixels. Note: Must be e ven.
ALPHA_ZERO Alpha blend value used for YUV 4:2:2+alpha format overlays when the alph a bit=0.
VO_YADD Y_BASE_ADR
BFR1BASE_ADR Y-component buffer address or Buffer 1 add ress.
•In video-refresh modes: Y-component starting byte address.
•In data-streaming and message-passing modes: Buf f er1 starting byte address. Note:
must be 64-byte aligned in data-streaming mode and 4-byte aligned in message pass-
ing mode.
VO_UADD U_BASE_ADR
BFR2BASE_ADR U-component b uffer address or Buff er 2 address.
•In video-refresh modes: U-component starting byte address
•In data-streaming mode: Buffer 2 starting byte address; must be 64-byte aligned
•Not used in message-passing mode
VO_VADD V_BASE_ADR
SIZE1 V-comp onent buffer a ddres s or Buffer 1 length .
•In video-refresh modes: V-component starting byte address
•In data-streaming and message-passing modes: Buff er1 length in bytes. Note: must be
a multiple of 64 in data-streaming mode. SIZE1 is limited to 24 bits.
VO_OLADD OL_BASE_ADDR
SIZE2 Overla y-image buffer address or Buffer2 leng th .
•In video-refresh modes: overlay-image starting byte address. OL_BASE can be repro-
grammed on a frame-by-frame basis.
•In data-streaming mode: Buffer2 length in bytes . Note: Must be multiple of 64 in data-
streaming mode; Not used in message-passing mode.
VO_VUF U_OFFSET Offset in bytes from start of one line to start of next line (16-bits unsigned).
V_OFFSET Offset in bytes from start of one line to start of next line (16-bits unsigned).
VO_YOLF Y_OFFSET Offset in bytes from start of one line to start of next line (16-bits unsigned).
OL_OFFSET Offset in bytes from start of one line to start of next line (16-bits unsigned).
Table 7-8. VO register fIelds
Register Field Description
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-20 PRELIMINARY SPECIFICATION
7.16.4 EVO Control Register (EVO_CTL)
PNX130 0 EVO features are enable d by s etting the ap-
propriate fields of the EVO_CTL register shown in
Figure 7-30. The register fields are described in
Table 7-9. If features are enabled, new PNX1300 the
functionality replaces TM-1000 functions.
The hardware reset value of EVO_CTL register is
0x10000000, which means that EVO functions are dis-
abled on reset and must be enabled by software. The MS
four bits indicate the EVO revision number.
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read, and writ-
ten as ‘0’s.
MMIO_BASE
offset:
EVO_MASK (r/w)0 x10 1844
EVO_CLIP (r/w)0 x10 1848
EVO_KEY (r/w)0x10 184C
EVO _ C TL (r/w)0x10 1840
CLIPPING_ENABLE
SYNC_STREAMING
FIELD_SYNC
KEY_ENABLE
EVO_ENABLE
31 0371115192327
31 0371115192327
FULL_BLENDING
1000 RESERVED
RESERVED KEY_Y
KEY_V KEY_U
HIGHER_CLIPUV LOWER_CLIPUV HIGHER_CLIPY LOWER_CLIPY
MASK_Y MASK_UV
GENLOCK
RESERVED
EVO_SL VD L Y (r / w )0x10 1850 RESERVED SLAVE_DLY
Figure 7-30. EVO MMIO registers.
Table 7-9. EVO_CTL Register Fields
Register Field Description
EVO_CTL EVO_ENABLE When set to 1, EVO features are enabled. When set to 0 (the hardware reset value), the EVO
behaves exactly like a TM-100 0 VO unit. Default: 0.
FULL_BLENDING Activates full 8-bit alpha blending when set to 1. When set to 0, only the original five TM-1000
blending levels are implemented (0%, 25%, 50%, 75%, 100%). Default: 0.
CLIPPING_ENABLE When set to 1, the values stored in EVO_CLIP ar e used for the clipping of output data. Otherwise,
TM-1000 default values (240 and 16 for Y, U and V) are used . Default: 0.
SYNC_STREAMING When set to 1 in data-streaming mode, VO_IO2 generates a DATA_VALID signal. See Section
7.18.2, “Data -tran sfer Mo des”. Default: 0.
FIELD_SYNC When set, VO_IO2 will generate frame synchronization signal that follows the field number in
SAV/EAV codes (Field1 gives a low VO_IO2, Field2 gives a high VO_IO2). Def ault: 0.
GENLOCK Activates Genlock mode when set to 1 and VO_CTL. SYNC_MASTER = 0. Default: 0.
KEY_ENABLE When set, this bit activates chroma key. The overla y values (Y, U and V) are compared to the val-
ues stored in the EVO_KEY register. Bits that correspond to bits set in MASK_Y and MASK_UV
are ignored f or the comparison. When there is an e xact match between the pixel value and the
value in EVO_KEY register (less the bits selected by MASK_Y and MASK_UV), then the overlay
value is not present in the output stream, resulting in full transparency.
The key is 24 bits (Y, U a nd V ar e 8 bits e ach). Default: 0.
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-21
7.16.5 EVO-Related Registers
As shown in Figure 7-30, four additional registers are in-
troduced in the PNX1300, as follows.
•EVO_MASK and EVO_KEY — used in chroma key
(see Section 7.15.2).
•EVO_CLIP — provides programmable clipping (see
Section 7.15.3).
•EVO_SLVDLY — used in Genlock mode (see
Section 7.10).
Th es e reg is t e rs are sh ow n i n Figure 7-30, an d th eir reg-
ister fields are shown in Table 7-10.
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when r ead, and writ -
ten as ‘0’s.
7.17 ENHANCED VIDEO OUT OPERATION
As described in Section 7.14, the EVO operates in either
video-refresh or data-transfer modes. The DSPCPU
s tarts the EV O b y setting the appropriate VO MMIO reg-
isters and the appropriate EVO MMIO registers.
VO_C TL . MODE mus t be s et to the ap pr o priate tr a ns fer
mode, appropriate addresses, address offsets, and im-
age timing registers and the associated control bits in the
control register must be set. Lastly, software sets
VO_CTL. VO_ENABLE to begin EVO operation. The
EVO transfers the image, data, or message as com-
manded. In video-refresh and data-streaming modes,
the EVO runs continuously. In message-passing mode,
the EVO runs only until the message has been trans-
ferred.
The EVO unit is reset by a PNX1300 hardware reset, or
by a soft ware rese t, as des cribe d in Table 7-7 for the RE-
SET bit.
The VO_CLK signal is normally set as an output to drive
the data transf er for all modes at a programmable ra te.
The VO_CLK signal can be an input or output, as con-
trolled by the VO_CTL. CLKOUT bit. When
CL KO UT = 1, VO_C LK is a n outp ut , and its freq ue nc y is
set by the VO_CLOCK register value. When
CLK OU T = 0, V O_ CLK is a n in put a nd th e EVO gene r-
at es data at the clo c k rate of the sender.
In video-refresh modes, the EVO receives or generates
horizontal and frame synchronization signals on the
VO_IO1 and VO_IO2 lines, as described in
Section 7.9.4.
7.17.1 Video Refresh Modes
In video-ref resh mode, th e EVO transfers an image from
SD RAM to the EVO p ort. Th e VO_CTL. MODE field d e-
fines the video image memory data format and deter-
mine s wh ether the E VO i s t o pe rfo rm hor izon tal ups cal -
ing (see Table 7-5). The EVO accepts memory image
dat a in YU V 4:2:2 c o-si ted, YUV 4: 2:2 int ers pers ed an d
YUV 4:2:0 for mats, and generates a CCIR 656-compati-
ble, YUV 4 :2:2 co -s ited im age outp ut str eam. Sc alin g is
identified by t he YUV-1× and YUV-2× modes. In YUV-1×
mode s, lumi nanc e a nd chromi na nc e p as s unmo di f ied. In
YUV-2× modes, luminance and chrominance are hori-
zontally upscaled by a factor of t wo.
During video refresh, the VO_STATUS. YTR bit is set
when the Image Line Counter reaches the
Y_THRESH OLD value. When an image field has be en
transferred , the VO_S TATUS. BFR1_E MPTY bi t i s set.
The DSPCPU is interrupted when either the YTR or
BFR 1_EMPT Y fl ag is se t and its corr espon ding inter rupt
is enabled. To maintain continuous transfer of image
fields, the DSPCPU supplies new pointers for the next
field following each BFR1_EMPTY interrupt. If the
DSP CP U does not sup ply n ew po int ers b efor e the nex t
field, the URUN bit is set, and the EVO uses the same
pointer values until they are updated.
Table 7-10. EVO-Related MMIO Registers Fields
Register Field Description
EVO_MASK MASK_Y This 4-bit v alue is used to mask the four lower bits of the overlay Y component during the
chroma key process. Example: Setting MASK_Y to ‘1’ will eliminate the influence of the
LSB of KEY _Y in the keying pro cess.
MASK_UV This 4-bit value is used to mask the four lower bits of the overlay U and V components
during the chroma key process. Example: Setting MASK_UV to ‘1’ will e limin ate the
influence of the LSB of KEY_U and KEY_V in the keying process.
EVO_CLIP LOWER_CLIPY A Y value lower or equal to LOWER_CLIPY is forced to LOWER_CLIPY. Default: 16.
HIGHER_CLIPY A Y value higher or equal to HIGHER_CLIPY is forced to HIGHER_CLIPY. Default: 235.
LOWER_CLIPUV An U or Y value less than or equal to LOWER_CLIPUV is forced to LOWER_CLIPUV.
Default: 16.
HIGHER_CLIPUV An U or and an V value higher than or equal to HIGHER_CLIPUV is forced to
HIGHER_CLIPUV. Default: 240.
EVO_KEY KEY_Y Value compared to the Y component of the overlay for chroma keying.
KEY_U Value compared to the U component of the overlay for chroma keying.
KEY_V Value compared to the V component of the overlay for chroma keying.
EVO_SLVDLY Number of V O_CLK cycles of internal delay for VO_IO2 in Genlock mode.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-22 PRELIMINARY SPECIFICATION
Graphics Overlay
The graphics overlay is enabled by the VO_CTL. OL_EN
bi t. T he graphics overlay is typic ally a softw ar e-generat-
ed graphic overlaid onto the output video image st rea m.
The graphics overlay is either generated in YUV by the
DSPCPU o r converted by the DSPCPU from an RGB to
a YUV overlay image. Because RGB-to-YUV conversion
can pot entially lose information, this conversion is done
by the DSPCPU, because it has the most information
about how best to perform this conversion in the most ef-
fective manner.
The overlay height should be chosen such that the over-
lay does not vertically extend beyond the image area. A
height greater than this causes undefined results and
may result in vertical overlay wraparound.
Note: The emitted byte data rate is limited to 45% of the
SDR A M cloc k w hen ov er lay s ar e enable d.
The YUV overlay logic assembles the U0, Y0, V0, Y1
bytes for a pair of Y UV 4: 2:2 pi xels f o r bot h t h e main im-
age and the overlay image. The alpha bit for pixel 0 (the
LSB of the U0 byte of the overlay image) selects
ALPHA_ZERO or ALPHA_ONE as the alpha source,
and the alph a bl en d logi c co mbi ne s U0, Y0, an d V 0 fro m
the main and o verlay images to generate t he U0, Y0 and
V0 output values. The alpha bit for pixel 1 (the LSB of the
V0 byte of t he ove rla y image) selects ALPHA_ZERO or
ALPHA_ONE as the alpha source for blending the Y1
pixels to generate the Y1 output value . The alpha blend-
ed U0, Y0, V0 and Y 1 bytes are sent to the EVO output
por t in the YUV 4 22 sequenc e. T he overlay U an d V val -
ues used assume an LSB of zero.
Video Image Addressing
Th e ou tp ut i mage is rea d f ro m S D R AM a t a loc ation de -
fined by Y_BASE_ADR, Y_OFFSET, U_BASE_ADR,
U_OFFSET, V_BASE_ADR, and V_OFFSET. The de-
fault memory packing is big-endian alth ough little-endian
packing is also supported by setting the VO_CTL.
LTL_END bit.
Horizontally-adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
sample s are pack ed into on e 32-bit wor d). Upon hor izo n-
tal retrace, the starting byte address for the next line is
computed by adding the corresponding offset value to
the previous line’s starting byte address. Note that
{OL,Y ,U ,V } _O F FS ET val ue s are 16- bi t uns ig ned quanti-
ti es. This pr o ce ss c on tinu es unti l th e t ot al image—height
in lines and width in pixels per line—has been read from
memory for luminance (Y). For chrominance, the same
num ber of lines are read, but half the numbe r of pixels
per li ne a re read i n Y UV 4:2:2 a nd Y U V 4:2:0 format s1.
The YUV 4 :2:0 format has half the number of U and V
lines in memory that the YUV 4:2:2 formats have, but
each line of U and V data is read and used twice. See
Figure 7-19 through Figure 7-22.
Blanking: Field 2 Overlap
Blanking: Field 1
Video Image: Field 1
Blanking: Field 1 Overlap
Blan king: Field 2
Video Image: Field 2
525 Line / 60 Hz
4
20
264
266
283
525
Bl an k ing : F ie ld 1
Vi de o Im age: F ie ld 1
Blanking: Field 1 Overlap
Bl an king : F ield 2
V ide o Im age: Fi el d 2
625 L ine / 50 H z
1
23
311
313
336
623
Blanking: Field 2 Overlap
624
625
1
Fig ur e 7-3 1 . EVO fram e t im in g.
1. Note that consecutive pixel components of each line
are sto red in cons ecutive memo ry addresses but con-
secutive line s need no t be in con secutive memor y ad-
dresses
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-23
7.18 FRAME AND FIELD TIMING CONTROL
The frame timing for 525/60 and 625/50 timing cases is
shown pictorially in Figure 7-31. CCIR 656 line defini-
tions are used.
7.18.1 Recommended values for timing registers
The recommended values for the various fields of the
timing regis t e r s ar e s how n in Table 7-11 for 525/60 and
625/50 timing cases. The FREQUENCY field value
shown is for 27 MHz assuming a DSPCPU clock of
143 MHz.
7.18.2 Data-transfer Modes
In data-streaming and message-passing modes, the
EVO supplies a stream of 8-bit data to the
VO_DATA[7:0] lines at rates up to 81 MHz.
Not e: In the P NX13 00, th e data-r ate is limi ted to an 81 -
MHz EVO clock.
Data is read from SDRAM in packed form (four 8-bit
by tes per 32-bit word ). N o dat a select ion or data interpre-
tation is done, and data is transferred at one byte per
VO_CLK from successive byte addresses.
Note: Unused bits of the EVO MMIO regi sters must be
set to 0 when operating in data transfer modes.
Data-Streaming Mode. In data-streaming mode, data is
st ore d in SD R AM i n tw o bu f fe rs.
When t he EVO has transferred out the contents of one
buffer, it interrupts the DSPCPU and begins transferring
out the conten ts of the second bu ffer. T he DSPC PU sup-
plies pointers to both buffers. The EVO can provide a
continuous stream of data to the EVO output if the
DSPCPU updates the pointer to the next buffer before
the EVO starts transferring data from the next table.
Not e: In this mo de, SY NC_M ASTER mu st be set t o en-
sure correct operation of VO_IO1 and VO_IO2 as out-
puts.
Whe n ea ch buffer has been transferred, the correspond-
ing bu ffe r-e mpt y bit i s set in t he st atu s re gist er, and the
DSPCPU is interrupted if the buffer-empty interrupt is en-
abled. To maintain continuous transfer of data, the
DSPCPU supplies new pointers for the next data buffer
following each buffer-empty interrupt. If the DSPCPU
does not supply new pointers before the next field, the
URUN bit is set, and the EVO uses the same pointer val-
ues until they are update d.
When data-streaming mode is enabled and
EVO_ENABLE = 1 and SYNC_STREAMING = 1, the
VO_IO2 signal indicates a data-valid condition. This sig-
nal is asserted when the EVO starts outputting valid data
(th at is, da ta -str eam ing mo de is e na bled a n d vi deo o ut-
put is run ning ) an d is de -ass ert ed when da ta- strea ming
mode is disabled . The VO_IO1 signal generates a pulse
one VO_CLK cycle before the first valid data is sent. See
Section 7.11 for timing signal details.
Message-Passing Mode. In message-passing mode
data is stored in SDRAM in one buffer.
Not e: In th is mo de, S YNC _MAS TER mus t be s e t t o en -
sure correct operation of VO_IO1 and VO_IO2 as out-
puts.
When message passing is started by setting VO_CTL.
VO_ENABLE, the EVO sends a Start condition on
VO_IO1. When the EVO has transferred the contents of
the buffer, it sends an End condition on VO_IO2 as
shown in Figure 7-18, sets BFR1_EMPTY, and inter-
ru pt s the DSPCP U . T he EVO s to ps , and no fu rth er op er-
ation takes place until the DSPCPU sets VO_ENABLE
agai n to s ta rt anot he r m ess age, or un til t he DSC PU i ni-
tiates other EVO operation. See Section 7.11 fo r timing
si gn al d et a ils.
7.18.3 Interrupts and Err or Condition s
The EVO has five interrupt conditions defined by bits in
the VO_STATUS register: BFR1_EMPTY,
BFR2_EMPTY, HBE, URUN, and YTR. Each of these
conditions has a corresponding interrupt enable flag and
interrupt acknowledge bit in the VO_CTL register.
The EVO asserts a SOURCE 10 interru pt requ est to the
PNX1300 vectored interrupt controller as long as one or
mor e en abled ev ent s is a sse r ted.
Note: The interrupt controller should always be pro-
gra mme d suc h that the EVO inte rrup t op erate s in l evel -
tr igge red mode . T his ensur es that no EVO even ts can be
lost to the interrupt handler. Refer to Se ctio n 3.5. 3 , “INT
and N MI (M ask abl e and N on-M aska ble In terr upt s) ,” for
a des cr iptio n of s ett ing l evel -tri ggere d mo de , as we ll as
for recommendations on writing interrupt handlers.
The BFR1_EMPTY, BFR2_EMPTY and YTR status
flags indicate to the DSPCPU that a buffer has been
emptied or tha t the Y t hre shol d has been r e ac he d.
The buffer-underrun (URUN) status flag indicates that
the DSPCPU did not acknowledge a BFR1_EMPTY or
BFR2_EMPTY interrupt before the EVO required the
nex t bu ffer. In this case, the EVO us es the old address
pointer value and continues image or data transfer.
Table 7-11. Timing register recommended values
Register Field 525/60
Value 625/50
Value
VO_CLOCK FREQUENCY 0x855E,
E191 0x855E,
E191
VO_FRAME FRAME_LENGTH 525 625
FIELD_2_START 264 311
FRAME_PRESET 1 1
VO_FIELD F1_VIDEO_LINE 20 23
F2_VIDEO_LINE 283 336
F1_OLAP 2 2
F2_OLAP 3 –2 (0xE)
VO_LINE FRAME_WIDTH 858 864
VIDEO_PIXEL_START 138 144
VO_IMAGE IMAGE_HEIGHT 240 288
IMAGE_WIDTH 720 720
(704 visible)
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-24 PRELIMINARY SPECIFICATION
Whe n t he DS PCPU up date s th e po int er , th e ne w poi nter
value will be used at the start of the next frame or buffer
tr an sfer . Th er efo r e, th e UR UN fla g ca n be i nter pr et ed as
indi cating to the DSPCP U that the EVO is usin g its old
pointer values because it did not receive the new ones in
time.
Note: The actual buffer pointer write operation to the
MMI O re gist ers is no t seen by the ha rdw are—o nly w rit -
ing a ’1’ to the appropriate BFR1_ACK or BFR2_ACK
bits signal s bu ffer a va il abil ity.
The Hardware B andwidth Erro r (HBE) flag indi cates that
the EVO did not get data from SDRAM via the
PNX1300’s internal data highway in time to continue
data transfer or video refresh. Data or video refresh will
continue using whatever data is in the EVO internal data
buffers. T he address counter for the failing buffer(s) will
cont in ue to c ount , an d the E V O wi ll cont inu e to r eque st
dat a fro m t h e SD RA M ove r the highway.
The EVO is a read-only device, transferring data from
SDRAM to the EVO output port. Unlike Video In, the EVO
does not modify SDRAM data. URUN and HBE are the
only EVO error conditions that can arise. In the case of
URUN or HBE, a scrambled image may be temporarily
displayed or incorrect data may be temporarily sent. The
EVO can cause no other system hardware error condi-
tions.
Even changing operating modes can not cause system
hardware error conditions to arise. For example, chang-
ing the MODE bits, the OL_EN and format bits, or the
LTL _E ND bi t whi le th e EV O is ru nn in g may ca us e w ron g
data to be displayed or tran sferred. However, the EVO
does n ot det e ct t h is or stop fo r it.
In normal operation, the user should not change the
mode or transfer-control bits while the EVO is enabled.
The EVO should be disabled befor e changing bits such
as the MODE bits, the OL_EN bit, or the LTL_END bit.
Howeve r if t hese bits are changed w hile the EVO is run-
ning, they will take effect at the beginning of the next field
or buffer.
7.18. 4 Latenc y and Bandwidth Requi rem en ts
In order to avoid Hardware Bandwidth Error (HBE) con-
ditions, the internal highway bus arbiter (see Cha pt er 20,
“Arbiter”) must be programmed a ccor ding to the latency
requirements of the EVO unit described in this section . In
the following discussion, it is assumed that d ata for video
lines (in Y, U, V and overlay planar memory format) is
stored in memory aligned on 64-byte boundaries. In oth-
er words, it means that the {OL,Y,U,V}_OFFSET fields
ar e mult iples of 64 bytes . Otherw ise in terna l EVO arbit ra-
tion for OL, Y, U and V requests will be different than de-
scribed here, and the following latencies would not be
guaranteed. The EVO uses inter nal 64-byte buffers.
1. Latency requirements for the EVO in image mode
4:2:2 or 4:2:0 co-sited or interspersed without upscal-
ing and wi t h o v erl ay disa b l ed is e x pres se d a s foll o ws .
During 128 EVO clock cycles, the EVO block must
have 2 requests a cknowledged, that is, ([2Ys, 1U and
1V] / 2). For example, if the EVO clock is 27 MHz,
then the EVO must get two requests (128 bytes) from
SDR AM in 128 / 027 = 4 740 ns.
Th e byte band wid th B1x per vi deo line within the ac-
tive im age for th is case is :
where ceil(X) is a func tion r e turn ing the l east integr al
value greater than or equal to X, and W is the
IMAGE_WIDTH field value.
2. In the same modes but with over lay enabled, the la-
tenc y is as follows :
•During the first 64 EVO clock cycles at least one
request must be acknowledged for the OL data.
•During 128 EVO clock cycles, the EVO unit must
have 4 requests acknowledged ([4 OLs, 2 Ys, 1 V
and 1 U] / 2).
For example, if the EVO clock runs at 54 MHz then the
EVO must get the first request from SDRAM in 64/.
054 = 1185 ns and must aver age a bandwidth latenc y
of 4 requests in 128/.054 = 2370 ns.
Byte bandwidth B1x,OL per video line within the active
image is then as follows:
3. Wh en the E VO is se t to ima g e mode wi t h 2× upscal-
ing, the latency requirements are multiplied by a factor
of 2. Fo r examp l e, if 1× mode call ed f or one request
per 64 EV O cloc k cyc les, t he late ncy bec omes one r e-
que st pe r 128 EVO cloc k cycl es . Bandwi dth is ro ughl y
di vi de d by 2:
4. La tenc y for da ta- st reaming mod e or me s sa ge- pa s s-
ing mode is as follow s :
During 64 EVO clock cycles, the EVO unit must get
one request from SDRAM. For example, if the EVO
clock runs at 38 MHz, then the latency is 64/.038 =
1684 n s an d ban dw id th is 38 MB /s.
7.18.5 Power Down and Sleepless
The EVO block enters in power down state whenever
PNX13 00 i s put in glo bal po wer dow n mode , except if the
SLEEPLESS bit in VO_CTL is set. In the latter case, the
block continues DMA operation and will wake up the
DSP CPU whenever an interrupt is generated.
The EVO blo ck can be sepa r ate ly po wer e d dow n by se t-
ting a bi t in the BLO CK_P O WER _ DO WN regi st er. R e fe r
to Chapter 21, “Power Management.”
B1xceil W
64
------()ceil W
128
---------()24+×+
64×=
B1xOL B1xceil W
32
------()4+
+64×=
B2xceil W
128
---------()ceil W
256
---------()24+×+
64×=
B2xOL B2xceil W
64
------()4+
+64×=
Philips Semiconductors Enhanced Video Out
PRELIMINARY SPECIFICATION 7-25
It is recommended that EVO be stopped (by negating
VO_CTL. ENABLE) before block level power down is
started , or t hat SLEEPLESS mode is used when global
power down is activated.
7.19 DDS AND PLL FILTER DETAIL S
The PLL fil ter red uce s the phase ji tter of the DDS synthe-
sizer output. It can also be used to multiply the DDS out-
put frequency by 2×. The DDS and PLL filter together
provide a high-quality, accurately-programmable output
video clock. The PLL filter block is shown in Figure 7-32.
At hardware reset, the output multiplexer is set to 0x3,
and the PLL system is disabled. To start the PLL system,
the following steps must be performed:
1. As sign a DDS f requen cy. T hi s sta rt s th e DDS. Allow
f or at leas t 31 DSPCP U cycl es f or the DD S fr eque ncy
setti ng to take effect.
2. Ch oo se a v al ue f or PL L_S and PL L_ T. F or 8-40 MHz
operation, a value of 1 (which selects division by 2) is
recommended.
3. Choose a valu e for CLOCK_SEL ECT. For 8-81 M Hz
oper a tio n, C LO CK_SE LE CT = 00 is re c om m en ded.
4. Assign values to the VO_CTL regis ter con taini ng the
above choices. The first assignment with
CLOCK_SELECT not equal to 0x3 enables the PLL
s ystem. Allow for a maximum of 5 0 micr oseconds to
achieve lock.
Onc e the PL L is locke d, sm all change s to the DD S fre-
quency are allowed, and the VO_CLK output will
smoothly track the f requenc y change.
Note: Most consumer electronics equipment imposes
very high precision requirements on th e value of t he col-
or bur s t fr equen cy. A vid e o en c od er will der i ve t he co lo r
burst frequency from VO_CLK. When changing the
VO_ CL K f req ue ncy i n sof twa re to ph as e- l oc k the EV O to
a master reference, special care is required to keep the
colo r burst s ignal frequency within a tolerance of ab out
50 ppm. When using a Philips DENC (Digital Encoder),
the color burst frequency is derived from the master
DEN C frequenc y by a pr o g ram mable sy nthesiz er o n t he
DENC chip. In thi s case, V O_CL K c hange s larger than
50 ppm are allowed by changin g th e DENC s y nth esi zer
over its I2C interface to compensate for the VO_CLK
change.
Table 7-12 illustrates recommended settings.
00
01
10
11
Square-Wave DDS
FREQUENCY
VCO
8–90 MH z
VO_CLK
VO_CLK Internal
(to Fr am e Timing Gen . )CLKOUT
9 × CPU Clock
03
Loop
Filter
Phase
Detect
PLL_S div T+1
PLL_T
CLOCK_SELECT
div S+1
Figure 7-32. PLL filter block diagram.
Table 7-12. DDS and PLL example settings
Desired
Frequency DDS frequency PLL_S PLL_T CLOCK_SEL ECT Usage
4 – 10 MHz 8 – 20 MHz 1 (divide by 2) 1 (divide by 2) 01 (T divider) Custom low speed video
8 – 45 MHz 8 – 45 MHz 1 (divide by 2) 1 (divide by 2) 00 (VCO) Standard or 16:9 digital video
40 – 81 MHz 20 – 40. 5 MHz 1 (divide by 2) 3 (divide by 4) 00 (VCO ) Hi gh pixel rate custom vi deo
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
7-26 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 8-1
Audio In Chapter 8
by Gert S lavenb urg
8.1 AUDIO IN OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 A udio In (AI) unit connects to an off-chip
stereo A/D converter subsystem through a flexible bit-se-
rial connection. The AI unit p rovides all signals needed to
int e rfa ce to high qual ity , lo w cost ove rsa mpl in g A/D con-
verters, in clud ing a generator for a precisely programma-
ble oversampli ng A/D system clock . Toge ther, the AI u nit
and ex t e rna l A/D prov id e t he f oll ow i ng c ap ab ilities :
•One or two channels of audio input.
•8- or 16-bit samples pe r channe l.
•Pr ogrammable sampling rate.
•Intern al or externa l sa mpling c lo ck s o urc e.
•Supports autonomous writes of sampled audio data
to memor y using double buffer ing (DMA).
•Supports 8-bit mono and stereo as well as 16-bit
mono and stereo PC standard memory da ta forma ts.
•Su pports litt le- a nd big-endi an mem ory forma ts.
8.2 EXTERNAL INTERFACE
Four PNX1300 pins are associated with the AI unit. The
AI_OSCLK outp ut is an accurately programmable clock
output intended to serve as the master system clock for
the external A/D subsystem. The other three pins
(AI_ SCK , AI _WS an d AI _SD) c ons titu te a fle xib le ser ial
input interface. Using the AI unit’s MMIO r eg is ter s, these
pin s ca n b e co nfi gur ed t o o pe rat e i n a var i ety of seria l i n-
terface framing modes, including but not limited to:
•Standard stereo I2S (MSB first, 1-bit delay from
AI_WS, left & right data in a frame).1
•LSB first with 1–16 bit data per channel.
•Complex serial frames of up to 512 bits/frame, with
‘valid sample’ qualifier bi t.
The AI unit can be used with many serial A/D converter
devices, including the Philips SAA7366 (stereo A/D),
Crysta l S em ico nduc t o r CS5 331, CS5336 (stereo A/ D ’s),
CS4218 (codec), Analog Devices AD1847 (codec).
1. A definition of the Philips I2S serial interface protocol,
among others, can be found in the Philips IC01 da-
tabook.
Table 8-1. AI unit external signals
Signal Type Description
AI_OSCLK OUT Over-sampling clock. This output can be
programmed to emit any frequency up to
40-MHz with a sub Hertz reso luti on. It is
intended for use as the 2 5 6fs or 384fs
over sam p ling clock by external A /D sub-
system.
AI_SCK I/O-5 • When the AI unit is programmed as
serial-interface timing slave (power-up
default), AI_SCK is an input. AI_SCK
receives the serial bitclock from the
external A/D subsystem . Th is clock is
treated as fully asynchronous to
PNX1300 main clock.
• When the AI unit is programmed as the
serial-interface timing master, AI_SCK
is an output. AI_SCK drives the serial
clock for the external A/D subsystem.
The frequency is a programmable inte-
gral divide of the AI_OSCLK frequency.
AI_SCK is limited to 22 MHz. The sample
rate of valid samples embedded within
the serial stream is also limited by the
bandw idth. latency available in the sys-
tem (Section 8-10).
AI_SD IN-5 Serial data from external A/D subsystem.
Data on this pin is sampled on positive or
negative edges of AI_SCK a s determi ned
by the CLOCK_EDG E bit in th e
AI_SERIAL register.
AI_WS I/O-5 •When the AI unit is programmed as the
ser ial-in ter face timing slave ( power-up
default), AI_WS acts as an input.
AI_WS is sampled on the same edge
as sel ecte d fo r AI_SD.
•When the AI unit is progr ammed as the
ser ial-in ter face tim ing master, AI _WS
acts as an output. It is asserted on the
opposite edge of the AI_SD sampling
edge.
AI_WS is the word-select or frame-syn-
chronization signal from/to the e xternal A/
D subsystem.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
8-2 PRELIMINARY SPECIFICATION
8.3 CLOCK SYSTEM
Figure 8-1 illustrates the different clock capabilities of the
AI unit. At the heart of the clock system is a square wave
DDS (Direct Digital Synthesizer). The DDS can be pro-
grammed to emit frequencies from approx. 1 Hz to 40
MHz with a resolution of better than 0.3 Hz.
Th e ou tp ut of th e D DS is alwa y s s en t on t h e AI_O SC L K
output pin. This output is intended to be used as the
256fs or 384f s syst em c lo ck sour c e in stea d of a fixed fr e-
quency crystal for ov e r s a mplin g A/D converters, such as
the Philips SAA7366T, or Analog Devices AD1847.
The P NX1300 AI DDS frequency is set by writing to the
FREQUENCY MMIO register. The programmer can
change the FREQUENCY setting dynamically, so as to
adjust the input sampling rate to track an application de-
pendent master reference.
Depending on bit 31 (MSB), the DD S runs in one of two
modes:
•bit 31 = 1 (PNX13 00 im pr oved mo de )
•bit 31 = 0 (TM-1000 compatibility mode)
8.3.1 PNX1300 Improved Mode
In im pr ov ed mode , a high qual i ty , low -ji t te r AI_O SC LK is
generated. The setting of the FREQUENCY register to
accom plish a g iv en A I_O S CLK freq uenc y is given by:
This mode, and the above formula, should be used for all
new software development on PNX1300. It is not avail-
able on T M- 1 000.
In the improved mode the DDS synthesizer maximum jit-
te r c an be c ompute d as f o llow s :
Example of jitter values can be found in Table 8-2.
8.3.2 TM-1000 Compatibility Mode
TM-1000 compatibility mode is provided so that TM-1000
softw are run s wit hout changes. It should NOT be us ed
for new PNX1300 software development. TM-1000
mode is automatically entered whenever FREQUEN-
CY[31] = 0. In TM-1000 mode, AI_OSCLK frequency is
set as follows:
8.4 CLOCK SYSTEM OPERATION
AI_SCK and AI_WS can be configured as input or out-
put, as determined by the SER_MASTER control field.
As output, AI_SCK is a divider of the DDS output fre-
quen c y. Whet her in put or out put, the AI_SC K pin si gnal
is used as th e bit clock for serial-parallel conversion.
If set as ou tpu t, A I_WS can si mil a rly b e prog r amm ed us-
ing WSDIV to control the serial frame length from 1 to
512 bits.
The preferred applicat ion of t he clock syst em options is
to use AI_OSCLK as A/D master clock, and let the A/D
converter be timing master over the serial interface
(SER_MASTER=0).
In case an external codec (e.g. the AD184 7 or CS4218)
is used for common audio I/O, it may not be possible to
independently control the A/D and D/A system clocks. In
th a t cas e i t i s re c o mmen de d t h at the Audio Out (AO) unit
FREQUENCY
AI_OSCLK
AI_SCK
AI_WS
div N+1 SCKDIV
div N+1
Square Wave DDS
9 × DSPCPUCLK
AI_SD
SER_MASTER
Ser ial To Parall el Converter
16
16 LEFT[15:0]
RIGHT[15:0]
sample_clock
(e.g. 64×fs)
WSDIV
31 0
70
08
(e.g. 256×fs)
Fi gu re 8 - 1. AI clo ck sy stem and I/ O in t erf a ce.
FREQUENCY 231 fOSCLK 232
⋅
9fDSPCPU
⋅
------------------------------+=
jitter 1
9fDSPCPU
⋅
-----------------------------=
Ta ble 8-2. Jitter values for common DSPCPU MHz
fDSPCPU
(MHz) jitter
(nSec) fDSPCPU
(MHz) jitter
(nSec)
143 0.777 180 0.617
166 0.669 200 0.555
FREQUENCY fOSCLK 232
⋅
3fDSPCPU
⋅
------------------------------=
SCKDIV 0 255[, ]∈
fAISCK fAIOSCLK
SCKDIV 1+
----------------------------------=
Philips Semiconductors Audio In
PRELIMINARY SPECIFICATION 8-3
clock system DDS is used t o provide a single master A/
D and D/A clock. The AO unit, or the D/A co nver ter, can
be used as serial interface timing master, and the AI unit
is set to be slave to the serial frame determined by AO
(AI SER_MASTER=0, AI_SCK and AI_WS externally
wired to the corresponding AO pins). In such systems, in-
dependent softwar e control over A/D and D/A sampling
rate is not possible, but c omponen t cou nt is min imized.
8. 5 SER IAL DATA FRAMING
The AI unit can accept data in a wide variety of serial
data framing co nventions. Figure 8-2 illustrates the no-
tion of a serial frame. If POLARITY=1 and
CLOC K_EDG E= 0, a frame is de fin ed w ith res pect to t he
positive transition of the AI_WS signal, as observed by a
posi tive cl ock tran sition o n AI_SCK. Each d ata bit sa m-
pled on positive AI_SCK transitions has a specific bit po-
sition: the data bi t sampled on the clock edge after the
clock edge on which the AI_WS transition is seen has bit
position 0. Each subsequent clock edge defines a new
bit position. As defined in Table 8-5, other combinations
of P OLA RI TY an d CLO CK _ED GE can be used to d e fi ne
a variety of serial frame bitposition definitions.
The capturi ng of samples is governed by FRAMEMODE.
If FRAMEMODE=00, every serial frame results in one
sample from the serial-parallel converter. A sample is de-
fined as a left/right pair in stereo modes or a single left
channel value in mono modes. If FRAMEMODE=1y, the
serial frame data bit in bit position VALIDPOS is exam-
ined. If it ha s va lu e ‘y’, a sample is taken from the data
stream (the valid bit is allowed to precede or follow the
left or right channel data p rovided it is in the same serial
fra me as the d ata ).
The left and right sample data can be in a LSB-first or
MSB-first form, at an arbitrary bit position, and wit h an ar -
bi tra r y le ng t h.
Table 8-3. Sample rate settings (fDSPCPUCLK=133
MHz, improved PNX1300 mode)
fsOSCLK SCK FREQUENCY SCKDIV
44.1 kHz 256fs64fs2187991971 3
48.0 kHz 256fs64fs2191574340 3
44.1 kHz 384fs64fs2208246133 5
48.0 kHz 384fs64fs2213619686 5
Tab l e 8-4 . AI MM IO clock & inter fac e con tro l bit s
Field Name Description
SER_MASTER 0 ⇒ (RESET default), the A/D converter
is the timing master over the serial inter-
face. AI_SCK and AI_WS are set to be
inputs.
1 ⇒ PNX 1300 is tim ing master over the
AI serial interface. The AI_SCK and
AI_WS pins are set to be outputs.
FREQUENCY Sets the clock frequency emitted by the
AI_OSCLK output. RESET de fault 0.
SCKDIV Sets the divider used to derive AI_SCK
from AI_OSCLK. Set to 0..255, for divi-
sion by 1..256. RESET default 0.
WSDIV Sets the divider used to derive AI_WS
from AI_SCK. Set to 0..511 for a serial
frame length of 1..512. RESET default 0.
7654321031302928272625242322212019181716151413121110987654321
AI_SCK
AI_WS
framen
0
AI_SD framen+1
Figure 8-2. AI serial fra me and bit position definition (POLARITY=1, CLOCK_EDGE=0).
Table 8-5. AI MMIO serial framing control fields
Field Nam e Descript ion
POLARITY 0 ⇒ serial frame starts on AI_WS negedge
(R ESET de fault)
1 ⇒ serial frame starts on AI_WS posedge
FRAMEMODE 0 0 ⇒ accept a sample every serial frame
(R ESET de fault)
01 ⇒ unused, reserved
10 ⇒ accept sample if valid bit = 0
11 ⇒ accept sample if valid bit = 1
VALIDPOS • Defines the bit position within a serial frame
where the valid bit is found.
• Default 0.
LEFTPOS • Defines the bit position within a serial frame
where the first da ta bit of the left channel is
found.
• Default 0.
RIGHTPOS • Defines the bit position within a serial frame
where the first data bit of the right channel
is found.
• Default 0.
DATAMODE 0 ⇒ MSB first (RESET default)
1 ⇒ LSB first
SSPOS • Start/Stop bit position. Default 0.
• If DATAMODE=MSB first, SSPOS deter-
mines the bit index (0..15) in the parallel
word of the last data bit. Bits 15 (MSB) up
to/including SSPOS are taken in order from
the serial frame data. All other bits are set
to ‘0’.
• If DATAMODE=LSB first, SSPOS deter-
mines the bit index (0..15) in the parallel
word of the first data bit. Bits SSPOS up to/
including 15 are taken in order from the
serial frame data. All other bits are set to ‘0’.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
8-4 PRELIMINARY SPECIFICATION
In MSB-first mode, the serial-to-parallel converter as-
signs the value of the bit at LEFTPOS to LEFT[15]. Sub-
sequent bits are assigned, in order, to decreasing bit po-
sitions in the LEFT data word, up to and including
LEFT[SSPOS]. Bits LEFT[SSPOS–1:0] are cleared.
He nce, in MSB-f irst mod e, an arbi trary n umber of bit s are
c aptured. They are left-adjuste d in the 16 -bit parallel out-
put of the converter.
In LSB- first mode, the serial to parallel converte r as s igns
the valu e of the b it at LE FTPOS to LE FT[ SSPOS] . Su b-
sequent b its are as signed, in or der, to increasing bit po -
sitions in the LEFT data word, up to and including
LEFT[15]. Bits L EFT[SSPOS–1:0] are cleared. Hence, in
LSB -f i rst mode , an ar bi tra ry nu mbe r of bits ar e ca ptu r ed.
They are returned left-adjusted in the 16-bit parallel out-
put of the converter.
Refer to Figure 8-3 an d Table 8-6 to see an e xample of
how the AI unit MMIO registers are set to collect 16-bit
sam pl es us ing th e Ph ilip s SAA 7366 I 2S 18-bit A/D c on-
v ert er. This se tu p as sum es the SAA7 36 6 ac ts a s th e se-
rial master.
For examp le, if it were desi rable t o use o nly the 1 2 MSBs
of the A/D converter in Figure 8-3, use the settings of
Table 8-6 with SSPOS set to ‘4’. This results in
LEFT[15:4] being set with data bits 0..11, and LEFT[3:0]
bein g se t to ’0’. RI GH T [ 15 :4 ] is set wi th d ata b i t s 32 ..4 3
and R IG H T[3: 0 ] is se t t o ’0’.
8.6 MEMORY DATA FORMATS
The A I unit autonomously writes samples to memory in
mono and stereo 8- and 16-bits per sample formats, as
shown in Figure 8-4. Successive samples are always
s to red at in cr easing memory address loc at ions. The set-
ting o f the LITTLE_ENDIAN bit in the AI_CTL register de -
CLOCK_EDGE • if ‘0’(RESET default) the AI_SD and AI_WS
pins are sampled on positive edges of the
AI_SCK pin. If SER_MASTER =1, AI_WS is
ass er ted on negative edges of AI_SCK.
• if 1, AI_SD and AI_WS are sampled on neg-
ative edges of AI_SCK. As output, AI_WS
is asserted on positive edges of AI_SCK.
Table 8-5. AI MMIO serial framing control fields
Field Nam e Descript ion
Figure 8-3. Serial frame of the SAA7366 18 bit I2S A/D converter (format 2 SWS).
16362525150343332311918
AI_SCK
AI_WS
AI_SD
leftn(18)
3210
rightn(18)
0
leftn+1(18)
Ta ble 8-6. Exam pl e s etup for S AA 7366
Field Value Explanation
SER_MASTER 0 SAA7366 is serial master
FREQUENCY 161628209 256fs 44.1 kHz
SCKDIV 3 AI_SCK s et to AI_OSCLK /4
(not needed since
SER_MASTER=0)
WSDIV 63 Serial frame length of 64 bits
(not needed since
SER_MASTER=0)
POLARITY 0 Frame star ts with neg. AI_WS
FRAMEMODE 00 Take a sample each ser . frame
VALIDPOS n/a Don’t care
LEFTPOS 0 Bit position 0 is MSB of left
channel and will go to
LEFT[15]
RIGHTPOS 32 Bit position 3 2 is MSB of right
channel and will go to
RIGHT[15]
DATAMODE 0 MSB f irst
SSPOS 0 Stop with LEFT/RIGHT[0]
CLOCK_EDGE 0 Sample WS and SD on posi-
tive SCK edges for I2S
Figure 8-4. AI memory DMA formats.
adr
leftn
adr+1
leftn+1
adr+2
leftn+2
adr+3
leftn+3
adr+4
leftn+4
adr+5
leftn+5
adr+6
leftn+6
adr+7
leftn+7
8-bit
mono
adr
leftn
adr+1
rightn
adr+2
leftn+1
adr+3
rightn+1
adr+4
leftn+2
adr+5
rightn+2
adr+6
leftn+3
adr+7
rightn+3
8-bit
stereo
16-bit
mono leftn
adr
leftn+1
adr+2
leftn+2
adr+4
leftn+3
adr+6
16-bit
stereo leftn
adr
rightn
adr+2
leftn+1
adr+4
rightn+1
adr+6
Philips Semiconductors Audio In
PRELIMINARY SPECIFICATION 8-5
ter m ines ho w in cre asi ng me mory addr esse s m ap to b yte
posi ti on s with in wo rds . Refe r to Append ix C, “Endian-ness,”
for details on byte orderi ng conventions.
The AI hardware implements a double buffering scheme
to ensure that no sa mples are lost, even if the DSPCPU
is highly loaded and slow to respond to interrupts. The
DSPCPU software assigns buffers by w riting a base ad-
dress and size to the MMIO control fields described in
Table 8-7. R e fer to Section 8.7 for details on hardware/
software synchronization.
In 8-bit capture modes, the eight MSBs of the serial par-
allel converter output data are written to memory. In 16-
bit capture modes, all bits of th e parallel data are written
to memory. If SIGN_CONVERT is set to ’1’, the MSB of
the data is inverted, which is equivalent to translating
from two’s complement to offset binary representation.
This allows the use of an external two’s complement 16-
bit A/D converter to generate 8-bit unsigned samples,
which is often used in PC audio.
Note that the AI hardware does not generate A-law or µ-
law 8-bit data formats. If such formats are desired, the
DSP CPU can be u s ed to c o nv er t f rom 1 6-bit lin ear data
to A-law or µ-law data.
Figure 8-5. A I status /control field MMIO layout .
MMIO_base
offset:
AI_STATU S (r/w)0x10 1C00
AI_CTL (r/w)0x10 1C04
AI_SE RIAL (r/w)0x10 1C08 SCKDIV
AI_FRAMING (r/w)0x10 1C0C
AI_FREQ (r/w)0x10 1C10
AI_BASE1 (r/w)0x10 1C14
FREQUENCY
BUF1_ACTIVE
AI_BASE2 (r/w)0x10 1C18 BASE2
AI_SIZE (r/w)0x10 1C1C SIZE (i n samp l es)
31 0371115192327
VALIDPOS
BASE1
OVERRUN
HBE (Highway bandwidth error)
BUF2_FULL
RESET
CAP_ENABLE
CAP_MODE
SIGN_CONVERT
LITTLE_ENDIAN
0
DIAGMODE
OVR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_OVR
ACK_HBE
ACK2
ACK1
WSDIV
SER_MASTER
DATAMODE
FRAMEMODE
POLARITY
LEFTPOS RIGHTPOS SSPOS
00000
000000
BUF1_FULL
SLEEPLESS
CLOCK_EDGE
000000
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
RESERVED
Table 8-7. AI MMIO DMA control fields
Field Nam e De scription
LITTLE_ENDIAN 0 ⇒ capture in big endian memory format
(RESET default)
1 ⇒ capture little endian
BASE1 Base address of buffer1; a 64-byte aligned
addr ess in local SDRA M.
RESET default 0.
BASE2 Base address of buffer2; a 64-byte aligned
addr ess in local SDRA M.
RESET default 0.
SIZE • Number of sam ples to be placed in
buffer before switching to other buffer
• Stereo modes: a pair of 8- or 16-bit data
is 1 sample
• Mono modes: a single value i s 1 sa mple
• RESET def ault 0.
CAP_MODE 00 ⇒ mono (left ADC only), 8 bits/ sample.
(RESET defaul t).
01 ⇒ stereo, 2 times 8 bits/sampl e
10 ⇒ mono (left ADC only), 16 bits/sample
11 ⇒ stereo, 2 times 16 bits/sample
SIGN_CONVERT 0 ⇒ leave MSB unchanged (RESET
default)
1 ⇒ invert MSB
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
8-6 PRELIMINARY SPECIFICATION
8 . 7 AUD I O IN OPE R ATION
Figure 8-5, Table 8-8 and Table 8-9 describe the func-
tion of the control and status fields of the AI unit. To en-
sure compatibility with future devices, undefined bits in
MMI O re gist ers shou ld be ignor ed w he n rea d, and w rit-
ten as ’0’s.
The AI unit is reset by a PNX1300 hardware reset, or by
writing 0x80000000 to the AI_CTL register. Upon RE-
SET, capture is disabled (CAP_ENABLE = 0), and
buffer1 is the active buffer (BUF1_ACTIVE=1). A mini-
mum of 5 v al id AI_S C K cl oc k cyc les is re quir e d to allo w
internal AI circuitry to stabilize before enabling capture.
This can be accomplished by programming AI_FREQ
and AI_SERIAL and then delaying for the appropriate
time inte r va l.
Programing of the AI_SERIAL MMIO register needs to
follow the following sequence order:
•set AI_FREQ to ensure that a valid clock is gener-
ated (Onl y whe n AI is the master of the audio clock
system)
•MMIO(AI_CTL) = 1 << 31; /* Software Res et */
•MMIO(AI_SERIAL) = 1 << 31; /* sets serial-master
mode, start s AI_SCK */
•MMIO(AI_SERIA L) = (1 << 31) | (SCKDIV value); /*
then set DIVIDER val ues */
The DSPCPU initiates capture by providing two equal
size empty buffers and putting their base address and
size in the BASEn an d SIZE re gister s. Onc e two valid (l o-
cal memory) buffers are assigned, capture can be en-
abled by writing a ‘1’ to CAP_ENABLE. The AI unit hard-
ware now proceeds to fill buffer 1 with input samples.
On ce bu ffe r 1 fill s up , BUF1_ FU LL is ass ert ed , and cap-
ture continues without interruption in buffer 2. If
BUF1_INTEN is enabled, a SOURCE 11 interrupt re-
quest is generated.
Table 8-8. AI MMIO control fields
Field Nam e Descr iptio n
RES ET The AI l o gic is res e t by writing a 0x80000000
to AI_CT L. This bit always reads as a ‘0’.
See Section 8.7, “Audio In Operation” for
detail s on softwa re reset.
DIAGMODE 0 ⇒ normal operation (RESET default)
1 ⇒ d iagn ostic mode (see Section 8.11,
“Diagnos tic Mode”)
SLEEPLESS 0 ⇒ participate in global power down
(RES ET default)
1 ⇒ refrain from participating in power down
CAP_ENABLE Capture Enable flag. If 1, AI unit captures
sampl es and a cts as DMA mas ter to wri te
samples to local SDRAM. If ’0’ (RES ET
default), AI unit is inactive.
BUF1_ INTEN Buffer 1 fu ll Interrupt Enable. Default 0.
0 ⇒ no interrupt
1 ⇒ interrupt (SOURCE 11) if buffer 1 full
BUF2_INTEN Buffer 2 full interrupt enable. Default 0
0 ⇒ no interrupt
1 ⇒ interrupt (SOURCE 11) if buffer 2 full
HBE_INTEN HBE Interrupt Enable. Defa ult 0.
0 ⇒ no interrupt
1 ⇒ interrupt (SOURCE 11) if a highway
bandwidth error occurs.
OVR_INTEN Overrun Interrupt Enable. Default 0
0 ⇒ no interrupt
1 ⇒ interrupt (SOURCE 11) if an overrun
error occurs
ACK1 Write a ’1’ to clear the BUF1_FULL flag and
remove any pending BUF1_FULL interrupt
requ est. This bit always reads as 0.
ACK2 Write a ’1’ to clear the BUF2_FULL flag and
remove any pending BUF2_FULL interrupt
requ est. This bit always reads as 0.
ACK_HBE Write a ’1’ to clear the HBE flag and
remove any pending HBE interrupt request.
Thi s bit always re ads as 0.
ACK_OVR Write a ’1’ to clear the OVERRUN flag and
remove any pending OVERRUN interrupt
requ est. This bit always reads as 0.
Table 8-9. AI MMIO status fields (read only)
Fie ld Name Descriptio n
BUF1_ACTIVE • If ‘1’, buffer 1 will be used for the next
incoming sample. If ‘0’, buffer 2 will receiv e
the next sample.
• 1 after RESET.
BUF1_FULL • If ‘1’, buffer 1 is full. If BUF1_INTEN is also
‘1’, an interrupt request (source 11) is
pending. BUF1_FULL is cleared by writing
a ‘1’ to ACK1, at which point the AI hard-
ware will as sume that BASE1 and SIZE
describe a new empty buffer.
• 0 after RESET.
BUF2_FULL • If ‘1’, buffer 2 is full. If BUF2_INTEN is also
‘1’, an interrupt request (source 11) is
pending. BUF2_FULL is cleared by writing
a ‘1’ to ACK2, at which point the AI hard-
ware will as sume that BASE2 and SIZE
describe a new empty buffer.
• 0 after RESET.
HBE • Highway Bandwidth Error. Condition raised
when the 64-byte internal AI buffer is not
yet written to SDRAM when a new input
sample arrives. Indicates insufficient allo-
cation of PNX1300 highway bandwidth for
the audi o sampling rate/ mode. Refe r to
Cha pter 20, “Arbiter.”
• 0 after RESET.
OVERRUN • OVERRUN error occurred, i.e. the CPU did
not provide an empty buffer in time, and 1
or more samples were l o st. If OVR_INTEN
is also 1, an interrupt request (source 11)
is pending. The OVERRUN flag can ONLY
be cleared by writing a ‘1’ to ACK_OV R.
• 0 after RESET.
Table 8-9. AI MMIO status fields (read only)
Field N am e D escription
Philips Semiconductors Audio In
PRELIMINARY SPECIFICATION 8-7
Note that the buffers must be 64-byte aligned, and a mul-
tiple of 64 sampl es in size (the si x LSBs of AI_BASE1,
AI_BASE2 and AI _S IZE are alw ays ’0’).
The DSPCPU is required to assign a new, empty buffer
to BASE1 an d pe r fo rm an AC K1, befo re buff e r 2 fi lls u p .
Capture con tinues i n buffer 2, until it fills up. At t hat t ime,
BUF2_FULL is asserted, and capture continues in the
new buffer 1, etc.
Upon receipt of an ACK, the AI hardware removes the re-
lated interrupt request line assertion at the next DSPCPU
clock edge. Refer to Section 3.5.3, “INT and NMI
(M as ka bl e an d N o n- Ma s ka bl e Int e rr u pts) ,” for the rules
regarding ACK and interrupt re-enabling. The AI interrupt
shoul d alway s be op erate d in level-sensi tiv e mode , since
AI can si gnal mu lti ple condit ions tha t eac h need in depe n-
dent ACK s over the singl e internal SOURCE 11 request
line.
In normal operation, the DSPCPU and AI h ardware con-
tinuously exchange buffers without ever loosing a sam-
ple. If the DSPCPU fails t o provide a new buffer in t i me,
the OVERRUN error flag is raised. This flag is no t af fec t-
ed by ACK 1 or ACK2; it c an only be clear ed b y an explici t
ACK_OVR.
8.8 POWER DOWN AND SLEEPLESS
The AI uni t ent ers po wer do wn state whene ver PNX1300
is put in global power down mode, except if the SLEEP-
LESS bit in AI_CTL is set. In the latter case, the unit con-
tinues DMA operation and will wake up the DSPCPU
whe ne v er an in terrup t is ge ne r at ed .
The AI unit can be separately powered down by setting a
bit in the BLOCK_POWER_DOWN register. Refer to
Chapter 21, “Power Management.”
It is recommended that AI be stopped (by negating
AI_CTL.CAP_ENABLE) before block level power down
is started, or that SLEEPLESS mode is used when global
power down is activated.
8.9 HIGHWAY LATENCY AND HBE
The AI unit u ses internal buffering before writing data to
SDRAM. The internal buffer consists of one stereo sam-
ple input holding register and 64 bytes of internal bu ffer
memory. Under normal operation, the 64-byte buffer is
written to SDRAM while the input register receives an-
ot he r sample . This n or m al oper a t i on is guar a nteed to be
maintained as long as the highway arbiter is set to guar-
antee a latency for the AI unit that matc hes the samplin g
interval. Given a sample rate fs, and an associated sam-
ple inte r va l T (in n se c) , th e arbiter sho uld be s et to h a ve
a latency of at most T-20 nsec. Refer to Chapter 20, “Ar-
biter,” for i nformation on arbiter programming. If the re-
quested latency is not adequate, the HBE (Highway
Bandwidth Error) condition may result. This error flag
gets set when the input register is full, the 64-byte buffer
has n ot ye t been writ ten to me mo ry, an d a ne w samp le
arrives.
Table 8-10 shows the r equi red arbit er la tenc y setti ngs for
a number of common operating modes. The rightmost
column illustrates the nature of the resulting 64-byte
highway requests. Is not necessary to compute arbiter
settings, but they may be used to compute bus availabil-
ity in a given interval.
8 . 10 E R ROR BE HAVIOR
If either an OVERRUN or HBE error occurs, input sam-
pling is temporarily halted, and samples will be lost. In
case of OVERRUN, sampling resumes as soon as the
DSPCPU makes one or more new buffers available
thr oug h an ACK1 or ACK2 operat ion. In the ca se of HBE ,
sampling will resume as soon as the internal buffer is
writ ten to SD RAM.
HBE and OVERRUN are ‘sticky’ error flags. They will re-
main s et un ti l an expl icit ACK_HBE or ACK_OVR.
8.11 DIAG NOS TIC MODE
Diagnostic mode is entered by setting the DIAGMODE
bit in the AI_CTL register. In diagnostic mode, the
AI_ SCK, AI_W S a nd A I_S D i nput s of th e se ria l-p aral lel
c onv ert er a r e take n f rom the o ut pu t pin s o f t he P NX1 300
AO unit. This mode can be used during the diagnostic
phase of system boot to verify correct operation of most
of the AI unit and AO unit logic circuitry.
Note that the inputs are truly taken from the PNX1300
AO external pins, i.e. if an external (boar d level) source
is driving AO_SCK or AO_WS, diagnostic mode is not
capable of testing Audio Out.
Sp ecia l car e mu st be ta ken to en ab le d iagn ostic mo de.
The recommended way of en tering diagnostic mode is :
•setup the AO unit such that an AO_SCK is generated
•set DIAGMODE bit followed by a 5 (AI_SCK) cycle
delay
•perform a software reset of the AI unit and immedi-
at el y se t t h e D IAGM O D E bit ba ck to ‘1’.
Table 8-10. AI highway arbiter l atency requirement
examples
CapMode fs
(kHz) T
(nS)
max
arbiter
latency
(nsec)
access pa ttern
stereo
16 bits/sample 44.1 22,676 22,656 1 req ues t every
362,812 nsec
stereo
16 bits/sample 48.0 20,833 20,813 1 req uest ever y
333,333 nsec
stereo
16 bits/sample 96.0 10,417 10,397 1 request every
166,667 nsec
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
8-8 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 9-1
Audio Out Chapter 9
by G ert Slavenburg, Santan u Du tta
9.1 AUDIO OUT OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX130 0 Audio Ou t (AO) unit con tains many fea-
tures not available in the TM-1000 and the TM-1100. It
has up t o 8 channe ls, and d r iv es up t o 4 e xt e rnal s t e reo
D/A converters through a flexible bit-serial connection.
It provides all signals to interface to high quality, low cost
over sa mpli ng D /A co nv erter s, i nclu ding a p recis ely pro -
grammable oversampling D/A system clock. The AO unit
and ex ternal D/A’s together provide the following capa-
bilities:
•Up to 8 ch an ne ls o f aud io ou tp ut .
•16-bit or 32-bit samples per channel.
•Pr ogrammable sampling rate.
•Internal or e xternal sampling clock source.
•Autonomously reads processed audio data from
memory usi ng double bu fferi ng (DMA).
•Supports 16-bit mono and stereo PC standard mem-
ory da ta for m ats.
•Su pports litt le- an d big-endian mem ory formats.
•Provides control capability for highly integrated PC
codecs such as the AD1847, CS4218 or UAD1340.
•No support for connecting several D/As to one serial
dat a output.
9.2 EXTERNAL INTERFACE
Seven PNX1300 pins are associated with the AO unit.
Th e AO _OSC LK o utpu t i s an acc urate ly p rog ramm able
cl ock o utp ut inte nd ed t o be u sed as t he m aste r s yst em
clock for the external D/A subsystem. The other pins
(AO_SCK, AO_WS and AO_SDx) constitute a flexible
serial output interface. Using the AO MMIO registers,
these pins can be conf igured to operate in a variety o f se-
ria l int er f ac e f ram ing m odes , inclu di ng but not limit ed to:
•Standard stereo I2S (MSB first, 1-bit delay from
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-2 PRELIMINARY SPECIFICATION
AO_WS, left & right data in a frame).
•LSB first, with 1–16-bit data per channel.
•Com plex serial frames of up t o 512 bi ts / frame.
•Up to 8 ch anne ls o f aud i o ou tp ut.
9.3 SUMMARY OF OPERATION
Th e AO un it con sist s of t hree m ajor subs yst ems , a pro-
gra mma ble s amp le clo ck ge nera tor, a DM A en gine a nd
a da ta se r ia li zer .
The DMA engine reads 16 or 32-bit samples from mem-
ory using a double buffered DMA approach. The
DSP CPU ini tia lly assi gns two full sampl e buffe rs cont ain-
ing an integral number of samples for all active channels.
Th e DMA en gine ret riev es s ampl es f rom t he first bu ffer
until exhausted and continues from the second buffer,
while requesting a new first sample buffer from the
DSPCPU, etc.
The samples are given to the data serializer, which
sends them out in a MSB first or LSB first serial frame for-
mat that can also contain 1 or 2 codec cont rol words of
up t o 16 bi ts. Th e fram e str uctur e is h ighly pro gramma ble
by a s er ies of MMIO fields .
9 .4 INT ER NA L C L OC K SO UR CE
Figure 9-1 illustrates the different clock capabilities of the
AO unit. At the heart of the clock system is a square
wave DDS (Direct Digital Synthesizer). The DDS can be
Table 9-1. AO unit external signals
Signal Type Description
AO_OSCLK OUT Over sampling clock. Can be programmed
to emit any frequ enc y up to 40 MHz, with
sub-Hz resolution. Intended for use as the
2 56 or 384fs oversampling clock by the
exter nal D/A conve rsion sub system.
AO_SCK IO •When AO is programmed to act as a
serial interface timing slave (RESET
default), A O_SCK acts as input. It
receives the serial cloc k from the exter-
nal audio D/A subsystem. The clock is
treated as fully asynchronous to the
PNX1300 main clock.
•When AO is programmed to act as
serial interface timing master , AO_SCK
acts as output. It drives the serial clock
for the external audio D/A subsystem.
Clock frequency is a programmable
integral divide of the AO_OSCLK fre-
quency.
AO_SCK is limited to 22 MHz. The sam-
ple rate of valid samples embedded within
the se r ial strea m is limited by the
AO_SCK maximum frequency and the
available highway bandwidth.
AO_WS IO •When AO is programmed as the serial-
interface timing slave (RESET default),
A O_WS acts as an input. AO_WS is
sampled on the opposite AO_SCK
edge at which AO_SDx are asserted.
•When AO is programmed as serial-
interface timing master, AO_WS acts
as an output. AO_WS is asserted on
the same AO_SCK edge as AO_SDx.
AO_WS is the word-select or frame-sync
signal from/to the ex ternal D/A sub-
system. Each audio channel receives 1
sample for every WS period.
AO_WS can be set to change on
AO_OSCLK positive or negative edges by
the CLO CK_E DGE bi t.
AO_SD1 OUT Serial data to stereo external audio D/A
subsystem. AO_SD1 can be set to
change on AO_OS C LK p os i tive or nega-
tive edges by the CLOCK_EDGE bit.
AO_SD2 OUT Serial data to stereo external audio D/A
subsystem. AO_SD2 can be set to
change on AO_OS C LK p os i tive or nega-
tive edges by the CLOCK_EDGE bit.
AO_SD3 OUT Serial data to stereo external audio D/A
subsystem. AO_SD3 can be set to
change on AO_OS C LK p os i tive or nega-
tive edges by the CLOCK_EDGE bit.
AO_SD4 OUT Serial data to stereo external audio D/A
subsystem. AO_SD4 can be set to
change on AO_OS C LK p os i tive or nega-
tive edges by the CLOCK_EDGE bit.
Table 9-1. AO unit external signals
Signal Type Description
FREQUENCY
AO_OSCLK
AO_SCK
AO_WS
div N+1 SCKDIV
div N+1
Square Wave DDS
9 × DSPCPUCLK
AO_SDx Parallel to Serial Converter
16
16 LEFT[15:0]
RIGHT[15:0]
(e.g. 64×fs)
WSDIV
31 0
70
08
(e.g. 256×fs)
32 AO_CC[31:0]
Figure 9-1. AO clock system and I/O interface
SER_MASTER
Philips Semiconductors Audio Out
PRELIMINARY SPECIFICATION 9-3
programmed to emit frequencies from approx. 1 Hz to 80
MH z wi th a sub H ertz r es olution.
The output of the DDS is always sent to the AO_OSCLK
output pin. This output is intended to be used as the
256fs or 384fs system c lo ck so urc e f or ov er s ampli ng D/A
converters, such as the Philips SAA7322, or codecs
such as the AD1847, CS4218, or UAD1340.
The PNX1300 DDS frequency is set by writing to the
FR EQU ENCY MMIO r e gi ster . The p rog ra mmer is free t o
change the FREQUENCY setting dynamically, in order
to adjust the outgoing audio sample rate. In ATSC trans-
port stream decoding, this is the method by which the
system software locks audio output sample rate to the
original program provider sample rate.
Depending on bit 31 (MSB), the DDS runs in one of the
two following modes:
•bit 31 = 1 (standa rd improved m ode)
•bit 31 = 0 (TM-1000 compatibility mode)
9.4.1 PNX1300 Standard Improved Mode
This mode was first available in the TM-1100. In this
mode, a high qu ality, low-jitter AO_OSCLK is generated.
The setting of the FREQUENCY register to accomplish a
given AO_O SCLK freque ncy is g iven by the formula:
This mode, and the above formula, should be used for all
In the improved mode the DDS synthesizer maximum jit-
te r c an be c omp ut e d as f o llow s :
Ex am pl e of jitt e r value s ca n be fo un d in Table 9-3.
Table 9-2. Clock system setting (fDSPCPU=133 MHz)
fsOSCLK SCK FREQUENCY SCKDIV
44.1 kHz 256fs 64fs 2187991971 3
48.0 kHz 256fs 64fs 2191574340 3
44.1 kHz 384fs 64fs 2208246133 5
48.0 kHz 384fs 64fs 2213619686 5
Ta ble 9-3. Jitter values for common DSPCPU MHz
fDSPCPU
(MHz) jitter
(nSec) fDSPCPU
(MHz) jitter
(nSec)
143 0.777 180 0.617
166 0.669 200 0.555
FREQUENCY 231 fOSCLK 232
⋅
9fDSPCPU
⋅
------------------------------+=
jitter 1
9fDSPCPU
⋅
-----------------------------=
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-4 PRELIMINARY SPECIFICATION
9.4.2 TM-1000 Compatibility Mode
TM-1000 clock compatibility mode is provided so that
TM-1000 audi o software runs wi thout change s. It shoul d
NOT be used for new software development , due to a 3x
higher jitter. TM-1000 mode is automatically entered
whenever FREQUENCY[31] = 0. In TM-1000 mode,
AO_OSCLK frequency is set as follows:
9.5 CLOCK SYSTEM OPERATION
The output of the DDS is always sent to the AO_OSCLK
output pin . This output is typically used as the 256 fs or
384fs system clock source for oversampling D/A convert-
ers, such as the Philips SAA7322, or codecs such as the
AD 1847, CS4218 or UD1340.
AO_ WS and AO_S CK are sent to each e xtern al D /A co n-
verter in the master mode.
AO_WS, the word strobe, determines the sample rate:
each active channel receives one sample for each
AO_WS period.
AO _SC K is t he da ta bit c loc k. T he n umb er of AO _SC K
clocks in an AO_WS period is the number of data bits in
a serial frame required by the attached D/A converter .
AO_WS is a divider of the bit clock and is set using WS-
DI V to cont rol the s eri al fram e le ng th . Th e nu mb er of bit s
per frame is equal to WSDIV+1. There are some mini-
mum length requirements for a serial frame, refer to
Section 9.6.1.
AO_ SCK an d AO _WS ca n be conf ig ur ed a s in pu t or ou t-
put, as determined by the SER_MASTER control field. If
set as outp ut, AO _SCK c an be set to a divi der of the DDS
output frequen cy.
Whe ther set as i nput or outp ut , the AO_SCK pin signal is
always used as the bit clock for parallel-serial conver-
sion. T he A O _WS p in always acts as the tr igger to start
the generation of a s erial fra me. AO_WS can similarly be
programmed using WSDIV to control the serial frame
length. The number of bits per frame is equal to WS-
DIV+1.
Th e pref erre d u se o f the c loc k sy stem opt ions is t o use
AO_OSCLK as D/A master clock, and let the D/A con-
verter be a timing slave of the serial interface
(S ER_MASTER=1). This is importa nt in view o f compa t-
ibility with future Trimedia devices, which may on ly su p -
port the AO unit as serial interface master.
Som e D /A con ve rte rs ho w ev er, like the AD 1847 , prov id e
better SNR properties if they are configured as serial
master, with the AO unit as slave (SER_MASTER=0). As
illustrated by Figure 9-1, the internal parallel to serial
converter t hat constr ucts the serial frame is oblivious to
which compon ent is timing master.
9.6 SERIAL DATA FRAMING
The AO unit c an gene rate data in a wide variety o f serial
data framing conve ntions. Figure 9-2 illustrates the no-
tion of a serial frame. If POLARIT Y=1, a frame starts with
a positive edge of the AO_WS signal. If POLARITY=0, a
serial frame starts with a negative edge on AO_WS. If
CLOCK_EDGE=0, the parallel to serial converter sam-
ples AO_WS on a positive clock edge transition, and out-
put s t he firs t bit ( b it 0) of a seri al fr ame o n t he next falli ng
edge of AO _SCK .
If CLOCK_EDGE=1, the parallel to serial converter sam-
ple s AO_W S on th e negat ive ed ge of AO_SC K, wh ile au-
dio data is o utp u t on the po siti ve edge , i.e. th e A O _S C K
polar ity would be r e ver s ed w it h respe ct t o Figure 9-2.
FREQUENCY fOSCLK 232
⋅
3fDSPCPU
⋅
------------------------------=
SCKDIV 0 255[, ]∈
fAOSCK fAOOSCLK
SCKDIV 1+
----------------------------------=
Table 9-4. AO MMIO Clock & I nte rface Control
Field Name Description
SER_MASTER 0 ⇒ (RESET default), the D/A subsystem
is the timing master over the AO
se r ial in ter face. AO_SCK and
A O_WS act as inputs.
1 ⇒ PNX1300 is the timing master over
the serial interface. AO_SCK and
A O_WS act as outputs. T his mode is
requi red for 4,6 o r 8 cha nnel opera-
tion.
The SER_MASTER bit should only be
changed while the A O unit is disabled, i.e.
TRAN S_EN A BL E = 0.
FREQUENCY Sets the clock frequency emitted by the
AO_O SCLK outp ut. RESET de fault 0.
SC KDIV Sets t he divider used to derive AO_SCK
from AO_OSCLK. Set to 0..255, fo r divi-
sion by 1 ..256. RESET default 0.
WSDIV Sets the divider used to derive AO_WS
from AO_SCK. Set to 0..511 fo r a serial
frame length of 1..512. RESET default 0.
7654321031302928272625242322212019181716151413121110987654321 framen
0framen+1
3130
framen-1
AO_SCK
AO_WS
AO_SDx
Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0)
Philips Semiconductors Audio Out
PRELIMINARY SPECIFICATION 9-5
Every serial fram e transm its a single left and right chan-
nel sample, and optional codec co ntr ol da t a to each D /A
converter. The left and right sample data can be in an
LSB first or MSB first form, at an arbitrary serial frame bit
position, and with an arbitrary length.
In MS B-fi rst m od e (DA TAM O DE = 0), th e p ara ll el to se-
rial converter sends the value of LEFT[MSB] in bit posi-
tion LEFTPOS in the serial frame. Subsequently, bits
from decreasing bit positions in the LEFT data word, up
to an d incl udin g LEFT[ SSPOS] , are transm itt ed in or der.
In LSB-first mode (DATAMODE = 1), the parallel-to-seri-
al c onve rte r se nd s the v a lue of LEFT[SSPOS] in bit po-
sition LEFTPOS in the serial frame. Subsequent bits
from the LEFT data word, up to and including
LEFT[MSB], are transmitted in order. Table 9-6. shows
the transmitted bits in different modes.
Frame bits that do not belong to either LEFT[MSB:SS-
POS] or RIGHT[MSB:SSPOS] or a codec control field
(Section 9.7, “Codec Control”) are shifted out as zero.
This zero extension ensures that PNX1300 can be used
in combination with D/A converters of higher precision
th an the ac tual num ber of trans mitt ed bit s in the curr en t
operating mode, e.g. 18-bit D/As operating with 16-bit
memory data.
9.6.1 Serial Frame Limitations
Due to the implementation, there is a minimum serial
fr am e le ng th requ i re d t ha t is op er a ting mode de pe ndent.
This is shown in Table 9-7.
Table 9-5. AO Serial Framing Control Fields
Field Nam e Descr iptio n
POLARITY 0 ⇒ serial frame starts with an AO_WS
negedge (RE SET default)
1 ⇒ serial frame starts with an AO_WS
posedge
This bit should NOT be changed during
operation of the AO unit, i.e. only update this
bit when TRANS_ENABLE = 0.
LEFTPOS(9) Defines the bit position within a serial frame
where the first data bit of the left channel is
placed. Reset default ‘0’.
RIGHTPOS(9) Defines the bit position within a serial frame
where the first data bit of the right channel is
placed. Reset default ‘0’.
DATAMODE 0 ⇒ MSB first (RESET default)
1 ⇒ LSB first
SSPOS Start/Stop bit position. Reset default 0. Note
that SSPOS is a 5-bit field, with SSPOS bi t 4
not-a djac ent. This is for backwards compati-
bility in 16 bits/sample modes with TM-1000/
1100.
• If DATAMO DE=MSB first, transmissio n
starts with the MSB of the sample, i.e. bit
15 for 16 bits/s ample modes or bit 31 for 32
bits /sample modes . SSPOS de term ines
the bit index (0..31) in the parallel input
word of the last transmitted data bit.
• If DATAMO DE= L SB fir st, SS PO S det er-
mines the bit index (0..31) in the parall el
word of the first transmitted data bit. Bits
SSPOS up to/including the MSB are trans-
mitted, i.e. up to bit 15 in 16 bits/sample
mode and bit 31 in 32 bit s /sample mode.
See Table 9-6 for more information.
CLOCK_EDGE 0 ⇒ the parallel to serial c onver ter sa mpl es
AO_WS on positive edges of AO_SCK
and outputs data on the negative edge
of AO_SCK (R ESET default).
1 ⇒ the parallel to serial c onver ter sa mpl es
AO_WS on negative edges of AO_SCK
and outputs data on positive edges of
AO_SCK.
WS_PULSE 0 ⇒ emit 50% AO_WS (RESET default).
1 ⇒ emit single AO_SCK cycle AO_WS
NR_CHAN 00 ⇒ Only AO _SD1 is active
01 ⇒ AO_SD1 and 2 are active
10 ⇒ AO_SD1, 2 and 3 are active
11 ⇒ AO_SD1..SD4 are active
Each SD output either receives 1 or 2 chan-
nels dependin g on TRANS_MODE mono
resp. stereo . Non-active channels receive 0
value samples. In mono modes, eac h chan-
nel of a SD output receives identical left &
ri ght samples. See als o Table 9-10.
Table 9-6. Bits transmitted for each memory data
item S
operating mode first
bit last
bit
valid
SSPOS
values
16 bits/sample, MSB-first S[15] S[SSPOS] 0..15
16 bits/sample, LSB-first S[SSPOS] S[15] 0..15
32 bits/sample, MSB-first S[31] S[SSPOS] 0..31
32 bits/sample, LSB-first S[SSPOS] S[31] 0..31
Table 9-7. Minimum serial frame length in bits
operating mode minimum serial fr ame length
16 bits/sample, mono 13 bits
32 bits/sample, mono 13 bits
16 bits/sample, stereo 13 bits
32 bits/sample, stereo 36 bits
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-6 PRELIMINARY SPECIFICATION
9.6.2 I2S Ser ial Framing Exam ple
Refer to Figure 9-3 and Table 9-8 to see how th e AO unit
MMIO regi ster s should be set to tra nsmit 16 or 32 bits of
stereo data via an I2S serial standard to an 18-bit D/A
converter with a 64-bit serial frame.
9.7 CODEC CONTROL
In addition to the left and right data fields that are gener-
ated based on autonomous DMA action, a serial frame
generated by the AO unit can be set to contain 1 or 2
control f iel ds up to 16 bi ts in leng th. E ach control f ield can
be independently enabled/disabled by the CC1_EN,
CC2_EN bits in AO_CTL. The content shifted into the
fr ame is ta ken fro m the CC1 and C C2 fi eld in the AO_CC
register. The CC1_POS and CC2_POS fields in the
AO_CFC register determine the first bit position in the
frame where the control field is emitted. The field is emit-
ted observing the setting of DATAMODE, i.e. LSB or
MSB first.
The CC_BUSY bit in AO_STATUS indicates if the AO
unit is ready to receive another CC1, CC2 value pair.
Writing a new value pair to AO_CC writes the value into
a buffer register, and raises the CC_BUSY status. As
soon as b ot h C C 1 an d C C2 v al ue s hav e be en c op ied to
a shadow register in preparation for transmission,
CC_BUSY is negated, indicating that the AO logic is
rea dy to ac cep t a new code c control pai r. Th e old CC1/
CC2 data keeps being transmitted - i.e. software is not
required to provide new CC1 and CC2 data.
Sof tware always ne eds t o ensur e that the CC _BUSY sta-
tus is negated before writing a new CC1, CC2 pair. By
polling CC_BUSY, the DSPCPU can emit a sequence of
individual audio frames with distinct control field values
reliably. This can, for example, be used during codec ini-
ti al iz at io n. No p rov is io n i s ma de for in t err up t dri ven oper -
ation of such a sequence of control values; it is assumed
that after initialization, the value of control fields deter-
mine s lo w , asy nc h ronou s c h angi ng pa r am e ters suc h as
volume.
It is legal to program the control field positions within the
fr am e su ch th at CC1 an d CC2 ov e rl ap each othe r and/or
left/right data fields. If two fields are defined to start at the
same bit position, the priority is left (highest), right, CC1
th en CC 2 . The fie ld w i th th e highes t pr ior it y wi ll b e em it-
ted starting at the conflicting bit position. If a field f2 is de-
fined to start at a bit position i that f alls within a field f1
starting at a lower bit position, f2 will be e mitt e d st ar ti ng
from i and th e r es t of f1 will be lost. Any bit positions not
belong ing to a d at a or contr o l fie l d wil l be em itt ed as ‘0’.
Table 9-8. Example setup for 64-bit I2S framing
Field Value Explanation
POLARITY 0 Frame starts with negedge AO_WS.
LEF TPO S 0 LEFT[ms b] will go to ser ial fram e
position 0.
RIGHTPOS 32 RIGHT[msb] will go to serial frame
position 32.
DATAM ODE 0 MSB fi rst.
SSPOS 0 Stop with LEFT/RIGHT[0], send 0’s
after.
(for 32 bits/samp le m ode, this fi el d
could be set to 14 to ensure zeroes
in all unused bit positions)
CLOCK_EDGE 0 AO_SDx change on negedge
AO_SCK
WSDIV 63 Serial frame length = 64.
WS_PULSE 0 emit 50% duty cycle AO_WS.
163625251503332313018173210 0 left channel datan+1(18)
left channel datan(18) right channel datan(18)
49
Figure 9-3. Serial frame (64 bits) of a 18-bit precision I2S D/A converter.
AO_SCK
AO_WS
AO_SDx
Table 9-9. AO MMIO codec control/status fields
Field Nam e Descr ip tion
CC1 (16) The 16 -bit value of CC1 is shifted into each
emitted serial frame starting at bit position
CC1 _PO S, as long as CC1_EN is ass erted.
CC1 _PO S Defines the bit position within a ser ial fra me
where the first data bit of CC1 is placed.
RESET Default 0.
CC1_EN 0 ⇒ CC1 emission disabled (RESET de f ault )
1 ⇒ CC1 emi ssion enabled.
CC2(16) The 16-bit value of CC2 is shifted into each
emitted serial frame starting at bit position
CC2 _PO S, as long as CC2_EN is ass erted.
CC2 _PO S Defines the bit position within a ser ial fra me
where the first data bit of CC2 is placed.
De fault 0.
CC2_EN 0 ⇒ CC2 emission disabled (RESET de f ault )
1 ⇒ CC2 emi ssion enabled.
CC_BUSY 0 ⇒ AO is ready to receive a CC1, CC2 pair
(RES ET default).
1 ⇒ AO is not ready to receive a CC1, CC2
pair. Try a gai n in a few SCK cl ock i nter-
vals.
Philips Semiconductors Audio Out
PRELIMINARY SPECIFICATION 9-7
Figure 9-4 shows a 64-bit frame suitable for use with the
CS4218 codec. It is obtained by setting POLARITY=1,
LEFTPOS=0, RIGHTPOS=32, DATAMODE=0, SS-
POS=0, CLOCK_EDGE=1, WS_PULSE=1, CC1_POS =
16, CC1_EN=1, CC2_POS=48, CC2_EN=1.
Note that frames are generated (externally or internally)
even when TRANS_ENABLE is de-asserted. Writes to
CC1 and CC2 should only be done after
TRANS_ENABLE is assert ed. The ‘first’ CC values will
th en go out on the ne x t frame . For a s umma r y of cod e c
contr ol fields se e Table 9-9
9.8 MEMORY DATA FORMATS
Th e AO un it au ton om ous l y re ad s samp les fr o m me m ory
in 16 or 32 bit-per-sample memory formats, as shown in
Figure 9-5 for some example modes. Memory samples
are retr i ev e d and us e d as de sc ribed in Table 9-10. Suc-
ce s sive samples ar e alwa y s read fr om inc r easing me m-
ory address locations. The setting of the
LI TTL E _ E ND IAN b it in th e A O _ C TL regi ster deter m in es
the byte order of retrieved 16 or 32 -bit samples. Refer to
Appendix C, “Endian-ness,” for details on byte ordering con-
ventions.
AO ha rdw are i mple men ts a do uble bu fferin g s cheme t o
ensure that there are always sam ple s available to t r a ns -
mit , even if the D SPCP U is hig hl y lo ad ed and slow to re-
spond to interrupts. The DSPCPU software assigns 2
equal size buffer s by writing a base address and size to
the MMIO co ntr ol fie l ds de scri be d in Figure 9-6. Refer to
Section 9.9 , “Au di o O u t O p era t io n ,” for details on hard-
ware/software synchronization.
If SIGN_CONVERT is set to one, the MSB of the memory
data is inve rted, which is eq uivalent to translating from
offset binary representation to two’s complement. This
allows the use of an external two’s complement 16- bit D/
A co nv ert er to g en era te au dio f r om 16-bi t u nsig ne d s am-
ples. This MSB inversion also applies to the ‘0’ values
tra nsm itted to non-ac t iv e ou t p ut ch an nels .
Note that th e A O ha rdwar e does not support A-law or µ-
law eight-bit data formats. If such formats are desired,
the DSPCPU should be used to convert from A-law or µ-
law data to 16-bit linear data.
Table 9-10. Operating modes and memory formats
NR_CHAN MODE destination of successi ve s a mples
00 mono SD1.left
00 stereo SD1.left, SD1.right
01 mono SD1.left, SD2.left
01 stereo SD1.left, SD1.right, SD2.left, SD2.right
10 mono SD1.left, SD2.left, SD3.left
10 stereo SD1.left, SD1.right, SD2.left, SD2.right,
SD3.left, SD3.right
11 mono SD1.left, SD2.left, SD3.left, SD4.left
11 stereo SD1.left, SD1.right, SD2.left, SD2.right,
SD3.left, SD3.right, SD4.left, SD4.right.
Figure 9-4. Example codec frame layout for a Crystal Semi, CS4218.
16362
484732313210 0
left datan+1(16)
left channel datan(16) right channel datan(16)
15 CC1(16)
16
lsb lsb lsb CC2(16) lsb
AO_SCK
AO_WS
AO_SDx
Figure 9-5. AO memory DMA formats.
adr
SD1.leftn
adr+2
SD1.rightn
adr+4
SD1.leftn+1
adr+6
SD1.rightn+1
adr+8
SD1.leftn+2
adr+10
SD1.rightn+2
adr+12
SD1.leftn+3
adr+14
SD1.rightn+3
16-bit, stereo,
NR_CHAN=00
32-bit, stereo,
NR_CHAN=00 SD1.leftn
adr
SD1.rightn
adr+4
SD1.leftn+1
adr+8
SD1.rightn+1
adr+12
adr
SD1.leftn
adr+2
SD1.rightn
adr+4
SD2.leftn
adr+6
SD2.rightn
adr+8
SD3.leftn
adr+10
SD3.rightn
adr+12
SD1.leftn+1
adr+14
SD1.rightn+1
16-bit, stereo,
NR_CHAN=10
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-8 PRELIMINARY SPECIFICATION
9.9 AUDIO OUT OPERATION
Figure 9-6, Table 9-11 and Table 9-12 describe the func-
tion of the control and status fields of the AO unit. To en-
sure compatibility with future devices, any undefined or
reserved MMIO bits sh ould be ig nored whe n read, and
written as zeroes
The AO unit is reset by a PNX1300 hardware reset, or by
wr iti n g 0 x8 000 0000 to th e AO _C TL reg i st er. The AO un it
is not affected by DSPCPU reset initiated through the
BIU_CTL register. Either reset method sets all MMIO
fields as indicated in the tables.
The timestamp counter is reset by TRI_RESET# or by
DSPCPU r ese t init iated t hro ugh BI U_CTL. It i s not af fec t-
ed by AO_CTL reset. This ensures that the timestamp
counter stays synchronous with the DSPCPU
CCCOUNT register.
After an AO reset, 5 AO_SCK clock cycles are required
to stabilize the internal circuitry before enabling Audio
Out. This can be accomplished by programming the
AO_FREQ and AO_SERIAL registers to start AO_S CK
generation then waiting for the appropriate 5 AO_SCK
cycle interval.
Program ing of the A O_SERI A L MMI O r egis ter needs to
follow the following sequence order:
•set AO_FRE Q to ensure that a valid cl ock is ge ner-
ated (Only when AO is the master of the audio clock
system)
•MMIO(AO_CTL) = 1 << 31; /* Software Reset */
Figur e 9-6. A O status/co ntrol field MMIO layout.
MMIO_base
offset:
AO_S TA TUS (r/w)0x10 2000
AO_CTL (r/w)0x 10 2004
AO_SERIAL (r /w)0 x10 2008 SCKDIV
AO_FRAMING (r/w )0x10 200C
AO_FREQ (r/w)0x10 2010
AO_BASE1 (r/w)0x10 2014
FREQUENCY
BUF1_ACTIVE
AO_BASE2 (r/w)0x10 2018 BASE2
AO_SIZE (r/w)0x10 201C SIZ E (in samples)
31 0371115192327
BASE1
UNDERRUN
HBE (Highway bandwidth error)
BUF2_EMPTY
RESET
TRANS_ENABLE
TRANS_MODE
SIGN_CONVERT
LITTLE_ENDIAN
0
UDR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_UDR
ACK_HBE
ACK2
ACK1
WSDIV
DATAMODE
CLOCK_EDGE
POLARITY
LEFTPOS RIGHTPOS SSPOS
00000
000000
SLEEPLESS
BUF1_EMPTY
AO_CC (r/w)0x10 2020
AO_CFC (r/w)0x10 2024 CC1_POS CC2_POS
CC2CC1
CC1_EN
CC2_EN
WS_PULSE
CC_BUSY
NR_CHAN
000000
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
RESERVED
SSPOS[4]
AO_TSTAMP (r/o )0x10 2028 TIMESTAMP
31 0371115192327
SER_MASTER
Philips Semiconductors Audio Out
PRELIMINARY SPECIFICATION 9-9
•MMIO(AO_SERIAL) = 1 << 31; /* sets serial-master
mode, starts AO_SCK */
•MMIO(AO_SERIAL ) = (1 << 31) | (SCKDIV value); /*
then set DIVIDER values */
Upon reset, transmission is disabled (TRANS_ENABLE
= 0), and buff er 1 is the ac tive buff er (BU F1_ A CTI VE =1).
The DSPCPU initiates transmission by providing two full
equal size buffers and putting their base address and
size in the BASEn and SIZE registers. Once two valid
buffers are assigned, transmission can be enabled by
writing a ‘1’ to T RANS_ ENABLE. T he AO hard w are now
proceeds to empty buffer 1 by transmission of output
samples. Once buffer 1 empties, BUF1_EMPTY is as-
serted, and transmission continues without interruption
from buffer 2. If BUF1_INTEN is enabled, a SOURCE 12
interrupt request is generated.
Note that buffer s mus t be 64-byte a ligned (t he si x LSB s
of A O _BA SE1 , AO_BASE2 are z ero). Buffe r sizes mus t
be a multiple of 64 samples (the 6 LSB’s of AO_SI ZE ar e
zero).
The DSPCPU is required to assign a new, full buffer to
BASE1 and perform an ACK1 before buffer 2 empties.
Transmission continues from buffer 2 until it is empty. At
that time, BUF2_EMPTY is asserted and transmission
continues from the new buffer 1, etc. An ACK performs
two fu ncti on s: it te ll s the A O unit t h at th e co rresp on di ng
BASE register now points to a buffer filled with samples,
and it clears BUF_EMPTY. Upon receipt of an ACK, the
AO hardware removes the BUF_EMPTY related inter-
rupt request line assertion at the next DSPCPU clock
edge. Refer to the interr upt controlle r document atio n for
details on interrupt handler programming. The AO inter-
rupt (SOURCE 12) should always be operated in level
se n si tiv e mode
9.10 INTERRUPTS
The AO unit has a private interrupt request line to the
DSPCPU vectored interrupt controller. It uses SRC# 12
(same as TM-1000/TM-1100/T M-1300 AO).
An interrupt is asserted as long as one or more of the
UNDERRUN, HBE, BUF1_EMPTY or BUF2_EMPTY
condition f l ags and the corr e sponding I N TEN bit ar e as -
serted. Interr upts are s ticky, i.e. an int errupt re main s as-
serted until the software explicitly clears the condition
flag by an ACK_x action.
Table 9-1 1. AO MM IO DMA control fields
Field Nam e Descr ip tion
LITTLE_ENDIAN 0 ⇒ big endian memory format (RESET
default)
1 ⇒ little endian
BASE1 Base Address of buffer1. Must be a 64-
byte aligned address in local SDRAM.
RESET default 0.
BASE2 Base Address of buffer2. Must be a 64-
byte aligned address in local SDRAM.
RESET default 0.
SIZE DMA buffer size, in samples.
T hi s n um be r of mo no sa m pl e s or st ereo
sample pairs is read from a DMA buffer
before swi tching to the other buffer.
Buffer size in bytes is as follows:
16 bps, mono : 2 * SIZE
32 bps, mono : 4 * SIZE
16 bps, stereo : 4 * SIZE
32 bps, stereo : 8 * SIZE
RESET default 0.
TRANS_MODE 00 ⇒ mono, 32 bits/sample. (RESET
default). Left data and Right data
sent to each active output are the
same.
01 ⇒ stereo, 32 bits/sample
10 ⇒ mono, 16 bits/sample. Left data
and Right data are the same.
11 ⇒ stereo, 16 bits/sample
Ref er to Table 9-10 for an explanation of
how TRANS_MODE and NR_CH AN
map to output behavior.
SIGN_CONVERT 0 ⇒ leave MSB unchanged (RESET
default)
1 ⇒ invert MSB
(not applied to codec control fields)
Table 9-12. AO DMA status fi elds (r ead only)
Field Nam e Descr ip tion
BUF1_ACTIVE •If 1, buffer 1 will be used for the next sam-
ple to be transmitted.
•If 0, buffer 2 will contain the next sample
(1 after RESET).
BUF1_EMPTY •If 1, buffer 1 is empty.
•If BUF1_INTEN is also 1, an interrupt
request (source 12) is asserted.
•BUF1_EMPTY is cleared by writing a ‘1’
to ACK1, at which point the AO hardware
will assume that BASE1 and SIZE
describe a new full buffer.
•0 after RESET.
BUF2_EMPTY •If 1, buffer 2 is empty.
•If BUF2_INTEN is also 1, an interrupt
request (source 12) is asserted.
•BUF2_EMPTY is cleared by writing a ‘1’
to ACK2, at which point the AO hardware
will assume that BASE2 and SIZE
describe a new full buffer.
•0 after RESET.
HBE •High way Bandwi dth Error.
•0 after RESET.
•Indicates that no data was transmitted
due to inability to read the local AO buffer
from SDRAM in time. This indicates an
insufficient allocation of PNX1300 High-
way bandwidth for the audio sampling
rate/mode.
UNDERRUN •An UNDERRUN erro r h as o ccurred, i.e.
the CPU failed to provide a full buffer in
time, and no samples were transmitted,
although req ues ted by the D/A converter.
•If UDR_INTEN is also 1, an interrupt
request (source 12) is pending. The
UNDERRUN flag can ONLY be cleared by
writ ing a ‘1’ to ACK_UD R .
•0 after RESET.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-10 PRELIMINARY SPECIFICATION
9.11 TIMESTAMP
The AO_TSTAMP MMIO register provides a 32-bit
timestamp value that contains the CCCOUNT time value
at which the last sample of the last DMA buffer t ransmit-
ted was sent across the SD output pin. This value is
availa ble f o r softw ar e insp ection ( r ea d-only ) in t he inter -
rupt handler for BUFx_EMP TY.
The implementation involves an internal DSPCPU clock
c ycle cou nt e r that is res et to ha ve t he same val u e a s th e
DSPCPU CCCOUNT register. It is guaranteed to be in
sync with the 32 LSB of CCCOUNT provided that PC-
SW.CS=1.
9.12 POWERDOWN AND SLEEPLESS
The AO unit enters powerdown state whenever
PN X13 00 i s p ut in gl ob al po wer dow n mode , excep t i f the
SLEEPLESS bit in AO_CTL is set. In the latter case, the
block continues DMA operation and will wake up the
DSP CPU whenever an interrupt is gene ra ted. The inter-
nal timestamp counter never powers down to ensure that
it remains synchronous with CCCOUNT.
Th e AO u nit can be se par ately power ed do w n by set ting
a bit in the BLOCK_POWER_DOWN register. Refer to
Chapter 21, “Power Management.”
If the block enter s powerdown state, AO_SCK, AO_SDx,
and AO _WS hold their v al ue stable . AO_ O S C LK contin-
ues to provide a D/A converter clock. The signals r esume
th eir ori gina l tr an si t io n s a t t he po in t wh ere the y w e re in -
terrupted once the system wakes up. The external D/A
converter subsystem is most likely confused by this be-
havior, hence it is recommended AO unit to be stopped
(by negatin g TRANS_ ENABLE) befo re block level po w-
erdown is started, or that SLEEPLESS mode is used
whe n gl obal po werdow n is ac ti vated.
9.13 HIGHWAY LATENCY AND HBE
The AO unit uses an internal 64-byte buffer as well as an
output holding register that contains a single mono sam-
ple or single stereo sample pair. Under normal operation,
the internal buffer is refreshed from SDRAM fast enough
to a void an y mis sing sample s, w hile data is being emit -
ted fr om the hol d in g regi st er . If the high w ay arbit er is set
up with an insufficient latency guarantee, the situation
can arise that the 64-byte buffer is not refilled and the
holding register is exhausted by the time a new output
sample is due. In that ca se the HB E error is raised. The
last sample for each channel will be repeated until the
buffer is refreshed. The HBE condition is sticky, and can
only be cleared by an explicit ACK_HBE. This condition
indicates an incorrect setting of the highway bandwidth
arbiter.
Given a sample rate fs, and a n as s oc iated sam pl e int e r-
val T (in ns), the arbiter should be set to have a latency
of at mo st T -2 0 ns f or a ll mo des . The laten cy for 4,6 and
8 ch annel mode s can be c omput ed as if the system i s op-
erating in stereo mode with a 2x, 3x respectively 4x sam-
ple rate.
Table 9-14 shows the r equi red arbit er la tenc y setti ngs for
a number o f common operating modes. The rig ht most
column in illustrates the nature of the resulting 64-byte
highway requests. Is not necessary to compute arbiter
settings, but they may be used to compute bus availabil-
ity in a given interval.
Refer to Cha pter 20, “Arbiter,” f or information on arbiter
programming.
Table 9-1 3. AO MMIO Control F ields
Field Name Description
RESET Resets the audio-out logic. See Section
9.9, “Audio Out Operation” for a descrip-
tion of the recommended procedure.
TRAN S_E NABLE Transmiss ion Enable flag .
0 ⇒ (RESET default) AO inactive.
1 ⇒ AO transmits samples and acts as
DMA master to read samples from
local SDRAM.
Do NO T change the POLARITY bit while
transmission is enab led.
SLEEPLESS 0 ⇒ (power up default) AO goes into
power-down mode if PNX1300 goes
to global powerdown mode.
1 ⇒ AO continues operation when
PNX1300 goes to global powerdown
mode. Samples are read from mem-
ory as needed, and AO interrupts,
when enabled, will wake up the
DSPCPU.
BUF1_ INTEN Buffer 1 Em pty I nter rupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if buffer 1
empty
BUF2_ INTEN Buffer 2 Em pty I nter rupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if buffer 2
empty
HBE_INTE N HBE Interr up t Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if a highway
bandw idth error occurs.
UDR_INTEN UNDERRUN Interrupt Enable.
0 ⇒ (default) no interrupt
1 ⇒ interrupt (SOURCE 12) if an
UNDERRUN error occurs
ACK1 • Write a 1 to clear the BUF1_EMPTY flag
and remove any pending BUF1_EMPTY
interrupt request.
• ACK1 always reads 0.
ACK2 • Write a 1 to clear t he BU F2_EMPTYflag
and remove any pending BUF2_EMPTY
interrupt request.
• ACK2 always reads 0.
ACK_HBE •Write a 1 to clear the HBE flag and
•remove any pending HBE interrupt
request.
•ACK_HBE always reads as 0.
ACK_UDR •Write a 1 to clear the UNDERRUN flag
and remove any pending UNDERRUN
inter rupt re quest.
•ACK_UDR a lways r eads 0.
Philips Semiconductors Audio Out
PRELIMINARY SPECIFICATION 9-11
9 . 14 E R ROR BE HAVIOR
In normal operation, the DSPCPU and AO hardware
continuously exchange buffers without ever failing to
transmit a sample. If the DSPCPU fails to provide a new
buffer in time, the UNDERRUN error flag is raised, and
the last valid sa mple o r sample pa ir is repeated until a
new buffer of data is assigned by an ACK1 or ACK2. The
UNDERRUN flag is not affected by ACK1 or ACK2; it can
only b e clea r ed by an explici t ACK_UDR.
If an HBE error occurs, the last valid sample or sample
pair is repeated until the AO hardware retrieves a new
sample buffer across the highway.
Table 9-14. AO highway arbiter latency requirement
examples
TransMode fs
(kHz) T
(ns)
max.
arbiter
latency
(ns)
access
pattern
stereo
16 bits/sample 44.1 22,676 22,656 1 request e very
362,812 ns
stereo
16 bits/sample 48.0 20,833 20,813 1 request every
333,333 ns
stereo
16 bits/sample 96.0 10,417 10,397 1 request every
166,667 ns
6 channel
16 bits/sample 48.0 20,833 6,924 1 request every
111,111 ns
stereo
32 bits/sample 48.0 20,833 20,813 1 request every
166,667 ns
6 channel
32 bits/sample 48.0 20,833 6,924 1 request every
55,556 ns
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
9-12 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 10-1
SPDIF Out Chapter 10
by G ert Slavenburg, Santan u Du tta
10.1 SPDIF OUT OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
Th e PN X1 300 S P D IF Out put unit (SP D O) all ow s ge ne r-
ati on of a 1-bi t hig h-spee d ser ial dat a stream . The pri ma-
ry ap plic ation is to mak e SP D IF ( Sony /P h ilip s Digital In -
terface) data available for use by external audio
equipment.
The S PDO unit has the following features:
•fully compliant with IEC958, for both consumer and
profession al appl icatio ns
•supports 2-channel linear PCM audio, with 16 or 24
bits per sample
•suppor ts one or more Dolby Digital(r) 6-channel data
streams embedded per Project 1937
•supports one or more MPEG-1 or MPEG-2 audio
streams embedded per Project 1937
•allows arbitra ry, programmable, sam ple rates from 1
Hz to 30 0 kH z
•can output data with a sample rate independent of
and asynchronous to the sample rate of the Audio
Out (AO) unit
•hardware performs autonomous DMA of memory
resident IE C958 sub-frames
•hardware performs parity generation and bi-phase
mark encoding
•allow s s oftw are t o have full c ont rol over al l da ta con -
te nt, incl udin g user and c han ne l data
Alternate use of the SPDO unit to generate a general-
purpose high-speed data stream is possible. Potential
appl ic ation s in clud e use as a high -sp eed U AR T or hi gh
speed se r ia l da t a ch an ne l. I n th is case features are:
•up t o 40 M bit/se c data rat e
•full software control over each bit cell transmitte d
•LSB first or MSB first data format
10.2 EXTERNAL INTERFACE
The ex ternal interf ace co nsists of only one pin, SP DO,
which is described in Table 10-1.
An external circuit (see Figure 10-1) is required to pro-
vide an electrically isolated output and convert the 3.3 V
out put p in to a d riv e lev el of 0.5 V pe ak-p eak in to a 75 -
ohm load, as required for consumer applications of IEC-
958.
10.3 SUMMARY OF OPERATION
In both SPDIF and transparent DMA modes, SPDO
sends alternating memory data buffers out across the
output pin. Software initially gives SPDO two memory
data buffers and enables the S P DO unit. When the first
buffer is sent, SPDO requests a new buffer from software
while switching over to use the other buffer, etc. Trans-
miss io n c on t inue s u ni nt err upt ed unt il the unit is di sable d.
10. 3 .1 SPD IF M o de
SPDIF driver software assembles SPDIF data in each
mem ory dat a bu ffer. Ea ch me mory data b uffer c onsis ts
of groups of 32-bit words in memory. Each word de-
scribes the data to be transmitted for a single IEC-958
sub-frame, including what type of preamble is to be in-
cl uded . Ea ch s ub-fr am e is tr an smit ted in 64 -clo ck c ycle
intervals of the SPDO clock, a programmable clock gen-
era te d by th e S PD O Di rec t D igi t a l Syn the s iz er (DDS ).
10.3.2 Transparent DMA Mode
In transparent DMA mode, software prepares each data
bit exac tly as it is to be t rans mitte d, in a serie s of 32-bi t
words in each memory data buff er. Each 32-bit word is
Tabl e 10- 1. S PD O ext ernal sign a ls
Signal Type Description
SPDO I/O SPDIF output. Self clocking interface
carrying either 2-channel PCM data with
samples up to 24 bits, or encoded Dolby
AC-3(r) or MPEG audio data for decod-
ing by an external audio component.
Figure 10-1. External SPDIF interface circuitry
10 uF 240E
110E
transformer
1:1
1.5 - 7 MHz
RCA
phono
SPDO
PNX1300
PNX1300/01/ 02/11 Data Book Philips Semiconductors
10-2 PRELIMINARY SPECIFICATION
transmitted LSB first or MSB first in 32-clock cycle inter-
vals of the SPDO clock, a programm able cloc k generat-
ed by the SPDO Direct Digital Synthesizer.
10.4 IEC-958 SERIAL FORMAT
Figure 10-2 show s the se ria l forma t l ayo ut of a IE C-9 58
block. A block starts with a special ‘B’ pre-amble, and
c onsist s of 192 frames . The sampl e-rat e of all embedded
audi o data is eq ual to the frame rate. Each frame con-
si sts of 2 s u b-fr ames . S ub-f ram e 1 a lwa ys s ta rts wit h a
‘M’ pre-amble, except for sub-frame 1 in frame 0, which
starts with a ‘B’. Sub-frame 2 always starts with a ‘W’ pre-
amble.
When IEC-958 data carries 2-channel PCM data, one
audio sample is transmitted in each sub-frame, ‘left’ in
sub-fram e 1 and ‘right’ in sub-fr ame 2. Each s ample can
be 16 or 24 bits in length, where the MSB is always
aligned with bit slot 28 of the sub-frame. In case of more
tha n 2 0 bi ts /s ampl e, the Aux field is used for the 4 LSBs.
Whe n IEC- 958 data carri es non-PCM audio , such as 1 or
mor e stre ams of Dolby AC-3 encod ed data and/or MPEG
audio, each sub-frame carries 16-bit data. The data of
successive frames adds up to a payload data-stream
which carries its ow n burst-data. This is described in [2].
Pr ogr am mers sh ou ld refe r to th e IEC -95 8 do cumen t s [1]
and P rojec t 19 37 docum ent [2] f or a prec ise de sc riptio n
of the required values in each field for different types of
consumer equipment. A complete discussion of this is-
sue is outside the scope of this document.
The SPDO block hardware only concerns itself with gen-
erating B, W and M pr eambles as we ll as generating the
P (pa rit y) bit. All ot her bit s in t he sub-fra me are comp let e-
ly determined by software and copied verbatim from
memory to ou tput, subject only to bit-cell coding .
The prog rammer mu st con st ruct valid IE C-958 blocks by
constructing the right sequence of 32-bit words as de-
scribed in Section 10.7, “IEC -958 Me mory Data For mat.”
10.5 IEC-958 BIT CELL AND PRE-AMBLE
Each data bit in IEC-958 is transmitted using bi-phase
mark encoding. In bi-phase mark encoding, each data b it
is transmit ted as a cell consisting of two consecutive bi-
nary states. The first state of a cell is always inverted
from the second state of the previous cell. The second
state of a ce ll is iden tical to the firs t sta te if the data bit
valu e is a “0”, a nd in ve r te d if the data bit valu e i s a “1”.
Pre-ambles are coded as bi-phase mark violations,
where the first state of a cel l is not the inverse of the last
state of the previous cell.
Th e dura t ion of ea c h state in a cell is ca lled a UI (Unit I n-
terval), so that each cell is 2 UI’s long. In SPDO, the
length of a UI is 1 SPDO clock cycle as determined by
Figure 10 -2. Serial format of a IEC958 block
sub-frame 1Msub-frame 2Wsub-frame 1Bsub-fr ame 2Wsub-frame 1Msub-frame 2W
Start of block (indicated by unique B pre-amble)
sub-frame sub-frame
frame 0 frame 1
sub-framM
frame 191
031282420161284
Sample data
L
S
B
M
S
B
B, W or M
pre-amble Aux. VUCP
Validity flag
User data
Channel status
Parity bit
sub-frame (2 channel PCM)
031282420161284
16-bit data
L
S
B
M
S
B
B, W or M
pre-amble VUCP
Validity flag
User data
Channel status
Parity bit
sub-frame (n on-PCM audio )
unused (0)
Philips Semiconductors SPDIF Out
PRELIMINARY SPECIFICATION 10-3
the settings of the DDS (see Section 10.8, “Sample Rate
Programming”).
Figure 10-3 illustrates the transmission format of 8-bit
dat a va lue “10011000”, as well as the tran smission for-
mat of the 3 pre-ambles. Note that each pre-amble al-
ways starts with a rising edge. This is made possible
thanks to the presence of the parity bit, which always
guaran te es an even number of ‘1’ bits in each sub-frame.
10.6 IEC-958 PARITY
The par ity bit, or P bit in Figure 10-2, is computed by the
SP DO ha rd ware . T he P bit valu e shou ld be se t such that
bit ce lls 4 to 31 inc l us iv e co ntai n an e v en num ber of ‘1’s
(and hence even number of ‘0’s). The P bit is bi-phase
mark encoded using the same method as for all other
bits.
10.7 IEC-958 MEMORY DATA FORMAT
The DSPCPU software must prepare a memory data
structure tha t inst ructs th e SPDO hardware to gen erate
correct IEC-958 blocks. This data structure consists of
32-bit words with the following content:
The data struc ture f or a blo ck con sist s of 384 of thes e 32-
bit descriptor words, one for each subframe of the block,
with the correct B, M, W values. All data content, includ-
ing the U, C and V flag are fully under control of the soft-
ware that builds each block.
A DMA buffer handed to the hardware is required to be a
multiple of 64 bytes in length. It can contain 1 or more
complete blocks, or a block may straddle DMA buffer
boundaries. The 64-byte length will result in DMA buffers
th at contain a multiple o f 16 s ub - frames.
No te that the descriptor structure is a 32-bit wo rd memo-
ry data structure, and is hence subject t o processor en-
dian-ness. To allow software to be efficient in both little-
endian and big-endian operation, the SPDO block
SPDO_CTL register has an endian-ness bit
‘LITTLE_ENDIAN’. The SPDO block performs byte
swapping when loading the SPDIF descriptors as fol-
lows.
•If LITTLE_ENDIAN = 1, 32-bit words at address ‘a’
will be assembled from bytes (a+3,a+2,a+1,a), with
th e byte at ‘a+3’ co ntaining the MSB’s and the byte at
‘a’ the LSB’s.
•If LITTLE_ENDIAN = 0, 32-bit words at address ‘a’
will be assembled from bytes (a,a+1,a+2,a+3), with
the byte at ‘a’ con taining the MSB’s and the byte at
‘a+3’ th e LSB’s.
10.8 SAMPLE RATE PROGRAMMING
In he SPDO unit, the frame rate always equals fs, the
sam ple rate of embedded au dio. This relation holds for
PCM as well as for Dolby AC-3 and MPEG encoded au-
dio. Each frame consists of 128 Unit Intervals (UI’s). Th e
length of a UI is determined by the frequency setting of
the DDS (Direct Digital Synthesizer) in the SPDO block.
The DDS can be programmed to emit frequencies from
appr o x . 1 Hz t o 8 0 MH z i n s te ps of ap pr ox . 0 .3 Hz, wit h
a ji tte r of appr ox. 750 pse c (at DSPC PU f reque ncy of 143
MH z, se e equa t i on s be low ).
Programming is accomplished through the FREQUEN-
CY MMIO register: the relation between FREQUENCY
re gister val ue, DSP CPU clo ck val ue an d synthe size d fre-
quency is:
Putting equation 1 and 2 above together yields the for-
mula for setting FREQUENCY to accomplish a given
sample rate:
The DDS synthesizer maximum jitter can be computed
as follow s :
Ta ble 10-2. SPDIF sub-frame descript or word
bits definition
31 (MSB) this bit must be a ‘0’ for future compatibility
30..4 Data value f or bits 4..30 of the subframe, exactly
as they are to b e transm itted. Har dware will per-
form the bi-phase mark encoding and parity gen-
eration.
3..0
(LSB) 0000 - generate a B preamble
0001 - generate a M preamb le
0010 - generate a W preamble
0011 .. 1111 reserved for future
Figure 10 -3. Bi-p ha se m ark da ta transmissio n
“1” “0” “0” “1” “1” “0” “0” “0”
UI
cell
bi-phase mark violation
B
bi-phase mark violation
M
bi-phase mark violation
W
fs
fDDS
()
128
----------------= Eq. 1
FREQUENCY 231 fDDS 232
⋅
9fDSPCPU
⋅
-----------------------------+= Eq. 2
FREQUENCY 231 fs239
⋅
9fDSPCPU
⋅
-----------------------------+=
PNX1300/01/ 02/11 Data Book Philips Semiconductors
10-4 PRELIMINARY SPECIFICATION
Table 10-3 s hows settings fo r common sample rat e and
DSPCPU cl ock combinations:
The programmer is free to change FREQUENCY, and
hence the system sample rate to perform long-term
tracking of any absolute timing source and/or control
software buffer fullness. Changes to the FREQUENCY
register pull-in or delay the next clock edge and have no
instantaneous effect on clock level, i.e. the rate of phase
progression is changed, not the phase.
10.9 TRANSPARENT MODE
When SPDO is set to operate in transparent mode, it
takes all 32 bits of the memory data and shifts them out
verbatim, without bi-phase mark encoding, parity gener-
at ion , or pr e am bl e.
Two transparent modes are provided, as determined by
TRANS_MODE in SPDO_CTL: LSB first and MSB first.
One bit of memory data is transmitted for each DDS
clock, such that the FREQUENCY register value for a
desired bit rate is given by the following equation:
The 32-bit memory word is constructed according to the
same rules for LITTLE_ENDIAN as in Section 10.7,
“IEC-958 Memory Data Format.”
10.10 DMA OPERATION
Before enabling the SPDO block, software must assign
two bu ffe rs w ith data to SPDO _ BASE1 , SP DO _BA SE2 ,
and SPDO_SIZE (buffer size in bytes). Each memory
buf fer s ize mu st be a mul tip le of 64 byte s r egard le ss o f
the operating mode.
The SPDO block is enabled by writing a ‘1’ to
SPDO_CTL.TRANS_ENABLE. Once enabled, the first
DMA buffer is sent out at the programmed sample rate.
On ce th e fir st bu ffe r is em pty, BUF 1_ACTIV E is nega ted,
a timestamp is generated (see Section 10.13, “Times-
tamps”) and the B UF1 _EM PTY flag in S PDO _STA TUS
is asserted. If BUF1_INTEN in SPDO_CTL is also as-
serted, an interrupt to the DSPCPU is generated. The
SPDO block continues emitting the data in DMA buffer 2.
In normal operation, the DSPCPU a ssigns a new buffer
1 full of data to SPDO and signals this by writing a ‘1’ to
ACK_BUF1. The SPDO bl ock immedi ately negates the
BUF1_EMPTY condition and the related interrupt re-
ques t. Once b uffer 2 is e mpty, sim ilar signaling occurs
and the hard ware s witche s ba c k to using b u f fer 1.
10.11 DMA ERROR CONDITIONS
Two types of error can occur during DMA operation.
If the software fails to provide a new buffer of data in
time, and both DMA buffers empty out, the SPDO hard-
ware raises the UNDERRUN flag in SPDO_STATUS.
Transmission switches over to the use of the next buffer,
but the data transmitted is incorrect. If UDR_INTEN is
asserted, an interrupt will be generated. The UNDER-
RUN flag is sticky, i.e. it will remain asserted until the
software clears it by writing a ‘1’ to ACK_UDR.
A lo wer level error can also occur when the limited size
internal buffer empties out before it can be refilled across
the hig hway. T his si tuation can arise only if insu fficient
bandw idth ha s be en r e ques t e d fr om the hig hw ay . In t h is
case, the HBE error flag is raised. Refer to Secti on 10 .17,
“HBE and Highway Latency” for a description of how to
s et th e arbiter latenc y correctly .
10.12 INTERRUPTS
The SPDO block uses interrupt SRC NUM 25, with inter-
rupt vector MMIO off s et 0x1008E4.
It is highly recommended that the interrupt be operated
in lev el-sens itive mo de onl y.
Th e SP DO bl oc k g en er a tes an i nt e rr u pt if o ne of the fo l-
lowing status bit flags, and its corresponding INTEN_xxx
flag are set: BUF1_EMPTY, BUF2_EMPTY, HBE, UN-
DERRUN.
All t hes e status flags ar e s ticky, i. e. the y are asserted by
hardware when a certain condition occurs, and remain
set until the interrupt handler explicitly clears them by
writing a ‘1’ to the corresponding ACK bit in SPDO_CTL.
The SPDO hardware takes the flag away in the clock cy-
cl e after t he ACK is r ece ived . T his all ows imm edi ate r e-
turn from interrupt once performing an ACK.
10.13 TIMESTAMPS
Any outgoing DMA buffer is assigned a 32-bit ‘time of de-
parture’ tim esta mp. The coun te r use d to ge ne rat e t imes-
ta mps uses t he D S P C P U cl oc k and t he s ame r eset time
as the DSPCPU CCCOUNT register, resulting in a value
that corresponds to the 32 LSB’s of CCCOUNT - provid-
ed that PCSW.CS=1, i.e. t he real CCCOUNT counter in-
cr ements o n every clock cycle .
Ta ble 10-3 . SPD IF sa mple rate setting
fs
(kHz) fDSPCPU
(MHz) FREQUENCY
(hexadecimal) UI
(nSec) jitter
(nSec)
32.000 143 0x80D0,9316 244.14 0.777
32.000 166 0x80B3,ACF8 244.14 0.669
32.000 180 0x80A5,B36E 244.14 0.617
44.100 143 0x811F,711B 177.15 0.777
44.100 166 0x80F7,9D93 177.15 0.669
44.100 180 0x80E4,5B47 177.15 0.617
48.000 143 0x8138,DCA1 162.76 0.777
48.000 166 0x810D,8375 162.76 0.669
48.000 180 0x80F8,8D25 162.76 0.617
jitter 1
9fDSPCPU
⋅
-----------------------------=
FREQUENCY 231 232 bitrate⋅
9fDSPCPU
⋅
------------------------------+= Eq. 2
Philips Semiconductors SPDIF Out
PRELIMINARY SPECIFICATION 10-5
The timestamp can be read in the DMA interrupt handler
as MMIO register SPDO_TSTAMP. Its contents corre-
sponds to the (sync hro nized) cloc k edge at whi ch th e last
bi t in t he D MA b uff er w as s ent a cro ss t he ou tp ut sign al
pin.
1 0.1 4 MM IO REGI ST ER DESC RI PTI O N
Fi gu r e 10 -4. S P DO un it st a tus / co nt ro l fi e ld MMIO layout.
MMIO_base
offset:
SPD O_S T A TUS ( r /0x10 4C00
SPDO_CTL (r/w)0x10 4C04
SPDO_FREQ (r/w)0x10 4C08
SPD O_ BA SE1 (r /w)0x10 4C0C
FREQUENCY
BUF1_ACTIVE
SPD O_ BA SE2 (r /w)0x10 4C10 BASE2
SPDO_SIZE (r/w)0x10 4C14 SIZE (in bytes)
31 0371115192327
BASE1
UNDERRUN
HBE (Highway bandwidth er ror)
BUF2_EMPTY
RESET
TRANS_ENABLE
TRANS_MODE
LITTLE_ENDIAN
0
UDR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_UDR
ACK_HBE
ACK_BUF2
ACK_BUF1
00000
000000
SLEEPLESS
BUF1_EMPTY
000000
31 0371115192327
31 0371115192327
SPDO_TSTAMP (r/o)0x10 4C18 TIMESTAMP
Tabl e 1 0 -4. SPDO_ STATUS MM IO regis ter
field type description
BUF1_EMPTY
r/o
Sticky flag - set if DMA buffer 1 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF1.
BUF2_EMPTY
r/o
Sticky flag - set if DMA buffer 2 emp-
tied by the S PDO hardwar e. Can only
be cleared by software write to
ACK_BUF2.
HBE
r/o
Highway Bandwidth Error . Stic ky flag -
set if internal SPDO buffers emptied
before new data brought from memory.
Refer to Section 10.17, “HBE and
Highway Latency.” Can be cleared
only by a software write to ACK_HBE.
UNDERRUN
r/o
Sticky flag - set if both DMA buffers
were emptied before a new full buffer
was assigned by the DSPCP U. The
har dwa re h as per for m ed a normal
buffer switch over and is emi tting old
data. Can only be cleared by software
write to ACK _UDR.
BUF1_ACTIVE r/o Flag - set if the hardware is currently
emitting DMA buffe r 1 data; negated
when emitting DMA buffer 2 data.
Ta ble 10-5. SPDO _ CTL MMIO registe r
field type description
ACK_BUF1
w/o
Always reads as ‘0’. Write a ‘1’ her e
to clear BUF1_EM PTY. This
informs SPDO that DMA buffer 1 is
now full. Writing a ‘0’ has no effect.
ACK_BUF2
w/o
Always reads as ‘0’. Write a ‘1’ her e
to clear BUF2_EM PTY. This
informs SPDO that DMA buffer 2 is
now full. Writing a ‘0’ has no effect.
ACH_HBE w/o Always reads as ‘0’. Writing a ‘1’
here clear s HBE.
ACK_UDR w/o Always reads as ‘0’. Writing a ‘1’
here clears UNDERRUN .
BUF1_INTEN r/w If BUF1_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asser t ed .
Ta ble 10-4. SPDO_STATUS MM IO regis ter
field type description
PNX1300/01/ 02/11 Data Book Philips Semiconductors
10-6 PRELIMINARY SPECIFICATION
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when r ead, an d wri t-
ten as ’0’s.
The SPDO_FREQ register determines the frequency of
operation of the DDS, and hence the sample rate of out-
goin g audio. Refe r to Section 10.8, “Sample Rate Pro-
gramming.” and Sec tion 10 . 9 , “Tr ansp ar e nt M ode.”
SPDO_BASE1 contains the memory address of DMA
buffer 1. SPDO_BASE2 contains the memory address of
DMA buffer 2. SPDO_SIZE determines the size, in bytes,
of both DMA buffers. Assignment to SPDO_BASE1,
SPDO_BASE2 and SPDO_SIZE have no effect on the
state of the SPDO_STATUS flags; the ACK_BUF1 and
ACK_BUF2 bits signal the assignment of valid data to
the DMA buffers. Any change to the BASE register
should only be done to an inactive buffer and should pre-
cede the ACK to that bu ffe r.
SPDO_TSTAMP is a read-only register containing the
cycle count at which the last bit from the last emptied
buffer was transmitted across the output pin. Refer to
Secti on 10.13, “Timestamps.”
10.15 RESET
The SPDO block is reset by global PNX1300 reset pin
TRI_RESET# or by writing a ‘1’ to the RESET bit in
SPDO_CTL. The SPDO block is not affected by
DSPCPU reset initiated though the PCI block BIU_CTL
register. Either reset method sets the SPDO block in the
following state:
•SPDO_ BASE 1, SPDO_ BASE 2, SPDO_ S IZE = 0
•SPDO_STATUS: all defined fields set to ’0’, except
BUF1_ACTIVE = 1
•SPD O _CT L all de f in ed fields set t o value 0
The SPDO block timestamp counter is reset by
TRI_RESET# or by DSPCPU reset initiated through
BIU_CTL, so as to ensure that it stays synchronous to
the CCCOUNT DSPCPU register.
10.16 POWER DOWN AND SLEEPLESS
The SPDO block enters powerdown state whenever
PN X13 00 i s p ut in gl ob al po wer dow n m ode , excep t i f the
SLEEPL ESS bit in SPDO _CT L is s et. In t he latter ca s e,
the block continues DMA operation and will wake up the
DSP CPU whenever an interrupt is generated.
SPD O ca n be sepa r at ely p owere d d ow n b y s e t t ing a b it
in the B LOCK_POWER_DOWN register . For a descrip-
tion of powerdown, see Chapter 21, “Power Manage-
ment.”
The SPDO block should not be active when applying glo-
bal powerdown (TRANS_ENABLE = 0), or if active,
SLEEPLESS should be asserted. SPDO should not be
act i ve if pow ered do wn sepa rately.
If th e bloc k ent ers po wer -do wn st ate w hile tra ns mis sion
is enabled, its operation continues from the interrupted
clock cycle, but the output signal generated by the block
has undergone a pause that is unacceptab le to external
equipment.
10.17 HBE AND HIGHWAY LATENCY
The SPDO unit uses one inter nal 64 -byte buffer and t w o
32-bit holding registers. Under normal operation, the in-
ternal buffer is refilled from SDRAM fast enough to avoid
missing any data, while data is being sent from the two
32-bit registers. If the highway arbiter is set u p wi th an in-
sufficient latency guarantee, the situation can arise in
which the 64-byte buffer is not refilled in time. In that case
the HBE error is raised, and some data has been irrevo-
ca bly lo st . T he HBE co ndit io n is st ic ky, an d ca n onl y be
c leared by an explicit ACK_HBE.
BUF2_INTEN r/w If BUF2_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asser t ed .
HBE_INTEN r/w If HBE asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
UDR_INTEN r/w If UNDERR UN asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
SLEEPLESS
r/w
If ‘1’, the SPDO block does not
power down when PNX1 300 go es
into global power-down mode. If ‘0’,
the block does power down.
LITTLE_ENDIAN
r/w
If asserted, the 32-bit data SPDIF
desc ript or word or tr ans parent
mode data word is as sembled
using little endian byte ordering,
otherwise big-endian.
TRANS_MODE
r/w
•000 - IEC-958 mode. Hardware
performs bi-phase mark encod-
ing, pr eamble g eneration, and
parity generation, and transmits
one IEC-958 subframe for each
data descriptor word.
•010 transparent mode, LSB first.
The 32-bit data descriptor words
are transmitted as is, LSB first.
•011 transparent mode, MSB
first. The 32-bit data descriptor
words are transmitted as i s,
MSB firs t.
•Any other code reserved for
future extensions.
The transmission mode should only
be changed wh il e tran smissi on is
disabled.
TRANS_ENABLE
r/w
Writing a ‘1’ to this bit e nables
transmission per the selected
mode. Wri ting a ‘0’ here stops any
ongoing transmission after com-
pleting any actions related to the
current data descriptor word.
RESET
w/o
Writing a ‘1’ to thi s bit resets the
SPDO unit and s hould be used with
extreme caution. Ongoing trans-
mission will be interrupted, receiv-
ers may be left in a strange state.
Tabl e 1 0 -5. SPDO _ CTL MMIO regi ster
field type description
Philips Semiconductors SPDIF Out
PRELIMINARY SPECIFICATION 10-7
The highway arbiter needs to be programmed such that
the SPDO unit’s latency requirement can always be met.
Refer to Chapter 20, “Arbiter” for details. The required la-
te nc y ca n be c om puted as in di cated be low.
Given an output data rate fs in samples/sec, 2x 32 bits
are required each sample interval. The arbiter should be
s et to hav e a l ate ncy so that th e buf fer is re f i lled be for e a
sample interval expires. See Table 10-6 for example
practical set tings.
10.18 LITERATURE REFERENCES
[1] IEC-958 Digital Audio Interface, Part 1: General; Part
2: Professional applications; Part 3: Consumer applica-
tions.
[2] ‘Int erf ac e for no n-P CM e nc ode d Au di o b its tr ea ms ap-
plying IEC958’, Philips Consumer Electronics, June 6
1997. IEC 100c/WG11(project 1937)
Table 10-6. SPDO block highway latency
requirements
fs
(kHz) Max. latency
(nSec)
32.000 31250
44.100 22675
48.000 20833
PNX1300/01/ 02/11 Data Book Philips Semiconductors
10-8 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 11-1
PCI Interface Chapter 11
by Gert Slavenburg, Ken-Sue Tan, Babu Kandimalla
11.1 PCI OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 includes a PCI interface for easy integration
into personal computer applications—whe re t h e PCI- bu s
is the stan dar d for high- s peed per ip her a ls. In e m bedd ed
applications, with PNX1300 serving as the main CPU,
the PCI bus can interface to peripheral devices that im-
plem en t func tion s n ot prov ided by the on- chip peri ph er-
al s. See Figure 11-1.
The main function of t he PCI interface is to connect the
PNX1 300 on-chip highway and PCI buses. A bus cycle
on the internal highway that targets an address mapped
into PCI space will cause the P CI interfa ce t o create a
PCI bus cycle. Similar ly, a bus cyc le on PCI that targets
an address mapped into PNX1300 memory space will
cause the PCI interface to create a highway bus cycle
targeted at SDRAM. For some operations, the PCI inter-
face is explicitly programmed by the DSPCPU.
Fr om PNX1 30 0, o nl y the DSP CPU an d t he i mag e cop ro-
ces sor (I CP) un it ca n caus e th e PCI inter face to crea te
PCI bus cycles; the other on -chip peripherals cannot see
external hardware through the PCI interface. From PCI,
SDRAM and most of the registers in MMIO space can be
accessed by external PCI initiators.
The PCI i nterface implemen ts DMA (als o ca lled bloc k or
bur st) an d non-D MA tr an sfer s. DM A tra nsf ers are inte r-
ruptible on 64-byte boundaries. The PCI interface can
service outbound (PNX1300 → PCI) and inbound (PCI
→ PN X13 00) data flows simultaneously.
Table 11-1 lists so me of the featu res of the PC I int erf ace.
PNX1300 DMA read transactions use an efficient ‘mem-
ory read multip le’ PCI transaction s , unless explicitly dis-
abled. Section 11.6.5.
PNX1300 contains an on-board PCI_CLK generator for
low-cost configurations. It can be enabled/disabled at
bo ot time . See Section 13.1 on pag e13-1.
PNX1300 has a sideband control signal that allows glue-
less connection of simple slave peripherals directly to the
PCI bus wires. This can be used to conne ct Flash, ROM,
SRAM, UARTs, etc. with 8-bit data and demultiplexed
addresses. Refer to Chapter 22, “PCI-XIO External I/O
Bus.”
PCI Agent PCI Agent PCI Agent
PNX1300 PCI Bus
Arbiter
Host CPU
(e.g., x86)
Interrupt
Controller
PCI Agent PCI Agent PCI Agent
PNX1300 PCI Bus
Arbiter
a) PNX1300 as peripheral b) PNX1300 as host CPU
PCI Bus PCI Bus
PCI Bridge
Fi gu re 11- 1. T wo typ i cal sy st e m imp le ment a tio n s: (a) sh ows PNX 1300 as a PC I pe riphe r al in a deskt op PC, (b )
sh ow s an em be d d ed syst e m w it h P N X130 0 a s t he host CP U .
Table 11-1. PCI interface characteristics
Characteristic Comments
PCI Compliance PCI Local Bus Specification Rev. 2.1
PCI Speed Up to 33 MHz
Data b us width 32-bit only
Address space 32 bits (4 GB)
Voltage levels Drive & receive at either 3.3 V or 5V
Burst mode Yes, w/ double buffering so maxi-
mum transf er rate (132 MB/sec) is
sustainable
Posted write Yes, can be disabled
PCI ‘special cycle’Not recognized
PCI ‘memory write &
invalidate’Supported for PNX1300 as initiator
PCI ‘interrupt acknowl-
edge’Not generated
PCI ‘dual-address
cycle’Not generated
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-2 PRELIMINARY SPECIFICATION
11.2 PCI INTERFACE AS AN INITIATOR
The following classes of operations invoked by PNX1300
cause the PCI interface to act as a PCI initiator:
•Transparent, single-word (or smaller) transactions
caused by DSPCPU loads and stores to the PCI
addr e s s apertur e
•Explicitly programmed single-word I/O or configura-
tio n read or wri te tr an sa c t io ns
•Explicitly programmed multi-word DMA transactions.
•ICP DMA
11.2.1 DSPCPU Single-Word Loads/Stores
From the point of view of programs executed by
PNX1300’s DSPCPU, there are three apertures into
PNX1300’s 4-GB me mory address space:
•SDR A M sp ace (0. 5 t o 64 MB; pr ogramm able)
•MMIO space (2 MB)
•PCI space
MMIO registers control the positions of the address-
space apertures (see Chapter 3, “DSPCPU Architec-
ture”). The SDRAM ape rture beg ins at the address sp ec-
ified in the MMIO register DRAM_BASE and extends up-
wa rd to the ad dres s in the D RAM _LIMI T regi st er. The 2-
MB MMIO aperture begins at the address in
MMIO_BASE ( default s to 0xEFE00000 after power-up).
All addresses that fall outside these two apertures are
ass umed t o be part of the PC I addre ss ap ertu re . Re fer -
ences by DSPCPU loads and stores to the PCI aperture
are reflected to external PCI devices by the coordinat ed
act i on of t h e da ta ca che an d P CI in t erf a c e.
When a DSPCPU load or store targets the PCI aperture
(i.e., neither of the other two apertures), the DSPCPU’s
da ta ca che au t o matically carr ie s out a sp ecia l sequence
of events. The data cache writes to the PCI_ADR and (if
the DSPCPU operation was a store) PCI_DATA regis-
ter s in t he PCI interf ace and as ser ts (l oad) or de-asserts
(store) the internal signal pci_read_operation (a direct
conn e cti on from th e da ta ca c he to th e PC I inte rfa c e) .
While the PCI interface executes the PCI bus transac-
tion, the DSPCPU is held in the stall state by the data
cache. When the PCI interface has completed the trans-
action, it asserts the internal signal pci_ready (a direct
c onnection from the PCI interface to the da ta cach e ).
When pci_ready is asserted, the data cache finishes the
original DSPCPU operation by reading data from the
PCI_DATA register (if the DSPCPU operation was a
load) and releasing the DSPCPU from the stall state.
Explicit Writes to PCI_ADR, PCI_DATA
The PCI_ADR and PCI_DATA registers are intended to
be used only by the data cache. Explicit writes are not al-
lowed and may cause undetermined results and/or data
corruption.
11.2.2 I/O Operations
Explicit programming by DSPCPU software is the only
way to perform transactions to PCI I/O space. DSPCPU
software writes three MMIO registers in the following se-
quence:
1. The IO_ADR register .
2. Th e IO _DATA r eg is t er (if PC I oper at io n is a wr i te) .
3. The IO_CTL register (controls direction of data move-
ment and which bytes participate).
The PCI interface starts the PCI-bus I/O transaction
wh en sof twa re wr it es to IO _CT L. The in t erf ac e can ra ise
a DSPCPU interrupt at the completion of the I/O transac-
tion (see BIU_ CTL regist er defin ition in Section 11.6.5,
“BIU_CTL Register”) or the DSPCPU can poll the appro-
pri ate s tat us b it (see BIU _ST ATUS reg ister defin iti on in
Section 11.6.4, “BIU_STATUS Register”). Note that PCI
I/O transactions should NOT be initiated if a PCI config-
ura tion tr an sac tion d es cribed be low is pe nding. T his is a
strict implementation limitation.
The fully detailed description of the steps needed can be
found in Sec ti on 11 .6 .1 3, “IO_CTL Register.”
11.2.3 Configuration Operations
As with I/O operations, explicit programming by
DSPCPU software is the only way to perform transac-
tions to PCI configuration space. DSPCPU software
writes three MMIO registers in the following sequence:
1. The CONFIG_ADR register .
2. The CO N FIG_DATA re gister (i f PCI operation is a
write).
3. The CONF IG_ CT L r egi st er ( c on tro ls dir ec tio n o f data
movement and which bytes pa rticipate).
The PCI inter f ac e star ts th e PCI -bu s co nf igur a tion tr ans-
action when software writes to CONFIG_CTL. As with
the I/O op erati ons, the biu _sta tus a nd BIU_C TL reg iste rs
monitor the status of the operatio n and control interrupt
signaling. Note that PCI configuration space transactions
should NOT be initiated if a PCI I/O transaction de-
s cribed above is pendi ng. This is a st r ict im plemen tation
limitation.
The fully detailed description of the steps needed can be
found in Sec ti on 11 .6 .1 0, “CONFIG_CTL Re gister.”
11.2.4 DMA Operations
The PCI interface can operate as an autonomous DMA
engine, executing block-transfer operations at maximum
PC I band wid t h. As wi th I / O an d con fig ur a tion oper a tio ns,
DSPCPU soft ware explicitly programs DMA operations.
General-purpose DMA
For DMA between SDRAM and PCI, DSPCPU s oftware
writes three MMIO registers in the following sequence:
1. The SRC_ADR and DEST_A DR reg ister s.
2. The DM A_CT L register (controls directio n of data
movement and am ount of data transferred).
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-3
The PCI i nterface begins t he PCI-bus t r ansact ions whe n
software writes to DMA_CTL. As with the I/O and config-
ura tion oper a t i ons, the B IU _STA TU S and B IU _CT L reg-
isters monitor the stat us of the opera tion and control in-
terrupt signaling.
The fully detailed description of the steps needed to start
a DMA transaction can be found in Section 11.6.16,
“DMA_CTL Register.”
Image-Coprocessor DMA
The PCI interface also executes DMA transactions for
the Image Coprocessor (ICP). The ICP performs rapid
post- proc es si ng of imag e data a nd w rit es it at PCI DM A
s peed t o a P CI gra ph ic s car d fr am e bu ffe r. Th e I CP ca n-
not perform PCI read transactions. BIU_CTL.IE (ICP
DMA E nable) should be asserted before attempting ICP
PC I operation. Programming of ICP DMA is described in
Secti on 14.6, “Operation and Programming.”
1 1.3 P C I I NT ERF AC E AS A TA RG E T
Th e PN X1300 P C I inte rfac e resp onds a s a t arg et to ex-
ter nal ini tia to rs for a limi ted set of PC I tran sa ct io n typ es :
•Configuration read/write
•Memory read/write, read line, and read multiple to
th e PN X1300 S DR AM or MM IO ap er tu res. Se e Sec-
tion 11 .8 , “Limitations.”
PNX1300 ignores PCI transactions other than the above.
11.4 TRANSACTION CONCURRENCY,
PRIORITIES, AND ORDERING
The PCI interface can be processing more than one op-
eration a t a given tim e. There are five distinc t classe s of
oper a tion s im pl em ented by th e P CI inter fa c e:
1. DSPCPU load/store to PCI space.
2. PCI I/O read/write and PCI configuration read/write.
3. G en er al - pu rp os e D MA re ad/w rit e.
4. ICP DMA write.
5. Externa l- P CI- ag ent- i nitiated r e ad/w rite ( t o PN X 13 00
on-chip re s ource).
If the ac t iv e ge ner al -purp os e D MA tran saction is a read,
up to five transactions, one f rom each, can be active si-
multaneously. If the active general-purpose DMA opera-
tion is a write, then only four transactions can be active
simultaneously because general-purpose DMA writes
force ICP DMA writes to wait until the general-purpose
DM A com ple t es . When a general-purpose DMA write is
pending, an in-progress ICP DMA operation is suspend-
ed at the next 64-byte block boundary and waits until the
c omple t io n o f th e DM A wr i t e ope r atio n. Gene r al- pu rpos e
DMA reads are interleaved with ICP DMA writes, so both
can be active concurrently.
PCI single-data-phase transactions (DSPCPU load/
store, I/O read/write, and configuration read/write) are
executed in the order they are issued to the PCI inter-
face . Note th e stric t imple men tation limita tion th at PC I -
I/O and PCI configuration transactions cannot be simul-
ta ne ou sly ac t iv e .
11.5 REGISTERS ADDRESSED IN PCI
CONFIGURATION SPACE
Sin ce it is a P CI de vice , PN X130 0 ha s a set o f c onfi gu-
rat ion registers to determin e PCI behavior. PCI configu-
ration registers allow full relocation of interrupt binding
and address mapping by the system’s host processor.
This relocatability of PCI-space parameters eases instal-
lation, configuration, and system boot.
Th e PCI st anda rd sp ecif ies a 64 -byte PC I con figu rati on
head er region wi thin a reserved 256-byte blo ck. Duri ng
s ystem initialization, host system software scans the PCI
bus, looking for PCI headers, to determine what PCI de-
vices are present in the system. The fields in the header
re gion uniquel y ide nti fy the P CI de vice a nd allo w the h ost
to co ntrol th e devic e in a generic way. Figure 11-2 sho ws
the layout of the c onfiguration header region.
Figure 11-2 also shows the initial values for the configu-
ra tion regi sters . Some r egis ters, such as Device ID, have
har dwir e d va lu es, wh ile oth er s are progr a m me d b y s oft-
ware. Still others are set automatically from the external
boot R O M du rin g PNX1 30 0 ’s po wer -u p in itial iz ati on .
11.5.1 Vendor ID Register
For PNX1300, the value of the 16-bit Vendor ID field is
hardwired to 0x1131 (Philips). This value identifies the
manufacturer of a PCI device. Valid vendor identifiers
ar e as si gn ed by th e PC I spe cial inter es t group (PCI SI G)
to ensure uniqueness. The value 0xFFFF is reserved
and must be retur ned by the host/PC I bridge when an at-
te mpt is made t o read a non - exis tent d ev ice ’s Ve ndor ID
configuration register.
11.5.2 Device ID Register
For PNX1300, the value of the 16-bit Device ID field is
har dw ired t o 0 x54 02. Th e Devic e ID is assi gned b y the
manufacturer to uniquely identify each PCI device it
makes.
11.5.3 Command Register
The 16-bit command register provides basic control over
a PCI d ev i ce ’s ability to generate and/or respond to PCI
bus cycle s. According to the PCI s pecific ation, after re-
set , al l bits in t h is re gi ster are clear e d to ‘0’ (exc e pt for a
dev ic e th at mu st be in itially en ab le d) . Clea r in g al l bi ts t o
’0’ logic ally d isc on nect s the de vi ce from th e PCI bu s for
all acces s es except configuration accesses.
The command register format is shown in Figure 11-3.
Table 11-2 summarizes the field values. Note that the
valu es li sted as ‘normally taken’ are not necessarily the
re set values , i.e. th e Comma nd regi ster is res et to al l ‘0’s,
meaning the features are disconnected on reset.
Following are detailed descriptions of the command reg-
ister fields.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-4 PRELIMINARY SPECIFICATION
I/O (I/O access enable). This bit controls a device’s abi l-
ity to resp ond to I/O-s pace ac cesses . A v alu e of ’0’ dis-
ables PCI device response; a value of ’1’enables re-
sponse. This bit is hardwired to ’0’ because all PNX1 300
int ernal re gister s a r e mem or y m apped.
MA (Memory access enable). This bit controls re-
sponse to memory-space accesses. A value of ’0’ dis-
ables PNX1300 response; a value of ’1’ enables re-
sponse. This bit is set to ’0’ at powe r-up; softw are can set
this bi t t o ’1’ with a configuration write.
31
00
0Normally ’0’0 Hardwired to ground sp Set by software if aperture size allows p Set by software
1Normally one 1 Hardwired to Vdd s Set by hardware from boot EEPRO M
015
Device ID (0x5402) Vendor ID (0x1131)
004
01 000 reserved reserved 11 11
Status Command
0000 0
008
10 100 010000010
Class Code (0x04800 0) Revision ID (see text)
0000 0 0 00000000000
00C
00 000 0
BIST (0x00) Latency Timer
0000 0 0 0000pppp00p
Header Type (0x00) Cache Line Size
p10
spspspspsp0
DRAM Base Addres s
pppp spsp000000000000000000
p14
pp ppp 0
MMIO Base Addr ess
pppp p 00000000000000000000
18, 1C,
20, 24
28
30
34, 38
3C
000 1 Interrupt Line
001100000000p
2C
s sssssssssssssss
ppppppp
Interrupt Pin (0x01)Min_Gnt (0x03)Max_Lat (0x01)
0000 0010
723
01010100000000100001000100110001
00p000
Configuration-Space Address Offset
000 000 000000000
Four other base address registers
0000 0 0 00000000000
000 000 00000 0 0 000000
Reserved register
0
Expansion Rom Base Address
00000000000000000000
0
Two reser ved register s
00000000000000000000
0000000000000
0000000000 0
0000000000 0
0
ssssssssssssssss
Subs ystem ID S ubsys tem Vendo r ID
00ppp00
Key
s
Prefetchable
Figure 11-2. PCI configuration header region register layout and initial values. (All values in hex.)
15 0
Comm and Regist er I/O
1
MA
2
EM
3
SC
4
MWI
5
VGA
6
PAR
7
Wait
8
SERR#
9
FB
10
Reserved
Figur e 11-3 . Comm an d Regis t er form at.
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-5
EM (E nable m ast eri ng) . This bit controls the PNX1300
PCI interface’s ability to act as a PCI master. A value of
’0’ prevent s the PCI interface from initiating PCI access-
es; a valu e of ’1’ a llo ws the P CI inte rfac e to in itia te PC I
accesses.
Not e t h at t he EM bi t is au to mat i ca lly set to ’1’ w henever
the HE bit in the BIU_CTL register is set to ’1’ (see Sec-
tion 11.6.5, “BIU_CTL Register”). M a ster ing mu st be en -
abled f or PN X 1 30 0 to ser ve as PC I host pro c e ss o r.
EM is set to ’0’ at power-up. Host syst em software can
set this bit to ’1’ with a configuration write.
SC (Special cycle). This bit controls PCI device recog-
n ition of special- cycle operations. A value of ’0’ causes a
PCI device to ignor e all special cycles; a value of ’1’ al-
lows a PCI device to monitor special cycle operations.
Th is bit i s ha r dw ired to ’0’ in PNX1300.
MWI (Memory write and invalidate). This bit deter-
mine s a PCI device’s ability to generate memory-write-
and-invalidate commands. A value of ’1’ allows a PCI de-
vice to generate memory-write-and-invalidate com-
mands; a value of ’0’ fo r c es the P C I d ev ice t o use mem -
ory-write commands instead. PNX1 300 implement s this
bit. The conditions und er which PNX1300 DMA tra nsac-
tions generate memory-write-and-invalidate are de-
scribed in Section 11.6.16, “DMA_CTL Register.” De-
tai l s of op er ati on can be fou nd in Section 11.5.7, “Cache
Li ne S i ze R egis ter.” Image Coprocessor DMA writes al-
ways use re gular memory-wri te tra nsacti ons.
VGA (VGA palette snoop). T his bi t c ontr ols ho w VGA -
compatible PC I devices handle acc ess es to their pa lette
registers. This bit is hardwired to ’0’.
PAR (Parity error response). This bit controls signaling
of parity errors (data or address). A value of ’0’ causes
the PCI interface to ignore parity errors; a value of ’1’
causes the PCI interface to report parity errors on the
perr# PCI sign al. T his bit is set to ’0’ at po w er-up; s in ce
the PCI in terf ac e c h ecks pari ty , softw are ca n se t thi s bit
to ’1’ wi t h a co nf ig ur a tion w rite.
Wait (Wait-cycle control). This bit controls whether or
not a PC I device does address/data stepping. PCI devic-
es that never do stepping must hardwire this bit to 0.
Since PNX1300 does not implement stepping, this bit is
hardwired to ’0’.
SE RR # (ser r # en able ) . Thi s bi t enab le s the dr i ver of th e
serr# pin (system error): a value of ’0’ d isables it, a value
of ’1’ enables it. Al l PCI device s that have an serr# pin
must implement this bit. This bit is set to ’0’ after reset; it
ca n be set to ’1’ with a conf iguration write. SERR# and
PAR must both be set to ’1’ to al low sig naling of address
par ity err o r s on th e se r r# si gnal.
FB (Fast back-to-back enable). Th is bit con t rol s wh et h-
er or not a PCI master can do fast back-to-back transac-
ti ons to di ffe r ent de vi ce s. A value of ’0’ means fas t back-
to-back transactions are only allowed when the transac-
tions are to the same agent; a value of ’1’ means the
master is allowed to generate fast back-to-back transac-
tions to different agents. Initialization software will set
this bit if all targets are capable of fast back-to-back
transactions. In PNX1300, this bit is hardwired to ’0’.
Reserved. Re ad s fro m re se rved bits retur ns ’0’; writes to
res e r ve d bi ts ca us e no acti on .
11.5.4 Status Register
The status register is used to record information about
PCI bu s even ts. The status register format is sh own in
Figure 11-4. Table 11-3 l ists the S tatus register fie lds.
Reserved. Reads from reserved bits return ’0’; writes to
res e r ve d bi ts ca us e no acti on .
66M (66-MHz capable). This bit is hardwired to ’0’ for
PNX1300 (P CI runs at 33-MHz max imum).
UDF (user-definable features). Since the PNX1300
PCI interface does not implement PCI user-definable
features, t hi s bit i s hardwired to ’0’.
FBC (Fast back-to-backcapable). The PNX1300 PCI
interface does not support fast back-to-back capability,
so this bit is hardwired to ’0’.
DPD (Data parity detected). Since the PNX1300 P CI in-
terface can act as a PCI bus initiator, this bit is imple-
mented. DPD is set in the initiator’s sta tus r e gi ster whe n:
•The PAR (parity-error response) bit in the command
register is set, and
Ta ble 11-2 . Field values for Command Register
Field Value Explanat ion
I/O Hardwired to 0 (ignore I/O space accesses)
MA 0 ⇒ no recognition of memory-space accesses
1 ⇒ recognizes memory-space accesses
EM 0 ⇒ cannot act as PCI initiator
1 ⇒ can act as PCI initiator
SC Hardwired to 0 (ignore special cycle accesses)
MWI 0 ⇒ cannot generate memory write and invalidate
1 ⇒ can generate memory write and invalidate
VGA Hardwired to 0
Par 0 ⇒ ignore parity errors
1 ⇒ acknowledge parity errors
SERR# 0 ⇒ disable driver for serr# pin
1 ⇒ enable driver for serr# pin
FB 0 ⇒ fast back-to-back only to same agent
1 ⇒ fast back-to-back to different agents
Reserved Write ignored; reads return 0
15 0
Status Regist er 45
66M
6
UDF
7
FBC
8
DPD
910 Reserved
14
SSEDPE 13
RMA 12
RTA 11
STA DEVSEL
Figure 11-4 . Status register format.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-6 PRELIMINARY SPECIFICATION
•The initiator assert ed perr# or de tected it asserte d by
the target (during a write cycle).
DEVSEL (Device select timing). This read-only field
defines the slowest timing that will be used for the
devsel# signal when PNX1300 is a target on the PCI bus.
Table 11-4 shows the allowable encodings and mean-
ings. These bits are hardwired to ‘01’ to indicate that
PNX1300 uses a ‘medium’ devsel # t im in g.
STA (Sig naled targe t abort). PNX 13 00’s PCI interface
s ets this bit w hen it is a target device and aborts a trans-
action.
RTA (Receive targ et abo rt). PNX1300’s PC I interface
sets t hi s bit wh e n it is the i nit ia tin g de v ic e an d th e tra ns -
actio n is abo rted by the targ et device. (Al l initi ati ng devic-
es must implement this bit.)
RMA (R ecei v e ma ste r abort) . PNX1300’s PCI interface
sets this bit when it is the initiating device and aborts a
transaction (except when the transaction is a special cy-
cle). (All initiating devices must implement this bit.)
SSE (Signaled system error). PNX1300’s PCI interface
sets this b it w hen it a sse rts th e serr # sign al. (PN X13 00
can generate serr#, so this bit is implemented; devices
incapable of generating serr # need not i mplement SSE.)
DPE (Detected parity erro r). PNX1300’s PCI inte rface
sets this bit when it detects a parity error, even if par ity
error handling is disabled. ( The PAR bit in the command
reg is te r ena bl es th e hand ling of pa r it y err o r s .)
11.5.5 Revision ID Register
The value in the Revision ID register is a read only value
chosen by the manufacturer to indicate product revi-
sions. For the PNX1300 product family, the two MSBs of
the revision ID indicate the fab w here the part w as man-
ufactured. The next tw o bits indicate an all-la yer revision
num ber, an d the 4 LSBs indicate metal layer revisions .
Ea ch all -la yer revis ion ad d s 0x10 to th e revi sion ID and
rese ts the 4 LSBs to ‘0’. Non - p i n or -func t io n co m pa t ib le
Tri Me dia de vic es w i ll use t h e sa m e R ev is io n ID conv en -
tion, but with a revised Device ID.
11.5.6 Class Code Register
The value in the Class Code register is read-only. Sys-
tem softw ar e uses the Class Code regi s ter to ident ify the
generic function of the device, and in some cases, the
Class C o de can speci fy a re gister- lev el pr o gr am ming in -
terface.
Class Code consists of three 1-byte fields as shown in
Figure 11-5. The value of the upper byte, Base Class
Code, broadly classifies the function of the device. The
value of the middle byte, Subclass Code, identifies the
function more specifically. The value of the lower byte
specifies a register-level programming interface so that
device-independent software can interact with the de-
vice. The meanings of the Base Class byte values are
shown in Table 11-6.
The value of Base Class is hardwired to 0x04 since
PNX1300 i s a multimedia device. Currently, there ar e no
specific register-level programming interfaces defined
for multimedia devices.
Table 11-7 lists t he def ined subcl asses of mul ti media d e-
vices. PNX1300 is both a video and audio multimedia de-
vi c e, so its su bclas s va l u e i s ha r dw ir ed t o 0 x80.
Ta ble 11-3. Stat us regis ter f ields
Field Characteristics
Reserved W rit es ignor ed; reads ret urn 0
66M P CI bus speed (h ardwir ed to 0 ⇒ 33-MHz)
UDF User-definab le features (hardwired to 0 ⇒ none)
FBC Fast back-to-back capable (hardwired to 0 ⇒
unsupported)
DPD Data parity detected
DEVS EL devsel# signal timing (hard wired to 1 ⇒ ‘medium’)
STA S ign aled tar get abort
RTA Rec ei ve target abort
RM A R ecei ve master abor t
SSE Signaled system error
DPE Detected parity error
Table 11-4. DEVSEL encodings
DEVSEL Meaning
00 Fast
01 Medium
10 Slow
11 Reserved
Table 11-5. Actual revision ID values
Va lue (hex) Product descr ip tion
0x80 TM-1300 original mask - tm1f-1.0
0x81 TM-1300 1st metal revision - tm1f-1.1
0x82 TM-1300 2nd metal revision - tm1f-1.2
0x83 PNX1300/01/02/11 3nd metal revision - tm1f-
1.3
23 0
Class Code Programming InterfaceBase Class Code 15 7
Subclass Code
Fig ure 11-5. Class-code register format.
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-7
11.5.7 Cache Li ne Size Register
This field only matters when the MWI bit in confi guration
spac e is set. The value of the Cach e Line Size register
specifies the host system cache line size in units of 32-
bi t word s. I ni tiat ing de v ices , s uch as the PNX1 30 0, th a t
can generate memory-write-and-invalidate commands
must implement this register. When implemented, the
cache line size allows initiators participating in the PCI
caching protocol to retry burst accesses at cache-line
boundaries.
This register is implemented in PNX1300. In the
PNX1300, PCI DMA performs write-and-invalidate cy-
cles as per the table below. ICP DMA and CPU PCI
writes are perf ormed using nor m al m e mor y - w ri te cyc le s.
11.5.8 Latency Timer Register
The value of the Latency Timer register specifies the
mini m um numbe r o f PC I cloc k cyc les the PNX1 30 0 B IU
(as initiator) is allowed to own the PCI bus. This register
is readable and wri table in PCI configuration space.
Thi s r e gist e r mus t be writ abl e i n an y PC I-i n it ia tin g d ev ic e
that can burst more than two data phases. In the
PNX1300 PCI interface, the least-significant three bits
are hardwired to ’0’ and soft war e ca n pro gram a ny valu e
into the most-significant five bits. This permits software
to specify the time slice with a minimum granularity of
eight PCI clocks. A value of ’0’ signifies maximum laten-
c y, i.e. 256 PCI cloc ks.
11.5.9 Header Type Register
The value o f the Header Type register defines the format
of words 16 through 63 in configuration space and
whether or not the device contains multiple functions.
Figure 11-6 shows the format of Header Ty pe.
Bit 7 of Header Type is ’0’ for single - func t io n devic es, ’1’
fo r mult i-fu nct ion devi ces . PN X130 0 i s a s in gle-f unc tion
devi ce , s o bit 7 i s ’0’. Table 11-9 sh ows t he encod ings o f
the Layou t field.
11.5.10 Built-In Self Test Register
When implemented, t he BIST r egister is used to control
th e op eration of a d evi ce’s built -i n self test ing capabili t y.
PNX1300 does not implement BIST, so this register is
hardwired to return ’0’s when read.
11.5.11 Base Address Registers
The PNX1300 PCI interface implements two configura-
tion space memory Base Address registers:
DRAM_BASE and MMIO_BASE. DRAM_BASE relo-
cates PNX1300’s SDRAM within the system address
space; MMIO_BASE relocates the 2-MB memory-
mapped I/O address ape rt ure.
Th e v al ue s i n the B a s e Ad dr e ss re gis te r s deter m i ne the
address map as seen by both the DSPCPU and exte rnal
PCI ma sters. T hese val ues are normally s et once, and
no t chan ged dy namicall y on ce the D SP C PU op erates.
Table 11-6. Base Class Encod ings
Base Class
(in hex) Meaning
00 Device was built bef ore class code definitions
were fina lized
01 Mass-storage controller
02 Netw or k co ntr oller
03 Display controller
04 Mul t ime d ia d evic e
05 Memor y cont rol ler
06 Br idge device
07 Simple communications controller
08 Base system peripheral
0A Docking station
0B Processor
0C Serial bus control ler
0D–FE Reserved
FF Device does not fit any of the above classes
Ta ble 11-7 . Subclass & programming interface fields
Subclass
(in hex) Programming
Interface (in hex) Meaning
00 00 Video device
01 00 Audio device
80 00 O t h er m ul t im e d ia device
Table 11-8. Cache line size values
Cache Line Size
(binary) Effect
0000,0100 write-and-invalidates are done in 4-
DW ORD, i.e. 16-byte chunks
0000,1000 wr i te-and- invalidate in 8-DWORD chunks
0001,0000 wr i te-and- i nvalidate in 16-DWO RD chunks
all other values only normal ‘memory-write’ is performed
Table 11-9. Layout encodings
Layout (in hex) Meaning
00 Non-bridge PCI device
01 PCI-to-PCI bridge device
7
Header T ype 0
Layout
6
MF
Figure 11-6. Header type register format.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-8 PRELIMINARY SPECIFICATION
Hardware RESET initializes DRAM_BASE to 0x0 and
MMIO_BASE to 0xefe0,0000, after which the PNX1300
boot pr o t o co l se t s th e fin al v alue.
In s ta ndal one sy ste ms, the au to nomo us bo ot se quen ce
is exec uted . In thi s case, the val ues of DRAM _BA SE an d
MMIO_BASE are copied from the content of the serial
boot EEPROM, as described in Section 13.2.2, “Initial
DSPCPU Program Load for Autonomous Bootstrap.”
In X8 6 or ot her ho st- a ss is ted pl at for ms , the PC I hos t as-
s isted boot sequence is e x ecute d. In this case, the base
re gisters ar e not se t from the E EPROM . Inst ead, the host
BI OS ex ecu t es a sc an for devi ce s o n eac h P CI bus. Dur-
ing this scan, memor y ape r tures needed by each device
are dete rm ined , and a suit able bas e is assi gn ed b y the
host BIOS. Th e details of this process are described be-
low.
Figure 11-7 shows the formats for DRAM_BASE and
MMIO_BASE. Following are descriptions of the register
fields.
M (Memory). The value of the M bit indicates whether
the desired resource is a memory or PC I/O aperture.
The M b it is ha rdwired to ’0’, indicating a me mory type
aperture for both the DRAM_BASE and MMIO_BASE
registers.
T ( T ype) . The value of the T field indicates the size of the
base address register and constraints on its relocatabili-
ty. Table 11-10 li sts th e en codi ngs an d mean in gs o f t he
T field.
PNX1300’s PCI-int erface base registers are 32 bits wide
and c an be rel ocated i n the 32-b it add ress space; thus,
the value of the T field is ‘00’ for both DRAM_BASE and
MMIO_BASE.
P (Prefetchable). The value of the P bit indicates to oth-
er devices whether or not the range is prefetchable.
The P bit in DRAM_BASE reflects the DRAM prefetch-
able attribute as set by the prefetchable bit in the boot
prom (Refer to Table 13-5 on page 13-7 for program-
ming).
MMIO is not prefetchable, so the P bit is hardwired to ’0’
for MMIO_BASE.
Being prefetchable means there are no side effects on
reads, the device retu rns all bytes on reads regardless of
the byte enables, and host bridges can merge processor
writes in t o t h is range w ithout caus ing er ror s.
Note: the setting of the P bit does not change the behav-
ior of the cache or memory interface. It simply signals the
host if the range is a ssume d to be prefet chable.
DRAM/MMIO base add ress. In X86 or other host plat-
forms, the configuration space DRAM Base Address and
MM IO Base Add ress fields se rve two purposes. Firs t , th e
hos t BIO S sof t ware can us e th em t o dete rmi ne t he size s
of t he SDRAM and MMIO apertures. Second, the BIOS
can w ri t e to th es e fi elds t o caus e the a per tures t o be re-
located within the PCI memory address space.
To determine the sizes of an aperture, the BIOS first
writes all ‘1’s (0x FF FFFF FF) to the ad dre ss fi eld . When
the BIOS reads the field immediately after , the value re-
turned will have ’0’s in all d on ’t-care bits and ‘1’s in all re-
quired address bits. Required address bits form a left-
aligned (i.e., st arting at the MSB ) contiguous field of ‘1’s,
thus effect ively specifying the size of the aperture.
Fo r exam ple, t he MM IO a pe rt u re is a fi xe d 2- M B sp ac e .
After w riting all ‘1’s to the MMIO Base Address field, a
subsequent read returns the value 0xFFE00000. The M,
T, and P fields are all ’0’ indicating the aperture is mem-
ory (not I/O), can be relocated anywhere in a 32-bit ad-
dre s s sp ac e, an d is no t pr efe t c ha bl e. S in c e the ap er t ure
has 21 address bits (th e p osition of the first ’1’ bit), MMIO
space is a 2-MB aperture (221 bytes). The host BIOS now
as sign s a s uit abl e 2-MB al ig ne d bas e add res s by wri t in g
to the MMIO_BASE register in configuration space.
The DRAM aperture can range in size from 1 MB to 64
MB ( but t he siz e must be a p ower of 2). Thus, t he number
of r equi red addr ess bi ts can ran ge fr om 20 to 26. The ac-
tual amount of SDRAM present is determined by the con-
tent of the first byte of the boot EEPROM, as described
in Sec ti on 13 .4 , “Detailed EEPROM Contents.” Th e P CI
BIU uses this size to determine which of the bits marked
‘sp’ in Figure 11-7 are writable and which are set to ‘0’.
This causes the BIOS to determine the correct actual
DRAM aperture size.
Table 11-10. Type field encodings
Type Meaning
00 Base register is 32 bits wide; mapping can relocate
anywhere in 32-bit memory space
01 Base register is 32 bits wide; mapping must relocate
below 1 MB in memory space
10 Base register is 64 bits wide; mapping can relocate
anywhere in 64-bit address space
11 Reserved
31 0
DRAM_BASE M
DRAM Base Address
123 TP
MMIO_BASE MTP
4
00000000spspspspspsp00000000
25 19
MMIO Base Addres s 00000000000000000
31 0123420
Fig ur e 11 -7 . B a se ad dr e ss r eg ister fo r ma t.
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-9
11.5.12 Subsystem ID, Subsystem Vendor ID
Register
The sub syste m and subsys tem ve ndor ID ar e new i n PCI
Rev 2.1. T hes e fi el ds are optional, but their use is highly
re commen ded as a means to have sof tware dr ivers iden-
tif y the b o a rd rather than the chip on the board.
Th is r egis ter is impl emente d s t arting wit h PN X 130 0 and
onwards, and replaces the ‘Personality’ re gister function-
ality i n t he TriMed ia CTC ch ip .
The board manufacturer chooses the values of both 16
bits fields by modifying the PNX1300 Boot EEPROM.
The location of these bits is described in Section 13.4,
“Detailed EEPROM Contents.” A legal Vendor ID must
be obtained f rom the P C I SI G . Th e v end or i s f r ee t o as-
sign subsystem ID’s.
11.5.13 Expansion ROM Base Address
Register
Th e E xpa nsi o n ROM B ase A ddress r egis t e r is si milar in
purpose to the SDRAM and MMIO Base Address regis-
ters. This register relocates a separate memory ap ert ure
for PCI devices that wish to implement additional ROM.
PNX1300 does not implement expansion ROM; conse-
quently, the least-significant b it of thi s r e gist er —which in -
dicates whether or not PNX1300 responds to expansion
ROM accesses—is hardwired to ’0’. All other bits also
read as ’0’s.
11.5.14 Interrupt Line Register
The value of the Interrupt Line Register determines
which input of the system interrupt controller is driven by
PNX1300’s interrupt pin. As it configures the system and
assigns resources, host system software writes this reg-
ister to assign one of the system interrupt lines to
PNX1300.
11.5.15 Interrupt Pin Register
The val ue of the Interrup t Pi n Reg i ster dete rmines wh ich
interrupt pin PNX1300 uses. Table 11-11 lists the possi-
ble v alu es for this r egi ster .
Since PNX1300 uses inta#, the value of this register is
hardwired t o ‘1’.
11.5.16 Max_Lat, Min_Gnt Registers
The value in the Max_Lat register specifies how often the
PNX1300 PCI interface needs access to the PCI bus.
The value in the Min_Gnt register specifies the minimum
length for a bu rs t per i od on the P C I bus.
Both of these timer values are specified as multiples of
250 ns. Values of ’0’ indicate that a device has no specif-
ic r equ ir emen ts for la tenc y and burst- leng t h.
For PNX1300, Max_Lat is hardwired to 0x01 (250 ns),
and Min_G nt is h ar d w ire d t o 0x 03 (750 ns ) .
11.6 REGISTERS IN MMIO SPACE
The P NX 1300 PCI i nter fac e con t ains 1 3 M MIO re gi ster s;
most, except the status bits in BIU_Status, are usually
written only by the D SPCPU. Table 11-12 li st s the s up-
ported cycles sequenced by the PCI interface and the
registers involved in each cycle. To ensure compatibility
wi th fut ure de vices , all unde fined M MIO bits sho uld b e ig-
nor ed when read, and w ritt e n as ’0’s.
Th e M M IO re gi ster s ar e a ll ac ces si ble to D SPC PU sof t -
ware, and all but the PCI_ADR and PCI_DATA registers
are accessible to external PCI initiators. The facilities of
PNX1300’s PC I inte r face can be usef ul to ex tern al init ia-
tors in certain circumstances. F or example:
•The PCI DMA engine might be useful during host-
ass i s ted b oot .
•Host-resident diagnostics may want to test the PCI
int e rface during b oot .
•The MMIO registers can be used to diagnose mal-
func tio ni ng parts.
Note, however, that external PCI initiators can access
MMIO registers in only one way: as 32-bit words on nat-
urally aligned, 32-bit addresses. If any other type of ac-
cess is attempted, the results are undefined. Also, the
byte ord er of the exte rna l ini tiator and th e P CI in terf ace
must be th e same; ot herwise, the result o f an acces s wit h
disagreeing byte order is undefined.
For easy reference, Table 11-13 lists the MMIO registers
together with their offsets from MMIO_BASE and their
accessibility by the DSPCPU and external PCI initiators.
Figure 11-8 shows the formats of the PCI interface
MMIO registers. The following are detailed descriptions
of th e MM IO re g is ter s .
11.6.1 DRAM_BASE Register
The DRA M_BASE registe r in MMIO sp ace is a s hadow
copy of the DRAM_BASE register in PCI Configuration
space. See Sec tion 1 1. 5.11, “Base Address Registers,”
for more de tails . This co py pro vides MMI O-sp ace ac cess
to this register. The P,T and M bitfields of this MMIO reg-
ister are read-only.
11.6.2 MMIO_BASE Register
The MMIO_BAS E register in MMIO spac e is a copy of
the MMIO_BASE register in PCI Configuration space.
See Section 11.5.11, “Base Address Registers,” for
Tabl e 1 1 - 11. Int erru pt p in encod ing s
Interrupt Pin Meaning
1Use interrupt pin inta#
2 Use interrupt pin intb#
3 Use interrupt pin intc#
4 Use interrupt pin intd#
all others Reserved
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-10 PRELIMINARY SPECIFICATION
more details. This shadow copy provides MMIO-space
access to this register. The P,T and M bitfields of this
MMIO register are read-only.
11.6.3 MMIO/DRAM_BASE updates
The DRAM_BASE and MMIO_BASE registers are not
normally written through MMIO; their value is determined
by the boot process. Though no t recommended, the reg-
is ters are w ritable in MMIO. Special care s hould be exer-
cised when writing th ese registers:
•writing to SDRAM_BASE moves the origin of any
executing DSPCPU program, which will cause it to
fail
•writing to MMIO_BASE moves devices around, and
moves MMIO_ BASE and SD RAM _BASE around
•writing to both registers in sequence requires a delay,
due to the implementation. It is recommended to
space such writes far apart, or iterate until the first
register written to reads back with the new value
before writing the second one.
MMIO_base
offset:
DRAM_BASE (r/w)0x10 0000
MMIO_BASE (r/w)0x10 0400
BIU_STATUS (r/w )0x10 3004
SDRAM Base Address
MMIO Ba se Addr es s
BIU_CTL (r/w)0x10 3008
PCI_ADR (r/w )0x10 300C PCI Address
PCI_DATA (r/w)0x10 3010
CONFIG_ADR (r/w)0x10 3014
CONFIG_DATA (r/w)0x10 3018
DN
Error: Duplicate dma_cycle
CONFIG_CTL (r/w )0x10 301C
IO_ADR (r/w)0x10 3020 I/O Ad dre ss
IO_DATA (r/w )0 x10 3024 I/O Data
IO_CTL (r/w)0x10 3028
SRC_ADR (r/w)0x10 302C
DEST_ADR (r/w)0x10 3030 Destination Address
Sour ce Addr ess
31 0371115192327
Reserved IntE
PCI Data
BN
C onfigur ation Data
DMA_CTL (r/w)0x10 3034
INT_CTL (r/w)0x 10 3038 INT
TL
PTM
PTM
Error: Du plicate io_cycle or config_cycle
Done
Busy
Done
Busy
Done
Busy
Done
Busy
CR (PCI Clear Reset)
HE (Host Enable)
IE (ICP DMA Enable) BO (Bur st Mode Off)
SE (Byte Swap Enable)
00
RNFN
BE
RW (Read/Write)
BE
RW (Read/Write)
D
IE
PCI-to-SDRAM
dma_cycle
io_cycle
config_cycle
IS
SR (PCI Set Reset)
RMA Re ceived Maste r Abort
RTA Received Target Abort
TTE Target Timer Expired
T
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
RMD (Read Multiple Disable)
Fig ure 11-8. PCI interface registers accessible in MMIO add ress space.
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-11
11.6.4 BIU_STATUS Register
The BIU_Status register holds bits that track the status of
bus cyc le s in i tia ted by the DSPCPU and bus cycles from
exte rna l dev ices that w ri te into SDR AM.T wo b its of s ta -
tus are provid ed f or each type of bus cy cle: a bus y bit and
a don e bit. Th e DSP CP U can re ad both bits; a done b it
is cleared by writing a ‘1’ to it . The status register also
hold s two err o r-fl ag bits.
DSPCPU software must check the busy bits to avoid is-
suing a PCI interface bus cycle request while a request
of a similar type is in progress. If a bus cycle is issued
whi le a reque st o f similar type is in progres s, the PCI i n -
terface ignores the second command and sets the ap-
propria te error bit in the status re gister.
When the DSPCPU issues either an io_cycle or
conf ig_cycl e request while a previo us request o f either
type is already in progress, the PCI interface sets bit 8 in
BIU_STA TUS. When the DSPCP U issues a dma_c ycle
wh ile a p reviou s one i s alrea dy in pro gre ss, the P CI inter-
face sets bit 9 in BIU_STATUS. To reset either of the er-
ror bits 8 or 9 in BIU_STATUS write a ‘1’ to it.
RTA (Received target abort). This bit is set when
PNX 1 30 0 initiated a tran s ac tio n that w a s a bo r te d by t he
target. To reset this bit, write a ‘1’ to this bit position. This
bi t is set sim ultaneous with the R TA bi t in t he configura-
tion space status register, but is cleared independently.
RMA (Received master abort). This bit is set when
PNX1300 initiated a transaction and aborts it. This usu-
al ly signals a tr an sa c tion t o a no n ex is te nt dev ic e. To r e -
set this bit, write a ‘1’ to this bit position. This bit is set si-
mult an eous with the RM A bi t in the co nfi gurat io n spa ce
st atus r egis t er, bu t is c le ar ed in dependen t l y.
TTE (Target timer expired). In normal operation, a read
of a PNX1300 data item is performed on retry basis:
PNX 1 30 0 tells the ex t e rnal m as t e r t o retr y, me anw hi le it
fetches the data item across the highway. This bit is set
if an external master did not retry a read of a PNX1300
dat a ite m wit hin 32 768 PCI cl ocks. The re quested da ta is
discarded. To reset this bit, write a ‘1’ to this bit position.
Thi s is pu rel y a softw ar e inf o rmat i on bit . No sof twa re ac-
tion is re quired when this condition occurs, but it may in-
di ca te a no n- c o mp lian t or d efe c tiv e mas t er on the bu s.
11.6.5 BIU_CTL Register
The BIU_CTL register contains bits that control miscella-
neous aspects of the PCI interface operation. Following
are de s cri ption s of the fields.
SE (Swap bytes enable). This bit is initialized after reset
to ’0’, wh ic h c aus es the PC I int e rfa ce to o pera t e i n it s d e-
fau lt bi g-end ian mo de. Wr iti ng a ’1’ to SE ca uses ac cess-
es to MMI O reg iste rs ov er the PCI in terf ace t o b e ma de
in littl e endia n m od e.
BO (B urst m ode of f) . This bit is init ializ ed to ’0’, which
allow s the PC I inter f ac e t o su pp or t bu r s t-m ode w rite s as
a target on the PCI bus. Setting this bit to ’1’ disables
burst-mode writes.
With burst mode enabled, the PCI interface buffers as
much data as possible into r_buffer before issuing a dis-
connect to the PCI initiator. With burst mode disabled,
th e PC I int e r face buffe r s onl y one data phase befo r e i s-
suing a d is c on ne ct to the P CI in i tia t o r.
IntE (Interrupt enables). The bits in the IntE field control
the s ignalin g of in terrup ts t o the DS PCPU fo r PCI inte r-
face e ve nts. T he se ev en ts rais e D SPC PU in terrup t 16 i f
enabled. Interrupt 16 must be set up as a level triggered
interrupt. Table 11-14 lists the function of each IntE bit.
IntE is initially set to ‘0’s (interrupts disabled).
Not e that the error condition masked by bit 6 (see Sec-
tion 11.6.4, “BI U_STATUS Register”) occurs when either
a confi g_cycle or an io_cycl e is requested and a request
of either t y pe is already i n p rogress. That is, the second
Tab l e 11 -12. PCI M MI O re gi s ter s and bus cycles
Internal Cycle Registers Involved
mmio_cycle
(MMIO register R/W) All registers accessible by
exter nal PCI devices
mem_cycle
(PCI-space memory R/W) PCI_ADR,
PCI_DATA
dma_cycle
(Block data transfer) SRC_ADR,
DEST_ADR,
DMA_CTL
IO_cycle
(I/O r egis ter R /W) IO_ADR,
IO_DATA,
IO_CTL
config_cycle
(Configuration register R/W) CONFIG_ADR,
CONFIG_DATA,
CONFIG_CTL
Table 1 1-13. PCI MMIO registe r accessibility
Register MMIO_BASE
Offset
Accessibility
DSPCPU External
Initiator
DRAM_BASE 0x10 0000 R/W R/W
MMIO_BASE 0x10 0400 R/W R/W
BIU_STATUS 0x10 3004 R/W R/W
BIU_CTL 0x10 3008 R/W R/W
PCI_ADR 0x10 300C R/W –/–
PCI_DATA 0x10 3010 R/W –/–
CONFIG_ADR 0x10 3014 R/W R/W
CONFIG_DATA 0x10 3018 R/W R/W
CONFIG_CTL 0x10 301C R/W R/W
IO_ADR 0x10 3020 R/W R/W
IO_DATA 0x10 3024 R/W R/W
IO_CTL 0x10 3028 R/W R/W
SRC_ADR 0x10 302C R/W R/W
DEST_ADR 0x10 3030 R/W R/W
DMA_CTL 0x10 3034 R/W R/W
INT_CTL 0x10 3038 R/W R/W
Table 11-12. PCI MMIO registers and b us cycles
Internal Cycle Registers Involved
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-12 PRELIMINARY SPECIFICATION
request need not be of exactly the same t ype t hat is al-
ready in progress.
IE (ICP DMA enable).This bit is must be set to ’1’ to a llow
the IC P to write pixel data th rough the PCI interface. If
th is bit i s cle ared to ’0’, the ICP is not allowed to use the
PCI i nt erfa ce. Pr ogra mmin g of I CP DMA is desc rib ed in
Secti on 14.6, “Operation and Programming.”
HE (Host e na ble). T his bit is ini t ia lize d to ’0’, which pre-
vents the DSPCPU from serving as the host CPU in the
PCI system. If this bit is set to one, the Enable Mastering
(EM) bit in the PCI Configuration register (see Section
11.5.3, “Command Register”) is also set to ’1’ (since
PNX13 00 mu st be enable d to serv e as a PCI bu s init iator
to perfor m P C I co nfig ur ation).
CR (PCI clear reset). This bit releases the DSPCPU
fr om its res et sta te . The PNX1 30 0 dev ic e dri ver (exe cu t-
ing on an external host CPU) sets this bit to ’1’ after it
completes PNX1300’s configuration. The DSPCPU
starts to execute the pointed by DRAM_BASE MMIO
register.
SR (PCI set reset). Th is bit for ces the DSPC PU i nto its
reset state. Writing ’1’ t o this bit r esets the CPU; writing
’0’ causes no action. The PNX1300 device driver (exe-
cuting on an external host CP U) can set this bit to reset
the DSPCPU. This form of reset resets only CPU and In-
struction cache. The Dcache is NOT reset, nor are any
peripherals.
RMD (Read Multiple Disable). In default operating
mode, the RMD bit should be set to ‘0’. In that c as e , the
BIU uses ‘memory read multiple’ PCI transactions for
BIU DMA, and ‘memory read’ PCI transactions for
DSPCPU reads to PCI space. If the RMD bit is set, DMA
transactions a re forced to also use t he - less efficient -
memory read transactions. Note that TM-1000 only used
memor y r ead t r ansa ctions.
11.6.6 PCI_ADR Register
The 30-bit PCI_ADR register is intended to be written
onl y by the data cache . PC I_ADR par ticipate s in the spe-
cial two-cycle data-cache-to-PCI protocol. See Section
11.6.7, “PCI_DATA Register,” for more information.
Only t he DSPCPU c an write to PCI_A DR. Exte rnal PCI
initiators can neither read nor write this register.
DSPCPU software should not write to this register (by
writ ing to P CI _ADR in MMIO s pace ). Th is re gis ter is in -
te nd ed on ly t o s u ppor t th e s pec ia l pr o toc o l b etw ee n the
data cache and PCI bus. An unexpected write to
PCI_ADR via MMIO space will not be prevented by hard-
ware and may result in data corruption on the PCI bus.
11.6.7 PCI_DATA Register
The 32-bit PCI_DATA register is intended to be used
only by the data cache. PCI_DATA participates in the
special two-cycle data-cache-to-PCI protocol.
The PCI_DATA and PCI_ADR registers are used togeth-
er by the data cache to perform a single data phase PCI
memory-space read or write. A read operation is trig-
gered when the data cache has writt en the transaction
address in to PCI_ADR and asser ted the inter nal signal
pci_read_operation (a direct internal connection be-
twe en the da t a c ac h e an d PC I interfac e) . A write op er a -
tion is triggered when the data cache has written both
PCI_ADR and PCI_DATA with the signal
pci_read_o per at ion de as se rt ed .
While the PCI interface is performing the PCI read or
write, the DSPCPU is st alled waiting for the completion
of the PCI transaction. When the PCI transaction is com-
plete, the PCI interface asserts pci_ready (a direct inter-
nal connection between the data cache and PCI inter-
face). T o finish a read operation, t he data cache reads
the PCI_DATA register, forwards the data to the
DSPCPU, and then unlocks the DSPCPU. To finish a
write, the data cache simply unlocks the DSPCPU.
Note that, if the DSPCPU attempts to access a non-exis-
tent PCI address, an RMA condition occurs. In this case,
the v alue in th e PCI_DA TA re gister is set to ‘0’. Hence ,
the DSPCPU always reads non-existent PCI locations as
‘0’.
No rmal MMIO w rit e o per at ion s t o PCI_ DAT A have no ef-
fect. Reads return the register’s current value. External
PCI initiators can neither read nor write this register.
11.6.8 CONFIG_ADR Register
The CONF I G_A DR re gist er is wri tte n by the DSP CPU t o
set up for a configuration cycle. When PNX1300 is acting
as the host CPU, it must configure devices on the PCI
bus. The DSPCPU write s CONFIG_ADR to select a con-
figuration register within a specific PCI device. See Sec-
tion 11.6.10, “CONFIG_CTL Register,” for more infor-
mati on on i niti atin g confi gu r at io n cycl es .
Following are descriptions of the fields of CONFIG_ADR.
BN (PCI bu s number). The BN fi el d (the two leas t-s ig-
nificant bits of CONFIG_ADR) selects one of four possi-
ble P CI bu ses . A v alu e of ’0’ fo r B N me an s that t he ta r-
geted device is on the PCI bus directly connected to
PNX1300 and that any PCI-to-PCI bridges should ignore
the conf igura tio n addre ss. Any value for B N ot her than ’0’
means th at the targeted devi ce is on a P CI bu s connect-
ed to a PCI-to-PCI bridge and that all devices directly
c onnected to PNX 1300’s lo cal PC I bus should ignore the
configur ation addr e ss.
RN (Register number). The RN field (bits 2..7 of
CO N FIG _A D R) i s used t o s peci fy on e of the 64 config u-
Table 1 1 -14. IntE b it function s
BIU_CTL Bit If se t t o ‘1’, interrupt DSPCPU when...
2 config_cycle done
3 io_cycle done
4 dma_cycle done
5 pc i_d ram write cycle done
6 second confi g_cycle or io_cycle requested
7 second dma_cycle requested
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-13
ration words within the target device’s configuration
space.
FN (Function number). The FN field (bits 8..10 of
CON FIG_ADR) i s us ed to speci fy one of up to eight func-
tio ns o f t he a dd ressed PC I device.
DN (Device number). The DN field (bits 11..31 of
CONFIG_ADR) is used to select the targeted PCI de-
v ice. Each bit corr esponds to one of the 21 po ssible PCI
devices on a single PCI bus, i.e., each bit correspo nds to
the idsel signal of one PCI device. Only one idsel sig-
nal—and, therefore, only one DN bit—can be asserted
during a given configuration cycle.
11.6.9 CONFIG_DATA Register
The 32-bit CONFIG_DATA register is used by the
DSPCPU to buffer data for a configuration cycle. When
PNX13 00 is acti ng as the host CPU , it m ust conf igure the
PCI bus and devices. The DSPCPU writes or reads
CON FI G_D AT A de pe ndin g on whet her it is per for m in g a
write or read to a PCI device’s co nfigurat io n space . Se e
Section 11.6.10, “CONFIG_CTL Register,” for mor e in-
formation on initiating configuration cycles.
11.6.10 CONFIG_CTL Register
The DSPCPU wri tes to CONFIG _CT L to tri gger a conf ig-
uration read or write cycle on the PCI bus. A PCI config-
ura tion r e ad or wr i te shoul d not be p erformed dur ing a n
ongoin g P CI I/O re ad or wri te.
The steps involved in a DSPCPU PCI configuration ac-
ce s s are :
1. Wait until BIU_STATUS io_cyc le.Busy and
config_cycl e. B usy are b oth de- ass ert ed
2. Write to CON F I G_ADR as de sc r ibe d above, an d ( in
c ase of a wri te op er atio n) write to C O NFIG_DATA.
3. Write to CONFIG_CTL to start the read or write.This
act i on sets config_c ycle .Bu sy.
4. Wait (polling or interrupt based) until
config_c yc le. Don e is as s ert e d by th e ha r dware.
5. Retrieve the requested data in CONFIG_D ATA (in
c ase of a rea d)
6. Clear config_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of CONFIG_CTL
and a discussion of how a DSPCPU write to
CONFIG_CTL triggers configura tion cycles.
BE (Byte enables). The BE field (the four LSBs of
CONFIG_CTL) determines the state of PCIs 4-line c/be#
bus during the data phase of a configuration cycle. Since
the c/be # bu s sign al s are acti ve l ow , a ‘0’ in a BE field bit
means byte participates; a ‘1’ in a BE field bit means
‘byte does not participate.’ Table 11-15 shows the corre-
spondence between BE bits and bytes on the PCI bus
assum ing little- en dian byte order.
RW (Read/Write). The RW field (bit 4 of CONFIG_CTL)
det erm ines whe ther the confi gur ation cyc le will be a read
or a write. Table 11-16 shows the interpretation of RW.
A write by the DSPCPU to the CONFIG_CTL register
starts a configuration cycle on the PCI bus. The
CONFIG_DATA (for a write) and CONFIG_ADR regis-
ter s mus t be set up before w ri tin g to CO NFIG _ CTL .
During a co nfigur a tio n r e ad , the PCI inter face d ri v e s the
PCI bus with the address from CONFIG_ADR and the
BE field from CONFIG_CTL. The returned data is buff-
ered in C ONFIG_ DATA. W hen th e data is ret urned , the
PC I inte r face wil l g en era te a DSPCP U i nt err u pt if the ap-
propriate IntE bit is set in BIU_CTL. Alternatively,
DSPCPU sof twar e can pol l the appr opria te “done” sta tus
bin in BIU_STATUS. Finally, DSPCPU software reads
the CONFIG_DATA register in MMIO space to access
the data returned from the configurat ion cycle.
A write operation proceeds as for a read, except that PCI
data is d riven from CONF IG_DATA d uring the tran sac-
tion and no data is returned in CONFIG_DATA.
11.6.11 IO_ADR Register
The 32-bit IO_ADR register is written by t he DSPCPU to
set up for an ac c es s t o a lo c ati on in PCI I/O s pa c e. The
DSPCPU writes the address of the I/O register into
IO_ADR. See Section 11.6.13, “IO_CTL Register,” for
more information on initiating I/O cycles.
11.6.12 IO_DATA Register
The 32-bit IO_DATA register is used by the DSPCPU to
set up for an ac c es s t o a lo c ati on in PCI I/O s pa c e. The
DSPCPU writes or reads IO_DATA depending on wheth-
er it is performing a write or read from IO space. See
Section 11.6 .13, “IO_CT L Regi ster, ” for more informa-
tion on init iatin g I/O c y cl es .
11.6.13 IO_CTL Register
The DSPCPU writes to IO_CTL to trigger a read or write
ac cess to PCI I/O s pace. Th e functio n of thi s re gister is
similar to that of CONFIG_CTL, and the protocol for an I/
O cycle is similar to the configuration cycle protocol. A
Table 11-15. BE field interpretation (assumes little-
endian byte o rdering)
BE B it Interpretat ion
00 ⇒ byte 0 (LSB) participates
1 ⇒ byte 0 (LSB) does not participate
10 ⇒ byte 1 participates
1 ⇒ byte 1 does not participate
20 ⇒ byte 2 participates
1 ⇒ byte 2 does not participate
30 ⇒ byte 3 (MSB) participates
1 ⇒ byte 3 (MSB) does not participate
Table 11-16. RW Interpretation
RW Interpretation
0Write
1Read
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-14 PRELIMINARY SPECIFICATION
PCI I/O read or write should not be perfor med du ring an
ongoin g P CI co nfi gu r at io n re ad or wr ite.
Th e steps inv olved in a D S PC PU PC I I/ O acces s a re:
1. Wait until BIU_STATUS io_cyc le.Busy and
config_cyc le.B usy ar e both de-asserted
2. Write IO ad dr e s s to IO _AD R , and ( in c as e of a w rite
oper a t io n) write data to I O _ DATA.
3. Write to IO_CTL to start the read or write.This action
sets io_cycle.Busy.
4. Wait (polling or interrupt based) until io_cycle.Done is
asserted by the hardware.
5. Retriev e the requested data in IO_DATA (in case of a
read)
6. Clear io_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of IO_CTL and a
dis cus si on of how a DSPC PU wri te to IO_C TL tr igg er s I/
O cycles.
BE (Byte enables). The BE f ield (t he four least-signifi-
cant bit s of IO _ C TL ) dete r mi ne s th e sta t e of PCI’s 4-line
c/be# b us during the data phase o f an I/O cyc le. S ince
the c/be # bu s sign al s are acti ve l ow , a ‘0’ in a BE field bit
means ‘byte participates;’ a ‘1’ in a BE field bit means
‘byte does not participate.’ Table 11-15 shows the corre-
spondence between BE bits and bytes on the PCI bus
assum ing little- en dian byte order.
RW (Read/Write). The RW field (bit 4 of IO_CTL) deter-
mines whether the I/O cycle will be a read or a write.
Table 11-16 sh ows the inter preta tion o f RW (0 ⇒ wri te,
1 ⇒ read).
A write by the DSPCPU to the IO_CTL register starts an
I/O cycle on the PCI bus. The I O_DATA (for a write) and
IO_ADR registers must be set up before writing to
IO_CTL.
During an I/O read, the PCI interf a ce d r iv es the PC I bus
with the address from IO_ADR and the BE field from
IO_CTL. The returned data is buffered in IO_DATA.
When the da ta is retu rned, the PCI in terface w ill ge ner-
ate a DSPCPU interrupt if the appropriate Int E bit i s set
in BIU_CTL. Alternatively, DSPCPU software can poll
the appr opria te ‘done’ stat us bi t in BIU_ STAT US. Fina lly,
DSPCPU so ft w are reads th e IO_DATA register in MMIO
space to ac ces s the da t a r eturned fr om the I/ O c yc le.
A write operation proceeds as for a read, except that PCI
data is driven from IO_DATA during the transaction and
no data is returned in IO_DATA.
11.6.14 SRC_ADR Register
The 32-bit SRC_ADR register is used to set the source
add r ess for a bl oc k tr a nsfe r D MA o pe rat i on. The ad dre ss
in SRC_ADR must be word (4-byte) aligned, i.e. the 2
LSB s have to be ‘0’. Th e con ten t o f thi s r e gist er d ur i ng or
aft er DM A is not defi ned, he nce i t cann ot be us ed to tra ck
progress o r ver ify completion o f a DMA transaction.
11.6.15 DEST_ADR Register
Th e 32-b it D EST_ ADR regi st er is u sed to se t th e des ti -
nat ion addr ess f or a b lo ck t ransf er D MA o per atio n. T he
address is DEST_ADR must be word (4 byte) aligned,
i.e. the 2 LSBs must be ‘0’. The content of t his register
during or after DMA is not defined, hence it cannot be
used to track progress or verify completion of a DMA
transaction.
11.6.16 DMA_CTL Register
A write by the DSPCPU to the DMA_CTL register starts
a DMA block transfer on the PCI bus. The SRC_ADR
and DEST_ADR registers must be set up before writing
to DMA_CTL.
The steps involv ed in a DMA transfer are:
1. Wait until BIU_STATUS dma_cycle.Busy is de-assert-
ed
2. Write to SRC_ADR and DEST_ADR as described
above
3. Write to DMA_CTL to start the DMA transaction.This
act i on sets dma_ cyc le. Busy
4. Wait (polling or interrupt based) until dma_cycle.Done
is asserted by the ha rdware
5. C lear dma_cycle.Don e by writing a ‘1’ to it
The fields of DMA_CTL are described below.
TL (Transfer length). The TL field (bits 0..25 of
DMA_CTL) specifies the number of data bytes to be
tr an sfer re d du r ing t he DMA op era ti on . It must be a mult i-
pl e of 4 byte s. The ma x imum l en gth of a DMA oper ati on
is limited to 64 MB, the maximum amount of SDRAM
supported by PNX1300. The content of this field during
or after a DMA transaction is not defined.
D (DMA direction). Th e D fi el d (bi t 26 of DMA_ CTL ) de-
term ines the directi on of data movement during the block
transfer. Table 11-17 (shows the interpretation of the D
field.
T (DMA Transaction type). The T field (bit 27 of
DMA _CTL ) determine s the t ransacti on typ e of a wri te, as
described below.
Table 11-17. D interpretation
D Data Movement Directi on
0 SDRAM → PCI memory space (DMA write)
1 PCI memory space → SDRAM (DMA read)
Table 11-18. T interpretation
T DMA Write transaction type
0memory write
1 memo r y w r i te- and- invalidate
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-15
PNX1300 generates memory write-and-invalidate PCI
transactions if all conditions below are satisfied, other-
wise it generates regular memory write transactions:
•The MWI bit in the Command Register is set.
•Th e Cach e Line Size regis ter is s et to 4 ,8 , or 16 32 -
bit words.
•The DMA source address is 64 byte aligned.
•The DMA destination address is cache line size
aligned.
•The T bit is set
PNX1300 generates ‘memory read multiple’ PCI transac-
tions for DMA reads, unless the RMD (Read Multiple Dis-
able ) bit is set in BIU_CTL, in which case the less effi-
cient ‘memory read’ transactions are used.
During a PCI → S DRAM bloc k t ra nsf e r, the PC I interface
dr ives t he PCI b us wit h the addr ess fr om SRC_A DR. Th e
returned data is buffered in r_buffer. The PCI interface
then drives the address from DEST_ADR and the data
from r_buffer to the SDRAM controller. SRC_ADR and
DEST_ADR are incremented, the TL field in DMA_CTL
is decremented, and this sequence repeats until TL
reaches ‘0’.
At the end of the PCI → SDRAM block transfer, the PCI
interface will generate a DSPCPU interrupt if the appro-
priat e IntE bit is set i n BIU_ CTL . Alternati vely, DSPC PU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
During an SDRAM → PCI b lock tran sf er, t he PCI inter-
fa ce dri ve s the add res s from SRC _A DR t o th e SD RAM
controller. The returned data is buffered in w_buffer. The
PCI int erf ace then drive s th e a ddre ss fr om DES T_A DR
and the data from w_buffer to the PCI bus. SRC_ADR
and DEST_ADR are incremented, the TL field in
DMA_CTL is decremented, and this sequence repeats
unt il T L r e ac hes ‘0’.
At the end of the SDRAM → PCI block transfer, the PCI
int erface can generate a D S PC PU in terr up t if th e appro-
priat e IntE bit is set i n BIU_ CTL . Alternati vely, DSPC PU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
11.6.17 INT_CTL Register
The INT_CTL register contains three fields for setting,
enabling, and sensing the four PCI interrupt lines.
Table 11-19 shows the interpretation of the fields in
INT_CTL.
INT (Interrupt bits). The INT field (bits 0..3 of INT_CTL)
can force a PCI interrupt to be signalled.
IE (Interrupt enable). The IE field (bits 4..7 of INT_CTL)
enable s P N X1 30 0 t o dri ve P CI in t e rr up t lines .
IS (Interrupt state). The IS field (bits 8..11 of INT_CTL)
senses the state of the PCI interrupt lines.
Figure 11-9 shows a conceptual realization of the logic
used to implement the control of each intx# pin.
See also Sec ti on 3.6 , “PNX1300 to Host Interrupts.”
11. 7 PCI BUS P ROTOCOL OVERVIEW
PNX1300’s PCI interface can generate and respond to
several types of PCI bus commands. Table 11-20 lists
the 12 po ssible commands and w hethe r or not PNX1300
can generate them.
Table 11-21 lists the 12 possible commands and wheth-
er or not PNX1300 can respond to them.
The basic transfer mechanism on the PCI bus is a burst,
which consists of an addr ess phase followed by one or
more data phases. In PNX1300, the DSPCPU and ICP
are the only two units that can cause PNX1300 to be-
Table 11-19. INT_CTL Bits
INT_CTL PCI Signal Programming
Field Bit
INT 0 inta# 0 ⇒Deassert intx#
1 ⇒Assert intx# (if enabled);
i.e., pull intx# pin to a low
logic level
1 intb#
2intc#
3 intd#
IE 4 inta# 0 ⇒Disable open-c ollect or
output to intx#
1 ⇒Enable open-collector
output to intx#
5 intb#
6intc#
7 intd#
IS 8 i nta# Read s state of intx# pin:
0 ⇒No interr upt asserted
(intx# is high)
1 ⇒Interrupt is asserted
(intx # is low)
9 intb#
10 intc#
11 intd#
Table 11-20. PNX1300 PCI Commands as Ini tiator
PNX1300 Generates PNX1300 Cannot
Generate
Configuration read
Configuration write
Memory read
Memory read multiple
Memory write
Memory write and invalidate
I/O read
I/O wri te
Interrupt acknowledge
Special cycle
Dual address
Memor y read line
INTx
oc PCI intx#
IEx
ISx
Figure 11-9. Conceptual realization of intx# pin con-
trol logic.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-16 PRELIMINARY SPECIFICATION
come a PCI-bus initiator, i.e., only the DSPCPU and ICP
can access external resources.
11.7.1 Single-Dat a-Phase Operations
When the DSPCPU reads or writes PC memory, the PCI
transaction has only a single data phase. A typical sin-
gle-data-phase read operation is illustrated in
Figure 11-10. During the first clock period, the PNX1300
asserts the frame# signal to indicate that the transaction
has begun and that an address and command are stable
on ad and c/be#, respectively.
PNX1300 then releases the ad bus, deasserts frame#,
asserts irdy#, asserts byte enables on c/be#, and waits
for the target to claim the transaction by asserting
devsel#. The target asserts trdy# to signal the master
that the ad bus contains stable data. The assertion of
trdy# causes the initiator (PNX1300 in this case) to sam-
ple the ad bus data and deassert irdy# to complete the
single-data-phase read transaction.
Figure 11-11 shows a ty pica l sing le-dat a-ph ase wri te op-
eration. The operation begins like a read: PNX1300 as-
serts t he fr ame# signal and dr ives the ad bu s with the tar-
get address and drives the command on to the c /be# bus.
The operation continues when PNX1300 deasserts
fr am e# , ass er ts i r dy #, and dri ve s th e b yt e en able s a s b e-
fore, but it also drives the data to be written on the ad
bus. The target device asserts devsel# to claim the trans-
action. Eventually, the target asserts trdy# to signal that
it is s ampli ng t he dat a on t he ad bu s. PNX1300 co ntinue s
to drive the data on the ad bus until after the target deas-
ser ts trdy#, w hich com pletes the w r ite operation.
11.7.2 Multi-Dat a-Phase Operations
As with the single-data-phase operations, DMA opera-
tions begin with the assertion of frame# and valid ad-
dr ess and com man d in fo rm ati on . See Figure 11-12. The
target knows a burst is requested because frame# re-
mains ass er ted w hen ir dy # beco mes as s e rt e d.
In th e examp le tim ing of Figure 11-12, a fast device is re-
ceiving the burst from PNX1300. The target asserts
devsel# and trdy# simultaneously. The trdy# signal re-
mains asserted while PNX1300 sends a new word of
data on each PCI clock cycle. The burst operation shown
is a 16-word burst transfer. Since only the starting ad-
dr ess is sent by the in iti ator, both initi ator an d targe t must
increment source and destination addresses during the
burst.
The initiator signals the end of the burst of data in
Figure 11-12 when it deasserts frame# in clock 17. The
last word (or partial word) of data is transferred in the
c lock cy cle aft e r frame# is deas ser te d. Fina lly , the target
ack now ledg es th e last da ta ph ase by d eas ser ting trd y#
and devs el#.
Figure 11-13 illustrates back-to-back DMA burst data
transfers. The ICP is capable of exploiting the high band-
wid th a vailable with bac k-to -b a ck D M A op e rati ons when
it is writing image data to a frame buffer on a PC I v id eo
card.
Th e timin g of Figure 11-13 a ssume s th at the PCI bus is
granted to PNX1300 until at least the beginning of the
second DMA burst operation. For as long as bus owner-
ship is gr a nted to P N X1300 a nd t h e IC P ha s queu ed r e -
quests for data transfer, the PCI interface will perform
back-to-back DMA operations. If the target eventually
bec omes una ble to acc ept mor e data, i t signal s a disco n-
nect on the PNX1300 PCI interface. The PCI interface
remembers where the DMA burst was interrupted and at-
temp ts to re st art fro m tha t po int a fte r two bu s clocks.
Ta ble 11-21. PNX1300 PCI commands a s target
PNX1300 Responds To PNX1300 Ignores
Configuration read
Configuration write
Memory read
Memory write
Memory write and invalidat e
Memory read li ne
Memory read multiple
I/O read
I/O write
Interrupt acknowledge
Special cycle
Dual address
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
1234
Address
Byte Enables
Command
Data
Wa it (AD turnaround)
Data Transfer
Figure 11- 10. Basic single-data-phase read opera-
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
123 n
Address Data
Byte EnablesCommand
Wait
Da t a Transfer
Fig ure 11-11. Basic single-data-phase write opera-
Philips Semiconductors PCI Interface
PRELIMINARY SPECIFICATION 11-17
11.8 LIMITATIONS
11.8.1 Bus Locking
The PCI interface does not implement lock#, sbo, and
sbone pins. Consequently, it is possible for both the
DSPCPU and external PCI initiators to wr it e to a criti cal
memory section simultaneously. Software must imple-
ment policies to gua rantee memo ry coher ency.
11.8.2 No Expansion ROM
PNX1300 does not implement the PCI expansion ROM
capability.
11.8.3 No Cacheline Wrap Address
Sequence
The PCI interface does not implement the PCI cacheline-
wrap address mode for external PCI initiators that ac-
cess PNX130 0 SDRAM .
11.8.4 No Burst for I/ O or Configuration
Space
On ly sin gle-da ta-phas e trans acti ons to conf igur atio n and
I/O spaces are supported. The byte-enable signals se-
lect t h e by te(s) within the ad dr e ss e d wo rd .
11.8.5 Word-Only MMIO Register Access
Ex ter nal in itiator s can a c cess PNX1300 MMIO registers
only as full words. The byte-enable signals have no ef-
fect on the data transferred. External initiators must read
and w rite all four b yte s of MMIO reg i ster s.
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
123456 17
Address
Byte Enables
18
Command
Data 1 Data 2 Data 3 Da ta 4 Data 15 Data 16
Data Transfer
Data Transfer
Data Transfer
Data TransferData Transfer
Data Transfer
Data Transfer
Figure 11-12. PCI burst write operation with 16 data phases.
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
1 2 3 18 19 20
Address
Byte Enables
35
Byte EnablesCommand
Data 1 Data 15 Data 16 Data 17 Data 31 Data 32
36
Da t a Transfer
Da t a Transfer
Da t a Transfer
Da t a Transfer
Da t a Transfer
Da t a Transfer
Figur e 11-13 . Bac k-to -back PCI burst wr it e ope r atio ns wit h 16 d ata ph as es which mi ght be ge ne rated by the
ICP when writing image data to a PCI-resid ent video frame buffer.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
11-18 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 12-1
SDRAM Memory System Chapter 12
by Eino Jacobs, Chri s Nelson, Thorwald Rabeler, Moh ammed Yous uf, Luis Lucas
12.1 NEW IN PNX1300/01/02/11
•Support of 256-Mbit SDRAMs organized in x16. The
REFRESH counter must be changed. Refer to
Section 12.11 for more details.
•16-bit memory interface support in addition to the 32-
bit mode of TM-1300.
12.2 PNX1300 MAIN MEMORY OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 connects to its local memory system with a
dedi ca ted m em ory bus , sho wn in Figure 12-1. This bus
interfaces only with SDRAM or SGRAM (synchronous
graphics DRAM with its DSF pin tied low); PNX1300 is
the only master on this bus.
A variety of device types, speeds, and rank1 sizes are
s uppor t ed all ow i ng a wi de ran ge of PNX1 30 0 system s t o
be built. Table 12-1 sum mari zes the memory syst em fea-
tu res . Th e m em or y d ev ic e s can ha ve t wo o r four banks.
The mai n mem or y inter f ac e pro vid es all cont rol and data
signals with sufficient drive capacity for a glueless con-
nection up to a 183-MHz memory system ( for PNX1302,
166 MHz otherwise) with up to two memory devices. The
memory-system speed can be different from PNX1300
core s peed; t he r a ti o bet ween the memory system clock
and P N X1 300 co r e cl oc k is p rogr am m ab le .
With current memory technology, PNX1300 supports a
glueless memory interface of up to 64MBytes with two
4×4M×16 SDRAM chips (two devices with 4 banks of
four million words, each 16 bits wide).
PNX1300 provides also a 16-bit memory interface (in-
stead of 32-bit only for TM-1300) for applications requir-
ing lower cost and lower performance. The available
bandwidth is then reduced by two and the latency on
cache misses is increased by two for the Instruction
cache and by one SDRAM cycle f or the Data cache on
c ritical wor d fir st dema nd.
The maximum amount of memory in the 16-bit mode is
32MBytes.
12.3 MAIN-MEMORY ADDRESS
APERTURE
PNX1300’s lo ca l ma in m e mo r y is j us t one of th re e a p er-
tures into the 4-GB address space of the DSPCPU:
•SDRAM ( 0 .5 to 64 MB in size),
•MMIO (2 MB in size), and
•PCI (any address not in SDRAM or MMIO).
MMIO registers control the positions of the address-
s pac e ape r tur es . T he SD RAM apert ur e begins a t the ab-
solute address specified in the MMIO register
DRAM_BASE and extends upward to the address spec-
ified in the DRAM_LIMIT register. If the SDRAM a p erture
overlaps the memory hole, the memory hole is ignor ed.
The MMIO aperture begins at the address in
MMIO_BASE, which defaults to 0xEFE00000 a f ter p ow -
er-up, and extends upwards 2 MB. (See Chapter 3,
“DSPCPU Architecture,” for a detailed discussion.) All
addresses that fall outside these two apertures are as-
sumed to be part of the PCI address aperture.
1. In this document, the term ‘rank’ is used to refer to a
group of memory devices that are accessed together.
Historic ally, the te rm ‘bank’ has been use d in this con-
text; to avoid confusion, this document uses bank to re-
fer to on -chip organi zation (S DRAM device s ha ve two
or four internal banks) and rank to refer to off-chip, sys-
tem-le vel or gani za tion .
Table 12-1. Memory System Features
Characteristic Comments
Data width 16 and 32 bits
Number of ranks Four chip-select signals support up to four
ranks (can be used as addresses)
Memory size From 512 KB to 64 MB
Devices
supported •J edec SGRA M (DSF ti ed low)
•Jedec SDRAM (×4, ×8, ×16, ×32)
•PC100/133 and later
Clock rate Up to 183 MHz SDRAM speed (program-
mable ratio betwe e n
core clock and memory system clock)
Bandwidth 732 MB/s (at 183 MHz and 32-bit i/f)
Glue le ss in terface •Up to 2 chips at 183 MHz (e.g., 32 MB
memor y with 4x1Mx32 SDRAM)
•Up to 4 chips at 166 M Hz (e.g., 64 MB
memor y with 4x1Mx32 SDRAM)
Signal level s 3.3-V LVTTL
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-2 PRELIMINARY SPECIFICATION
12.4 MEMORY DEVICES SUPPORTED
All devices must have a LVTTL, 3.3-V interface.
Table 12-2 lists the devi ces and o rga ni za tion s s up po rte d
in a 32-bit memo ry inte rface .
Refer to Section 12.8, “Address Mapping,” in order to
evaluate the support of 2-bank, 64-Mbit devices. These
devices are not widely used. Hence they are not de-
scr i be d in t h is do cum ent.
Table 12-3 lists the devi ces and o rga ni za tion s s up po rte d
in a 16-bit memo ry inte rface .
12.4.1 SDRAM
PNX1300 supports synchronous DRAM chips directly.
SDRAM has a fast, synchronous interface that permits
burst transfers at 1 word per clock cycle. The memory in-
side an SD R A M dev ice is div ided into tw o or f our bank s;
the SDRAM im pl em ents i nter lea ve d ba nk acce ss to su s-
tain maximum bandw idth.
SDRAM devices implement a power down mechanism
with self-refresh. PNX1300 power management takes
advantage of thi s mechan is m .
PNX1300 supports only Jedec-compatible SDRAM with
two or four internal banks of memory per device.
12.4.2 SGRAM
Also supported in PNX1300 systems, SGRAM is essen-
tially an SDRAM with additional features for raster graph-
ics f unct ions . The de vic e type is standardi zed by Jedec
and offered by multiple DRAM vendors. Tying the DSF
in put of a n SG RAM l ow mak es th e devi ce op era tes li ke
a stan da r d 32- b it- wi de SDRA M and thu s compat i bl e wi th
the PNX1300 memory interface. PNX1300 is not sup-
porting the new types of SGRAMs that have a DDR inter-
face.
12.5 MEMORY GRANULARITY AND SIZES
PNX 1 30 0 su ppor t s a va r ie ty of mem ory sizes thank s to :
•Many po s si ble co nf ig ur at ions of SD R A M devic es
•Support for up to four memor y ranks
The minimum memory size is 4 MB using two
2×512K×16 SDRA M d ev ices on the 32 -bi t dat a bus, or 2
MB with one of these devices on a 16-bit data bus. Up to
two memory devices can be connected without any glue
logic and without sacrificing performance. The maximum
memory size with full performance is 64MB using two
4×4M×16 SDR AM chip s on a 32- b it dat a bus, and 3 2 MB
usin g one 4×4M×16 SD RAM chip on a 16 -b i t data b u s.
Sev eral memor y confi gur ations can be co nstru cted usin g
mor e d evice s. To do so, the fr equ ency of th e mem ory i n-
Table 12-2. Supported Rank Configurations (32-bit)
Device Size
(Mbit) Device(s) Rank Size
16 2 × 512K × 16 SDRAM 4 MB
2 × 1M × 8 SDRAM 8 MB
2 × 2M × 4 SDRAM 16 MB
64 4 × 512K × 32 SDRAM 8 MB
4 × 1M × 16 SDR A M 1 6 MB
4 × 2M × 8 SDRAM 32b MB
128 4 × 1M × 32 SDRA M 16 MB
1281
1. Limited support fo r a 32-MB c onfi guratio n only.
4 × 2M × 16 SDRAM 322 MB
2. However MM_CONFIG.SIZE may be set to
16MB (i.e. 6). Refer to Figure 12-10 and
Figure 12-11 for the two possible connection
details.
2563
3. Limited support fo r a 64-MB c onfi guratio n only.
4 × 4M × 16 SDRAM 644 MB
4. However MM_CONFIG.SI ZE is 32 MB (i.e. 7 ).
Table 12-3. Supported Rank Configurations (16-bit)
Device Size
(Mbit) Device(s) Rank Size
16 2 × 512K × 16 SDRAM 2 MB
64 4 × 1M × 16 SDRAM 8 MB
128 4 × 2M × 16 SDRAM 161 MB
256 4 × 4M × 16 SDRAM 322 MB
Figure 1 2-1. PNX1 300 internal highwa y bus to the external glueless SDRAM interfa ce.
PNX1300
Memory
Interface
Chip Selects#
Address,
Clock Enabl es,
RAS#, CAS#, WE#
Byte Enables[3:0]
Clock
Data[31:0]
CS#
Address, Control
DQM[3:0]
CLK
DQ[31:0]
33 Ω
SDRAM
Memory
Array
Data
Highway
PNX1300
On-Chip
Peripherals
DSPCPU
1. However MM_CONFIG.S IZE is set to 8 MB (i.e. 5)
2. However MM_CONFIG.SIZE is set to 8 MB (i .e. 5) .
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-3
ter fa ce m ust be l owe red t o accou nt for ext r a pr opa ga tio n
delay due to the excessive loading on t he interface sig-
nals (see Sec tio n 12 . 13 , “Output Driver Capacity”).
Th e fol low in g rules ap ply to me m ory ra nk d es i g n:
•All devices in a rank must be of the same type.
•All ranks m us t be a pow er of two in s ize.
•All ranks must be of equal size.
Table 12-4 lists some examples of 32-bit memory sys-
te m de si gns .
Re fer t o th e T M-1 10 0 Databook f or s mal le r me mo ry co n-
figurations.
Note:
•Some of these configurations may not be economi-
ca ll y attra c tive due t o the p r ic e prem i u m .
•‘Max. MHz’ refers to the memory interface/SDRAM
speed, not the PNX1300 core operating frequency.
The maximum MHz also depends on the device
being used, i.e. PNX1300, PNX1311 or PNX1302.
Refer to S ection 1.9.7.10 on page 1-18 for maximum
oper a ting sp eeds.
Table 12-4 lists some example of 32-bit memory system
designs.
12.6 MEMORY SYSTEM PROGRAMMIN G
Memory system parameters are determined by the con-
tents of two configuration registers, MM_CONFIG and
PLL_RATIOS. Table 12-6 describes the function of
th es e regis ter s, an d Figure 12-2 shows their formats.
To ensure compatibility with future devices, any unde-
fined MMIO bi ts should be ign ored when read.
MM_CONFIG and PLL_RATIOS are loaded from the
boot EEPROM, as descri bed in Section 13.4, “Detailed
EEPROM Contents.” Dur in g th is bo ot pr oce ss , th e m em-
ory interface is held in reset stat e. After t he memory in-
terface is released from reset, the contents of these reg-
isters cannot be altered.
Th es e regis t e rs are visible i n MM IO space . The y ca n be
read, but writes have no effect.
12.6.1 MM_CONFIG Register
The MM_CONFIG register tells the memory interface
how to use the local DRAM memory. The fields in this
register tell the interface the rank size and the refresh
rate of the memory. Table 12-8 summarizes the field
functions.
REFRESH (Refresh interval). The 16-bit REFRESH
field specifies the number of memory-system clock cy-
cles between refresh operations. The default value of
this field is 1000 (0x03E8). See Section 12.11, “Refresh,”
for more information.
BW (Bus Width). If set to ‘0’ then the memory interface
dat a bu s wi dth is 32 bits. If se t to ‘1’ th en the me mory in-
terface data bus width is 16 bits.
SIZE (Rank size). The 3-bit SIZE field specifies the size
of each rank of DRAM. Each rank must be the size spec-
ified by SI ZE. The de fault is a rank size of 4MB. Re fer to
Table 12-7 f or the in te rpre tatio n of th is fi eld.
Table 12-4. E xa m pl es of 3 2- bi t Memo ry Confi gurati ons
Size
(MB) Ranks Rank C onfigurations Max.
MHz Peak
MB/s
8 1 four 2×1M×8 SDRAM 166 664
2two 2×512K×16 SDRAM
two 2×512K×16 SDRAM 166 664
1 one 4×512K×32 SDRAM 183 732
16 1 two 4×1M×16 SDRAM 183 732
1 one 4×1M×32 SDRAM 183 732
2 one 4×512K×32 SDRAM
one 4×512K×32 SDRAM 183 732
24 3 one 4×512K×32 SDRAM
one 4×512K×32 SDRAM
one 4×512K×32 SDRAM
166 664
32 11
1. Howe ver MM_CONFIG.SIZE may be 16 MB (i.e.
6). Refer to Figure 12-10 and Figure 12-11 for
the two possible connection details.
two 4×2M×16 SDRAM 183 732
11four 4×2M×8 SDRAM 166 664
2two 4×1M×16 SDRAM
two 4×1M×16 SDRAM 166 664
2 one 4×1M×32 SDRAM
one 4×1M×32 SDRAM 183 732
4 one 4×512K×32 SDRAM
one 4×512K×32 SDRAM
one 4×512K×32 SDRAM
one 4×512K×32 SDRAM
166 664
48 3 one 4×1M×32 SDRAM
one 4×1M×32 SDRAM
one 4×1M×32 SDRAM
166 664
64 12
2. However MM_CONFIG.S IZE is 32 MB (i.e. 7 ).
two 4×4M×16 SDRAM 183 732
4 one 4×1M×32 SDRAM
one 4×1M×32 SDRAM
one 4×1M×32 SDRAM
one 4×1M×32 SDRAM
166 664
Table 12-5. Sup por t ed 16 -bit Memor y Conf igura tio ns
Size
(MB) Ranks Rank Config urations Max.
MHz Peak
MB/s
8 1 one 4×1M×16 SDRAM 183 732
161
1. However MM_CONFIG.S IZE is set to 8 MB (i.e. 5)
1 one 4×2M×16 SDRAM 183 732
322
2. However MM_CONFIG.S IZE is set to 8 MB (i.e. 5)
1 one 4×4M×16 SDRAM 183 732
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-4 PRELIMINARY SPECIFICATION
12.6.2 PLL_RATIOS Register
The P LL_RATIOS register controls the operation of the
s epar ate memo r y-in t erf ac e an d CP U PLLs. Fiel ds in t his
register determine if the PLLs are active and what in-
put:output ratio each PLL should generate. Table 12-8
summarizes the field functions. Figure 12-3 shows how
the PLLs are connected and how fields in the
PLL_RATIOS register control them. For normal opera-
Table 12-6. Memory Configuration Registers
Register Purpose
MM_CONFIG Describes external memory configuration
PLL_RATIOS Con tro ls se parat e mem ory and CPU P LLs
(phase-locked loops)
Table 12-7. MM_CONFIG Fields
Field Function
REFRESH Ref r esh interval in memory clock cyc les.
Default value 1000 (0x03E8).
SIZE Memory rank size 0 Reserved
1 512KB
21MB
32MB
44MB
58MB
6 16MB
7 32MB
Fig ure 12-2. Memory interface configuration registers.
31 0
MM_C ON FIG ( r/o) 423SIZE
PLL_RATIOS (r/o) CR
REFRESH
19
31 04237
SDRAM PLL Bypass
SDRAM PLL Disable
CPU PLL Bypass
CPU PLL Disable
SDRAM Ratio
CPU Ratio
56
SB SD CB CD SR
0x10 0100
MMIO_base
offset:
0x10 0300
16-bit memory interface
BW
Table 12-8. PLL_RATIOS Fields
Field Function
CR CPU:memory ratio 01:1
12:1
23:2
34:3
45:4
5–7Reserved
SR Memory :exter nal ratio 02:1
13:1
CD CPU PLL Disable 0CPU PLL on
1CPU PLL off
CB CPU PLL bypass 0CPU ← PLL
1CPU ← Memory
SD SDRAM PLL Disable 0SDRAM PLL on
1SDRAM PLL off
SB SDRAM PLL bypass 0Memory ← PLL
1Memory ← external
Figur e 12-3. PNX1 300 memory and co re PL L connections.
Memory System
PLL DSPCPU PLL
CR
0423756
SD SB CD CB SR PLL_RATIOS Register
PNX1300
Core
Clock
PNX1300
TRI_CLKIN
MM_CLK1
MM_CLK0
External Clock Input
Memory Sy stem Cloc ks TO DDSes && EV O PLL
x3, x9
PNX1300
Peripheral
Clocks
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-5
tion Both PLLs must be activated, i.e. {CD,CB,SD,SB}
must be equal to 0000 (binary value).
Th e ope ra t in g lim i ts of the interna l PLL s are:
•27 M H z < Output of t h e SD RA M PL L < 200 M Hz
•33 M H z < Ou tp ut of t h e CPU PLL < 26 6 MH z
These are not the speed grades of the chips, just the PLL
limits.
CR (CPU-to-memory PLL ratio). The 3-bit CR field se-
lect s on e of five inp ut-t o-out pu t cl oc k rati os f or th e C PU
PLL. The input clock is the memory system clock; the
output clock determines the PNX1300 core operating fre-
quency. The default value is ‘0’, which implies a 1:1
CPU:memory ratio. See Table 12-8 for other encoding.
SR (Mem ory-t o-exter nal PL L rati o). Th e 1-bit S R fie ld
selects one of two memory-to-external clock ratios for
the memory interface PLL. The PLL input is PNX1300’s
external input clock TRI_CLKIN; the PLL output deter-
mines the operating frequency of the memory interface
and S DRAM d evic es. T he defau lt value is ‘0’, which im-
plies a 2:1 memory:external rat io. A value of ‘1’ implies a
3:1 ratio.
CD (CPU PLL disable). The 1 -bit C D field determines
wh ether or no t th e CPU PL L is tur ned o n. The r eset value
is ‘1’, which disables operation of the CPU PLL and dis-
sipates almost no power. For normal operation the value
should be ze ro, enabling the CPU PLL.
CB (CPU PLL bypass). The 1-bit CB field determines
whether the input or the output of the CPU PLL drives
PNX1300’s core logic. The default value is ‘1’, which
caus e s the PN X130 0 c ore to be cl oc ked b y t he input of
the CPU PLL (i .e ., the m emory inte rfa c e clo c k). A value
of ‘0’ causes nor mal op erat ion, and th e cor e is c locked b y
the output of the CP U PLL.
Note that if both CB and SB are set to ‘1’ (bypass the
CPU PLL and the SDRAM PLL), PNX1300’s core logic is
effectively clocked at the external input frequency.
Note: it is illegal to use the output of a disabled PLL. For
example, it is illegal to have CD set to ‘1’ while CB is set
to ‘0’.
SD (SDRAM PLL disable). The 1-bit SD field deter-
mines whether or not the SDRAM PLL is turned on. The
defaul t value is ‘1’, which disables the SDRAM PLL. In
this state, it dissipates almost no power. For normal op-
eration the value should be ‘0’, enabling the SDRAM
PLL.
SB (SDRAM PLL bypass). The 1-bit SB field deter-
min es whe th er t h e i npu t or t he output of the S DRAM PLL
drives the memory interface and memory devices. The
default value is ‘1’, which causes the memory system to
be cloc k ed by th e i np ut of th e S DRAM PLL (PNX13 00 ’s
external input clock). A value of ’0’ causes normal oper-
ati on, and the me mory sys tem is cloc ked by the output of
the SDRAM PLL.
12.7 MEMORY INTERFACE PIN LIST
Th e mem ory inter fac e co nsis ts of 6 1 sign al pi ns in clud -
ing clocks (but excluding power and ground pins).
Table 12-9 l is ts th e inter f ace si gnal pins .
12.8 ADDRESS MAPPING
The address ma pping is determined by the state of the
rank-size bits and the bus width bit in the MM_CONFIG
register.
12.8.1 Address Mapping in 32-bit mode
Table 12-10 shows how internal address bits from the
PN X13 00 d ata h ig hwa y bus are ma pp ed to ma in -me mo-
ry address-bus and chip select pins (MM_A[13:0],
MM_CS#[3:0]) in 32-bit data bus mode.
The column “Rank A ddr./H . Way B its” specifies which in-
ternal data-highway address bits select the preliminary
SDRAM rank. The actual rank used is subject to the lim-
it at io n im pli ed by the relationship between SDRAM aper-
ture size (described in Section 13.2.1) an d th e ran k si ze.
Table 12-9. Memory Interface Signal P ins
Name Function I/O Active...
MM_CLK[1:0] Memory bus clock O High
MM_CS#[3..0] Chip selects for the four
m emory ranks or Address O Low
MM_RAS# Row-address strobe O Low
MM_C AS# Column addr es s s tr obe O Low
MM_WE # Wr ite enable O Low
MM_A[13:0] Address O High
MM_ C K E[1:0] Clock ena ble O Hig h
MM_D QM[3:0 ] Byte enables for dq b us O Hi gh
MM_D Q[31:0] Bi-direc tio nal data bus I/O High
Table 12-10. 32-bit Address Mapping
Rank
Size
Rank
Addr. Row
Address Column
Address Bank
Address
H.Way
Bits Pins H.Way
Bits Pins H.Way
Bits Pin H.Way
Bit
4 MB 23–22 10–021–11 7–010–6,
4–211
5
8 MB 24- 23 12,
10–011,
22–12 12,
8–0
11,
11–6,
4–211
16 MB 25-24 13-12
10–012-11,
23–13 12,
9–0
11,
12–6,
4–211
32 MB –
CS#3
CS#2
13-12
10–0
25,
24,
12-11,
23–13
CS#3,
CS#2,
12
9–0
25,
24,
11,
12–6,
4–2
11
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-6 PRELIMINARY SPECIFICATION
The rank is selected via the chip select bits,
MM_CS#[3:0].
The column “Row Addr ess/H.Way B its” specifies which
internal data-highway address bits map to the SDRAM
row address. “Row Address/Pins” specifies which lines
of P N X1300’s MM_A address bus serve as the SDRAM
row address. For the 32 MB ranksize the chip selects
may be used as row address.
The column ‘Column Address/H.Way Bits’ specifies
wh ich da ta-hi ghway add ress bits map to the SDRAM co l-
umn address. ‘Column Address/Pins’ specifies which
lines of PNX1300’s MM_A address bus serve as the
SDRAM column address. For the 32 MB ranksize the
chip selects may be used as column address.
MM_A[12] is only defined for a 8- or 16-MB rank size.
MM_A[12] contains H.Way bit 11 during the RAS and
CAS op erati ons. MM_A[1 2] ca n be us ed as a bank select
(4-bank SDRAMs) or as a Row address (two bank
SDRAMs).
MM_A[13] is only defined for a 16-MB rank size.
MM_A[ 1 3] contains H .Way bit 12 during t he R A S op era-
tion. MM_A[13] can only be used as a Row address.
For the 32 MB ranksize the chip selects MM_CS#[3:2]
pins are used as addresses. MM_CS#2 is used as a
bank select in addition to MM_A[11] and MM_CS#3 is
used as a row address.
Highway address bits 5–0 are the offset within a 64-byte
block. All ‘0’ for an aligned block transfer. Table 12-8 lists
th e m a pp in g of bits 5–2 to identify in which SDRAM po-
sitions the words of a block are located. Bit 5 is always
mapped to (one of) the SDRAM internal bank selects;
th us, ea ch SD RAM ban k rece ives half (32 by tes) of th e
block transfer.
Highway address bits 4–2 are the w ord off set in a cache
block. Bits 1–0 are the byte offset within a 32-bit word.
12.8.2 Address Mapping in 16-bit mode
Table 12-11 shows how internal address bits from the
PN X13 00 data h ig hwa y bu s are ma pp ed to ma in- me mo-
ry address-bus and chip select pins (MM_A[13:0],
MM_CS#[3:2]) in 16-bit data bus mode.
1 2.9 M EM OR Y I N TERF AC E AN D SD R AM
INITIALIZATION
Imme diat ely after res et, th e main -me mory in ter face is in i-
tialized by placing default values in the MM_CONFIG
and P L L_ R A T IO S regis t e rs ( s ee Sec ti on 12 .6, “Memory
System Programming”). During the subsequent hard-
ware boot process, when PNX1300 reads initial values
fro m a n ex ter n al R OM , these r eg is te r s can be set to di f-
ferent values.
After PNX1300 is released from the reset state, the
memory interf a ce auto ma t ically e x ecutes 10 refr esh op-
erations, then initializes the mode register in each
SDRAM chip. Table 12-12 shows the settings in the
SDRAM mode register(s).
12.10 ON-CHIP SDRAM INTERLEAVING
The main-memory interface (MMI) takes advantage of
the on-chip interleaving of SDRAM devices. Interleaving
allows the precharge, RAS, and CAS commands needed
to a cce ss one i nter n al bank t o be perf or me d whi le use ful
data transfer is occurring with the other internal bank.
Thus, the overhead of preparing one bank is hidden dur-
ing data movement to or from the oth er.
The benefit of on-chip interleaving is sustainable full-
bandwidth data transfer (1 word per clock cycle). The
tr an siti o n f rom on e i nter n al ba nk to the othe r ha ppen s o n
8-wo rd boun dar ies; t ransferring 8 word s giv es t he in ac-
tive b a nk t ime to prepare (perf orm precha rge, RAS, and
CAS ) so t hat w hen the las t wo rd of the 8- wor d bl ock in
the active bank has been transferred, the next word from
the just-precharged bank is ready on the next cycle .
The seamless transitions between the two on-chip banks
can be sus tain ed f or a st ream of co nt iguo us a ddr ess es
with the same directi on (read or writ e). That is, a str eam
of co nt iguous read s or c on ti g u ou s w rites ca n su stain full
bandwidth. If a write fol lows a read, then a small gap be-
tween transfers is needed.
Each ban k ac cess i s termi nated w ith a read or write with
automatic precharge, making a separate precharge com-
mand befor e th e ne xt R A S unnece s sa r y.
Fo r 4 bank s SDR AM de v ices , the si gn als us ed as bank
addresses are interchangeable (i.e. it does not matter
which of the two signals is connected to Bank 1 or Bank
0 of the SD R A M dev i ce).
12.11 REFRESH
The MMI perf orms SDR AM ref resh cycl es auto no mou sly
using the CAS-before-RAS (CBR) mechanism. SDRAMs
have a 4K re fr es h i nter v al : either 409 6 r o w s must be r e -
Table 12-11. 16-bit Address Mapping
Rank
Size
Rank
Addr. Row
Address Column
Address Bank
Address
H.Way
Bits Pins H.Way
Bits Pins H.Way
Bits Pins H.Way
Bit
2 MB –9–020–11,5 7–010–6,
3–111 4
8 MB –
CS#3,
CS#2,
13–12,
10–0
24,
23,
12–11,
22–13,5
CS#3,
CS#2,
12,
8–0
24,
23,
11,
11–6,3–1
11 4
Table 12-12. SDRAM Mode Register Settings
Parameter Value
Bur st length 4
Wrap type Inter leaved
CAS latency 3
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-7
freshed every 64 ms or 2048 rows every 32 ms or one
row every 15.62 µsec. New SDRAM devices (i.e. 256
Mbit generation s uppo r t an 8K re fr es h interval, t herefor e
one r ow every 7 .8 1 µsec.
The MMI performs refresh at timed intervals: one CBR
refresh command must be issued every 15.6 µs or eve ry
7.81 µs ec. A counter in the MMI keeps t rac k of the num-
ber o f SD R AM c lock cyc les b etw een r efr es h ope r ations .
Thi s co un ter star t s aft er t he CBR oper at io n has co mpl e t-
ed; this C BR op era t ion t ak e 1 9 cycl es . Wh en th e c ou nter
rea che s a p rog ramm e d lim it, t he next re fres h op erat ion
is due, and the next-in-line data transfer request from the
dat a-highway is delay ed until the C B R op erati on is exe -
cuted.
All devices in the mai n- memory system are r efreshed si-
mult an eous ly. T he R EFRE SH fi eld in th e MM _CON FIG
register determines the number of memory-system clock
cycles (as distinguished from PNX1300 core clock cy-
cles) bet w ee n the C BR ref res h oper a ti ons.
Ea ch C BR ref r es h o pe r at io n t a ke s 19 SD R AM cl oc k cy -
cles. Th us, at 10 0-MHz , refr esh co nsumes about 1.2 % of
maximum available SDRAM bandwidth (19 cycles out of
1560). The bandwidth impact is slightly lower at higher
frequencies.
Table 12-13 lists the number of memory-system clocks
for typical SDRAM operation speeds with a 15.62 µs re -
fresh period. This number includes the worst case sce-
nario in order to guaranty the 15.62 µs ref r es h per io d.
Table 12-14 lists the number of memory-system clocks
for typical SDRAM operation speeds with a 7.81 µs re-
fresh period.This number includes the worst case sce-
nario in order to guaranty the 7.81 µs refresh period.
12. 12 P OWE R-DOWN M ODE
Wh en PN X130 0 is p ut i nt o po w er- d own m ode to r e du ce
power consumption, the MMI responds by putting the
SDRAM devices into their power-down mode. In this
mode, the SDRAM devices retain their contents through
self-refresh.
12.13 OUTPUT DRIVER CAPACITY
PNX1300’s ou tput driv er ci rcu it s for t he memory ad dres s
and control signals (output signals in Table 12-9), can
drive up to two memory devices when the memory inter-
face is operating at 183 MHz. If more devices are con-
nected, then a lower SDRAM clock frequency must be
chosen.
Table 12-15 lists the clock frequency as a function of the
number of memory devices connected to unbuffered
memory interface signals.
Tw o identi cal out puts are pr ovid ed for bot h the MM_ CKE
(clock-enable) and MM_CLK signals. Each MM_CKE
and MM_CLK signal is capable of driving one SDRAM
devices at 183 MHz.
12.14 SIGNAL PROPAGATION DELAY
COMPENSATION
The PNX1300 MMI no longer has the two special pins,
MM_MATCHOUT and MM_MATCHIN, that were used in
the TM-1100 and TM-1000. This loop helped the inter-
face compensate for the propagation delay through cir-
c uit- boa r d tr ac es to a nd fr om th e e xt ern al SDRA M d evic-
es. It is now integrated into the MMI. Read timing is
internally deriv ed.
To avoid excessive ringing of the clock signals, series
ter m in atio n wi t h a 33-oh m r es isto r is advi se d at t h e cloc k
outputs.
The dela y of the memo ry clock with respect to the inter-
nal sending and receiving clocks is adjusted inside the
memory interf ace t o achieve reliable communi cation and
guar an t ee c or r e ct setup an d ho ld time s.
Figure 12-4 shows a conceptual circuit board layout.
Two SDRAM devices share a single clock output. The
c lock sign als should have sour ce-series termination.
12.15 CIRCUIT BOARD DESIGN
PNX13 00 and i ts memo ry ar ray for m a high -spe ed digit al
system. Even though only a small number of chips is in-
volv ed, this digi tal system op erates at fre quencies high
enough to make the analog characteristics of the con-
nections between the chips significant. Consequently,
the system designer must take care to ensure reliable
operation.
12.15.1 General G uidelines
•In general, PNX1300 and its memory chips must be
as close together as possible to minimize parasitic
Table 12-13. REFRESH value for a 15.62 µ
µµ
µs period
SDRAM Operation Speed Value For RE FR ESH Field
(decimal, hexadecimal)
100 MHz 1523, 05F3
125 MHz 1914, 0779
133 MHz 2038, 07F6
143 MHz 2195, 0892
166 MHz 2554, 09F9
183 MHz 2819, 0B03
Table 12-14. REFRESH value for a 7.81 µ
µµ
µs pe r iod
SDRAM Operation Speed Value For RE FR ESH Field
(decimal, hexadecimal)
100 MHz 742, 02E6
125 MHz 936, 03A9
133 MHz 992, 03E7
143 MHz 1072, 0435
166 MHz 1256, 04E9
183 MHz 1384, 05E6
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-8 PRELIMINARY SPECIFICATION
capacitance. Close proximity is especially important
for a 1 8 3-M H z mem ory sy s tem .
•Signal traces between PNX1300 and the memory
chips must b e matched in le ngth as closely as possi-
ble to mi ni m i ze si gnal skew.
•The clock-signal trace(s) must be as short as possi-
ble.
•Address and control-signal traces should also be
short, but their length is less critical than the clock’s.
•Data-signal traces should also be short, but their
length is less critical than the clock’s, especially if
only one or two ranks are connected.
•Connections to several loads must follow a “T” con-
nection scheme in order to limit the reflections.
12.15. 2 Speci fic Guidelines
•The maximum length for a signal trace should be
10cm. For 183-MHz operation, signal trace length
mu st no t be lo ng er than 7c m .
•The maximum capacitive load is 30 pF per trace,
including loads.
•The signal traces on the PNX1300 circuit board must
be designed as 50-ohm transmission lines .
•At most one SDRAM device may be connected to
each MM _C LK s ig nal at 183 MH z .
12.15.3 Termination
No termination is required for address, dat a, and control
sign als. Addre ss and c ontrol signals are dr iven on ly by
PNX1300; the output impedance of the drivers is suffi-
ciently matched to prevent excessive ringing. PNX1300
design assumes that when driving data lines, the output
drivers of SDRAM chips are also sufficiently impedance
matched.
Ser ies te r min ati on of the cl ock out pu t s with a 33- o hm re-
sistor is advised.
12.16 TIMING BUDGET
The gl ueless interface of the PNX1300 main - m emory in-
terface makes the mem ory system si mple and straight-
for wa r d fro m on e po in t of view, but to ens ure re li able op-
eration at high clock rates, system designers must follow
the board design guidelines (see S ec tion 12 .15, “Circuit
Board D e sign”).
SDR AM devices must meet the critical specifications li st -
ed in Table 12-16 to ensure reliable ope rati on of an 143-
MHz (Tcycle = 7 ns) memory system.
For a 166 MHz operation, SDRAM devices must meet
th e critic a l s pec ifi cati ons li sted in Table 12-17 to ensu re
Table 12-15. Glueless interface limits for address/
clocks
Mem ory Chips Maximum Clock F re quency
2 183 MHz
4 166 MHz
8133 MHz
Fig ure 12-4. Conceptual board layout.
Address
&
Control
CLK
DQ[31:0]
33 Ω
Address
&
Control
CLK
DQ[31:0]
SDRAM
Device
SDRAM
Device
PNX1300
Memory
Interface
Address,
Clock Enables,
RAS#, CAS#, WE#
Clock
Data[31:0]
Data
Highway
PNX1300
On-Chip
Peripherals
DSPCPU
Table 12-16. Critic al 143-MHz SDRAM parameters
Timi ng Param eter Value
Max. output delay tAC 6. 4 ns
Min. output hold time tOH 2. 0 ns
Max. input setup time tIS 2. 0 ns
Max. input hold time tIH 1.0 ns
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-9
reliab le operation of an 1 66- M H z (Tcycle = 6 ns) memo r y
system.
For a 183 MHz operation, SDRAM devices must meet
the cr itic al sp ecifica ti ons list ed in Table 12-18 to ens ure
rel iabl e o pe r ation of an 183- MH z ( Tcycle = 5.4 ns) mem-
ory system.
These values leave virtually no margin for the critical tim-
ing pa ra meters in a hi g h- speed sys tem and ass ume a to-
tal worst cas e dela y fro m 0.6 n s to 0.4 ns (Fr om 143 MHz
to 183 MHz operating frequency the trace layout must be
impr oved to reduce trace delay as well as sk ew) and a
TSU for PNX1300 of 0 ns.
Th e max imum oper ati ng freq ue ncy i s usu ally comp ut ed
with the following equation: .
Where TCS is the skew between MM_CLK0 and
MM_CLK1, and TSU the input data setup time as defined
in Section 1.9.7.10 on page 1-18, and Tboard includes
tra ce delay and trace skew.
12.16.1 Main AC Parameter requirements
The PNX1300 SDRAM interface was designed to sup-
port a wide range of SDRAM vendors. Table 12-19, de-
scribes some of the minimum SDRAM AC requirements
for PNX130 0 to oper ate corre ctl y. The symb ols o r name s
are not really standardized and may di ffer from one ven-
dor to another one. The table is not meant to be exhaus-
tive and shows only the main parameters. Parameters
are expressed in clock cycles rather than n s.
1 2.1 7 EX A MPL E BL O CK DIAGR AMS
Th e following fi gures illus t rate some of t he memory co n -
fig urati ons th at can be built wi th PNX 130 0. For al l the m
the signals used as bank addresses, are interchange-
able (i.e . it does n ot matter wh ich of the two signals is
connected to Bank 1 or Bank 0 of the SDRAM device).
12.17. 1 Block Diagrams for a 32-bit interface
The following sections present examples of possible
c onnect ions with 16-, 64-, 128- a nd 256 Mbit SDR AMs .
MM_CONFIG.BW must be set to ‘0’ (refer to bw,
Section 12.6.1).
12.17. 1.1 16-Mbit Devices or Less
Th ese de vic es all ow sma ll mem or y conf igur atio ns to be
built . They a r e de sc ribed i n mo re details in the TM - 10 00
and T M -11 00 Da ta bo ok s .
Table 12-17. Critical 166-MHz SDRAM parameters
Timing Parameter Value
Max. output delay tAC 5.5 ns
Min. output hold time tOH 2. 0 ns
Max. input setup time tIS 1.5 ns
Max. input hold time tIH 1.0 ns
Table 12-18. Critical 183-MHz SDRAM parameters
Timing Parameter Value
Max. output delay tAC 5.0 ns
Min. output hold time tOH 2. 0 ns
Max. input setup time tIS 1.5 ns
Max. input hold time tIH 1.0 ns
Tcycle tAC Tboard TCS TSU
+++≥
Table 12-19. Minimum AC Parameters
Description Symbol Clocks
ACTIVE command period tRC 10
ACTIVE to PRECHARGE command tRAS 7
PRECH ARGE com mand peri od tRP 3
ACTIVE Bank A to A CTIVE bank B tRRD 3
ACTI VE to RE AD or W R ITE command tRCD 3
WRITE recovery time tWR 2
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-10 PRELIMINARY SPECIFICATION
12.17. 1.2 64-Mbit Devices
64- M bit SDRAM S or ga nized in x 32 c an be used to build
an 8-, 16-, 24-, or 32-MB memory system. Figure 12-5
shows an 8-MB memory system (one device only) and
Figure 12-6 det ails an extension of t he block diagram in
order to build a 16-MB configuration.
DQ[31:0]
DQM[3:0]
CLK
Address[10:0]
Control
CS#
4×512K×32
SDRAM
MM_CS#[0]
MM_CLK[0]
BA[1:0]
Figur e 12-5. Sc hem a t ic of a 8 -M B mem or y sy ste m co nsist ing of one 4×512K×32 SDR A M (one r a nk).
PNX1300
MM_CS#[0]
MM_RAS, CAS, WE#, CKE
MM_A[10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
33 Ω
MM_A[12,11]
DQ[31:0]CLK
Address[10:0]
Control DQM[3:0]
CS#
4×512K×32
SDRAM
MM_CS#[0]
MM_CLK[0]
MM_DQM[3:0]
MM_DQ[31:0]
DQ[31:0]CLK
Control DQM[3:0]
CS#
MM_DQM[3:0]
MM_DQ[31:0]
MM_CS#[1]
MM_CLK[0]
33 Ω
4×512K×32
SDRAM
BA[1:0]
BA[1:0]
Address[10:0]
MM_CS#[1:0]
MM_RAS#, CAS#, WE#, CKE
MM_A[10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_A[12,11]
Figure 12-6. Schematic o f a 16-MB memory system consisting of two ranks of 4 ×512K×32 SDRAM chips.
PNX1300
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-11
64-Mbit SDRAMs organized in x16 can be used to build
a 16-, 32-, 48- or 64-MB memory systems. Figure 12-7 details a 32-MB memory system. Re moving the devi ce
c ont rolled by MM_CS #[1] makes a 1 6 -M B system.
Figure 12-7. Schematic of a 32-MB memory system consisting of four 4×1M×1 6 SDRAM chips (two ranks)
MM_CS#[1:0]
MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CS#[1]
MM_CLK[1] MM_DQ[31:16]
MM_DQ[15:0]
MM_CS#[1]
MM_CLK[0]
MM_DQ[31:16]
MM_DQ[15:0]
MM_CS#[0]
MM_CS#[0]
MM_CLK[1]
MM_CLK[0]
33 Ω
MM_DQM[1:0]
MM_DQM[3:2]
MM_DQM[3:2]
MM_DQM[1:0]
PNX1300
MM_RAS, CAS, WE#, CKE
DQ[15:0]CLK
Control DQM[1:0]
CS#
4×1M×16
SDRAM
BA[1:0]
Address[11:0]
MM_A[12,11]
DQ[15:0]CLK
Control DQM[1:0]
CS#
4×1M×16
SDRAM
BA[1:0]
Address[11:0]
DQ[15:0]CLK
Control DQM[1:0]
CS#
4×1M×16
SDRAM
BA[1:0]
Address[11:0]
DQ[15:0]CLK
Control DQM[1:0]
CS#
4×1M×16
SDRAM
BA[1:0]
Address[11:0]
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-12 PRELIMINARY SPECIFICATION
64-Mbit SDRAMs organized in x8 devices could b e used
to build a 32-MB memory system as illustrated in
Figure 12-8. Note that due to the unu sual way of using
the devic es , i t is the on l y sup po rte d co nfi gu rat io n wit h x8
devi ces. MM_CONFIG.SIZE must be set to 6 (i.e. 16-MB
rank si ze, Section 12.6.1).
Figure 12-8. Schematic of a 32-MB memory system consisting of four 4×2M×8 SDRAM chips (on e rank)
MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[1] MM_DQ[31:24]
MM_DQ[23:16]MM_CLK[1]
MM_DQ[15:8]
MM_DQ[7:0]
MM_CLK[0]
MM_CLK[0]
33 Ω
MM_DQM[2]
MM_DQM[3]
MM_DQM[1]
MM_DQM[0]
PNX1300
MM_RAS, CAS, WE#, CKE
DQ[7:0]CLK
Control DQM]
4×2M×8
SDRAM
BA[1:0]
Address[11:0]
MM_A[11]
MM_CS#[1]
DQ[7:0]CLK
Control DQM
4×2M×8
SDRAM
BA[1:0]
Address[11:0]
DQ[7:0]CLK
Control DQM]
4×2M×8
SDRAM
BA[1:0]
Address[11:0]
DQ[7:0]CLK
Control DQM]
4×2M×8
SDRAM
BA[1:0]
Address[11:0]
CS#
GND
CS#
GND
CS#
GND
CS#
GND
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-13
12.17. 1.3 128-Mbit Devices
128-Mbit SDRAMs organized in x16 are partially sup-
por ted . The su ppor t is prov ided for a 32 -MB mem ory s ys-
tem. I t can on ly contain one r ank ( i.e. it canno t be ext end-
ed using the other MM_CS# pins). There are two
possible connection schemes.
Figure 12-9 is backward compatible with TM-1300.
MM_CONFIG.SIZE must be set to 6 (i.e. 16 MB rank
size, Section 12.6.1).
Figure 12-9. Schematic of a 32-MB memory system consisting of two 4×2M×16 S D RA M ch ips (one r ank)
MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[0] MM_DQ[31:16]
MM_DQ[15:0]MM_CLK[1]
33 Ω
MM_DQM[1:0]
MM_DQM[3:2]
PNX1300
MM_RAS, CAS, WE#, CKE
DQ[15:0]CLK
Control DQM[1:0]
4×2M×16
SDRAM
BA[1:0]
Address[11:0]
MM_A[11]
MM_CS#[1]
DQ[15:0]CLK
Control DQM[1:0]
4×2M×16
SDRAM
BA[1:0]
Address[11:0]
CS#
GND
CS#
GND
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-14 PRELIMINARY SPECIFICATION
Figure 12-10 is not backward compatible with TM-1300.
MM_CONFIG.SIZE must be set to 7 (i.e. 32 MB rank
size, Section 12.6.1). This new scheme ha s the advan-
tage of bei ng com patible w ith the Figure 12-12. This al-
lows to build a system that receives 32- or 64-MB mem-
ory syste m wi th t he exact same footprint.
Figure 12-10. Schematic of a 32-MB memory system consisting of two 4×2M×16 SDRAM chips (one rank)
MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[0] MM_DQ[31:16]
MM_DQ[15:0]MM_CLK[1]
33 Ω
MM_DQM[1:0]
MM_DQM[3:2]
PNX1300
MM_RAS, CAS, WE#, CKE
DQ[15:0]CLK
Control DQM[1:0]
4×2M×16
SDRAM
BA[1:0]
Address[11:0]
MM_A[11]
MM_CS#[2]
DQ[15:0]CLK
Control DQM[1:0]
4×2M×16
SDRAM
BA[1:0]
Address[11:0]
CS#
GND
CS#
GND
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-15
128-Mbit SDRAMs organized in x32 can be used to build
16-, 32- , 48- or 64-MB memory systems. A 32-MB sys-
tem is pictured in Figure 12-11. A 16-MB system can be
obtained by removing the device controlled by
MM_CS#[ 1]. S imilar ly it can be extended to 48- or 64-MB
by adding devices controlled by MM_CS#[3:2].
DQ[31:0]CLK
Address[11:0]
Control DQM[3:0]
CS#
4×1M×32
SDRAM
MM_CS#[1:0]
MM_RAS#, CAS#, WE#, CKE
MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CS#[0]
MM_CLK[1]
MM_DQM[3:0]
MM_DQ[31:0]
DQ[31:0]CLK
Control DQM[3:0]
CS#
MM_DQM[3:0]
MM_DQ[31:0]
MM_CS#[1]
MM_CLK[0]
33 Ω
MM_A[12,11]
4×1M×32
SDRAM
BA[1:0]
Fig ure 12-11. Schematic of a 32-MB memory system co nsisting of two ranks of 4×1M×32 SDRAM chips.
BA[1:0]
Address[11:0]
PNX1300
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-16 PRELIMINARY SPECIFICATION
12.17. 1.4 256-Mbit Devi ces
256-Mbit SDRAMs organized in x16 can be used to build
a 64-MB memory systems. Figure 12-12 deta i ls a 64- MB
memory system. MM_CONFIG.SIZE must be set to 7
(i.e. 32-MB rank size, Section 12.6.1).
Note the connections described in Figure 12-12 fo r t he
256- M bit S D R A M s organ ized in x16 ca n also be us ed to
connect the 128-Mbit SDRAM devices organized in x16
allowing the same footprint on the board for two different
memory size configurations (i.e. 64 MB or 32 MB). Refer
to Figure 12-10 for detailed connection of the 32-MB
case.
Figure 12-12. Schematic of a 64-MB memory system consisting of two 4×4M×1 6 SDRAM chips (one rank)
MM_CS#3, MM_A[13,10:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[0] MM_DQ[31:16]
MM_DQ[15:0]MM_CLK[1]
33 Ω
MM_DQM[1:0]
MM_DQM[3:2]
PNX1300
MM_RAS, CAS, WE#, CKE
DQ[15:0]CLK
Control DQM[1:0]
4×4M×16
SDRAM
BA[1:0]
Address[12:0]
MM_A[11], MM_CS#2
DQ[15:0]CLK
Control DQM[1:0]
4×4M×16
SDRAM
BA[1:0]
Address[12:0]
CS#
GND
CS#
GND
Philips Semiconductors SDRAM Memory System
PRELIMINARY SPECIFICATION 12-17
12.17. 2 Block Diagrams for a 16-bit interface
The following figures (i.e. Figure 12-13, Figure 12-14
and Figure 12-15) detail the SDRAM connections for the
64- , 128- an d 256 -Mb it SDRA Ms orga ni ze d in x16. The y
respectively build a memory system of 8-, 16- or 32-MB.
MM_CONFIG.SIZE must be set to 5 (i.e. 8-MB rank size,
Section 12.6.1) for all of the pictured configurations.
MM_CONFIG.BW must be set to ‘1’ (refer to bw,
Section 12.6.1).
Note the connections described in Figure 12-15 for the
256-Mbit SDRAM device organized in x16 can also be
used to con nect a 12 8-Mb it SD R A M device o rganize d in
x16, Figure 12-14, allowing the same footprint on the
board for two different memory size configurations (i.e.
32 MB or 16 MB).
Figure 12- 13. Schematic of a 8-MB memory system consisting of one 4×1M×16 SDRAM c hips (one rank )
MM_CLK[0] MM_DQ[15:0]
MM_DQM[1:0]
DQ[15:0]CLK
Control DQM[1:0]
4×1M×16
SDRAM
BA[1:0]
Address[11:0]
CS#
GND
MM_A[13,10:0]
MM_CLK[0]
MM_DQ[31:0]
MM_DQM[3:0]
33 Ω
PNX1300
MM_RAS, CAS, WE#, CKE
MM_A[12,11]
F igur e 1 2-14 . Schema t ic of a 16- MB me mo r y sy stem consist i ng of o ne 4×2M×16 SDRAM chips (one rank)
MM_A[13,10:0]
MM_CLK[0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[0] MM_DQ[15:0]
33 Ω
MM_DQM[1:0]
PNX1300
MM_RAS, CAS, WE#, CKE
MM_A[11], MM_CS#2
DQ[15:0]CLK
Control DQM[1:0]
4×2M×16
SDRAM
BA[1:0]
Address[11:0]
CS#
GND
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
12-18 PRELIMINARY SPECIFICATION
F igur e 1 2-15 . Schema t ic of a 32- MB me mo r y sy stem consist i ng of o ne 4×4M×16 SDRAM chips (one rank)
MM_CS#3,MM_A[13,10:0]
MM_CLK[0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CLK[0] MM_DQ[15:0]
33 Ω
MM_DQM[1:0]
PNX1300
MM_RAS, CAS, WE#, CKE
MM_A[11], MM _CS#2
DQ[15:0]CLK
Control DQM[1:0]
4×4M×16
SDRAM
BA[1:0]
Address[12:0]
CS#
GND
PRELIMINARY SPECIFICATION 13-1
System B oot Chapte r 13
by Gert S laven burg, Bob Brad field, and Hani Salloum
13.1 BOOT SEQUENCE OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
Before a PNX1300 system can begin operating, the
main-memory interface (MMI) registers and on-chip
clock ratio register must be configured. Since the
DSPCPU cannot begin operating until after these regis-
ters and circuits are initialized, the DSPCPU cannot be
relied on to initialize these resources. Consequently,
PNX1300 needs an independent bootstrap facility for
low -leve l in iti ali z ation .
PNX1300 implements low-level system initialization by
combin ing a small bl ock of on-c hip sys tem bo ot l ogic with
a sing le exter nal s erial boot E E PROM connected to the
I2C in t erf ac e. See Figure 13-1. Serial EEPROMs with an
I2C inter f ac e ar e s lo w but have the ad vantag es of b eing
s pace- e ffi ci en t an d inex pe ns ive . The amount of info rma-
tion needed f or initial system boot i s small, s o speed is
not a concern.
The PNX1300 system boot block performs differently for
each of two major types of PNX1300 system, distin-
guished by host-assisted and autonomous bootstrap-
ping. The most significant bit of the tenth byte in the ex-
ternal EEPROM determines the system boot procedure
and mus t mat ch th e sy s t em co nf i gu r at io n.
In ho st -as s is ted bo otst rapping, a PNX1300 device is in-
tegrated into a system where some other processor
serves as the host. For example, a PNX1300 chip might
be p art of a PCI card in a standard person al compu ter
(P C) . In th is case , the P NX 1300 sy st em boot on ly need s
to load enough information from the serial EEPROM to
configure the on-chip timing circuits and MMI; the host
pro c esso r can pe rform all othe r PN X1300 s etu p ch ores.
In t he seco nd typ e of syst em, aut onomo us boot stra ppin g
takes place. In this configuration, a PNX1300 device
serves as the host ( main) processor; consequently, the
PNX1300 system boot must perform more work. In addi-
tion to configuring on-chip timing and the MMI, t he sys-
tem boot must set the base addresses of the main mem-
ory and MMIO address apertures and load into main
memory a l evel 1 bootstrap pr o gr am f o r t he DS P C PU .
Only the first 10 bytes of the serial EEPROM are needed
wh en PNX130 0 is not th e host PCI pr oces sor; thu s, such
systems can use a very low-cost 128-byte EEPROM de-
vice. When PNX1300 serves as the system’s host pro-
c essor, the boot lo gic permits almost 2 KB of storage for
the level 1 boot str ap DSPCP U p rog ram i n a si ng le eight -
pin EEPROM device.
Figure 13-1. The system boot logic uses the I2C in-
terface to access a s e rial EEPRO M that contains
main- m em ory and system timing info r mation.
4.7K Ω
PNX1300
System Boot
Block
I2C Interfac e Serial
EEPROM
SCL
SDA
4.7K Ω
Vdd
Table 13-1. System Boot Features
Characteristic Comments
Boot Configurations
Supported •Host assisted, e.g., PNX1300 is a
PCI slave in a standard PC.
•Autonomous, e.g., PNX1300 is the
host PCI processor.
ROM Devi ce Types
Supported •Single standard I2C serial
EEPROMs from 128 bytes to 2 KB in
size.
•EEPROMs connect via the
PNX1300 built-in 2-wire I2C inter-
face.
•The use of EEPROMs with hard-
ware Write Protect (WP) is recom-
mended. A jumper on WP allows
user control over i n-sy stem repro-
gramming using the I2C interface.
•The EEPROM must respond to I2C
devi ce address 1010.
RO M device
examples •Atmel 24C01A (128 bytes, WP)
•Atmel 24C08 (1KB , WP)
•At mel 24C 1 6 (2KB, WP).
ROM size •From 128 bytes to 2 KB (one
device) for initia l program load.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
13-2 PRELIMINARY SPECIFICATION
13.2 BOOT HARDWARE OPERATION
Th e PNX 13 00 bo ot sequ en ce b egins wi th th e as serti on
of the reset signal TRI_RESET#. After reset is de-assert-
ed, onl y the sys tem boot block , I 2C, an d P CI i nter fa c es
are allowed to operate. In particular, the DSPCPU and
the internal data highway bus will remain in the reset
state until they are explicitly released during the boot pro-
cedure. In autonomous boot, the system boot block is re-
sponsible for r eleasing the DSPCPU and highway from
reset. In host-assisted boot, the boot logic releases the
highway from reset and the PNX1300 software driver
(which runs on the host processor) releases the
DSPCPU from res et.
The system boot block operation is illustrated in a flow
chart shown in Figure 13-2.
13.2.1 Boot Procedur e Comm on to Both
Autonomous and Host -Assisted
Bootstrap
There sho uld be n o other I2C master active from reset
until boot EEPROM load completes. The system boot
pr ocedu re begi ns by load ing a few cri tica l piec es of infor -
mation from the ser ial EEPROM . This p art of the proce-
dur e is com mon to b oth auto nom ous an d ho st-as sist ed
bootstrapping. See Table 13-2 for a summary and
Table 13-5 for full bit-accurate EEPROM layout details.
The first byte of the EEPROM is read using a serial clock
equal to BOOT_CLK/1000, which is guaranteed to be
less than 100 kHz. After reading the first byte, which con-
tai ns the ac tual BO OT_CLK rate as well as the EEPROM
speed capability, the boot block proceeds to read subse-
quent bytes at the highest valid speed.
The number of line s in the EEPR OM device should be ‘0’
in case of a 128-byte device and ‘1’ for larger devices.
The SDRAM apertur e size should be set to the smallest
size that is larger than or equal to the actual size of
SDRAM connecte d to PNX1300. The SDRAM apert ure
size information is forwarded to the PCI interface for use
in host BIOS configuration, as described in Section
13.3.2, “Stage 2: Host-Sys tem PCI Configuration.”
The BOOT_CLK speed bits should be set to match the
closest rounded up frequency of the external clock cir-
cuit, i.e. for an external clock of 40 MHz or 50 MHz the
value should be 10. This field, together with the EE-
PROM maximum clo ck sp ee d bit are used to deci de the
bes t p oss ib le divi der rat io for ge ner a tio n of the I2C clock,
as show n in Table 13-3. In addition, the delay actions in
Figure 13-2 are taken based on the specified
BOOT_CLK value.
The EEPROM maximum clock speed bit is set to match
the speed grade of the serial EEPROM device.
The test mode bit should always be set to ‘0’. It is only set
to on e for facto ry ATE tes tin g.
Th e S ubsy stem I D and Su bsys tem Ve ndor I D d ata has
no meaning to the PNX1300 hardware; its meaning is
entirely software defined. The value is loaded by the sys-
tem boot block from the EEPROM and published in the
PCI configuration space register at offset 0x2C to pro-
vide the 16-bit Subsystem ID and Subsystem Vendor ID
values . Thes e va lu es a r e us e d by d riv er soft wa r e to di s -
tin guis h the bo ard ve ndor and pro duc t r ev isio n inform a-
tion for multiple board products based on the PNX1300
chip. Refer to Section 11.5.12, “Subsystem ID, Sub-
Table 13-2. Information Loaded During First Part of
Bootstrapping Procedure
Information Size Interpretation
Nu mber of l ines in
EEPROM device 1 bit 0 128 li nes
1 256 or more lines
SDRAM aperture size 3 bits 000 1 MB
001 1 MB
010 2 MB
011 4 MB
100 8 MB
101 16 MB
110 32 MB
111 64 MB
BOOT_CLK speed 2 bits 00 100 MHz
01 75 MHz
10 50 MHz
11 33 MHz
I2C clock speed 1 bit 0 100 KHz
1 400 KHz
Test mode 1 bit 0 normal operation
1rapid ATE testing
Subsystem ID 16 bits Value is copied to Sub-
system ID regi ster in PC I
confi guration space.
Subsystem Vendor ID 16 bits Value is copied to Sub-
system Vendor ID regis-
ter in PCI config space.
MM_CONFIG register
initialization 20 bits Value is simply written to
the MM_CONFIG regis-
ter; see S ect ion 12.6.1,
“MM_CONFIG Register.”
PLL_RATIOS regis ter
initialization 8 bits Value is simply written to
the PLL_ R ATIOS regis-
ter; see S ect ion 12.6.2,
“PLL_RATIOS Register.”
Autonomous/host-
assisted boot 1 bit 0 host-as sisted
1 autonomous
Enable internal
PCI_CLK
1 bit
0 PC I_CLK taken
from outside
1 use on-chip XIO
PC I _C LK cl o ck
generator
Note: MUST be set
if no external PCI
clock is supplied
SDR AM prefetchable 1 bit 0 not pr efetchable
1 prefetchable
Philips Semiconductors System Boot
PRELIMINARY SPECIFICATION 13-3
s ystem Ven dor I D R e gist er , ” for mo re i nf orm at io n on th e
c hoice of values.
The MM_CONFIG and PLL_RATIOS registers control
the har dwa re o f t h e MM I and PN X130 0 o n-c hi p c lo ck c ir-
cuit s. Th ese re gist ers a re des cri bed in d etail i n Section
12.6, “Memory System Programming.” The boot value
s ho uld be s et to re flect the ex act ca pabilit ies of the a ctua l
SDRAM in the system.
The ‘enable i nt e r n al PC I_C L K gener a tor ’ bit determines
the PCI_CLK pin operating mode. If this bit is ‘0’,
PCI_CLK acts compatible with TM-1000 and normal PCI
operation, i.e. it is an input p in that takes PC I clock from
the external world. If this bit is ‘1’, an on-chip clo ck d ivider
in the XIO logic becomes the source of PCI_CLK, and
the PCI _C LK pin is configured as an output. In the latter
case, the PCI_CLK frequency can be programmed to a
divider of the PNX1300 highway clock by setting the
XIO_CTL register ‘Clock F r equency ’ di vi de r valu e. Refer
to Chapter 22, “PCI-XIO External I/O Bus.” Note: This bit
must be set if no external PCI clock is supplied.
The ‘S DRAM pre fet chab le’ bit is copied to the PCI con-
figuration space register DRAM_BASE and only visible
as bit #3 ( P bit) of DRAM _BASE in a PCI c onfigurati on
read, but not visible by MMIO access. Its purpose is to
tel l the PCI host, that SDRAM reads wi ll ca use n o side e f-
fect s. The ho st may apply op timiza tions on PCI acc ess,
if this bit is set .
The ‘autonomous/host-assisted boot’ bit determines
wh ether the syst em boot log ic will con tin ue readi ng mor e
inf orm ation f rom the EEP ROM or ha lt it s ope ration so th e
host can complete system initialization. After the infor-
mation listed in Table 13-2 has been loaded into
PNX1300 registers, an external PCI host processor can
finish the initialization of PNX1300. If no external PCI
host processor is present, the autonomous/host-assisted
boot bit should be set to ‘1’ to allow the system boot logic
to load the information described in the next sect ion.
Table 13-3I2C speed as a function of EEPROM byte 0
BOOT_CLK
bits EEPROM
speed bi t divider
value actual I2C
speed
00 (100 MHz) 0 (100 KHz) 1008 99.2 KHz
00 1 (400 KHz) 256 390.6 KHz
01 (75 MHz) 0 (100 KHz) 752 99.7 KHz
01 1 (400 KHz) 192 390.6 KHz
10 (50 MHz) 0 (100 KHz) 512 97.6 KHz
10 1 (400 KHz) 128 390.6 KHz
11 (33 MHz) 0 (100 KHz) 336 98.2 KHz
11 1 (400 KHz) 96 343.8 KHz
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
13-4 PRELIMINARY SPECIFICATION
TRI_RESET#
de-asserted
8-bit serial read:
1 bit: EPROM capacity
3 bi t s: DR AM ap ert ur e si ze
2 bits: PNX1300 clock speed
1 bit: I2C clock r a t e
1 bit: Test mode control
Write to EEPROM
size register
Write aperture s i ze to
DRAM_ROUND_SIZE
size register in PCI BIU
Write to PNX1300
cl ock speed register
32-bit serial read
Write to
SUBSYSTEM ID
registers in PCI BIU
Write 20 bits to
MM_CONFIG
register in MMI
Write to
PLL_RATIOS
register in MMI
Disable
MMI_RESET
to activate highway
Autonomous
Boot YesNo
System boot halts
(Host driver will compl ete
the boot procedure)
Save 11-bit
byte count
Writ e to
MMIO s pace:
MMIO_BASE
Writ e to
MMIO s pace:
DRAM_BASE
Writ e to
MMIO s pace:
DRAM_CACHEABLE_LIMIT
Bytecount == 0 YesNo
Write to SDRAM
W rit e 32 bits of code on to hi g hw a y
with all by t e enables a ctive.
Then execute 15 dummy w rites on
highw ay to m eet M M I pr ot ocol .
Decrement byte
count by four
Write to MMIO space:
Disable CPU_RESET.
DS PC P U st art s ex ecut i on at
DR A M _ BAS E i n bi g -endia n mode.
System boot halts
24-bit serial read
8-bit serial read
8-bit serial read
64-bit serial read
8-bit serial read
64-bit serial read
64-bit serial read
32-bit serial read
32-bit serial read
Wait 400 usec for
PLLs to lock
Wait ca. 0.6 msec for
I2C to stabilize
Figure 13-2. Flow chart of system boot proced ure for both host-assisted and autonomous configurations.
Philips Semiconductors System Boot
PRELIMINARY SPECIFICATION 13-5
13. 2 .2 Init ia l D S P C P U P r o g ra m Lo ad for
Autonomous Bootst rap
In a system where PNX1300 serves as the host CPU, the
sys t e m bo ot bloc k p erf o rm s an autono m ou s boot proce-
dure. For an autonomous boot, the system boot block
reads all the information described in Section 13.2.1,
“Boot Procedure Common to Both Autonomous and
Host-Assisted Bootstrap,” and then—because the au-
to no mo us bo ot b it is s et—co ntinue s r e ad ing in f o rm at i on
from the EEPROM. After this part of the system boot pro-
cedure is done, the DSPCPU starts executing. See
Table 13-4.
The DSPCP U bootstra p pro gram by te co unt enc odes the
number of bytes of DSPCPU program code contained in
the EEPRO M(s). This 11- bit un sign ed byte cou nt can en-
code up to 2048 bytes, which is also the maximum
amount of EEPROM storage supported. The actual
amount of EEPROM available for the DSPCPU boot-
s tra p pro gr am is li mi ted t o 20 00 bytes. Ot he r inf orma t io n
consumes 47 bytes, and the DSPCPU code must be an
integral number of 32-bit wor ds.
Fou r pair s of 32- bit MMIO- re gi st er a dd res ses and v al ue s
follow the bootstrap program byte count. Each address
tells the boot block where in the 32-bit DSPCPU address
space to store the corresponding 32-bit value.
The first pair initializes the MMIO_BASE. The
MMIO_ B A SE s ets the ba se ad d ress of the 2-MB MMIO-
register address aperture within the DSPCPU 32-bit ad-
dr ess spac e. All MMI O regi st ers ar e addr e sse d using an
offset that is relative to the value of MMIO_BASE. For
th is pair, the address i s required to be 0xEFF00400 be-
cause that is the default MMIO_BASE enforced when
PNX1300 is reset. The new value for MMIO_BASE is en-
coded in the corr es ponding valu e.
The DRAM_BASE address/value pair determine the
base address of the SDRAM address aperture within the
32-bit DSPCPU address space. The address must be
equal to 0x100000 plus the new value of MMIO_BASE
set previously in the boot procedure. The DRAM_BASE
value must be naturally aligned given the rounded DRAM
aperture size, i.e. a 6 MB DRAM aperture should start on
a 8 MB addr e ss multipl e.
Th e DRAM _LI MIT ad dre ss/v alu e pai r d eterm ine t he ex -
te nt of t h e SD R AM a dd r es s a pe r tu r e. The ad dr e s s mu s t
be equal to 0x100004 plus the new value of
MMI O_BA SE set pre vio usly in th e bo ot pro ced ure. The
value in DRAM_LIMIT should be 1 higher than the ad-
dress of the last valid byte of SDRAM memory, and must
be a 64 KB multiple.
The DRAM_CACHEABLE_LIMIT address/value pair de-
termine the extent of the cacheable aperture of the
SDRAM address spa ce. The address mus t be equal to
0x100008 plus the value of MMIO_BASE set previously
in the boot procedure. The cacheable aperture always
begins at the address value in DRAM_BASE; the value
in DRAM_CACHEABLE_LIMIT is one higher than the
address of the last byte of cacheable SDRAM memory,
and mu st be a 64 K B mult ip le . It is safe t o i ni tial ly se t the
value of DRAM_CACHEABLE_LIMIT equal to
DRAM_LIMIT. The RTOS can, if desired, change the val-
ue later .
The next 32-bit value in boot EEPROM memory is a copy
of the DRAM_BASE value encoded previously. The sys-
tem boot hardware loads the DSPCPU bootstrap pro-
gram into SDRAM starting at DRAM_BASE.
The bytes of the D SPCPU b ootstrap program follow the
copy of the SDRAM_BASE value. The bootstrap pro-
Table 13-4. Information Loaded During Second Part
of Bootstrapping Procedure for Autonomous Boot
Information Size Interpretation
DSPCPU bootstrap pro-
gram byte count n11 bits up to 500 32-bit words
(2048 bytes less 47 header
bytes)
MMIO _BA SE address 32 bits Value must be
0xEFF00400
MMIO _BA SE val ue 32 bits Va lue is simpl y wri tten to
0xEFF00400 to determine
new base address of 2-MB
MMIO regist er aperture
within 32-bit DSPCPU
addr ess space
DRA M_B ASE address 32 bits MMIO_BA SE + 0x100000
DRAM_BASE value 32-
bits Value is simpl y wri tten to
DRAM_BASE to determine
base addr ess of SDRAM
aperture within 32-bit
DSPCPU address space
DRA M_LIMIT address 32-
bits M MIO _BASE + 0x100004
DRA M_LIMIT value 32-
bits Value is simpl y wri tten to
DRA M_LIMIT to deter-
mine limit addr ess of
SDR AM aper ture withi n
32-bit DSPCPU address
space
DRAM_CACHEABLE_
LIMIT address 32-
bits M MIO _BASE + 0x100008
DRAM_CACHEABLE_
LI MIT value 32-
bits Value is simpl y wri tten to
DRAM_CACHEABLE_LIM
IT to determine limi t
addr ess of cac heable part
of SDRAM aperture within
32-bit DSPCPU address
space
DRAM_BASE value 32-
bits Copy of the DRAM_BASE;
must be equal to value
specified abov e
SDR AM code word 0 32-
bits First 32-bit word of initial
DSPCPU bootstrap pro-
gram
SDR AM code word 1 32-
bits Second 32-bit word of ini-
tial DSPC PU boo tstrap
program
.
.
.
.
.
.
.
.
.
SDRAM code wo rd n/4 32 bits Last 32-bit word of initial
DSPCPU bootstrap pro-
gram
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
13-6 PRELIMINARY SPECIFICATION
gra m can con sis t o f up to 50 0 32 -bit word s of DS PC PU
instructions. The byte count must be a multiple of four.
Not e that the bytes are stored in the EEPROM in a byte
swapped order per group of 4 compared to SDRAM, as
detaile d in Table 13-5.
After the entire DSPCPU bootstrap program is loaded
into SDRAM at DRAM_BASE, the system boot logic re-
leas es the DSPCPU from the reset st ate. A t this point,
the DSPCPU begins executing the bootstrap program
s tar tin g at D RAM_BASE an d PNX1300 is fu lly o perat ion-
al. At the same time, the boot logic releases the I2C inter-
face.
13.3 HOST-ASSISTED BOOT
DESCRIPTION
For a host-assisted bootstrap, the complete bootstrap
process consists of three distinct stages, but the system
boot hardware performs only the first stage. The other
two stag es are the responsibility of the host system.
13.3.1 Stage 1: PNX1300 System Boot
Hardware
In the first stage, the PNX1300 hardware must be initial-
ized enou g h to al low the h ost s yste m to q uer y an d ma -
nipulate PNX1300 resources. The system boot hard-
ware, using the procedure described above in Section
13.2.1, “Boot Procedure Common to Both Autonomous
and Host-Assisted Bootstrap,” initializes the Subsystem
ID, Subsystem Vendor ID, MM_CONFIG, and
PLL_RATIOS registers, waits for the PLLs to lock, en-
ables the internal highway and MMI, but leaves the
DSPCPU in the reset state. After this minimal initializa-
tion, th e ho st sys te m ca n fin ish the b o otstra p pro c e ss.
At th e com ple tio n of st age 1, th e PNX1 30 0 hard ware is
ready to respond to PCI configuration space accesses,
and the boot block has released th e I2C interface.
13.3.2 Stage 2: Host-System PCI
Configuration
Stage 2 is carried out either by the host-system PCI
BIOS or by a combination of t he BIOS and the host op-
er ating syste m (e.g. , Wind ows 95). Dur ing this sta ge, the
host system configures all PCI-bus clients.
The PCI-bus configuration consists of querying the bus
clients to determine the following:
•The number of PCI base-address registers imple-
mented by each client. For P NX1300, the number of
PCI base-address registers is always two
(MMIO_BASE and DRAM_BASE).
•The size of each aperture associated with the base-
address registers. For PNX1300, the size of the
MMIO aperture is always 2 MB. The size of the
SDRAM aperture can range from 1 MB to 64 MB,
and t he size must be a power of two (s even distinct
sizes).
Using this information, the host system relocates each
address aperture to eliminate overlaps in the PCI ad-
dress space. T he host system accomplishes the reloca-
tion by consid ering each ap erture’s size and then writing
an appropriate starting address to each base-address
register. For PNX1300, the base addresses of the MMIO
and SDRAM apertures must be relocated in this way.
Note that in the case of auton omous boot, this relocation
is done statically by the system boot hardware when it
simply copies the values of MMIO_BASE and
DRAM _B ASE from t he seria l EEPRO M in to th es e regis -
ters.
Th e ste p s of the P CI p rotoco l for determining the size of
an a dd re ss aper tur e are as f o ll ows ( s ee Secti o n 11.5.11,
“Base Address Registers,” for a more complete discus-
sion):
•The host writes a 32-bit word of all ‘1’s (0xffffffff) to
the base-address re gister.
•The host reads the base-address register immedi-
at ely afte r th e wri te. T he valu e retu r ned w ill have ‘0’s
in all don’t-care bits and ‘1’s in all required address
bits. The required address bits form a left-aligned
(i.e., starting at the most-significant bit) contiguous
field of ‘1’s.
•This left-aligned field of ‘1’s effectively specifies the
size of the address aperture by indicating the bits of
the base-address regi ster that a re sig nificant for relo-
cation. That is, an address aperture of size 2n can
only begin on a 2n-byte-aligned boundary.
As a n ex am pl e, consi de r th e c ase of the MMI O ap er ture .
The host will perf orm the following steps during stage 2
of the bootstrap process:
•Write 0xffffffff to MMIO_BASE.
•Read from MMIO_BASE, which returns the value
0xf fe00 00 0. T h e h os t se es th at this valu e has a n 11 -
bit left-aligned field of ‘1’s, which indicates that the
apertu r e can on ly be relocated o n 2- MB boundari es ;
thus, the ape rture size is 2 MB.
•Write a new value to MMIO_BASE with the top 11
bits set to relocate the MMIO aperture to a 2-MB
region of PCI address space that does not conflict
with othe r PCI address ap ertu res .
At th e com ple tio n of st age 2 , the PNX1 30 0 hard ware is
ready to respond to host configuration space accesses,
hos t M MI O ac cesse s a nd host SDR AM aper t ure acce ss-
es. The DSPCPU is still in RESET state.
13.3. 3 St age 3: PNX1300 Dr iver Execut ing on
the Host
During the final stage of the bootstrap process, the
PNX1300 software driver execut ing on the host system
wi ll wri t e to SD RAM a pr o gram for t he DSPC PU, an d in i-
ti al iz e a ny MMIO re gi st ers . When the in iti al progr a m l oad
is compl et e , the dri ver release s the DSPCPU from its re-
set state by a write to the BIU_CTL register with the CR
bit set. See Chapter 11, “PCI Interface.” Now, with the
DSPCPU an d host bot h run ning, th e PNX 1300 boots tra p
pro c es s is complete.
Philips Semiconductors System Boot
PRELIMINARY SPECIFICATION 13-7
13.4 DETAILED EEPROM CONTENTS
Table 13-5 sh ows th e seria l EEP R OM con te nts ne ed ed
for an autonomous boot procedure. For the host-assisted
boot procedure, only the contents up to line nine are
needed.
Note that the 32-bit words in the serial EEPROM are not
st ore d on 32 - b it word- al ig ned ad dr e ss e s.
Table 13-5. Serial boot EEPROM contents
Line Data Byte
bit 7 b it 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0
0#lines
0: 128 lines
1: 256 or more
lines
SDR AM si ze [2 :0]
000: 1MB
001: 1MB
010: 2MB
011: 4MB
100: 8MB
101: 16MB
110: 32MB
111: 64MB
BOOT_CLK[1:0]
00: 100 MHz
01: 75 MHz
10: 50 MHz
11: 33 MHz
EEPROM
clock
0: 100 KHz
1: 400 KHz
Test Mode
0: normal
1: rapid ATE
1
2
3
4
Subsystem ID, 8 msb
Subsystem ID, 8 lsb
Subsystem Vendor ID, 8 msb
Subsystem Vendor ID, 8 lsb
5
6
7
———— MM_CONFIG[19:16]
MM_CONFIG[15:8]
MM_CONFIG[7:0]
8PLL_RATIOS[7:0]
sdram PLL
bypass sdram PLL di s-
able cpu PLL bypass cpu PLL disable sdram ratio cpu ratio[2:0]
9boot type
0: host assist.
1: autonomous
enable inter-
nal PCI_CLK
SDRAM
prefetchable
0:no 1:yes —— byte count [10:8]
10 byte count [7:0]
11
12
13
14
MMIO_BASE address [31:24] (must be 0xEF)
MMIO_BASE address [23:16] (must be 0xF0)
MMIO_BASE address [15:8] (must be 0x04)
MMIO_BASE address [15:8] (must be 0x00)
15
16
17
18
MMIO_BA SE value [31:24]
MMIO_BA SE value [23:16]
MMIO_B ASE valu e [15:8]
MMIO_BASE v alue [ 7:0]
19
20
21
22
DRAM_BASE address [31:24] (must be byte 3 of MMIO_BASE + 0x100000)
DRAM_BASE address [23:16] (must be byte 2 of MMIO_BASE + 0x100000)
DRAM_BASE address [15:8] (must be byte 1 of MMIO_BASE + 0x100000)
DRAM_BASE address [7:0] (must be byte 0 of MMIO_BASE + 0x100000)
23
24
25
26
DRAM_BASE value [31:24]
DRAM_BASE value [23:16]
DRAM_BASE value [15:8]
DR AM_BASE v alue [ 7:0]
27
28
29
30
DRAM_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100004)
DRAM_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100004)
DRAM_ LIMIT add ress [15:8] (must be byte 1 of MMIO_ BASE + 0x100004 )
DRAM_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100004)
31
32
33
34
DRAM_LIMIT value [31:24]
DRAM_LIMIT value [23:16]
DRA M_LIM IT val ue [15:8]
DRA M_LIMIT value [7:0]
35
36
37
38
DRAM_CACHEABLE_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100008)
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
13-8 PRELIMINARY SPECIFICATION
39
40
41
42
DRA M_CACH EAB LE_LIMIT val ue [31:24]
DRA M_CACH EAB LE_LIMIT val ue [23:16]
DRA M_CACH EABLE_LIMIT val ue [15:8]
DRAM_CACHEABLE_LIMIT value [7:0]
43
44
45
46
repeat of DRAM_BASE value [31:24]
repeat of DRAM_BASE value [23:16]
repeat of DRAM_BA SE value [15:8]
repeat of DRAM_BASE value [7:0]
47
48
49
50
byte 0 of DSPCPU bootstrap program (stored at DRAM_BASE + 3)
byte 1 of DSPCPU bootstrap program (stored at DRAM_BASE + 2)
byte 2 of DSPCPU bootstrap program (stored at DRAM_BASE + 1)
byte 3 of DSPCPU bootstrap program (stored at DRAM_BASE + 0)
.
.
.
.
.
.
j+47 byte j of DSPCPU bootstrap program (stored at DRAM_BASE + ((j div 4) + (3 – (j m od 4) )) )
.
.
.
.
.
.
(n–1)
+47 last byte of DSPCPU bootstrap program (bits [7:0] of last 32-bit word, stored at DRAM_BASE + n – 4)
Table 13-5. Serial boot EEPROM contents
Line Data Byte
bit 7 b it 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0
Philips Semiconductors System Boot
PRELIMINARY SPECIFICATION 13-9
13.5 EEPROM ACCESS PROTOCOL S
Figure 13-3 shows the SDA (serial data) line protocols
fo r th re e t y pe s of r e ad ac ces se s s up p o rt e d by I2C serial
EEPROMs. A read from the address currently latched in-
side th e EEPRO M can b e for e ither a single by te or fo r
an arbitrary series of sequential bytes. The master
makes the choice by setting the ACK bit after a byte has
been transferred.
A ran dom - ac ces s r e ad is acc omplish ed by p erformi ng a
dummy write, which overwrites the latched address
stored inside the EEPROM. Once the internal address
lat ch is set t o the de sir ed val ue, one of the other two read
pro tocols can be us e d t o read on e or mo re bytes .
The boot logic inside PNX1300 uses a single random
read transaction to location 0 of device address 1010000
followed by a sequential read extension to read all re-
quired EEPROM bytes in a single pass.
SDA Lin e Protocol :
Random Read
S
T
A
R
T
Device Addr ess
W
R
I
T
E
W
A
7
W
A
6
W
A
5
W
A
4
W
A
3
W
A
2
W
A
1
W
A
0 1010A
0P
1P
0
D
7D
6D
5D
4D
3D
2D
1D
0
S
T
A
R
T
R
E
A
D
S
T
O
P
A
C
K
A
C
K
A
C
K1010
D
A
0
P
A
0
P
A
0
N
O
A
C
K
Device Addr ess
Dummy Write
1010A
0P
0P
0
S
T
A
R
T
R
E
A
D
S
T
O
P
A
C
K
A
C
K
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SDA Lin e Protocol :
Sequential Read
Data n Data n+1 Data n+2 Data n+3
1010A
0P
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Current-Address Read
Data n
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Figure 13-3. Protocols supported by the boot block for reading the EEPROM
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
13-10 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 14-1
Image C oproce sso r Chapte r 14
14.1 IMAGE COPROCESSOR OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The Image Co processor ( I CP) connects to the PN X1300
on- ch i p data high way t o p erf orm S DR AM bl oc k rea d an d
writ e actions . It also co nnects to the PC I inte rfac e to al-
low block write transactions across PCI.
The major functions of the ICP are:
•Filter an image by reading the image from SDRAM
and writing the image back to SDRAM, while apply-
ing a us er -defin e d poly phas e filte r with op tio nal ho ri -
zont a l u p- or down -s c a ling.
•Filter an image by reading the image from SDRAM
and writing the image back to SDRAM, while apply-
ing a use r defin ed po ly ph as e fi lter wit h op ti onal verti -
cal up- or down-scaling.
•Filter an image and convert it from planar to RGB or
YUV composite by reading the image from SDRAM
and writing the image out to PCI bus memory (graph-
ics card) or SDRAM, while performing horizontal
scaling and conversion to one of a several RGB or
YUV formats. The programmer can add optional bit -
map masking to selectively enable/disable pixel
writes to PCI (to refresh only the exposed part of a
video window) and an optional image overlay with
alph a blen ding and op tio nal ch roma keyin g (PC I o ut-
put only).
•Move an image by reading the image from SDRAM
and w r i tin g it back to SD RA M .
All of the ICP functions move and transform data from
memory to memory or memory to the PCI bus. Hence,
the DSPCPU can use the ICP in a time-sharing fashion
to sim ultaneous ly achie ve:
1. Vertical and horizontal resizing/subsampling on the
image stre a m from t h e Vide o I n (VI) un it.
2. Vertic al and hori zo nta l r esi zi ng /u psamp l in g o n the i m-
age str ea m s e nt t o th e Video O ut (VO) u nit .
3. Pr esentat ion of a c olle ction of l iv e video w indows w ith
programmable up and down scaling and arbitrary
ove rlap configu ra tion on PC I gr aphics cards.1
Full 2D scaling and filtering requires two passes over the
data: one for horizontal scaling and filtering and one for
ver ti cal sc al ing and filter i ng .
Figure 14-1 shows a block diagram of the PNX1300 with
the ICP. Figure 14-2 shows a block diagram of the inter-
nal s tru ctur e of th e IC P. Th e IC P cont ain s a 5-t ap f ilter ,
YUV to RGB converter, an overlay and alpha blending
unit, and an output formatter. These blocks communicate
with ea ch other through F IFOs that also buffer the block
dat a to and fro m the PNX 13 00 D ata H igh wa y. Th e I CP
uses a microprogram-controlle d sequencer to control its
int ern al timi ng . The progr am fo r thi s se quen ce r is i n a t a-
ble in SDRAM. The ICP reads the appropriate portion
from the SDRAM each time the ICP is commanded to
per for m a func tion. Mic ropr ogra m co nt rol s impl ifi es a nd
minimizes the ICP hardware and increases the flexibility
of the ICP to perform additional tasks without adding
hardware.
14.2 REQUIREMENTS
14.2.1 Functions
The major functions of the ICP include:
1. Read an image from SDRAM and write the image
back t o SD R AM , whi le ap plying a us er def ined
polyph ase f i lter wi th op tiona l up or down s cali ng in
horizontal direction.
2. Read an image from SDRAM and write the image
back t o SD R AM , whi le ap plying a us er def ined
polyph ase f i lter wi th op tiona l up or down s cali ng in
ve rtic al directio n.
3. Read an image from SDRAM and write the image out
to PCI bus memory (graphics card) or SDRAM, while
pe rfo rmi ng horiz onta l scaling and conversion to one
of a several RGB and YUV formats. The PCI output
mode includes optional bitmap masking to selectively
enable/disable pixel writes to PCI (to refresh only the
exposed part of a video window) and optional RGB
over lay with alpha blending and optional chroma key-
ing.
14.2.2 Bandwidth
IC P ba nd wid t h can be est imat ed from t h e wo r st-c as e i m-
age processing bandwidth. If the worst case image is
102 4 x 7 68 at 30 Hz i n YUV 4:2: 2 f orm at, the pixel rate is
1024 x 768 x 30 = 23.59 Mpix/sec. For YUV 4:2: 2 image
coding at 2 bytes per pixel, this is 23.59 x 2 = 47.19 MB/
1. Note that function 2 and 3 don’t normally occur simulta-
neously, and if an application attempts both simulta-
neously, some performance limitations are incurred.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-2 PRELIMINARY SPECIFICATION
sec. The minimum bandwidth for the ICP function is
therefore 47.18 MB/sec., or approximately 50 MB/sec.
Video DMA In
Au di o D MA In
Audio DMA Out
I$
D$
I2C Interface
Image
coprocessor
PNX1300
Memory
Controller
PCI Mast e r/Slave Interface
VLD
Video Out
Digital
DMSD
or R aw
Video
Serial
Digital
Audio
JTAG
Clock
PCI Local Bus
SDRAM
SDRAM
Highway
SSI
Camera
Figu r e 1 4-1 . PNX1 30 0 chip bloc k d iagram
DSPCPU
Coprocessor
FIFO
Bank 5-tap
Filter
Micr oprogram C ontrol U nit
To PCI
Y
U
V
Overlay
Bit Mask
To SDRAM
Microcode
Overlay +
Alpha Blending +
Chroma K eying
YUV => RGB
Conversion
Output Formatti n g +
Bit Masking
Image Coprocessor
Overlay
Bit Mas k
To SDRAM
PN X1300 Data Highway
Figure 14-2. Image coprocessor block diagram
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-3
Scaling and filtering of the two dimensional image re-
quires two passes of the image data through the filter,
one f or ver ti c al an d one for hori zontal. S c al in g an im a ge
and sen ding it t o th e PC I bus r e q uires three t r an s fer s o f
the image over the SDRAM bus: one transfer to read the
image for vertical filtering, one transfer to write the fil-
te red da ta back , and one t ran sf er to r ead the i ma ge fo r
horizontal filtering and output to the PCI bus. This means
an average of SDRAM bus bandwidth of 3 x 50 = 150
MB/ s ec for t he 1024 x 768 image case described above,
assuming a scaling factor of 1.0. A larger or smaller scal-
ing fact o r mea ns t hat eith er t he inpu t or ou t put i ma ge wil l
be sm alle r th an 1024 x 76 8. The b andwi dths req uired a re
determined by th e larger of t he two images, input or ou t-
put. This is because all input pixels must be scanned to
gener at e all t h e ou tput pixels .
14.2.3 Image Size and Scal ing
Ima ge siz es i n th e PNX1 30 0 have a nomin al ran g e of 16
x 16 to 1024 x 768. Sizes smaller than 16 x 16 are pos-
sible, but are too small to be recognizable images. Imag-
es lar ger th an 1024 x 768 (up to 64 K x 64 K) are possible
but they cannot be processed in real time and require
larger SDRAM sizes. Scaling factors have a nominal
range of 1/4 (down scaling by 4) to 4 (upscal ing by 4) .
Larger up and down scaling factors are possible, up to
1000 and beyond; however, very large upscaling factors
result in a la rge magnificat ion of a few pixel s, and very
lar ge dow n sca ling factors give on ly a few p ixel s as a re -
sult.
14.3 INTERFACE
The ICP u ni t has n o PN X13 00 e xt ern al pins . I t inte rf ace s
internally to the Data Highway and the PCI Interface.
14.4 DATA FORMATS
The ICP unit accepts input and overlay image data to
gene rat e ou tpu t im age d ata. Th e IC P acc omm oda tes a
variety of formats for the input, overlay and output data.
These image data formats define the relationship be-
tween the Y, U, and V or R, G, and B components of the
ima ge as th ey are sto red in mem ory. Th e ICP acc epts in-
put image data in planar format, where the Y, U and V
components are in separate tables in SDRAM. The vari-
ous input image da t a fo r m at s di f fe r in t he po s i ti on of t h e
U a nd V comp onent s re lativ e to t he Y comp onen t and th e
am ount of U and V data relative to the Y data.
In all modes except the YUV to RGB conversion modes,
eac h ICP op erati on pro cesse s one Y , U, or V imag e com-
ponent. Three separate commands are required to pro-
cess all three components of an image. Since each com-
ponent is scaled and filtered separately, the software
defines the image format and format conversion by how
it scales ea ch component.
For pixel format conversion for PCI or SDRAM output
mode, ea ch outp ut pix el is a c ombina tion of RGB or YUV
components as defined by the output format. The YUV
input data and the RGB or YUV overlay data are com-
bined by the ICP hardware pixel by pixel to form the RGB
or YUV output pixels. Because all three YUV compo-
ne nts are sim ultaneous ly w o ven t ogethe r to creat e each
output pixel, the ICP hardware must know the image
dat a f or m at i n S DR A M , defi ned as ho w the c o mp onen t s
of the im age data ar e t o be fou n d and com bine d .
In the YUV to RGB conversion mode, the ICP accepts
the following input data formats: YUV 4:2:2 co-sited,
YUV 4:2:2 int ersper sed, and Y UV 4:2: 0. I n this mo de, the
IC P will a ls o ac ce pt ima ge over l ay dat a wh en PCI outp ut
is specified. The ICP accepts image overlay data in sev-
eral combined formats: RGB 24+α, RGB 15+α, and YUV
4:2:2+α. In this mode, t he ICP generates output data in
several RGB and YUV fo rmats. These formats are com-
pat i ble w i t h a w ide v a riety of PCI fr am e bu f fers.
14.4.1 Image Input Formats
The ICP image input formats define the relat i ve positions
of the Y component and the U and V components of the
inpu t ima ge pixel data. There are three input formats to
th e ICP: 4:2: 2 c o- s i ted , 4:2 :2 i nter s pe rs ed, and 4:2 : 0 in -
ter s per sed. The 4:2:2 form ats ha ve 2 U and 2 V pixe ls fo r
every 4 Y pixels, so the ratio of Y to U or V is 2:1. The
4:2:0 for mat has 1 U and 1 V pixel for every 4 Y pixels,
so th e ratio of Y to U o r V is 4:1. Th e input form ats are
given below. The input formats have a significant impact
on t h e 2 d im ens iona l scal ing ope r atio n.
14.4.1.1 YUV 4:2:2 Co-Sited
In the YUV 4:2:2 co-sited f ormat, the U and V pixels co-
incide with the Y pixel on every ot her pixel, as shown in
Figure 14-3.
14.4.1.2 YUV 4:2:2 Interspersed
In th e YUV 4 :2: 2 int e rs per se d for m at, the U and V pix el s
lie between the Y pixels on eve ry oth er pixel of the hori-
zont al li ne, a s sh own in Figure 14-4.
14.4.1.3 YUV 4:2:0 XY Interspersed
In th e YUV 4 :2: 0 int e rs per se d for m at, the U and V pix el s
lie between the Y pixels on eve ry oth er pixel of the hori-
zont al li ne, a s sh own in Figure 14-5.
14.4.1.4 YUV 4:1:1 Co-Sited
In the YUV 4:1:1 co-sited f ormat, the U and V pixels co-
incide with the Y pi xel on every fourth pixel, as sh own in
Figure 14-6.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-4 PRELIMINARY SPECIFICATION
Figure 14-3. 4:2:2 Co-si ted input format
Chrominance
(U,V) samples Luminance
samples
Figure 1 4 -4. 4:2:2 Interspersed input format
Chrominance
(U,V) samples Luminance
samples
Figure 14-5. 4:2:0 XY Interspersed input format
Chrominance
(U,V) samples Luminance
samples
Figure 14-6. 525-60 YUV 4:1:1 Co-Sited input format
Chrominance
(U,V) samples Luminance
samples
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-5
14.4.2 Image Overlay Formats
The ICP accepts image overlay data in three formats,
RGB 24+α, RGB 15+α, and YUV-4:2:2+α as shown in
Table 14-1. The overlay image fo rmat m ust be the sam e
typ e as the ou tput image for mat gener ated by t he ICP for
the ma in im ag e. For ex ampl e, if t he output image i s o ne
of t he RG B f orm at s, the ov erl ay must be on e o f t he two
RGB overlay formats, RGB-24-α and RGB-15+α. If the
output image format is YUV, the overlay format must be
in YUV-4:2:2+α format. The formats must be of the same
type because the ICP does no conversion on the overlay
data.
In R GB 24 +α, pixels are packed 1 pixel/word, a f ull by te
of al ph a i nf o rm ation (stor ed in th e m o st si gn if i ca nt by t e )
is included w ith each pi xel. I n RGB 15+α, one bi t of al pha
is incl uded for ea ch pixe l. The pi xels in the ov erl ay image
are pack ed as 2 pixels per 32 -bit word, and the alpha bit
is the most significant bit of each half word. In the same
manner, the YUV-4:2:2+α format packs two pixels into
one 32-bit word, and has one bit o f alpha for each pixe l.
The least significant bit of the U and V components sup-
plies the alph a bi t fo r the Y 0 and Y1 pi xels, resp e cti vely.
The al pha bit in these formats se lects be tween two alpha
values stored in the ICP, alpha 1 and alpha 0. The alpha
1 and alpha 0 values are loaded from the parameter
bloc k w he n the ICP is st arted.
14.4.3 Alpha Blending Codes
Image overlay uses alpha blending, which combines the
ove rlay image with the main imag e according to th e al-
pha valu e. The al pha val u e is sup plie d by th e al pha byte
in RGB 24+α f or m a t and by the al pha r eg is te r s , Alp ha 0
and Alpha 1 in the other formats. The alpha code format
is sho wn in Table 14-2.
14.4.4 Output Formats
The output formats are the RGB image formats sent to
th e PCI in terf ace o r SDR AM. Thes e for mat s ar e sh own
in Table 14-3. Note: B1 = Byte 1 of blue = [b7...b0]1.
Ta ble 14-1 . Ima ge Ov erlay Formats
Format Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0
RGB 24+αa7 - a0 r7 - r0 g7 - g0 b7 - b0
YUV-4:2:2+αY1 (v7-v1) + αY0 (u7-u1) + α
Pixel 1 Pixel 0
RGB 15+αα r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 α r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b 2 b1 b0
Table 14-2. Alpha Blending Codes
Alpha Code Al pha Value Im age Over lay
00h 0 100% 0%
20h 32 75% 25%
40h 64 50% 50%
60h 96 25% 75%
80h - FFh 128-255 0% 100%
Table 14-3. Output Data Formats
Format Word Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0
Pixel 3 Pixe l 2 P ixel 1 Pixel 0
RGB 8A: 233 1 r1 r0 g2 g1 g0 b2 b1 b0 r1 r0 g2 g1 g0 b2 b1 b0 r1 r0 g2 g1 g0 b2 b1 b0 r1 r0 g2 g1 g0 b2 b1 b0
RGB 8R: 332 1 r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0
Pixel 1 Pixel 0
R GB 15+α1α r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b 4 b3 b2 b1 b0 α r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
RGB-16 1 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
1 Pixel/Word
R GB 24+α1 a7 - a0 r7 - r0 g7 - g0 b7 - b0
Packed 4 Pixels/3 Words
RGB 24-packed 1 B1 R0 G0 B0
2G2B2R1G1
3R3 G3 B3 R2
Packed 2 Pixels/Word
YUV- 4:2: 2 1 Y1 V0 Y0 U0
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-6 PRELIMINARY SPECIFICATION
14.5 ALGORITHMS
14.5.1 Introduction
Th e ICP pr ov id es f il ter i ng , res iz in g (s c aling ) and YU V to
RGB conversion of the source image. Filtering provides
image enhancement. Scaling generates a new image
that is larger or smaller than the current image. YUV to
RG B c on v er s ion is used t o gene rate an RGB version of
the image for output to an RGB format frame buffer
thr ough the PCI interface or to SDR AM.
Th e filter in g, sc alin g, a nd YU V to RG B co nv e r sion algo-
rit hms ar e disc uss ed separately . The IC P uses thes e al -
gorithm s in tw o w a ys .
1. It provides one pass horizontal scaling with horizontal
5-t ap fi lte ring of Y, U, or V.
2. It provides one pass vertical scaling with vertical 5-tap
filtering of Y, U, or V.
14.5.2 Filtering
The ICP pro vide s high qu ality, 5 -ta p poly phase filte ring ,
bot h h ori zo nt al and v ert ic al , of Y, U, or V d ata. E ac h f ilt er
type is performed as a separate one dimensional filter
pass. Two dimensional filtering of the image requires two
passes of the one dimensional filters.
Multi-tap FIR filt ering
In m ul ti -t ap FIR f il ter i ng o f an ima ge , t h e new f ilt er out put
(pixel) value is a weighted sum of adjacent pixels. The
weighting coefficients determine the type of filtering
used . A 5-ta p filter generates th e new pixel value as a
wei gh t e d su m o f t he c urr en t valu e and the tw o p ix e l s on
either side (2 left and 2 right for horizontal filtering, 2
above an d 2 below for ver ti cal) .
A m ulti-tap FIR fil t e r ca n be used to gene r ate valu es for
new pixels that are displaced fr om the original (‘center’)
pixe l in th e sa me way as li ne ar inter po latio n. Fo r e xam -
ple, as sume the new pixel l ocation is shi fted slightly to
the right of the center pixel of the input image. A ho ri zon-
tal fil ter can be u sed to es tima te the ne w pi xe l value by
weighting the right pixel filter coefficients more heavily
tha n th e le ft, propo r tio na l to the relat i ve po siti o n off s et of
the new pixel. (In this sense, interpolation is a 2-tap fil-
ter.) This is shown in Figure 14-7. Th e ICP hor izo ntal an d
v er tical filter operations use this meth od to combin e scal-
ing with filtering.
Mirroring pixels at the st art an d end of a line or wi n dow
A line m ay s tart and/or e nd at the edge of the input im-
age. In this cas e, t he t w o start and/or end p ix els needed
for the first and last pixels of the line, respectively, are
missing. The ICP uses pixel mirroring to solve this prob-
lem. In pixel mirroring, the two available pixels are used
to su bs ti t ut e the tw o m is s in g pix els. Th e fi r st pi xel, us es
copies of t h e two pi xe ls to th e r i gh t as t houg h t h ey w e r e
the two pixels to the left. Specifically, P+2 substitutes for
P- 2, and P+1 sub st i tute s for P- 1. T he l ast pixe l u s es co p-
ies of the two p ixel s to the left as th ough th ey we re the
two pi xels t o t h e r ight. S inc e the left and r igh t pix els are
now the same, this is called pixel mirroring.
There are five states of pixel mirroring: first output pixel,
s econd output p ixel, middle pixe ls, next to last o u tput p ix -
el an d last output pixe l. The first ou tput pixel uses pixels
numbered (2,1,0,1,2). The second pixel uses (1,0,1,2,3).
The middle pixels use (P-2, P-1, P, P+1, P+2). The next
to last pixel uses (N-3, N-2, N-1,N, N-1), where N is the
number of the last input pixel. The last pixel uses (N-2,
N-1, N, N-1, N-2) .
In som e c ase s of upsca li ng, one m ore in pu t pix el may b e
need ed at the end of the line. In these ca ses, the pixe l
value(s) are not generated by the mirror logic. Instead,
th e ICP us es a copy o f the l as t outp ut pixe l as the be st
est i ma te of the r eq ui r ed out put pi xel .
14.5.3 Scaling
Scalin g over view
Resizing, or scaling, the image means generating a new
image that is larger or smaller than the original. The new
image will have a larger or smaller number of pixels in the
hor izo ntal an d/ or ver tica l dir ectio ns tha n the or igi nal im -
age. A larger image is scaling up (more new pixels); a
smaller image is scaling down (fewer newer pixels). A
simple case is a 2:1 increa se or decrease in size. A 2:1
decrease could be done by throwing away every other
pixel (although this simple method results in poor image
quality). A 2:1 increase is more interesting. The new pix-
els can be generated in between the old ones by:
1. Duplicating the original pixels
2. Linear interpolation, where the new in-between pi x el s
are the we ighted aver ag e of the adjacent input pixe ls
Input Pixels
Output Pixels
Filter (uses 5 input pixels)
Interpolation (uses 2 input pixels)
Figure 14-7. Pixel generation by interpolation and filtering
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-7
3. M ulti- tap filter i ng, wh er e t h e new i n-betwe en pixels
are m ulti- p ixel filter ed ver s ion of t he adjacent input
pi xels. Th is approach r esults in the best i mage .
The more general case is where the output image reso-
lution is n ot an i nte gral m ultip le or sub -m ult iple of th e in -
put image re soluti on, such as converting from 640 x 480
to 1024 x 76 8. In this case, the outp ut pixel s h ave dif fe r -
ing po sitio ns rela tive t o t he inp ut pixe ls in the hori zonta l
or vertical dimensions. In converting from 640 to 1024,
th e fi rst o utput pix el on a lin e c orres po nd s t o the f i rs t in-
put pix el. Th e sec ond out put p ixel is at 64 0/10 24 of the
di stan ce be twe en t he fi rst an d se co nd in put pi xels . T he
third output pixel is at (2*640)/1024 of the distance =
1280/1024 = 1+ 256/1024 = 256/1024 of the distance be-
twe en th e s eco nd and thi rd inpu t pix els, etc. The output
pixels shift with respect to the input pixel grid as you
move along the line in the horizontal or vertical dimen-
sions. This is shown in Figure 14-8.
New p ixels are gene rated by interpolation or filtering of
the original pixels. Int erpolat ion is the weighted average
of the input pixels adjacent to the output pixel. Filtering
extends interpolation to include input pixels beyond the
input pair adjacent to the output pixel. The number of pix-
els used to gene rate the output defines the filter type. In-
terpolation is a 2-tap filter. A 4-tap filter would use the two
pixels to the left and the two pixels to the right of the out-
put pixe l. A 5 -tap filt er id enti fie s the s ingle pixe l neare st
the output as the center pixel, and uses this pixel plus
tw o to the left and two to the right to generate the output.
If the r atio of the ou t p ut pixel cou nt pe r line (in H or V) to
input pixel count per line is the ratio of small integers,
th ere is a re peat ing p at t er n in t he se r ela ti v e po sitions of
input to output pixel locations. For example, for 640 to
1024, the ratio is 8/5. The pattern repeats for ever y 8 out-
put and every 5 input pixels. If the ratio is not a ratio of
s mal l integer s, the patt ern wil l take a l ong ti me to r ep eat .
The wor s t c ase would be 640 to 6 41, for exampl e. There
would be no exact repetition for the whole line.
The interpolator or filter coefficients must be weighted
according to the relative position of the new pixel relativ e
to the old pixels. The weighting factor is between 0.0 and
1.0, correspond ing to the relative posit ion of the new pix -
el with respect to the old pixel grid. With a repeating pat-
te rn, few er weig ht ing f acto rs are nee ded, an d t heref ore
few e r coe ffi ci en ts in t he lin ea r int erp ol at o r or f ilt er gen er -
ati ng th e new pi xels, si nce yo u can reu se the m each t im e
the pattern repeats. A filter with a repeating pattern is
called polyphase, indicating a repeating pattern in the
phas e ( of fs et posi tion) of t he ou tput pi xels re lativ e t o the
input pixels.
Generating the output pixels : relating the output grid to the
input grid
Sca li ng is a pixe l t rans f orma ti on in whi ch a n arr a y of ou t-
put pixels is generated from an array of input pixels. The
value of each pixe l on the outp ut pi xel grid is calcula te d
fr om the valu es of its adj acen t pixe ls on th e inp ut gri d. To
find these adjacent pixels, you overlay the output grid on
the input grid and align the starting pixels, X0Y0, of the
two grids. To identify the adjacent input pixels for a given
output pixel, you divide the output pixel X (pixel number
alo ng th e outp ut li ne) and Y (pixe l lin e numb er withi n wi n-
do w) by their corresponding scaling factors:
Xin = Xout / (hor iz o nta l sc al in g facto r )
where: horizontal scaling factor =
outp ut le ng th / inp ut le ngth
Yin = Yout / (v ertica l scal ing fac t o r)
where: verti cal scaling factor =
out p ut he ig ht / inp ut heig ht
Note that the resulting Xin and Yin values will be real
numbers because the output pixels will usually fall be-
tween the input pixels. The fractional portion indicates
the fra ct io na l di st an ce to t he next pi xe l. To ca l cul ate the
out pu t pixe l va lu e, you us e t h e v alue for th e n ea res t pi xe l
to t he lef t and ab ov e and comb i ne i t with t he valu e of the
other adjacent pixel(s). For example, horizontal interpo-
latio n us es th e star ting pix el to the le ft int erpol ated with
th e next p ixel to the r ight , with the fracti on al va lue us ed
to determine the weighting for the interpolation.
ICP scaling output resolution
In th e ICP , sca ling i s fo rced to have a repeating pattern
by limi ting th e reso lut ion of the new pixel p osi tion to 1/32 ;
the new position is forced to be at a location n/32 in H
and V relative to the position of the original pixel grid.
This results in a w ors t case error of approximat ely 1.5%
in amplitude relative to calculations using exact output
pixel positions. This is comparable to the errors caused
by quantizi ng the ampl itude of the pi xels . The a ddit i onal
quantization noise can be avoided by choosing an appro-
pri ate s cale fa ctor wh ich, whe n inv er ted, resu lt s in fr ac -
tional values which are expressed in 32
nds, su ch as th e
8/5 scaling factor in the 640 to 1024 example above. A
diagram of the input to output pixel relationship and the
123451
18765
4
321
Input Pixels
Output Pixels
Figure 14-8. 640 to 1024 up scaling example
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-8 PRELIMINARY SPECIFICATION
output fractional X and Y subpixel offset is shown in
Figure 14-9.
Output scaling calculation method
The output pixel distance in H and V in the ICP is calcu-
lated to high precision (16-bit fraction) even though the
output resolution is fi xed at 1/ 32 of the input grid. Each
output pixel’s location relative to the input pixel grid is giv-
en by :
X location of output pixel = X0 of input line + output
pi xe l nu mb er / X Scale Fact o r
Y location of output pixel = Y0 of input window
+ output line number / Y scale factor
The X and Y locations may not be integer values, de-
pending on the scale factor. The resulting X and Y pixel
locations can be separated into an integer and a fraction-
al pa rt. The i nteg er p art o f th e X and Y lo cati on s elec ts
the pixel and line number closest to the output pixel, re-
spectively. The fractional part gives the fractional dis-
ta nce o f the ou tp ut pix el to the next X an d Y i nput p ixel
values. These fractional parts are the dX and dY values
shown in Figure 14-9.
The output pi xel value can be calculated by interpolation
bet wee n the t wo inp ut p ixel s or b y 5-ta p fi lteri ng u sing the
5 ne ares t p ix el s rat h er t ha n t he 2 near es t pixel s. Interpo -
lation or filtering uses the fractional position values, ∆X
and ∆Y, to select the appropriate filter coefficients. In the
ICP, these values are limited to 5 bits for a resolution of
1/32, even though the actual position value has much
higher resolution. The ICP uses fractional values cen-
tered around the center pixel with a range of -16/32 to
+15/32.
To perform scali ng, the X and Y locations of the output
pixel relative to the input pixel grid must b e generated.
This includ es bo th the inte ge r part to loca te the adja ce nt
pixels and the fractional part to choos e the filter coeffi-
cients which generate the output value from the adjacent
pixels. This could be done by generating the output pixel
X and Y numbers and dividing each by its associated
s cale factor. Sin c e divi ding is expensi ve in ha rdwar e and
time, the ICP effectively multiplies the X and Y pixel num-
bers by the inverse of the X and Y scaling factors, resp.
This is done by incrementing the X and Y input pixel
counters by X and Y increment values that are the in-
verse of the X and Y scale factors, resp. For output pixel
Xn, the inverse of the scale factor is added to the X input
location n times. This is equivalent to multiplying n by the
inverse of the scale factor.
The ICP uses a 1 6-bit in tege r and a1 6-bit frac tio nal valu e
for the X and Y increment values. This allows a fractional
value resolution of 1/64K. Since the increment value will
be added 1024 times in a 1024-pixel line, any error in an
individual calculation will be multiplied by 1024. The high
resolution of the calculat io n prevents an accumulation of
err or as you increment along the line.
Only the most significant 5 bits of the fractional value are
us ed by the filter coefficient RAMs. However, the X and
Y coun te rs ar e inc reme nt e d by th e high-r es olut io n X an d
Y increment values. The result of this truncation is a
worst case error of approximate ly 1.5 % in amplitude rel-
ative to arbitrary pixel output positions.
The error caused by discrete (1/32) resolut ion can be re-
duc ed t o e xac tly z er o i f th e ou tput imag e si ze i s adj ust e d
to have a repeating pattern that fits on these 1/32 bound-
aries. For zero error, this implies that the scaling factor
must be of the form of B/A, where B (the output pixel
count factor) is a sub -multiple of 32 [i.e. 1, 2, 4, 8, 16, 32],
and A (the input pixel count factor) is an integer deter-
mined by the neare st acceptable scale factor for a given
B. In the 640 to 1024 conversion case, the B/A ratio was
8/5, meeting this requirement.
The in tege r v alues, if accumu lated , woul d be equal to the
total number of input pixels when scaling is complete.
The integer values for each pixel define the number of
pixe ls to r ead fr om mem ory an d shi ft in to g enera te the
next output pixel. For example, a scaling factor of 1.0 will
res u lt in one pixel shifte d in fo r ea ch output pixel gener-
ated. Upscaling will have integer increment values of
less than one. This means that the integer value will be
‘0’ for some pixels and ‘1’ for others. For e xampl e, up-
scaling by 2.0 will result in inte ger values of ‘1’ half the
time and ‘0’ for the other half, depending on the carry out
from the fractional increment.
Pixel shift byp as sing for large dow n scal ing
Do wn scali ng wil l have inte ger in crem ent valu es of gr eat-
er than one. In this case, the integer value indicates the
number of pixels to read to obtain filter pixels for the next
output pixels. There are two ways to read and shift in the
pixe ls fo r down s caling : shif t all an d shift b ypass . In the
shift all mode (the default mode) all five pixels are shifted
for each input value read and shifted in. Shift all mode
uses th e five inpu t pi xels neare st t he ou tput p ix el, in de-
pend en t of s cali ng f acto r. I n the s hift bypa ss c ase, only
the last pixel is shifted in. For example, in a down scaling
of 10 , ni ne pixe ls a re re ad an d th e 10t h pixe l is shif t ed in
to the filter. Shift bypass mode is used for large down
scaling, i.e. down scaling factors of 2.0 or greater. The
shift bypass mode is selected by setting the GET B bit in
the parameter table. It uses input pixels that are nearest
the outp ut pixe l and t hose n earest each of the four output
Figure 14-9. ICP 1/32 output resolution
12
Input Pixe ls
Output Pixels
dY
dX
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-9
pixels adjacent to the output pixel. The shift bypass
mode also fo r ces the coefficient RAM inputs to ‘0’, since
interpolation between adjacent input pixels is no longer
being pe r formed.
Using scaling to convert from YU V 4:2:0 to YU V 4:2:2
YUV information in the 4:2:0 format has the UV pixels off-
set from the input grid in both X and Y. Also, the U and V
pixels are at 1/2 of the horizontal and 1/2 of the vertical
frequencies of the Y pixels. This means the UV pixels
mus t be filt ere d and a ddit ionall y s caled in both X and Y
in or der to li ne up wi th the ou tpu t Y pixels eve n if no ini tia l
scaling is done. To generate 4:2:2 interspersed data,
vertically up-scale U and V by a factor of 2 with a start off-
set of -1/4 pixel. Upscaling by 2 generates the additional
lines required, and starting with a -1/4 pixel offset (rela-
tive to U, V spac e) moves the outp ut up to the same line
as the Y pixels. To generate 4:2:2 co-sited, then filter hor-
izontally with no scaling factor but with a start offset of -
1/4 pixel, moving the output left 1/4 pixel.
14.5.4 YUV to RGB Conversion
In the ICP, YUV to RGB conversion is done by sequen-
tially processing triplets of Y, U, and V pixel data to con-
vert the pixels to an internal YUV 4:4:4 format and apply-
ing the YUV to RGB conversion algorithm on the YUV
4:4:4 pixels. The results of this conversion normally go to
the PCI bus but can also go back to SDRAM.
YUV to RGB conversion has two steps. First the Y, U and
a V pix e l da t a are us ed to g e ne rate an R G B pix el at th e
output location. When the Y,U, an d V pixels are ready,
YUV to RGB conversion is performed using t he following
algorithms:
R = Y + 1.375(V)= Y + (1 + 3/8)(V)
G = Y - 0.34375(U) - 0.703125(V)
= Y - (11/32)(U) - (45/64)(V)
B = Y + 1.734375(U)
= Y + (1 + 4 7/ 64 )( U)
In CCIR601, the U and V values are offset by +128 by in-
v ertin g the most s igni fica nt bit of th e 8-bi t byt e. Thi s is th e
wa y the U and V va lues are s tored in SDRAM . The ab ove
algor ithm s ass um e that the U an d V values ar e co nvert-
ed b ack to normal sign ed two ’s complement v a l ues by in-
ver ting the MSB befor e be in g us ed.
14.5.5 Overlay and Alpha Blending
The ICP can add an overlay image to the main image
when in the horizontal filter to RGB/YUV mode with PCI
output. The overlay image is a user-defined rectangle
within the main image. When the over lay is active, each
overlay pixel is combined with each main image pixel to
generate the resulting pixel to be displayed. Each pixel
combina t io n is con t rolled by an al pha val u e w hich deter -
mines the proportions of overlay and main image that
contrib ute to the ou tput pi xel. T h e relation is g iv en by:
Pout = (alpha) * Poverlay + (1-alpha) * Pmain =
(alpha) * (Poverlay-Pmain) + Pmain
where: alpha ranges from 0 to 1
In the ICP, the a lpha value range is limited by the hard-
ware to five values: {0.0, 0.25, 0.50, 0.75, 1.0}.
An alph a valu e is supplied for each overlay pixel. In the
RGB 24+α overlay data format: an 8-bit alpha value is
containe d w ithin the ov er l ay d ata .
In all other overlay data formats (RGB 15+α, etc.) , an al-
pha bit in the overlay data determines the alpha value.
The alpha bit selects between two 8-bit values, alpha 1
and alph a 0, sup plied by a pair of internal IC P registers.
These registers are loaded from the parameter block
when the ICP is started. When the alpha bit is ‘1’, alpha
1 valu e is u se d as th e al ph a va lu e; whe n th e alp ha bit is
‘0’, al pha 0 is used as t he al pha value . The t wo alph a re g-
isters allow translucent images and backgrounds while
being restricted to one bit per pixel for alpha selection.
Alpha blending has several uses.
1. Alpha can be used to disable porti ons of the overlay ,
called keying. When the alpha for a pixel is ‘0’, there
is no overlay. When the alpha is ‘1’, the overlay is
100%, replacing the image. This allows the user to put
an ir regular sh ap ed obje c t in an image without show-
ing the bounding rectangle of the overlay.
2. Alpha blending allows translucent (smoky) back-
grounds and/or translucent (ghostly) overlay images
3. Usi ng alpha at the edge s of sma ll i mages such as fo nt
characters increases their effective visual resolution.
Chroma keying
The ICP also optionally provides a restricted form of
chrom a ke ying so me time s ca lled col or ke yi ng. When th e
overlay Y value is ‘0’ (an ill e gal va lu e i n t he YU V 4: 2:2 +α
format) or the RGB val ues are all ‘0’ (RGB15+α format),
the alpha value is forced to ‘0’ and no overlay or blending
occurs. This provides three levels of overlay: none, alpha
zero, and alpha one. This combination can be used to
generate an irregularly shaped menu (an oval shape, for
example) which is translucent (e.g. an alpha value of
50%) that contains opaque (alpha = 100%) letters. In a
game, this could be a message written on a foggy back-
ground in an oval window. The chroma keying provides
the definition of the oval shape, the alpha zero value de-
fines the translucent foggy background and the alpha
one value defines the opaque characters on the foggy
background.
Chroma keying in the ICP is intended for computer gen-
erated or modified overlays. Chroma keying turns off the
overlay process for selected pixels by forcing an alpha
value of ‘0’ for those pixels. Chroma keyed pixels use
special codes to identify them. These codes must be
computer generated in most cases. For example, the
DSPCPU or other CPU would proc ess an overlay image
and convert the overlay pixels to be turned off into chro-
ma keyed pixels by changing the da ta for those pixels to
the chroma k ey code.
The ICP does not have full chroma keying. F ull chroma
k eying has adjustable threshold values for the pixel com-
ponents. Adjustable thresholds allow the user to auto-
matically select an overlay sub-image from a larger over-
lay b ac kgrou nd, such as se lect ing an i mag e of an ac to r
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-10 PRELIMINARY SPECIFICATION
against a bright blue ba ckground while i nhibi tin g the bl ue
background.
14.5.6 Dithering
Sho rt ou tput co des, such as R GB 8, h ave few bits f or ou t-
put-value determination. RGB 8R has (2,3,3) bits for
(R, G,B ). Th e resu lt i s a co arse, pa tchy i mag e if not hing
is done to correct for the limited resolution. Dithering sig-
nif ican tly impr ove s th e effect ive res olut ion of thes e imag-
es. For example, RGB 8 images dithering looks nearly as
good as R G B 16.
Dithering works by adding a random dithering value to
the pixel before it is truncated by the output formatter.
The dither is added to the portion which will be truncated.
Th e carr y fr om th is ad d wi ll oc cas io nally prop agat e in to
the most signif icant portion of the p ixel before truncation.
The carry from the add thus ‘dithers’ t he displa yed val-
ue.In the example shown in Figure 14-10, a random dith-
er value is added to the original data before truncation.
The dither value should have a range of from approxi-
mately 0 to 1 LSB of the truncated value. The dither value
should be symmetrical around 1/2 the LSB of the quan-
tizing error of th e truncation. In the example shown, the
dither signal has val ues of (1/8, 3/ 8, 5/8, 7/8). This set of
values has a range of approximately 0 to 1 LSB, and it is
symm etri c al aroun d 1/2 LSB.
In this example, the input signal has a value of 2.83.
Without dithering, this value would be truncated to an
outp ut value of 2 in all cases. Averaging the un-dithered
signal over four pixels still gives you a value of 2. By add-
ing the d it he r si gn al , the outp ut valu e i s 2 o r 3 depe nd in g
on the value of t he added dither signal. Averaging over
fou r pixels, the a verage out put value is 2. 75, much c loser
to the input value than without the dither signal. The dith-
er sign al ha s s ignif ic antly redu ced th e err or w hen ave r-
aged ov e r four p ix el s .
Tw o types of d ithe ring a re c ombined in the ICP : quad pix-
el and full image dithering. Quad pixel dithering, also
known as ordered dithering, adds one of four dithering
values to each pixel. The four dithering values corre-
spond to four-pixel quads in the output image. The pixels
in each quad have fixed pos itions in the input image, so
the dither val ues ar e chosen on the bases of odd or even
line number and odd or even pixel number in the line.
The dit her values of (0/4, 3/4, 2/4, 1/4) are added by line
and pixel number: even line & even pixel, even line & odd
pixel, odd line & even pixel, odd line & odd pixel. This
gi ve s a fo ur va lu e order e d fu nc t io n fo r four adja cen t pix -
els in the image. The (0,3,2,1) pattern is chosen specifi-
cally to prevent pairs of high or low pixel values from
clustering. Spatial dithering provides a significant im-
provement in effective resolution.
Full image dithering adds a single randomly generated
number to every pixel of the image. The result is that the
intensity and color accuracy increases as the si ze of the
sam ple is enlarged. Th e r andom number ha s a long bit
length to prevent repeating patterns in the image. The
random number can be static or dynamic. In the static
case, the random nu mber generator s tarts with a f ixed
seed at the start of the image. The random number spa-
tial pattern is fixed for the image even t hough the image
data may change from frame to frame. In the dynamic
case, the random number generator runs continuously,
and the di t her ing patter n cha ng es from frame to f rame .
The ICP combines quad pixel dithering with full image
dithering to provide the final dithering signal for each pix-
el. The quad pixel dither provides the two most signifi-
cant bits of the dither signal, and the full image dither pro-
v ides the leas t significant 4- bits of the d ither signal. The
c ombined dith er signal is 6 bits.
From 1 to 6 bits of dither signal are used, depending on
the output format. If fewer than 6 b its are needed, only
the MSBs of the dither signal are used. For example in
the RGB 8R output format, the R output value is 3 bits in
siz e. The output uses the 3 MSBs of the R input value
and t runc ates th e 5 LSB s. The di ther u nit add s 5 bits of
dit her s ign al ( the 5 MSB s) to t he 5 LSB s o f the R inpu t
v alue before truncati on, and the RG B formatter truncates
the result after adding.
0
1
2
32.830
Dither = 0
Output = 2
0
1
2
32.955
Dither = 1/8
Output = 2
0
1
2
33.205
Dither = 3/8
Output = 3
0
1
2
33.455
Dither = 5/8
Output = 3
0
1
2
33.705
Dither = 7/8
Output = 3
No Dithering:
Output = 2.0 1/4 LSB Dithe ring
Ou t p ut = ( 2+ 3+3+3)/ 4 = 11/4 = 2.750
Error = +0.830
No Dithering 1/4 LSB Dithering
Error =(2.830 - 2.750) = +0.080
Figure 14-10. Dithering
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-11
14.5.7 Implementation Overview: Horizontal
Scaling and Filtering
Figure 14-11 sho ws a data flo w bl oc k di agr am of the ICP
horizontal scaling algorithm implementation. Blocks of
pixels a r e pr ov ided by the i nput bl oc k buffer. Eac h bloc k
of pixels is transferred sequentially to the 5-tap filter. The
fi lter d oes sca lin g and f ilter ing of the d ata a nd puts th e re-
sulting pixels in the output buffer. Complet ed pi xels in t h e
output buffer are written back to SDRAM or to the PCI
output. A bypass multiplexer allows the filter to be by-
passed for SDRAM to SDRAM block moves.
Input pixel access is controlled by the Y Counter. The Y
Co unter selects th e word and byte for th e cu r rent pixe l in
the Y FIF O bu ff er. The Y In crem ent regi st er, Y LSB Re g-
ister and the Y MSB Counter control the increment of the
Y C ounter. If the Y MS B Counter co ntents is not ‘0’, the
Y Cou nt e r is i nc reme nt ed and the Y MSB r egi st er i s de c-
rem e nted un ti l th e Y MSB Cou nt er is ‘0’.
Th e Y MS B Cou nter is loaded w ith the integer po rt i on of
the results of the Y Counter Increment operation. Y
Co un ter Incr e ment i nvo lv es ad di ng the Y I ncre men t frac -
tion an d inte ger values to the Y LS B reg ister and Y MSB
Counter, respectively. If there is no scaling (scaling fac-
tor = 1.0), t he Y Increment integer value will be ‘1’, and
the Y Increment fractional value will be ‘0’. Each Y
Counter Increment operation will increment the Y
Counter by one in this case.
The Y Cou nt er keeps trac k of h ori zo ntal l y in dex ed pix el s
sent to the filter. The Y Counter is incremented once (1.0
for no scaling) for each pixel. For a line of pixels begin-
ning with Xa and e ndin g with X b, the Y Coun ter re ads pix-
els from the block buffer beginning with Xa-2 and ending
with Xb+2. Th e extr a pixe ls ar e requi red by the 5- tap filt er,
wh ich us es a to tal of 5 pixe ls to gene rat e each outp ut pix-
el, two pi xels before a nd t wo pi xel s af ter eac h pixel. Th e
horizontal filter uses the current output from the block
buf fer an d four delaye d ver sion s of it to generat e the fil ter
out put as th e w eigh ted sum of th e ce nt er pix el p lus the
tw o on e it he r si de . (F or t he case wh ere the s cal i ng fa ct or
= 1.0, the LS Bs are always ‘0’.)
For up o r down s caling, the Y Increment value is not 1.0,
it is the inverse of the scaling factor (See “ICP scaling
output resolution,” on page 14-7). For up scaling by a
factor of 2.0, the effective Y increment val ue is 0 .5, for
exampl e. Th is mean s two outpu t pix els ar e generated for
each input pixel. The Y Counter effectively increments as
0.0, 0.5, 1.0, 1.5, 2.0, etc. The LSBs of the counter (i.e.
the fractional part less than 1) in the Y LSB register are
use d by t o the fil ter to g e n erate the inter mediate values.
An LSB value of 0.5 indicate s that the output pixel is half
way between X n and X n+1. The f ilter c ont ains a set of 5
filter parameter RAMs, one for each coefficient. The 5
most significant LSBs from the counter select the filter
coefficients which will generate the correct value for the
output pixel at the relative offset from 0.0 indicated by the
LSBs.
SDRAM
To SDRAM
Y MSB Cntr
Pixel Clock
5 Stage Multipli-
er-Accumulator
Y LSBs
Reg
Reg
Reg
Reg
Pixel Data
a+2 RAM
a+1 RAM
a+0 RAM
a-1 RAM
a-2 RAM
Z Counter
Mux
Bypass
Bypass
SDRAM
Address
Block
Y Co unte r
Y Incr Fraction
Y LSB Reg
Carr y Out
Filter Source Select
5-tap Filter
YUV Code Delay
Y Incr Integer
N Byte Inc r
Figure 14-11. ICP horizontal scaling data flow block diagram
Output
Buffe rs 6,7
Bloc k FIFO
Buffers 0,1
Block FIFO
via
highway
or PCI
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-12 PRELIMINARY SPECIFICATION
The Y Counter indicates the next pixel from the input
buffer. A new pixel is clocked into the filter registers only
when the Y Counter contents change, which happens
when the Y MS B Counter is loaded with a value greater
than ‘0’. Note that for Y increment values less than 1.0
(up scaling), the change will be caused by carry incre-
ment from the Y LSBs, and a new pixel will not be
cl oc k ed into the f il t er sh ift re gister on ev ery Y cloc k .
For increment values of 2.0 or for values of 1.0 or greater
with carry in (down scaling), multiple new pixels will be
cloc k ed in to th e filte r s hi ft regis te r befo re th e filter inpu ts
are ready. The number of new bytes needed fo r the nex t
pixel is the sum of the Y Increment Integer value and the
carry out of the Y LS B adder. This r esult is loa ded into
the Y MSB Counter. The filter clock is stalled until the in-
puts are ready. The integer value of the increment -- in-
cludin g carry -- defines the n umber of n ew pixels to be
cloc ked thr ough the shi ft regi ster b efore the fi lter in puts
are r e ady f o r use.
In thi s d iscussi on, the Y Co unter LSBs form a 16 -bit bi-
nar y n umber . The u pper 5 bi ts of this 16-bit number form
a 5- bit bi nar y num ber be twe en 0 a nd 31 r epresenting a
fractional distance between Y pixels between 0/32 and
32/31. If the new pixel relative distance is 31/32, it is
nearest the right pixel of the two pixels it is between, and
the righ t 2 pi xels will be more heavi ly weighted than the
left 3.
The horizontal filter shown in Figure 14-11 is pipelined to
generate a pixel for every integer increment of the Y
Counter. The filter input is always 5 clocks ahead of its
out p ut. T h e fi r st s tag e gene r a tes the f ilter term an+2Xn+2
usin g the data from the input block an d the an+2 coeffi -
c ient from the coefficient RAM driven by the Y LSBs. The
s econd s tage r egisters hold the data for Xn+1 and its cor-
responding Y LSBs and generate an+1Xn+1. The last
st age reg ist ers ho ld th e da ta for X n-2 and the Xn-2 LSBs
and gene r at e an-2Xn-2.
The LSB Register contents can change on every clock.
In t he 2:1 s cal i ng ex ample, th e LSB s al te rnated between
0.0 and 0.5. The LSB Counter represents each output
pixel’s x offset value from the input pixel grid. The LSB In-
c rement value is 16 bits long. The 5 upper bits go to the
c oeff i ci ent R AMs , and t he 1 1 lo wer b its pr ov id e prec is io n
increme nt of the LS B C ounte r for precision in repres ent-
ing the sc al i ng fa ct or . The 11 lower bi ts of the LSB Incre-
ment valu e adde d to the 11 lower bi ts of the LSB Counte r
determine when to increment the 5 LSBs that drive the
coefficient RAMs and when to clock a new Y pixel into
the filter.
14.5.7.1 Loading the extra pixels in the fi lter
For a 5-tap filter, 4 more pixel inputs are needed to the
filter than are generated at the filter output, two before
the first pixel and two after the last pixel. In the worst
c ase of a wi ndow that is ex act ly N bl oc ks wi de and star ts
at the first pixel of the first block, t wo e xtra b locks mus t
be read - one at each end of the window - in order to get
these 4 pixels! This is an unavoidable problem with a
multi-tap filter. For an n-tap filter, n-1 extra pixels are
needed. There are two techniques that avoid this effi-
ci en c y hit of f e tc hi ng ex tr a b l oc k s.
1. M ove the w indow e dges so t hey are not w ithin 2 pi x -
els of a 64 input pixel boundary.
2. Simulate t he ed ge pixels, su c h a s b y mirror ing the
pair of pixels you have on the other side. This is the
only solutio n to the probl em of st arting (o r ending) a t
the edge of the image , where there are no pixels to
the left (or right) of the image window.
The ICP us es a utom at ic mirro r ing t o su pp ly these pixel s.
Mirroring is used in both horizontal and vertical filter
modes.
14.5. 7.2 Mirroring p ixels at the ends of a li ne
A line m ay s tart and/or e nd at the edge of the input im-
age. In this cas e, t he t w o start and/or end p ix els needed
for the first and last pixels of the line, respectively, are
mis sing . T he st art mi rror us es the tw o p ix els to t he righ t
of th e first pixe l, and the end mirr or uses th e two pixe ls to
the right of the last pixel. These pixels are supplied by
controlling the Y counter.
A mirror mult ipl exe r i n the 5 -tap filter provides m irroring
of o ne or tw o pix el s a t the filt er in p uts. This mirro r m ulti -
plexer is us ed for b oth horizo n ta l an d vertica l filtering. I n
hor iz ontal f il ter in g, the first a nd la st tw o pixe ls in the line
are mirro red. T he mirror mu lt iplexe r is set to the appro-
priate mirror code for the first and last two pixels in the
line. The first two pixels are mirrored for the first two clock
pulses, and the last two pixels are detected using the pix-
el counter for the line.
Mirroring is optional , depending on whet her the start or
end o f th e line is on a win dow boun dary . Th e D SPC PU
or microprogram must d etect this and enab le start and/or
end mir rorin g as req ui r ed .
14.5. 7. 3 Horizontal filter SDRAM ti ming
Figure 14-13 show s a ti m ing di ag r am for block d ata fl o w
between the SDRAM and the filter for a scaling factor of
1.0 . The bu s block re ad s an d wr ite s ar e o ne fou r th of th e
fi lter pr oce ssing time because the fil ter processes data at
10 0 Mpi x/se c, an d th e SDRA M re ad s and write s blo cks
of pixels at 400 Mpix/sec. The SDRAM logic reads the
next block while the current block is being processed.
This also provides the two pixels from the next block re-
quir e d to finis h filter in g the c urr e nt bl ock .
If the scaling factor is greater or less than 1.0. the
SDRAM bus activit y will be different. For scaling fact ors
gr eate r than 1.0, t here will b e fewer S DRAM r eads for the
s ame numb er o f writ es gen er ate d b y t h e fi lt er. For ex am-
ple, a scale factor of 2.0 means that it is necessary to
re ad on ly half as many b lock s to gener ate th e sam e num-
ber of output blocks. For a scale factor less than one,
th ere w ill be m or e r ead s f o r th e s ame nu mbe r o f w rite s .
For a scale factor of 0.5, two blocks must be read for ev-
ery block of output. If the scale factor is less than 1/3,
more time will be spent reading and writing SDRAM than
filtering.
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-13
14.5.8 Implementation Overview: Vertical
Scaling and Filtering
Figure 14-14 sho ws a data flo w bl oc k di agr am of the ICP
vertical scaling algorithm implementat ion. Bl oc ks of pix-
els are loaded sequentially into five input block buffers,
one for e ach of the 5 terms of the 5- tap filter. Each bl ock
of pixels is transferred sequentially to the 5-tap filter. The
fi lter d oes sca lin g and f ilter ing of the d ata a nd puts th e re-
sulting pixels in the output buffer. Complet ed pi xels in t h e
out p ut buffer are w ritten ba c k to SD R AM .
In vertical scaling, five separate blocks of pixels, one for
each li ne, are req uir ed be caus e the pixe ls ar e sto red in
hor izo ntal se quenc e in t he SDRAM . The Y Co unter steps
through the 64 ho rizontal pixels of th e fi ve input blocks
and writes the resulting pixels into the output block. Four
of th e fi v e bl oc ks a re us e d on the ne xt pas s, so t ha t one
blo ck of pixe ls in gene rates one b lock o f pixe ls ou t exc ept
for end conditions. The image is processed in 64-pixel
columns. Since the image to be filtered will not generally
s tar t or en d on a bl ock bou nd ar y, th e num be r of hori zo n-
tal pixel s for th e fir st an d last col umns wil l be les s than 64
in these cases. Also, the data in the columns must be
aligned vertically. This results in the requirement that the
li ne -t o - lin e ad dres s of f se t value mu st be a multiple of 64
byt e s. N ote that only the ad dress off s e t valu e is mo du lo
64; the image to be filtered can start and stop anywhere.
Block al ignment is not req uired.
Ver ti ca l s cal i ng an d fi lt e rin g p roce ss es five 64-pi xe l i nput
line s egm en t s t o ge nerate one 64-pix el ou t pu t segm ent.
When input lines Yn-2 to Yn+2 have been processed to
genera te one 64-pixel output segment for output line Yn,
five new input segments are needed for the next output
line segment in the 64-pixel column, Yn+1. If the ver tical
scale factor is 1.0 (no scaling), line segments Yn-1 to
Yn+2 ar e re used , a ne w blo c k fo r Yn+3 is loaded and the
block f o r li ne Yn-2 is discarded.
To load Yn+3, the MCU adds the Y offset value to the
block address (upper 26 bits) of the Y Counter, and the
Y Counter selects the next Y block to be read from
SDRAM. The Y Counter points to the line block address
for last Y block loaded, and the Y offset value is the ad-
dress difference between the start of one line and the
start of the next, X0Y0 to X0Y1. The line offset is always
an integral number of SDRAM blocks. The line offset val-
ue must b e add ed to t he c urre nt lin e ad dres s to ge t the
next line address.
Up and down scaling u se the U Counter and U Increment
valu e. Th e U Co unte r is use d to de te ct how man y lin es
must be re ad (0 to 5) to gene rate th e next output li ne and
to gene rate t he v ertic al of fs et fr acti on fo r the 5-t ap fi lter
for output lines that fall betwee n the input lines. The U
Counter is set to its starting value (typically ‘0’) at the
start of the column, and the U Increment value is added
to the U Counter for each output line segment generated
in t he col umn. Fo r a sc aling f acto r of 1. 0, the U In creme nt
value is 1.0 , and eac h line proc es s ed w i ll g en er a te a r e -
quest for one block. If the scaling factor is 1/2, the i ncre-
ment value will be two, corresponding to moving down
tw o lines. In th is case , twic e the li ne off set is added to the
Y Counter value.
For up scaling by a factor of 2.0, the Y increment value is
0.5. This means tw o output lines are generated for each
input line. The U Counter increments as 0.0, 0.5, 1.0, 1.5,
2.0, etc. The LSBs of the U Counter (i.e. the fractional
par t le ss than 1) are passed along to the fil ter to generate
the intermediate values. An LSB value of 0.5 means that
In p ut Pixel s: Y
Output Pixels: Y’
123456
Y’=F(Y3,Y2,Y1,Y2,Y3)
Y’=F(Y2,Y1Y2,Y3,Y4)
Y’=F(Y1,Y2,Y3,Y4,Y5)
Y’=F(Y2,Y3,Y4,Y5,Y6)
Y’=F(Y3,Y4,Y5,Y6,Y5)
2N: Y’=F(Y 4,Y5,Y6,Y5,Y4)
(3) (2) (5) (4)
Mirrored P ix e ls
Figure 14-12. Horizontal Pixel Mirroring
SDRAM Bus
Filt er A c tio n
Read X0 Write Xa
Read X1
Filter X1 => Xb
Filter X0 => Xa
Read X2 Write Xb
Filter X2 => Xc
Read X3
Figure 14-13. SDRAM and horizontal filter block timing
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-14 PRELIMINARY SPECIFICATION
the outp ut line is half way bet ween Y n and Yn+1. T he fil ter
cont ai ns a s et of 5 filt er p aram eter RAM s, o ne for each
coefficient. The 5 most significant LSBs from the counter
select the filter coefficients wh ich will generate the cor-
rect value for the output pixel at the relative offset f rom
0. 0 indic ated by the LSBs.
For down scaling, the increment factor will be greater
than one. If the increment factor is 2.0, two new blocks
wi ll have to be load ed bef ore st ar tin g th e nex t vert i ca l fi l-
ter pass. If the increment factor is 5 or greater, all five
blocks must be loaded. The number of blocks to be load-
ed for the next line is equal to the integer increment value
plus ca r r y out fr om th e L SB po rtion o f t he U Counte r in-
crement.
Note that the LSB ad der carry out is available before the
U Counter has been updated. This allows the current U
Counter value LSB bits to be used for the filter coeffi-
cients while using the carry out for the next value to pre-
dict how many blocks to fetch. The integer value from the
U in cremen t value plus the carr y in fro m the LSB por tion
of the Increment adder is the number of blocks to be
loaded. These blocks must be sequentially loaded (and
not skipped) so that th e filter has the necessary 5 adja-
cent lines to perform the filtering. The contents of the in-
teger portion of the U Counter (updated after the add) are
not used.
Only one new block can be loaded while the current line
is be ing p r oc es s ed . If two o r more bl oc ks are n eede d t o
process the next line, load one in overlap. Wait until the
current line is done, then load the rest of the blocks. The
microprogram only has to make two decisions for the
next line: is the increment value ‘0’ or greater than ‘0’,
and if gre ater than ‘0’, is it greater than five. If it is ‘0’, do
nothing: you will reuse all five blocks. If it is 1-4, load the
next block. If it is fi ve or more, calculate the address of
th e fir st block - - by adding N tim es the address offset to
the Y counter -- and fetch it.
When a new block is loaded and it is time to process the
next line, the block which was Yn+2 becomes Yn+1. The
Y blocks, in effect, shift up one line as you scan down the
image. This shifting action is implemented by shifting the
block select codes in the Filter Source Select Register
(FSSR). The FSSR contains six 3-bit register fields.
Th ese 3-b it fie lds are ro tat ed by a shif t command to th e
FSSR. The output of five of the FSSR fields go to the in-
put mul tiple xer, wh ic h select s the next block combi natio n
and sends it to the filter. The output of the sixth field is the
free block to be filled for the next line while the current
lin e i s be in g pr oce ss ed. The sele ct code is als o t he bloc k
code (0 to 5), so the free block is identified by its block
code in the FSSR. The FSSR codes for the six cases of
vertical filter ing are shown in Table 14-4.
SDRAM
To SDRAM
Output Buf fers 6,7
Bloc k FIFO
Y Counter
Yn + 2 Buffe r
5-tap Filter
a+2 RAM
a+1 RAM
a+0 RAM
a-1 RAM
a-2 RAM
Yn+1 Bu ffe r
Yn+0 Bu ffe r
Yn-1 Bu ffe r
Yn-2 Bu ffe r
U Incr Integ er
U LSBs
U LSB Reg
U Incr Fraction
Z Coun te r
Fil t er S our ce Selec t
6 In x 5 Out
Multiplexer
FSSR
Y Lin e cl oc k
Line Clock Carry
Byte Index
Pixel Clock
Block Count
to Microcode U MSB Cn tr
Block Address
to SDRAM
Output
Pixel clock
Figure 14-14. ICP vertical scaling data flow block diagram
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-15
14.5.8.1 Mirroring lines at the ends of an
image
A windo w may start and /or en d at the edge of the input
image. In this case, the two start and/or end lines needed
for the first and last lines of the window, respective ly, are
missing. These pixels are supplied by the mirror multi-
plexer at the 5-tap filter which m irrors the input lines.The
mirror multiplexer is controlled by the mirror counter and
mir ror end re gi ster i n t he sa me m ann er a s in h oriz ont al
filtering. The mirror register in vertical filtering is incre-
mented by the output line counter. Mirroring is performed
on the first two and last two lines of the column. Mirroring
is optiona l, depen ding on whether the start or end of the
lin e is on a win dow boun dary. The DSP CPU or mi cropr o-
gram must detect this and enable start and/or end mirror-
ing as required.
14.5.8.2 Vertical filter SDRAM block t iming
Figure 14-15 sho w s a ti mi ng di ag r am for block d ata flo w
between the SDRAM and the filter for a scaling factor of
1.0 . The bu s bl oc k rea ds a nd wri tes r e quir e o ne four t h of
the filter processing time because the filter processes
data at 100 Mpix/sec, and the SDRAM reads and writes
blocks of pixels at 400 Mpix/sec (peak). The vertical filter
s tar ts by re adin g in th e five bl ocks neces sary to generate
the next output block. While the current block is being
processe d, the next block is read fro m SDRAM to pre-
pare for the next output block.
14.5.9 Horizontal Scaling and Filtering for
RGB Output
Figure 14-16 sho ws a data flo w bl oc k di agr am of the ICP
hor izon tal s calin g to R GB ou tput al go rithm impl emen ta -
tion. The six input block buffers are arranged as three
block FIFOs, one each for Y, U and V pixel streams.
These three streams are sequentially filtered, pixel by
pixel by the 5-tap filter to generate a scaled output se-
quenc e of Y, U, V, Y, U, V, e tc . Th is YU V stream is f ed
to the YUV to RGB converter where it is converted to one
of several RGB output formats, blended with RGB over-
lay pixels supplied by the Overlay FIFO and masked by
bit mask pixels from the bit mask block. The resulting
scaled, converted, overlay blended and masked RGB
stream is sent to the PCI interface -- typically to an RGB
format frame buffer on the PCI bus -- or to SDRAM.
Th e inpu t pix el stre ams fro m the i nput FIFO s are tra ns-
fer re d se qu en tial l y to the 5- t ap filt e r. E ac h str ea m has it s
own set of four-stage delay registers used to perform
horizontal filtering on the stream. A pair of 3 -way mu lti-
plexers switch the five filter data inputs and the 5-bit filter
coefficient select codes to the 5-tap filter. This set of mul-
tiplexers is d riven by the YUV Sequen ce coun ter, a 2-bit
counter that provides the YUV processing sequence.
In horizontal scaling and filtering from SDRAM to
SDRAM, each Y, U and V component is filtered sepa-
rately as a complete image. In RGB output horizontal
scaling and filtering, the image is processed as three in-
terwoven streams of all three YUV co mponents.
In the RGB output mode, the ICP normally generates
RGB data and writes it into a frame buffer memory on the
PC I bus o r to t he SD RAM . The fram e buf f er me mor y for-
mat is RG B wi t h on e R, one G a nd on e B va lu e p er pi xe l.
This could be called RGB 4: 4:4. To generate this imag e,
the ICP generates a YUV 4:4:4 image and converts it to
RGB. This process is done one RGB output pixel at a
time. The ICP generates a U pixel and saves it in a reg-
ister, generates a V pixe l an d saves it in a register, then
generates a Y pixel for output. The YUV to RGB convert-
er combines each Y pixel as it is generated with the pre-
viousl y stor ed U and V pix els to gene rate t he RGB ou tput
data. This process is repeated until the whole image has
been c on v er te d and se nt t o th e PC I bus o r SD RAM.
14.5. 9.1 YUV sequ ence counter in YUV 4 :2:2
output Mode
For RGB output formats, the YUV data must be scaled to
YUV 4:4:4 format before conversion to RGB. The YUV
data in SDRAM is typically stored in YUV 4:2:2. This
means that the U and V data must be upscaled by 2 rel-
ative to the Y data to generate the internal YUV 4:4:4 for-
mat required for RGB conversion.
Fo r the Y UV 4:2: 2 o utpu t fo rmat s, t he U an d V data do
not need to be up scaled to 4:4:4. The YUV 4:4:4 data
would be upscaled only to be decimated back to YUV
4:2:2. For YUV 4:2:2 output, the U and V pixels are used
twice . T his is done by having a hal f- speed mode f or th e
YUV Sequence Counter. In this mode, t he sequence is
U0, V0, Y0, Y1, U2, V2, Y2, Y3, etc. The U and V are not
Table 14-4. FSSR codes for vertical filtering.
Case Pn-2 Pn-1 Pn+0 Pn+1 Pn+ 2 IO B lock
154321 0
205432 1
310543 2
421054 3
532105 4
643210 5
SDRAM Bus
Filter Action
Read Y5 Write Ya
Read Y6
Filter Y3-6 => Yb
Filter Y2-5 => Ya
Read Y7 Write Yb
Filter Y4-7 => Yc
Read Y8
Figure 14-15. SDRAM and vertical filter block timing
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-16 PRELIMINARY SPECIFICATION
up s c aled by 2 re la ti ve to the Y com po nen t for YUV 4:4:4
out p ut, a lt h ou gh they c ou ld b e u p scale d as p art of gen -
era l up s calin g of the im age.
The YUV 4:2:2 output mode also provides higher pro-
c essing ban dw idth relative to YUV 4: 4:4 up scaling. Half
as many U and V pixels are pr ocessed.The output pixel
rat e is one pixel per 20 nanoseconds for the YUV 4:2:2
output mode versus one pixel per 30 for conversion to
YUV 4:4:4. This can be used to provide some processing
performance improvement for very large images at the
expense of some chroma quality.
14.5. 9.2 PCI output block ti ming
The IC P out puts pixel s to th e PCI in ter face at a peak rate
of 3 3 Mpix /s ec in RGB mod e an d 50 M p ix / s econ d in t he
YUV mod e usin g YUV sequ enci ng. For one wor d per pix-
el output codes, such as RGB-24, this is a peak rate of
33 Mword s/se c o r 132 M pix/ sec in the R GB sequen cing
mod e. Th is is t he sam e sp eed as the 13 2 M B/sec peak
rate of the PCI interface. (At 50 Mpix/sec, the result
would be 200 MB/sec.) The BIU control for the PCI inter-
fa ce has a FIFO for buffe ring data fr om the IC P , but this
buffer is only 16 words deep. Therefore, the ICP wil l oc-
cas io na lly h av e to w a it for the PCI to acce pt more d ata.
In the PCI output mode, this stalls the ICP clock.
1 4.6 OP ER AT IO N AN D PR OG RAM MI NG
The ICP uses a combination of hardware and a Micro-
program Control Unit (MCU) to implement its scaling, fil-
tering and conversion functions. The microprogram is a
To PCI
5 Stage Multiplier-
Accumulator
Y, U, V LSBs
Reg
a+2 RAM
a+1 RAM
a+0 RAM
a-1 RAM
a-2 RAM
Y Counter
Y LSB Counter
Buffers 0,1
Block FIFO
Filter Source Select
5-tap Filter
Reg
Reg
Reg
Reg
U Counter
U LSB Counter
Buffers 2,3
Block FIFO Reg
Reg
Reg
Reg
V Counter
V LSB Counter
Buffers 4,5
Block FIFO Reg
Reg
Reg
OL Counter
B, BX Counter
Buffer 8
Bit Mas k
Buffers 6 ,7
Overlay
FIFO
Multiplexer: Y, U, V Select
Mux
YUV to RGB Conversion, Formatting, Alpha Blending & Bit Masking
YUV
Counter
Sequence
Pixel
Clock Y, U , V Data FIFO Clocks
Mirror Multiplexer
Y Mirror Cntr
U Mirror Cntr
V Mirror Cntr
Mux
RGB to SDRAM case
RGB to PCI c ase
Figure 14-16. ICP horizontal scaling for RGB output data flow block diagram
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-17
fac t ory- supp lie d s ta te ma ch in e th at resid es in SDR AM. It
is read each time the ICP executes an operation. Using
an SDRAM-re sident microprogram -controlled state ma -
c hine min imi ze s har dwa re and pro vid es fl ex ib ilit y in ha n-
dling spe c ial con ditions wi thout additional ha rdware .
Impor tant Not e: You must set the ICP DMA Enable bit
(IE) in the BIU_CTL register of the PCI interface for RGB
output to PCI. This bit must be set before initiating RGB
to P CI oper ati on s, or th e ICP wil l stal l w aiti n g fo r the P CI
to become ready. Refer to Section 11.6.5, “BIU_CTL
Register.”
14.6.1 ICP Register Model
The ICP is controlled by the DSPCPU through five MMIO
registers: the MicroProgram Counter (MPC), the Micro
Instruction Register (MIR), the Data Pointer (DP), the
Dat a R eg is ter (DR) and t he I C P S tat u s r eg ist e r ( SR ), as
show n in Figure 14-17. Th e MPC , DP an d SR ar e us ed
in normal operations, and the MIR and DR are used in
test and debug. Note that the MMIO registers should
never be written while the ICP is executing microcode, i.e
test the Busy bit in the SR register before writing any ICP
MMIO register.
The MP C is the MCU instruct ion coun ter. It points to t he
next microinstruction to be executed. The entry point in
the microprogram defines which ICP operation is to be
executed.The DP po ints to the locati on in SDRAM of a
table of parameters used by the ICP to process the im-
age d ata, such as the ima ge inpu t and output start ad-
dre s ses, s caling factor , etc.
The SR has 1 3 ac ti ve bits : Bus y (B ), Done (D), don e In -
terrupt Enable (IE), ACK_DONE (A), Little Endian (L),
Step (S), Diagnostic (DG), Reset (R), Priority Delay (PD,
4 bit s) . Bi ts 12 .. 30 a re r es erve d.
•(B)usy indicates the ICP is busy executing micro-
code.
•(D)one indicates that the previous requested function
is complete, and that the ICP clock is stopped.
•(D)one causes an interrupt to the DSPCPU when
Interrupt Enable is set.
•(A)CK_DONE clears (D)one and the corresponding
interrupt.
•(L)ittle Endian sets the highway endian swap multi-
plexer to little endian mode for data on the SDRAM
bus.
•(S) tep cau se s the MCU to execut e on e micr oin str uc-
tion. Step is used for diagnostics to step the ICP
th rough its m icroins t ruc t ion s one c lock step at a ti me .
Writing a ‘1’ to Step sets Busy, which is reset at the
end of exec ut i on of the next mi croin s t ru ctio n .
•(DG) allows SDRAM operations in step mode.
•(R) is a write-only bit that resets ICP internal regis-
ters.
•(PD) sets a timer for bus activity that defines the min-
imum bus bandwidth available to the ICP.
The ICP Status Register contains 20 read-only status
bit s. The uppe r 16 bit s o f th e S tat u s Reg i st er c an con tai n
a 16-bit code returned by the microprogram upon com-
pletion. B it s 15 thr ou gh 12 are reser v ed for error flags.
Impor tant Not e: Yo u mus t s et t he ICP DMA Enabl e b it
(IE) in the BIU_CTL register of the PCI interface for RGB
output to PCI. This bit must be set before initiating RGB
to P CI oper ati on s, or th e ICP wi l l stal l wai ti ng for th e PCI
to become ready. Refer to Section 11.6.5, “BIU_CTL
Register.”
14.6.2 Power Down
The ICP block enters in power down state whenever
PNX1300 is put in global power down mode.
Mi c r oP rogram C ounter ( M P C, ICP_MPC)
Data Pointer (DP, ICP_DP)
ICP Status (ICP_SR) D
10
31
31 0
BIE
2
Mic roIn s truc ti on R e gi ste r (MIR, IC P_M IR)
Data Re gister (DR, ICP_DR)
3
ALS
45
0x10 2400
0x10 2404
0x10 2408
0x10 2410
0x10 2414
MMIO Offsets
Priori ty Delay
12 11 6
DGR
78
Figure 14-17. ICP MM IO Registers
30
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-18 PRELIMINARY SPECIFICATION
Th e IC P bl o ck ca n be separatel y po wered down by se t-
ting a bi t in the BL O CK_POWE R_ D O WN re gi st er. Refer
to Chapter 21, “Power Management.”
It is recommended that ICP is in an idle state before
bl oc k level pow er dow n is ac ti vated.
14.6.3 ICP O peration
Th e DSP CPU com man ds th e IC P to perf orm a n op era -
tion by loading the DP with a pointer to a parameter
block, loading the MPC with a microprogram start ad-
dress and setting Busy in the SR. For example to cause
the ICP to scale and filter an image, set up a block of
SDRAM with the image and filter parameters, load the
MPC with the starting address of the appropriate micro-
program entry point in SDRAM, load the DP with the ad-
dre ss of the par amet er bl ock, and se t Bus y in t h e SR b y
writ ing a ‘1’ to it. When the filter operation is complete,
the ICP will set Done and issue an interrupt. The
DSPCPU clears the interrupt by writing a ‘1’ to
ACK_DONE. Note: The interrupt should be set up as a
‘level triggered.’
Wh en the D SP C P U se t s Bus y , the MC U be gins reading
the microprogram from SDRAM. The microinstructions
are read in from SDRAM as required by the ICP, and in-
ternal pre-fetching is used to eliminate delays. Setting
Busy e nables the MCU clock, the first block of microin-
st ructi on s is au tom atica ll y read in, and th e MC U begi ns
instr uc t i on e xecution at th e current address in the MPC.
Clearing Busy stops the MCU clock. Busy can be cleared
by hardware reset, by the MCU, or by the DSPCPU.
Hardware reset clears the Status register, including Busy
and Done, and internal registers, such as the TCR.
When the MCU completes a microprogram operation,
the mi cropro gram typical ly cle ars Bu sy and sets Done,
causing an interrupt if IE is enabled.
The DSPCPU performs a software reset by clearing
(writing a ‘0’ to) Busy and by writing a ‘1’ to R eset. T he
DSPCPU can also set Done to force a hardware inter-
rupt, if desired.
14.6.4 ICP Microprogram Set
The ICP comes with a factory-generated microprogram
set which implements the functions of the ICP. The mi-
croprogram set includes the following functions:
1. Lo ad in g t he fi lter c o eff ic ient RAM s.
2. Horizontal scaling and filtering from SDRAM to
SD RAM of an inpu t image to an out pu t i ma ge. The i n-
put and o utpu t image s can be of any s iz e and posi tion
that fi ts in SDRA M. Th e sc alin g f actor s are, in g e ner-
al, limited only by input and output image sizes.
3. Vertic al scal i ng an d fil t ering fr om SDRA M to SDR AM
of an i np ut imag e t o an ou tp ut im a ge. The i np ut and
output images can be of any size and position that fits
in SDRAM. The scaling factors are, in general, limited
only by input and output image sizes.
4. Horizontal scaling, filtering and YUV to RGB conver-
sion of an input image from SDRAM to an outpu t im-
age t o PC I or S D RA M , wi th an al ph a-blende d and
chroma-keyed RGB overlay and a bit mask. The input
and output ima ges can be of any size and position
tha t fit i n SD RA M a nd ca n be ou tp ut to t he PC I bus o r
SDRAM. In general, scaling factors are limited only by
input and o utput image sizes.
The microprogram is supplied with the ICP as part of the
device driver. The entry point in the microprogram de-
fi ne s whi ch I CP oper at ion is to be done . The ent ry poin ts
are given below in terms of word of fsets from the begin-
ning of the microprogram:
Offset Function
0 Load coefficients
1 Horizontal scaling and filtering
2 Vertical scaling and filtering
3 Horizontal scaling, filtering, YUV to RGB
c onversion, bit masking (P CI) and over-
lay ( PCI) with alpha blending and
ch roma keying
14.6.5 IC P Pr ocessing Ti me
The pr ocessi ng time for typi cal operations on typica l pic-
tu re si zes has be en m easu r e d.
Measure ments were perform ed with the following co nfig-
uration:
•CPU clock and SDRAM clock set to 100 MHz
•PCI clock set to 33MHz
•All measurement with PCI as pixel destination were
done with an Imagine 128 Series II graphics card,
which never caused a slowdown of the ICP opera-
tion.
•TRITON2 mother-board with SB82437UX and
SB82371SB based Intel Pentium chipset.
•PNX1300 arbiter set to default settings
•PNX1300 latency timer set to maximum value = 0xf8.
•Overlay sizes were the same as picture sizes.
Results are tabulated below for three different cases of
availa ble me m or y b an dw i dth :
1. No other load to SDRAM, i.e. full SDRAM bandwidth
avai labl e f or ICP. See Table 14-5.
2. SDRAM memory loaded to 95% of its bandwidth by
DCACHE traffic from DSPCPU. Priority delay = 1, i.e.
IC P did wai t on e blo ck time before comp e ti ng fo r memo-
ry. See Table 14-6.
3. SDRAM memory loaded to 95% of its bandwidth by
DCACHE traffic from DSPCPU. Priority delay = 16, i.e.
ICP did wait 16 block times bef ore competing for memo-
ry. See Table 14-7.
Note: A load of 95% of the memory bandwidth is very
rar ely found in a real system. So the results in these ta-
bles may be useful to estimate upper bounds for the
compu t a tio n time in a lo aded s ys tem.
The priorit y delays were set to the mini mum and m axi-
mum p oss ible va lues , so the co m putat ion t ime for othe r
priority delay values should be somewhere in between.
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-19
A si mpl e line ar m odel of com put ati on tim e has been fi t-
ted to the tabular data and to corresponding measure-
ments with half the number of pixels per line.
It was assumed that
processing time = (time per line start)* (number of lines)
+(time per pixel) * (number of pixels)
Table 14-8, Table 14-9 and Table 14-10 give the time
per line start and the time per pixel in this equation for the
th ree m em or y ba nd w id t h ca se s .
The maximum deviation between measured time and fit-
ted model is on the order of 10% in the range W = 180 ...
1024, H = 240 ...768. The deviation is much less in most
ca s es . The va lu es wer e fo un d by le as t squa r es fit to t he
mea su red data.
In some cases the cumulative time for line starts contrib-
uted so litt le to the total co mpu tatio n time th at the val ue
per line s tart co ul d on ly b e d eter m in ed rela t i ve ly i na c cu-
rately. In other words the pixel time portion dominated
the equation so much that t he line time po r tion was neg-
ligibl e, given the inaccurac ies of the model.
Therefore the simple m odel is only thought to allow inter-
polation for other picture sizes within the range W = 180
...1024, H = 240 ... 768. Extrapolation to picture sizes
muc h ou tsi de th is r ang e sh ould n ot be att emp ted u sing
this da ta.
In some cases the real ICP performance may be much
bet ter t han th at pr edic ted by the mo del, due t o irre gu lar
behavior of the ICP.
For horizontal and vertical up/down-scaling operations
use the larger W or H value occurring at input/output with
the H/V filter times table or model.
This will lead to overestimation of processing time by up
to 20 % .
Table 14-5. Measured processing time in ms - no other load to SDRAM
W in pixels 3 60 640 720 72 0 800 800 1024
H in pixels 240 480 480 768 480 600 768
hor izontal filter, 1 comp onent 1.22 3.82 4.4 3 7 .08 4.78 5.98 9.2 7
hor izontal filter, 3 comp onents Y UV 4:2:2 2.68 8.18 9.2 9 1 4.86 10.08 12.60 19. 35
vertical filter , 1 component 2.57 8.73 10.24 16.36 11.19 13.97 22.30
vert ica l filter, 3 compone nts YUV 4:2:2 5.15 17.47 20. 48 32.72 22.95 28.65 44. 60
yuv to rgb8a , pci outp ut 3.36 10.7 4 11. 93 19.08 13.04 16.30 26.02
yuv to rgb15 a, pci output 3.39 10.79 11. 96 19.12 13.10 16.41 26.15
yuv to rgb24 , pci outp ut 3.72 12.2 4 13. 52 21.62 14.85 18.59 29.98
yuv to rgb24 a, pci output 4.34 14.52 16. 04 25.02 17.58 21.63 35.01
yuv to rgb8a, sdram o utput 3.39 10.78 11. 95 19.09 13.13 16.40 26.08
yuv to rgb15a, sdram output 3.46 11.04 12.26 19.60 13.46 16.82 26. 87
yuv to rgb24, sdram o utput 3.62 11.69 13. 06 20.88 14.43 18.03 28.71
yuv to rgb24a, sdram output 3.90 12.69 14.11 22.57 15.65 19.56 31. 07
yuv to rgb8a, bitmask, pci output 3.37 11.42 12.49 19.97 13.61 17.01 27.83
yuv to rgb8a , RGB 15a overl ay, pci output 3.67 11.7 2 12. 92 20.67 14.23 17.79 28. 23
yuv to rgb8a , RGB 24a overl ay, pci output 4.23 13.5 7 15. 32 24.51 16.93 21.15 33. 15
yuv to rgb8a, yuv 422a overlay, pci output 3.67 11.72 12.92 20.67 14.23 17.79 28.23
yuv to rgb8a, 422 sequencing, pci output 2.52 7.77 8.57 13.70 9.32 11.65 18.40
Table 14-6. M easured processing time in ms - SDRAM loaded 95%, priority delay = 1
W in pixels 360 640 7 20 720 800 800 1024
H in pixels 240 480 480 768 48 0 600 768
hor izontal filter, 1 comp onent 2.0 1 6.37 7.60 12.16 8.02 1 0.02 16.02
hor izontal filter, 3 comp onents Y UV 4:2:2 4.11 13.69 15.6 2 24.96 16.56 2 0.68 32.65
vertical filter, 1 component 2.60 8.79 10.34 16.50 11.25 14.05 22.43
vert ica l filter, 3 compone nts YUV 4:2:2 5.2 0 17.5 9 20.6 6 32.96 23.15 28.89 44.87
yuv to rgb8a , pci outp ut 3.51 11.0 8 12.1 7 19.46 13.51 16.88 26.56
yuv to rgb15 a, pci output 3.52 11.11 12.2 2 19.51 13.47 16.82 26.65
yuv to rgb24 , pci outp ut 3.88 12.5 1 13.7 9 22.08 15.21 18.99 30.26
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-20 PRELIMINARY SPECIFICATION
yuv to rgb24 a, pci output 4.39 14.29 15.84 25.30 17.72 22.00 34.83
yuv to rgb8a , sdram output 3.69 11.67 12.75 20.39 14.20 17.80 27.95
yuv to rgb15 a, sdram output 4.25 13.15 14.64 23.41 16.79 20.98 31.49
yuv to rgb24 , sdram output 5.17 16.56 18.71 29.90 20.85 26.06 40.82
yuv to rgb24 a, sdram output 5.82 18.64 21.02 33.62 23.23 29.03 45.34
yuv to rgb8a, bitmask, pci output 3.65 12.37 13.45 21.50 14.68 18.34 30.13
yuv to rgb8a, rgbl15a overlay, pci output 4.94 15.30 17.23 27.51 19.06 23.78 36.70
yuv to rgb8a, rgbl24a overlay, pci output 6.77 21.93 24.85 39.73 27.44 34.31 53.67
yuv to rgb8a, yuv422a overlay, pci output 4.95 15.30 17.22 27.51 19.06 23.80 36.70
yuv to rgb8a , 422seque nci ng, p ci output 3.0 4 8.92 9.63 15.39 10.53 13.16 20.37
Table 14-6. M easured processing time in ms - SDRAM loaded 95%, priority delay = 1
W in pixels 360 640 7 20 720 800 800 1024
H in pixels 240 480 480 768 48 0 600 768
Table 14-7. M easured processing time in ms, SDRAM loaded 95%, priority dela y = 16
W in pixels 360 640 720 720 800 800 1024
H in pixels 240 480 480 768 480 600 768
hor izontal filter, one co mpone nt 7.70 24.28 29.32 46.9 0 30.05 37 .56 60.39
hor izontal filter, 3 comp onents YUV 4:2:2 15. 28 52.00 6 0.08 96.10 63.13 78 .90 123.29
vertical filter, one component 7.50 26.71 30.92 49.31 33.57 41.93 68.18
ver tica l filter, 3 compone nts YUV 4:2:2 14. 48 53.45 60.70 96.8 3 68.69 85 .79 136.40
yuv to rgb8a , pci outp ut 10.55 31.61 34.95 55.8 4 37.18 46.47 74.29
yuv to rgb15 a, pci output 10. 55 31.61 34.93 55.8 4 37.17 46.45 74.29
yuv to rgb24 , pci outp ut 10.39 31.71 34.93 55.8 4 37.25 46.54 73.58
yuv to rgb24 a, pci output 10. 49 31.95 35.06 55.9 8 37.15 46.46 74.10
yuv to rgb8a , sdram output 13. 83 41.93 48.10 76.94 51.57 64 .42 99.33
yuv to rgb15a, sdram output 17.58 55.55 60.95 97.4 9 65.82 82.24 137.71
yuv to rgb24, sdram o utput 20.25 65.46 74.67 119 .44 81.74 10 2.12 158.43
yuv to rgb24a, sdram output 24.05 78.51 88.98 142 .21 98.69 125.67 196.99
yuv to rgb8a, bitmask, pci output 11.05 35.04 37.75 60.37 40.15 50.19 85.13
yuv to rgb8a, rgbl15a overlay, pci output 18.19 57.11 62.60 100.04 70.84 88.26 136.03
yuv to rgb8a, rgbl24a overlay, pci output 24.81 80.19 91.86 145.57 100.72 125.00 198.15
yuv to rgb8a, uv422a overlay, pci output 18.20 57.11 62.60 100.04 70.00 88.28 135.98
yuv to rgb8a , 422seque nci ng, pci output 10.56 31.09 3 4.79 55.6 3 36.27 45.33 74.43
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-21
14.6.6 Priority Delay and ICP Minim um Bus
Bandwidth
The Priority Delay field in the Status register sets the time
the ICP will wait for SDRAM service before changing
fr om a lo w -priority bus request to a high-priority request.
The ICP normally requests SDRAM bus service at the
low est- p r iority l evel , sinc e it i s a back gr ou nd pr o c essing
device. In some cases, service to the ICP could be con-
tin u ously del ay ed by other background devic es , suc h as
th e VLD proc ess or or by h igh-p rio rity r equ ests fro m the
DSPCPU.
Th e PD fi eld se ts a ti mer on th e cur rentl y ac tive bus re-
quest. T he t i mer is load ed w ith the PD valu e and s t arted
each time a bus request is submitted. The timer is incre-
men ted once each bloc k tim e , the tim e requ ire d to lo ad
one bloc k of 64 b yte s. If t he ti m er reach es 1 6 befo r e the
request is serviced, the ICP changes its bus request pr i-
ority from low to high.
The resulting time delay until the ICP changes to high pri-
ori ty is:
timer delay = (16 - PD)*(block time)
One block time is 16 clock cycles.
Table 14-8. Line start and pixel time for linear model,
no other load on SDRAM
function t/linestart
(µs) t/pixel
(ns)
hor izontal filter, 1 comp onent 1.1 11
horizontal filter, 3 components YUV 4:2:2 3.2 22
vertical filter, 1 component 0.2 29
vert ica l filter, 3 co mpone nts YUV 4:2:2 0.7 58
yuv to rgb8a , pci outp ut 3.2 30
yuv to rgb15 a, pci output 3.3 30
yuv to rgb24 , pci outp ut 3.7 34
yuv to rgb24 a, pci output 5.3 40
yuv to rgb8a, sdram o utput 3.4 30
yuv to rgb15a, sdram output 3.3 31
yuv to rgb24, sdram o utput 3.1 33
yuv to rgb24a, sdram output 3.4 36
yuv to rgb8a, bitmask, pci output 2.5 32
yuv to rgb8a, rgbl15a overlay, pci output 3.8 32
yuv to rgb8a, rgbl24a overlay, pci output 4.0 39
yuv to rgb8a, yuv422a overlay, pci output 3.8 32
yuv to rgb8a , 422seque nci ng, pci output 3.2 20
Table 14-9. Line start and pixel time for linear model,
SDRAM loaded 95%, priority delay = 1
function t/linestart
(µs) t/pixel
(ns)
hor izontal filter, 1 comp onent 0.9 2 0
hor izontal filter,3 c ompo nents YUV 4:2: 2 2.8 4 0
vertical filter, 1 component 0.2 29
vert ica l filter, 3 co mpone nts YUV 4:2:2 0.7 5 8
yuv to rgb8a , pci outp ut 3.8 30
yuv to rgb15 a, pci output 3.8 30
yuv to rgb24 , pci outp ut 4.5 34
yuv to rgb24 a, pci output 6.0 39
yuv to rgb8a, sdram o utput 4.3 3 1
yuv to rgb15a, sdram output 4.9 36
yuv to rgb24, sdram o utput 4.6 4 7
yuv to rgb24a, sdram output 5.0 53
yuv to rgb8a, bitmask, pci output 3.2 34
yuv to rgb8a, rgbl15a overlay, pci output 5.5 42
yuv to rgb8a, rgbl24a overlay, pci output 5.8 63
yuv to rgb8a, yuv422a overlay, pci output 5.5 42
yuv to rgb8a , 422seque nci ng, pci output 4.9 21
Table 14-10. Line start and pixel time for linear
model, SDRAM loaded 95%, pri ority delay = 16
function t/linestart
(µs) t/pixel
(ns)
hor izo ntal filt er, 1 comp onent 2.9 77
hor izo ntal fil ter, 3 components YUV422 8.7 154
vertical filter , 1 component 0.4 87
vertical filter, 3 components YUV 4:2:2 1.2 174
yuv to rgb8a , pci output 13.9 82
yuv to rgb15 a, pci output 13.8 82
yuv to rgb24 , pci output 13.7 82
yuv to rgb24 a, pci output 14.0 82
yuv to rgb8a, sdram output 15.8 115
yuv to rgb15a, sdram output 18.5 1 51
yuv to rgb24, sdram output 17.5 187
yuv to rgb24a, sdram output 16.6 2 33
yuv to rgb8a, bitmask, pci output 14.3 91
yuv to rgb8a, r gb l15a overlay, pci output 20.7 153
yuv to rgb8a, r gb l24a overlay, pci output 21.6 232
yuv to rgb8a, yuv422a overlay, pci output 20.8 153
yuv to rgb8a, 422sequencing, pci output 14.0 80
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-22 PRELIMINARY SPECIFICATION
Table 14-11 gives the dela y in block ti mes a s a func t i on
of th e PD fi eld .
The priority delay mechanism in interaction with the arbi-
ter mechanism allows the user to allocate enough band-
width for the ICP to do its processing in the required
frame time. For details of the arbiter mechanism see
Chapter 20, “Arbiter.”
14.6.7 ICP Pa rameter Tables
Ea ch mic ro progr am i n th e micr op rog ram se t ha s an as -
sociated parameter table used by the ICP to process the
image data, such as the image input and output start ad-
dr esses , scal ing fact or, et c. The DP poin ts to the loca tion
in SDRAM of the first word of the parameter table. The
par am eter tab le ad dr ess m us t be w ord alig ned. The pa-
rameter table can be more than one SDRAM block (16
32-bit words) long.
Note: In pack ed R GB2 4 to PCI o perat io n t he ou tp ut ad-
dress offset from the start of video memory must be a
multiple of 6 bytes, i.e. on an even pixel boundary.
14.6.8 Load Coef ficients
This routi ne lo ads t he fi lter coeffici ent RAMs w ith coeffi-
cient data in the parameter table. A total of 32 sets of five
10-bit coefficients are loaded. Each set of five coeffi-
cients forms a 50-bit coefficient word. Two coefficients
are stored in each 32-bit word in SDRAM. Three 32-bit
words ar e u sed for each set of five c oefficien ts that form
a coefficient word. The parameter table is 96 words (6
SDRAM blocks) long. Each coefficient is stored as the 10
LSBs of each 16-bit half word of the 32-bit word.
The parameter table for the coefficient load function con-
tains the coefficient data directly, as shown below. The
parameter table is 96 words long.
14.6.9 Horizontal Fi lter - SDRAM to SDRAM
This routine performs horizontal scaling and filtering of
one component (Y, U or V) of an N x M image from one
locat i on in SD R AM t o another.
14.6.9.1 Algorithms
The routine reads image data from SDRAM using the Y
address c ounter, then scal es and filters the data in the
hor iz o ntal di r ec tio n an d w rites i t back to th e S DR AM us -
ing t he Z add r es s count er . The 5-ta p fil t e r sca le s and fi l-
te rs the da ta . The LS B In crem ent va lue s uppl ie d by the
parameter table determines the scaling. The routine
reads and writes a line at a time until the full image is
transferred. The filter mirrors the ends of each line to pro-
vide the extra pixels needed by the filter at the ends of
each line.
14.6.9.2 Parameter table
The parameter table, shown in Table 14-13, supplies the
inpu t an d outp ut st arti ng addre sse s and offs ets , the im-
age heigh t in line s an d width in pixels, and the incremen t
value, w h ic h is de r iv ed from th e sc ale fa c to r .
The input and output addresses are the byte addresses
of their respective tables. The y do not need to be word-
or block-aligned.
The input and output line offsets define the difference in
bytes from the address of the first pixel in the first line to
the address of the fir st pi xel in t he seco nd li ne for their re-
sp ecti ve b lock s. The line of fset mu st be c ons tan t for all
lines in each table. The line offset allows some space be-
tween the end of one line and the start of the next line. It
also al lo w s th e IC P t o s ca le an d fi lter a sub s et of an ex -
ist ing i mage , su ch as magn ifyi ng a po rtion of an i mage .
Th ere a re no restrictions on line offset values other than
they must be 16-bit, two’s complement integer values.
(Note t hat t hi s al lo ws nega t iv e offsets. You can use this
to flip an image vertically.)
The input and output image height and width values a re
the height in li nes and width in pixels per line for their re-
Table 14-11. ICP priority delay vs. PD code
PD
Code Delay
block times
1111 1
1110 2
1101 3
1100 4
1011 5
1010 6
1001 7
1000 8
0111 9
0110 10
0101 11
0100 12
0011 13
0010 14
0001 15
0000 16
Table 14-12. Load coefficients parameter table
Parame te r Word
Description
Upper 2
bytes Lo we r 2
bytes
a+2 a+1 RAM Coefficient word 0
a+0 a-1
a-2 0
a+2 a+1 RAM Coefficient word 1
a+0 a-1
a-2 0
a+2 a+1 RAM Coefficient word 31
a+0 a-1
a-2 0
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-23
spective images. The height and width are 16-bit positi ve
binar y nu m be r s be tw ee n 0 an d 64K -1.
The Integer increm ent an d Fract ion increm ent valu es are
the sc alin g param eter s. Th e Integ er valu e is a 16- bit in-
te ge r, and th e Fr ac ti on va lue is a po si t iv e bi na r y frac t i on
bet ween 0 an d 0.99 999+ . F or up sca ling (o utput image
bigger ), the in cr e m en t va lue i s th e inv er se of th e sc alin g
value. If you are upscaling by a factor of 2.5, the incre-
ment value will be the inverse of 2.50 = 0.40. The Integer
inc r eme nt valu e wil l b e 0 an d t he Fr ac tion in cr em ent val-
ue will be 0.40. For down scaling, the increment value is
equal to the scaling value. If you are down scaling by 2.5
(output image smaller), the Integer increment value will
be 2, and the Fraction increment value will be 0.500.
To pe r for m sc ali ng , t he Int eg er and Fr ac tio nal inc remen t
values must be generated and placed in the parameter
tab le. The simplest way to gen erat e these v alue s in com-
mon computer languages such as C is as follows:
1. G en er ate the Inc r em ent Value as a fl oating poin t
number = In put Width / Output Wid th
2. M ult ip ly th e Inc reme nt Va lue by 6 55 36
3. Co n v ert the resu lt to a Long Int e ger ( 32 bits ) . The up-
per 16 bits of the Long integer will be the Integer in-
crement value, and the lower 16 bits will be the Frac-
tional value.
4. Store the 32-bit Long integer in the parameter table as
the combined Integer and Fractional increment val-
ues.
The S tart Fraction defines the starting value in the scal-
ing counter for each line. It is a 16-bit, two’s complement
fr ac tio nal valu e b et wee n -0. 5 00 a nd + 0.4 99 99 . T he Start
Fra ction all ow s the input data t o be off set by up to half a
pixe l, r ef erre d to the in pu t pix e l grid . It is ‘0’ for Y and for
UV co-sited data, and set to ‘-0.25’ (C000h) for inter-
sperse d to co - s ite d co nver s i on of U a nd V dat a. The ‘-
0.25’ value effectively shifts the U and V data toward the
s tar t of t he li ne b y 1/4 pi xe l, the am ou nt req uir ed for con -
version.
14.6.9.3 Control word format
The Control word pr ovides bit fields whic h affect the hor -
izontal filtering operation. The format of the Control word
is as follows.
Bit Name Function
15 Bypas s Bypa ss fi lte r. Pi c ks near est in pu t pi x el
and pa ss e s i t to o utput unfiltered.
W hen B ypa ss is set & scale fact o r is
1.0, this results in an image block
move
9 G E TB L arg e dow n-sca ling bi t . Picks near e st
input pixels and passes them to filter.
Equivalent to bypass + 5-tap filter of
output pi xels. LSB v alue = 0 for filter-
ing.
The Byp ass bit cause s t h e d ata t o bypa ss th e 5 -ta p f i lte r.
The scaling operation sel ects th e center pixel, and this
pixe l is p asse d to th e fil te r outp ut . No fi lte rin g or inte rpo -
lation is provided. If the scaling factor is ‘1.0’, the result is
an image block move where the image is moved from
one par t of SD RA M to anothe r w i thou t mo di f ic at ion. If the
s cali ng fact or i s o t her t h an ‘1.0’, the effective algorithm is
pixel picking, where the input pixel nearest the output
pixel location is used as the output pixel.
The GETB bit is an optional bit for large (> 4) down scal-
ing. When GETB is ‘0’ (normal op eration), the 5-tap filter
receives the pixel nearest the output pixel as its center
pixel plus the tw o adja cen t input pixels on either side of
thi s pi xe l to form th e fi ve fi lt er in pu ts . When GET B is se t,
the filter receives the pi xel nearest the output pixel as its
c enter pi xel plus the tw o pixe ls ne arest the adjacent out-
put pixels on either side of this pixel to form the five filter
inputs. T he effec tive algorithm is pixel picking p l us 5-t a p
filtering of the result. GETB also forces the scaling LS B
va lu e to ‘0’, since output pixels are being filtered and no
Ta ble 14-1 3. Horizontal filter parameter table
Parame te r Word Description
Upper 2 bytes Lower 2 bytes
Input image start address Start address of X0Y0 (byte address)
Y counter
Start fraction Input image
Line o ffset Starting value: may be 0.5, etc. for interspersed convert;
Line offset from X0Y0 to X0Y1
Fraction increment In teger in creme nt I n cremen t value for Y = 1/sc ale factor
Input image height Input image Width Height and width in input lines and pixels
Output image start address Start address of X0Y0 (byte address)
Control Output Image
Line o ffset Control bits; Line offset from X0Y0 to X0Y1
Output image height Output image width Height and width in output lines and pixels
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-24 PRELIMINARY SPECIFICATION
interpolation is used. (See Section 14.5.2, “Filtering”)
This is shown in Figure 14-18.
14.6. 10 Vertical Filte r - SDRAM to SDRAM
This routine performs vertical scaling and filtering of one
c ompon en t (Y, U or V) of an N x M ima ge from on e loc a-
tion in SDRAM to another.
14.6.10.1 Algorithms
The routine reads image data from SDRAM using the Y
address counte r , scales and filters the data in the vertical
direction , and wr ites it back t o the SDRAM using the Z
address counte r. The 5-tap filter scales and filters the da-
ta. The U LSB register is used as the scaling coefficient
register . The U L SB I ncrement value supp lied by the pa-
rameter table determines the scaling. Lines at the top
and bottom of the image are mirrored to provide the extra
line data ne eded by the 5- tap filter .
The routine reads and writes data in 64-byte (one
SD RAM bl oc k) colu mns of pixe ls u nti l t he entir e i mag e is
tr an sfer re d. For eac h colum n, lin e segme nt s of 64 pixel s
are processed until the entire column has been pro-
cessed. Each 64-pixel line segmen t generated r equires
five vertically adjacent 64-pixel line segments as input to
the 5-tap filter. The routine processes the image in pixel
columns to eliminate redundant read of input pixel data:
each new line segment typically requires reading only
one new 64 byt e line se gme nt .
The routine processes data in 64-pixel blocks, corre-
sponding to the inpu t block buffer sizes . Fiv e bu f fers are
used in processing the current line segment, while the
s ixth buffer reads in the next line segment in overlap with
current processing.
14.6.10.2 Parameter table
The parameter table, as shown in Figure 14-19, supplies
th e inpu t and o utp ut sta rti ng ad dre sse s and of fs ets, the
image height in lines and width in pixels, and the scale
factor.
0 12345 67891011121314151617181920
0 12345 67891011121314151617181920
P2N = F(10, 11, 12, 13, 14)
P2L = F(2, 7, 12, 17, 22)
21 22 23 2425
Normal Down Scaling
Large Dow n Scali ng
Input Pixels
Output Pixels
Input Pixels
Output Pixels
Figure 14- 18. Nor mal vs . Lar ge d own scal ing for scale factor = 5.0
Figure 14-19. Vertical fi lter parameter table
P arameter Word Description
Upper 2 bytes Lower 2 bytes
Input image start address Start address of X0Y0 (byte address)
U counter
Start fraction Input imag e
Line offset Starting value: may be 0.5, etc. for interspersed convert;
Line offset from X0Y0 to X0Y1
Fraction increment Integer i ncre ment Incr emen t va lue for U = 1/scale factor
Input image height Input image width Height and width in input lines and pixels
Output image start address Start address of X0Y0 (byte address)
Control Output image
Line offset Control Word; Line offset from X0Y0 to X0Y1
Output image height Output Image Width Height and width in output lines and pixel s
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-25
The input and output addresses are the byte addresses
of their respective tables. The in put and the output ad-
dress need to be 64-byte aligned.
The input and output line offsets define the difference in
bytes from the address of the first pixe l in the first line to
the address of the fir st pi xel in t he seco nd li ne for their re-
spective blocks. The line offset must be constant for all
lines in each table. It allows some space between the
end o f on e line a n d the start of the n ext line. It also allows
th e IC P to s ca le a n d filter a subse t of an existing image ,
such as magnifying a portion of an image. Offset values
are 16- bit, tw o’s complement integer values.
Vertical filtering has a restriction on input and output line
offset values: they must be positive, and they must be
multiples of 64. Note that this only applies to the line-to-
lin e s pac in g. Even with t hi s re st rict i on, i np ut im ages ma y
be an y height and any width and may sta rt at any byte
address. Also, image subsets of arbitrary height and
wid th ca n b e us ed. As long as the o rig inal imag e ha s a
line offset which is a multiple of 64 , all subsets of that im-
age w ill al so autom atic ally have a li ne off set, which is a
multiple of 64 - the same as the original image. All imag-
es should have line offsets which are multiples of 64 as
good programming practice, even though this restriction
onl y appl ies t o ver tic al fil terin g. I f an image d oes no t hav e
a mult ipl e of 64 line o ffset, it can be con ve rte d to tha t by
usin g hor iz ontal fil terin g in t he i mag e blo ck m ove m ode
with the output offset value being a multiple of 64.
The input and output image height and width values are
the height in li nes and width in pixels per line for their re-
spective images. The height and width are 16-bit positi ve
binar y nu m be r s be tw ee n 0 an d 64K -1.
The Integer increm ent an d Fract ion increm ent valu es are
the sc alin g param eter s. Th e Integ er valu e is a 16- bit in-
te ge r, and th e Fr ac ti on va lue is a po si t iv e bi na r y frac t i on
bet ween 0 an d 0.99 999+ . F or up sca ling (o utput image
bigger ), the in cr e m en t va lue i s th e inv er se of th e sc alin g
value. If you are upscaling by a factor of 2.5, the incre-
ment value will be the inverse of 2.50 = 0.40. The Integer
inc r eme nt valu e wil l b e 0 an d t he Fr ac tion in cr em ent val-
ue will be 0.40. For down scaling, the increment value is
equal to the scaling value. If you are down scaling by 2.5
(output image smaller), the Integer increment value will
be 2, and the Fraction increment value will be 0.500.
To pe r for m sc ali ng , t he Int eg er and Fr ac tio nal inc remen t
values must be generated and placed in the parameter
tab le. The simplest way to gen erat e these v alue s in com-
mon computer languages such as C is as follows:
1. G en er ate the Inc r em ent Value as a fl oating poin t
number = Input Height / O utpu t Height
2. M ult ip ly th e Inc reme nt Va lue by 6 55 36
3. Co n v ert the resu lt to a Long Int e ger ( 32 bits ) . The up-
per 16 bits of the Long integer will be the Integer in-
crement value, and the lower 16 bits will be the Frac-
tional value.
4. Store the 32-bit Long integer in the parameter table as
the combined Integer and Fractional increment val-
ues.
Th e S t art F ra c t io n d e f in es th e star ti ng v al ue in th e s cal -
ing counter for each line. It is a 16-bit, two’s complemen t
fractional value between -0.500 and 0.49999+. This val-
ue is plac ed in the Start Fractio n a llo w s the input data to
be offset by up to half a line, referred to the input pixel
gri d. I t is set to ‘0’ for all conventional YUV input data.
14.6.10.3 Control w ord format
The Control word provides bit fields which affect the ver-
tical filtering operation. The form at of the Contr ol wo rd is
as follow s .
Bit Name Function
15 By pass Bypass filter. Picks nearest input line
and pa ss e s i t to o utput unfiltered.
W hen B ypa ss is set & scale fact o r is
1.0, this results in an image block
move
The Byp ass bit cause s t h e d ata t o bypa ss th e 5 -ta p f i lte r.
The scaling operation selects the center line, and this
lin e i s pas se d to th e fi l ter o utpu t . No f ilt er i ng or inte r pola-
ti on is pr ovid ed. If t he scal ing f ac tor is 1. 0, the r esult is an
image block move where the image is moved from one
part of SDRAM to another without modification. If the
scaling factor is other than 1.0, the effective algorithm is
line picking, w here the input line nearest the output line
location is u se d as th e ou t p ut line.
14.6.11 Horizontal Filter with RGB/YUV
Conversion to PCI or SDRAM
This routine moves an N x M image in YUV 4:2:2, YUV
4:2 : 0 o r Y UV 4:1 :1 form at from S DRAM t o t he PC I bus o r
to SDRAM. The image is scaled and filtered in the hori-
zontal direction during the move. Optional bit masking
and/or RG B o ve r la y c an be u sed du ri ng t he move when
PCI output is specified.
14.6.11.1 Algorithms
The routine reads image data from SDRAM using the Y,
U, and V address counters, scales and filters the data in
the horizontal direction and writes it to the PCI interface
or SDRAM. The 5-tap filter scales and filters the data.
The LSB I ncremen t val ue for each of the Y, U a nd V c om-
ponents supplied by the parameter table determines the
scaling. Separate scaling factors allows YUV 4:2:2 inter-
spersed to co-sited transformation as the data is being
filtered. The scaled and filtered data is converted to RGB
or Y U V f o r m at before bein g sent to th e PC I inter fa ce or
to SD R AM. In t he P C I output ca se, ov e rlay data with al -
pha blending and chroma keying can be added to the
output image, and the output image can be gated by a b it
mas k befor e it is sent to th e P CI inte rfa ce .
The routine reads and writes a line at a time until the full
imag e i s tr ansf erre d. T he filt er mi rror s th e end s of ea ch
line to pr o vid e th e extr a pix els n eeded by t h e f ilter at the
ends of each line.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-26 PRELIMINARY SPECIFICATION
14.6.11.2 Parameter table
The parameter table, shown in Table 14-14, supplies the
input and output starting addresses and offsets for Y, U,
V, OL, B and Z , the image height in lines and width in pix-
el s, an d t he s c al e fac t o r s for ea ch c om p on ent .
The input and output addresses are the byte addresses
of t heir re specti ve tab les. They d o not need to b e word or
block aligned. Note the following restriction: in packed
RGB24 to PCI operatio n the output address offset from
th e s tart of vid eo me m ory m us t be a m u lt i ple of 6 by t e s ,
i.e. on an even pixel boundary.
The input and output line offsets define the difference in
bytes from the address of the first pixe l in the first line to
the address of the fir st pi xel in t he seco nd li ne for their re-
sp ecti ve b lock s. The line of fset mu st be c ons tan t for all
lines in each table. The line offset allows some space be-
tween the end of one line and the start of the next line. It
also al lo w s th e IC P t o s ca le an d fi lter a sub s et of an ex -
ist ing i mage , su ch as magn ifyi ng a po rtion of an i mage .
Th ere a re no restrictions on line offset values other than
they must be 16-bit, two’s complement integer values.
(Note t hat t hi s al lo ws nega t iv e offsets. You can use this
to flip an image vertically.)
The input and output image height and width values a re
the height in li nes and width in pixels per line for their re-
spective images. The height and width are 16-bit posi tive
binar y nu m be rs betw e en 0 an d 64 K-1 .
The Integer increm ent an d Fract ion increm ent valu es are
th e sca ling pa ra meters. T here is a se para te s cali ng pa -
rameter for each of the Y, U and V input components.
The Int eger va lue i s a 16-b it in teger, and the F racti on va l-
ue is a positi ve b ina r y f ra ction bet ween 0 and 0.99999+.
For up scaling (output image bigger), the increment val-
ue is the inverse of the scaling value. If upscal ing by a
factor of 2.5, the increment value will be the inverse of
2.50 = 0.40. T he Integer increment value will be ‘0’ and
the Fraction increment value will be ‘0.40’. For down
scaling, the increment value is equal to the scaling value.
If you ar e down sc aling b y 2.5 (output imag e smaller ), the
Int ege r inc reme nt valu e wi ll be ‘2’, a nd th e Fract ion in cre-
ment valu e will be ‘0.500’.
To pe r for m scal i ng , the I nt eger and Frac ti onal inc rem ent
values must be generated and placed in the parameter
Tabl e 1 4 - 14. Ho rizo nta l filt e r to RGB out put pa ram ete r table
P arameter Word Description
Upper 2 bytes Lower 2 bytes
Input image Y start address Y Start address of X0Y0 (b yte address)
Y Counter
Start fraction Input image
Y line offset Starting value: may be 0.5, etc. f or interspersed convert;
Y Line offset from X0Y0 to X0Y1
Y fraction increment Y integer increment Increment value for U = 1/scale factor
Y input image height Y input image width Y Height and width in pixels
Input image U start address U Start address of X0Y0 (byte address)
U counter
Start fraction Input image
U line offset Starting value: ma y be 0.5, etc. for interspersed convert;
U Line offset from X0Y0 to X0Y1
U fraction inc rement U integer increme nt In cremen t value for Y = 1/sc ale factor
U input image height U input image Width U Height and width in pixels
Input image V start address V Start address of X0Y0 (b yte address)
V Counter
Start fraction Input image
V line offset Starting value: may be 0.5, etc. f or interspersed convert;
V Line offset from X0Y0 to X0Y1
V fraction increment V integer increment Increment value for V = 1/scale f a ctor
V Input image height V input image width V Height and width in pixels
Output image start address Start address of X0Y0 (byte address)
Control Output image
Line offset Input & output formats & control bits;
Line offset from X0Y0 to X0Y1
Output image height Output image width Height and width in output pixels
Bit Map image start address Start address of X0Y0 (byte address)
0 Bit map image
Line offset Line offset from X0Y0 to X0Y1
RGB ov erlay start address Start address of X0Y0 (byte address)
Alpha 1 & Alpha 0 Ove rlay
Line offset Alpha 1 & Alpha 0 blend code for RGB15+ α, etc.;
Line offset from X0Y0 to X0Y1
Overlay end pixel Overlay start pixel Start and end pixels along line
Overlay end Line Overlay start l ine Start and end lines in frame
Philips Semiconductors Image Coprocessor
PRELIMINARY SPECIFICATION 14-27
tab le. The simplest way to gen erat e these v alue s in com-
mon computer languages such as C is as follows:
1. G en er ate the Inc r em ent Value as a fl oating poin t
number = Input Width / O utpu t Width
2. M ult ip ly th e Inc reme nt Va lue by 6 55 36
3. Co n v ert the resu lt to a Long Int e ger ( 32 bits ) . The up-
per 16 bits of the Long integer will be the Integer in-
crement value, and the lower 16 bits will be the Frac-
tional value
4. Store the 32-bit Long integer in the parameter table as
the combined Integer and Fractional increment values
Fo r YU V 4:2: 2 or YUV 4:2:0 inp ut data and R G B o utp ut
data, the scaling factor for U and V must be twice the
scaling factor for Y, unless YUV 4:2:2 sequencing is used
for speed. In YUV 4:2:2 or YUV 4:2:0 data, the horizontal
c ompon en ts of U and V are hal f those o f Y. The U and V
must be upscaled by 2 to generate a YUV 4:4:4 f ormat
inter nally f or YUV to RGB co nversio n. For Y UV 4:1 :1 in-
put data, th e U an d V componen t s must be ups caled by
a fact or of 4 to generate the require d interna l Y UV 4:4 :4
format.
The S tart Fraction defines the starting value in the scal-
ing counter for each line. It is a 16-bit, two’s complement
fr ac tio nal valu e b et wee n -0. 5 00 a nd 0 . 49 99 9+ . The Start
Fra ction all ow s the input data t o be off set by up to half a
pixe l, r ef erre d to the in pu t pix e l grid . It is ‘0’ for Y and for
UV co-sited data, and is set to ‘-0.25’ (C000) for inter-
spersed to co-sited conversion of U and V data. The ‘-
0.25’ value effectively shifts the U and V data toward the
s tar t of t he li ne b y 1/4 pi xe l, the am ou nt req uir ed for con -
version.
The Alpha 1 and Alpha 0 valu es are 8-bit fields within the
16-bit Alpha field. These values are loaded into the Alpha
1 and Alpha 0 registers, resp., for use by RGB 15+α and
YUV 4:2:2+α overlay formats in alpha blending.
The Overlay start and end pixels and lines define the
s tar t and en d pixel s an d l ine s wit hi n the ou tp ut im age for
the overlay. The first pixel of the overlay image will be
blended with the pixel at the Overlay Start Pixel and
Overlay Start Line in the ou tput image.
14.6.11.3 Control word format
The Control w ord pr ovides b it fields w hich a ffect the hor-
izontal filtering operation. The format of the Control word
is as follows.
Bits Name Function
15 Bypass Normally set to 0 to enable filtering.
Ca n be s et to 1 to a cc o mpli sh data
move without filtering.
14 422SEQ 4:2:2 Sequence bit. Used with YUV
4:2:2 output
13 YUV420 YUV 4:2:0 input format
12 OE N O ver lay en able. Vali d only for PC I out-
put
11 PCI PCI output enable. Otherwise SDRAM
output
10 BEN Bit mask enable. Valid only for PCI
output
9 GETB Large down scaling bit. Picks five
input pixels nearest 5 output pixels
and passes to filter.
Equivalent to filter b ypass + 5-tap filter
of output pixels. LSB value = 0 for fil-
tering.
8 OLLE Overlay little endian enable
7-6 O FR M Overlay for ma t
0 = RGB 24+α
1 = RGB 15+α
2 = YUV 4:2:2+α
5 CHK Chroma keying enable
4 LE RG B output little endian enable
3-0 RGB RGB Output Code
0 = YUV 4:2:2+α
1 = YUV 4:2 :2
2 = RGB 24+α
3 = RGB 24 packed
4 = RGB 8A (RGB 233)
5 = RGB 8R (RGB 332)
6 = RGB15+α
7 = RGB 16
The 422SEQ bit controls the internal sequencing of the
YUV to RGB operation. It is set to ‘1’ when YUV 4:2:2
outpu t is s elec ted. When 422S EQ is ‘0’, no rmal R GB out-
put is assumed. In this mode, the input is YUV 4:2:2 or
YUV 4:2:0, and the output is RGB. To generate the RGB
output, the YUV 4:2:2 or YUV 4:2:0 input must be up-
scaled to YUV 4:4:4 before conversion to RGB. This
means the scaling factor for U and V must be twice the
sca ling fact or for Y. The int ernal seq uenci ng of the fil ter
in this cas e is UVY, U VY, U VY to generate R GB, RGB ,
RGB. For YUV 4:2:2 output formats, no upscaling of U
and V is requir ed. In thi s case, t he 422SE Q bit is set to
one, an d th e f ilter sequ ence is UVYY, UVYY, U VY Y.
Th e 422 SEQ b it c an b e set in RGB outp ut mo de to de -
c re ase the processin g time for t he ima ge at the expense
of color bandwi dth an d some corr esponding decrease in
picture quality. If the 422SEQ bit is set for RGB output,
the filter will perform the UVYY sequence. In this case,
the U and V components are not upscaled by 2, and the
YUV to RGB converter updates its U and V components
every other pixel. In the normal case (422SEQ=0), it
takes 6 clock cycles to generate two RGB pixels. In the
422S EQ=1 case, it takes 4 clock cycles to generate two
RG B pix e l s, r e du ci ng proces s in g t im e by 33 % .
The YUV420 bit indicates that the input data is in YUV
4:2:0 format. In YUV 4:2:0 format, the U and V compo-
nents are half the width and half the height of the Y data.
YUV 4:2:0 data is normally converted to YUV 4:2:2 data
by a separate v ertical ups caling by a factor of 2.0 for best
quality . The YU V420 bit allow s u s in g YU V 4: 2:0 data di-
rectly but with some quali ty degradation. When YUV420
is set, the ICP up scales the data vertically by line dupli-
cat i on . E ac h U and V inp ut li ne i s us ed tw ic e. The sepa -
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
14-28 PRELIMINARY SPECIFICATION
rat e vertical scaling step is eliminated at the expense of
some quality since the lines are simply duplicated rather
th an be in g fully sc a l ed and filte r ed.
The OEN bit enables overlay. Set it to ‘1’ if an overlay is
used, ‘0’ if not. Overlays are only valid for PCI output.
The PCI bit selects PCI as the output port for the ICP da-
ta. A ‘1’ sel ects P CI ou tpu t; a ‘0’ sel e cts SDRAM ou tp ut.
The BEN bit enables bit masking. Set it to ‘1’ if bit mask-
ing is used, ‘0’ if not. Bit masking is only valid for PCI out-
put.
The GETB bit is an optional bit for large (> 4) down scal-
ing. When GETB is ‘0’ ( norm al operatio n) , the 5-tap filter
receives the pixel nearest the output pixel as its center
pixel plus the tw o adja cen t input pixels on either si de of
th is pi xe l to for m th e fi ve fi lt er in pu ts . Wh en GET B is set,
the filter receives the pixel nearest the output pixel as its
center pixel plus the two adjacent output pixe ls on ei th er
s ide of thi s pi xel to for m the f iv e fil ter inpu ts. T he effecti ve
algorithm is pixel picking plus 5-tap filtering of the result.
GET B als o fo rc es t he sca li ng LSB val ue to ‘0’, sinc e ou t-
put pixel s are being f iltered and no interpolation is used.
The OFRM bit field selects the overlay data format, as
shown in the C o ntrol w ord for m at li st.
The CHK bit enables chroma keying. Set it to ‘1’ if chro -
ma keying is used, ‘0’ if not.
The OLLE bit sets the endian-ness of the overlay data in-
put. Set it to ‘1’ if the overlay data is little-endian , ‘0’ if big
endian . Th is bit i s nor m al ly se t to t he same v alue as the
LE bit in the Status register.
The LE bit set s t he endian-n ess of th e R GB/ YU V outpu t
data. Set it to ‘1’ if the output data is little-endian, ‘0’ if big
endi an . The LE bit i s norm ally set to the s ame val ue as
th e LE bit in the S ta tus r e gi st er .
Th e RG B fiel d define s t h e o utput da t a fo r m at , as sh ow n
in th e Con tr o l word for ma t lis t.
Important Note: The ICP DMA Enable bit (IE) in the
BIU_CTL register of the PCI interface must be set for
RGB output to PCI. This bit must be set before initiating
RGB to PCI operations, or the ICP will stall waiting for the
PC I to become ready.
PRELIMINARY SPECIFICATION 15-1
Vari able Leng th Decoder Chapter 15
by Gene Pinkston and Selliah Rathnam
15.1 VLD OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The variable length decoder (VLD) unit Huffman-de-
codes MPEG-1 and MPEG-2 (Main Profile) video bit-
streams[1-3]. This chapter describes a programmers
vi ew of th e V LD.
The VLD reads an MPEG stream from SDRAM, decodes
th e bi ts tr e am un de r th e c on tr o l of D SP CP U a nd ou tpu ts
tw o dat a st re ams . The outp ut data strea ms contai n ma c-
roblock header information and the run-length encoded
DCT coeffic ients. T he output data s tr eam s are stored in
the S D RAM buffe rs .
The VLD unit, operates independently during the slice
decoding process. The rem aining decoding of th e MPEG
stream is carried out by the DSPCPU.
15.2 VLD OPERATI ON
Enab led by the DSPCPU, t he VLD unit can be initialized
by hardwar e or software reset opera tions. Hardware re-
set is provided by the external TRI_RESET# pin. Soft-
ware reset is provided by one of the VLD commands.
The DSPCPU controls the VLD through the VLD com-
mand register. There are five commands supported by
the VLD:
•Shift the bitstream by some number of bits (a maxi-
mum of 15-bit shift)
•Searc h for the next start code
•Reset the VLD
•Parse some number of macroblocks
•Flush VLD output buffers to SDRAM
The normal mode of operat ion will be for the DSPCPU to
req ue s t th at the VLD t o p arse s om e numb er of ma c r ob -
locks . Onc e the V L D h as be gun parsing mac r oblo cks, it
may stop for any one of the following reasons:
HWY_BUS
RD Buffer
Macroblock
DMA
ENGINE
Control status
status
MMI O &
CONF REGs
SHIFTER
start_code_
detector
mb_addr
mb_type
cbp
dmv &
motion
dct_lum
dct_chr
dctcoef
(0)
dctcoef
(1)
escape_codes
VLD
FLOW
Control
Interrupt
Run-Level
Hdr W R FIFO
WR FIFO
Figure 15-1. VLD block diagram
64 Bytes
64 Bytes
64 Bytes
PNX1300/01/ 02/11 Data Book Philips Semiconductors
15-2 PRELIMINARY SPECIFICATION
•The command was completed with no exceptions
•A start code was detected
•An er ror was e nco unter ed in the bitst r ea m
•The VLD input DMA completed, and the VLD is
stalled waiting for more data
•One of the VLD output DMAs has completed and the
VLD is stalled because the output FIFO is full
The DSPCPU can be interrupted whenever the VLD
halts.
Consider the case in which the VLD has encountered a
start code. At this point, the VLD will halt and set the sta-
tus fl ag to ind icate th at a star t code h as been detecte d.
This event will generate an interrupt to the DSPCP U (if
corresponding interrupt is enabled). Upon entering the
interrupt routine, the DSPCPU will read the VLD status
register to determine the source of the interrup t. Once it
has d etermined that a start code was encoun tered, the
CPU will read 8 bits from the VLD shift regist er to deter-
min e t h e typ e of star t code en co un ter ed . I f it a ‘slice’ st a rt
code, the DSPCPU reads from the shift register the slice
quantization scale and any extra slice information. The
slice quantization scal e is then written back to the VLD
quantizer-scale register. Before exiting the interrupt rou-
tine, the DSPCPU will clear the start code detected sta-
tus bit in the status register and issue a new command to
pro c es s the rem ainin g m acr ob lo ck s .
15.3 DECODING UP TO A SLICE
MPE G d ecodi ng up to t he sl ic e laye r is ca rri ed ou t by th e
DSPCPU and the VLD. The VLD is controlled by the
DSPCPU for the decoding of all parameters up to the
slice-start code. During this process, the DSPCPU reads
fr om th e VLD_ SR regist er wh ich co ntains the n ext 1 6 bits
of the bitstream. The DSPCPU also issues shift com-
mand s to th e VLD in or der to advance the con tents o f the
shift register by the specified number of bits. The
DSP CPU ma y also com man d t he VLD to advance to t he
next start code. Refer to Table 15-6 for a complete lis t of
VLD commands and their functions. Once at the slice
layer, the VLD operates independently for the entire slice
deco ding. The slice de coding st arts on ce the DSPCPU
issues a parse command.
15.4 VLD INPUT
Input to th e VLD is con tr olle d by the VLD input DMA en-
gine. The input DMA engine is programmed by the
DSPCPU to read from SDRAM. The DSPCPU programs
this DMA engine by writing the address and the length of
the SDR AM buff er co ntai ning the MP EG stream. The ad-
dress of the buffer is w ritten to the VLD _BIT_ADR regis-
ter. The length, in bytes, of the buffer is written to the
VLD_BIT_CNT register.
Esc Count MBA Inc MB Type Mot Type DC T Type MV count MV Format DMV
MV Field S el [0][0] Motion Code [0][0][1]Motion Residual [0][0][0] Motion Residual [0][0][1]Motion Code [0][0][0]
MV Field S el [1][0] Motion Code [1][0][1]Motion Residual [1][0][0] Motion Resi dual [1][0][1]Motion Code [1][0][0]
MV Field Sel [0][1] Motion Code [0][1][1]Motion Residual [0][1][0] M otion Re sidual [0][1][1]Motion Code [0][1][0]
MV Field Sel [1][1] Motion Code [1][1][1]
Motion Residual [1][1][0] M otion Re sidual [1][1][1]
Motion Code [1][1][0]
quant scaleCBPdmvector[0]dmvector[1]
31
First Forward Motion Vector
Second Forward Motion Vector (for MP EG2 only)
First Backward Motion Vector
Second Backward Motion Vector (for MPEG2 only)
012346111725
71523293031 13
71523293031 13
71523293031 13
71523293031 13
410121431
Figure 15-2. MPEG-2 macroblock header output format
w1
w2
w3
w4
w5
w0
MB1
MB2
Philips Semiconductors Variable Length Decoder
PRELIMINARY SPECIFICATION 15-3
The VLD reads data from SDRAM into an internal 64-
byte FIFO. The VLD processing engine then reads data
from the FIFO as needed. Once this internal FIFO is
empty the VLD reads more data from SDRAM. The
VL D_BI T_A DR and VLD_ BIT _CNT re gist ers are upda t-
ed af ter ea ch re ad from main memory. Th e content of the
VLD_BIT_ADR register reflects the next address from
which the bitstream data will be fetched. The content of
th e VLD _ B IT_ C N T r eg is t e r r efl ects the num b e r of byt e s
rem a ining to be read befor e the current trans fe r is co m-
plete. When the number of bytes remaining to be read
from SDRAM is zero, a status flag i s set a nd an interrup t
can be generated to the DSPCPU. The DSPCPU will
provide the new bitstream buffer address and t he num-
ber of bytes in the bitstream buffer to the VLD.
15.5 VLD OUTPUT
The VLD outputs two data streams which are written
back to main memory by two output DMA engines.
Th ese DM A en gine s are p rogr amm ed by the DS PCP U.
One of the output str eams contains macroblock header
information and the other contains run-length encoded
DCT coefficients. Each DMA engine contains a 64-byte
FIF O whic h is tra ns fe r re d to main m e mo r y on ce it is fu ll .
The main memory address and count f or the macroblock
header output are contained in the VLD_MBH_ADR and
VLD_MBH_CNT registers respectively. The main mem-
or y add r ess and cou nt fo r the D CT coe ffi ci ent ou tp ut ar e
contained in the VLD_RL_ADR and VLD_RL_CNT reg-
isters respectively. The counts for both the macroblock
header and coefficient data are expressed in terms of 32-
bit (4 bytes) words.
15.5.1 Macroblock Header Output Data
For each MPEG-2 macroblock parsed by the VLD, six
32-bit words of macroblock header information will be
output from the VLD. Figure 15-2 pictures the layout of
the VLD output, the fields are described in Table 15-1.
Note that these fields may or may not be valid depending
upon the MPEG-2 video standard[2]. For example, mo-
tion vectors are not valid for intra coded macroblocks.
Similarly, ‘DCT Type’ is not valid for field pictures.
For each MPEG-1 macroblock parsed by the VLD, four
32-bit words of macroblock header information will be
output from the VLD. Figure 15-3 pictures the layout of
the VLD output, while the fields are described in
Table 15-2. Note that these fields m ay or may not be val-
id depending upon the M P EG-1 vi deo standa r d[1].
Table 15-1. References for the MPEG-2 macroblock
header data
Item Default
value
Refe rences from MPEG-2
Video Stan d ard , IS 13818- 2
document
Esc count 0 Section 6.2.5
MBA i nc - Sec tion 6.2.5 and Table B - 1
MB type unde-
fined Section 6.2.5.1 and Tables B-
2, B-3, and B-4; Only 5 Msb
bits fr om the tables ar e used
Mot type unde-
fined Section 6.2.5.1; Field or Frame
motion type will be decided by
the user
DCT type unde-
fined S ection 6.2.5. 1
MV count unde-
fined Tables 6-17 and 6-18. The MV
Count value is one less than
the value from the tables.
MV format unde-
fined Tables 6-17 and 6-18
DMV unde-
fined Tables 6-17 and 6-17
MV field Sel[0]0] to
MV field Sel[1][1] unde-
fined S ection 6.2.5 and 6.2.5.2
Motion
code[0 ][0][0] to
Motion
code[1][1][1]
unde-
fined S ection 6.2.5. 2.1 an d
Table B-10
Motion Res id-
ual[0][0][0] to
Motion Res id-
ual[1][1][1]
unde-
fined S ection 6.2.5. 2.1; the co rre-
spon ding rsize bit s are
extracted from the bitstream
and stored as left justified; to
get the final value shift the
given number by 8 (corre-
sponding rsize). T he rsize val-
ues are stored in VLD_PI
register
dmvector[1] and
dmvector[0] unde-
fined Section 6.2.5.2.1 and Table B-
11; signed 2-bit integer from
Table B11.
CBP - Sec tion 6.2.5, 6.2.5.3 and
Table B- 9
Quant scale - Section 6.2.5; 5-bit from bit-
stream and use Table 7-6 to
compute the quant scale valu e.
Table 15-2. References fo r the MPEG-1 macroblock
he ader data
Item Default
value References from IS 11 172-2
document
Esc count 0 Section 2.4.3.6
MBA in c - Section 2.4.3.6
MB type unde-
fined S ec tion 2.4.3. 6 and Table s B-
2a to B2d
Motion
code[0][0][0] to
Motion
code[0][1][1]
unde-
fined S ec tion 2.4.2. 7 and Table B-4
Motion resid-
ual[0][0][0] to
Motion resid-
ual[0][1][1]
unde-
fined S ec tion 2.4.2.7;the corr e-
sponding rsize bits are
extracted from the bitstream
and stored as left justified; to
get the final value shift the
given number by (8 - corre-
sponding rsize). The rsize val-
ues are stored in VLD_PI
register.
CBP - S ection 2.4.3. 6 and Table B-3
Quant scale - Section 2.4.2.7
PNX1300/01/ 02/11 Data Book Philips Semiconductors
15-4 PRELIMINARY SPECIFICATION
15.5.2 Run-Level Output Data
The DCT coefficients associated with the macroblock are
output to a separate memory area and each DCT coeffi-
c ient is repre sented as one 32-bit quanti ty (16 bits of r un
and 16 bits of level). For intra blocks, the DC term is ex-
pressed as 16 bits of DC size and a 16-bit value whose
most significant bits (the number of bits used for DC level
is determined by DC size ) represent the DC level. Each
block of D C T coefficien t s is terminat ed by a run valu e of
‘0xff’.
15.6 VLD TIME SHARING
The PNX1 30 0 VLD is ta rg ete d for a sing le bitstr eam de-
code and there i s no provi sion to decode more than one
bits trea m a t a time by usi ng th e VL D in tim e m u lti pl exed
mode . How ever in ter na l deve lo pm ent has sh ow n tha t up
to 4 simultaneous MPEG1 bitstreams can be decoded.
This procedure is beyond the scope of this databook but
can be discussed further by contacting customer sup-
port.
15.7 MMIO REGISTERS
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when r ead, an d wri t-
ten as ‘0’s.
15.7.1 VLD Status (VLD_STATUS)
Thi s regist er cont ains the curre nt stat us info rmati on most
pertinent to the normal operation of an MPEG video de-
code application. VLD status description is detailed in
Table 15-3 and pict ure d in Figure 15-4. Default value (af-
ter hardware reset) is ‘0’.
Interr upts can be enabled for any of the defined status
bits (see following VLD_IMASK description). Acknowl-
edgment of the interrupt is done by writing a ‘1’ to the cor-
re spond ing bit in VL D_STAT US regi ster . Wri tin g a one t o
the bits one through five c lears the cor responding bi ts.
However bit 0 (COMMAND_DONE) is cleared only by i s-
suing a new command. Writing a ‘0’ to bit 0 of the status
re gist er will res ult in undefined beha vior of the VLD. Note
that se veral status bits may be asserted simultaneously.
Thus it is recommended to use level triggered interrupts
(see Section 3.5.3.6 on page 3-11) and carefully ac-
k nowledge th e interru pt.
15.7.2 VLD Interrupt Enable (VLD_IMASK)
This r e gis ter allow s the DS PC PU to c on t rol the in itiati on
of the interrupt for the corresponding bits in the VLD Sta-
tus Register. Writing a ‘1’ into any of the defined
VLD_IMASK bits enables the interrupt for the corre-
spond ing bit in the status register (VLD_STATUS). De-
fault v alue (a fte r hardware re set) is ‘0’.
Esc Count MBA Inc MB Type
Motion Code [0][0][1]Motion Residual [0][0][0] Motion Residual [0][0][1]Motion Code [0][0][0]
Motion Code [0][1][1]Motion Residual [0][1][0] Motion Residual [0][1][1]Motion Code [0][1][0]
quant scaleCBP
31
First Forward Motion Vector
First Backward Motion Vector
012346111725
71523293031 13
71523293031 13
410121431
Figur e 15-3. MPEG1 Macroblock Header Output Format
w1
w2
w3
w0
MB1
MB2
Philips Semiconductors Variable Length Decoder
PRELIMINARY SPECIFICATION 15-5
15.7.3 VLD Control (VLD_CTL)
The VLD_CTL register has one bit indicating the endian-
nes s of the VLD un it. Li ttl e- Endi an = ‘1’, B ig-Endian = ‘0’.
Default value (after hardware reset) is ‘0’.
15.8 VLD DMA REGISTERS
There are one input DMA engine and two output DMA
engines in the VLD block. Each of the three DMA en-
gines (or channels) for the VLD is controlled by two
MMIO registers. The address register always contains
the address of the next SDRAM tra nsaction. The count
register always indicates the amount of data to be trans-
ferred to or from mai n memory. A DM A c ompl etes when
its coun t reaches zero. Once a DMA count re gister be-
comes zero, a bit is set in the status register and the
DSPCPU can be interrupted. The DSPCPU sets a non-
zero value to a DMA count register to initiate a new DMA
transaction. The input count register always contains
number of bytes to be fetched from the main memory.
The output count registers always contain the number of
word s (4 by tes) to be w ri tten to the m ai n me m ory .
Not e that both of th e DMA output engines wr ite only to
64-byte aligned addresses and they always write 64
byt es. Wh en fl ush ing the DM A out put FI FOs th ere m ay
not be 64 bytes of valid data at the time t he flush com-
mand is received. In this case, 64 bytes are still written to
the main memory. The valid bytes can be determined
from the count register value before issuing the flush
command. The valid data always resides in the first N
byt e s whil e t h e la s t 64 -N byte s w il l c ont a in ra ndom d ata
and shou ld be ignored.
15.8.1 DMA Input
The bitstream input to the VLD is controlled by
VLD_BIT_ADR and VLD_BIT_CNT MMIO registers.
VLD_BIT_ADR contains the main memory address for
the next read from the main memory to the VLD input
FIFO. VLD_BIT_CNT register contains the number of
bytes remaining to be read before the current DMA is
completed.
The VLD input addr ess is byte aligne d.
15.8.2 Macroblock Header Output DMA
The macrob lock header output of the VLD is contro lled
by VLD_MBH_ADR and VLD_MBH_CNT registers.
VLD_MBH_ADR contains the address of the next write
of macroblock header data to the main memory.
VLD_MBH_CNT contains the remaining number of
words (4 bytes) to write before the current DMA expires.
The macroblock header output address is 64-byte
aligned.
15.8. 3 Run-Leve l Output DMA
The run-level output of the VLD is controlled by
VLD_RL_ADR and VLD_RL_CNT. VLD_RL_ADR con-
tains the address of the next w r ite of macrobl ock header
data to the main memory. VLD_RL_CNT contains the
number of 4-byte writes remaining before the current
DMA expires.
The ru n-level buf fer address is 64 -byte alig ned.
Ta ble 15-3. VLD_STATUS r egister
Name Size
(bits) Description
COMMAND_DONE 1 Indicates successful completion
of current command
STARTCODE 1 VLD enco untered 0 x000001
while executing parse or next
start code command
ERROR 1 VLD encountered an illegal
Hu ffman c ode or a n unexpected
start code
DMA_IN_DONE 1 DMA transfer of given SDRAM
buffer has completed and VLD
is stalled waiting on more main
memory input data; DSPCPU is
responsible to provide the new
SDRAM buffer to VLD
MBH_OUT_DONE 1 Macroblock Header DMA trans-
fer has completed
RL_ OUT_DO NE 1 Run- level DMA tran sfer c om-
plete
Ta ble 15-4. VLD c ontrol (R/W)
Name Size
(bits) Description
Reserved 1
Little Endian 1 Forces VLD to operate in Little
Endian Mode when set to 1.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
15-6 PRELIMINARY SPECIFICATION
Figure 15-4. VLD MMIO Registers Layout.
31 0371115192327
MMIO_base
offset:
VLD_COMMAND (r/w)0x10 2800
VLD_STATUS (r)0x10 2810
RL_OUT_DONE
MBH_OUT_DONE
DMA_IN_DONE
ERROR
STARTCODE
COMMAND_DONE
VLD_CTL (r/w)0x10 2818
COMMAND COUNT
31 0371115192327
31 0371115192327
31 0371115192327
VLD_SR (r)0x10 2804
31 0371115192327
31 0371115192327
31 0371115192327
VALUE
VLD_QS (r/w)0x10 2808
VLD_PI (r/w)0x10 280C
QS
VBRS HBRS VFRS HFRS
MPEG2 CONCEAL_MV
INTRA_VLC
FPFD
PICT_STRUC
PICT_TYPE
VLD_RL_CNT (r/w)0x10 2830 31 0371115192327
VLD_BIT_ADR (r/w)0 x10 281C
VLD_BIT_CNT (r/w)0x10 2820 31 0371115192327
VLD_MBH_ADR (r/w)0x10 2824 31 0371115192327
VLD_MBH_CNT (r/w)0x10 2828 31 0371115192327
VLD_RL_ADR (r/w)0 x10 282C 31 0371115192327
LITTLE_ENDIAN
BIT_ADR
MBH_ADR
RL_ADR
BIT_CNT
RL_CNT
MBH_CNT
VLD_IMASK (r/ w)0x10 2814 Int. Enables
0 0 0 0 0 0
0 0 0 0 0 0
Philips Semiconductors Variable Length Decoder
PRELIMINARY SPECIFICATION 15-7
15.9 VLD OPERATI ONAL REGISTERS
15.9.1 VLD Com mand (VLD_COMMAND)
This register indicates the next action to be taken by t he
VLD. Some commands have an associated count which
resides in the least significant 8 bits of this register. There
are currently five commands recognized by the VLD
block:
•Shift the bitstream by ‘count’ bits (‘count’ must be
less than or equal to 15)
•Parse ‘count’ un-sk ipp ed macr o blocks
•Search for the next start code
•Reset the VLD
•Flush the VLD output buffers
The DSPCPU must wait for the VLD to halt before the
nex t co mma nd can be issu ed . Not e tha t the r e are se ver -
al ways in which a command may complete. Only a suc-
cessful completion is indicated by the
COMMAND_DONE bit in the status register. A command
may complete unsuccessfully if a start code or an error is
encountered before the requested number of items has
been processed. Note also that expiration of a DMA
count does not constitute completion of a command.
When a DMA count expires the VLD is stalled as it waits
for a new DMA to be initiated. It is not halted. Default val-
ue (after hardware reset) is ‘0’. VLD_COMMAND fields
are des cribed in Table 15-5 and the different commands
exp laine d in Table 15-6.
15.9.2 VLD Shift Register (VLD_SR)
Th is re ad on ly reg ist er is a s hado w of th e VL D’s op era-
tional shift register. Tt allows the DSPCPU to access the
bit st re am t h roug h th e VL D. B i ts 0 th rou gh 15 are the cur-
ren t cont en ts of t he VLD shift regi st er. Bi t s 1 6 to 31 ar e
RESER VED and should be tr eated as undefined by the
programmer.
15.9.3 VLD Quantizer Scale (VLD_QS)
This 5-bit register contains the quantization scale code
(from th e slic e he ade r ) to be out put by t he VL D unt il it is
overridden by a macroblock quantizer scale code. The
quantizer scale code is part of the macroblock header
output.
Tabl e 15-5. VL D Command Register
Name Size
(bits) Description
COUN T 8 Count for current comm and
COMMAND 4 VLD command to be exe-
cuted
Ta ble 15-6. VLD Commands
Command Field
coding
Flags Set after
Completion of the
Command Description
Shift the bitstream
by ‘count’ bits 1 COMMAND_DONE
or
DMA_IN_DONE
VLD shift s the number of bits in its internal shift register. The sh ift register value
is available in the VLD_SR register.
The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.
The flag is reset by issu ing the new command.
Sear ch for the
next start code 3 STARTCODE
or
COMMAND_DONE
or
DMA_IN_DONE
VLD search for a start code. The search code has 0x000001 prefix and an addi-
tional 8-bit value.
The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.
The STA RTCODE detected flag is reset by writing a ‘1’ value to the flag.
The COMMAND_D ONE flag is rese t by issuing the new command.
Reset the VLD 4 None Refer section 15.12 for more details
Parse for a given
number of mac-
roblocks
2 COMMAND_DONE
or
STARTCODE
or
ERROR
or
DMA_IN_DONE
VLD parses for a given number of un-skipped macroblocks and the associated
run-level values. COUNT will indicate the remaining macroblocks to parse. Note
t hat this number is sl ightly inaccurate since a par sed macroblock can stil l be in
internal 64- byte FIFO.
If VLD encounters a start code, the parsing action will be terminated and VLD
sets only the S TARTCODE detected flag. If VLD parses the given number of un-
skipped macroblocks without encountering a start code, VLD will s et the
COMMAND_DONE flag.
The ERROR fla g will be set when VLD encounters an error w hile parsing the bit-
stream.
The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.
The STA RTCODE detected flag is reset by writing a ‘1’ value to the flag.
The COMMAND_D ONE flag is rese t by issuing the new command.
Flush the VLD out-
put buffer 8 COMMAND_DONE VLD flushes the remaining macroblock header data and the remaining run-level
data to SDRAM. The highway byte-enables w ill be used in order to write only the
valid data to SDRAM. Only the valid word count values written to SDRAM will be
subtracted from the VLD_MBH_CNT and the VLD_RL_CNT registers.
PNX1300/01/ 02/11 Data Book Philips Semiconductors
15-8 PRELIMINARY SPECIFICATION
15.9.4 VLD Picture Info (VLD_PI)
Thi s 32- bi t reg is ter conta in s th e pic t ure la ye r inf or ma tio n
nece ssary for the VLD to parse the macro blocks within
that picture. Again, the values for each of these fields are
det e rmi ned by th e ap pr o priate sta nd ard ( MPEG [1 -3] ).
15.10 ERROR HANDLING
Upon encountering a bitstream error, the VLD will set the
bits tream-e rr or flag (E RROR) i n the VLD_S TATUS reg -
ister and interrupt the DSPCPU, if the interrupt is en-
abled. Note that if a start code is present (in the VLD shift
register) when an error is detected, then both the start
code and the error bits will be set. A separate flush com-
man d i s requ ired t o f lush any v alid da ta in the r un-l evel
and macroblock header output buffers.
Th e DSPC PU de-as ser ts th e ERR OR f lag s b y wri ting a
‘1’ to the ERROR flag.
15.11 INTERRUPT
The interrupt source number for the VLD is 14 and it
should be set in level sensitive mode (see Section
3.5.3.6 on pag e3-11).
15.12 RESET
The VLD block is reset by a hard w are reset or a softw are
reset. The hardware reset signal is generated from the
external pin TRI_RESET#. The software reset is initiated
by writing a ‘Reset VLD’ command in the
VLD_COMMAND register. Refer Table 15-8 for the de-
tails on the software reset procedure.
15.13 ENDIAN-NESS
VL D s upp orts litt le-e ndia n an d big -endi an m ode s of op-
erations. Refer to Appendix C for the endian-ness spec-
ification of the VLD input and output data.
15.14 POWER DOWN
The VLD block can be separately powered down by set-
tin g a bi t in t h e BLO C K_ P O W E R_D O W N re gi ster . For a
description of powerdown, see Chapter 21, “Po w er Ma n -
agement.”
The VLD b lock should not be active when applying block
powerdown.
If the block enters power-down state while it is enabled,
its behavior upon power-up is undefined.
15.15 REFERENCES
[1] ISO/IEC IS 13818-2, International Standard (1994),
MPEG-2 Vid eo.
[2] ISO/IEC IS 11172-2, International Standard (1992),
MPEG-1 Vid eo.
[3] MPEG Video Compression Standard, by Joan L.
Mitchel l, William B. Pennebaker, Chad E. Fogg, Didier J.
LeGall; ITP publication.
Ta ble 15-7. VLD pictur e info register (r/w)
Name Size
(bits) Description
PICT_TYPE (picture
type) 2 I, P, or B picture
PICT_STRUC (picture
structure) 2 field or frame picture
FPFD (frame predic-
tion frame dct) 1 s pec ifi es that th is pic tur e
uses onl y frame predic tio n
and frame dct
INTRA_VLC 1 Use DCT table zero or one
CONCEAL_MV 1 concealment vectors present
in the bitstream
reserved 6 Reserved for future expan-
sion
MPEG2 mode 1 Switches VLD between
MPEG-1 and MPEG-2
decoding.
Value ‘1’ = MPEG-2 mode
reserved 2 reserved
HFRS (h orizontal for-
ward rsize) 4 s ize of residual motion vecto r
VFRS (ve rtical forward
rsize) 4 size of re sidual motion vector
HBRS (horizontal
backward rsize) 4 size of residual motion vecto r
VBRS (ver ti ca l back-
ward rsize) 4 s ize of residual motion vecto r
Table 15-8. Soft ware reset procedur e
Cycle
no. Action Remarks
i DSPCPU issues the ‘Reset
the VLD’ command by writ-
ing the required value in the
VLD_COMMAND r egister.
i to j VLD will complete the pend-
ing, if any, highway transac-
tions.
Any hi ghway transac-
tions, once started, will
not be aborted in the
middle
j+1 VLD will perform the full
reset. All sta tus and contr ol
regi st ers ar e res et and
all the buffe rs are
made empty.
M M I O Regist e r s init ial-
ized to zero includes
VLD_STATUS.
PRELIMINARY SPECIFICATION 16-1
I2C Interface Chapter 16
by Essam Abu-ghoush, Robert Nichols
16.1 I2C OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 includes an I2C i nt e rfa ce wh ic h ca n be us ed to
control many different multimedia devices such as:
•DM S D s - Digital multi - standa r d decoders
•DENCs - Digital encoders
•Digital cameras
•I2C - Parallel I/O expa nder s
The key features of the I2C interface are:
•Su pports I2C single ma ster mode
•I2C dat a r ate up t o 400 kbits/sec
•Support for the 7-bit addressing option of the I2C
specification
•Provisions for full software use of I2C interface pins
for implem enting software I2C or similar protocols
Note that the I2C pi ns are also us ed to load the initial boot
parameters and/or code from a serial EEPROM as de-
scribed i n Section 13, “System Boot”. The boot logic is
only active upon PNX1300 hardware reset and quiescent
afterwards.
A typical system using the I2C interface i s presented in
Figure 16-1. The PN X130 0 is co nnec ted as a mas ter to
a series of slave devices through SCL and SDA. Note
that the bus has one pullup resistor for each of the clock
and data lines. The pullup should be set to a voltage no
higher than VREF_PERIP H.
16.2 COMPARED TO TM-1000
The following are the main I2C differences from TM-
1000:
•The SEX bit is removed. Endian-ness is fixed.
•The I2C clock r ate is clos er to 100/400 kH z
•The GDI bit now correctly indicates write- completion
•Clock stretching is always enabled.
16.3 EXTERNAL INTERFACE
The I2C external interface is composed of two signals as
s how n in Table 16-1.
16.4 I2C REGISTER SET
The I2C user interface consists of four registers visible to
the programmer. The registers are mapped into the
MMIO address space and are fully accessible to the pro-
grammer. Figure 16-2 shows the I2C register set. To en-
sure compatibility with future devices, any undefined
MMIO bits should be ignored when read, and written as
‘0’s.
16.4.1 IIC_A R Register
The IIC_AR is the I2C address register and is used in both
master receive and tra nsmit modes. This regi ster is writ-
ten with the address(es) of the I2C slave device and the
bytecount for transmit/receive. Table 16-2 lists the bit-
field definitions fo r the IIC_AR re gister .
Figure 16-1. Typical I2C system implementation
SCL
SDA
PNX1300 Slave
I2C
Slave
I2C
+ VREF_PERIP H
RpRp
Table 16-1. I2C Ex ternal interface
Signal Type Description
IIC_SDA I/O I2C serial data
IIC_SCL O I2C clock
Table 16-2. IIC_AR Register
Bits Fie ld Name Definition
31:25 ADDRESS 7-bit slave device address.
24 DIRECTION Read/Write control bit
23:16 reserved must be written to ‘0’
15:8 COUNT Byte count of requested transf er
7:0 res erved Read as ‘0’
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
16-2 PRELIMINARY SPECIFICATION
ADDRESS must be programmed to contain the 7 bits of
th e des ired sl av e address
The DIRECTION bitfield controls read/write operation on
the I2C inter fac e. The bi t defi ni tion is :
•DIRECTION = 0 –> I2C w rite
•DIRECTION = 1 –> I2C read
The COUNT field must contain the desired bytecount for
the current transfer. The COUNT field will decrement by
one for each data byte transferred across I2C. The re-
maining bytecount for the current transfer can be read
from the COUNT field at any time. Note that the
DS PCPU must re f rai n fr om rewrit i ng the IIC_AR regi st er
until the current transfer completes to avoid corrupting
the bytecount or a ddres s fi elds.
Note: Fo r writes , the b yte co unt de creme nts b efore the
byte is actually transferred over the I2C bus. However,
the last byte is saved in an internal register and the
DSP CPU can w rite a new wo rd when C OUNT = 0.
16.4.2 IIC_D R Register
The IIC_ DR regis ter cont ains the actual data transferred
during I2C operation. For a master transmit operation,
data transfer will be initiated when data is writ ten to this
reg iste r. Tra ns miss ion will be gi n wit h the tr an sfer of th e
address byte in the IIC_A R register followed by the data
bytes that were written to the IIC_DR register, byte3 first
and byte0 last. The I2C interface will interrupt for more
transmit data to be written to the IIC_DR until the transfer
by tecou nt COUNT in the IIC_AR register is reached.
In master receive operation, one or more data bytes re-
ceived are placed in the IIC_DR register by the I2C inter-
face. Data bytes received are loaded into the IIC_DR
register starting with byte3, then byte2, byte1 and byte0.:
The numbe r of by tes t he DSPCPU r eques ts for a tran sfer
is written into the COUNT bitfield of the IIC_AR register .
Th e tra nsf er com plet es w hen the I2C interf ace receiv es
the number of bytes indicated by the COUNT bitfield of
th e I I C_A R re gist e r.
Figure 16-2. I2C registers
MMIO_base
offset:
IIC_AR (r/w)0x10 3400 037111519232731
COUNT
IIC_DR (r/w)0 x10 3404 037111519232731
IIC_SR (r/o)0x10 3408 037111519232731
reserved
DIRECTION
ADDRESS
BYTE3 BYTE2 BYTE1 BYTE0
reserved
DIRECTION
STATE
SDNACKI
SANACKI
FI
GDI
GD_IEN
F_IEN
SDNACK_IEN
SANACK_IEN
IIC_CR (r/w)0x10 340C 037111519232731
CLRFI
CLRGDI
CLRSANACKI
CLRSDNACKI
ENABLE
RBC
SDA_STAT
SCL_STAT
SW_MODE_EN
SDA_OUT
SCL_OUT
Philips Semiconductors I2C Interface
PRELIMINARY SPECIFICATION 16-3
16.4.3 IIC_S R Register
The I2C status register contains status information re-
gar ding the t ran sf er in p rog ress and t he natur e o f inte r-
rupts associated with I2C operation.
Th e IIC _SR regi st er is re ad only and is inte nded a s the
primary source of status regarding current I2C operation.
The IIC_SR register must be used in conjunction with the
II C_CR r egiste r. The int erru pt sour ces of the IIC_SR re g-
is ter are indi vidual ly ena bled by writ ing t o the appropriate
enab le bit i n th e I IC_CR re gist er. The bi tfi eld de finit ions
of the IIC_SR register are presented in Table 16-3. The
IIC_ SR p rov ides fo ur sou r ce s of inte r rupts . No te: the in-
terrupt should be set up as level triggered interrupt.
•GDI interrupt — The GD I bit toge th er with the FI bi ts
provide status about I2C transfer completion. The
interpretation of GDI/FI bit combinations are different
depe nding on whether the I2C interface is in master
transmit or ma ster receive mode. Refer to Table 16-4
and Table 16-6 for GDI/FI interpretation.
•FI interrupt — See GDI bit definition and GDI/FI
transmit and receive definitions in Table 16-4 and
Table 16-6.
•SANACKI interrupt — This interrupt flag bit indicates
th at a sl ave addre ss wa s transm it ted but n o slave on
the I2C bus acknowledges the address to claim the
transaction. This is an error condit ion. On ce the I2C
interface has set this interrupt flag, the interface is
idle. The DSP CPU s hou ld cl ear t his i nt errup t f lag by
writing a ‘1’ to IIC_CR.CLRSANACKI before re-
at temp ting t his transfer or starti ng an other I2C trans-
fer.
•SDNACKI interrupt — This interrupt flag bit indicates
th at an addr es sed slave r ece iver devic e ha s refus ed
to ack no wl edge the c u rre nt byte of data fo r an on g o-
ing transfer. T his is a n error condition. Once the I 2C
interface has set this interrupt flag, the interface is
idle. The DSP CPU s hou ld cl ear t his i nt errup t f lag by
writing a ‘1’ to IIC_CR. CLRSDNACKI before retr ying
this transfer or starting another.
The SDA_STAT and SCL_STAT bits indicate th e current
st at e of the SDA an d S C L s ig nals. T he STATE field in di -
Table 16-3. IIC_SR register
Bits Field Name Definition
31 GDI Good Data Interrupt. This is the nor-
mal transfer complete interrupt flag.
This interrupt may be asserted without
the IIC_S R.FI interrupt bit at the end of
an I2C transfer or after master abort of
an I2C transfer.
30 FI Full Interrupt. This interrupt indicates
the condition of the IIC_DR register
dependent upon whether the I2C inter-
face is in r ecei ve or transmit mode.
29 SANACKI Slave Address No Acknowledge Inter-
rupt.
28 SDNACKI Slave Data No Ac knowledge Interrupt.
27 SD A_STAT This bit is used to examine the state of
the e xternal I2C SDA data pin. Bit
p o larity is :
1 = SDA pad is low
0 = SDA pad floated high
26 SCL_STAT This bi t is used to examine the state of
the e xternal I2C SCL clock pin. Bit
p o larity is :
1 = SCL pad is low
0 = SCL pad floated hig h
25:23 STATE The STATE field indicates the microac-
tiv ity of the I2C bus.
22 DIRECTION Direction of current data transfer.
21 Reserved Read as ‘0’
15:8 RB C Remai ning Byte Count.
7:0 Reserved Read as ‘0’
Table 16-4. Master transm it mode GDI/FI status
GDI FI Description
0 0 Message is not complete. The IIC_DR is not
empty. No interrupt.
0 1 Message is not complete. The IIC_DR is empty
and the requested transmit byte count is not
equal to 0. The DSPCPU must write additional
bytes of the current transfer to the IIC_DR regis-
ter.
1 X Message transmission has completed. The
IIC_DR is empty. The byte transmit count = 0.
Tabl e 16- 5. S TAT E fie ld valu es
STATE Meaning
000 I2C Interface is idle.
001 RESERVED FOR FUTURE USE
010 IDL E (MS G i s done, awai ting clear GDI to go to
000 state)
011 Address phase is being processed
100 BYT E3 (fi rst byte) is being processed
101 BYT E2 is being processed
110 BYT E1 is being processed
111 BYT E0 (l ast) is bein g processed
Table 16-6. Master receive GDI/FI conditions
GDI FI Description
0 0 Message is not complete. IIC_DR is not full.
No interrupt.
0 1 IIC_DR contains received data and needs to
be read serviced. More data bytes are
expected since the receive b yte count is not
equal to 0.
1 X The transfer has been completed and the
receive byte count is equal to 0. 0 to 4 valid
bytes are in the IIC_DR register awaiting read
servicing by the DSPCPU.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
16-4 PRELIMINARY SPECIFICATION
ca te s the m ic r oa c tivity of th e I2C i nte r face. The fiel d val-
ues an d thei r mean i ng s ar e pre sen t ed in Table 16-5 The
DIRECTION status bit indicates if the I2C inter fac e is in
transmit or receive mode.
•if DI RE CTION = 0 then I 2C is a transmitter.
•if DI RE CTION = 1 then I 2C is a receiver.
The RBC bitf ield i ndic ates th e rem aining byte count f or an
I2C transfer in pr ogress. The IIC_SR.RBC bitfield serves
as a read-only ‘s hadow register’ for the IIC_AR.COUNT
bitfield. During I2C transfer, the RBC bitfield will reflect
the remaining bytecount. To avoid corrupting an I2C
transfer, the DSPCPU must refrain from writing to the
IIC_AR.COUNT bitfield until a message is complete.
Co mpleti on is indi cate d by the RBC bitf ield d ecre mentin g
to ze ro .
16.4. 4 IIC_CR Register
The I 2C co ntr ol re gi ster c o ntain s co nt rol in fo rmati on re-
quired for enabling I2C transfers. This register is used to
enable and clear inte rrupt sources w hich normally occur
during I2C operation. The four interrupt sources de-
scribed in the section on the IIC_SR register are enabled
and cleared through the IIC_CR register. The enable bit-
fields are:
•GD_IEN — Enable for normal transfer complete
interrupt.
•F_IEN — Enable for IIC_DR data service request
interrupt.
•SANACK_IEN — Enable for slave address not
acknowledged interrupt. This is an error interr upt.
•SDNACK_IEN — Enabl e for slave data no t ackno wl-
edged interrupt. An addressed slave receiver has
ref used to acce pt the last by te tran smitte d to it. This
is handled as an error interrupt.
In a dditi on to the inter rupt enable bits , the I IC_CR c on-
tai ns inte rrupt clear bi ts ass ocia ted w ith each of the inter-
rupt sour ces in t he IIC_SR register. Thes e IIC _CR inter-
rupt clear bits are define d as :
•CLRGDI — Clear bit for the GDI interrupt in the
IIC_SR register. Writing a ‘1’ to th is bit cl ears the G DI
interrupt.
•CLRFI — Clear bit for the FI interrupt in the IIC_SR
register. Writing a ‘1’ to this bit clears the FI interr upt.
•CLRSANACKI — Clear bit for the SANACKI inter-
rupt in the IIC_SR register. Writing a ‘1’ to this bit
cl ears the SA N ACK I inter r upt.
•CLRSDNACKI — Clear bit for the SDNACKI inter-
rupt in the IIC_SR register. Writing a ‘1’ to this bit
clea rs th e S DN ACKI interrupt.
The remaining bitfield of the IIC_CR register is:
•ENABLE — Master enable for I2C serial interface.
ENA BLE mus t be se t eq ual t o ‘1’ to tran sfer a ny bits
from the I2C interface block. Writing a ‘0’ to the
Table 16-7. IIC_CR Register
Bits Field Name Definition
31 GD _IEN Enable for normal trans fer complete
interrupt
30 F_IEN Enable for IIC_DR data ser vice
request interrupt
29 SANACK_IEN Enable for slave address not
acknowledged interru pt
28 SDNACK_IEN Enable for slave data not acknowl-
edged inte rru pt. An addressed slave
receiver has refused to accept the
last byte transmitted to it
27:26 Reserv ed1 Always write ‘0’s to these bits.
(See Note1)
25 CLRGDI Clear bit for the GDI interru pt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the GDI interrupt
24 CLRFI Clear bit for the FI interrupt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the FI interrupt
23 CLRSANACKI Clear bit for the SA NACKI interrupt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SANACKI interrupt.
22 CLRS DNACKI Clear bit for the SDNACKI interr upt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SDNACKI inter-
rupt.
21:6 Re s erved2 Alw ays write ‘0’s to these bits.
(See Note1)
10 SW_MODE _EN 0 (power-on/reset default) - Normal
I2C hardware operating mode.
1 - Enable software operating mode.
The I2C pins are entirely controlled
by user writes to the ‘sda_out’ and
‘scl_out’ regis ter bi ts.
7 SDA_OUT Enabled by sw_mode_en. This bit is
used by sw to manually control the
e xternal I2C SDA data pin. Bit polar-
ity is:
1 = SDA pad pulled low
0 = SDA pad left open drain
6 SCL_OUT Enabled by sw_mode_en. This bit is
used by sw to manually control the
e xternal I2C SCL clock pin. Bit polar-
ity is:
1 = SCL pad pulled low
0 = SCL pad left open drain
5:2 Reserv ed3 Always write ‘0’s to these bits.
(See Note1)
1 Reserv ed4 Always write ‘0’s to these bits.
(See Note1)
0ENABLE
I2C serial interface enable
Table 16-7. IIC_CR Register (Continued)
Bits Field Name Definition
Philips Semiconductors I2C Interface
PRELIMINARY SPECIFICATION 16-5
ENABLE bit effectively resets the entire I2C interface,
including all status and interrupt flag bits. A transfer
in progress is aborted and the byte currently trans-
ferred is lost.
Note: For writes, Reserved1, 2, 3 and 4 bitfields
MUST always be written with ‘0’s.
16.5 I2C S OFTW AR E O PE RAT IO N M O DE
I2C sof tw a r e op era t io n m od e is in te nd ed fo r us e by sof t-
ware I2C or similar algorithm implementations. In this
case, the SCL and SDA pins are fully controlled and ob-
served by software, and the hardware I2C interface is
disconnected from the SCL and SDA pins. Refer to
Figure 16-3 for a clarification of the principles involved.
Software mode is by default disabled after boot. Soft-
ware mode is enabled by writing a ‘1’ to
IIC_CR.SW_MODE_EN. At that point, the SC L a nd SDA
pins can be controlled by the IIC_CR SDA_OUT and
SC L_OUT bits. Writing a ‘1’ to either bit causes the cor-
responding pin to become active, i.e. be pulled low. The
SDA and SC L lines a re op en -col lecto r o utpu ts, a nd can
hence a lso be pulled low by external devices . The a ct u a l
pin state can be observed by software by examining
IIC_SR SDA_STAT and SCL_STAT bits. A 1 in these
MMIO bits indicates that the corresponding pin is cur-
rently pulled low.
By ap pr opr i ate so f twa r e, possi bl y us in g a tim er in ter rup t,
full I2C functionality can be implemented using this
mechanism.
16.6 I2C HA RDW ARE OPE RATI ON MODE
Ha rdw are oper a tio n o f I 2C is the default mode after boot.
The PNX1300 I2C hardware interface operates in one of
two modes:
1. M as t e r -t ransm itter (to w rite data to a slave)
2. Master-re c e iver ( to read data from a slave)
As a ma ster, the I2C logi c will g ener ate all the s erial c lock
pulses and the START and STOP bus conditions. The
START and STOP bus conditions are shown in
Figure 16-4. A tran sfer is ended with a STOP cond ition
or a repeated START condition. Since a repeated
STA R T con dition i s a ls o the be gi nnin g o f the next seria l
transfer, the I2C bus will not be released.
Note: The I2C interface on PNX1300 will operate as a
master ONLY!
The number of bytes transferred between the START
and S TO P con dit ions from tra nsm itter to r ece iver i s no t
li mi te d. Eac h 8- b it da t a by te is fo llow e d by on e ac kn ow l -
edge bit. The transmitter releases the SDA line which will
pull- up t o a H IG H le ve l du r in g th e ac k now le dg e bit tim e .
The receiver acknowledges by pulling the data line LOW
SCL
SDA
hardware
DATA
HIWAY
open drain
scl_stat
scl_out
I2C
DQ
sda_stat
sda_out
tribuf
tribuf
sw_mode_en
sw_mode_en
buf
open drain
buf
DQ
Figure 16- 3 . I2C softw are m ode only logic
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
16-6 PRELIMINARY SPECIFICATION
during th is ackn ow ledge period. The ma ster must always
generate the SCL transitions for the acknowledge bit
time.
Two types of data transfers are supported by the
PNX1300 I2C interface:
•Data transfer from a master transmitter to a slave
rec eiver, als o call ed a W RIT E oper atio n. Th e mas ter
first transmits a 1-byte slave address, then the
desired number of data bytes. The slave receiver
retu rns an acknowledge bit after ea ch byte. The mas-
ter terminates the transaction by a STOP after the
last byte.
•Data transfer from slave transmitter to master
rec e iver, al s o ca lle d a RE AD oper at io n. Th e firs t by te
(the slave address) is transmitted by the master and
acknowledged by the slave. The selected slave
transmits successive data bytes which are each
acknowledged by the master, except the last byte
desired by the master, for which the master gener-
ates a ‘notack’ condition. This causes the slave to
terminate byte transmission. The slave transmitter
then must release the bus so that the master may
gener ate a STOP co ndition.
The type of tr ansa ction i s ind icat ed by the LS bit of the a d-
dres s byte. D ata tr ansfer fro m a mas ter tr ansmi tter to a
s lave r ece i ver is ca ll ed a WRI TE. It is signi f ie d by a ‘0’ in
the LSbit of the address byte. Data trans fer from a slave
transmitter to a master receiver is called a READ. It is
signified by a ‘1’ in the L SBit of the address byte.
Example steps for successful programming of the I2C in-
terface on PNX1300 are outlined as follows for both
reads and writes. Enable the I2C interface prior to at-
temp ting an y ac c es se s to ex tern al I2C devices.
To en able t h e interfac e:
•Set bit IIC_CR.E NABLE ( 0x10340c) = 1
For write addressing mo de:
1. On entry, clear any possible I2C inte r rupt sources by
writing IIC_CR bits [25:22] = ‘1111’. (Note that pro-
gram mers must mask an d e nable high- level in terrup t
sources through the VIC facility in the DSPCPU. See
the appropriate PNX1300 databook chapter).
2. Enable desired I2C in te rru pt s ou r ces by setti ng
IIC_CR[31:28] bits appropriately.
3. Simultaneously load IIC_AR[31:25] with 7-bit slave
address, IIC_AR.DIRECTION = 0 and IIC_AR[15:8]
with the ap prop riate by t ec o unt for th e tr ansfer.
4. Load IIC_DR[31:0] with data for the write. Note that
writing this register triggers the transfer across the I2C
bus.Up to 4 bytes will be transferred after writing, de-
pendent on b ytecount in IIC _AR[8:15}.Transfers of
mor e th an 4 by te s ha v e to be don e b y brea ki ng the m
down into a sequence of 4-byte transfer s and a last
transfer which may be less than 4 bytes. This is done
by repeatedly reloading the register until the byte-
c ount i s f ulfil led. Transfer is done hig h b yte fi rst , pro-
ceeding to low byte.
5. Detect I2C resulting condition code in IIC_SR[31:28]
and respond - OR - Detect I 2C high le ve l inter rupt and
respond. (Note that this last step is dependent upon
system software requiremen ts).
6. If trans fer count is not yet fulfilled, clear GDI and FI
bit s and pr o ceed wit h step iv ) unt il all data is w ritt e n.
Fo r re ad add r es sing m ode:
1. On entry, clear any possible I2C interrupt sources by
writing IIC_CR bits [25:22] = ‘1111’. (Note th at pro-
grammers must mask and enabl e high level interrupt
sources through the VIC facility in the DSPCPU. See
the appropriate databook chapter).
2. Enable desired I2C in te rru pt s ou r ces by setti ng
IIC_CR[31:28] bits appropriately.
3. Simultaneously load IIC_AR[31:25] with 7-bit slave
address, IIC_AR.DIRECTION = 1 and IIC_AR[15:8]
with the ap prop riate by t ec o unt for th e tr ansfer. Not e
that wri tin g thi s reg is te r tr ig g ers the rea d ac ros s the
I2C bus .
4. Detect I2C resulting condition in IIC_SR[31:28] and
respond - OR - Detect I2C interrupt and respond.
(Note that this last step is dependent u pon system
software requirements.)
5. Clear GDI and FI bits and read the contents of
IIC_DR. Up to 4 bytes will be available in IIC_DR, fe-
v er if the re main in g b yt ec ou nt w as less th an 4. Byte s
are s tor ed high byte fi r st, proceeding t o low byte.
6. Proceed with step iv) until all dat a is read, i.e byte-
count is fulfilled.
16.6.1 Slave NAK
If a slave device does not generate an ACK where re-
quir e d, this i s co ns id ered a NA K. U p on rece ipt of a NAK
after transmitting a device address or data byte, the mas-
ter takes the following actions:
•the I2C st ate beco mes I D L E (STAT E = 000)
•a STOP condition is issued on the bus
•no mor e data is sent
SDA
SCL SP
START STOP
Figure 16-4. START and STOP Conditions on I2C
Philips Semiconductors I2C Interface
PRELIMINARY SPECIFICATION 16-7
16.7 I2C CL OC K RAT E GE NER AT IO N
The I2C hardware block diagram is shown in Figure 16-5
below. In hardware operating mode, the IIC__SCL exter-
nal clock is derived by division from t he BOOT_CLK pin
on PNX1300. The BOOT_CLK pin is normally connected
to TRI_CLKIN. Th e IIC__SCL c lock d ivider va lue is de-
termined at boot time and cannot be changed thereafter.
The value chose n depends on th e first byte re ad fro m the
EEPROM , as descr ibe d in Section 13.2 .1, “Boot Proce-
dure Common to Both Autonomous and Host-Assisted
Bootstrap.”
The PNX1300 I2C block is able to ‘stretch’ the S CL cl o ck
in response to slaves that need to slow down byte trans-
fer. This mechanism of slowing SCL in response to a
sl av e is called ‘c loc k st ret ching.’ This clock stre tching is
acc ompl ishe d by the sl ave by hold in g t he S CL line ‘low’after completion of a byte transfer and acknowledge se-
quence. Clock stretching is always enabled.
Table 16-8. I2C speed and EEPROM byte 0
BOOT_CLK
bits EEPROM
speed bit divider
value actual I2C
speed
00 (100 MHz) 0 (100 kHz) 1008 99.2 kHz
00 1 (400 kHz) 256 390.6 kHz
01 (75 MHz) 0 (100 kHz) 752 99.7 kHz
01 1 (400 kHz) 192 390.6 kHz
10 (50 MHz) 0 (100 kHz) 512 97.6 kHz
10 1 (400 kHz) 128 390.6 kHz
11 (33 MHz) 0 (100 kHz) 336 98.2 kHz
11 1 (400 kHz) 96 343.8 kHz
Figure 16- 5 . I2C block diag ram
Boot S/M
and Logic
Reset
Logic
I2C Clock
Gen Prog
PAD
I2C
I/F
S/M
Serializer/Deserializer
PAD
n
01
01
PAD
Addr
Register
Data
Register
Boot Addr ess
Boot Data
cpu-arst
TRI_RESET#
controls controls
cpu-arst
IIC_SCL
PAD
BOOTCLKIN
ATE
(eeprom ima ge
Byte0,bit0)
IIC_SDA
controls
I2C low
level S/M controls
boot addr
cpu-arst
boot_sclk
sclk
Boot
Data
IIC_AR reg
IIC_DR reg
I
sclk
.
.4
sync
Data Hiway
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
16-8 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 17-1
Synchronous Serial Interface Chapter 17
1 7.1 S YN CH RO NO US S E RI AL I N TE RF ACE
OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 synchronous serial interface (SSI) unit in-
terfaces to an off-chip modem analog front en d ( MAF E)
subsystem, network terminator, ADC/DAC or codec
through a flexible bit-serial connection. The hardware
performs full-duplex serialization/deserialization of a bit
stream from a ny of the se devices. Any such front end de-
vice connected must support transmitting, receiving of
data, and initialization via a synchronous serial interface.
Since the communication algorithm is implemented in
software by the PNX1300 DSPCPU and the analog inter-
face is off chi p, a wide variety of modem, networ k and/ or
FAX pr otocols may be supported.
Th e S S I hardw a r e inc lu d es :
•A 16-bit receive shift register (RxSR), synchronized
by an external receive frame synchronization pulse
(SSI_RxFSX) and clocked by an external clock
(RxCLK)
•A 32-bit MMIO receive data register (SSI_RxDR) to
prov id e da ta ac c es s fro m the DS P C PU
•32- e n t r y de ep,16 -bi t w id e r ec ei ve buffer ( Rx FIF O) , to
buffer be tween th e receive shift register (RxSR) and
MMIO receive data register (SSI_RxDR)
•A 16-bit transmit shift register (TxSR), synchronized
by an ex ternal or internal transmit fram e synchron iza-
tion pulse and clocked by an external clock (either
SSI_IO1 or SSI_RxCLK )
•A 32-bit MMIO transmit data register (SSI_TxDR) to
transmit data from the DSPCPU.
•30-entry deep, 16-bit wide transmit buffer (TxFIFO),
to buffer between the MMIO transmit data register
(SSI_TxDR) and transmit shift register (TxSR)
•Transmit frame sync pulse generation logic
•Control and stat us logic
•Interrupt generation logic
The SSI unit is not a hiway bus master. All I/O is complet-
ed through DSPCPU MMIO cycles. FIFOs are used to in-
crease allowable interrupt response time and decrease
interrupt rate.
17.2 INTERFACE
The external interface consists of the 6 pins described in
Table 17-1.
17.3 BLOCK DIAGRAM
The main block diagram of the SSI unit is illustrated in
Figure 17-1.
The I/O block is used for control of the I/O pins and for
selectin g the transmi t clock and transmit frame synchro-
ni za tion s ignals .
Th e fram e sy n c hr o ni zation bl oc k can be us ed for ge n er -
at in g a n inter n al s yn chr o niz a t io n sign al de r iv e d fr om re -
ceive clock input (SSI_RxCLK) or from an I/O pin
(SSI_IO1).
The SSI transmit block buffers and transmits the bits us-
ing the generated frame synchronization signal (TxFSX)
and the transmit clock. The transmit clock is either the re-
ce iv e cl oc k or th e clo c k prese nt on SSI_I O 1.
The SSI receive block receives and buffers the bits on
the SSI_RxDATA line, using the receive clock
(S SI_RxC LK) an d the rece ive fra me synch roniz atio n sig-
nal (SSI_Rx FSX).
Each of the blocks will be described in detail in the next
subsections.
Table 17-1. Synchronous serial interface pins
Name Type Description
SSI_RxCLK IN-5 Serial interface clock signal; pro-
vided by an external commun ica-
tio n device.
SSI_RxFSX IN-5 Frame synchronization reference
signal; provided by an external
communi cation device.
SSI_RxDATA IN-5 Receive serial data signal; provided
by the receive channel of an exter-
nal c ommuni cat ion d evice.
SSI_TxDATA OUT Transmit serial data signal output.
SSI_IO1 I/O-5 Transmit clock input or general pur-
pose I/O pin.
SSI_IO2 I/O-5 Transmit Frame synchronization
signal input or output or general
purpose I/O pin.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-2 PRELIMINARY SPECIFICATION
17.3.1 General Purpose I/O
Figure 17-2 illustrates the functionality of the general
purpose I/O pins. The SSI_IO1 and SSI_IO2 external
pins may be used as general purpose I/O by proper con-
fig uration of the S SI_ CTL regi ste r, o r they ma y be used
as t ransmit clock input and as transmit framing signal in-
put or output. The SSI_CTL.IO1 and SSI_CTL.IO2 Mode
Select fields control the direction and functionality of
th es e tw o pi ns .
A hardwa re reset or a softwa re reset of the transmitter
through SSI_CTL.TXR command sets the SSI_CTL.IO1
and SSI_CTL.O2 fields to 11b, a conflic t-free in itial pin
state.Table 17-2 show s th e e f fect of SSI _CT L.I O1 o n pi n
SSI_IO1, Table 17-3 shows the effect of SSI_CTL.IO2
on SSI_IO2. Note: If SSI_IO1 is not selected as transmit
cloc k inpu t, the tr ansmit cloc k is taken from the r ecei ve
clock signal instead . If SSI_I O2 i s not sele ct ed a s tr an s-
mit framing signal input or output, the transmit framing
si gn al is taken from the r ec eive fr amin g si gnal in stead.
SSI_RxCLK
TxFSX
SSI_RxFSX
Frame Synchronization
Block
Figure 17-1. The SSI int erface block diagr am
SSI_IO2
SSI_IO1 I/O Control
Block
SSI Transmit
Block
TxCLK
SSI_TxDATA
SSI Receive
Block
SSI_RxDATA
IO1[1:0]=00
RIO1
WIO1
Figur e 1 7- 2. I/O b lock diagr am
internal TxFSX
2:1
MUX
IO2[1:0] = 00
WIO2 IO2[1:0] = 00
SSI_IO2
RIO2
IO2[0] = 0
IO2[0] = 1
SSI_IO1
IO1[1:0]=01
SSI_RxFSX TxFSX
SSI_IO2
2:1
MUX
IO2[1:0] = 11
2:1
MUX
IO2[1:0] = 10
internal TxFSX IO2[1:0] = 10
IO2[1:0] = 11
TxCLK
2:1
MUX
IO1[1:0]=10
IO1[1:0]=10
SSI_IO1
SSI_RxCLK
Philips Semiconductors Synchronous Serial Interface
PRELIMINARY SPECIFICATION 17-3
17.3.2 Frame Synchronization
The internal f rame synchronization logic is illustr ated in
Figure 17-3. An internal Frame Synchronization signal
(TxFSX) is being generated from the transmit or receive
cl oc k sele c ted by SSI _CTL.IO1. The Clock is divided by
th e w o r d length ( 16) a nd a Frame Rate Divider which is
controlled by the F SS[3:0] bits in the SSI_CTL register .
FMS dete rmines the F ra me Mod e operati on, wh ether the
fra me s y nc p ulse i s w or d - le ngth or bi t-length. T he tran s -
mit framing signal is selected depending on
SSI_CTL.IO2, as shown in Table 17-4.
17.3. 3 SSI Transmit
The transmitter control block diagram is illustrated in
Figure 17-4. Th e transmitter clock can be selected f rom
two sources, i.e. SSI_IO1 or SSI_RxCLK by program-
ming IO1[1:0] bits in the SSI_CTL register (see
Figure 17-2). A tr ansfer tak es pla ce on e ither the risi ng or
falling edge of the clock, which can be configured with
SSI_CTL.TCP.
The transmitter has a 30-entry deep, 16-bit transmit
buffer that buffers the data between the 32-bit
SSI_TXDR register and the 16-bit transmit shift register
(TxSR).
The TxSR is a 16-bi t transmit shift register. I t c an be con-
figured to shift out MSB or LSB first with SSI_CTL.TSD.
A de tai led desc rip tion of the config ura tion of the trans mit-
ter can be found in the SSI_CTL and SSI_CSR register
description (17.10.1 and 17.10.2)
SSI _T x DR is a 32 - bi t MM IO tra ns m it r eg is te r .
17.3. 4 SSI Re ceive
The receiver control block diagram is illustrated in
Figure 17-5. The receiver clock, frame synchronization
and data si gn al ar e alway s tak en fr om th e ex ter na l pin s .
The receive r has a 32-entry deep, 16-bit re ceive bu ffer
that buffers the data between the 16-bit receive shift reg-
ister (RxSR) and the 32-bit SSI_RXDATA register.
The input pin SSI_RxDATA provides serial shift in data
to th e R x SR . The R xSR is a 1 6- b it re ce iv e sh ift reg is t er .
RxSR can be configured to shift in from MSB or LSB first
using SSI_CTL.RSD. A transfer takes place on either the
rising or fa llin g edge of the receiver clock, which can be
configured with the SSI_CTL.RCP.
Table 17-2 Effect of SSI_CTL.IO1 on SSI_IO1
IO1[0:1] Function of SS I_IO1
00 general purpose output with positive logic
pol ar i ty , re fle c tin g the v al ue in
SSI_CTL.WIO1
01 general purpose input, with optional change
detector f unctio n. The input state can be
read from SSI_CSR.RIO1. The change
dete ct or is clo cke d by t he hig hway b us. The
change detector may optionally generate an
interrupt, under the control of CDE bit of
SSI_CTL.
10 Transm it cloc k (TxCLK) input
11 tri-state, input signal value ignored
Table 17-3 Effect of SSI_CTL.IO2 on SSI_IO2
IO2[0:1] Function of SSI_IO2
00 Ge ner al p ur p ose ou tput with po sitiv e lo gic
pol ar i ty , re fle c tin g the v al ue in
SSI_CTL.WIO2
01 General purpose input. The input state can
be read in from SSI_CSR.RIO2. No change
detector is provided for this pin.
10 I nte r na l tr a ns mit f ram ing si gnal (T x FSX ) o ut -
put.
11 Transmit framing signal (TxFSX) input.
SSI_RxCLK
TxCLK
SSI_IO1
Word Length
Divider Frame Rate
Divider Frame Sync
Mode
FSS[3:0] FMS
Figure 17-3. Frame synchronization generation block diagram
internal TxFSX
2:1
MUX
IO1[1:0]=10
IO1[1:0]=10
Table 17-4. Ef fect of SSI_CTL.IO2 on t ransmit
framing signal
IO2[0:1] Sou rce of transmit framing signal
00 taken from RxFSX
01 taken from RxFSX
10 i nter nal ly generated
11 taken from SSI_IO2 pin
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-4 PRELIMINARY SPECIFICATION
A de ta iled de scr ip tion of the co nf i gura t ion of th e rece iv er
can be f ou nd in th e S SI_C T L and S SI_C SR re gi ster de-
scr iption (17.10.1 and 17.10.2)
SSI_RxDR is a 32-bit MMIO receive data register.
Due to the possibility of speculative reading of the
SS I_R xDR , t he read i ts el f can n ot be impl em ent ed t o a c-
know led ge t he d ata as a sid e e ffect. For t his re ason an
explicit acknowledge mechanism is provided by the
SSI_RxACK register.
Th e SS I _R x AC K is a 1 - bi t MMIO re gister that is u sed to
signal the SSI receiver state machine that a word has
been suc ces sfully r ead f rom t he SS I_R xDR .
Writing a ‘1’ to this register initiates updating of the inter-
nal stat e. Writing a ‘0’ ha s n o ef f ec t.
Th e re gis t er cann ot be read , its ef fec t ma y be ob s er v ed
in the WAR field of the SSI_CSR.
The status fields of the SSI_CSR will update within 1
highway clock cycle after writing to the SSI_RXACK reg-
ister.
SSI_TxDATA Transmit
Shift Reg 64-byte Transmit Buffer Transmit
Data Reg
TxCLK Transmit Control Logic
TxFSX
Transmit
Control Reg
Transmit
Status R eg
Figure 17-4. The Sync Ser ial Interface Transmit B lock Diagram
TxSR SSI_TXDR
SSI_RxCLK
SSI_RxFSX
SSI_RxDATA Receive
Shift Reg 64-byte Receive Buffer Receive
Data Reg
Receive Control Logic
Receive
Control Reg
Receive
Status Reg
Figure 17-5. The SSI receive block di agram
RxSR SSI_RXDR
Philips Semiconductors Synchronous Serial Interface
PRELIMINARY SPECIFICATION 17-5
17.4 SSI TRANSMIT OPERATION
17.4.1 Setup SSI_CTL
Write the SSI_CTL to reset and enable the transmitter.
Bo th t h e t r an sm i t te r and rece iver m u st be res et sim ulta-
neo usl y. Thi s w ill set all regi st ers an d int e rnal logi c to be
same as after a power-up reset. The recommended pro-
cedur e i s to s et up all tr a ns m it t er-r ela t e d co ntr ol b it s be -
fore perf orming a TXE assert. In particular, fi elds TCP ,
RSD, IO1, IO2, FMS, FSP, MOD and T MS should NOT
be changed after enabling the transmitter until after the
next t ra nsm itter reset .
The TxCLK is taken from the SSI_IO1 pin or from the re-
ceive clock, dependent on SSI_CTL.IO1. The direction of
shift in the TxSR and the clock edge on which to shift
must also be configured in SSI_CTL. If the DSPCPU
does not poll the SSI status registers, it should enable
the tra ns mitt er int er ru pt and se t the ILS fi el d by wri t ing t o
the SSI_CTL to allow interrupt driven servicing of the
SSI. Note that both transmit and receive use the same
ILS fiel d. Set the framin g con trols, slo t size, and mode re-
quired according to the external communication circuit’s
req ui r em e nt s by wr i tin g the SS I_ C TL . F in al ly , set th e in-
terrupt level to respond to empty levels in the TxFIFO.
No te tha t t he Rx and T x m ach ines sh are t h e fr ami ng an d
clock divide controls. They cannot be set to different val-
ues f o r Rx an d Tx .
If the RxCLK used to derive the TxCLK needs a divide by
two, this is done by setting SSI_CSR.CD2.
17.4.2 Operation Details
Th e trans mit s tat e mac hine wi ll wa it for t rans mit da ta to
be written to the SSI_TxDR register. (see also
Figure 17-6) As soon as SSI_TxDR is written, it’s value
will be propagated through two entries of the TxFIFO
(TxFIFO is 16-bit and SSI_TxDR is 32-bit) and trans-
ferred to TxSR, synchronized to TxFSX. The order of
transferring the two 16-bit parts in the 32-b it SSI_TxDR
can be configured by the endian bit SSI_CTL.EMS. Data
will begin shifting out of TxSR, one bit for each active
edg e of t he Tx CLK, from eit her bit 15 (MSB fir st S SI_C TL
setting) or from bit 0 (LSB first) until TxSR is empty. For
endian control and shift direction see also subsection
17.8. When the shift register is empty, th e transmit state
machine will load the value from the next available
TxFIFO location and begin shifting out that data. The
transmissi on continues u ntil the tran smit state machi ne
is disabled or reset .
If the l ast available TxFIFO has not been updated at the
appropriate time to reload TxSR, the last transmitted
fr ame i s retr ansmit ted a nd a tr ansmi t under run er ror i s in-
dicated in the transmitter status SSI_CSR.TUE
17.4.3 Interrupt and Status
The refill status of the SSI_TxDR register is stored in
SSI_CSR. As the transmit state machine loads a TxFIFO
register to the TxSR, it sets the associated status bits.
The SSI will generate an internal interrupt when the num-
ber of em pty w ords in the TxF IFO ri ses abov e th e lev el
set by SSI_CSR.ILS. If the transmit state machine at-
tempts to read a TxFIFO while the last available TxFIFO
has not been updated, it will set the transmit underrun bit.
This can cause a pr otoco l error in the transmission.
The number of available word buffers (SSI_CSR.WAW)
and tra nsmi tte r dat a r egis ter em pty (SSI _CSR .TD E) in -
formation is updat ed automatically by the SSI block.
... ... ... ... 7 6 5 4 3 2 1 0
TxSR
32-bit MMIO Reg
30-de pth of 16-bit buffer
16-bit
SSI_TxDATA
29 28 27 ...
rd_ptr
From
Hiway
wr_ptr
SSI_TxDR
Figur e 1 7-6 . The tra nsm it bu ffer oper atio n
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-6 PRELIMINARY SPECIFICATION
17.5 SSI RECEIVE OPERATION
17.5.1 Setup SSI_CTL
Wr ite the SS I_CT L to res et an d enab le th e recei ver. B oth
the transmitter and receiver must be reset simultaneous-
ly. This will set all registers and internal logic the same as
after a power-up reset. The recommended procedure is
to se t up all r ec eive r relate d cont ro l bits be fore per f orm-
ing a RXE assert. In particular, fields TCP, RSD, IO1,
IO2, FMS, FSP, MOD and TMS should NOT be changed
aft e r en ab li ng the re ce iv er u nt il a fte r th e n ex t re ce ive r r e-
set.
The direction of s hift in the RxS R, mode , a nd the clock
edge p olarit y must also b e configured in SS I_CTL. Set
th e fr ami ng controls ac cording to the e x ternal communi -
cation circuit’s requirements. Note that the Rx and Tx
mac hine s share th e frami ng an d clo ck divide control s.
If the DSPCPU does not poll the SSI status registers, it
should enable the receiver interrupt and set the ILS field
by writing to the SSI_CTL to allow interrupt driven servic-
ing o f the SS I receiver. Note that both transmit and re-
ceive us e t h e same I L S f iel d.
If the R x C LK is double t he f requency of the data rate on
the SSI bus, SSI_CSR.CD2 can be used to divide the re-
ce iv e cloc k by tw o.
17.5.2 Operation Details
The receive state machine will begin shifting
SSI_RxDATA into the RxSR on the first active edge of
SSI_ RxCLK receiv ed after the receiver is en abled (see
also Figure 17-7). When full, the RxSR is parallel trans-
ferred to the first available RxFIFO entry and possibly
SSI_RxDR. Reception continues and when RxSR is full
again, a parallel load of the next available RxFIFO entry
from RxSR is accomplished. This continues until the re-
ceiv er is disabled or reset. If the receive stat e machi ne
must transfer RxSR int o one of the RxFIFO entries and
non e of the RxFI FO ent rie s is ava ila bl e, the val ue wi ll be
lost and the receive overrun bit will be set.
17.5.3 Interrupt and Status
The status of the RxFIFO is visible in SSI_CSR. WA R is
th e n umb er of 32 -bi t wo rd s a vai lable f or r ead; it is m ore
than ILS (RDF). As the receive state machine loads
RxFIFO from the RxSR, it sets the associated status bit.
The SSI will generate an internal interrupt when the num-
ber of fu ll entr ies in R xFI FO is more the n SSI_CT L.ILS .
If the receive state machine attempts to load RxFIFO
while none of the RxFIFO entries is available, it will set
the receive overrun bit and genera t e a n i nterrupt.
Due to the possibility of speculative reading of the
SSI_RxDR, the DSPCPU must explicitly indicate a suc-
cessful re ad of SSI_RxDR by writing a ‘1’ in the L SB to
the SSI_RxACK register. The status fields of the
SSI_CSR will update within 1 highway clock cycle after
compl eti on of wr iting to SSI_RXACK reg ist er.
17.6 FRAME TIMING
The frame timing can be controlled by the FSS and VSS
fields in the SSI_CTL register.
The FSS[ 3:0] bits cont rol the divide rat io for the progr am-
mable frame rate divider used to generate the frame
sync pulses. The valid value ranges from 1 to 16 slots of
16 bit ea c h, e.g. a value of 5 indicates that a frame con-
tains 5 slots of 16 bits each. Note: the value ‘16’ is ac-
c omplished by st or ing a ‘0’ in this field. If a codec is con-
nected which generates 6 slots and the SSI block is
programmed to 5 slots a framing error is indicated in
SS I_C SR .FE S; an d if TIE or RIE is enab le d, an int e rru pt
is generated.
For an example of a frame timing diagram see
Figure 17-11 and Figure 17-12.
The VSS[3:0] bits control the number of valid slots in the
frame, st arting from slot 1 . For example, if t he VSB[3:0]
bi ts ar e if set t o 4 and FS S s et to 5, slots 1, 2, 3 an d 4 in
the frame contain valid data from the transmitter FIFO
and slot 5 will contain non-valid data. The receiver will
only a cc e pt data in s lot 1, 2 , 3 an d 4.
4 5 6 7 ... ... ... ... ... 29 30 31
RxSR
32-bit MMIO Reg
32-depth of 16-bit buffer
16-bit
SSI_RxDATA
0 1 2 3
rd_ptr wr_ptr
To
Hiway
SSI_RxDR
Figure 17-7. The receive buffer operation
Philips Semiconductors Synchronous Serial Interface
PRELIMINARY SPECIFICATION 17-7
17.7 INTERRUPT GENERATION
Dep ending on the s ett i ngs of the TIE, RI E and C DE bi t s
in th e SSI_ C TL regis te r, the SSI unit ca n genera te in te r-
rupts. This is best illustrated by Figure 17-8. Note:
RX FES and T X FES are t he inter na l rec ei ve an d tr an smit
fr amin g erro r c onditi ons. When an SSI inter rup t is detect-
ed, the interrupt service routine should check all status
bits.The interrupts should be set up as level-triggered in-
terrupts.
17.8 16-BIT ENDIAN-NESS AND SHIFT
DIRECTION
The S SI unit supports both access orders for the 16-bit
halves of a ma c hine w o rd. In add it i on , th e s hi ft direc tion
c an be con trolled t o sele ct MS B or LSB shifting first. The
SSI_CTL.EMS bit controls the 16-bit endian mode, and
the T SD and RSD bits control transmit and receive shift
direction.
When EMS is set, the first data word received in a frame
wil l be tr an s ferre d to bi t 15-0 of the SSI _ R xDR, the se c -
ond word will be transferred to bits 31-16 of the
SSI_RxDR. EMS = ‘0’ rev erses the order of the halves of
SSI_RxDR. Like wise in the transmitter , when EMS is set,
the fi rs t dat a wo r d tr an smi tte d i n a fr ame will be bits 1 5 -0
of SSI_TxDR, the second word transferred will be bits
31-16 of SSI_T xDR.
TSD and RSD control the shift direction of transmit and
receive shift registers (TxSR and RxSR). Transmit data is
transmi tte d M SB first wh e n TSD is ‘0’ or LSB first other-
wise. Receive data is received MSB first when RSD
equals ‘0’, LSB first otherwise.
For an example of the transmit operation see
Figure 17-9. Receive works the same, only that data is
sh ift ed in.
Figur e 17-8 . I nt e rrupt genera tio n logic .
TUE and
or
TDE
TXFES
TIE
ROE and
or
RDF
RIE
or SSI interrupt
CDE & CDS
RXFES
Figure 17-9. 16-bit endian and shift direction operation.
SSI_TXDR31 015
SSI_RXFSX
SSI_TXDATA D16 D15 D14 D13 ....... D2 D1 D0 D31 D30 D29 ....... D18 D17 D16 D15 D14 D13 ......
1st word 3th word
SSI_RXFSX
SSI_TXDATA D31 D0 D1 D2 ....... D13 D14 D15 D16 D17 D18 ....... D29 D30 D31 D0 D1 D2 ......
1st word 3th word
SSI_RXFSX
SSI_TXDATA D0 D31 D30 D29 ....... D18 D17 D16 D15 D14 D13 ....... D2 D1 D0 D31 D30 D29 ......
1st word 3th word
SSI_RXFSX
SSI_TXDATA D15 D16 D17 D18 ....... D29 D30 D31 D0 D1 D2 ....... D13 D14 D15 D16 D17 D18 ......
1st word 3th word
2nd word
2nd word
2nd word
2nd word
EMS = 1, TSD = 0
EMS = 1, TSD = 1
EMS = 0, TSD = 0
EMS = 0, TSD = 1
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-8 PRELIMINARY SPECIFICATION
17.9 SSI TEST MODES
The SSI unit has two test modes which can be controlled
by setting SSI_CSR.TMS. A remote and a local loop
back testmode are supported (see also Table 17-9).
17.9.1 Remote Loopback
This tes t m ode allo ws a remo te transm itter to te st itse lf,
the intervening transmission media, and its associated
receiver. In this mode, the data received on the
SSI_RxDATA pin is buffered and transmitted on the
SSI_TxDATA pin. The data is not transferred to
SSI_TxDR/TxFIFO and the DSPCPU is never interrupt-
ed. The transmitter is clocked by the SSI_RxCLK pin with
a co mb in ator i al c lock d elay .
17.9.2 Local Loopback
This test m ode allo ws t he DSP CP U to r un lo cal che cks
of the SSI. Data written to the TxFIFO is serialized and
pass e d to the rec eive r via a n int erna l ser ial c o nnec tion .
The receiver d eserializes the data and pa sses it t o the
RxFIFO register. Interrupts will be generated if enabled.
During local loop back mode, the data on the
SSI_ R x D ATA pin is i gn or e d an d the SS I_ Tx D AT A pin is
tristated. An external CLK must be provided during lo cal
loop ba ck mo de o r no t ra nsmissi on o r reception will o c-
cur.
17.10 MMIO REGISTERS
The MMIO Control and Status registers are shown in
Figure 17-10. The register fields are described in
Table 17-5, Table 17-6, Table 17-7, Table 17-8, and
Table 17-9. T o ens ure c ompati bilit y wi th futur e devi ces ,
any undefined M MIO bi t s shou ld be ig nor e d w h en read,
an d wr itt en as ‘0’s.
SSI_CTL (r/w)0x10 2C00 31 0
MMIO_BASE
offset:
SSI_TXDR (w/ o)0x10 2C10
SSI_RXDR (r/o)0x10 2C20
SSI_RXACK (w/o)0x10 2C24
371115192327
TXDATA
RXDATA
SSI_CSR (r/w)0x10 2C04 WAW
FMS
FSP
MOD
EMS
TDE
RDF
TUE
RIO1
RIO2
037111519
31 0371115192327
FES
CDS
ROE
TXR
RXR
TXE
TSD
RSD
TCP
RCP
RXE
IO1 IO2
WIO1
WIO2TIE
RIE
FSS VSS ILS
WAR
31 2327
CTUE
SROE
CFES
CCDS
TMS
CDE
CD2
SLP
reset: 0x00f00000
reset: 0x0000f000
RX_ACK
Fig u re 17- 10 . SS I MM IO regi ste rs.
Philips Semiconductors Synchronous Serial Interface
PRELIMINARY SPECIFICATION 17-9
17.10.1 SSI Control Register (SSI_CTL)
SSI_CTL is a 32-bit read/write control register used to direct the operation of the SSI. The value of this register after a
har dw are r e set i s 0x 00 F 0 0000.
Table 17-5. SSI control register (SSI_CTL) fields.
Field Description
TXR Transm itter Software Rese t (Bit 31). Setting TXR performs the same func tion s as a hardware reset. Resets all
transmitter functions. A transmission in progress is interrupted and the data remaining in the TxSR is lost. The
TxFIFO pointers are reset and the data contained will not be transmitted, but the data in the SSI_TxDR and/or
TxFIFO are not explicitly deleted. The transmitter status and interrupts are all cleared. This is an action bit. This bit
always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the RXR field will initiate a reset for the SSI module.
Note: this bit is always set together with RXR because a separate transmitter or receiver reset is not implemented.
RXR Receiver Software Reset (Bit 30). Setting RXR performs the same functions as a hardware reset. Resets all
receiver functions. A reception in progress is interrupted and the data collected in the RxSR is lost. The RxFIFO
pointers are reset, and the SSI will not generate an interrupt to DSPCPU to retrieve data in the SSI_RxDR and/or
RxFIFO . The data in the SSI_RxDR and/or RxFIFO is not explicitly deleted. The receiver status and interrupts are
all clea r e d .This is an action bit .Thi s bit al ways reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the TXR field
will initiate a reset for the SSI module. Note: this bit is alwa ys set together with TXR, because a separate transmitter
or receiver reset is not implemented.
TXE Transmitter Enable (Bit 29). TXE enables the operation of the transmit shift register state machine. When TXE is set
and a frame sync is detected, the transmit state machine of the SSI is begins transmission of the frame. When TXE
is cleared, the transmitter will be disabled after completing transmission of data cur ren tly in the TxS R. The serial out-
put (SSI_TxDATA) is three-stated, and any data present in SSI_TxDR and/or TxF I FO will no t be transmitt e d (i.e., data
can be written to SSI_TxDR with TXE cleared; TDE can be cleared, but data will not be transf erred to the TxSR).
Status fields updated by the Transmit state machine are not updated or reset when an active transmitter is disabled.
RXE Receive Enable (Bit 28). When RXE is set, t he receive state machine of the SSI is enabled. When this bit is cleared,
the receiver will be disabled by inhibiting data transfer into SSI_RxDR and/or RxFIFO. If data is being received while
this bit is cleared, the remainder of that 16-bit word will be shifted in and transferred to the SSI RxFIFO and/or
SSI_RxDR.
Status fields updated by the Receive state machine are not updated or reset when an act ive receiver is disabled.
TCP Transm it Clock Polari ty (Bi t 27). The TCP bit value should onl y be chang ed when the trans mitte r is disabled . TCP
contr ols on whi ch edge of TxCLK data i s output. TCP=0 c auses da ta to be outp ut at risin g edge of Tx CLK, TCP=1
causes data to be output at falling edge of TxCLK.
RCP Receiv e Clock P olarity (Bit 26). RCP controls which edge of RxCLK samples data. The data is sampled at rising edge
when RCP = ‘1’ or fallin g edge when RCP = ‘0’.
TSD Transm it Shift Direc tion (Bit 25). TSD c ontrols the shift direc tion of transmi t shift regis ter (TxSR). Tr ansmit data is
trans mitt ed MS B first when TSD = ‘0’ o r L SB firs t ot he rwis e. Th e ope ratio n o f th is bit is explained in more detail in
section 17.8.
RSD Receiv e Shift Direction (Bit 24). The RSD bit value should only be changed when the receiver is disabled. RSD con-
trols the shift direction of receive shift register (RxSR). Receive data is received MSB first when RSD = ‘0’, LSB first
otherwise. The operation of this bit i s explained in more detail in section 17.8.
IO1 Mode Select SSI_IO1 pin (Bit 23-22). The IO1 field value should only be changed when the transmitter and receiver
are disabled. The IO1[1:0] bits are used to select the function of SSI_IO1 pin. The functi on may be selected as listed
in table Table 17-6.
IO2 Mode Select SSI_IO2 pin (Bit 21-20). The IO2 field value should only be changed when the transmitter and receiver
are disabled. The IO2[1:0] bits are used to select the function of SSI_IO2 pin. The funct ion may be selected according
to Table 17-7
WIO1 Write IO1 (Bit 19). Value written here appears on the SSI_IO1 pin when the pin is configured to be a general purpose
output.
WIO2 Write IO2 (Bit 18). Value written here appears on the SSI_IO2 pin when this pin is configured to be a general purpose
output.
TIE Transmit Interrupt Enable (Bit 17). Enables interrupt by the TDE flag in the SSI status register (transmit needs refill)
Also en ables interrupt of the TUE (transmitter underrun error) and TXFES (transmit framing error)
RIE Receive Interrupt Enable (Bit 16). When RIE is set, the DSPCPU will b e in terrupted when RDF in the SSI status reg-
ister is set (receive complete). It will also be interrupted on ROE (receiver ov errun error) and on RXFES (receive fram-
ing error).
FSS Frame Size Sel ect (Bits 15-12 ). The FS S[3 :0] bits control the divide ratio for the p rogrammable frame ra te divider
used to generate the frame sync pulses. The valid setup value ranges from 1 to 16 slot(s). The value ‘16’ is accom-
plished by storing a 0 in this field.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-10 PRELIMINARY SPECIFICATION
VSS V alid Slot Size (Bit 11-8). The VSS[3:0] bits control the valid slot size (starting from slot 1 ) f or diff erent modem analog
fro nt end devic e s. The valid setup value ranges from 1 to 16 slot(s). The value 16 is accomplished by storing a ‘0’ in
this field.
FMS Frame S ync Mode S ele ct (Bit 7). The FMS bi t va lue shoul d onl y be changed when the tra nsmitter and rec eiver are
disabled. FMS selects the type of frame sync to be recognized by both Rx and T x . When FMS = ‘1’, frame sync is
word-length bit clock. When this bit = ‘0’, frame sync is a 1-bit clock.
FSP Frame S ync Polari ty (Bit 6). The FSP bit value s hould only be chan ged when the tra nsm itter and receiver are dis-
abled. FSP controls which edge of frame sync is the active edge for both Rx and Tx. This bit causes frame signal to
be a ct ive at risi ng edge when FSP = ‘0’ , or falling edge when FSP = ‘1’.
MOD Mode Select (Bit 5). The MOD bit value should only be changed when the transmitter and receiv er are disabled. MOD
sele cts the operational mode of the SSI f or ISDN functi onality. Whe n MOD is set, the SSI is conf igure d as a U-inter -
face for ISDN NT. Oth erwise, set to ‘0’. Setting MOD bit and CD2 supports the MC145574 and MC145572 ISDN in-
terface transceivers.
EMS Endian Mode Select (Bit 4). Selects the big- or little-endian mode operation. See Section 17.8 for more detail.
ILS Interrupt Le vel Select (Bit 3-0). Sets the point where an interrupt is generated for normal data buffer servicing. The
number ranges from 1 to 15. This field controls interrupt level of both transmit and receive functions.
Table 17-5. SSI control register (SSI_CTL) fields.
Field Description
Tab l e 17 -6. IO 1 mo de se l e ct
Bit Mode
00 General Purpose Output: Configures the SSI_IO1 pin for general purpose output. The pin follows the state of the WIO1
field of the SSI_CTL.
01 General Purpose Input: Change detector may be used. Value can be read in from the RIO1 field of the SSI_CSR.
10 Enable External TxCLK: Allo ws for use of an externally generated TxCLK. Th e clock is provided via the TxCLK pin. All
general purpos e I/O func tions are unavailable.
11 Disable: Pin is not used. Output buffer is tristated and the input is ignored. (RESET def ault)
Tab l e 17 -7. IO 2 mo de se l e ct
Bit Mode
00 General Purpose Output: Configures the SSI_IO2 pin as a general purpose output. The pin follows the state of the WIO2
field of the SSI_CTL.
01 General Purpose Input: Value can be read in from RIO2 field of the SSI_CSR.
10 Fram e Signal Tx FSX (Output): Outputs the frame signal generated by the internal frame signal generation logic.
11 Fram e Signal Tx FSX (Input): Allows for use of an exte r nally generate d TxFSX. The frame sync signal is provided via
TxFSX pin. All general purpose I/O functions are unavailable. (RESET default)
Philips Semiconductors Synchronous Serial Interface
PRELIMINARY SPECIFICATION 17-11
17.10.2 SSI Control/Status Regist er (SSI_CSR)
SSI_CSR is a 32-bit read/write register that controls the SSI unit and shows the current status of the SSI module. The
default value after hardware reset is 0x0000F000.
Table 17-8. SSI control/status register (SSI_CSR) fields
Field Description
TMS Test Mode Select (Bit 31-30). Value should only be changed when the transmitter and receiver are disabled. See
Table 17-9.
CDE Cha nge Detector Enable (Bi t 29). CDE enable s the change de tect or function on the SS I_IO 1 pin. When CD E i s set,
the D SPCPU will be in terrupted when CDS in th e SSI status regi ster is set. W hen CDE is cl eared, this int errupt i s
disabled. However, the CDS bit will always indicate the change detector condition.
When the change detector is enabled, the CLK samples SSI_IO1. The CDS bit will be se t for either a ‘0’ –> ‘1’ or a ‘1’
–> ‘0’ change between the current value and the stored v alue.
CD2 RXCLK Divider (Bit 28). When CD2 = ‘1’, the internal RxCLK is divided by two. In the divide by 2 mode, the clock edge
that samples the asserted Frame Sync Pulse will resync the RxCLK divider to be a data capture edge. Data samples
will occur ever y other clock thereafte r u ntil the end of the valid slots in the frame.
SLP Sleeples s ( Bit 27) . When s et, t his bi t al lows the SS I to ignore the global power down signal. If cleared, assertion of
the global power down signal will cause the SSI transmitter to finish transmission of the current 16-bit word, then enter
a state simi lar to transmit ter dis abled, (SSI_CTL. TX E = ’0’).
In the receiver, a 16-bit word currently being tran smitted to RxSR will compl ete reception and be transferred to the
RxFIFO . The receiver will then enter a state similar to receiver disabled, (SSI_CTL.RXE = ‘0’).
CTUE Clear T r ansmitter Underrun Error (Bit 21). A control bit written by the DSPCPU to indicate that the transmitter underrun
error flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.TUE. The bit always reads ‘0’.
CROE Clear Receiver Overr un E rror (B it 20 ). A control bit w ritten by the DSPCPU to indicate t hat the receiver overrun error
flag should be cleared. This i s an action bit. Writing a ‘1’ clears SSI_CSR.TOE. The bit always reads ‘0’.
CFES Clear Framing Er ror St atus (Bit 19). A c ontrol bit wri tten by th e DSP CPU to indicate th at the receiver’s framing error
flag should be cleared. This i s an action bit. Writing a ‘1’ clears SSI_CSR.FES. The bit always reads ‘0’.
CCDS Clear Change Detector Status (Bit 18). A control bit written by the DSPCPU to indicate that the change detector status
on IO1 flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.CDS. The bit always reads ‘0’.
WAW Word b uffers Avail able for Write (Bit 15-12). The WAW[ 3:0] bits provide the number of 32-bit words available for write
in the tr ansmit buffer (TxFIF O). T he SSI can stor e 15 words in the tra nsmit FIFO. W hen the FIFO is empty, WAW =
‘15’. Wh en the FIFO is f ull, WAW = ‘0’ and the S SI wil l ignor e a ny furt her attem pts to ad d wor ds to the F IFO. Note:
The fill routine should check that WAW is nonzero, before writing data.
WAR Word buf fers Available for Read (Bit 11-8). The WAR[3:0] bits provide the number of 32-bit word a vailable for read in
the receive buffer (RxFIFO). The SSI can store 16 words in the receive FIFO. However, the maximum value indicated
by the WAR regi ster = ‘15’ (because it’s a 4-bit register field). When the FIFO is empty, WAR = ‘0’. W hen the FIFO is
fu ll, WA R = ‘15’ and the SSI will generate an overrun error if more data is received.
TDE Transmit Data register Empty (Bit 7). In normal operation, this bit will b e se t when the number of empty words in the
TxFIFO is greater than the Interrupt Lev e l Select value, SSI_CTL.ILS. If SSI_CTL.TIE is set, the SSI will generate an
interrupt. When set, it in dicates that the SSI_TxDR/TxFIFO regi sters require DSPCPU service for refilling after normal
transmission. As the DSPCPU refills the TxFIFO during the interrupt service routine, this bit will be cleared by the SSI
whe n the number of e mpty slots dr ops below the value of SSI_CTL.IL S.
RDF Recei ve Data regist er Full (Bit 6). In normal operatio n , this b it will be se t when the num ber of words i n the Rx FI FO is
greater than S SI_CTL.I LS. If SSI_CTL.RIE is set, th e SS I w ill generat e an int errupt. When set, this bit indicates that
normal received data resides in SSI_RxDR register and RxFIFO buff er for reading. DSPCPU must service the RxFIFO
before a receiver overrun occurs.
TUE Transmitter Underrun Error (Bit 5). No current data was ava ilable from the TxFIFO when a load of the TxSR was
scheduled. The transmitted message may have been corrupted. Generates interrupt if enabled by TIE.
ROE Receive Overrun Error (Bit 4). No RxFIFO slot in which to store received data. These bits have been lost and the mes-
sage stream is incomplete. Generates an interrupt if enabled by RIE.
FES Frame Error (Bi t 3). A frame s ync p ulse has been detected w h ere not expec ted or di d not occur as expected duri ng
transmit or receive. Received data may be invalid. Transmit data have been sent out of sync. Receive frame error
RXFES generates an interrupt if enabled by RIE. Transmit frame error TXFES generates an interrupt if enabled by TIE
CDS Change Detector Status (Bit 2). The input change detector on SSI_IO1 pin has detected a change in state.
RIO1 Read IO1 (bit 1). RIO1 reflects the value on the SSI_IO1 pin.
RIO2 Read IO2 (bit 2). RIO2 reflects the value on the SSI_IO2 pin.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
17-12 PRELIMINARY SPECIFICATION
17.11 TIMING DIAGRAMS
Figure 17-11 and Figure 17-12 illustrate the timing of the
dat a sign als an d the frame timin g.
17.12 POWER DOWN
SSI block can be separate ly powered down by se tting a
bit in the BLOCK_POWER_DOWN register. For a de-
scription of powerdown, see Chapter 21, “Power Man-
agement.” Th e SSI bloc k sh ou ld no t be act iv e w h en ap -
pl yi ng b loc k po w e rdo wn.
If th e bloc k ent ers po wer -do wn st ate w hile tra ns mis sion
is enabled, behavior upon power-up is undefined.
Ta ble 17-9. Test mode select
Bit Mode
0X Normal Operation.
10 Remote Loopback Test: Direct connection of receiver serial data to transmitter serial data. Transmitter is
clocked with RxCLK. No data loaded to the SSI_RxDR register or RxFIFO buffer and no CPU interrupt is gener-
ated. Useful to allow remote device to test the communication medium and the Rx and Tx front ends.
11 Local Loopbac k Test: Feed back is after S SI_TxDR and SSI_ RxDR regi ster a nd ser i ali zer/des er ia li zer. Allows
DSPCPU to test the bulk of the Rx and Tx circuits. During Local Loopback Test, an e xternal clock on
SSI_RXCLK should be present to clock the SSI unit.
Figure 17-11. SSI Serial timing. (FSP = 0, RSD = 0, TSD = 0, TCP = 0, RCP = 0, FMS = 0)
SSI_RXCLK
SSI_RXFSX
SSI_RXDATA
SSI_TXDATA
D0 D15 D14 D13 D12
D0 D15 D14 D13 D12
D11 D10 D9 D8
D11 D10 D9 D8
D7 D6 D5 D4
D7 D6 D5 D4
D3 D2 D1 D0
D3 D2 D1 D0
D15 D14 D13 D12
D15 D14 D13 D12
Figure 17-12. SSI Serial timing. (FSP = 0, RSD = 0, TSD = 0, TCP = 0, RCP = 0, FMS = 0, FSS = 5, VSS = 4)
SSI_RXCLK
SSI_RXFSX
SSI_RXDATA
SSI_TXDATA
1st DATA
1st DATA
1st Frame
2nd DATA
2nd DATA
3th DAT A
3th DATA
4th DATA
4th DAT A
1st DATA
1st DATA
2nd Frame
PRELIMINARY SPECIFICATION 18-1
JTAG Functional Specification C hapter 18
by Ren ga Sundararajan, Hans B ouwmee ster and Frank Bouwm an
18.1 OVERVIEW
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The IEEE 1149. 1 (JTAG) standard can be used for vari-
ous p urp oses incl ud ing te stin g co nne ction s betw ee n in-
te gra t ed c ir cu it s on bo ar d lev e l, cont r olling the tes t i ng of
the int ernal struct ures o f th e integ rated cir cuits, and mo n-
ito rin g and com mu nica ting w it h a runn ing sy stem .
The JTAG standard defines on-chip test logic, four or five
dedicated pins collectively called the Test Access Port
(TAP) and a TAP controller.
The JTAG standard defines instructions that must al-
ways be implemented by a TAP controller in order to
guarantee correct behavior on board level. Apart from
mandatory instructions, the standard also allows user-
defined and private instructions. In PNX1300, user de-
fined and private instructions exist for debug purposes
and f or p rod ucti on t est. For de bug t he re is co mmu ni ca-
tion between a debug monitor running on the PNX1300
DSPCPU and a debugger front-end running on a host
computer. This will be explained in chapter Section 18.3
18.2 TEST ACCESS PORT (TAP)
The Test Access Port includes three or four dedicated in-
put pins and one output pin:
•TCK (Test Clock)
•TMS (Test Mode Select)
•TDI (Test Data In)
•TRST (Test Reset, optional!)
•TDO (Test Data Out)
TRST is not present on PNX1300.
TC K pr ovid es th e cloc k for t est log ic requ ired by th e stan-
da rd. TCK is a syn chr ono us to the sys tem c loc k. S tor ed
state devices in JTAG controller must retain their state
indefi nitely when TCK is st opped at 0 or 1.
Th e sign al r e ceiv ed at TM S i s de coded by the T AP con -
troller to control test functions. The test logic is required
to sa m pl e TM S at th e ris in g edge of T CK.
Serial test instructions and test data are received at TDI.
The TDI signal is required to be sampled at the rising
edge of TCK. When test data is shifted from TDI to TDO,
the data must appear without inversion at TDO after a
numb er of ris in g an d fal li ng edges of TCK det e rmin ed by
the len gth of the instr uction or tes t data register selected.
TDO is the serial output for test instructions and data
from the TAP controller. Changes in the state of TDO
must occur at the falling edge of TCK. This is because
devic es conne cted to TD O are required t o sa mple T D O
at the rising edge of TCK. The TDO driver must be in an
inactive state (i.e., TDO line HIghZ) except when data
scanning i s in pro gress.
18.2.1 TAP Controller
The T AP controller is a finite state machine; it synchro-
nously responds to changes in TCK and TMS signals.
Th e TAP in struc tio ns and data a r e serially scan ned into
the TAP controller’s inst ru ctio n a nd data reg iste rs vi a t h e
common input line TDI. The TMS signal tells the TAP
controller to select either the T AP instruction register or
a TAP data register as the destination for serial input
from the common line TDI. An instruction scanned into
the instruction register selects a data register to be con-
nected between TDI and TDO and hence to be the des-
tination for serial data input.
TA P cont ro ller st ate changes are de termin ed by t he TMS
sign al. The states are used for sca nning in/out TAP in -
struction and data, updating instruction and data regis-
ters, and for executin g instructions.
Th e co ntr oller st ate dia gra m (Figure 18-1) show s sepa-
ra te stat es fo r ‘capture’, ‘shift’ and ‘update’ of da ta an d in-
s tr uctions. The reas on for sep ar ate states is to leav e the
contents of a data register or an instruction register un-
disturbed until serial scan-in is finished and the update
state is entered. By separating the shift and update
states, the contents of a register (the parallel stage) is not
affected during scan in/out.
The TAP controller must be in Test Logic Reset state af-
te r pow er-u p. It rema ins i n th at sta te as long as TM S is
held at ‘1’. It transitions to Run-Test/Idle state when TMS
= ‘0’. Th e Run- T es t/ I dle s tate i s a n idle s tate of the con -
tr oll er in be tween sca nnin g in/out an in struc tio n/da ta reg-
ister. T he ‘Run-Test’ part of the name refers to start of
built-in tests. The “Idle” part of the name refers to all other
cas es. Not e that ther e are two similar sub-struc tures in
the state diagram, one for scannin g in an instruction and
another for scanning in data. To scan in/out a data regis-
ter, one has to scan in an instruction first.
An instruction or data register must have at least two
stages , a shift regis ter stag e and a parallel input/output
stage. When an n-bit data register is to be ‘read’, the reg-
is ter is sele cted by an ins tru ct io n. Th e regi st ers cont e nts
are ‘captured’ first (loaded in parallel into shift register
stage), n bits are shifted in and at the same time n bits
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
18-2 PRELIMINARY SPECIFICATION
are shifted out. Finally the register is ‘updated’ with the
new n bits shifted in.
Note: when a register is scanned, its old value is shif ted
out of TDO. The new value shifted in via TDI is written to
the register at the update state. Hence, scan in/out in-
volve the same steps. This also means that reading a
register via JTAG destroys its contents unl ess otherwise
stated. We can specify some registers as read-only via
JTAG so that when the controller transitions to update
state for the r ead-only register, the update has no effect.
Sometimes, read-write registers are needed (for exam-
pl e, cont rol r egi ster s used for ha nds hake ) w hic h ca n be
read non-destructively. In such cases, the value shifted
in determines whether the old value is ‘remembered’ or
somethin g else happen s.
18.2.2 PNX1300 JTAG Instruction Set
PNX 130 0 us es a 5-bit ins truct ion r egi ster . The un spe ci-
fied opcodes are private and their effects are undefined.
Table 18-1 lists the JTAG instructions.
0
0
1
0
1
1
0
0
1
1
Select
DR Scan
Capture
DR
Shift
DR
Exit1
DR
Pause
DR
Exit2
DR
Update
DR
0
0
1
0
1
1
0
0
1
1
Select
IR Scan
Capture
IR
Shift
IR
Exit1
IR
Pause
IR
Exit2
IR
Update
IR
1 1
0
1
01
Test Logic
Reset
Run-Test/
Idle
11
0 0
Figure 18-1. State diagram of TAP controller
00
Table 18-1. J TAG instruction encoding
Encoding Instruction name Action
00000 EXTEST Select (dummy) boundary
scan register
00001 SAMPLE/PRELOAD Select (dummy) boundary
scan register
11111 BYPASS Select bypass register
10000 RESET Reset TriMedia to power on
state
10001 SEL_DATA_IN Select DATA_IN register
Philips Semiconductors JTAG Func ti onal Specification
PRELIMINARY SPECIFICATION 18-3
The JTAG instructions EXTEST, SAMPLE/PRELOAD,
and BY PASS are stand ard instru ctions and ar e n ot dis -
c ussed here. Th e MACRO , BURNIN, an d PASS_C _S in-
structions are used during hardware test mode, and are
also not discussed here. All other instructions are dis-
cu s se d i n Section 18.3
18.3 USING JTAG FOR PNX1300 DEBUG
Figure 18-2 shows a n o ver vi ew of the JTA G acce ss path
from a host machine to a t arget TriMedia system and a
si m plified bl ock diagr am of t he Tr iMe dia pr o ces sor . T he
JTAG Interface Module shown separately in the diagram
may be a PC add-on card such as PC-1149.1/100F
Boundary Scan Controller Board from Corelis Inc. or a
similar module connected to a PC serial or parallel port.
Th e JTA G in ter f ac e mo dule is n ec es s ar y only for TriMe-
dia systems that are not plugged into a PC. For PC-host-
ed Tr iMedia sys tems, the host base d debu gger fr ont- end
c an communicate w ith the target resident debug monitor
via the PCI bus.
The enha nce me nts t o t he standa r d fun ct i on alit y o f J TAG
te st log ic pr ovide s a handshake mechanism for transfer-
ring data to and from a TriMedia processor’s MMIO reg-
isters r eserve d for this purpose, fo r posting an int errupt ,
and f or r es etting pr ocess or s tate. The a ctua l inte rpre ta-
tion of th e c onten ts of t h e MMIO reg is te rs is dete rm in e d
by a software protocol used by the debug monitor run-
ning on the Tr iM edia p ro ces sor and t he debug front -end
running on a host machine.
Th e co mm u nic a tion be t ween a hos t co mp ut er and a ta r-
get TriMe di a s ystem vi a JTA G req ui res, at a high le vel of
abstraction, th e following components.
•A host computer with a serial or parallel inter-
face.
The host computer transfers data to and from the
JTAG interface module, preferably in word-parallel
fashion. A JTAG interface device driver is also
needed to access and modify the registers of the
JTAG interface module.
•A JTAG interface module (hardware) that asyn-
chronously transfers data to and from the host
computer.
Th e inter face module sync hr on ous ly t ra ns fe rs data to
and from the JTAG TAP on a TriMedia processor, and
supplies the te st clock, TCK, and other signals to the
10010 SEL_DATA_OUT Select DATA_OUT register
10011 SEL_IFULL_IN Select IFULL_IN register
10100 SEL_OFULL_OUT Select OFULL_OUT regis-
ter
10101 SEL_JTAG_CTRL Select JTAG_CTRL regis-
ter
11110 MACRO Hardware test mode select
01010 BURNIN Private
01110 PASS_C_S Private
Table 18-1. JTAG instruction encoding
Encoding Instruction name Action
Host Machine JTAG Interface
JTAG board
Connector
Ser ia l or Parall el
Connection
JTAG TAP (TCK, TMS, TDI, TDO)
Main
Memory
(SDRAM)
DSP
CPU MMI
I$
D$
JTAG
controller MMIO
Sc an C hai n conn ecting pos sibly
other chips on board
Tr iM e dia B o ard
Figure 18-2. TriMedia system with JTAG test access
DATA Highway
Module
(such as a PC)
May be a PC p lug-in boar d
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
18-4 PRELIMINARY SPECIFICATION
TriMedia JTAG controller. The interface module may
be a PC pl ug -in board .
This module may transfer data from and to the host
computer in bit-serial or word-parallel fashion. It
transfers data from and to the JTAG registers on a
TriMedia processor in bi t-serial fas hion in accordance
with the IEEE 1149.1 standard. The JTAG interface
module connects to a 4-pin JTAG connector on a Tri-
Med ia b oard w hic h provid es a pa th to t he JTAG pi ns
on a TriMedia processor. It is the responsibility of the
interface module to scan data in and out of the TriMe-
dia processor into its internal buffers and make them
ava ilable to the host com put e r.
•A JTAG controller on the TriMedia processor
which provides a bridge between the external
JTAG TAP and the internal system.
The c ontro ller transfe rs data from /to th e TA P to /from
its scannable registers asynchronous to the internal
system clock. A monitor running on a TriMedia pro-
cesso r and the debugge r fr ont -end running o n a hos t
computer exch ange da t a via J TAG by r ea ding/w riti ng
th e MM IO re gi ster s r es erve d for this pu rpos e, includ-
ing a cont rol register used for the handshake.
18.3.1 JTAG Instruction and Data Regi sters.
PNX1300 has two JTAG data registers and one JTAG
control reg ister (see Figure 18-3) in M MI O sp ace and a
number a JTAG instructions to manipulate those regis-
ters. Table 18-2 lists the MMIO addresses of the JTAG
data and control registers. The addresses are offsets
from MMIO_BASE. All references to instruction and data
re gi ster s belo w ar e JTAG inst r uc tions an d data reg is te rs
and not T riMedia instruction or data registers.
•Two 32-bit data registers, JTAG_DATA_IN and
JTAG_DATA_OUT in MMIO space. Both registers
can be conn ected in between TDI and TDO like the
standard Bypass and Boundary Scan registers of
JTAG (not shown in Figure 18-3).
The JTAG _DATA_ IN regist er can be read or written to
via the JTAG port. The JTAG_DATA_OUT register is
read-only via the JTAG port, so that scanning out
J TAG_DATA_OUT is no n-destr uctiv e.
The JTAG_DATA_IN and JTAG_DATA _OUT are read-
able/writable from the TriMedia processor via the
usual load/store operations.
•An 8-bit control register JTAG_CTRL in MMIO
space. The JTAG_CTRL register is used for hand-
sha ke be tween a d ebug moni tor r unn ing on a Tr iM e-
dia and a debugger front-end running on a host.
JTAG_CTRL.ofull = ‘1’ means that JTAG_DATA_OUT
has vali d d ata to b e s c anne d out. On pow er-on r es e t
of the TriMedia processor, JTAG_CTRL.ofull = ‘0’.
JTAG_CTRL.ofull is both readable and writable via
J TAG ta p. Writi ng 0 t o JTAG _C TRL .oful l via JTA G is a
‘remember’ operation, i.e., JTAG_CTRL.ofull retains
its previous state. Writing a ‘1’ to JTAG_CTRL.ofull
vi a JTAG is a ‘clear’ operation, i.e., JTAG_CTRL.ofull
becomes ‘0’.
J TAG_CTR L.ifull = ‘0’ means that the JTA G_DATA_IN
register is empty. JTAG_CTRL.ifull = 1 means that
JTAG_DATA_IN has valid data and the debug monitor
has not yet copied it to its private area. On power-on
reset of the TriMedia proc essor, JTAG _CTR L.ifull = 0.
JTAG_CTRL.ifull is readable and writable via JTAG.
Writing a ‘0’ to JTAG_CTRL.ifull via JTAG is a
remember operation, i.e., JTAG_CTRL.ifull retains it
previous state. Writ ing a ‘1’ to JTAG_CTRL.ifull posts
an inter rup t on hardw are line 18 .
The peripheral blocks on a TriMedia processor may
enter a ‘power down’ state to reduce power con-
sumption. The JTAG_CTRL.sleepless bit determines
if th e JTAG blo ck pa r tic ipate s in a pow er d own stat e.
In the power-on RESET state, JTA G_CTRL.sleepless
bit is ‘1’ meaning the JTAG block does not power
down. It can be read and written to by the TriMedia
processor via load/store operations and by the
debugger fron t -end r u nn in g on a ho st by sc an in/out.
•Two virtual registers, JTAG_IFULL_IN and
JTAG_OFULL_OUT. The first virtual register
JTAG_IFULL_IN connects the registers
Table 18-2. MMIO Register Assignments
MMIO Offset JTAG R egi st er
0x 10 3800 JTAG_ DATA _IN
0x 10 3804 JTAG_DATA_OUT
0x 10 3808 JTAG_CTR L
To
TDO
JTAG_DATA_IN
JTAG_DATA_OUT
JTAG_CTRL
from
TDI
0
1
ifull ofull
unused bits
7
0
31
31 0
Figure 18-3. Additional JTAG data registers and control register
2
sleepless
bit
3
Philips Semiconductors JTAG Func ti onal Specification
PRELIMINARY SPECIFICATION 18-5
JTAG_CTRL.ifull and JTAG_DATA_IN in series. Like-
wise, the virtual register JTAG_OFULL_OUT con-
nects JTAG_CTRL.ofull and JTAG_DATA_OUT in
series.
The reason fo r the vir tual registers is to shor ten the
time for scanning the JTAG_DATA_IN and
J TAG_DATA_OU T registers. Without virtual registers,
we must scan in an instruction to select
JTAG_DATA_IN, scan in data, scan an instruction to
select JTAG_CTRL register and finally scan in the
control register. With vir tual register, we can scan in
an instruction to select JTAG_IFULL_IN and then
scan in both control and data bits. Similar savings
can be achieved for scan out using virtual registers.
•Five JTAG instructions
•5 instructions, SEL_DATA_IN, SEL_DATA_OUT,
SEL_IFULL_IN, SEL_OFULL_OUT, and
SEL_JTAG_CTRL, f or selecting the registers to be
connected between TDI and T DO for ser ial input/
output.
•An instruction RESET for resetting the TriMedia
processor to power on state.
•In the capture-IR state of the TAP controller, the least
2 significant bits (bits 0 and 1) of the shift register
st age mus t be load ed wi th the ‘01’ as required in the
standard. The standard allows the remaining bits of
the IR shift stage to be loaded with design specific
data. The bits 2, 3 and 4 of the IR shift stage are
loaded w i th bits 0, 1 and 2 of the JTAG_C TR L r eg is-
ter. This m ean s tha t shift ing in any in stru ct ion al lows
th e 3 least s igni f ic an t bits of the J TAG_CT R L reg is te r
to be inspected. This reduces the polling overhead
for data transfer.
Race Condi tions
Since the JTAG data registers live in MMIO space and
are accessible by both the TriMedia processor and the
JTAG controller at the same time, race conditions must
not exist either in hardware or in software. The following
communication protocol uses a handshake mechanism
to avoid software race conditions.
18.3.2 JTAG Communication Protocol
The following describes the handshake mechanism for
trans fe rr ing da ta via JTA G .
•Transfer from debug front-end to debug monitor
The debugger front-end running on a host transfers
dat a to a debug mon ito r via JTAG_DATA _IN reg ister.
It must poll JTAG_CTRL.ifull bit to check if
JTAG_DATA_IN register can be written to. If the
JTAG_CTRL.ifull bit is clear, the front-end may scan
data into JTAG_DATA_IFULL_IN register. Note that
data and control bits may be shifted in with
SEL_IFULL_IN instruction and the bit shifted into
J TAG_CTRL.i full register must be ‘1’. This action trig-
gers an i nterr upt. The debug moni tor mu st copy the
data from JTAG_DATA_IN register into its private
area when servicing the interrupt and then clear
JTAG_CTRL.ifull bit thus allowing JTAG interface
module to write to JTAG_DATA_IN register the next
piece of data.
•Tra nsfer f rom mo nit or t o fr ont -end
The monitor running on TriMedia must check if
JTAG_CTRL.ofull is clear and if so, it can write data
to J TAG_DATA_OU T. Af ter th at , t he m oni tor mu s t se t
the JTAG_CTRL.ofull bit. The debugger front-end
poll s the JTAG_CTR L.ofu ll bit. Wh en that bit is se t, it
can scan out JTAG_DATA_OUT register and clear
JTAG_CTRL.ofull bit. Since JTAG_DATA_OUT is
read-only via JTAG, the update action at the end of
scan out has no effect on JTAG_DATA_OUT. The
JTAG_CTRL.ofull bit, however, must be cleared by
shif ting in th e value ‘1’.
•Controller States
In the power-on reset state, JTAG_CTRL.ifull and
JTAG_CTRL.ofull must be cleared by the JTAG con-
troller.
18.3.3 Example Data Transfer Via JTAG
Scanning in a 5-bit instruction will take 12 TCK cycles
from the Run-T est/I dle state: 4 cycles to reach Shift-IR
state, 5 cycles for actual shifting in, 1 cycle to exit1-IR
state, 1 cycle to Update-IR state, and 1 cycle back to
Run-Test/Idle state. Likewi se, scann ing in a 32 bit data
register will take 38 TCK cycles and transferring an 8-bit
JT AG_ C TRL dat a regis te r wil l take 14 T CK cycl es fr om
Id le stat e. How eve r, if a da ta tran sfer follo ws ins truc tion
transfer, then the transition to DR scan stage can be
done w ithout goin g through Idle state, sa v ing 1 cy cle.
18.3.3.1 Transferring data to TriMedia via
JTAG
Poll control register to check if input buffer is empty. Scan
in data when it i s em pty and set the ifu ll control bit to ‘1’
triggering an interrupt. Note that scanning in any instruc-
tion automatically scans out the 3 least significant bits
(i nc lu di ng i ful l an d of ull bit s) of th e JTAG_ C TR L regi st e r.
Table 18-3. Transfer of Data in via JTAG
Action Number of
TCK cycles
IR shift in SEL_IFULL_IN instruction 12
While JTAG_CTRL.ifull = 1, scan in
SEL_IFULL_IN instruction 11+
DR scan 33 bits of register JTAG_IFULL_IN 38
TOTAL 61+ cycles
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
18-6 PRELIMINARY SPECIFICATION
18.3.3.2 Transferring data from TriM edia via
JTAG
Poll control register to check if output buffer is full. Sc an
out data when it is fu ll an d clea r t he ofu ll c on tro l bit. Note
th at sc ann ing in an y i nstr uct ion a uto mat ica lly s can s o ut
the 3 least significant bits (including ifull and ofull bits) of
JTAG_CTRL register.
Note that the above timings do not include the over-
heads of the JTAG software driver for JTAG interface
module plugged into a PC.
18.3.4 JTAG Interface Module
It is exp ected t hat the in terf ace mo dule wil l be a p rogram-
mable JTAG interface module. One end of the module
should be connected to a JTAG tap and the other end to
a host computer via a serial or parallel line or plugged
into a PC. It is up to the JTAG driver software on a host
computer to program the JTA G interface module via the
serial/parallel interface for transferring data to/from the
target. The transfer rates will depend on the interface
module.
Tabl e 18-4. Tr ansfer of Data out via JTAG
Action Number of
TCK cycles
IR shift in SEL_OFULL_OUT instruction 12
While JTAG_CTRL.ofull = 0, scan in
SEL_O FULL_OUT instructio n 11+
DR scan 33 bits of r egister JTAG_OFULL_OUT 3 8
TOTAL 61+ cycles
PRELIMINARY SPECIFICATION 19-1
On-Chip Sema phore Assis t Devi ce Chapte r 19
19.1 OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 has a simple MP semaphore-assist device. It
is a 32-bit register, accessible through MMIO by either
the local PNX1300 CPU or by any other CPU on PCI
thr ou gh the ap er ture m ade a vailable on PCI. The sem a -
phor e , S EM , is loc a t ed at MMIO of f set 0x10 0500.
SEM o pe rat ion is as fo llo ws: e ach ma ster in the sy stem
constr u c ts a p er s on al no nz er o 1 2 b it ID (see be lo w ) . To
obtain the global semaphore, a master does the follow-
ing action:
write ID to SEM (use 32 bit store, with ID in 12 LSB)
ret r ieve S EM (u se 32 bit loa d, it ret urns 0x00 000nnn )
if (SEM = ID) {
“p erfor m s a sh ort c r iti ca l section ac tion”
write 0 t o SEM
}
else “try again later, or loop back to wri te”
19.2 SEM DEVICE SPECIFICATIO N
SEM is a 32-bit MMIO location. The 12 LSB consist o f
s torage flip-flops w ith s ur rounding l ogic, the 20 M SBs a l-
ways re turn a ‘0’ when r ead.
SEM i s RESET to ‘0’ by power up reset.
When SEM is written to, the storage flip-flops behave as
follows:
if (cur_con tent == 0) n ew_conten t = wri te_va lue;
else if (wr i te_v alue == 0) ne w _c ontent = 0 ;
/* ELSE NO ACTION ! */
19.3 CONSTRUCTING A 12-BIT ID
A P NX1300 pr ocess or can c onst ruct a pers onal, nonze ro
12-bit ID in a variety of ways. Below are some sugges-
tions.
PCI configspace PERSONALITY entry. Each PNX1300
receives a 16-bit PERSONALITY value from the EE-
PROM during boot. This PERSONALITY register is lo-
cated at offset 0x40 in configuration space. In a MP sys-
tem, some of the bits of PERSONALITY can be
indi vi dual ized for eac h C PU i nvol ved, gi ving it a un ique
2/3/4-bit ID, as needed given the maximum number of
CPUs in the design.
In the case of a host-assisted PNX1300 boot, the PCI
BIOS assigns a unique MMIO_BASE and DRAM_BASE
to every PNX1300. In particular, the 11 MSBs of each
MMIO_base are unique, since each MMIO aperture is 2
MB in size. These bits can be used as a personality ID.
Set bit 11 (MSB) to '1' to guarantee a nonzero ID#.
19.4 WHICH SEM TO USE
Ea ch PN X 13 00 in t h e sy s tem ad ds a SE M d ev ic e to the
mix. The intended use is to treat one of these SEM de-
vices as THE master semaphore in the system. Many
met ho ds can b e use d t o det ermi ne whic h S EM i s mast er
SEM. Some e x amples bel ow:
Each DSPCPU can use PCI configuration space access-
es to determine which other PNX1300s are present in
the system. Then, the PNX1300 with the lowest PER-
SON ALIT Y numbe r, or the lowest MMIO_ base is cho sen
as the PNX1 300 containin g the master s ema phore.
19.5 U SAGE NOT ES
To av oi d co nte nt io n on the ma st er S EM dev ice , it sho ul d
only be used for inter-processor semaphores. Processes
running on a single CPU can use regular memory to im-
plement synchronization primitives.
The critical secti on associated with SEM should be kept
as short as possible. Preferably, SEM should only be
used as th e bas is to make mu ltipl e memo ry -resi dent sim-
pl e se m ap ho r es . In t hi s c as e , th e non -ca chea bl e D R A M
area of each PNX1300 can be used to implement the
se m ap ho r e da t a str uc tur es e ffici ent l y.
As described here, SEM does not guarantee starvati on-
free access to critical resources. Claiming of SEM is
purely stochastic. This should work fine as long as SEM
is not overloaded. Utmost care should be taken in SEM
access frequency and duration of the basic critical sec-
tio ns to ke ep the load conditio ns reason able.
00000000000000000000
31 12 11 0
SEM
0x10 0500
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
19-2 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION 20-1
Arbiter Chapter 20
by Eino Jacobs, Luis Lucas, Chris Nelson, Allan Tzeng, Gert Slavenburg
20.1 ARBITER FEATURES
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 internal highway bus conveys all the
memory and MMIO traffic. The on-chip peripheral units
described in this databook are connected to this internal
highway bus. Accesses to the bus are controlled by a
ce nt r al a r biter . Figure 2-1 on pag e2-2 shows the whole
system where the arbiter is embedded in the main mem-
ory interface (MMI) block. The traffic includes the memo-
ry r eque st s i ss ue d b y mos t of the on- c hip uni t s a s we ll as
the MMIO transactions issued by the DSPCPU or PCI
block and responded to by the peripherals.
Th e arb it e r w a s des igned to mak e P N X1 30 0 a t rue real -
time system by providing a highly programmable bus
bandwidth allocation scheme. The primary characteris-
tics are:
•round robin arbitration
•hi erarchic al organization
•pro gr am m able al loca t ion of hig hwa y ban dwidth
•dual pr i oriti es w ith priority raisi ng mec han ism
These features are explained in the next sections of this
chap ter. The arbiter is programmed through two MMIO
registers:
•ARB_RAISE
•ARB_BW_CTL
The default values (after hardware RESET) stored in
the se two MMIO reg ister s are suit abl e fo r most of the ap-
plications. If these default settings introduce violations of
re al -ti me const rai nt s in u ni t s like Vi deo I n ( VI ), V ide o Out
(VO), Audio In (AI) and Audio Out (AO) (each of these
units has a Highway Bandwidth Error det ection mecha-
nism), the ARB_BW_CTL register should be pro-
grammed to 0x090A9. This setting gives almost maxi-
mum priority to real-time units but may slow down the
CPU.
Fine tuning of the arbiter setti ngs is descr ibed in the fol-
lowing sections.
20.2 DUAL PRIORITIES WITH PRIORITY
RAISING MECHANISM
The best CPU pe rformance is obtained if cache misses
can take priority over peripheral requests on the high-
way. However, peripherals need to have a maximum
guaranteed latency low enough to satisfy the real-time
constr aints of I/O units.
PN X13 00 p ro vi de s t hi s f eat ur e wit h the fo ll o win g prio r ity -
raising mechanism.
Peripheral unit requests can have 2 priorities: low and
high. With in each cla ss there is fair, round-r obin arbitr a-
tion (Section 20.3). Requests with high priority take pre-
cedence over requests with low priority.
Uni t s ca n i nd i c at e t h e p r io r ity o f their re q u ests t o b e l o w
or high.
A unit m ay in iti al ly po st a re qu est wi th lo w priority . If the
request is not serviced within a particular waiting time,
th e un it c an rais e the pr i ori t y of the re ques t to h ig h. Th is
c an be done when the wo r s t case latency at high prior ity
app r oac he s the rea l- t i me c ons tr ai nt of the unit . Thus , t h e
uni t uses on ly spare ba ndwid th with out slowing down th e
CPU unless re al-time constraints require it to claim high
priority.
In P NX 13 00, onl y th e IC P uni t has it s own pri o rit y raisi ng
logic (i.e. it controls the low to high transition of the re-
quest). Refer to Chapter 14, “Image Coprocessor,” for
more in form ation.
Priority raising for the VLD, PCI, VI and VO units is han-
dled by the arbiter central priority raising mechanism.
Th e c e ntral pr iori ty r aisi ng mec han ism se tti ngs ar e con -
trolled from the DSPCPU with the ARB_RAISE MMIO
register (see Table 20-1). The delay is the amount of
time for which the arbiter handles the request at low pri-
ority.
Th e dela y is de fine d by a 5- bit f ield (d ed icat ed per unit )
and is co unted in CPU clock cycle s. The granularity of
the delay is 16 cycles, so the maximum time spent at low
priority for each request can be programmed from 0 to
496 c ycles, inclu s ive, in increments of 16 cycles .
The default value for the entire ARB_RAISE register is
‘0’. This c auses all requests from VLD, PCI, VI and VO to
be handled as high-priority requests until the
Table 2 0-1. ARB_RAISE register layout
Offset Name Bits Fields
0x10010C ARB_RAISE 19:15 VLD_delay[4:0]
14:10 PCI_delay[4:0]
9:5 VI_delay[4:0]
4:0 VO_delay[4:0]
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
20-2 PRELIMINARY SPECIFICATION
ARB_RAISE register contents has been changed for the
applic ation r e quirem ents.
Corner-case no te: There is s ome risk in setting the delay
high, then lowering it, as the last request submit ted with
the high delay might violate the latency constraints of the
new real- tim e dom ain . Ho wev er thi s sho uld n ot ha pp en
since this register should be set before the application
starts.
The other units (AI, AO and BTI (boot block)) and the
CPU will always have their requests considered as high
priority. High priority for the CPU will give maximum pos-
si bl e pe r forma nc e.
AO and AI requests are happening at very low rate.
Hence, the probability that they take time away from the
CPU is negligible.
2 0.3 R OU ND ROBIN A RB ITRATION
In addition to the dual priority mechanism, a round-robin
arbitration is used to schedule the requests with same
priority. The purpose is to ensur e, for every unit with a
high-priority request, a maximum latency for gaining ac-
cess to the highway and/or a minimum share of the avail-
able bandwidth.
Round-robin arbitration ensures that no star vation of re-
quests can occur and therefore requests with real-time
constraints can be handled in time.
The round robin arbitration algorithm is as follows.
Re quests are granted accordi ng to a dynami c prio rity li st .
Whenever a unit reque st is granted, it wil l be moved to
the last position in the priority list and another unit will be
moved to the first position in the priority list. Priorities are
ro tated. A unit with a wait ing requ est wi ll eve ntu ally reac h
the first place in th e priority list.
As a n e xam pl e, Figure 20-1 shows a state diagram of an
ar bi tra t ion st a te ma chin e wi th 2 re quest e rs. The n odes A
and B indicate states A and B. In state A, requester A has
ownership of the highway, in state B requester B has
ow nership. The ar c from stat e A to state B i ndicat es that
if the current state is state A and a request from request-
er B i s ass er ted, th en a tran si tion t o stat e B o ccur s, i .e.
ow ne rshi p o f th e hi gh way passe s f rom r eq uest er A t o re-
quester B.
When, in a particular state, none of the arcs leaving from
th at no de has its cond ition fulfilled, the state machin e re-
mains in the same state.
When bo th requester A a nd B have requests asserted,
th en ow nersh i p of t he hi ghw ay s witches bet ween A and
B, creating fair allocation of ownership.
Figure 20-2 pictures a state diagram that allocates fair
arbitration with 3 requesters.
20.3.1 Weighted Round Robin Arbitrati on
Not all u nits ne ed t o have equal latency and bandwidth.
It is preferred to allocate bandwidth to units according to
th eir need s . Thi s is achi eved wit h we ighte d r ound -rob in
and can be illu str ate d in the fol l o wing ex am pl es .
Figure 20-3 pictures a state machine with two requesters
A and B w ith double weigh t gi ven t o reque ster A . The r e
are now 2 states A1 and A2 where requester A has own-
ers h ip of t he hi ghw ay . When both A an d B reques ts are
asserted, requester A will have ownership of the highway
twice as o f ten as requester B.
AB
Figure 20-1. State diagram of round robin arbitra-
tor with 2 requesters.
B
A
AB
Figure 20-2. State diagram of round robin arbitra-
tor with 3 requesters.
A&~C
B
C
AC
B&~A
C&~B
A1 B
Figure 20-3. State diagram of round robin arbitra-
tor wi th 2 r e que sters; A has double w e ight.
B&~A
A
A2
A
B
Philips Semiconductors Arbiter
PRELIMINARY SPECIFICATION 20-3
Figure 20-4 s h ow s a state machin e w it h 3 reque ste r s in
whi ch double weigh t is gi ven to r equester A . Such state machines can become very complex and
c annot be imple mented for a large system like P NX1300
with 9 requesters. Hierarchy or arbitration levels are
used to overcome this problem.
20.3.2 Arbitration Levels
The arbitration is split into multiple levels of hierarchy.
Each level of hierarchy has an independent arbitration
state machine. At the bottom of the hierarchy, the arbitra-
tion is performed between a group of units. Whichever of
these units ‘wins’ is passe d t o the next level o f h i erar c hy,
where the selected unit competes with other units at that
level for highway access.This is continued until the high-
es t le vel of arbitrat ion.
By splitting arbitration into multiple levels it is easy to
support a large number of highway units while the com-
plexity of the arbitration state machines at each level of
hi erar c h y r emain s mod est.
A1 B
Figure 20-4. State diagram of round robin arbitra-
tor with 3 requesters; A has double weight.
B
A2C
A
C
A
B&~A
C&~A
A&~B
A&~C
B&~C&~A
C&~B&~A
L1 arbitra tion
L6 arbitration
L5 arbitration
L4 arbitration
L3 arbitration
L2 arbitration
Ca ch e prio ri ty- ba s ed ar bitra ti on
vo_req
icp_reqh
icp_reql
vi_req
pci_req
vld_req ai_req ao_req
bti_mmio_req
bti_req
pci_mmio_req
ic_req
dc_req
dc_mmio_req
dc_req_pref
1/2/3 1/2/3
1/3/5 1/3/5/7
1/3/5/7 1/3/5
1/2 1/3/5
1/3/5 1/2
11 1
1111 2
Figure 20- 5. Arbitrat ion archit ecture
dvdd_req
1
spdo_req
1
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
20-4 PRELIMINARY SPECIFICATION
Hierarchy also makes it easy and natural to allocate bus
ban dw i dth o r l aten cy to a group o f unit s . Mos t band wi dt h
or la tenc y-dem a ndin g units a re loca te d at the top of the
hierarchy while the less demanding are at the bottom
and get a smal l a mount of overall bandwidth.
2 0.4 A RBI TE R ARCH I TECT U R E
In addition to the dual priority mechanism described in
Section 20.2, PNX1300 supports an arbitration architec-
tur e made of 6 fixed levels of hierarchy. This is combined
with a programmable weighted round robin algorithm per
leve l, as p ic tur ed in Figure 20-5.
The weights can be adjusted by software to allocate
ban dwi dth and la tenc y depen din g on ap plic ation requi re-
ments. Within a level of hierarchy the units can have
equ al weig ht s, giv ing them an equa l sh are of ban dwi dt h.
Alternatively, they can have different weights, giving
them an unequal share of the bandwidth for that level.
The arbitration weights at each level are described in
Table 20-3 and illustrated in Figure 20-5.
Table 20-2 presents the minimum bandwidth allocation
at Level 1 between the DSPCPU and the peripherals
(l ev el 2) acco r ding to th e di ffe r ent w eig ht val ue s that can
be programmed. Note that programming a weight of 3/3
or 2/2 ins tead of 1/1 is lega l and results in the same allo-
cation.
Note: The different types of requests from the DSPCPU
caches are arbitrated locally before sending a single
CPU request to the arbiter. The PCI bus also performs lo-
c al a rbi t rat io n bef or e sen ding a s ystem requ es t t o th e ar -
biter.
The weight programming is done by setting the MMIO
register ARB_BW_CTL. Register offset a s w ell as field
description and coding is provided i n Table 20-4.
The hardware RESET value of ARB_BW_CTL is 0, re-
sulting in a weight of 1 for all requests .
Note that each media processor application needs to
carefully re vi ew its arbite r settings .
Table 20-2. Minimum bandwidth allocation between
CPU c ac hes and periph era l units .
weight of
CPU and
caches
weight of
level 2 bandwidth
at level 1 bandwidth
at level 2
3 1 75% 25%
2 1 67% 33%
3 2 60% 40%
1 1 50% 50%
2 3 40% 60%
1 2 33% 67%
1 3 25% 75%
Table 20-3. Arbitration weights at each level
Level Arbitration Weights
level 1: CPU MMIO, Dcache, Lcache are arbitrated with
fixed prioriti es between each other and toget her
have a programmable weight of 1, 2 or 3.
Level 2 has a programma ble weight of 1, 2 or 3.
level 2: VO unit has a programmable weight of 1, 3 or 5.
Level 3 has a programmable weight of 1, 3, 5 or 7.
level 3: The ICP unit has a programmable weight of 1,3,5 or
7. Level 4 has a programmable weight of 1,3 or 5.
level 4 The VI unit has a programmable weight of 1 or 2.
Level 5 has a programma ble weight of 1,3 or 5.
level 5: The PCI unit has a prog rammable weight of 1,3 or 5.
Level 6 has a programmable weight of 1 or 2.
level 6: Level 6 contains several lower bandwid th and/or
latency-tolerant units. The VLD has a weight of 2. AI,
AO, DVDD and the b oot block (only ac tive duri ng
booting) have a weight of 1.
Table 20-4. ARB_BW_CTL MMIO register
Offset level of
arbitration field bits allowed
values
0x100104 n/a RESERVED 25:18
level 1 CPU weight 17:16 00 = weight 1
01 = weight 2
10 = weight 3
level 1 L2 weight 15:14 00 = weight 1
01 = weight 2
10 = weight 3
level 2 VO weight 13:12 00 = weight 1
01 = weight 3
10 = weight 5
level 2 L3 weight 11:10 00 = weight 1
01 = weight 3
10 = weight 5
11 = weight 7
level 3 ICP weight 9:8 00 = weight 1
01 = weight 3
10 = weight 5
11 = weight 7
level 3 L4 weight 7:6 00 = weight 1
01 = weight 3
10 = weight 5
level 4 VI weight 5 0 = weight 1
1 = weight 2
level 4 L5 weight 4:3 00 = weight 1
01 = weight 3
10 = weight 5
level 5 PCI weight 2:1 00 = weight 1
01 = weight 3
10 = weight 5
level 5 L6 weight 0 0 = weight 1
1 = weight 2
Philips Semiconductors Arbiter
PRELIMINARY SPECIFICATION 20-5
20.5 ARBITER PROGRAMMING
The PNX1300 arbiter accepts programmable bandwidth
weights to directly control the percentage of bandwidth
al lo ca ted to eac h unit. In the wor s t case all b a n dw i dt h is
used. If not all of the bandwidth is used, then all units
eventually get their desired bandwidth (as the bus be-
comes free) regardless of the weights. However, the
weights still indirectly guarantee each unit a worst-case
latency, which is important for the real-time behavior.
There are two basic types of PNX1300 coprocessor and
peripheral units. The first type is units which have hard
rea l-t ime c ons traint s, i .e. VO, VI, AO and AI . T o en sure
multimedia functi onality, these units must be able to ac-
quire the bus within a fixed amount of time in order to fill
or empty a buffer before it over- or underflows.
The second type, the CPU, PCI, ICP, VLD and DVDD
units, can absorb long latencie s but performance is en-
hance d (t he re are few e r sta ll c yc les or waiting c yc les ) if
latency is short. The bandwidth requirement is usually
known and depends on the application. It is especially
well known that ICP and VLD or DVDD have a fixed
bandwidth requirements in multimedia applications.
For the PNX1300 DSPCPU, latency is of prime impor-
tance. C P U pe r formance reduces as ave rage latency in-
creases. The design of the arbiter guarantees that the
DSPCPU g ets a ll un used bus bandwidth with lowest pos-
sible latency. Optimal operation is achieved if the arbiter
is set in such a w ay that the DSPCPU has the best pos-
s ible lat en cy give n t h e re qu ire d l at ency an d ba nd wid th of
units active in the application.
To pick programmable weights and priority raising de-
lays, the follow i ng proced ur e is r ec om mende d:
1. Tr y to keep CPU weight as high as po ssible th rough
the remaining steps.
2. Pick w ei ghts suffici ent to guarante e lat ency to hard
rea l-tim e per i ph erals (s ee Section 20.5.1).
3. Pick weights for remaining peripherals in order to give
eno ugh ba ndwid th t o each (see Section 20.5.2). Step
2 above has p r iority, because bandwidth can be ac-
quired as the bus becomes free and because the hard
real-time units use a known amount of bandwidth.
4. If lat ency and band width sl ac k remains, increase pri-
ority ra ise delays in order to improve average CPU la-
tency.
20.5.1 Latency Analysis
In the following, ceil(X) is the least integral value greater
th an or equal to X.
Latency is defined in each real-time unit chapter through
this databook. Refer to the related sections to find out the
latency requirement according to the mode and clock
speed at which the unit is operating.
This latency value has to be larger than the maximum la-
tenc y Lx (in nanoseconds) guaranteed by the arbiter.
For a unit x the arbiter guarantees a latency of:
Lx = Lx,sc * (SDRAM cycle time in ns)
where
Lx,sc = (Dx * T) + E + ceil(Dx * T / Kd) * K + ceil(16*Rx/C)
is th e la ten cy in SDRA M c lo ck cycle s.
La te nc y in C PU cl oc k cy c le s is de fi ned by :
Lx,cc = ceil(Lx,sc * C)
The symbols are defined as follows:
T = 20 c ycle s (tr ans acti on le ngt h, a ssum ing wors t ca se
pattern al ternating reads and writes).
E = 10 cycles (extra delay in case the first transaction
made by the CPU requires a different bank order to sat-
isfy th e cri tic a l word firs t.
K = 19 cyc les (refresh tra nsacti on leng th).
Kd is th e progr amme d refres h int erva l (see Sec tion 12.1 1
on page12-6).
C is the CPU/SDRAM ratio (i.e. 5/4, 4/3, 3/2, 2/1 or 1 as
exp laine d in Se ction 12.6 . 2 on page12-4 ).
Rx is th e p r io rity rais e de la y of unit x as st o re d i n MMI O
register ARB_RAISE (see Section 20.2).
Rx = 0 for units other than VO, VI, PCI or VLD.
Dx is t h e w o rs t cas e nu mbe r of r e qu es ts th at the a r b iter
allows before the request from unit x goes through.
Dx includes the transaction from unit x (the unit which
needs the data) as well as the internal implementation
delays that occur in the transaction.
Dx is de riv ed fr om th e arb iter se tt i ng s as fo llo w s :
DCPU ceil CPUweight L2weight
+
CPUweight
------------------------------------------------------
=
DVO ceil VOweight L3weight
+
VOweight
--------------------------------------------------
D2
×1+=
DICP ceil ICPweight L4weight
+
ICPweight
----------------------------------------------------
D3
×1+=
DVI ceil VIweight L5weight
+
VIweight
------------------------------------------------
D4
×1+=
DPCI ceil PCIweight L6weight
+
PCIweight
----------------------------------------------------
D5
×1+=
DVLD ceil 211011+++++
2
-------------------------------------------------
D6
×1+=
DAI ceil 211011+++++
1
-------------------------------------------------
D6
×1+=
DAO ceil 211011+++++
1
-------------------------------------------------
D6
×1+=
DDVDD ceil 211011+++++
1
-------------------------------------------------
D6
×1+=
DSPDO ceil 211011+++++
1
-------------------------------------------------
D6
×1+=
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
20-6 PRELIMINARY SPECIFICATION
Where
As an example, if CPUweight is 3, L2weight is 2, VOweight
is 3 and L3weight is 7, then
•D2 is ceil[(3 + 2) / 2] = 3,
•DVO is ce il[ ( 3 + 7) / 3] * 3 +1 = 13 .
If CPU/SDRAM ratio is 5/4 (for example memory fre-
quency is 80 MHz and CPU frequency is 100 MHz), re-
fresh interval Kd is 1220 cycles, and Rx is 2, then the
maximum latency for VO is:
•LVO,sc = 13 * 20 + 10 + ceil[13 * 20 / 1220] * 19 +
c eil(16 * 2 / (5 / 4)] = 315 SDRAM cycles
•LVO = LVO,sc * 12.5 = 3937.5 ns
Note: Aver ag e la te nc y is no r mal ly much low er t han w orst
ca s e l at e nc y be cause on r a r e o c casi ons many u ni ts w ill
iss ue r e quest s at exac tly t he same time (thi s is ass ume d
whe n ev alua t in g the ma xi mum la tenc y ) .
Note: A ll re al- time units hav e a sp ecia l ex cept ion n ot ifi-
cation fl ag that i s raised if an overflow or unde rflow oc-
curs while operating.
Note: To compute the latency Lx whe n a unit is not en-
abled, its weight has to be set to ‘0’ in the D{2,3,4,5,6}
equations and in D{AI,AO,VLD} for AI, AO or VLD.
The se equa t io ns are not ac cura t e for all th e we i ghts , but
gi ve an upper bound of the worst case (which is usually
too pessimistic).
A much more accurate number could be found by simu-
lating the arbiter, e.g. if the settings are: CPUweight=1,
L2weight=2, VOweight=1 an d L3weight=1, then
DVO = ceil[(1 + 1) / 1] * ceil[(1 + 2) / 2]
givi ng 4 requests. But actually the worst c ase grant re-
quests order is: CPU, L3, VO - resulting in 3 requests
only.
20.5.2 Bandwidth Analysis
In the following, ceil(x) means the least integral value
greater than or equal to x.
Minimum allocated bandwidth, Bx for a unit x, by the ar-
bit er is defined as foll ow s:
Bx = (Mcycles - Kk) * S / [T * Ex + (16 * Rx / C)]
Where:
Mcycles is the total amount of SDRAM cycles avai lable in
a period P in which the bandwidth is computed. For ex-
am ple, if the period is 1 second and SDRA M runs at 8 0
MHz then Mcycles is 80,000,000.
Kk is t he amou nt of SD RAM cycle s us ed by th e refr esh
during the same period P.
If P is i n se co nd s it co uld be ex p ressed as:
Kk = c ei l( 4 09 6 * P / .0 64 ) * K
For example, if P is 1 second then Kk is
ceil(4096 * 1 / .064) * 19 = 1216000 SDRAM cycles.
S is the size of the transaction on the bus.
For PNX1300, S is equal to 64 (bytes).
Ex is the ratio of requests available for a unit x according
to the arb ite r s et tin gs .
It means the unit x will get 1 / E
x o ut of the total requests.
Ex is derived from the arbiter settings as follows:
Where:
D2ceil CPUweight L2weight
+
L2weight
------------------------------------------------------
=
D3ceil VOweight L3weight
+
L3weight
--------------------------------------------------
D2
×=
D4ceil ICPweight L4weight
+
L4weight
----------------------------------------------------
D3
×=
D5ceil VIweight L5weight
+
L5weight
------------------------------------------------
D4
×=
D6ceil PCIweight L6weight
+
L6weight
----------------------------------------------------
D5
×=
ECPU CPUweight L2weight
+
CPUweight
------------------------------------------------------=
EVO VOweight L3weight
+
VOweight
--------------------------------------------------E2
×=
EICP ICPweight L4weight
+
ICPweight
----------------------------------------------------E3
×=
EVI VIweight L5weight
+
VIweight
------------------------------------------------E4
×=
EPCI PCIweight L6weight
+
PCIweight
----------------------------------------------------E5
×=
EVLD 211011+++++
2
------------------------------------------------- E6
×=
EAI 211011+++++
1
------------------------------------------------- E6
×=
EAO 211011+++++
1
------------------------------------------------- E6
×=
EDVDD 211011+++++
1
------------------------------------------------- E6
×=
ESPDO 211011+++++
1
------------------------------------------------- E6
×=
E2CPUweight L2weight
+
L2weight
------------------------------------------------------=
E3VOweight L3weight
+
L3weight
--------------------------------------------------E2
×=
E4ICPweight L4weight
+
L4weight
----------------------------------------------------E3
×=
Philips Semiconductors Arbiter
PRELIMINARY SPECIFICATION 20-7
For example, with the same settings as in the example of
Section 20.5.1, then
•E2 is (3 + 2) / 2 = 2.5
•EVO is (3 + 7) / 3 * 2.5 = 8.33 ,
which gives
•BVO = (80 - 1.216) * 64 / [ 20*8.33 + 16*2 / (5/4) ]
resulting in 26.23 million B/sec corresponding to 25.01
MB/sec.
Note: In order to co mpute the latency Bx when a unit is
not enabled, i ts wei ght h as to be considered as ‘0’ in the
E{2,3,4,5,6} equations and in E{AI,AO,VLD} for AI, AO or
VLD.
The maximum amount of requests, Ax, for unit x allowed
dur in g M cycles period is:
Ax = floor(Bx / S)
Where floor(X) is the greatest integral value less than or
equal to X .
Note: This number does not take into account the worst
case pa tter n for r equest ackn owled gment . Thus if th e pe-
rio d is to o sm al l Ax is not accurate.
2 0.6 E XT EN DED BE HA VI OR AN AL YSI S
The following sections describes a more accurate behav-
ior of the PNX1300 arbitration system.
20.6.1 Extended Bandwidth Analysis
The minimum bandwidth allocation derived from the ar-
bi ter se t tings is ac cur a t e if one o f the two following con-
ditions are true:
•The units emit requests all the time (i.e. do back-to-
back requests)
•After a request has been acknowledged, the unit
emits a new request before the new arbitrat ion point.
The arbitration is decided around every 16 cycles.
This time depends on the direction of the transac-
tio ns ( read/ w rite) .
In P NX130 0, the only uni t almo st abl e t o sust ai n bac k-t o-
bac k req ue st s is the dat a cache. The ot her uni t s will post
a request and wait for the data before the next request is
posted. This behavior makes the bandwidth computa-
tion:
•almost accurate if the unit is down in th e arbiter hier-
arc hy (t r u e if the un its pl aced abov e ar e enab led).
•rath er in ac curat e if l arge we ig ht s are us ed for a unit.
Since no back-to-back requests are implemented, the
worst case is that a u nit can only get one request out of
three if all the others are asking. This limits the use of
large weights for other units than data cache.
How e v er so m e un its m ight be able t o c atch one request
out of two . Thi s de pe nd s on the way req ue st s in ter l ea ve,
since the arbitration point is dependent on the type of the
request (read or write) as well as on the CPU ratio.
This makes it almost impossible to describe the behavior
precisely.
The exact bandwidth necessary for units like VO, VI, AO
or A I a re well kno wn (see de di cate d se ct ion s i n e ach c or -
respon di ng ch apte r). If the arbite r s ett ings a lloca te m ore
bandwidth for these units than they can use, the extra
band width can be use d by unit s that are located be low
th es e un it s ( VO , VI ) o r at the same level a s (A O and A I )
in the arbiter hierarchy.
As an example, with the default settings, VO gets 25% of
the available bandwidth and the CPU gets 50%. If the
SDR AM c lo ck sp ee d is 100 MHz , the n 10 0 M B/se c are
allocated to VO. If VO runs at 27 MHz (NTSC or PAL
mode), then VO will not use all this allocated bandwidth.
Th us any of the units that are belo w VO in the a rb i t e r hi -
erarchy can potentially use the remaining allocated
bandwidth.
In o ther w ords - even if only 1 0% are a lloc ated to one un it
like th e CPU , PCI or the IC P, it may use m ore .
20.6.2 Extended Latency Analysis
Some units (VO and VI) have a latency/bandwidth re-
qui reme nt and t hei r behav ior nee ds to be si mulated i n or-
der to find out t he correct settings. For example the re-
quirement for VO (in image mode 4:2:2 or 4:2:0 without
up scaling, overlay disabled) is:
•During 128 VO cl ock cy c le s, VO block ne ed s to
have 2 requests acked ([2 Ys, one U and one V]/2).
The defaul t value ‘0’ for AR B_B W_C TL le ad s to a bu s a l-
location of 50% for CPU, 25% for VO and 25% for L3
blocks.
The w orst cas e arbitr atio n for V O is then : CPU L3 C PU
VO, CPU L3 CPU V O to which the re fresh (K ), internal
delays (T) and E for the first CPU request need to be
added.
The first VO request will require 129 SDRAM cycles (DVO
= 5 or f ro m the wo rst cas e pa tt e rn 19 + 10 + 20 + 4 * 20 ).
The arbitration pattern shows that the following request
will require (in the worst case) an extra 4 * 20 SDRAM cy-
cles. Thus VO clock speed cannot be greater than
61. 2 4% ( 1 28 / [129 + 80]) of th e S D RA M clock speed.
By changing the settings to 33% for the CPU, 33% for VO
and 33% for L3 blocks (i.e. CPU weight = ‘1’, L2 weight = ‘2’,
VOweight = ‘1’, L3weight = 1), the new SDRAM/VO clock
percentage becomes 75.74% (128 / [109 + 60]) corre-
sponding to a worst case arbitration pattern of CPU L3
VO, CPU L3 VO.
Before changing the settings the minimum SDRAM
spe ed requi red to r un VO at 74.2 5 MH z ( h igh d efin ition
speed) was 122 MHz. After the new allocation 100 MHz
is fi ne . Note th at he re DVO remains equal to ‘5’.
E5VIweight L5weight
+
L5weight
------------------------------------------------E4
×=
E6PCIweight L6weight
+
L6weight
----------------------------------------------------E5
×=
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
20-8 PRELIMINARY SPECIFICATION
When VO is running in image mode 4:2:2 or 4:2:0 without
upscaling and overlay enabled, the requirements be-
come:
•During the first 64 VO clock cycles at least one
request must be acked (the OL (overlay) data).
•During 128 VO clock cycles, VO block requires that
4 re que sts b e a cked ([4 OLs, t wo Y s on e V an d one
U]/2).
If the settings are 33% for the CPU, 33% for V O and 33%
for L3 blocks then the worst case arbitration pattern is
CPU L3 VO, CPU L3 VO, et c.
The first requirement limits the VO/SDRAM ratio to
(64 / [19 + 10 + 20 + 3 * 20] ) = 58.7 % .
The second requirement gives a VO/SDRAM ratio of
44. 2 9% (128 / [19 + 10 + 20 + 3 * 20 + 3 * 20 * 3 ]).
Th us if VO cl oc k sp ee d is su ppos ed to be 54 M Hz (pro -
gr essiv e scan ) the SDR AM mu st ru n at le ast at 12 2 MHz.
By setting the arbite r to 25% for the CPU, 37.5% for VO
and 37.5% for VI (CPUweight = 1, L2weight = 3, VOweight =
1, L 3weight = 1, assuming only VO and VI are enabled)
the arbitration pattern becomes CPU VI VO VI CPU VO
VI VO CPU VI VO.
Now both VI and VO ar e able to catc h one req uest out of
two, thanks to the read / write overlap. This leads to a
VO/SDRAM ratio of 47 .5 % or a 113 MH z SDRAM.
20. 6.3 Raising P riority
If VO i s running at 27 M H z ( NTS C or PAL) wi thout over -
lay and CPUweight is set to ‘3’ while all the ot he r weigh t s
are set to ‘1’, then the worst case latency derived from
20.5.1 for VO is:
LVO,sc = (ceil[(1 + 1) / 1] + ceil[(3 + 1) / 1] + 1) * 20 + 10
+ 19 = 169 S DRAM cycles (assumes RVO = ‘0’).
The latency for VO is 1 request in 64 VO clock cycles. If
SDRAM is runn ing at 80 MHz , then t he max imum la ten cy
to ler at e d by VO is floo r (6 4 / ( 27 / 80)) = 1 89 SD R A M cy -
cles.
This means that VO requests can remain at low priority
for 189 - 169 = 20 SDRAM cycles.
If the CPU clock speed is 100 MHz (ratio is 5 / 4) then the
ARB_RAISE register can be programmed to:
floor(20 * (5 / 4) / 16) = 1.
VO requests will stay at low priority for 16 cycles allowing
sl ig htly be t ter average C PU pe r forma nc e.
20.6.4 Conclusion
There is no obvious way to set the best weights for laten-
cy or bandwidth allocation since the behavior of each
block cannot be easily described with equations. Practi-
c al results obtained by running applic ations showed th at
once the arbiter is weighted to meet latencies the re-
maining w eight settings do not allow much improvement.
The best way to tune the weights is by experiment, run-
ning the applic ation.
The only accurate computation is the maximum worst
c ase latency, w hich ensures that the hard real-time units
work properly. This computation gives an upper bound
and can be too pessimist ic - but it still gi ves the right or-
der of magnitude. Refer to Table 20-5 for the recom-
mended al location meth od.
Table 20-5. R ecomm ended Allocation Method
Video In allocate required latency
Video Out allocate required latency
Audio In allocate required latency
Audio Out allocate required latency
SPDIF O ut allocate required latency
ICP al locate bandwi dth
PCI al locate bandwi dth
VLD al locate bandwi dth/l atency
DVDD allocate bandw idth/l atenc y
PRELIMINARY SPECIFICATION 21-1
Power Management Chapte r 21
by Eino Jacobs and Hani Salloum
21.1 OVERVIEW
n this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX 1 30 0 suppor t s po w er manage men t in t wo w ay s :
•In global power-down mode, most clocks on the chip
are shut down and the SDRAM main memory is
brought into low-power self-refresh mode. The power
of all on-chip peripheral blocks except for BTI (boot
and I2C blocks), Dcache, Icache, PCI, timers and VIC
blocks is shut off. Some peripherals can be selec-
ti v el y pr e v en t ed from pa rtic ipat i ng in th e gl ob al pow er
down.
•A block power down me chani sm allows power down
of select peripheral blocks
2 1. 2 E N TE RING A N D EX I TING G LO B AL
POWER DOWN MODE
Power management is software controlled and is initiat-
ed by writing to the MMIO register POWER_DOWN. Dur-
ing execution of this MMIO operation, the system is pow-
ered down without completing the MMIO operation.
When the system wakes up from power down mode, the
MMIO operation is completed.
This means that during program execution on the
DSP CPU th e mo m en t of power dow n is d efi ne d ex actl y:
any instruction before the instruction that contains the
MMIO operation is completed before entering power
down mode. The instruction containing the MMIO opera-
tion and all subsequent instructions are completed after
wake up from power down mode.
Wak e-up fr om powe r down mo de is ef fect ed by re ceivi ng
an interrupt (any interrupt) that passes the acceptance
cr ite ria of th e inter ru p t con tr o lle r.
There is als o wake-up from power d own if a peripheral
unit asserts a memory request signal on the highway.
During power down mode the whole chip is powered
dow n, ex cept the PLLs, the i nterru pt logi c, the tim ers, the
wake-up logic in the MMI, and any logic in the peripheral
units and PCI bus interface that is not participating in the
power down.
Note: Writing to the global POWER_DOWN register (at
offset 0x100108) has no effect on the contents of the
BLOCK_POWER_DOWN register (at offset 0x103428),
an d vi ce v er s a .
21.3 EFFECT OF GLOBAL POWER DOWN
ON PERIPHERALS
Th e on -chip pe rip heral u nits part ici pate in glob al powe r
down. This can be a programmable option for selected
per iph erals. These sele cted perip herals ha ve a pro gram-
mabl e MMI O c on tro l bi t, t h e SL EEP L ESS b it , that can be
used to prevent it from participating in the global power
down mode. By default every peripheral unit must partic-
ipate in power down.
The following peripheral units have the SLEEPLESS bit:
Video In, Video Out, Audio In, Audio Out, SPDO, SSI,
an d JT AG .
Th e fol low ing p eriph er als d o no t hav e t he SL EEP LES S
bit and always participate in power down: VLD, boot/I2C
and I CP .
The following peripherals do not participate in global
power down, although they must power themselves
down when they are inactive: VIC, PCI.
When a pe ripheral does not participat e in global power
down, it ca n still d o regular ma in mem ory traffic. Every
time a peripheral unit asserts the highway request signal,
the MMI will initi ate a wake-up sequence. T he CPU must
execute software that initiates a new pow er down of the
s ystem. Thi s software can be the wait-loop of the RTOS.
Pr ogr amm er’ s no te : Si nce the sy stem i s awa ken ed e ach
tim e t h er e is a tr a nsa ction on the hig h wa y, it may be in -
ter estin g to ma ke a sof tware loop that does the activation
of t he PO WER_ DOWN mo de. The n th e activa tio n is con-
ditional and most of the time done using a global vari-
abl e, u sua lly s et by a han dl er. It then be co mes ma nd ato-
ry to be sure that there are no interruptible jumps
between the time the value of the global variable is
fetched and compared by the DSPCU and the time the
c ondi ti on al wri t e to the MMIO is per for me d (it is th e cla s-
sical semaphore or t est and set issue). Thus it is recom-
mended that a separate function be used with the ad-
dr ess of the varia ble as a parameter. This fun ction need s
then to be compiled specifically without interruptible
jumps.
The wake-up from power down mode takes approxi-
mat ely 20 SDRA M cloc k c ycle s. T his amou nt o f t ime is
added to the worst case latency for memory requests
compared to the situation when the system is not in pow-
er down mode.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
21-2 PRELIMINARY SPECIFICATION
21.4 DETAILED SEQUENCE OF EVENTS
FOR GLOBAL POWE R DOWN
The sequence of events to power down PNX1300 is as
follows:
•Is su e a MM IO write t o the POWER _D OW N re gi ster
•The main memor y in terface (MMI) waits till the com-
pletion of the current SDRAM transfer, if there is one
still bus y.
•The MMI brings SDRAM into the self refresh state,
goes into a wait state, and asserts the global signal
global_power_down.
•All units that par ticip ate in the power down, respond
to the global_power_down signal by disabling their
clocks.
•Only the PLL, interrupt controller, timers, wake-up
logic, t he PC I bus inter fac e, and any peripherals that
have their SLEEPL ESS bit c ontrol b it set continue to
be cl o cked. Th e S DR A M c lo ck co ntinues.
•An interrupt is detected by the interrupt controller or a
unit that didn’t participate in the power down requests
a memory transfer.
•The MMI de-asserts the global_power_down signal,
activating al l blocks on t h e ch ip.
•The MMI recovers SDRAM f rom self-refresh.
•The MMI causes completion of the MMIO operation
that i nitia ted th e p ower down sequence.
•When software takes an interruptible branch opera-
tion, the interrupt that caused the wake-up will be
serviced (if the wake-up was initiated by an interrupt).
2 1.5 MMIO RE G ISTER POWE R_DOWN
The register POWER_DOWN has an offset 0x100108 in
the MMIO aperture and has no content. Writing to this
register has the side-effect of powering down the chip.
Reading from this register returns an undefined value
an d ha s no s ide - e ff e ct.
21.6 BLOCK POWER DOWN
This fea t u r e is new in P NX 130 0. It sele ctiv ely shu ts off a
particular block or a set of blocks based on software pro-
gramming.
This type of power down can be used in applications
where certain blocks will never participate in the opera-
tion of the chip. The objective of having this type of power
down is saving on powe r consumption.
Each peripheral unit whi ch can participate in the global
pow er dow n ca n be s el ec tive ly po w ered do w n .
This is done by setting a control bit in MMIO register
BL OCK _POW ER_ DOW N spec if ical ly f or th e bloc k. T he
BLOCK_POWER_DOWN register is located at MMIO
offset 0x103428. See Figure 21-1 below.
Setting a particular bit to ’1’ in this register has the effect
of sh ut t in g off the cor r es po nd ing blo ck. W ri t in g ’0’ to th is
bit, enables the power for the block again.
A bl ock sh ould not be po were d down i f it is activ e. E nable
bit shou l d b e s et to ‘0’ before dec iding to powe r down t he
block.
Note: The unassigned bits of this register have to be writ-
ten to ‘0’ and read as ‘0’.
Note: Writing to the global POWER_DOWN register (at
offset 0x100108) has no effect on the contents of the
BLOC K_POWER_DOWN register (at offset 0x103428),
an d vi ce v er s a .
Figure 21-1. Power down register BLOCK_POWER_ DOWN
SPDO
DVDD
AO AI
EVO VI
31 03192327
SSI
VLD
1115
BLOCK_POWER_DOWN (r/w)
MMIO_base
offset:
0x10 3428
ICP
PRELIMINARY SPECIFICATION 22-1
PCI-XIO External I/O Bus Chapter 22
By David Wyland
22.1 SUMMARY FUNCTIONALITY
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX 1300 PCI-XIO bus allows glueless connection
to PCI peripherals, 8-bit microprocessor peripherals and
8-bit memory devices. All these device types can be in-
termixed in a single PNX1300 system.
The PCI-XIO bus provides the following features:
•All PC I 2.1 featur e s (32-bit, 33 M H z )
•Simple, non-multiplexed, 8-bit data, 24-bit address
XIO bus with control signals for 68K and x86 style
devices
•Glueless connection to ROM, EPROM, flash
EEPROM, UARTs , SRAM, etc.
•Programmable inter nal or exter nal bus clock source
•0-7 programm able wait states for XIO devices
•Suppor t for single byte read, single byt e write, DMA
read or DMA write
•The 16 MB of XIO device space is visible as 16
MWords (64 MBytes) in the D SPCPU memory map
22.1.1 Description
Th e XIO logic that impl eme nts th e pro toc ol fo r 8 -bit de -
vices ap pears as a on- chip PCI target device to the rest
of the PNX1300. It only responds when it is addressed by
the PNX1300 as initiator and never responds to external
PCI ma sters . W hen i t is addr esse d by the PNX1 300 as
an initiator, it responds to the PNX1300 PCI BIU as a nor-
mal slave de vice , activatin g PCI_ DEVSE L# .
The XIO logi c serves as a brid ge between the PCI bus
an d XI O devices such as ROM s, flash EPROM s and I/ O
device chips. The PNX1300 addresses XIO devices on
the PCI-XIO bus in the same way as registers or memory
in a ny oth er P CI slave devi ce . The X I O l og ic sup pl i es th e
PCI_TRDY# signals to the PCI bus and also supplies the
chip-select, read, write and data-strobe signals to XIO
devic es atta ched to the PCI-XIO Bus . A concep tual only
block diagram of the PCI-XIO Bus is shown in
Figure 22-2. The real hardware uses the PCI_AD[0:30]
signals and PCI_C/BE#[0:3] signals for both PCI and
XIO devices, as shown in Figure 22-3.
The XIO logic is activated when the Enable bit in the
XIO_CTL register is asserted and whenever the
PNX1300 (as initiator) addresses the PCI-XIO bus ad-
dress range, as defined by a 6-bit address field in the XIO
Bus Control Register. This 6-bit field defines the 6 most
signif icant bits of the XIO Bus address space. When the
PNX1300 sends out an address as an initiator, the upper
6 bit s of th e ad dr e s s ar e c om pa red w ith th is f ield. If t h ey
match, the PCI-XIO bus logic is activated. The
PCI_INTB# output is asserted to indicate that the PCI-
XIO Bu s is ac tive. It beco mes acti ve at PC I data p hase
time. When XIO is enabled, the PCI_INTB# signal be-
comes dedicated as XIO bus chip-select, and turns from
an open-drain output into a normal logic output.
PCI_INTB# serves as a global chip select for all XIO Bus
chips. When XIO is disabled, PCI_INTB# is available for
PCI-s peci fic use or as a gene ral pu rpos e sof twa re I/ O pin
with open-drain behavior as in TM-1000.
The Address field bits in the XIO Bus Control register
se rv e a s a base ad dress r e gis ter in P CI t erm s . The XI O
Bus Control register is not a PCI conf iguration regist er. It
does not need to be a PCI configuration register because
the PCI-XIO Bus can only be addressed by the
PNX1300. It will not respond to requests by any other ex-
ternal PCI device.
When the XIO-PCI Bus controller logic is activated, it
generates PCI_DEVSEL# as a response to the PCI bus.
When PCI_IRDY# has been received from the BIU, it as-
serts an external PCI_INTB# signal as the global chip se-
lect. It also reconfi gures the PCI address/data pins for 8-
bit byte transfer s. When the PCI-XIO Bus is active, the
lower 24 bits of the external 32-bit PCI bus are used to
output a 24-bit address for all transfers, read or write.
The upper 8 bits of the external PCI bus are unchanged
and transfer data normally. This is shown in Figure 22-3.
Th e 24-bi t ad dress on the XI O Bus pi ns is th e wor d ad-
dress for the PCI transfer, which is the lower 26 bits of
the PCI transfer address with the two least significant bits
ignored. One word is transf erred to or f rom the PCI bu s
for each by te read or writ ten on the XIO bus . In writes to
the XIO bus, a 32-bit word is transferred from the PCI
BIU to the XIO Bus co ntrol ler, but the lower 24 bits and
th e PC I byte enables are igno r ed. In read s fro m th e P CI
bus , a 3 2-bit word is tra nsfe rre d fr om th e XIO Bus c on-
troller to the PCI BIU with the data in the upper 8 bits and
the 24-bit address in the lower 24 bits. Note that the 24-
bit address returned in a read is the lower 26 bits of the
PCI transfer address with the two least significant bits
truncated. For example, a PCI transfer address of 44
hexadecimal would return a value of 11 hexadecimal as
th e lower 24 bits of the 3 2 -bit data in a rea d. The 24-bit
XIO Bus address is generated by an address counter in
the XIO Bus controller. This counter is loaded with the
PCI word address at PCI frame time at the start of the
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-2 PRELIMINARY SPECIFICATION
PC I transfer and is inc remented for each PCI word trans-
ferred.
The XIO Bus does not generate parity during XIO Bus
wri te transf ers o r chec k pari ty duri ng XIO Bu s read tr ans-
fers. This allows the XIO Bus to interface to standar d 8-
bit devices wit hout having to add parity-generation and
check logic. While the XIO Bus is active, the XIO Bus log-
ic inhibits parity checking and drives the PCI Parity and
Parity Error p in s so t ha t th ey do no t floa t.
Word tran sfer is used t o tran sfer th e bytes to an d from
the PCI bus for hardware simplicity. The primary intend-
ed use of the PCI-XIO Bus is for slow devices, ROMs,
fla sh EP ROM s and I /O. Beca us e the PC I-XI O bus i s so
muc h sl owe r th an th e PN X130 0, th ere is ti me a vail able
for the PNX1300 to pack and unpa ck the words. In the
case of ROMs and flash EPROMs, t he data is typically
compressed, requiring the PNX1300 CPU to both un-
pack and decompress the data.
Th e PC I-X IO B us C ont rol ler l ogi c re con figur es the byte
enables as control signals for the attached XIO Bus chips
dur in g XI O Bus tr an s fer s . It als o dr iv es th e PC I_TR D Y#
signal to the PCI Bus for each transfer. The PCI Bus byte
enables a r e reconfigured to generate XIO Bus timing s ig-
nals: Read (IORD), Write (IOWR) and Data Strobe (DS).
These signals al low ROM, flash EPR OM, 68K and x86
devices to be glu eless ly interfaced t o the XIO Bus. Fo r a
single device, the PCI_INTB# line is used as the glob al
Audio In
Audio Out
DSPCPU
400 MIPS
2.5 GOPS
I$
D$
I2C Interface
Image
Co Processor
PNX1300
MMI
PCI an d Exter n a l I/O ( PC I- XIO) B us I n t e rfa c e
VLD Assist
Video Out
Digital
DMSD
or Raw
Video
Serial
Digital
Audio
JTAG
XIO Bus PCI - XIO Bus AD[31:0]
SDRAM: 32-bit data
SDRAM
Highway
Synchronous
Video In
Glueless
Flash
EPROM I/F
XIO
I/O Device PCI
I/O Device
Clock
Camera
I2C Bus
CCIR 601
Digital
Vi deo Out
V.34 Modem
Controls PCI B us
Controls
Serial I/ F
Figure 22-1. Partia l PNX 1300 chip bl ock diagr am
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-3
chip enable. If more than one device is to be added, an
external decoder, such as a 74FCT138, can be used to
dec ode the up pe r bi ts of t he 24-bi t tra nsfer ad dr ess , wit h
the PCI_INTB# line used as a global chip enable to the
decoder.
The PCI - XIO B us controller has a wai t state generator to
pr ovi d e timi ng for sl ow de vi ces . The wa it stat e ge ner ator
allows the addition of up to 7 wait states for slow chip ac-
c ess a nd wr it e t ime s. The wai t sta te ge ne rat or lo gi c ge n-
era tes the P CI_TR D Y# sign al to the P CI bus .
The XIO Bus controller contains a clock generator for
standalone systems. The PCI-XIO Bus uses the PCI
clock. This clock is normally supplied by a PCI Bus cen-
tr al resou r ce o u t sid e th e PNX 1 300 chi p. In standalone or
low-cost systems, the internal clock generator can be
used. The internal clock generator divides t he PNX1300
highway clock by a 5-bit number in a prescaler. This al-
low s sett in g bus c lock s fr om 4 MHz t o 66 M Hz in a 1 33
MH z s y stem . T h e inter n al clo ck ge ner a tor pr o gr a m mi ng
is described in Sec tio n 22.5 , “XIO_CTL MMI O Register.”
22.2 BLOCK DIAGRAM
Figure 22-2 shows a conceptual block diagram of the
PCI-XIO Bus as a slave device on the PCI Bus. The XIO
Bus Controller generates an XIO Bus, which is an 8-bit
bus with a 24-bit address. Devices attached to the XIO
Bus appear as memory locations in the 16 MB address
space of the XIO Bus.
Figure 22-3 shows an implementation block diagram of
the PCI_XIO Bus. To conserve pins, the XIO Bus Con-
troller uses the PCI I/O pins as XIO Bus pins during XIO
Bus data transfers. It reconfigures the 32 PCI address/
data pins as 8 XIO Bus data pins and 24 XIO Bus ad-
dress pins, and it reconfigures the byte enable pins as
XIO Bus timing signals. By changing th e fu nctions of the
pi ns du ring the tran sf er, 3 6 pin s are sa ve d whic h wou ld
ot herw ise be r equ ire d to d rive th e XI O Bu s de vice s. By
rec o nfi gur in g th e P CI pins on ly d uring the data phase of
the XIO Bus t ransf ers, the PCI-XI O bus retains its PCI
Bus compatibility.
Figure 22-4 shows a more detailed block diagram of the
PCI-X IO Bus control ler.
PNX1300 SDRAM Data Highway
PCI
Bus
Interface
Unit (BIU)
PCI Bus
XIO Bus
Controller
PCI Device
PCI
Device PCI
Device PCI
Host
ROMx86
Device
PNX1300
8-bit data + 24-bit addres ses
XIO Bus
Figure 22-2. PCI-XIO bus device CONCEPTUAL block diagram
for address & data, these use the same pins/wires
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-4 PRELIMINARY SPECIFICATION
PNX1300 SDRAM Data Highway
PCI
Bus
Interface
Unit (BIU)
PCI Bus
XIO Bus
Controller
PCI D e vice
PCI
Device PCI
Device PCI
Host
ROM x86
Device
etc.
PNX1300
Mux
PCI_INTB#
PCI_IN TB# = XIO Bus Activ e As Target
PCI_AD[23:0]
PCI_AD[31:24] PCI_AD[31:24]
PCI_AD[31:0] PCI_AD[31:0] PCI_AD[31:0]
XIO Bus
Figure 22-3. PCI-XIO Bus device implementation block diagram
PNX1300 SDRAM Data Highway
XIO Config Reg Clock
Bus Timing
PCI
Bus
Interface
PCI_AD[31:24]
PCI_C/BE0#: IORD#
PCI_CLK
PCI-XIO Bus Controller
Unit (BIU)
=
Mux
Da ta O ut [31:2 4 ]
Da ta In [31: 0]
Data Ou t [23: 0]
Address [23:0]
PCI_AD[23:00]
Add r es s [31:24]
PCI_INTA#, INTC#, INTD#
PCI_C/BE1#: IOWR#
C/BE
TRDY XIO Controls
+ Wait States
PCI_INTB# = Chip Enable
PCI Controls: Fram e, etc.
PCI_TRDY#
PCI_DEVSEL#
OROR
DEVSEL
PCI_REQ#
PCI_GNT#
Ti e RE Q to G N T for stan d al one (no ho s t) cas e
PNX1300 Initiator
PCI_C/BE2#: DS#
PCI_C/BE3#
Figure 22-4. PCI-XIO Bus interface controller block diagram
PCI-XIO Bus
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-5
22.3 DATA FORMATS
The dat a t ran sf er f orm at s f or t h e PCI - XIO b us are s ho wn
in Figure 22-5. The 8-bit data field is the data transferred
to or fro m th e P CI- XIO Bu s. T h e read ad dr e s s is th e 24-
bit address on the P CI-XIO Bus address lines when the
read transfer takes place.
22.4 INTERFACE
22.4.1 PCI-XIO Bus Interface Design
The PCI-X IO Bus can accomm odate a va ri ety of dif fere nt
devices and bus protocols. The f ollowing are examples
of de vices interfaced to the PCI-XIO Bus.
Data Read Address
UnusedData
Read : XIO Bus to PCI
Write: PCI to XIO Bus
31 24 23 0
31 24 23 0
Figure 22-5. PCI-XIO Bus data formats
Table 2 2-1. PCI-XIO B us s ignal definitions
PNX1300 PCI Signal Pins I/O PCI Function XIO Function
PCI_IN TB# 1 O PCI-XIO B us Enable = XIO Bus Ac ti ve As Targ et Device
PCI_AD[23:0] 24 I/O PCI Address/Data Address bus: 16 MB
PCI_AD[31:24] 8 I/O Data bus: 8 bits
PCI_PAR 1 O Even Parity f or AD & C/BE
PCI_C/BE0# 1 Command/Byte Enables
On XIO read, BE[3:0] = 0110b’4
On XIO write, BE[3:0] = 0111b’4
I ORD# = Read Enable
PCI_C/BE1# 1 IOWR# = Write Enable
PCI_C/BE2# 1 D S# = Data Strobe
PCI_C/BE3# 1 unused
PCI_CLK 1 I/O 33 MHz PCI Clock: can optionally be generated by PNX1300 on board osc
PCI_FRAME# 1 I/O PCI Address/Command Strobe + Transfer In Progress
PCI_DEVSEL# 1 I/O Device Select Valid Asserted by PNX1300 = XIO Active
PCI_IRDY # 1 I/O Initiator Ready = Transfer In Progr ess
PCI_TRDY# 1 I/O Target Ready Asserted by PNX1300 = XIO Transfer Timing
PCI_STOP# 1 I/O Target Requests Stop of Transaction
PCI_IDSEL# 1 I Chip Select for PCI Config Writes
PCI_REQ# 1 O PNX1300 Requesting PCI Bus
PCI_GNT# 1 I PNX1300 Is Granted PCI Bus
PCI_PERR# 1 I Parity Er ro r to PNX1300
PCI_SERR 1 O System Err or from PNX 1300
PCI_INTA# 1 I/O General Pur po se I/O
PCI_IN TB# 1 I/O Gen eral Pu r pose I/O XIO Bus Active = Global C hi p Select
PCI_INT C# 1 I/O General Pu r po se I/O
PCI_INT D# 1 I/O General Pu r po se I/O
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-6 PRELIMINARY SPECIFICATION
22.4.1.1 Flash EEPROM
Figure 22-6 show s a n 8 - b it flash EE P R O M inte r fa c ed to
the PCI-XIO Bus. Examples of these devices are the Mi-
cron MT28F200C1 and the AMD 29LV400.
22.4.1.2 6 8K Bus I/O device
Figure 22-7 sho ws a 68K bus I/O device interfaced to the
PCI-XIO Bus. Example devices are the Motorola
MC68HC681 DUART and the MC68HC901 Multi-Func-
tion Per ipheral.
22.4.1.3 x86/ISA Bus I/O device
Figure 22-8 shows an x86 or ISA bus I/O device inter-
fac ed to th e PC I-XI O Bu s. An examp le de vice i s th e I nte l
82091 A dv a nc ed In t e gra t e d Periph er a l (A IP) .
22.4.1.4 Multiple Flash EEPROM
Figure 22-9 shows two 8-bit flash EEPROMs interfaced
to the PCI-XIO Bus. A 74FCT138 logic chip decodes up-
per bi ts P CI_AD[19-17] of the XIO bus address to gener-
ate the chip selects for the two EEPROMs. These bits
dec ode t he add ress sp ace in to bloc ks of 128 KB. The ad-
dress range of each enable is shown on the enable lines.
Si x spare c hip se lects a re av ailable fo r attachin g up to six
more EEPROMs or to attach other devices. The
74F C T138 pro vi des b oth d ecode of the ad dr e ss b its an d
th e AND f un ctio n for the P CI_I NTB # gl obal chip en able
Address
PCI_AD[16:0]
W rite Enable
PCI_C /BE1 #: IOWR#
Output Enable
PCI_C /BE0 #: IO RD#
Ch ip Selec t
PCI_INTB#
Data PCI_AD[31:24]
128K x 8 EE PROM
Figure 22-6. 8-bit Flash EEPROM Interface
Address
PCI_AD[23:0]
R/W#
P CI_ C/BE1#: IOWR#
DS#PCI_C/BE2: DS#
C hip Sele ct
PCI_INTB#
Data PCI_AD[31:24]
68K Bus Device
CLK
PCI_CLK
F igur e 2 2- 7 . 8-bi t 6 8K B us D ev ice Int e r fac e
Address
PCI_AD[23:0]
I /O Read E nable
PCI_C/BE0#: IORD#
I/ O Write E nablePCI_C/BE1#: IOWR#
Ch ip Sele ct
PCI_INTB#
Data PCI_AD[31:24]
x8 6 or I SA Bu s Devi ce
BALE
PCI_CLK
Figure 22-8. 8 -bit x86 / ISA Bus Dev ice interface
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-7
signal so that only one EEPROM chip enable signal is
active at global chip enable time.
22. 5 XIO_ CTL M MIO REGISTER
The PCI -X IO B us Co nt rol l er has one prog ramm er visi bl e
MMIO register: XIO_CTL. Its format is shown in
Table 22-2. T o ens ure c ompati bilit y wi th futur e devi ces ,
any undefined M MIO bi t s shou ld be ig nor e d w h en re a d,
and w r itt en as ‘0’s.
22.5.1 PCI_CLK Bus Clock Fr equency
PCI_CLK, the clock for the PCI and PCI-XIO bus can be
supplied externally or internally. This is determined at
boot time, by the ‘enabl e int ernal PCI_ CLK gene rator ’ bit,
bit 6 of byte 9 in the boot EEPROM. Refer to S ectio n 13. 2
on page 13-2. I f th is bit = ‘0’, PCI_CLK acts compatible
with TM-1000 and normal PCI operation, i.e. PCI_CLK is
an input pin that takes the PCI clock from the external
worl d. If th is bi t = ‘1’, an on-chip clock divider in the XIO
logic becomes the source of PCI_CLK, and the PCI_CLK
pin is configured as an output. In the latter case, the
PCI_CLK frequency can be programmed to a divi der of
the PNX1300 highway clock by setting the XIO_CTL reg-
ister ‘Clock Frequency’ divider value.
Table 22-2. XIO_CTL Register Fields: MMIO Address
0x10 3060
Field Bit s Func tion R eset Va lue
Addr ess 31:26 X IO addres s space undef ined
25:11 unused 0
Wait States 10:8 Wait states 0
Enable 7 Enable XIO Bus opera-
tion 0 = disabled
6:5 unused
Clock Fre-
quency 4: 0 Cl o ck d ivid e r 0x1 f
Address
PCI_AD[16:0]
W rite Enable
PCI_C/BE1#: IOWR#
Output EnablePCI_C/BE0#: IORD#
Ch ip Selec t
PCI_INTB#
Data
PCI_AD[31:24]
128Kx8 EEPROM
Address
W rite Enable
Output Enable
Ch ip Selec t
Data
74FCT138
A[2-0] O0
O1
O2
O3
O4
O5
O6
O7
E0
E1
E2
+3
PCI_AD[19-17] 0-128K
128-256K
256-384K
384-512K
512-640K
640-768K
768-896K
896-1024K
128Kx 8 EEPROM
Figure 22-9. Multiple 8-bit Flash EEPROM Interface
Table 22-3. PCI_CLK frequencies for 133.0 MHz
PNX1300 highway clock
Clock
Frequency
(use odd
values)
PNX1300
Clocks PCI -XI O Clo ck
Pe ri od , n s Frequency,
MHz
0 illegal illegal illegal
1 2 15 66.5
2 3 22.5 44.33
3 4 30 33.25
... ... ... ...
30 31 233 4.29
31 32 241 4.16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-8 PRELIMINARY SPECIFICATION
A table of PCI-XIO Bus Clock frequencies versus Clock
field values is shown in Table 22-3. Note that the
PCI_CLK operating frequency should be set to observe
the fr eque nc y l im it s g i ven in th e A C/ DC timi ng char act er -
ization data for PNX1300. Odd values of ‘Cl oc k Fr eq uen-
cy’ are re commende d, re sulti ng in an eve n divider , which
gener ates a 50% duty c y cle P C I_ C L K.
22. 5 .2 Wa it S t ate Ge n era t o r
Th e XIO Bu s co ntroll er has an au tomatic wait state g en -
erator to allow for re ad and write cycle times of devices
on t h e X IO b us.
22.6 PCI-XIO BUS TIMING
The timing for the PCI-XIO bus is shown below: Note that
the ‘fat’ lines indicate active drive by PNX1300. Thin lines
ind icat e areas where the PNX1 300 is no t active ly dr ivin g.
(I n thes e areas, pull-up resis tor s retai n the signal hi gh for
control signals, PCI_AD lines are left floating.)
Figure 22-10 shows the timing for a single byte read
transfer. Figure 22-11 shows the ti mi ng for a s in gl e by te
read transfer with wait states. Figure 22-14 shows the
timing for a DMA burst read transfer of 2 bytes, and
Figure 22-16 shows the timing for a DMA burst write
transfer of 2 bytes. The DMA burst tr an sfers are shown
a t m ax im u m r a te , wit h z e ro wai t sta te s . DM A b u rst tr an s-
fers with wait states insert wait states between the trans-
fer s. In th e read case, the IO RD# en able an d DS# are e x-
tended by the wait states. In the write case, the IOWR#
enable and DS# are delayed by the wait states.
Table 22-4. W a it state generator codes
Code Wait States
00
11
22
... ...
77
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame Time Bus Turnar oun d XIO Transfer
Figure 22-10. PCI-XIO Bus timing: single byte read, 0 wait states
& Ad dres s Set up
PCI_AD [23:0]: A DDR XIO Add r sPCI Address
PCI_AD[31:24]: DATA Read Data
PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Samp le Poi nt
Bus Idle
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-9
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Fr ame Time Bus Turnaround Wait (k times)
Figure 22-11. PCI-XIO Bus timing: single byte read, 1 or more wait states
& Add re ss Setu p
PCI_AD[23:0]: ADDR XIO AddrsPCI Address
PCI_AD[31:24]: DATA Read Data
PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Samp le Poi nt
XIO transfer
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame Time Write Cycle Data hold time
Figure 22-12. PC I-XIO Bus t iming: single byte write, 0 wait state s
PCI_AD[23:0]: ADDR XIO Add r sPCI Address
PCI_AD[31:24]: DATA PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Bus Idle
XIO Data
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-10 PRELIMINARY SPECIFICATION
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Fr ame Time
Figure 22-13. PC I-XIO Bus t iming: single byte write, 1 or m or e wait states
Wri te cycle
PCI _ AD [ 23 : 0]: A D DR XIO Ad drsPCI Address
PCI_AD[31:24]: DATA PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Data Hold time
XIO Data
Wait (k) Bus Idle
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Fr ame Time Bus Turnaround XIO D at a 1
Figure 22-14. PC I-XIO Bus t iming: DMA burst read, 2 bytes, 0 w ait states
& Add re ss Setu p
PCI _ AD [ 23 : 0]: A D DR XIO Addrs 1PCI Address
PCI_AD[31:24]: DATA Read Data 2
PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Sample Points
XIO Da t a 2 Bus Idle
XIO Ad drs 2
Read Data 1
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-11
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 22-15. PCI-XIO Bus timing: DM A bur st read, 2 bytes, 1 or more wait sta tes
PCI_AD[23:0]: ADDR XI O Ad drs 1PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
Read Sample Points
Read Data 1
wait(k) data 1 wait(k ) data 2
XIO Ad drs 2
Read Data 2
Frame Turn
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 22-16. PCI-XIO Bus timing: DM A bur st write, 2 bytes, 1 or more wait states
PCI _ AD [ 23 : 0]: A D DR PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
wait(k) hold data2 wait(k)
XIO Add r s 1
Frame data1
XIO Addr s 2
hold idle
XIO Data1 XIO Da ta 2
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-12 PRELIMINARY SPECIFICATION
22.7 PCI-XIO BUS CONTROLLER
O PER ATI ON AND P ROG RAMM ING
The PCI-XIO Bus is a PCI target device. All valid PCI
transfers with PNX1300 as the initiator are allowed, in-
cluding single word and DMA transfers. When data is
re ad from t he PCI -XI O B us, it read s a s a 32 -bi t wo r d wi t h
the 8 bits of dat a as th e mos t sign if ic ant byt e a nd the 24-
bit XIO Bus transfer address as the least significant
by tes. When data is w ritten to t he P CI-XIO Bus, it is wr it -
ten as a word, but only the mo st significa nt byte of the
data is transferred to the bus. The lower 24 bits are ig-
nored as they are replaced by the lower 24 bits of the
transfer address before being placed on the bus.
Before the PC I-XIO B us can be used, th e PCI- XIO Bus
Control Register must be set up. This register must be
loaded with the base address for the PCI-XIO bus and
the control fields for clock frequency, wait states per
transfer and PCI-XIO Bus enable.
To r e ad a single byt e to a P CI -XI O Bus dev i ce, fi r s t de-
fin e the 24 -bi t addr ess f or th e devi ce . This m ig ht be the
address in an EPROM for the desired byte. Multiply this
device address by four to convert it to a word address
and ad d the XIO Bus base address. The combined ad -
dress is the PCI transfer address. Use this address as
the transfer address for a single word DSPCPU load.
Table 22-5 shows examples of this address conversion.
At the completion of the load, the data rece ived wil l con-
sist of 8 bits of data and the 24-bit device address. To
writ e a by te, us e the s ame t ran sfer ad dr ess a nd wri te a
word to th is address with the desired data as the most
s ignifi c ant byte of the word wri tten.
To transfer data between the XIO-PCI bus and the
SDRAM using the PCI DMA capability, set the
SRC_ADR or the DEST_ADR register to the PCI-XIO
Bu s tr ansf er a ddres s, de pe ndin g on the di rec tion of t he
trans fer. The PC I-XIO Bu s tr an s fer a d dress is four tim es
the starting address as seen on the PCI-XIO Bus ad-
dr ess pi ns pl us th e PCI-X IO Bus c ontro ller bas e addre ss.
Thi s i s th e star t ing ad d res s fo r the PCI -XI O Bu s tran sf er.
Set the ot her address, destination or source, to the de-
sired starting address in SDRAM. Set the
PCI_DMA_CTL register for the desired direction and set
the transfer count to the four times number of PCI-XIO
Bus bytes to be transferred. The transfer count is four
time s the PC I-XIO Bus b yt es to be tra nsferre d becau se
the PCI-XI O Bus transfe rs one word to or from the PCI
bus for each byte transferred to or fr om devices on the
PCI-X IO Bus.
Word tran sfer is used to transfer th e bytes to and fr om
the PCI bus for hardware simplicity. Additional hardware
could be ad ded to pa ck an d un pac k by tes , but this i s an
unnecessary complication given the speed of the PCI-
XIO Bus relative to the speed of the PNX1300 bus and
CPU. The primary intended use of the PCI-XIO Bus is for
ROMs, flash EPROMs and I/O devices. Because the
PCI-XIO bus is so much slower than the PNX1300, there
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 22-17. PC I-XIO Bus t iming: DMA burst w rite, 2 bytes, 0 wait states
PCI_AD[23:0]: ADDR PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
hold data 2 hold bus idle
XIO Addrs 1
Frame data1
XIO Addrs 2
XIO Data 1 XIO Data 2
Table 22-5. PCI to XIO Bus address conversion
examples
XIO Bus
Address
in Hex
PCI Word
Address
in Hex
XIO-PCI
Base
Address
in Hex
PCI Tr ansfer
Address
in Hex
11 44 5800 0000 5800 0044
0123 048C 5800 0000 5800 048C
11 0012 44 0048 5800 0000 5844 0048
Philips Semiconductors PCI-XIO External I/O Bus
PRELIMINARY SPECIFICATION 22-13
is tim e avai labl e fo r th e PN X1300 t o pac k and u npack the
words. At three PCI-XIO bus wait states, at least 120
nanoseconds are required for each byte transferred. This
corresponds to 12 CPU instructions at 100 MHz. The
CPU may need to process each byte of data anyway. In
the case o f ROMs an d fla sh EPRO Ms, th e dat a is typica l-
ly comp r essed, requ i ri ng the PN X 1 300 C P U to bo t h un-
pack and decompress the data.
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
22-14 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION A-1
PNX1300/01/02/11 DSPCPU Operations Appendix A
by Ge rt Slavenburg, M arc el Janssens
A.1 ALPHABETIC OPERATION LIST
The f ollowing table lists the complete operation set of PNX1300’s DSPCPU. No te that t his is not an inst ruction list ; a
DSPCPU instruction contains from one to five of these operations.
Aalloc............................4
allocd..........................5
allocr...........................6
allocx..........................7
asl...............................8
asli..............................9
asr............................10
asri ...........................11
Bbitand........................12
bitandinv...................13
bitinv.........................14
bitor ..........................15
bitxor.........................16
borrow ......................17
Ccarry.........................18
curcycles ..................19
cycles .......................20
Ddcb............................21
dinvalid .....................22
dspiabs.....................23
dspiadd.....................24
dspidualabs..............25
dspidualadd..............26
dspidualmul..............27
dspidualsub..............28
dspimul.....................29
dspisub.....................30
dspuadd....................31
dspumul....................32
dspuquadaddui.........33
dspusub....................34
dualasr......................35
dualiclipi....................36
dualuclipi ..................37
Ffabsval......................38
fabsvalflags...............39
fadd ..........................40
faddflags...................41
fdiv............................42
fdivflags....................43
feql............................44
feqlflags....................45
fgeq ..........................46
fgeqflags...................47
fgtr............................48
fgtrflags.....................49
fleq............................50
fleqflags....................51
fles............................52
flesflags....................53
fmul...........................54
fmulflags...................55
fneq..........................56
fneqflags...................57
fsign..........................58
fsignflags..................59
fsqrt..........................60
fsqrtflags...................61
fsub...........................62
fsubflags...................63
funshift1....................64
funshift2....................65
funshift3....................66
Hh_dspiabs.................67
h_dspidualabs ..........68
h_iabs.......................69
h_st16d.....................70
h_st32d.....................71
h_st8d.......................72
hicycles.....................73
Iiabs...........................74
iadd...........................75
iaddi..........................76
iavgonep...................77
ibytesel .....................78
iclipi ..........................79
iclr.............................80
ident..........................81
ieql............................82
ieqli...........................83
ifir16..........................84
ifir8ii..........................85
ifir8ui.........................86
ifixieee......................87
ifixieeeflags...............88
ifixrz..........................89
ifixrzflags ..................90
iflip............................91
ifloat..........................92
ifloatflags..................93
ifloatrz.......................94
ifloatrzflags...............95
igeq...........................96
igeqi..........................97
igtr ............................98
igtri ...........................99
iimm........................100
ijmpf........................101
ijmpi........................102
ijmpt........................103
ild16........................104
ild16d......................105
ild16r.......................106
ild16x......................107
ild8..........................108
ild8d........................109
ild8r.........................110
ileq..........................111
ileqi.........................112
iles..........................113
ilesi.........................114
imax........................115
imin.........................116
imul.........................117
imulm......................118
ineg.........................119
ineq.........................120
ineqi........................121
inonzero..................122
isub.........................123
isubi........................124
izero........................125
Jjmpf.........................126
jmpi.........................127
jmpt.........................128
Lld32.........................129
ld32d.......................130
ld32r .......................131
ld32x.......................132
lsl............................133
lsli...........................134
lsr............................135
lsri...........................136
Mmergedual16lsb......137
mergelsb.................138
mergemsb ..............139
Nnop.........................140
Ppack16lsb...............141
pack16msb.............142
packbytes ...............143
pref.........................144
pref16x ...................145
pref32x ...................146
prefd.......................147
prefr........................148
Qquadavg..................149
quadumax...............150
quadumin................151
quadumulmsb.........152
Rrdstatus...................153
rdtag.......................154
readdpc ..................155
readpcsw................156
readspc...................157
rol ...........................158
roli...........................159
Ssex16......................160
sex8........................161
st16.........................162
st16d.......................163
st32.........................164
st32d.......................165
st8...........................166
st8d.........................167
Uubytesel..................168
uclipi.......................169
uclipu......................170
ueql.........................171
ueqli........................172
ufir16 ......................173
ufir8uu....................174
ufixieee...................175
ufixieeeflags...........176
ufixrz.......................177
ufixrzflags...............178
ufloat.......................179
ufloatflags...............180
ufloatrz....................181
ufloatrzflags............182
ugeq.......................183
ugeqi.......................184
ugtr.........................185
ugtri........................186
uimm.......................187
uld16.......................188
uld16d.....................189
uld16r .....................190
uld16x.....................191
uld8.........................192
uld8d.......................193
uld8r .......................194
uleq.........................195
uleqi........................196
ules.........................197
ulesi........................198
ume8ii.....................199
ume8uu ..................200
umin........................201
umul........................202
umulm.....................203
uneq.......................204
uneqi.......................205
Wwritedpc..................206
writepcsw................207
writespc..................208
Zzex16......................209
zex8........................210
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-2 PRELIMINARY SPECIFICATION
A.2 OPERATION LIST BY FUNCTION
Load/Store Operations
alloc............................4
allocd..........................5
allocr...........................6
allocx..........................7
h_st16d.....................70
h_st32d.....................71
h_st8d.......................72
ild16........................104
ild16d......................105
ild16r.......................106
ild16x......................107
ild8..........................108
ild8d........................109
ild8r.........................110
ld32.........................129
ld32d.......................130
ld32r .......................131
ld32x.......................132
pref.........................144
pref16x ...................145
pref32x ...................146
prefd.......................147
prefr........................148
st16.........................162
st16d.......................163
st32.........................164
st32d.......................165
st8...........................166
st8d.........................167
uld16.......................188
uld16d.....................189
uld16r .....................190
uld16x.....................191
uld8.........................192
uld8d.......................193
uld8r .......................194
Shift Operations
asl...............................8
asli..............................9
asr............................10
asri ...........................11
funshift1....................64
funshift2....................65
funshift3....................66
lsl............................133
lsli...........................134
lsr............................135
lsri...........................136
rol ...........................158
roli...........................159
Logical Operations
bitand........................12
bitandinv...................13
bitinv.........................14
bitor ..........................15
bitxor.........................16
DSP Operations
dspiabs.....................23
dspiadd.....................24
dspidualabs..............25
dspidualadd..............26
dspidualmul..............27
dspidualsub ..............28
dspimul.....................29
dspisub.....................30
dspuadd....................31
dspumul....................32
dspuquadaddui.........33
dspusub....................34
dualasr......................35
dualiclipi....................36
dualuclipi ..................37
h_dspiabs.................67
h_dspidualabs ..........68
iclipi ..........................79
ifir16..........................84
ifir8ii..........................85
ifir8ui.........................86
iflip............................91
imax........................115
imin.........................116
quadavg..................149
quadumax...............150
quadumin................151
quadumulmsb.........152
uclipi .......................169
uclipu......................170
ufir16 ......................173
ufir8uu ....................174
ume8ii.....................199
ume8uu ..................200
umin........................201
Floating-P oint Arithmetic
fabsval......................38
fabsvalflags...............39
fadd ..........................40
faddflags...................41
fdiv............................42
fdivflags....................43
fmul...........................54
fmulflags...................55
fsign..........................58
fsignflags..................59
fsqrt..........................60
fsqrtflags...................61
fsub...........................62
fsubflags...................63
Floating-P oint Conversion
ifixieee......................87
ifixieeeflags...............88
ifixrz..........................89
ifixrzflags ..................90
ifloat..........................92
ifloatflags..................93
ifloatrz.......................94
ifloatrzflags...............95
ufixieee...................175
ufixieeeflags ...........176
ufixrz.......................177
ufixrzflags...............178
ufloat.......................179
ufloatflags...............180
ufloatrz....................181
ufloatrzflags............182
Floating-P oint R elationals
feql............................44
feqlflags....................45
fgeq ..........................46
fgeqflags...................47
fgtr............................48
fgtrflags.....................49
fleq............................50
fleqflags....................51
fles............................52
flesflags....................53
fneq ..........................56
fneqflags...................57
Integer Arithmetic
borrow ......................17
carry.........................18
h_iabs.......................69
iabs...........................74
iadd...........................75
iaddi..........................76
iavgonep...................77
ident..........................81
imul.........................117
imulm......................118
ineg.........................119
inonzero..................122
isub.........................123
isubi........................124
izero........................125
umul........................202
umulm.....................203
Immediate Operations
iimm........................100
uimm.......................187
Sign/Zero Extend Ops
sex16......................160
sex8........................161
zex16......................209
zex8........................210
Integer Relationals
ieql............................82
ieqli...........................83
igeq...........................96
igeqi..........................97
igtr ............................98
igtri ...........................99
ileq..........................111
ileqi.........................112
iles..........................113
ilesi.........................114
ineq.........................120
ineqi........................121
ueql.........................171
ueqli........................172
ugeq.......................183
ugeqi.......................184
ugtr.........................185
ugtri........................186
uleq.........................195
uleqi........................196
ules.........................197
ulesi........................198
uneq.......................204
uneqi.......................205
Control-Flow Operations
ijmpf........................101
ijmpi........................102
ijmpt........................103
jmpf.........................126
jmpi.........................127
jmpt.........................128
Specia l-Register Ops
cycles .......................20
curcycles..................19
hicycles.....................73
nop.........................140
readdpc ..................155
readpcsw................156
readspc...................157
writedpc..................206
writepcsw................207
writespc..................208
Cache Operations
dcb............................21
dinvalid .....................22
iclr.............................80
rdstatus...................153
rdtag.......................154
Pack/Merge/Select Ops
ibytesel.....................78
mergedual16lsb......137
mergelsb.................138
mergemsb..............139
pack16lsb...............141
pack16msb.............142
packbytes...............143
ubytesel..................168
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-3 PRELIMINARY SPECIFICATION
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-4
Allocate a cache block
pseudo-op for allo cd(0)
SYNTAX
[ IF rguard ] alloc(d) rsrc1
FUNCTION
if rguard then {
cac he_block_mask = ~(cache_block_size -1)]
allocate adata cache block with [(rsrc1 + 0) & cache_block_mask] address
}
ATTRIBUTES
Function unit dmemspec
Operation code 213
Nu mber of operands 1
Modifier -
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
Th e a ll oc op eration i s a pse ud o op er at ion tr a ns form ed by th e s c hedu ler into an al locd ( 0) w ith th e s am e argum e nt s .
(N ote: pseudo oper ations cannot be use d in ass embly fi le s. )
The alloc operation allocate a cache block with the address computed from [(rsrc1 + 0) & cache_block_mask] and sets
th e stat us of t his cac he block as vali d. No data i s fe tche d fro m ma in me mor y for thi s ope ra tion. The al loca ted c ache
block da ta is undefined after this operation. It is the responsibi lity of the pro grammer to update the alloca ted cache
block by sto re operations .
Refer to the ‘cache architectur e’ sec tion for det ail s on t h e cache block size.
The alloc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the execution
of th e all oc opera ti on. If th e LS B of r gu ard is 1, allo c oper at ion i s exec ut e d; othe r w is e, it is no t exe cu te d.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd,
cache_block_size = 0x40 alloc r10 Allocates a cache block for the address space from
0xabc0 to 0x0xabff wit hout f e t ching the data from
main memory; The data in this address space is
undefined.
r10 = 0xab cd, r11 = 0,
cache_block_size = 0x40 IF r11 alloc r10 since guard is false, alloc operation is not executed
r10 = 0xac0f, r11 = 1,
cache_block_size = 0x40 IF r11 alloc r10 Allocates a cache block for the address space from
0xac00 to 0xac3f without fetching the data from main
memory; the data in this address space is undefined.
SEE ALSO
allocd allocr allocx
alloc
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-5 PRELIMINARY SPECIFICATION
allocd Allocate a cache block with displacement
SYNTAX
[ IF rguard ] allocd(d) rsrc1
FUNCTION
if rguard then {
cache_block_ma sk = ~(cache _block_ size -1)]
allocate adata cache block with [(rsrc1 + d) & cache_block_mask] address
}
ATTRIBUTES
Function unit dmemspec
Operation code 213
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge -25 5..252 by 4
Latency -
Issue slots 5
DESCRIPTION
The allocd operation allocate a cache block with the address computed from [(rsrc1 + d) & cache_block_mask ] and
sets the status of this cac he block a s valid. No data is fetched from main me mory for th is operation. The alloc ated
cac he block da ta is undefined a fter this operati on. It is t he responsibility of the programmer to update the allocated
cache block by store operations.
Refer to the ‘cache architectur e’ sec tion for det ail s on t h e cache block size.
The allocd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
exec ut ion of the al locd opera ti on . If th e LS B of rguard is 1, allocd operation is e xecuted; otherwise, i t is not executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd,
cache_block_size = 0x40 allocd(0x32) r10 Allocates a cache block for the address space from
0xabc0 to 0x0xabff wit hout f e t ching the data from
main memory; The data in this address space is
undefined.
r10 = 0xab cd, r11 = 0,
cache_block_size = 0x40 IF r11 allocd(0x32) r10 since guard is false, allocd operation is not executed
r10 = 0xabff, r11 = 1,
cache_block_size = 0x40 IF r11 allocd(0x4) r10 Allocates a cache block for the address space from
0xac00 to 0xac3f without fetching the data from main
memory; the data in this address space is undefined.
SEE ALSO
allocr allocx
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-6
Allocate a cache block with index
SYNTAX
[ IF rguard ] allocr rsrc1 rsrc2
FUNCTION
if rguard then {
cache_block_ma sk = ~(cache_block_size -1)]
allocate adata cache block with [(rsrc1 + rsrc2) & cache_block_mask] address
}
ATTRIBUTES
Function unit dmemspec
Operation code 214
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
Th e alloc r o pe ra tion allo cate a ca che block w ith t he a dd ress com p u ted fro m [ (rsrc1 + rscr2) & ca che_block_m ask] and
sets the status of this cac he block a s valid. No data is fetched from main me mory for th is operation. The alloc ated
cac he block da ta is undefined a fter this operati on. It is t he responsibility of the programmer to update the allocated
cache block by store operations.
Refer to the ‘cache architectur e’ sec tion for det ail s on t h e cache block size.
The allocr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
exec ut ion of the al lo cr op er a tio n. If the L SB o f rguard is 1, allo cr operation is execut ed; o therwise, it is no t executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xab cd, r12 = 0x 32
cache_block_size = 0x40 allocr r10 r12 Allocates a cache block for the address space from
0xabc0 to 0xabff without fetching the data from main
memory; The data in this address space is undefined.
r10 = 0xabcd, r11 = 0, r12=0x32,
cache_block_size = 0x40 IF r11 allocr r10 r12 since guard is false, allocr operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x4,
cache_block_size = 0x40 IF r11 allocr r10 r12 Allocates a cache block for the address space from
0xac00 to 0xac3f without fetching the data from main
memory; the data in this address space is undefined.
SEE ALSO
allocd allocx
allocr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-7 PRELIMINARY SPECIFICATION
allocx Alloca te a cache b lock with sc aled ind e x
SYNTAX
[ IF rguard ] allocx rsrc1 rsrc2
FUNCTION
if rguard then {
cache_block_ma sk = ~(cache_block_size -1)]
allocate adata cache blockwith [(rsrc1 + 4 x rsrc2) & cache_bloc k _ma sk] addres s
}
ATTRIBUTES
Function unit dmemspec
Operation code 215
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
The allocx operation allocate a cache block with the address computed from [(rsrc1 + 4 x rsc r2) & cache_block_mask]
and sets the status of t his cache block as valid. No data is fetched from main memory for this operation. The allocated
cac he block da ta is undefined a fter this operati on. It is t he responsibility of the programmer to update the allocated
cache block by store operations.
Refer to the ‘cache architectur e’ sec tion for det ail s on t h e cache block size.
The allocx operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
ex ecution of the allocx operation. If the LSB of rguard is 1, allo cx oper ati on is execu te d; other wis e, it is no t execu ted.
EXAMPLES
Initial Values Operation Result
r10 = 0xab cd, r12 = 0x c
cache_block_size = 0x40 allocx r10 r12 Allocates a cache block for the address space from
0xabc0 to 0x0xabff wit hout f e t ching the data from
main memory; The data in this address space is
undefined.
r10 = 0xabcd, r11 = 0, r12=0xc,
cache_block_size = 0x40 IF r11 allocx r10 r12 since guard is false, allocx operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x4,
cache_block_size = 0x40 IF r11 allocx r10 r12 Allocates a cache block for the address space from
0xac00 to 0xac3f without fetching the data from main
memory; the data in this address space is undefined.
SEE ALSO
allocd allocr
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-8
Arithmetic shift left
SYNTAX
[ IF rguard ] asl rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n ← rsrc2<4:0>
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← 0
if rsrc2<31:5> != 0 {
rd e st < - 0
}
}
ATTRIBUTES
Function unit shifter
Operation code 19
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As s hown below, the asl ope r ation takes two a rguments, rsrc1 and rsrc2. Rsrc2 sp ecify an unsigned shift a mount,
and r dest is set to rsrc1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not ze ro, then take this as
a shif t by 32 or mor e bi ts. Ze ros a r e sh ifted in t o th e LS Bs o f rdest while the MSBs shifted out of rsrc1 are lost.
The asl operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 asl r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 asl r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x20, r30 = 3 IF r20 asl r60 r30 → r110 r110 ← 0x100
r70 = 0xfffffffc, r40 = 2 asl r70 r40 → r120 r120 ← 0xfffffff0
r80 = 0xe, r50 = 0xfffffffe asl r80 r50 → r125 r125 ← 0x00000000 (shift by more than 32)
r30 = 0x7008000f, r60 = 0x20 asl r30 r60 → r111 r111 ← 0x00000000
r30 = 0x8008000f, r45 = 0x80000000 asl r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x23 asl r30 r45 → r100 r100 ← 0x00000000
031
rsrc1 31
rsrc2
000
Left shifter
32 bits from rsrc1
031
rdest 3
000
Interm ediate result
(example: n = 3)
rsrc2
0
SEE ALSO
asli asr asri lsl lsli lsr
lsri rol roli
asl
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-9 PRELIMINARY SPECIFICATION
asli Arithmetic shift left immediate
SYNTAX
[ IF rguard ] asli(n) rsrc1 → rdest
FUNCTION
if rguard then {
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← 0
}
ATTRIBUTES
Function unit shifter
Operation code 11
Nu mber of operands 1
Modifier 7 bits
Modifier range 0..31
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the asli opera tion takes a sing le a rg u me n t in rsrc1 and an imm e diate m odifier n and produces a
resu lt in rdest equal to rsrc1 ari thme tica lly sh ifted left by n bits. The value of n must be between 0 and 31, inclusive.
Zeros are shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The asli operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 asli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 asli(3) r60 → r100 no ch ange, since guard is fa l se
r20 = 1, r60 = 0x20 IF r20 asli(3) r60 → r110 r110 ← 0x100
r70 = 0xfffffffc asli(2) r70 → r120 r120 ← 0xfffffff0
r80 = 0xe asli(30) r80 → r125 r125 ← 0x80000000
031
rsrc1
000
Left shifter
32 bits from rsrc1
031
rdest 3
000
Interm ediate result
(example: n = 3)
Shift amount n
from ope r ation mod if ier
SEE ALSO
asl asr asri lsl lsli lsr
lsri rol roli
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-10
Arithmetic shift right
SYNTAX
[ IF rguard ] asr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n ← rsrc2<4:0>
rdest<31:31–n> ← rsrc1<31>
rdest<30–n:0> ← rsrc1<30:n>
if rsrc2<31:5> != 0 {
rdest <- rsrc1<31>
}
}
ATTRIBUTES
Function unit shifter
Operation code 18
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the asr operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
am ount, and rsrc1 is arithm etically shifted right by t hi s amount. If the rsrc2<31:5> value is not zero, then take this as a
shift by 32 or more bit s. The MSB (s ign b i t) of rsrc1 is replicated as needed to fill vacated bits from the left.
The asr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x7008000f, r20 = 1 asr r30 r20 → r50 r50 ← 0x38040007
r30 = 0x7008000f, r42 = 2 asr r30 r42 → r60 r60 ← 0x1c020003
r10 = 0, r30 = 0x7008000f, r44 = 4 IF r10 asr r30 r44 → r70 no ch ange, since guard is fa l se
r20 = 1, r30 = 0x7008000f, r44 = 4 IF r20 asr r30 r44 → r80 r80 ← 0x07008000
r40 = 0x80030007, r44 = 4 asr r40 r44 → r90 r90 ← 0xf8003000
r30 = 0x7008000f, r45 = 0x1f asr r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x1f asr r30 r45 → r100 r100 ← 0xffffffff
r30 = 0x7008000f, r45 = 0x20 asr r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x20 asr r30 r45 → r100 r100 ← 0xffffffff
r30 = 0x8008000f, r45 = 0x23 asr r30 r45 → r100 r100 ← 0xffffffff
031
rsrc1 0
rsrc2
SSS
Right shifter
32 bits from rsrc1
031
rdest 28
SSS
Intermediate result
(example: n = 3)
rsrc2
S
S
S
31
SEE ALSO
asl asli asri lsl lsli lsr
lsri rol roli
asr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-11 PRELIMINARY SPECIFICATION
asri Arithmetic sh ift right by immediate amount
SYNTAX
[ IF rguard ] asri(n) rsrc1 → rdest
FUNCTION
if rguard then {
rdest<31:31–n> ← rsrc1<31>
rdest<30–n:0> ← rsrc1<31:n>
}
ATTRIBUTES
Function unit shifter
Operation code 10
Nu mber of operands 1
Modif ier 7 bits
Modifier range 0..31
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the asri opera tion takes a sing le a rg u me n t in rsrc1 and an imm e diate m odifier n and produces a
resu lt in rdest that is eq ual to rsrc1 arithmeticall y shifted right by n bits. The value of n must be b etween 0 and 31,
incl usive. The M S B (si gn bit ) of r src1 is replicated as needed to fill vacated bits from the left.
The asri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x7008000f asri(1) r30 → r50 r50 ← 0x38040007
r30 = 0x7008000f asri(2) r30 → r60 r60 ← 0x1c020003
r10 = 0, r30 = 0x7008000f IF r10 asri(4) r30 → r70 no ch ange, since guard is fa l se
r20 = 1, r30 = 0x7008000f IF r20 asri(4) r30 → r80 r80 ← 0x07008000
r40 = 0x80030007 asri(4) r40 → r90 r90 ← 0xf8003000
r30 = 0x7008000f asri(31) r30 → r100 r100 ← 0x00000000
r40 = 0x80030007 asri(31) r40 → r110 r110 ← 0xffffffff
SSS
Right shifter
32 bits from rsrc1
031
rdest 28
SSS
Intermediate result
(example: n = 3) S
S
031
rsrc1
Shift amount n
from ope r ation mod if ier
S
SEE ALSO
asl asli asr lsl lsli lsr
lsri rol roli
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-12
Bitwise logical AND
SYNTAX
[ IF rguard ] bitand rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 & rsrc2
ATTRIBUTES
Function unit alu
Operation code 16
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The bitand operation computes the bitwise, logical AND of the first and second arguments, rsrc1 an d rsrc2. The
result is stored in the destination register, rdest.
The bitand operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xf310ffff, r40 = 0xffff0000 bitand r30 r40 → r90 r90 ← 0xf3100000
r10 = 0, r50 = 0x88888888 IF r10 bitand r30 r50 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0xf310ffff,
r50 = 0x88888888 IF r20 bitand r30 r50 → r100 r100 ← 0x80008888
r60 = 0x11119999, r50 = 0x88888888 bitand r60 r50 → r110 r110 ← 0x00008888
r70 = 0x55555555, r30 = 0xf310ffff bitand r70 r30 → r120 r120 ← 0x51105555
SEE ALSO
bitor bitxor bitandinv
bitand
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-13 PRELIMINARY SPECIFICATION
bitandinv Bitwise logical AND NOT
SYNTAX
[ IF rguard ] bitandinv rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 & ~rsrc2
ATTRIBUTES
Function unit alu
Operation code 49
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The bitandinv operation computes the bitwise, logical AND of the first argument, rsrc1, with the 1’s complement
of th e se co nd ar g u m e nt, rsrc2. Th e r es ul t i s sto re d in the de st in a ti on regi st er, r dest.
The bitandinv o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xf310ffff, r40 = 0xffff0000 bitandinv r30 r40 → r90 r90 ← 0x0000ffff
r10 = 0, r50 = 0x88888888 IF r10 bitandinv r30 r50 → r80 no change, since guard is f als e
r20 = 1, r30 = 0xf310ffff,
r50 = 0x88888888 IF r20 bitandinv r30 r50 → r100 r100 ← 0x73107777
r60 = 0x11119999, r50 = 0x88888888 bitandinv r60 r50 → r110 r110 ← 0x11111111
r70 = 0x55555555, r30 = 0xf310ffff bitandinv r70 r30 → r120 r120 ← 0x04450000
SEE ALSO
bitand bitor bitxor
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-14
Bitwise logical NOT
SYNTAX
[ IF rguard ] bitinv rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ~rsrc1
ATTRIBUTES
Function unit alu
Operation code 50
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The bitinv operation computes the bitwise, logical NOT of the argument rsrc1 and writes the result into rdest.
The bitinv operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xf310ffff bitinv r30 → r60 r60 ← 0x0cef0000
r10 = 0, r40 = 0xffff0000 IF r10 bitinv r40 → r70 no change, since guard i s false
r20 = 1, r40 = 0xffff0000 IF r20 bitinv r40 → r100 r100 ← 0x0000ffff
r50 = 0x88888888 bitinv r50 → r110 r110 ← 0x77777777
SEE ALSO
bitand bitandinv bitor
bitxor
bitinv
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-15 PRELIMINARY SPECIFICATION
bitor Bitwise logical OR
SYNTAX
[ IF rguard ] bitor rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 | rsrc2
ATTRIBUTES
Function unit alu
Operation code 17
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The bitor operation computes the bitwise, logical OR of the first and second arguments, rsrc1 and rsrc2. The
result is stored in the destination register, rdest.
The bitor operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xf310ffff, r40 = 0xffff0000 bitor r30 r40 → r90 r90 ← 0xffffffff
r10 = 0, r50 = 0x88888888 IF r10 bitor r30 r50 → r80 no change, since guard i s false
r20 = 1, r30 = 0xf310ffff,
r50 = 0x88888888 IF r20 bitor r30 r50 → r100 r100 ← 0xfb98ffff
r60 = 0x11119999, r50 = 0x88888888 bitor r60 r50 → r110 r110 ← 0x99999999
r70 = 0x55555555, r30 = 0xf310ffff bitor r70 r30 → r120 r120 ← 0xf755ffff
SEE ALSO
bitand bitandinv bitinv
bitxor
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-16
Bitwise logic al exclusive-OR
SYNTAX
[ IF rguard ] bitxor rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 ⊕ rsrc2
ATTRIBUTES
Function unit alu
Operation code 48
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The bitxor operation computes the bitwise, logical exclusive-OR of the first and second arguments, rsrc1 and
rsrc2. The result is stored in the destination register, rdest.
The bitxor operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xf310ffff, r40 = 0xffff0000 bitxor r30 r40 → r90 r90 ← 0x0cefffff
r10 = 0, r50 = 0x88888888 IF r10 bitxor r30 r50 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0xf310ffff,
r50 = 0x88888888 IF r20 bitxor r30 r50 → r100 r100 ← 0x7b987777
r60 = 0x11119999, r50 = 0x88888888 bitxor r60 r50 → r110 r110 ← 0x99991111
r70 = 0x55555555, r30 = 0xf310ffff bitxor r70 r30 → r120 r120 ← 0xa645aaaa
SEE ALSO
bitand bitandinv bitinv
bitor
bitxor
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-17 PRELIMINARY SPECIFICATION
borrow Compute borrow bi t from u nsi gned s ubtrac t
pseudo-op fo r ugtr
SYNTAX
[ IF rguard ] borrow rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 < rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 33
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The borrow ope r ation is a pseudo operation transformed b y the sched uler int o an ugtr with reversed arguments.
(N ote: pseudo oper ations cannot be u s e d in ass embly source fi les . )
The borrow operation computes the unsigned difference of the first and second arguments, rsrc1–rsrc2. If the
dif fere nc e gene r ate s a borro w ( if r src2 > rsrc1), 1 is sto red i n the de st i nati on regi st er, r dest; otherwise, rdest is set to 0.
The borrow operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r70 = 2, r30 = 0xfffffffc borrow r70 r30 → r80 r80 ← 1
r10 = 0, r70 = 2, r30 = 0xfffffffc IF r10 borrow r70 r30 → r90 no change, since guard i s false
r20 = 1, r70 = 2, r30 = 0xfffffffc IF r20 borrow r70 r30 → r100 r100 ← 1
r60 = 4, r30 = 0xfffffffc borrow r60 r30 → r110 r110 ← 1
r30 = 0xfffffffc borrow r30 r30 → r120 r120 ← 0
SEE ALSO
ugtr carry
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-18
Compute carry bit from unsigned add
SYNTAX
[ IF rguard ] carry rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (rsrc1+rsrc2) < 232 then
rdest ← 0
else
rdest ← 1
}
ATTRIBUTES
Function unit alu
Operation code 45
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The carry operation computes the unsigned sum of the first and second arguments, rsrc1+rsrc2. If the sum
gener ates a carry ( if t he sum is greater th an 232-1 ) , 1 is stored in t he destination register, rdest; othe r wis e, rdest is set
to 0.
The carry operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r70 = 2, r30 = 0xfffffffc carry r70 r30 → r80 r80 ← 0
r10 = 0, r70 = 2, r30 = 0xfffffffc IF r10 carry r70 r30 → r90 no ch ange, since guard is false
r20 = 1, r70 = 2, r30 = 0xfffffffc IF r20 carry r70 r30 → r100 r100 ← 0
r60 = 4, r30 = 0xfffffffc carry r60 r30 → r110 r110 ← 1
r30 = 0xfffffffc carry r30 r30 → r120 r120 ← 1
SEE ALSO
borrow
carry
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-19 PRELIMINARY SPECIFICATION
curcycles Re ad current clock cycle counter, least-
significant word
SYNTAX
[ IF rguard ] curcycles → rdest
FUNCTION
if rguard then
rdest ← CCCOUNT<31:0>
ATTRIBUTES
Function unit fcomp
Operation code 162
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
Refer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
curcycles operation copies the current low 32 bits of the master Clock Cycle Counter (CCCOUNT) to the
destination register, rdest.. The master CCCOUNT increments on all cycles (processor-stall and non-stall) if
PCSW.CS = 1; otherwise, the counter increments only on non-stall cycles.
The curcycles o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
CCCOUNT_HR = 0xabcdefff12345678 curcycles → r60 r30 ← 0x12345678
r10 = 0, CCCOUNT_HR = 0xabcdefff12345678 IF r10 curcycles → r70 no change, since guard is false
r20 = 1, CCCOUNT_HR = 0xabcdefff12345678 IF r20 curcycles → r100 r100 ← 0x12345678
SEE ALSO
cycles hicycles writepcsw
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-20
Read clock cycle counter, least-significant word
SYNTAX
[ IF rguard ] cycles → rdest
FUNCTION
if rguard then
rdest ← CCCOUNT<31:0>
ATTRIBUTES
Function unit fcomp
Operation code 154
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
Refer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
cycles operation copies t he low 32 bits of the slave register of Clock Cycle Counter (CCCOUNT) to the destination
register, rdest. The contents of the master counter are transferred to the slave CCCOUNT register only on a
successful interruptible jump and on processor reset. Thus, if cycles and hicycles are executed without
intervening interruptible jumps, the operation pair is guaranteed to be a coherent sample of the master clock-cycle
counter. The master counter increments on all cycles (proce ssor-stall and non-stall) if PCSW.CS = 1; otherwise, the
co un t er i ncr em ents only on n on -stall cy cles .
The cycles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
CCCOUNT_HR = 0xabcdefff12345678 cycles → r60 r30 ← 0x12345678
r10 = 0, CCCOUNT_HR = 0xabcdefff12345678 IF r10 cycles → r70 no ch ange, since guard is false
r20 = 1, CCCOUNT_HR = 0xabcdefff12345678 IF r20 cycles → r100 r100 ← 0x12345678
SEE ALSO
hicycles curcycles
writepcsw
cycles
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-21 PRELIMINARY SPECIFICATION
Data cache copy back
SYNTAX
[ IF rguard ] dcb(d) rsrc1
FUNCTION
if rguard then {
addr ← rsrc1 + d
if dcache_valid_addr(addr) && dcache_dirty_addr(addr) then {
dcache_copyback_addr(addr)
dcache_reset_dirty_addr(addr)
}
}
ATTRIBUTES
Function unit dmemspec
Operation code 205
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency 3
Issue slots 5
DESCRIPTION
The dcb operation causes a block in the data cache to be copied back to main memory if the block is marked dirty
and valid, and the block’s dirty bit is reset. The target block of dcb is the block in the data cache that contains the byte
addr e s sed by rsrc1 + d. The d value is an opc ode mo dif ie r, mus t be in t h e ra ng e –256 to 252 inclusive, and must be a
m ultip le of 4.
A valid copy of the target block remains in the cache. Stall cycles are taken as necessary to complete t he copy-back
oper atio n. I f th e ta rget bl ock is not d ir ty or if the block is no t in t he ca che, dcb has no ef fect a nd no st all c ycle s are
taken.
dcb has no effect on b l oc ks tha t are in the non-ca ch ea bl e SD RAM ape rtur e. dcb does not cha ng e th e repl ac eme nt
st atus of data-cache blocks.
dcb e nsures cohe rency between cach es and main memo ry by disc arding all pend ing prefetch operations and by
c ausing all non-empty copyback buffers to be e mpt ied to main memory.
The dcb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls if the
operation is carried out or not.If the LSB of rguard is 1, the op eration is ca rrie d out ; o the rw i se, it is no t car r i ed ou t.
EXAMPLES
Initial Values Operat ion Result
dcb(0) r30
r10 = 0 IF r10 dcb(4) r40 no change and no stall cycles, since
guard is false
r20 = 1 IF r20 dcb(8) r50
SEE ALSO
dinvalid
dcb
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-22
Inv alid ate data cac he b l ock
SYNTAX
[ IF rguard ] dinvalid(d) rsrc1
FUNCTION
if rguard then {
addr ← rsrc1 + d
if dcache_valid_addr(addr) th en {
dcache_reset_valid_addr(addr)
dcache_reset_dirty_addr(addr)
}
}
ATTRIBUTES
Function unit dmemspec
Operation code 206
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency 3
Issue slots 5
DESCRIPTION
The dinvalid operation resets the valid and dirty bit of a block in the data cache. Regardless of the block’s di rty
bit, th e block is n ot writ ten ba ck to main memory. T he tar get block of dinvalid is the blo ck in the da ta cach e tha t
contains the byte addressed by rsrc1 + d. The d value is an opcode modifier, must be in the range –256 to 252
inclusive, and must be a multiple of 4.
Stall cycles are taken as necessary to complete the invalidate operation. If the target block is not in the cache,
dinvalid has no effect and no stall cycles are taken.
dinvalid has no effect on blocks that are in the non-cacheable SDRAM aper ture. dinvalid does clear the
va li d bits of locked block s. dinvalid does not cha nge the replac ement status of data-cache b locks.
dinvalid ensures cohere ncy be tween caches and mai n memo ry by dis carding all pen ding prefetch operations
and by causing all non-empty c opyb ack buff ers to be e m p tie d to mai n memory.
The dinvalid operation optionally takes a guard, specifi ed in r guard. If a guard is present, its LSB controls if the
operation is carried out or not. If the LSB of rguard is 1, the operation is carried out; otherwise, it is not carried out.
EXAMPLES
Initial Values Operation Result
dinvalid(0) r30
r10 = 0 IF r10 dinvalid(4) r40 no change and no stall cycles, since
guard is false
r20 = 1 IF r20 dinvalid(8) r50
SEE ALSO
dcb
dinvalid
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-23 PRELIMINARY SPECIFICATION
Clipped sign ed absolute value
pseudo-op fo r h_dspiabs
SYNTAX
[ IF rguard ] dspiabs rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 >= 0 then
rdest ← rsrc1
else if rsrc1 = 0x80000000 then
rdest ← 0x7fffffff
else
rdest ← –rsrc1
}
ATTRIBUTES
Function unit dspalu
Operation code 65
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The dspiabs o perat i on is a pseudo opera ti on t ra nsformed by t he s cheduler into an h_ dspiabs with a constant
fir st argument ze ro and s e cond argument eq ual to the dspiabs ar gu ment . (N ot e: pseu do op er at i on s can no t be us ed
in ass embly source fil es. )
The dspiabs operation computes the absolute value of rsrc1, clips the result into the range [231–1..0] (or
[0x7 fff ffff..0] ) , and sto r es th e cl ip ped valu e into rdest. All values are signed integers.
The dspiabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff dspiabs r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0x80000001 IF r10 dspiabs r40 → r70 no ch ange, since guard is false
r20 = 1, r40 = 0x80000001 IF r20 dspiabs r40 → r100 r100 ← 0x7fffffff
r50 = 0x80000000 dspiabs r50 → r80 r80 ← 0x7fffffff
r90 = 0x7fffffff dspiabs r90 → r110 r110 ← 0x7fffffff
SEE ALSO
h_dspiabs h_dspidualabs
dspiadd dspimul dspisub
dspuadd dspumul dspusub
dspiabs
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-24
Clipped signed add
SYNTAX
[ IF rguard ] dspiadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← sign_ext32to64(rsrc1) + sign_ext32to64( rsrc2)
if temp < 0xffffffff80000000 then
rdest ← 0x80000000
else if temp > 0x000000007fffffff then
rdest ← 0x7fffffff
else
rdest ← temp
}
ATTRIBUTES
Function unit dspalu
Operation code 66
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the dspiadd operation computes the sum rsrc1+rsrc2, clips the result into the 32-bit signed
r ang e [2 31–1..–231] (or [0x7fffffff..0x80000000]), and stores the clipped value into rdest. All valu es ar e si gned in t egers.
The dspiadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x1200, r40 = 0xff dspiadd r30 r40 → r60 r60 ← 0x12ff
r10 = 0, r30 = 0x1200, r40 = 0xff IF r10 dspiadd r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x1200, r40 = 0xff IF r20 dspiadd r30 r40 → r100 r100 ← 0x12ff
r50 = 0x7fffffff , r90 = 1 dspiadd r50 r90 → r110 r110 ← 0x7fffffff
r70 = 0x80000000, r80 = 0xffffffff dspiadd r70 r80 → r120 r120 ← 0x80000000
031
rsrc1 031
rsrc2
031
rdest
+
032
Clip to [231–1..–231]
signed signed
Full-precision
33-bit result signed
signed
SEE ALSO
dspiabs dspimul dspisub
dspuadd dspumul dspusub
dspiadd
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-25 PRELIMINARY SPECIFICATION
Dual clipped absolute value of signed 16- b it
halfwords
pseu do-op for h_dspidualabs
SYNTAX
[ IF rguard ] dspidualabs rsrc1 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc1<15:0>)
temp2 ← sign_ext16to32(rsrc1<31:16>)
if temp1 = 0xffff8000 then temp1 ← 0x7fff
if temp2 = 0xffff8000 then temp2 ← 0x7fff
if temp1 < 0 then temp1 ← –temp1
if temp2 < 0 then temp2 ← –temp2
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 72
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The dspidualabs operation is a pseudo operation transformed by the scheduler into an h_dspidualabs with
a constant zero as first argument and the dspidualabs argument as second argument. (Note: pseudo operations
ca nn ot b e us ed in assembl y so u r c e f iles .)
The dspidualabs op erat ion pe rfor ms tw o 16-bi t cl ippe d, sig ned a bsol ut e valu e com put atio ns s epara tely on the
high and low 16-bit halfwords of rsrc1. Both absolute values are clipped into the range [0x0..0x7fff] and written into the
corresponding halfwords of rdest. All values are signed 16-bit in tegers.
The dspidualabs op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0032 dspidualabs r30 → r60 r60 ← 0x00010032
r10 = 0, r40 = 0x80008001 IF r10 dspidualabs r40 → r70 no ch ange, since guard is false
r20 = 1, r40 = 0x80008001 IF r20 dspidualabs r40 → r100 r100 ← 0x7fff7fff
r50 = 0x0032ffff dspidualabs r50 → r80 r80 ← 0x00320001
r90 = 0x7fffffff dspidualabs r90 → r110 r110 ← 0x7fff0001
SEE ALSO
h_dspidualabs dspiabs
dspidualadd dspidualmul
dspidualsub
dspidualabs
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-26
Dual clipped add of signed 16-bit halfwords
SYNTAX
[ IF rguard ] dspidualadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc1<15:0>) + sign_ext16to32(rsrc2<15:0>)
temp2 ← sign_ext16to32(rsrc1<31:16>) + sign_ext16to32(rsrc2<31:16>)
if temp1 < 0xffff8000 then temp1 ← 0x8000
if temp2 < 0xffff8000 then temp2 ← 0x8000
if temp1 > 0x7fff then temp1 ← 0x7fff
if temp2 > 0x7fff then temp2 ← 0x7fff
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 70
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the dspidualadd operation computes two 16-bit clipped, signed sums separately on the two
pairs of high and low 16-bit halfwords of rsrc1 and rsrc2. Both sums are clipped into the range [215–1..–215] (or
[0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualadd op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x12340032, r40 = 0x00010002 dspidualadd r30 r40 → r60 r60 ← 0x12350034
r10 = 0, r30 = 0x12340032, r40 = 0x00010002 IF r10 dspidualadd r30 r40 → r70 no change, since guard is
false
r20 = 1, r30 = 0x12340032, r40 = 0x00010002 IF r20 dspidualadd r30 r40 → r100 r100 ← 0x12350034
r50 = 0x80000001, r80 = 0xffff7fff dspidualadd r50 r80 → r90 r90 ← 0x80007fff
r110 = 0x00017fff, r120 = 0x7fff7fff dspidualadd r110 r120 → r125 r125 ← 0x7fff7fff
01531
rsrc1 01531
rsrc2
031
rdest
+
+
15
017017
Two fu ll-precision
17-bit signed sums
Clip to [215–1 .. –215]Clip to [215–1 .. –215]
signed signed signed
signed signed
signedsigned
signed
SEE ALSO
dspidualabs dspidualmul
dspidualsub dspiabs
dspidualadd
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-27 PRELIMINARY SPECIFICATION
Du al clipped multiply of sig ned 16- bit halfw o rds
SYNTAX
[ IF rguard ] dspidualmul rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc1<15:0>) × sign_ext16to32(rsrc2<15:0>)
temp2 ← sign_ext16to32(rsrc1<31:16>) × sign_ext16to32(rsrc2<31:16>)
if temp1 < 0xffff8000 then temp1 ← 0x8000
if temp2 < 0xffff8000 then temp2 ← 0x8000
if temp1 > 0x7fff then temp1 ← 0x7fff
if temp2 > 0x7fff then temp2 ← 0x7fff
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit dspmul
Operation code 95
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, the dspidualmul opera t io n comp ut es two 16- bi t clip pe d, s igne d pr od ucts separatel y on the tw o
pairs of high and low 16-bit halfwor ds of rsrc1 and rsrc2. Both products are clipped into the range [215–1..–215] (or
[0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualmul op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x0020010, r40 = 0x00030020 dspidualmul r30 r40 → r60 r60 ← 0x00060200
r10 = 0, r30 = 0x0020010, r40 = 0x00030020 IF r10 dspidualmul r30 r40 → r70 no change, since guard is fa l se
r20 = 1, r30 = 0x0020010, r40 = 0x00030020 IF r20 dspidualmul r30 r40 → r100 r100 ← 0x00060200
r50 = 0x80000002, r80 = 0x00024000 dspidualmul r50 r80 → r90 r90 ← 0x80007fff
r110 = 0x08000003, r120 = 0x00108001 dspidualmul r110 r120 → r125 r125 ← 0x7fff8000
01531
rsrc1 01531
rsrc2
031
rdest
×
×
15
031031
Two full-precision
32-bit signed products
Clip to [215–1..–215]Clip to [215–1..–215]
signed signed signed
signed signed
signedsigned
signed
SEE ALSO
dspidualabs dspidualadd
dspidualsub dspiabs
dspidualmul
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-28
Dual clippe d subtrac t of signe d 16-bi t hal fwords
SYNTAX
[ IF rguard ] dspidualsub rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc1<15:0>) – sign_ex t16to32(rsrc2<15:0>)
temp2 ← sign_ext16to32(rsrc1<31:16>) – sign_ext16to32(rsrc2<31:16>)
if temp1 < 0xffff8000 then temp1 ← 0x8000
if temp2 < 0xffff8000 then temp2 ← 0x8000
if temp1 > 0x7fff then temp1 ← 0x7fff
if temp2 > 0x7fff then temp2 ← 0x7fff
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 71
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As sho wn below, the dspidualsub op erat ion co mpu te s two 1 6-bit c lipp ed , sign ed differ enc es separately o n th e
two pair s of hi gh and low 1 6-bit ha l f words of r src1 and rsrc2. B o th diff e r ences are cl ipped into the range [215–1..–215]
(or [0x7fff. .0x8000]) and written into the corresponding halfwords of rdest. All valu es a re sign ed 16-bit integers.
The dspidualsub op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x12340032, r40 = 0x00010002 dspidualsub r30 r40 → r60 r60 ← 0x12330030
r10 = 0, r30 = 0x12340032, r40 = 0x00010002 IF r10 dspidualsub r30 r40 → r70 no change, since guard is
false
r20 = 1, r30 = 0x12340032, r40 = 0x00010002 IF r20 dspidualsub r30 r40 → r100 r100 ← 0x12330030
r50 = 0x80000001, r80 = 0x00018001 dspidualsub r50 r80 → r90 r90 ← 0x80007fff
r110 = 0x00018001, r120 = 0x80010002 dspidualsub r110 r120 → r125 r125 ← 0x7fff8000
01531
rsrc1 01531
rsrc2
031
rdest
−
−
15
017017
Two fu ll-precision
17-bit signed differences
Clip to [215–1..–215]Clip to [215–1..–215]
signed signed signed
signed signed
signedsigned
signed
SEE ALSO
dspidualabs dspidualadd
dspidualmul dspiabs
dspidualsub
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-29 PRELIMINARY SPECIFICATION
Clipped sign ed m ultiply
SYNTAX
[ IF rguard ] dspimul rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← sign_ext32to64(rsrc1) × sign_ext32to64(rsrc2)
if temp < 0xffffffff80000000 then
rdest ← 0x80000000
else if temp > 0x000000007fffffff then
rdest ← 0x7fffffff
else
rdest ← temp<31:0>
}
ATTRIBUTES
Function unit ifmul
Operation code 141
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, th e dspimul op eration comp utes the product rsrc1×rsrc2, clips the result into the 32-bit range
[231–1..–231] (o r [0x7fffffff..0 x8 00 00 000]), and s to res the cl ip pe d value int o rdest. All values are signed integers.
The dspimul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x10, r40 = 0x20 dspimul r30 r40 → r60 r60 ← 0x200
r10 = 0, r30 = 0x10, r40 = 0x20 IF r10 dspimul r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x10, r40 = 0x20 IF r20 dspimul r30 r40 → r100 r100 ← 0x200
r50 = 0x40000000, r90 = 2 dspimul r50 r90 → r110 r110 ← 0x7fffffff
r80 = 0xffffffff dspimul r80 r80 → r120 r120 ← 0x1
r70 = 0x80000000, r90 = 2 dspimul r70 r90 → r120 r120 ← 0x80000000
031
rsrc1 031
rsrc2
031
rdest
×
063
Clip to [231–1..–231]
signed signed
Full-precision
64-bit result signed
signed
SEE ALSO
dspiabs dspiadd dspisub
dspuadd dspumul dspusub
dspimul
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-30
Clipped sign ed subtract
SYNTAX
[ IF rguard ] dspisub rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← sign_ext32to64(rsrc1) – sign_ex t32to6 4(rsrc2)
if temp < 0xfffffffff80000000 then
rdest ← 0x80000000
else if temp > 0x000000007fffffff then
rdest ← 0x7fffffff
else
rdest ← temp<31:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 68
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As s hown below, the dspisub operation computes the difference rsrc1–rsrc2, clips the result into the 32-bit range
[231–1..–231] (o r [0x7fffffff..0 x8 00 00 000]), and s to res the cl ip pe d value int o rdest. All values are signed integers.
The dspisub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x1200, r40 = 0xff dspisub r30 r40 → r60 r60 ← 0x1101
r10 = 0, r30 = 0x1200, r40 = 0xff IF r10 dspisub r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x1200, r40 = 0xff IF r20 dspisub r30 r40 → r100 r100 ← 0x1101
r50 = 0x7fffffff, r90 = 0xffffffff dspisub r50 r90 → r110 r110 ← 0x7fffffff
r70 = 0x80000000, r80 = 1 dspisub r70 r80 → r120 r120 ← 0x80000000
031
rsrc1 031
rsrc2
031
rdest
−
032
Clip to [231–1..–231]
signed signed
Full-precision
33-bit result signed
signed
SEE ALSO
dspiabs dspiadd dspimul
dspuadd dspumul dspusub
dspisub
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-31 PRELIMINARY SPECIFICATION
Clipped unsigned add
SYNTAX
[ IF rguard ] dspuadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← zero_ext32to64(rsrc1) + zero_ext32to64(rsrc2)
if (unsigned)temp > 0x00000000ffffffff then
rdest ← 0xffffffff
else
rdest ← temp<31:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 67
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the dspuadd operation com putes un signed s um rsrc1+rsrc2, clip s the result into the unsigned
range [232–1. .0] (or [0xfffff fff..0]), and s tore s the cl ipp e d value i nto rdest.
The dspuadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x1200, r40 = 0xff dspuadd r30 r40 → r60 r60 ← 0x12ff
r10 = 0, r30 = 0x1200, r40 = 0xff IF r10 dspuadd r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x1200, r40 = 0xff IF r20 dspuadd r30 r40 → r100 r100 ← 0x12ff
r50 = 0xffffffff , r90 = 1 dspuadd r50 r90 → r110 r110 ← 0xffffffff
r70 = 0x80000001, r80 = 0x7fffffff dspuadd r70 r80 → r120 r120 ← 0xffffffff
031
rsrc1 031
rsrc2
031
rdest
+
032
Clip to [232–1..0]
unsigned unsigned
Full-precision
33-bit result unsigned
unsigned
SEE ALSO
dspiabs dspiadd dspimul
dspisub dspumul dspusub
dspuadd
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-32
Clipped unsigned multiply
SYNTAX
[ IF rguard ] dspumul rsrc1 rsrc2 → rdest
OPERATION
if rguard then {
temp ← zero_ext32to64(rsrc1) × zero_ext32to64(rsrc2)
if (unsigned)temp > 0x00000000ffffffff then
rdest ← 0xffffffff
else
rdest ← temp<31:0>
}
ATTRIBUTES
Function unit ifmul
Operation code 142
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As show n below, t he dspumul operation computes unsigned product rsrc1×rsrc2, clips the result into the unsigned
range [232–1. .0] (or [0xfffff fff..0]), and store s the cl ipp e d value i nto rdest.
The dspumul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x10, r40 = 0x20 dspumul r30 r40 → r60 r60 ← 0x200
r10 = 0, r30 = 0x10, r40 = 0x20 IF r10 dspumul r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x10, r40 = 0x20 IF r20 dspumul r30 r40 → r100 r100 ← 0x200
r50 = 0x40000000, r90 = 2 dspumul r50 r90 → r110 r110 ← 0x80000000
r80 = 0xffffffff dspumul r80 r80 → r120 r120 ← 0xffffffff
r70 = 0x80000000, r90 = 2 dspumul r70 r90 → r120 r120 ← 0xffffffff
031
rsrc1 031
rsrc2
031
rdest
×
063
Clip to [232–1..0]
unsigned unsigned
Full-precision
64-bit result unsigned
unsigned
SEE ALSO
dspiabs dspiadd dspisub
dspuadd dspumul dspusub
dspumul
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-33 PRELIMINARY SPECIFICATION
Quad clipped add of unsigned/signed bytes
SYNTAX
[ IF rguard ] dspuquadaddui rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
for (i ← 0, m ← 31, n ← 24; i < 4; i ← i + 1, m ← m – 8, n ← n –8) {
temp ← zero_ext8to32(rsrc1<m:n>) + s ign_ext8to32(rsrc2<m:n>)
if temp < 0 then
rdest<m:n> ← 0
else if temp > 0xff then
rdest<m:n> ← 0xff
else rdest<m:n> ← temp<7:0>
}
}
ATTRIBUTES
Function unit dspalu
Operation code 78
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the dspuquadaddui operation computes four separate sums of the four pairs of corresponding
8-b it bytes of rsrc1 and rsrc2. The bytes in rsrc1 are co nsid ere d un sign ed va lues ; t he by tes i n rsrc2 are considered
signed. The four sums are clipped into the unsigned range [255..0] (or [0xff..0]); thus, the final byte sums are
unsign ed. A ll co m pu t a tio ns a r e pe rfor m e d wi th ou t los s of prec is ion.
The dspuquadaddui operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
cont rol s t he m odif icat ion of t he de st inat ion r egi ster. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x02010001, r40 = 0xffffff01 dspuquadaddui r30 r40 → r50 r50 ← 0x01000002
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c IF r10 dspuquadaddui r60 r70 → r80 no change, since guard i s
false
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c IF r20 dspuquadaddui r60 r70 → r90 r90 ← 0xff38c800
01531
rsrc1 01531
rsrc2
031
rdest
+
+
+
+
23 7 23 7
71523
09 0909 09
Four full - precis ion
10-bit signed sums
Clip to [255..0]
unsigned unsigned unsigned unsigned signed signed signed signed
signed signed signed signed
unsigned unsigned unsigned unsigned
Clip to [255..0] Clip to [255..0] Clip to [255..0]
SEE ALSO
dspidualadd
dspuquadaddui
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-34
Clipped un signed subtract
SYNTAX
[ IF rguard ] dspusub rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← zero_ext32to64(rsrc1) – zero_ext32to 64(rsrc2)
if (signed)temp < 0 then
rdest ← 0
else
rdest ← temp<31:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 69
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the dspusub operation computes unsigned difference rsrc1–rsrc2, clips the result into the
unsigned range [232–1..0] (or [0xffffffff..0]), and stores the clipped value into rdest.
The dspusub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x1200, r40 = 0xff dspusub r30 r40 → r60 r60 ← 0x1101
r10 = 0, r30 = 0x1200, r40 = 0xff IF r10 dspusub r30 r40 → r80 no ch ange, since guard is false
r20 = 1, r30 = 0x1200, r40 = 0xff IF r20 dspusub r30 r40 → r100 r100 ← 0x1101
r50 = 0, r90 = 1 dspusub r50 r90 → r110 r110 ← 0
r70 = 0x80000001, r80 = 0xffffffff dspusub r70 r80 → r120 r120 ← 0
031
rsrc1 031
rsrc2
031
rdest
−
032
Clip to [232–1..0]
unsigned unsigned
Full-precision
33-bit result signed
unsigned
SEE ALSO
dspiabs dspiadd dspimul
dspisub dspuadd dspumul
dspusub
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-35 PRELIMINARY SPECIFICATION
dualasr Dual-16 arithmetic shift right
SYNTAX
[ IF rguard ] dualasr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n < - rsrc2<3: 0>
rdest<31:31-n> <- rsrc1<31>
rdest<30-n:16> <- rsrc1<30:16 +n>
rdest<15:15-n> <- rsrc1<15>
rdest<14-n:0> <- rsrc1<14:n>
if rsrc2<31:4> != 0 {
rdest<3 1:16> <- rsrc1<31>
rdest<1 5:0> <- rsrc1< 15>
}
}
ATTRIBUTES
Function unit shifter
Operation code 102
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency 1
Issue slots 1,2
DESCRIPTION
The argument rsrc1 contains two 16-bit signed integers, rsrc1<31:16> and rsrc1<15:0>. Rsrc2 specifies an
unsigned shift amount, and the two 16-bit integers shifted right by this amount. The sign bits rsrc1<31> and rsrc1<15>
are r e plic ated as neede d wi th in each 1 6 -bit value f ro m t he left. If the rsrc2<31:4> value is not zero, then take t hi s as a
shift by 16 or more, i.e. extend th e sign bit into either result .
The dualasr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica t io n of the des tina t io n reg i s te r. If th e LS B of rg ua rd is 1, r d es t is w ri t te n; othe r wis e, rdes t is n ot chan ged.
EXAMPLES
Initial Values Operation Result
r30 = 0x70087008, r40 = 0x1 dualasr r30 r40 -> r50 r50 <- 0x38043804
r30 = 0x70087008, r40 = 0x2 dualasr r30 r40 -> r50 r50 <- 0x1c021c02
r10 = 0, r30 = 0x70087008, r40 = 0x2 IF r10 dualasr r30 r40 -> r50 no ch ange, since guard is false
r10 = 1, r30 = 0x70084008, r40 = 0x4 IF r10 dualasr r30 r40 -> r50 r50 <- 0x07000400
r10 = 1, r30 = 0x800c800c, r40 = 0x4 IF r10 dualasr r30 r40 -> r50 r50 <- 0xf800f800
r10 = 1, r30 = 0x700c700c, r40 = 0xf IF r10 dualasr r30 r40 -> r50 r50 <- 0x00000000
r10 = 1, r30 = 0x700c800c, r40 = 0xf IF r10 dualasr r30 r40 -> r50 r50 <- 0x0000ffff
r10 = 1, r30 = 0x800c700c, r40 = 0xf IF r10 dualasr r30 r40 -> r50 r50 <- 0xffff0000
r10 = 1, r30 = 0x800c700c, r40 = 0x10000000 IF r10 dualasr r30 r40 -> r50 r50 <- 0xffff0000
r10 = 1, r30 = 0x800c700c, r40 = 0x10 IF r10 dualasr r30 r40 -> r50 r50 <- 0xffff0000
031
rsrc1 031
rsrc2 n
Right shifter
0
31
rdest
28
SSS
Four LSBs of rsrc2
S
SS
15
Right shifter Four LSBs of rsrc2
SSS Lower 13 bits
Intermediate result
(example: n = 3) SSSS Lower 13 bits
Intermediate result
(example: n = 3) S
15 12
SSS S
SEE ALSO
asl asli asri lsl lsli lsr
lsri rol roli
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-36
Du al-1 6 c lip signe d to signed
SYNTAX
[ IF rguard ] dualiclipi rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<31:16> <- min(max(rscrc1<31:16>, -rsrc2<15:0>-1), rsrc2<15:0>)
rdest<15:0> <- min(max(rscrc1<15:0>, -rsrc2<15:0>-1), rsrc2<15:0>)
}
ATTRIBUTES
Function unit dspalu
Operation code 82
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency 2
Issue slots 1,3
DESCRIPTION
The argument rsrc1 contains two signed16-bit integers, rsrc1<31:16> and rsrc1<15:0>. Each integer value is clipped
into the signed inte ger rang e (-rsrc2 -1) to rsrc2. Th e value in rsrc2 contai ns a n unsigned inte ger an d must have the
value between 0 and 0x7fff inclusive.
The dualiclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x00800080, r40 = 0x7f dualiclipi r30 r40 -> r50 r50 <- 0x007f007f
r30 = 0x7ffff7ffff, r40 = 0x7ffe dualiclipi r30 r40 -> r50 r50 <- 0x7ffe7ffe
r10 = 0, r30 = 0x7ffff7ffff, r40 = 0x7ffe IF r10 dualiclipi r30 r40 -> r50 no change, since guard is false
r10 = 1, r30 = 0x12345678, r40 = 0xabc IF r10 dualiclipi r30 r40 -> r50 r50 <- 0x0abc0abc
r10 = 1, r30 = 0x80008000, r40 = 0x03ff IF r10 dualiclipi r30 r40 -> r50 r50 <- 0xfc00fc00
r10 = 1, r30 = 0x800003fe, r40 = 0x03ff IF r10 dualiclipi r30 r40 -> r50 r50 <- 0xfc0003fe
r10 = 1, r30 = 0x000f03fe, r40 = 0x03ff IF r10 dualiclipi r30 r40 -> r50 r50 <- 0x000f03fe
SEE ALSO
iclipi uclipi dualuclipi
imin imax quadumax
quadumin
dualiclipi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-37 PRELIMINARY SPECIFICATION
dualuclipi D ual-16 clip signed to unsigned
SYNTAX
[ IF rguard ] dualuclipi rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<31:16> <- min(max(rscrc1<31:1 6>, 0), rsrc2<15:0>)
rdest<15:0> <- min(max(rscrc1<15:0>, 0), rsrc2<15:0>)
}
ATTRIBUTES
Function unit dspalu
Operation code 83
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency 2
Issue slots 1,3
DESCRIPTION
The argument rsrc1 contains two 16-bit signed integers, rsrc1<31:16> and rsrc1<15:0>. Each integer value is
clipped into the unsigned integer range 0 to rsrc2. The valu e in r src 2 contains an unsigned integer and must have the
value between 0 and 0 xffff inclusive.
The dualuclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica t io n of t h e des ti na t io n reg ister. If th e LS B of rg ua rd is 1, r d es t is w ritt e n; othe r wise, rd es t is n ot chan ge d.
EXAMPLES
Initial Values Operation Result
r30 = 0x00800080, r40 = 0x7f dualuclipi r30 r40 -> r50 r50 <- 0x007f007f
r30 = 0x7ffff7ffff, r40 = 0x7ffe dualuclipi r30 r40 -> r50 r50 <- 0x7ffe7ffe
r10 = 0, r30 = 0x7ffff7ffff, r40 = 0x7ffe IF r10 dualuclipi r30 r40 -> r50 no ch ange, since guard is false
r10 = 1, r30 = 0x12345678, r40 = 0xabc IF r10 dualuclipi r30 r40 -> r50 r50 <- 0x0abc0abc
r10 = 1, r30 = 0x80008000, r40 = 0x03ff IF r10 dualuclipi r30 r40 -> r50 r50 <- 0x00000000
r10 = 1, r30 = 0x800003fe, r40 = 0x03ff IF r10 dualuclipi r30 r40 -> r50 r50 <- 0x000003fe
r10 = 1, r30 = 0x000f03fe, r40 = 0x03ff IF r10 dualuclipi r30 r40 -> r50 r50 <- 0x000f03fe
SEE ALSO
iclipi uclipi dualiclipi
imin imax quadumax
quadumin
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-38
Floating-point absolute value
SYNTAX
[ IF rguard ] fabsval rsrc1 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 < 0 then
rdest ← –(float)rsrc1
else
rdest ← (float)rsrc1
}
ATTRIBUTES
Function unit falu
Operation code 115
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The fabsval operation computes the absolute value of the argument rsrc1 and stores the result into rdest. All
values are in IEEE single-precision floating-point format. If an argument is denormalized, zero is substituted for the
argument before computing the absolute value, and the IFZ flag in the PCSW is set. If fabsval causes an IEEE
exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can
be set as a side-e ffect of any floati ng-point operation but can only be reset by an explicit
writepcsw operation. The
update of the PCSW exception flags occurs at the same time as r dest i s w rit ten. I f any othe r fl oatin g -poin t com put e
operations update the PCSW at the same time, the net result in each exception flag is the logical OR of all
simultaneous updates ORed with the existing PCSW value for that exception flag.
The fabsvalflags operation computes the exception flags that would result from an individual fabsval.
The fabsval operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) fabsval r30 → r90 r90 ← 0x40400000 (3.0)
r35 = 0xbf800000 (-1.0) fabsval r35 → r95 r95 ← 0x3f800000 (1.0)
r40 = 0x00400000 (5.877471754e-39) fabsval r40 → r100 r100 ← 0x0 (+0.0), IFZ s et
r45 = 0xffffffff (QNaN) fabsval r45 → r105 r105 ← 0xffffffff (QNaN)
r50 = 0xffbfffff (SNaN) fabsval r50 → r110 r110 ← 0xffffffff (QNaN), INV set
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38) IF r10 fabsval r55 → r115 no ch ange, since guard is fa l se
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38) IF r20 fabsval r55 → r120 r120 ← 0x7f7fffff (3.402823466e+38)
SEE ALSO
iabs dspiabs dspidualabs
fabsvalflags readpcsw
writepcsw
fabsval
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-39 PRELIMINARY SPECIFICATION
IEE E status fl a gs from floatin g- po int absolute
value
SYNTAX
[ IF rguard ] fabsvalflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags(abs_val((float)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 116
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The fabsvalflags operation computes the IEEE exceptions that would result from computing the absolute
value of rsrc1 and writes a bit vector representing the exception flags into rdest. The argument value is in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the I EEE excep tion bits in th e PCSW. T he excepti on fl ags in PC SW are left unc hanged by this o peration . If r src1 is
denormalized, the IFZ bit in the result is set.
The fabsvalflags oper at io n optio n a lly take s a gu ar d , spec ified i n rguard. If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) fabsvalflags r30 → r90 r90 ← 0x0
r35 = 0xbf800000 (-1.0) fabsvalflags r35 → r95 r95 ← 0x0
r40 = 0x00400000 (5.877471754e-39) fabsvalflags r40 → r100 r100 ← 0x20 (IFZ)
r45 = 0xffffffff (QNaN) fabsvalflags r45 → r105 r105 ← 0x0
r50 = 0xffbfffff (SNaN) fabsvalflags r50 → r110 r110 ← 0x10 (INV)
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38) IF r10 fabsvalflags r55 → r115 no change, since guard i s false
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38) IF r20 fabsvalflags r55 → r120 r120 ← 0x0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fabsval faddflags readpcsw
fabsvalflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-40
Floating-point add
SYNTAX
[ IF rguard ] fadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← (float)rsrc1 + (f loat)rsrc2
ATTRIBUTES
Function unit falu
Operation code 22
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The fadd operation computes the sum rsrc1+rsrc2 and stores the result into rdest. A ll va lu es a re in IEEE si ngle -
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the sum, and the I FZ flag in the PCSW is set. If
the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fadd causes an
IEEE exception, the correspondin g exception flags in the PCSW are set. Th e PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw
oper ation. The upda t e of th e PCSW ex ception flags occ u rs a t th e sa me time as rdest is written. If any other floating-
poi nt comp ute op er a tio ns up da te the PCSW at the s am e ti me, the net resu lt in each e x cep t ion flag is t he logi ca l OR of
all sim ultaneo us up da tes O Red w ith the exis ting P CS W value for that ex ce pt ion flag .
The faddflags operation computes the exception flags that would result from an individual fadd.
The fadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fadd r60 r30 → r90 r90 ← 0xc0000000 (–2.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fadd r40 r60 → r95 r95 ← 0x00000000 (0.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r10 fadd r40 r80 → r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r20 fadd r40 r80 → r110 r110 ← 0x40400000 (3.0), INX flag set
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fadd r40 r81 → r111 r111 ← 0x40400000 (3.0), IFZ flag set
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x80800000 (–1.175494351e-38) fadd r82 r83 → r112 r112 ← 0x00000000 (0.0), OFZ, UNF, INX
flags set
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF) fadd r84 r85 → r113 r113 ← 0xffffffff (QNaN), INV flag set
r70 = 0x7f7fffff (3.402823466e+38) fadd r70 r70 → r120 r120 ← 0x7f800000 (+INF), OVF,
INX flags set
r80 = 0x00800000 (1.763241526e–38) fadd r80 r80 → r125 r125 ← 0x01000000 (2.350988702e–38)
SEE ALSO
faddflags iadd dspiadd
dspidualadd readpcsw
writepcsw
fadd
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-41 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point add
SYNTAX
[ IF rguard ] faddflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 + (float)rsrc2)
ATTRIBUTES
Function unit falu
Operation code 112
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The faddflags operation c omput es the I EEE exceptio ns that wo uld resul t from computin g the s um rsrc1+rsrc2
and s tor e s a bi t ve ct or re p rese nt in g the exce pt io n fla g s int o r dest. The argument values are in IEEE single-precision
floating-point format; the result is an integer bit vector. The bit vector stored in rdest ha s th e sam e forma t as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according
to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing the
sum, and the IFZ bit in the result is set. If the sum would be denormalized, th e OFZ bit in th e r esult is set.
The faddflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a gu ar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r10 = 0x7f7fffff (3.402823466e+38),
r20 = 0x3f800000 (1.0) faddflags r10 r20 → r60 r60 ← 0x2 (INX)
r30 = 0,
r10 = 0x7f7fffff (3.402823466e+38) IF r30 faddflags r10 r10 → r50 no ch ange, since guard is false
r40 = 1,
r10 = 0x7f7fffff (3.402823466e+38) IF r40 faddflags r10 r10 → r70 r70 ← 0xa (OVF INX)
r80 = 0x00a00000 (1.469367939e–38),
r81 = 0x80800000 (–1.17549435e–38) faddflags r80 r81 → r100 r100 ← 0x46 (OFZ UNF INX)
r95 = 0x7f800000 (+INF),
r96 = 0xff800000 (–INF) faddflags r95 r96 → r105 r105 ← 0x10 (INV)
r98 = 0x40400000 (3.0),
r99 = 0x00400000 (5.877471754e–39) faddflags r98 r99 → r111 r111 ← 0x20 (IFZ)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fadd fsubflags readpcsw
faddflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-42
Floa ting- poi nt di vi de
SYNTAX
[ IF rguard ] fdiv rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← (float)rsrc1 / (float)rsrc2
ATTRIBUTES
Function unit ftough
Operation code 108
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 17
Recovery 16
Issue slots 2
DESCRIPTION
The fdiv operation computes the quotient rsrc1÷rsrc2 and stores the result into rdest. All values are in IEEE
s ingle-precision floating-point format. Rounding is acc or ding to the IEEE roundin g mode bits in PCSW. If an argument
is denor malized, zero is substitut ed for the argument before computing the quotient, and the IFZ flag in the PCSW is
s et. If the result is den ormaliz ed, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
fdiv causes
an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw
oper ation. The upda t e of th e PCSW ex ception flags occ u rs a t th e sa me time as rdest is written. If any other floating-
poi nt comp ute op er a tio ns up da te the PCSW at the s am e ti me, the net resu lt in each e x cep t ion flag is t he logi ca l OR of
all sim ultaneo us up da tes O Red w ith the exis ting P CS W value for that ex ce pt ion flag .
The fdivflags operation computes the exception flags that would result from an individual fdiv.
The fdiv operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fdiv r60 r30 → r90 r90 ← 0xc0400000 (–3.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fdiv r40 r60 → r95 r95 ← 0xbf800000 (–1.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r10 fdiv r40 r80 → r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r20 fdiv r40 r80 → r110 r110 ← 0x7f400000 (2.552117754e38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fdiv r40 r81 → r111 r111 ← 0x7f800000 (+INF), IFZ, DBZ flags set
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x80800000 (–1.175494351e–38) fdiv r82 r83 → r112 r112 ← 0xbfc00000 (-1.5)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF) fdiv r84 r85 → r113 r113 ← 0xffffffff (QNaN), INV flag set
r70 = 0x7f7fffff (3.402823466e+38) fdiv r70 r70 → r120 r120 ← 0x3f800000 (1.0)
r80 = 0x00800000 (1.763241526e–38) fdiv r80 r80 → r125 r125 ← 0x3f800000 (1.0)
r75 = 0x40400000 (3.0),
r76 = 0x0 (0.0) fdiv r75 r76 → r126 r126 ← 0x7f800000 (+INF), DBZ flag set
SEE ALSO
fdivflags readpcsw
writepcsw
fdiv
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-43 PRELIMINARY SPECIFICATION
IEEE status flags from floating-point divide
SYNTAX
[ IF rguard ] fdivflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 / (float)rsrc2)
ATTRIBUTES
Function unit ftough
Operation code 109
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 17
Recovery 16
Issue slots 2
DESCRIPTION
The fdivflags operation computes the IEEE exceptions that would result from computing the quotient
rsrc1÷rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
for mat a s the I EEE except ion bit s in th e PCSW. The except ion fla gs in P CSW are left unc hanged by this o peration .
Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted
before computi ng the qu otien t, and the IFZ bit in t he r esult is set. If the quotient would be denormali zed , the OFZ bit i n
the result is set.
The fdivflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x7f7fffff (3.402823466e+38),
r40 = 0x3f800000 (1.0) fdivflags r30 r40 → r100 r100 ← 0
r10 = 0,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
IF r10 fdivflags r50 r60 → r110 no cha nge, since guard is false
r20 = 1,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
IF r20 fdivflags r50 r60 → r111 r111 ← 0xa (OVF INX)
r70 = 0x40400000 (3.0),
r80 = 0x00400000 (5.877471754e–39) fdivflags r70 r80 → r112 r112 ← 0x21 (IFZ DBZ)
r85 = 0x7f800000 (+INF),
r86 = 0xff800000 (–INF) fdivflags r85 r86 → r113 r113 ← 0x10 (INV)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fdiv faddflags readpcsw
fdivflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-44
Floating-point compare equal
SYNTAX
[ IF rguard ] feql rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 = (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 148
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The feql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
argument, rsrc2; othe rw is e , r dest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If feql causes an IEEE exception, the corresponding exception
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point oper a tio n but c an on ly be res et by a n exp li ci t writepcsw operation. The update of the PCSW exception flags
occurs at the same time as rdest is wr itten. If any other floating-point compute operat ions up date the PC SW at the
same time, the net r esult in each except ion flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
The feqlflags operation computes the exception flags that would result from an individual feql.
The feql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) feql r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) feql r30 r30 → r90 r90 ← 1
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 feql r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 feql r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) feql r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) feql r30 r61 → r121 r121 ← 0
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) feql r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) feql r60 r65 → r126 r126 ← 0, IFZ flag set
r50 = 0x7f800000 (+INF) feql r50 r50 → r127 r127 ← 1
SEE ALSO
ieql feqlflags fneq
readpcsw writepcsw
feql
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-45 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
equal
SYNTAX
[ IF rguard ] feqlflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 = (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 149
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The feqlflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The feqlflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) feqlflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) feqlflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 feqlflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 feqlflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) feqlflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) feqlflags r30 r61 → r121 r121 ← 0
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) feqlflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) feqlflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) feqlflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
feql ieql fgtrflags
readpcsw
feqlflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-46
Floating-p oint compare great er or equal
SYNTAX
[ IF rguard ] fgeq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 >= (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 146
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fgeq oper atio n set s the dest in ation reg iste r, r dest, to 1 if the fi rst arg ument, r src1, is greater than or equal to
th e se co nd a rgume n t, rsrc2; otherwise, rdest is set to 0. Th e argument s are treated as IEEE single-precision floating-
point values; the result is an integer. If an argument is denormalized, zero is substituted for the argument before
computing the comparison, and the IFZ flag in the PCSW is set. If fgeq causes an IEEE exception, the
corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a
side -ef fect of an y f loati ng -poin t op eratio n but c an on ly be re set by an explic it writepcsw operation. The update of
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update t h e PCSW at t he sa me time, th e net re sult in ea ch exc eption flag is t h e l og ical OR of all sim ultaneous upd a t es
ORed with the existi ng PCSW value for that exception flag.
The fgeqflags operation computes the exception flags that would result from an individual fgeq.
The fgeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fgeq r30 r40 → r80 r80 ← 1
r30 = 0x40400000 (3.0) fgeq r30 r30 → r90 r90 ← 1
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fgeq r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fgeq r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fgeq r30 r60 → r120 r120 ← 1
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fgeq r30 r61 → r121 r121 ← 0, INV flag set
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fgeq r50 r55 → r125 r125 ← 1
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fgeq r60 r65 → r126 r126 ← 1, IFZ flag set
r50 = 0x7f800000 (+INF) fgeq r50 r50 → r127 r127 ← 1
SEE ALSO
igeq fgeqflags fgtr
readpcsw writepcsw
fgeq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-47 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
great er or equal
SYNTAX
[ IF rguard ] fgeqflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 >= (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 147
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fgeqflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1>=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The fgeqflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fgeqflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fgeqflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fgeqflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fgeqflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fgeqflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fgeqflags r30 r61 → r121 r121 ← 0x10 (INV)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fgeqflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fgeqflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) fgeqflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fgeq igeq fgtrflags
readpcsw
fgeqflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-48
Floating-point compare greater
SYNTAX
[ IF rguard ] fgtr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 > (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 144
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fgtr operation sets the destination register, rdest, to 1 if the first ar gument , r src1, is grea ter tha n the seco nd
argument, rsrc2; othe rw is e , r dest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If fgtr causes an IEEE exception, the corresponding exception
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point oper a tio n but c an on ly be res et by a n exp li ci t writepcsw operation. The update of the PCSW exception flags
occurs at the same time as rdest is wr itten. If any other floating-point compute operat ions up date the PC SW at the
same time, the net r esult in each except ion flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
The fgtrflags operation computes the exception flags that would result from an individual fgtr.
The fgtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fgtr r30 r40 → r80 r80 ← 1
r30 = 0x40400000 (3.0) fgtr r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fgtr r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fgtr r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fgtr r30 r60 → r120 r120 ← 1
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fgtr r30 r61 → r121 r121 ← 0, INV flag set
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fgtr r50 r55 → r125 r125 ← 1
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fgtr r60 r65 → r126 r126 ← 1, IFZ flag set
r50 = 0x7f800000 (+INF) fgtr r50 r50 → r127 r127 ← 0
SEE ALSO
igtr fgtrflags fgeq
readpcsw writepcsw
fgtr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-49 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
greater
SYNTAX
[ IF rguard ] fgtrflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 > (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 145
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fgtrflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1>rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The fgtrflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a gu ar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fgtrflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fgtrflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fgtrflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fgtrflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fgtrflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fgtrflags r30 r61 → r121 r121 ← 0x10 (INV)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fgtrflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fgtrflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) fgtrflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fgtr igtr fgeqflags
readpcsw
fgtrflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-50
Floating-point compare less-than or equal
pseudo-op for fgeq
SYNTAX
[ IF rguard ] fleq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 <= (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 146
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fleq operation is a pseudo operation transformed by the scheduler into an fgeq with the arguments
exchanged (fleq’s rsrc1 is fgeq’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The fleq operation sets the destination register, r dest, to 1 if t he first a rgume nt, rsrc1, is less than or equal to the
s econd argume nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision float ing -poin t
v alues; the result is an integer. If an argument is denormalized, zero is substitut ed for the argument before computing
the comp ar is on , and th e IF Z fla g i n the P CSW is set . If fleq ca us es an IE EE excep tion, the corr esp onding exc e pt i on
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point oper a tio n but c an on ly be res et by a n exp li ci t writepcsw operation. The update of the PCSW exception flags
occurs at the same time as rdest is wr itten. If any other floating-point compute operat ions up date the PC SW at the
same time, the net r esult in each except ion flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
The fleqflags operation computes the exception flags that would result from an individual fleq.
The fleq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fleq r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fleq r30 r30 → r90 r90 ← 1
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fleq r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fleq r60 r30 → r110 r110 ← 1
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fleq r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fleq r30 r61 → r121 r121 ← 0, INV flag set
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fleq r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fleq r60 r65 → r126 r126 ← 0, IFZ flag set
r50 = 0x7f800000 (+INF) fleq r50 r50 → r127 r127 ← 1
SEE ALSO
ileq fgeq fleqflags
readpcsw writepcsw
fleq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-51 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
less -th an or equ al
pseudo-op for fgeqflags
SYNTAX
[ IF rguard ] fleqflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 <= (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 147
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fleqflags operation is a pseudo operation transformed by the scheduler into an fgeqflags with the
arguments exchanged (fleqflags’s rsrc1 is fgeqflags’s rsrc2 and vice versa). (Note: pseudo operations
ca nn ot b e us ed in assembl y so u r c e f iles .)
The fleqflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1<=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The fleqflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fleqflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fleqflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fleqflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fleqflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fleqflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fleqflags r30 r61 → r121 r121 ← 0x10 (INV)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fleqflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fleqflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) fleqflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fleq ileq fgeqflags
readpcsw
fleqflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-52
Floating-point compare less-than
pseudo-op for fgtr
SYNTAX
[ IF rguard ] fles rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 < (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 144
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fles operation is a pseudo operation transformed by the scheduler into an fgtr with the arguments
exchanged (fles’s rsrc1 is fgtr’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The fles operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the second
argument, rsrc2; othe rw is e , r dest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If fles causes an IEEE exception, the corresponding exception
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point oper a tio n but c an on ly be res et by a n exp li ci t writepcsw operation. The update of the PCSW exception flags
occurs at the same time as rdest is wr itten. If any other floating-point compute operat ions up date the PC SW at the
same time, the net r esult in each except ion flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
The flesflags operation computes the exception flags that would result from an individual fles.
The fles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fles r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fles r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fles r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fles r60 r30 → r110 r110 ← 1
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fles r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fles r30 r61 → r121 r121 ← 0, INV flag set
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fles r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fles r60 r65 → r126 r126 ← 0, IFZ flag set
r50 = 0x7f800000 (+INF) fles r50 r50 → r127 r127 ← 0
SEE ALSO
iles fgtr flesflags
readpcsw writepcsw
fles
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-53 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
less-than
pseudo-op for fgtrflags
SYNTAX
[ IF rguard ] flesflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 < (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 145
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The flesflags operation is a pseudo operation transformed by the scheduler into an fgtrflags with the
arguments exchanged (flesflags’s rsrc1 is fgtrflags’s rsrc2 and vice versa). (Note: pseudo operations
ca nn ot b e us ed in assembl y so u r c e f iles .)
The flesflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1<rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The flesflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) flesflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) flesflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 flesflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 flesflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) flesflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) flesflags r30 r61 → r121 r121 ← 0x10 (INV)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) flesflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) flesflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) flesflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fles iles fleqflags
readpcsw
flesflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-54
Floating-point multiply
SYNTAX
[ IF rguard ] fmul rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← (float)rsrc1 × (float)rsrc2
ATTRIBUTES
Function unit ifmul
Operation code 28
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
The fmul operatio n co mpu tes th e pr odu ct rsrc1×rsrc2 and stores the result into rdest. All values are in IEEE single-
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
deno rm alize d, zero is su bstitute d f o r the argument before computing the product, and the IFZ flag in the PCSW is set.
If the result is denormal ized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fmul causes an
IEEE exception, the correspondin g exception flags in the PCSW are set. Th e PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw
oper ation. The upda t e of th e PCSW ex ception flags occ u rs a t th e sa me time as rdest is written. If any other floating-
poi nt comp ute op er a tio ns up da te the PCSW at the s am e ti me, the net resu lt in each e x cep t ion flag is t he logi ca l OR of
all sim ultaneo us up da tes O Red w ith the exis ting P CS W value for that ex ce pt ion flag .
The fmulflags operation computes the exception flags that would result from an individual fmul.
The fmul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fmul r60 r30 → r90 r90 ← 0xc0400000 (-3.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fmul r40 r60 → r95 r95 ← 0xc1100000 (-9.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r10 fmul r40 r80 → r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r20 fmul r40 r80 → r105 r105 ← 0x1400000 (3.52648305e-38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38) fmul r41 r80 → r110 r110 ← 0x0, OFZ, UNF, INX flags set
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0) fmul r42 r43 → r106 r106 ← 0xffffffff (QNaN), INV flag set
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fmul r40 r81 → r111 r111 ← 0, IFZ flag set
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38) fmul r82 r83 → r112 r112 ← 0, UNF, INX flag set
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF) fmul r84 r85 → r113 r113 ← 0xff800000 (-INF)
r70 = 0x7f7fffff (3.402823466e+38) fmul r70 r70 → r120 r120 ← 0x7f800000, OVF, INX flags set
r80 = 0x00800000 (1.763241526e–38) fmul r80 r80 → r125 r125 ← 0, UNF, INX flag set
SEE ALSO
imul umul dspimul
dspidualmul fmulflags
readpcsw writepcsw
fmul
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-55 PRELIMINARY SPECIFICATION
IEE E status flags from flo atin g- po int m u ltip l y
SYNTAX
[ IF rguard ] fmulflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 × (float)rsrc2)
ATTRIBUTES
Function unit ifmul
Operation code 143
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
The fmulflags operation computes the IEEE exceptions that would result from computing the product
rsrc1×rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
for mat a s the I EEE except ion bit s in th e PCSW. The except ion fla gs in P CSW are left unc hanged by this o peration .
Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted
befor e co m p u tin g the pr o du ct , and the I F Z bit in th e r e su lt is set. If the prod uct would be denormalized , t h e OFZ bi t in
the result is set.
The fmulflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fmulflags r60 r30 → r90 r90 ← 0
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fmulflags r40 r60 → r95 r95 ← 0
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r10 fmulflags r40 r80 → r100 no cha nge, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38) IF r20 fmulflags r40 r80 → r105 r105 ← 0
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38) fmulflags r41 r80 → r110 r110 ← 0x46 (OFZ UNF INX)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0) fmulflags r42 r43 → r106 r106 ← 0x10 (INV)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fmulflags r40 r81 → r111 r111 ← 0x20 (IFZ)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38) fmulflags r82 r83 → r112 r112 ← 0x06 (UNF INX)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF) fmulflags r84 r85 → r113 r113 ← 0
r70 = 0x7f7fffff (3.402823466e+38) fmulflags r70 r70 → r120 r120 ← 0x0a (OV F INX)
r80 = 0x00800000 (1.763241526e–38) fmulflags r80 r80 → r125 r125 ← 0x06 (UNF INX)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fmul faddflags readpcsw
fmulflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-56
Floating-point compare not equal
SYNTAX
[ IF rguard ] fneq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 != (float)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit fcomp
Operation code 150
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fneq operation sets the destination register, rdest, to 1 if the first a rgum ent, rsrc1, is not eq ual t o the s e cond
argument, rsrc2; othe rw is e , r dest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If fneq causes an IEEE exception, the corresponding exception
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point oper a tio n but c an on ly be res et by a n exp li ci t writepcsw operation. The update of the PCSW exception flags
occurs at the same time as rdest is wr itten. If any other floating-point compute operat ions up date the PC SW at the
same time, the net r esult in each except ion flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
The fneqflags operation computes the exception flags that would result from an individual fneq.
The fneq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fneq r30 r40 → r80 r80 ← 1
r30 = 0x40400000 (3.0) fneq r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fneq r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fneq r60 r30 → r110 r110 ← 1
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fneq r30 r60 → r120 r120 ← 1
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fneq r30 r61 → r121 r121 ← 0
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fneq r50 r55 → r125 r125 ← 1
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fneq r60 r65 → r126 r126 ← 1, IFZ flag set
r50 = 0x7f800000 (+INF) fneq r50 r50 → r127 r127 ← 0
SEE ALSO
ineq feql fneqflags
readpcsw writepcsw
fneq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-57 PRELIMINARY SPECIFICATION
IEEE stat us fl ags from floating-point compa r e
not equal
SYNTAX
[ IF rguard ] fneqflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 != (float)rsrc2)
ATTRIBUTES
Function unit fcomp
Operation code 151
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fneqflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1!=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single -prec ision floating-point format; the result is an intege r bit ve ctor. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denorm alize d, z er o is substituted before c omputing the comp aris on, a nd the IFZ bit in the result is set.
The fneqflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0), r40 = 0 (0.0) fneqflags r30 r40 → r80 r80 ← 0
r30 = 0x40400000 (3.0) fneqflags r30 r30 → r90 r90 ← 0
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r10 fneqflags r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0) IF r20 fneqflags r60 r30 → r110 r110 ← 0
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0) fneqflags r30 r60 → r120 r120 ← 0
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN) fneqflags r30 r61 → r121 r121 ← 0
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF) fneqflags r50 r55 → r125 r125 ← 0
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39) fneqflags r60 r65 → r126 r126 ← 0x20 (IFZ)
r50 = 0x7f800000 (+INF) fneqflags r50 r50 → r127 r127 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fneq ineq fleqflags
readpcsw
fneqflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-58
Sign of floating-point value
SYNTAX
[ IF rguard ] fsign rsrc1 → rdest
FUNCTION
if rguard then {
if (float)rsrc1 = 0.0 then
rdest ← 0
else if (float)rsrc1 < 0.0 then
rdest ← 0xffffffff
else
rdest ← 1
}
ATTRIBUTES
Function unit fcomp
Operation code 152
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fsign operation sets the destination register, rdest, to either 0, 1, or –1 depending on the sign of the argument
in r src1. rdest is set to 0 if rsrc1 is equal to zero, to 1 if rsrc1 is positive, or to –1 if r src1 is negative. The argument is
tre ate d a s an IEEE sing le -pr e c is io n flo ating - p oi nt value; th e r e s ult is an integer. If the argument is denormalized, zero
is substituted b efore com puting t he comparison, and the IFZ flag i n the P CSW is set; t hus, th e res ult of fsign for a
denormalized argument is 0. If fsign causes an IEEE exception, the corresponding exception flags in the PCSW are
set . T he PCSW ex c eption flags ar e s t i cky : the fl ags can be set a s a side -e ff ect of any floating-point operation but ca n
only be r ese t by an expl ic it writepcsw operation. The update of the PCSW exception flags occurs at the same time
as r dest is writt en. If any other floating-point compute operations update the PCSW at the same time, th e n et re sult i n
each exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that
exception flag.
The fsignflags op eratio n com p utes th e exce ption f lags th at woul d resul t from a n ind iv idua l fsign.
The fsign operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) fsign r30 → r100 r100 ← 1
r40 = 0xbf800000 (-1.0) fsign r40 → r105 r105 ← 0xffffffff (-1)
r50 = 0x80800000 (-1.175494351e-38) fsign r50 → r110 r110 ← 0xffffffff (-1)
r60 = 0x80400000 (-5.877471754e-39) fsign r60 → r115 r115 ← 0, IFZ flag set
r10 = 0, r70 = 0xffffffff (QNaN) IF r10 fsign r70 → r116 no change, since guard i s false
r20 = 1, r70 = 0xffffffff (QNaN) IF r20 fsign r70 → r117 r117 ← 0, INV flag set
r80 = 0xff800000 (-INF) fsign r80 → r120 r120 ← 0xffffffff (-1)
SEE ALSO
fsignflags readpcsw
writepcsw
fsign
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-59 PRELIMINARY SPECIFICATION
IEEE sta tus flags fr om fl oat i ng -po int sign
SYNTAX
[ IF rguard ] fsignflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags(sign((float)rsrc1))
ATTRIBUTES
Function unit fcomp
Operation code 153
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The fsignflags operation computes the IEEE except ions that would result from computing the sign of rsrc1 and
st ore s a bi t vecto r repr ese n ti ng the ex ce p t io n flags into rdest. The arg u ment value is i n IEEE single -prec is ion flo ating -
point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If the argument is
denormalize d, zero i s su bstituted be fo re comp uting th e sign , and the IFZ bit in the resul t is s e t.
The fsignflags opera t io n opt ion al ly tak e s a gu ard , spe ci fie d in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) fsignflags r30 → r100 r100 ← 0
r40 = 0xbf800000 (-1.0) fsignflags r40 → r105 r105 ← 0
r50 = 0x80800000 (-1.175494351e-38) fsignflags r50 → r110 r110 ← 0
r60 = 0x80400000 (-5.877471754e-39) fsignflags r60 → r115 r115 ← 0x20 (IFZ)
r10 = 0, r70 = 0xffffffff (QNaN) IF r10 fsignflags r70 → r116 no change, since guard is f als e
r20 = 1, r70 = 0xffffffff (QNaN) IF r20 fsignflags r70 → r117 r117 ← 0x10 (INV)
r80 = 0xff800000 (-INF) fsignflags r80 → r120 r120 ← 0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fsign readpcsw
fsignflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-60
Floating-point square root
SYNTAX
[ IF rguard ] fsqrt rsrc1 → rdest
FUNCTION
if rguard then
rdest ← square_root(rsrc1)
ATTRIBUTES
Function unit ftough
Operation code 110
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 17
Recovery 16
Issue slots 2
DESCRIPTION
The fsqrt operation computes the squareroot of rsrc1 and stores the result into rdest. All values are in IEEE
s ingle-precision floating-point format. Rounding is acc or ding to the IEEE roundin g mode bits in PCSW. If an argument
is de no rmalize d, zero i s s ubs ti tu te d fo r th e ar gume nt before co m pu t in g t he s qua r eroot, and the I F Z fla g in the PC SW
is set. If t he result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fsqrt
causes an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw op erat ion. Th e upda te of the PC SW exce pti on fla gs occurs at the s a me tim e a s rdest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneo us upd a tes O R e d wit h th e exis ting P CS W value for that ex ce pt ion f lag.
The fsqrtflags op eratio n com p utes th e exce ption f lags th at woul d resul t from a n ind iv idua l fsqrt.
The fsqrt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0) fsqrt r60 → r90 r90 ← 0xffffffff (QNaN), INV flag set
r40 = 0x40400000 (3.0) fsqrt r40 → r95 r95 ← 0x3fddb3d7 (1.732051), INX flag set
r10 = 0, r40 = 0x40400000 (3.0) IF r10 fsqrt r40 → r100 no cha nge, since guard is false
r20 = 1, r40 = 0x40400000 (3.0) IF r20 fsqrt r40 → r110 r110 ← 0x3fddb3d7 (1.732051), INX flag set
r82 = 0x00c00000 (1.763241526e–38) fsqrt r82 → r112 r112 ← 0x201cc471 (1.32787105e-19), INX flag set
r84 = 0x7f800000 (+INF) fsqrt r84 → r113 r113 ← 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38) fsqrt r70 → r120 r120 ← 0x5f7fffff (1.8446743e19), INX flag set
r80 = 0x00400000 (5.877471754e-39) fsqrt r80 → r125 r125 ← 0, IFZ flag set
SEE ALSO
fsqrtflags readpcsw
writepcsw
fsqrt
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-61 PRELIMINARY SPECIFICATION
IEEE sta tus flags from floating-po int square r oo t
SYNTAX
[ IF rguard ] fsqrtflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags(square_root((float)rsrc1))
ATTRIBUTES
Function unit ftough
Operation code 111
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 17
Recovery 16
Issue slots 2
DESCRIPTION
The fsqrtflags operation computes the IEEE exceptions that would result from computing the squareroot of
rsrc1 and stores a bit vector representing the exception flags into rdest. The argument value is in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the IEEE ex cept io n bits in th e PCSW. The exceptio n flag s in PCSW are le ft unch ange d by this operat ion. Roundin g is
according to the IEEE rounding mode bits in PCSW. If the argument is denormalized, zero is substituted before
computing the squareroot, and the IFZ bit in the result is set. If the result is denormalized, and the OFZ fl ag in the
PCSW is set.
The fsqrtflags opera t io n opt ion al ly tak e s a gu ard , spe ci fie d in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0) fsqrtflags r60 → r90 r90 ← 0x10 (INV)
r40 = 0x40400000 (3.0) fsqrtflags r40 → r95 r95 ← 0x2 (INX)
r10 = 0, r40 = 0x40400000 (3.0) IF r10 fsqrtflags r40 → r100 no ch ange, since guard is fa l se
r20 = 1, r40 = 0x40400000 (3.0) IF r20 fsqrtflags r40 → r110 r110 ← 0x2 (INX)
r82 = 0x00c00000 (1.763241526e–38) fsqrtflags r82 → r112 r112 ← 0x2 (INX)
r84 = 0x7f800000 (+INF) fsqrtflags r84 → r113 r113 ← 0
r70 = 0x7f7fffff (3.402823466e+38) fsqrtflags r70 → r120 r120 ← 0x2 (INX)
r80 = 0x00400000 (5.877471754e-39) fsqrtflags r80 → r125 r125 ← 0x20 (IFZ)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fsqrt readpcsw
fsqrtflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-62
Floating-point subtract
SYNTAX
[ IF rguard ] fsub rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← (float)rsrc1 – (float)rsrc2
ATTRIBUTES
Function unit falu
Operation code 113
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The fsub operation computes the difference rsrc1–rsrc2 and writes the result into rdest. All values are in IEEE
s ingle-precision floating-point format. Rounding is acc or ding to the IEEE roundin g mode bits in PCSW. If an argument
is denormalized , zero is su bstituted for the ar gument before com puting the d iffe rence, a n d the IFZ flag in t he PCS W i s
s et. If the result is den ormaliz ed, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
fsub causes
an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw
oper ation. The upda t e of th e PCSW ex ception flags occ u rs a t th e sa me time as rdest is written. If any other floating-
poi nt comp ute op er a tio ns up da te the PCSW at the s am e ti me, the net resu lt in each e x cep t ion flag is t he logi ca l OR of
all sim ultaneo us up da tes O Red w ith the exis ting P CS W value for that ex ce pt ion flag .
The fsubflags operation computes the exception flags that would result from an individual fsub.
The fsub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fsub r60 r30 → r90 r90 ← 0xc0800000 (-4.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fsub r40 r60 → r95 r95 ← 0x40c00000 (6.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r10 fsub r40 r80 → r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r20 fsub r40 r80 → r110 r110 ← 0x40400000 (3.0), INX flag set
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fsub r40 r81 → r111 r111 ← 0x40400000 (3.0), IFZ flag set
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38) fsub r82 r83 → r112 r112 ← 0x0, OFZ, UNF and INX flags set
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF) fsub r84 r85 → r113 r113 ← 0xffffffff (QNaN), INV flag set
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38) fsub r70 r86 → r120 r120 ← 0x7f800000 (+INF), OVF, INX flag
set
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0 fsub r87 r30 → r125 r125 ← 0xffffffff (QNaN)
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0 fsub r87 r30 → r125 r125 ← 0xffffffff (QNaN), INV flag set
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38) fsub r83 r89 → r126 r126 ← 0x0, OFZ, UNF and INX flags set
SEE ALSO
fsubflags isub dspisub
dspidualsub readpcsw
writepcsw
fsub
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-63 PRELIMINARY SPECIFICATION
IEEE status flags from floating-point subtract
SYNTAX
[ IF rguard ] fsubflags rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float)rsrc1 – (float)rsrc2)
ATTRIBUTES
Function unit falu
Operation code 114
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The fsubflags op erat ion c ompu tes th e IEE E exce ption s tha t w oul d resu lt fro m com puti ng the di ffer enc e rsrc1–
rsrc2 and writes a bit vector representing the exception flags into rdest. The argument values are in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the IEEE ex cept io n bits in th e PCSW. The exceptio n flag s in PCSW are le ft unch ange d by this operat ion. Roundin g is
according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before
computing the difference, and the IFZ bit in the resu lt is set. If the di f fe rence would be d enormal ized, the OFZ bit in the
result is set .
The fsubflags o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0) fsubflags r60 r30 → r90 r90 ← 0
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0) fsubflags r40 r60 → r95 r95 ← 0
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r10 fsubflags r40 r80 → r100 no cha nge, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38) IF r20 fsubflags r40 r80 → r110 r110 ← 0x2 (INX)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39) fsubflags r40 r81 → r111 r111 ← 0x20 (IFZ)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38) fsubflags r82 r83 → r112 r112 ← 0x40 (OFZ)
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF) fsubflags r84 r85 → r113 r113 ← 0x10 (INV)
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38) fsubflags r70 r86 → r120 r120 ← 0xA (OVF,INX)
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0 fsubflags r87 r30 → r125 r125 ← 0x0
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0 fsubflags r87 r30 → r125 r125 ← 0x10 (INV)
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38) fsubflags r83 r89 → r126 r126 ← 0x4 (UNF)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
fsub faddflags readpcsw
fsubflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-64
Fu nne l-s hift 1byte
SYNTAX
[ IF rguard ] funshift1 rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest<31:8> ← rsrc1<23:0>
rdest<7:0> ← rsrc2<31:24>
ATTRIBUTES
Function unit shifter
Operation code 99
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As show n below, t he funshift1 operation effectiv ely shifts left b y on e byte t he 64-bit concatenation of rsrc1 and
rsrc2 and writes the most- significant 32 bits of the shifted result to rdest.
The funshift1 o per at ion op tion ally ta kes a g ua r d, sp ec ified i n rguard. If a gu ar d is presen t , its LSB c ontrols the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xaabbccdd, r40 = 0x11223344 funshift1 r30 r40 → r50 r50 ← 0xbbccdd11
r10 = 0, r40 = 0x11223344,
r30 = 0xaabbccdd IF r10 funshift1 r40 r30 → r60 no ch ange, since guard is f alse
r20 = 1, r40 = 0x11223344,
r30 = 0xaabbccdd IF r20 funshift1 r40 r30 → r70 r70 ← 0x223344aa
07152331
rsrc1 07152331
rsrc2
07152331
rdest
SEE ALSO
funshift2 funshift3 rol
funshift1
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-65 PRELIMINARY SPECIFICATION
Funnel-shift 2 bytes
SYNTAX
[ IF rguard ] funshift2 rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest<31:16> ← rsrc1<15:0>
rdest<15:0> ← rsrc2<31:16>
ATTRIBUTES
Function unit shifter
Operation code 100
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the funshift2 operat ion effectively sh ift s le ft by two byt e s th e 64 -bit conc atena t i on of rsrc1 and
rsrc2 and writes the most- significant 32 bits of the shifted result to rdest.
The funshift2 o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xaabbccdd, r40 = 0x11223344 funshift2 r30 r40 → r50 r50 ← 0xccdd1122
r10 = 0, r40 = 0x11223344,
r30 = 0xaabbccdd IF r10 funshift2 r40 r30 → r60 no ch ange, since guard is f alse
r20 = 1, r40 = 0x11223344,
r30 = 0xaabbccdd IF r20 funshift2 r40 r30 → r70 r70 ← 0x3344aabb
07152331
rsrc1 07152331
rsrc2
07152331
rdest
SEE ALSO
funshift1 funshift3 rol
funshift2
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-66
Fu nnel-shif t 3 bytes
SYNTAX
[ IF rguard ] funshift3 rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest<31:24> ← rsrc1<7:0>
rdest<23:0> ← rsrc2<31:8>
ATTRIBUTES
Function unit shifter
Operation code 101
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the funshift3 operation effectively shifts left by three bytes the 64-bit concatenation of rsrc1
and r src2 and writes the most-significant 32 bits of the shifted result to rdest.
The funshift3 o per at ion op tion ally ta kes a g ua r d, sp ec ified i n rguard. If a gu ar d is presen t , its LSB c ontrols the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xaabbccdd, r40 = 0x11223344 funshift3 r30 r40 → r50 r50 ← 0xdd112233
r10 = 0, r40 = 0x11223344,
r30 = 0xaabbccdd IF r10 funshift3 r40 r30 → r60 no ch ange, since guard is f alse
r20 = 1, r40 = 0x11223344,
r30 = 0xaabbccdd IF r20 funshift3 r40 r30 → r70 r70 ← 0x44aabbcc
07152331
rsrc1 07152331
rsrc2
07152331
rdest
SEE ALSO
funshift1 funshift2 rol
funshift3
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-67 PRELIMINARY SPECIFICATION
Clipped sign ed absolute value
SYNTAX
[ IF rguard ] h_dspiabs r0 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc2 >= 0 then
rdest ← rsrc2
else if rsrc2 = 0x80000000 then
rdest ← 0x7fffffff
else
rdest ← –rsrc2
}
ATTRIBUTES
Function unit dspalu
Operation code 65
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The h_dspiabs operation computes the absolute value of rsrc2, clips the result into the range [0x0..0x7fffffff], and
stores the clipped value into rdest. All v a lu es ar e si gn ed int eg ers . Th is o per at ion req ui res a ze ro as fir s t arg um en t. The
programmer is advised to use the unary pseudo operation dspiabs instead.
The h_dspiabs o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff h_dspiabs r0 r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0x80000001 IF r10 h_dspiabs r0 r40 → r70 no ch ange, since guard is false
r20 = 1, r40 = 0x80000001 IF r20 h_dspiabs r0 r40 → r100 r100 ← 0x7fffffff
r50 = 0x80000000 h_dspiabs r0 r50 → r80 r80 ← 0x7fffffff
r90 = 0x7fffffff h_dspiabs r0 r90 → r110 r110 ← 0x7fffffff
SEE ALSO
h_dspiabs dspidualabs
dspiadd dspimul dspisub
dspuadd dspumul dspusub
h_dspiabs
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-68
Du al cl ipp ed abso lut e va lue of sign ed 16-b i t
halfwords
SYNTAX
[ IF rguard ] h_dspidualabs r0 rsrc2 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc2<15:0>)
temp2 ← sign_ext16to32(rsrc2<31:16>)
if temp1 = 0xffff8000 then temp1 ← 0x7fff
if temp2 = 0xffff8000 then temp2 ← 0x7fff
if temp1 < 0 then temp1 ← –temp1
if temp2 < 0 then temp2 ← –temp2
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 72
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The h_dspidualabs operation performs two 16-bit clipped, signed absolute value computations separately on
the high and low 16-bi t halfwords of rsrc2 . Both absolute values are clipped into the range [0x0..0x7fff] and wri tte n in to
the corresponding halfwords of rdest. All values are signed 16-bit integers. This operation requires a zero as first
argument. The programmer is advised to use the dspidualabs pseudo operation instead.
The h_dspidualabs oper at io n op ti onal ly ta k es a gu ard , sp ec if ied i n r guard. If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0032 h_dspidualabs r0 r30 → r60 r60 ← 0x00010032
r10 = 0, r40 = 0x80008001 IF r10 h_dspidualabs r0 r40 → r70 no change, since guard is false
r20 = 1, r40 = 0x80008001 IF r20 h_dspidualabs r0 r40 → r100 r100 ← 0x7fff7fff
r50 = 0x0032ffff h_dspidualabs r0 r50 → r80 r80 ← 0x00320001
r90 = 0x7fffffff h_dspidualabs r0 r90 → r110 r110 ← 0x7fff0001
SEE ALSO
dspidualabs dspiabs
dspidualadd dspidualmul
dspidualsub dspiabs
h_dspidualabs
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-69 PRELIMINARY SPECIFICATION
Hardware absolute value
SYNTAX
[ IF rguard ] h_iabs r0 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc2 < 0 then
rdest ← –rsrc2
else
rdest ← rsrc2
}
ATTRIBUTES
Function unit alu
Operation code 44
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The h_iabs operation computes the absolute value of rsrc2 and stores the result into rdest. The argument is a
signed integer; the result is an unsigned integer. Thi s op e ration requi res a ze ro as fi rst argume n t. The p rogr ammer is
advised t o use t h e iabs pseudo operation instead.
The h_iabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff h_iabs r0 r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0xfffffff4 IF r10 h_iabs r0 r40 → r80 no ch ange, since guard is false
r20 = 1, r40 = 0xfffffff4 IF r20 h_iabs r0 r40 → r90 r90 ← 0xc
r50 = 0x80000001 h_iabs r0 r50 → r100 r100 ← 0x7fffffff
r60 = 0x80000000 h_iabs r0 r60 → r110 r110 ← 0x80000000
r20 = 1 h_iabs r0 r20 → r120 r120 ← 1
SEE ALSO
iabs fabsval
h_iabs
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-70
Hardw are 16-b it sto re wi th disp lace men t
SYNTAX
[ IF rguard ] h_st16d(d) rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
mem[rsrc2 + d + (1 ⊕ bs)] ← rsrc1<7:0>
mem[rsrc2 + d + (0 ⊕ bs)] ← rsrc1<15:8>
}
ATTRIBUTES
Function unit dmem
Operation code 30
Nu mber of operands 2
Modifier 7 bits
Modifier ran ge –128..126 by 2
Latency n/a
Issue slots 4, 5
DESCRIPTION
The h_st16d operation stores the least-significant 16-bit halfword of rsrc1 into the memory locations pointed to by
the address in rsrc2 + d. The d value is an opcode modifier , must be in the range –128 and 126 inclusive, and must be
a multiple of 2. This store operation is performed as little-endian or big-endian depen di ng on t h e current setting of the
bytesex bit in the PCSW.
If h_st16d is misaligned (the memory address computed by rsrc2 + d is not a multiple of 2), the result of
h_st16d is undef ined, and t he MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if
th e TR P MSE (TRa P o n M is a lig ne d Stor e E x c ep tio n) bit in P CS W is 1, exce pti on proc es s ing wi l l b e requ es t e d o n the
next inte r ru ptible ju m p.
The h_st16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0 , h _s t 16 d has no side e ffec ts wh a teve r; in particular,
th e LRU and other status bits in t h e da t a cache are not affec ted.
EXAMPLES
Initial Values Operation Result
r10 = 0xcf e, r80 = 0x44332211 h_st16d(2) r80 r10 [0xd00] ← 0x22, [0xd01] ← 0x11
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd IF r50 h_st16d(–4) r70 r20 no ch ange, since guard is fa l se
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd IF r60 h_st16d(–4) r70 r30 [0xd02] ← 0xcc, [0xd03] ← 0xdd
SEE ALSO
st16 st16d st8 st8d st32
st32d readpcsw ijmpf
h_st16d
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-71 PRELIMINARY SPECIFICATION
Hardw are 32-b it sto re with disp lace men t
SYNTAX
[ IF rguard ] h_st32d(d) rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
mem[rsrc2 + d + (3 ⊕ bs)] ← rsrc1<7:0>
mem[rsrc2 + d + (2 ⊕ bs)] ← rsrc1<15:8>
mem[rsrc2 + d + (1 ⊕ bs)] ← rsrc1<24:16>
mem[rsrc2 + d + (0 ⊕ bs)] ← rsrc1<31:24>
}
ATTRIBUTES
Function unit dmem
Operation code 31
Nu mber of operands 2
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency n/a
Issue slots 4, 5
DESCRIPTION
The h_st32d operation stores all 32 bits of rsrc1 into the memory locations pointed to by the address in rsrc2 + d.
The d value is an opcode modi fier, must be in the range –256 and 252 inclusive, and must be a multiple of 4. This
store operation is pe rformed as little-endian or big-endian de pending on the cu rrent s etting of the bytesex b it in the
PCSW.
If h_st32d is misaligned (the memory address computed by rsrc2 + d is not a multiple of 4), the result of
h_st32d is undef ined, and t he MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if
th e TR P MSE (TRa P o n M is a lig ne d Stor e E x c ep tio n) bit in PC SW is 1, exce ption pr o c es s ing w il l b e requ es t e d o n the
next inte r ru ptible ju m p.
The h_st32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
mod ifi catio n o f t he ad dressed m em or y locatio n s (and the modification of cache if th e locations are cachea ble). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st32d has no side effects whatever; in
partic ul ar, the LRU and other stat us b its in t he da ta c ac he are not affe ct ed .
EXAMPLES
Initial Values Operation Result
r10 = 0xcfc, r80 = 0x44332211 h_st32d(4) r80 r10 [0xd00] ← 0x44, [0xd01] ← 0x33,
[0xd02] ← 0x22, [0xd03] ← 0x11
r50 = 0, r20 = 0xd0b,
r70 = 0xaabbccdd IF r50 h_st32d(–8) r70 r20 no ch ange, since guard is fa l se
r60 = 1, r30 = 0xd0c,
r70 = 0xaabbccdd IF r60 h_st32d(–8) r70 r30 [0xd04] ← 0xaa, [0xd05] ← 0xbb,
[0xd06] ← 0xcc, [0xd07] ← 0xdd
SEE ALSO
st32 st32d st16 st16d st8
st8d readpcsw ijmpf
h_st32d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-72
Hardw are 8-b it stor e with displacem en t
SYNTAX
[ IF rguard ] h_st8d(d) rsrc1 rsrc2
FUNCTION
if rguard then
mem[rsrc2 + d] ← rsrc1<7:0>
ATTRIBUTES
Function unit dmem
Operation code 29
Nu mber of operands 2
Modif ier 7 bits
Modifier ran ge –64..63
Latency n/a
Issue slots 4, 5
DESCRIPTION
The h_st8d operation stores the least-significant 8-bit byte of rsrc1 into the memory location pointed to by the
address formed from the sum rsrc2 + d. The value of the opcode mod ifier d must be in the range -6 4 and 63 inclusive.
Th is operat io n do es n o t depe nd on the by tes e x bit in the P CSW since onl y a single b yte is stored.
The h_st8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifi catio n of the addr e sse d mem ory loca ti o n ( and t he mo di fication of cac h e if the location is cacheable). If the LSB
of rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st8d has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r80 = 0x44332211 h_st8d(3) r80 r10 [0xd03] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd IF r50 h_st8d(-4) r70 r20 no ch ange, since guard is false
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd IF r60 h_st8d(-4) r70 r30 [0xcfe] ← 0xdd
SEE ALSO
st8 st8d st16 st16d st32
st32d
h_st8d
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-73 PRELIMINARY SPECIFICATION
Read c lock cy cle counte r, most -sig nif i can t wo rd
SYNTAX
[ IF rguard ] hicycles → rdest
FUNCTION
if rguard then
rdest ← CCCOUNT<63:32>
ATTRIBUTES
Function unit fcomp
Operation code 155
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
Refer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
hicycles operati on copies the high 32 bits of the slave re gister Cloc k Cyc le Co unter (CCCOUNT ) to the destination
register, rdest. The contents of the master counter are transferred to the slave CCCOUNT register only on a
successful interruptible jump and on processor reset. Thus, if cycles and hicycles are executed without
intervening interruptible jumps, the operation pair is guaranteed to be a coherent sample of the master clock-cycle
counter. The master coun ter increments on all cycles (processor-stall and non-stall) if PCSW. CS = 1; otherwise, the
co un t er i ncr em ents only on n on -stall cy cles .
The hicycles op eration optionally t akes a guard, spe cified in r guard. If a gua rd is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
CCCOUNT_HR = 0xabcdefff12345678 hicycles → r60 r60 ← 0xabcdefff
r10 = 0, CCCOUNT_HR = 0xabcdefff12345678 IF r10 hicycles → r70 no change, since guard is false
r20 = 1, CCCOUNT_HR = 0xabcdefff12345678 IF r20 hicycles → r100 r100 ← 0xabcdefff
SEE ALSO
cycles curcycles writepcsw
hicycles
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-74
Absolute v alu e
pseudo-op for h_iabs
SYNTAX
[ IF rguard ] iabs rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 < 0 then
rdest ← –rsrc1
else
rdest ← rsrc1
}
ATTRIBUTES
Function unit alu
Operation code 44
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The iabs operation is a pseudo operation transformed by the scheduler into an h_iabs with zero as the first
argument and a second argument equal to the iabs argument. (Note: pseudo operations cannot be used in
assembly source files.)
The iabs operation computes the absolute value of rsrc1 and stores the result into rdest. The argument is a signed
integer; the result is an unsigned integer.
The iabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff iabs r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0xfffffff4 IF r10 iabs r40 → r80 no ch ange, since guard is false
r20 = 1, r40 = 0xfffffff4 IF r20 iabs r40 → r90 r90 ← 0xc
r50 = 0x80000001 iabs r50 → r100 r100 ← 0x7fffffff
r60 = 0x80000000 iabs r60 → r110 r110 ← 0x80000000
r20 = 1 iabs r20 → r120 r120 ← 1
SEE ALSO
h_iabs dspiabs dspidualabs
fabsval
iabs
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-75 PRELIMINARY SPECIFICATION
Signed add
SYNTAX
[ IF rguard ] iadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 + rsrc2
ATTRIBUTES
Function unit alu
Operation code 12
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The iadd operation computes the sum rsrc1+rsrc2 and stores the result into rdest. The operands can be either
bot h sign ed o r un signed intege r s. N o overf lo w or unde rflo w dete c ti on i s perf orm ed .
The iadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 iadd r60 r60 → r80 r80 ← 0x200
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 iadd r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x100, r30 = 0xf11 IF r20 iadd r60 r30 → r90 r90 ← 0x1011
r70 = 0xffffff00, r40 = 0xffffff9c iadd r70 r40 → r100 r100 ← 0xfffffe9c
SEE ALSO
iaddi carry dspiadd
dspidualadd fadd
iadd
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-76
Add with immediate
SYNTAX
[ IF rguard ] iaddi(n) rsrc1 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 + n
ATTRIBUTES
Function unit alu
Operation code 5
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The iaddi oper ation s ums a sing le argu men t in r src1 and an immediate modifier n and stores the result in rdest.
The value of n must be between 0 and 127, inclusive.
The iaddi operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xf11 iaddi(127) r30 → r70 r70 ← 0xf90
r10 = 0, r40 = 0xffffff9c IF r10 iaddi(1) r40 → r80 no ch ange, since guard is f alse
r20 = 1, r40 = 0xffffff9c IF r20 iaddi(1) r40 → r90 r90 ← 0xffffff9d
r50 = 0x1000 iaddi(15) r50 → r120 r120 ← 0x100f
r60 = 0xfffffff0 iaddi(2) r60 → r110 r110 ← 0xfffffff2
r60 = 0xfffffff0 iaddi(17) r60 → r120 r120 ← 1
SEE ALSO
iadd carry
iaddi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-77 PRELIMINARY SPECIFICATION
S igned ave rag e
SYNTAX
[ IF rguard ] iavgonep rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← (sign_ext32to64(rsrc1) + sign_ext32to64(rsrc2) + 1) >> 1;
ATTRIBUTES
Function unit dspalu
Operation code 25
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As sh own b e low, the iavgonep operation returns the average of the two arguments. This operation computes the
su m rsrc1+rsrc2+1, shifts the sum right by 1 bit, and stores the result into rdest. The operands are signed integers.
The iavgonep operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x10, r70 = 0x20 iavgonep r60 r70 → r80 r80 ← 0x18
r10 = 0, r60 = 0x10, r30 = 0x20 IF r10 iavgonep r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x9, r30 = 0x20 IF r20 iavgonep r60 r30 → r90 r90 ← 0x15
r70 = 0xfffffff7, r40 = 0x2 iavgonep r70 r40 → r100 r100 ← 0xfffffffd
r70 = 0xfffffff7, r40 = 0x3 iavgonep r70 r40 → r100 r100 ← 0xfffffffd
031
rsrc1 031
rsrc2
031
rdest
+
032
Full precision
33-bit result S
S
sh ift down one bit
1
signedsigned
signed
signed
SEE ALSO
quadavg iadd
iavgonep
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-78
Signed select byte
SYNTAX
[ IF rguard ] ibytesel rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc2 = 0 then
rdest ← sign_ext8to32(rsrc1<7:0>)
else if rsrc2 = 1 then
rdest ← sign_ext8to32(rsrc1<15:8>)
else if rsrc2 = 2 then
rdest ← sign_ext8to32(rsrc1<23:16>)
else if rsrc2 = 3 then
rdest ← sign_ext8to32(rsrc1<31:24>)
}
ATTRIBUTES
Function unit alu
Operation code 56
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As shown bel ow, the ibytesel o pe ration s ele cts on e by te from the a rgume nt, r src1, si gn-exte nd s the byte t o 32
bits, and stores the result in rdest. The val ue of rsrc2 determin es which byte is selected, w ith rsrc2=0 selecting the
LSB of rsrc1 and rsrc2=3 selecting the MSB of rsrc1. If rsrc2 is not between 0 and 3 inclusive, the result of
ibytesel is undefined.
The ibytesel operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x44332211, r40 = 1 ibytesel r30 r40 → r50 r50 ← 0x00000022
r10 = 0, r60 = 0xddccbbaa, r70 = 2 IF r10 ibytesel r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0xddccbbaa, r70 = 2 IF r20 ibytesel r60 r70 → r90 r90 ← 0xffffffcc
r100 = 0xffffff7f, r11 0 = 0 ibytesel r100 r110 → r120 r120 ← 0x0000007f
01531
rsrc1 031
rsrc2
23 7 1
0
031
rdest 7
7
S
S
SSSSSSSSSSSSSSSSSSSSSSSS
3210
signed signed signed signed
signed
signed
SEE ALSO
ubytesel sex8 packbytes
ibytesel
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-79 PRELIMINARY SPECIFICATION
Clip signed to signed
SYNTAX
[ IF rguard ] iclipi rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← min(max(rsrc1, –rsrc2–1), rsrc2)
ATTRIBUTES
Function unit dspalu
Operation code 74
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The iclipi operation returns the value of rsrc1 clipped into the unsigned integer range (–rsrc2–1) to rsrc2,
inclusive. The argument rsrc1 is considered a signed integer; rsrc2 is considered an unsigned integer and must have
a va lu e be tween 0 a nd 0 x7fffffff inclusive.
The iclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x80, r40 = 0x7f iclipi r30 r40 → r50 r50 ← 0x7f
r10 = 0, r60 = 0x12345678,
r70 = 0xabc IF r10 iclipi r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0x12345678,
r70 = 0xabc IF r20 iclipi r60 r70 → r90 r90 ← 0xabc
r100 = 0x80000000, r110 = 0x3fffff iclipi r100 r110 → r120 r120 ← 0xffc00000
SEE ALSO
uclipi uclipu imin imax
iclipi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-80
Invalidate all instruction cache blocks
SYNTAX
[ IF rguard ] iclr
FUNCTION
if rguard then {
block ← 0
for all blocks in instruction cache {
icache_reset_valid_block(block)
block ← b lock + 1
}
}
ATTRIBUTES
Function unit branch
Operation code 184
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency n/a
Issue slots 2, 3, 4
DESCRIPTION
The iclr op eratio n re s ets t he vali d bi t s of al l block s in th e ins truc tion c ac he.
iclr does clear the valid bits of locked blocks. iclr does not change the replacement status of instr uction-cache
blocks.
iclr ensures coherency between caches and main memor y by discarding all pending prefetch operations.
The side effect time behavior of iclr is such that if instruction i performs an iclr, instructions i, i+1, i+2 will be
included in the disc ar d fr om the ins tr uc tion ca che, bu t i+3 will be retained.
The iclr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
iclr
r10 = 0 IF r10 iclr no change and no stall cycles, since
guard is false
r20 = 1 IF r20 iclr
SEE ALSO
dcb dinvalid
iclr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-81 PRELIMINARY SPECIFICATION
Identity
pseudo -op for iadd
SYNTAX
[ IF rguard ] ident rsrc1 → rdest
FUNCTION
if rguard then
rdest ← rsrc1
ATTRIBUTES
Function unit alu
Operation code 12
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ident operation is a pseudo operation transformed by the scheduler into an iadd with r 0 ( al ways contains 0 )
as the first argument and rsrc1 as the second. (Note: pseudo operations cannot be used in assembly source files.)
The ident operation copies the argument rsrc1 to rdest. It is used by the instruction scheduler to implement
register to register copying.
The ident operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x100 ident r30 → r40 r40 ← 0x100
r10 = 0, r50 = 0x12345678 IF r10 ident r50 → r60 no ch ange, since guard is false
r20 = 1, r50 = 0x12345678 IF r20 ident r50 → r70 r70 ← 0x12345678
SEE ALSO
iadd
ident
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-82
Signed compare equ al
SYNTAX
[ IF rguard ] ieql rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 = rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 37
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ieql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The ieql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ieql r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ieql r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x1000 IF r20 ieql r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 ieql r70 r40 → r100 r100 ← 0
r70 = 0x80000000 ieql r70 r70 → r110 r110 ← 1
SEE ALSO
igeq ueql ieqli ineq
ieql
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-83 PRELIMINARY SPECIFICATION
Sig ned com p are equ al wit h immedia te
SYNTAX
[ IF rguard ] ieqli(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 = n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 4
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ieqli ope ration sets th e destination register, rdest, to 1 if the first argument, rsrc1, is equal to the opcode
modifier, n; other wis e, rdest is set to 0 . The argum e n ts are tr eate d as signed intege r s.
The ieqli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ieqli(2) r30 → r80 r80 ← 0
r30 = 3 ieqli(3) r30 → r90 r90 ← 1
r30 = 3 ieqli(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ieqli(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ieqli(63) r40 → r100 r100 ← 0
r60 = 0xffffffc0 ieqli(-64) r60 → r120 r120 ← 1
SEE ALSO
ieql igeqi ueqli ineqi
ieqli
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-84
Sum of product s of signed 16-bit halfwords
SYNTAX
[ IF rguard ] ifir16 rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← sign_ext16to32(rsrc1<31:16>) ×sign_ext16to32(rsrc2<31:16>) +
sign_ext16to32(rsrc1<15:0>) ×sign_ext16to32(rsrc2<15:0>)
ATTRIBUTES
Function unit dspmul
Operation code 93
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, the ifir16 operation computes two separate products of the two pairs of corresponding 16-bit
halfwords of rsrc1 and rsrc2; the two products are summed, and the result is written to rdest. Al l v alu es ar e cons id ere d
signed; thus, the intermediate products and the final sum of products are signed. All int er mediate computations are
performed without loss of precision; the final sum of products is clipped into the range [0x80000000..0x7fffffff] before
being written into rdest.
The ifir16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x00020003, r40 = 0x00010002 ifir16 r30 r40 → r50 r50 ← 0x8
r10 = 0, r60 = 0xff9c0064, r70 = 0x0064ff9c IF r10 ifir16 r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0xff9c0064, r70 = 0x0064ff9c IF r20 ifir16 r60 r70 → r90 r90 ← 0xffffb1e0
r30 = 0x00020003, r70 = 0x0064ff9c ifir16 r30 r70 → r100 r100 ← 0xffffff9c
01531
rsrc1 01531
rsrc2
031
rdest
×
×+
signed signed signed signed
signed
032
Clip to [231–1..–231]
Full-precision
33-bit result signed
SEE ALSO
ifir8ii ifir8ui ufir8uu
ifir16
ifir16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-85 PRELIMINARY SPECIFICATION
Signe d sum of produc ts of sig ned bytes
SYNTAX
[ IF rguard ] ifir8ii rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← sign_ext8to32(rsrc1<31:24>) ×sign_ext8to32(rsrc2<31:24>) +
sign_ext8to32(rsrc1<23:16>) ×sign_ext8to32(rsrc2<23:1 6>) +
sign_ext8to32(rsrc1<15:8>) ×sign_ext8to32(rsrc2<15:8>) +
sign_ext8to32(rsrc1<7:0>) ×sign_ext8to32(rsrc2<7:0>)
ATTRIBUTES
Function unit dspmul
Operation code 92
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As sh o w n belo w, the ifir8ii o perat i on c omp ut e s four se para te produc t s of the four pai r s of co rre spondin g 8-b it
byte s o f r src1 an d rsrc2; the four products are summed, and the result is written to rdest. All values are considered
signed; thus, the intermediate products and the final sum of products are signed. All computations are performed
without loss of pr ecision.
The ifir8ii operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Re sult
r70 = 0x0afb14f6, r30 = 0x0a0a1414 ifir8ii r70 r30 → r90 r90 ← 0xfa
r10 = 0, r70 = 0x0afb14f6, r30 = 0x0a0a1414 IF r10 ifir8ii r70 r30 → r100 no ch ange, since guard is fa l se
r20 = 1, r80 = 0x649c649c, r40 = 0x9c649c64 IF r20 ifir8ii r80 r40 → r110 r110 ← 0xffff63c0
r50 = 0x80808080, r60 = 0xffffffff ifir8ii r50 r60 → r120 r120 ← 0x200
01531
rsrc1 01531
rsrc2
031
rdest
×
×
+
×
×
23 7 23 7
signed signed signed signed signed signed signed signed
signed
SEE ALSO
ifir8ui ufir8uu ifir16
ufir16
ifir8ii
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-86
Signe d sum of produc ts of un signed/signe d
bytes
SYNTAX
[ IF rguard ] ifir8ui rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(rsrc1<31:24>) ×sign_ext8to32(rsrc2<31:24>) +
zero_ext8to32(rsrc1<23:16>) ×sign_ext8to32(rsrc2<23:16>) +
zero_ext8to32(rsrc1<15:8>) ×sign_ext8to32(rsrc2< 15:8>) +
zero_ext8to32(rsrc1<7:0>) ×sign_ext8to32(rsrc2<7:0>)
ATTRIBUTES
Function unit dspmul
Operation code 91
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As sh o w n belo w, the ifir8ui o perat i on c omp ut e s four se para te produc t s of the four pai r s of co rre spondin g 8-b it
byte s o f r src1 an d rsrc2; the four products are summe d, and the result is written to r dest. The bytes from rsrc1 are
considered unsigned, but the bytes from rsrc2 are considered signed; thus, the intermediate products and the final
sum of pr od ucts a r e sign ed. Al l computations ar e pe rformed w ithout l os s o f pr ecision.
The ifir8ui operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r70 = 0x0afb14f6, r30 = 0x0a0a1414 ifir8ui r30 r70 → r90 r90 ← 0xfa
r10 = 0, r70 = 0x0afb14f6, r30 = 0x0a0a1414 IF r10 ifir8ui r30 r70 → r100 no change, since guard i s false
r20 = 1, r80 = 0x649c649c, r40 = 0x9c649c64 IF r20 ifir8ui r40 r80 → r110 r110 ← 0x2bc0
r50 = 0x80808080, r60 = 0xffffffff ifir8ui r60 r50 → r120 r120 ← 0xfffe0200
01531
rsrc1 01531
rsrc2
031
rdest
×
×
+
×
×
23 7 23 7
unsigned unsigned unsigned unsigned signed signed signed signed
signed
SEE ALSO
ifir8ii ufir8uu ifir16
ufir16
ifir8ui
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-87 PRELIMINARY SPECIFICATION
Convert floating-point to integer using PCSW
rounding mode
SYNTAX
[ IF rguard ] ifixieee rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (long) ((float)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 121
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifixieee o peration c onver ts t he sin gle-preci sion I EEE floa ting-point value i n r src1 to a signed integer and
writes the result into rdest. Roundin g is a cco rding to the IEEE round ing m ode b its in PCSW. If rsrc1 is denormalized,
zero is substituted before conversion, and the IFZ flag in the PCSW is set. If
ifixieee causes an IEEE exception,
s uch as overflow or underflow, the corre sponding excep tion flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw op erat ion. Th e upda te of the PC SW exce pti on fla gs occurs at the s a me tim e a s rdest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneo us upd a tes O R e d wit h th e exis ting P CS W value for that ex ce pt ion f lag.
The ifixieeeflags operation computes the exception flags that would result from an individual ifixieee.
The ifixieee operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ifixieee r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ifixieee r35 → r102 r102 ← 3, INX flag set
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ifixieee r40 → r105 no ch ange, since guard is false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ifixieee r40 → r110 r110 ← 0x80000000 (-231), INV flag set
r45 = 0x7f800000 (+INF)) ifixieee r45 → r112 r112 ← 0x7fffffff (231-1), INV flag set
r50 = 0xbfc147ae (-1.51) ifixieee r50 → r115 r115 ← -2, INX flag set
r60 = 0x00400000 (5.877471754e-39) ifixieee r60 → r117 r117 ← 0, IFZ set
r70 = 0xffffffff (QNaN) ifixieee r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ifixieee r80 → r122 r122 ← 0, INV flag set
SEE ALSO
ufixieee ifixrz ufixrz
ifixieee
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-88
IEEE status flags from convert floating-point to
integer using PCSW rounding mode
SYNTAX
[ IF rguard ] ifixieeeflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 122
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifixieeeflags operation computes the IEEE exceptions that would result from converting the single-
precision IEEE floating-point value in rsrc1 to a signed integer, and an integer bit vector representing the computed
except io n flag s is w rit ten i nto r dest. The bit vector stored in rdest ha s the s ame fo rm at as the IEEE exc eption bits in
the PCSW. The excep tion flags in PCSW are left unch anged by this operation. Rounding is accord ing to the IEEE
rounding mode bits in PCSW. If r src1 is denormalized, zer o is substituted before computing the conversion, and the
IFZ bit in the result is set.
The ifixieeeflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
cont rol s t he m odif icat ion of t he de st inat ion r egi ster. If the L SB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ifixieeeflags r30 → r100 r100 ← 0
r35 = 0x40247ae1 (2.57) ifixieeeflags r35 → r102 r102 ← 0x02 (INX)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ifixieeeflags r40 → r105 no change, since guard i s false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ifixieeeflags r40 → r110 r110 ← 0x10 (INV)
r45 = 0x7f800000 (+INF)) ifixieeeflags r45 → r112 r112 ← 0x10 (INV)
r50 = 0xbfc147ae (-1.51) ifixieeeflags r50 → r115 r115 ← 0x02 (INX)
r60 = 0x00400000 (5.877471754e-39) ifixieeeflags r60 → r117 r117 ← 0x20 (IFZ)
r70 = 0xffffffff (QNaN) ifixieeeflags r70 → r120 r120 ← 0x10 (INV)
r80 = 0xffbfffff (SNaN) ifixieeeflags r80 → r122 r122 ← 0x10 (INV)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ifixieee ufixieeeflags
ifixrzflags ufixrzflags
ifixieeeflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-89 PRELIMINARY SPECIFICATION
Co nvert flo atin g-point to inte ger with r o un d
toward zero
SYNTAX
[ IF rguard ] ifixrz rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (long) ((float)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 21
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifixrz operation converts the single-precision IEEE floating-point value in rsrc1 to a signed integer and
writes t he result into rdest. Rounding toward zero is perfor med; the IEEE rounding mode bits in PCSW are ignored.
Th is is th e pr eferr e d ro undi ng for ANSI C. If rsrc1 i s denormalized , ze r o is subs t ituted be fo r e conversio n, an d the IF Z
flag in the PCSW is set. If ifixrz causes an IEEE exception, such as overflow or underflow, the corresponding
exception flags in the PCS W are set. The PCSW exce ption flags are sticky: the fl ags can be set as a si de-effect of any
floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW
except io n flags o ccu rs at the sa me ti m e a s rdest is w rit ten. If any o ther float in g-poi nt co mpu te opera tio ns upd ate the
PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with
the existing PCSW value for that exception flag.
The ifixrzflags operation computes the exception flags that would result from an individual ifixrz.
The ifixrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ifixrz r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ifixrz r35 → r102 r102 ← 2, INX flag set
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ifixrz r40 → r105 no ch ange, since guard is false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ifixrz r40 → r110 r110 ← 0x80000000 (-231), INV flag
set
r45 = 0x7f800000 (+INF)) ifixrz r45 → r112 r112 ← 0x7fffffff (231-1), INV flag set
r50 = 0xbfc147ae (-1.51) ifixrz r50 → r115 r115 ← -1 , INX flag set
r60 = 0x00400000 (5.877471754e-39) ifixrz r60 → r117 r117 ← 0, IFZ s et
r70 = 0xffffffff (QNaN) ifixrz r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ifixrz r80 → r122 r122 ← 0, INV flag set
SEE ALSO
ifixieee ufixieee ufixrz
ifixrz
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-90
IEEE status flags from convert floating-point to
integer with round toward zero
SYNTAX
[ IF rguard ] ifixrzflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 129
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifixrzflags opera t io n com pu tes th e I EEE e xc ep ti on s t hat wo uld re su lt from converting the single-precision
IEEE float in g-poi nt va lue i n r src1 to a sign ed in teg er, an d an int eger bit vec tor repr esen ting th e comp ute d exce ption
flags is written into rdest. The bit vector stored in rdest has th e sam e form at as the I EEE ex c eptio n bits in the PCSW.
The exception flags in PCSW are left unchanged by this operation. Rounding toward zero is performed; the IEEE
rounding mode bits in PCSW are ignored. If rsrc1 is denormalized, zero is substituted before computing the
conversion, and the IFZ bit in the result is set.
The ifixrzflags op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ifixrzflags r30 → r100 r100 ← 0
r35 = 0x40247ae1 (2.57) ifixrzflags r35 → r102 r102 ← 0x02 (INX)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ifixrzflags r40 → r105 no ch ange, since guard is fa l se
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ifixrzflags r40 → r110 r110 ← 0x10 (INV)
r45 = 0x7f800000 (+INF)) ifixrzflags r45 → r112 r112 ← 0x10 (INV)
r50 = 0xbfc147ae (-1.51) ifixrzflags r50 → r115 r115 ← 0x02 (INX)
r60 = 0x00400000 (5.877471754e-39) ifixrzflags r60 → r117 r117 ← 0x20 (IFZ)
r70 = 0xffffffff (QNaN) ifixrzflags r70 → r120 r120 ← 0x10 (INV)
r80 = 0xffbfffff (SNaN) ifixrzflags r80 → r122 r122 ← 0x10 (INV)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ifixrz ufixrzflags
ifixieeeflags
ufixieeeflags
ifixrzflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-91 PRELIMINARY SPECIFICATION
If non -zero negate
SYNTAX
[ IF rguard ] iflip rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 = 0 then
rdest ← rsrc2
else
rdest ← –rsrc2
}
ATTRIBUTES
Function unit dspalu
Operation code 77
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The iflip operation copies rsrc2 to rdest if rsrc1 = 0; otherwise (if rsrc1 != 0), rdest is s et to the two’s-complement
of rsrc2. All valu es a re sign ed in tege r s.
The iflip operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0, r40 = 1 iflip r30 r40 → r50 r50 ← 0x1
r10 = 0, r60 = 0xffff0000, r70 = 0xabc IF r10 iflip r60 r70 → r80 no ch ange, since guard is false
r20 = 1, r60 = 0xffff0000, r70 = 0xabc IF r20 iflip r60 r70 → r90 r90 ← 0xfffff544
r30 = 0, r100 = 0xffffff9c iflip r30 r100 → r110 r110 ← 0xffffff9c
r40 = 1, r110 = 0xffffffff iflip r40 r110 → r120 r120 ← 0x1
SEE ALSO
inonzero izero
iflip
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-92
Convert signed integer to floating-point
SYNTAX
[ IF rguard ] ifloat rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (float) ((long)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 20
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifloat operation conver ts the signed integer value in rsrc1 t o sing le -pr ec is ion IEEE floa ti ng -po in t format a nd
writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If ifloat caus es an
IEEE exception, such as inexact, the correspondin g e xc ep ti on f la gs in t he PC S W are s et . Th e P CS W ex ce pt io n fl ag s
are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw op erat ion. Th e upda te of the PC SW exce pti on fla gs occurs at the s a me tim e a s rdest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneo us upd a tes O R e d wit h th e exis ting P CS W value for that ex ce pt ion f lag.
The ifloatflags operation computes the exception flags that would result from an individual ifloat.
The ifloat operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 3 ifloat r30 → r100 r100 ← 0x40400000 (3.0)
r40 = 0xffffffff (-1) ifloat r40 → r105 r105 ← 0xbf800000 (-1.0)
r10 = 0, r50 = 0xfffffffd IF r10 ifloat r50 → r110 no change, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ifloat r50 → r115 r115 ← 0xc0400000 (–3.0)
r60 = 0x7fffffff (2147483647) ifloat r60 → r117 r117 ← 0x4f000000 (2.147483648e+9), INX flag set
r70 = 0x80000000 (-2147483648) ifloat r70 → r120 r120 ← 0xcf000000 (-2.147483648e+9)
r80 = 0x7ffffff1 (2147483633) ifloat r80 → r122 r122 ← 0x4f000000 (2.147483648e+9), INX flag set
SEE ALSO
ufloat ifloatrz ufloatrz
ifixieee ifloatflags
ifloat
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-93 PRELIMINARY SPECIFICATION
IEEE status flags from convert signed integ er to
floating-point
SYNTAX
[ IF rguard ] ifloatflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float) ((long)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 130
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifloatflags op eratio n c omp ut es th e IEEE excepti ons that would resu lt fro m co nvert in g th e signed inte ge r
in r src1 to a si ng le - pre cis io n I EEE flo at i ng - po in t va lu e, and a n in te ge r bit vec tor repre sentin g the co mputed exc ept ion
flags is written into rdest. The bit vector stored in rdest has th e sam e form at as the I EEE ex c eptio n bits in the PCSW.
The exception fl ags in PC SW are left un changed by this operation. Rounding is according to the IEEE rounding mode
bit s in PC SW.
The ifloatflags op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ifloatflags r30 → r100 r100 ← 0
r40 = 0xffffffff (-1) ifloatflags r40 → r105 r105 ← 0
r10 = 0, r50 = 0xfffffffd IF r10 ifloatflags r50 → r110 no change, since guard i s false
r20 = 1, r50 = 0xfffffffd IF r20 ifloatflags r50 → r115 r115 ← 0
r60 = 0x7fffffff (2147483647) ifloatflags r60 → r117 r117 ← 0x02 (INX)
r70 = 0x80000000 (-2147483648) ifloatflags r70 → r120 r120 ← 0
r80 = 0x7ffffff1 (2147483633) ifloatflags r80 → r122 r122 ← 0x02 (INX)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ifloat ifloatrzflags
ufloatflags ufloatrzflags
ifloatflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-94
Co nvert sig ned integer to floa tin g- point wi th
rounding toward zero
SYNTAX
[ IF rguard ] ifloatrz rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (float) ((long)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 117
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifloatrz operation converts the signed integer value in rsrc1 to si ngle -pre ci sion IEE E floa tin g-poi nt form at
and writes the result into rdest. Rounding is performed toward zero; the IEEE rounding mode bits in PCSW are
igno red . This i s the pre ferred ro undi ng mo de fo r ANSI C. If ifloatrz causes an IEEE exception, such as inexact,
th e co r r es pondin g exce ption f la gs in the P C SW are set. The P CSW exception flags ar e sticky : t he flags can be s et as
a side-effect of any floating -p oint operation but can only be reset by an explicit writepcsw operation. The update of
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update t h e PCSW at t he sa me time, th e net re sult in ea ch exc eption flag is t h e l og ical OR of all sim ultaneous upd a t es
ORed with the existi ng PCSW value for that exception flag.
The ifloatrzflags operation computes the exception flags that would result from an individual ifloatrz.
The ifloatrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are writt en;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 3 ifloatrz r30 → r100 r100 ← 0x40400000 (3.0)
r40 = 0xffffffff (-1) ifloatrz r40 → r105 r105 ← 0xbf800000 (-1.0)
r10 = 0, r50 = 0xfffffffd IF r10 ifloatrz r50 → r110 no ch ange, since guard is fa l se
r20 = 1, r50 = 0xfffffffd IF r20 ifloatrz r50 → r115 r115 ← 0xc0400000 (–3.0)
r60 = 0x7fffffff (2147483647) ifloatrz r60 → r117 r117 ← 0x4effffff (2.147483520e+9), INX flag set
r70 = 0x80000000 (-2147483648) ifloatrz r70 → r120 r120 ← 0xcf000000 (-2.147483648e+9)
r80 = 0x7ffffff1 (2147483633) ifloatrz r80 → r122 r122 ← 0x4effffff (2.147483520e+9), INX flag set
SEE ALSO
ifloat ufloatrz ifixieee
ifloatflags
ifloatrz
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-95 PRELIMINARY SPECIFICATION
IEEE status flags from convert signed integ er to
floating-point with rounding toward zero
SYNTAX
[ IF rguard ] ifloatrzflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float) ((long)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 118
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ifloatrzflags operation computes the IEEE exceptions that would result from converting the signed
integ er in rsrc1 to a single -precision IE EE floa ting-point value, and an integer bit vector representing the comp uted
except io n flag s is w rit ten i nto r dest. The bit vector stored in rdest ha s the s ame fo rm at as the IEEE exc eption bits in
the PCSW. The ex ception fl ags in PCSW are left unchanged by this ope ration. Rounding is perfor med toward zero;
the IEEE rounding mode bits in PCSW are ignored.
The ifloatrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
cont rol s t he m odif icat ion of t he de st inat ion r egi ster. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ifloatrzflags r30 → r100 r100 ← 0
r40 = 0xffffffff (-1) ifloatrzflags r40 → r105 r105 ← 0
r10 = 0, r50 = 0xfffffffd IF r10 ifloatrzflags r50 → r110 no ch ange, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ifloatrzflags r50 → r115 r115 ← 0
r60 = 0x7fffffff (2147483647) ifloatrzflags r60 → r117 r117 ← 0x02 (INX)
r70 = 0x80000000 (-2147483648) ifloatrzflags r70 → r120 r120 ← 0
r80 = 0x7ffffff1 (2147483633) ifloatrzflags r80 → r122 r122 ← 0x02 (INX)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ifloatrz ifloatflags
ufloatflags ufloatrzflags
ifloatrzflags
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-96
Signed compare greater or equal
SYNTAX
[ IF rguard ] igeq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 >= rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 14
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The igeq oper atio n set s the dest in ation reg iste r, r dest, to 1 if the fi rst arg ument, r src1, is greater than or equal to
the secon d argument, rsrc2; ot he r wis e, rdest is set to 0. The arguments are treated as signed integers.
The igeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 igeq r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 igeq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 igeq r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 igeq r70 r40 → r100 r100 ← 0
r70 = 0x80000000 igeq r70 r70 → r110 r110 ← 1
SEE ALSO
ileq igeqi
igeq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-97 PRELIMINARY SPECIFICATION
Sig ned co mp are greater or equ al with imm ediate
SYNTAX
[ IF rguard ] igeqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 >= n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 1
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The igeqi operation sets the de st ina t i o n r egi ster, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the opcode modifier, n; othe r w is e, rdest is set to 0. The arguments are trea ted as sign ed in tegers .
The igeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 igeqi(2) r30 → r80 r80 ← 1
r30 = 3 igeqi(3) r30 → r90 r90 ← 1
r30 = 3 igeqi(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 igeqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 igeqi(63) r40 → r100 r100 ← 1
r60 = 0x80000000 igeqi(-64) r60 → r120 r120 ← 0
SEE ALSO
igeq iles ieqli
igeqi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-98
Signed compare gr eater
SYNTAX
[ IF rguard ] igtr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 > rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 15
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The igtr operation sets the destination register, rdest, to 1 if the first ar gument , r src1, is grea ter tha n the seco nd
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The igtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 igtr r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 igtr r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 igtr r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 igtr r70 r40 → r100 r100 ← 0
r70 = 0x80000000 igtr r70 r70 → r110 r110 ← 0
SEE ALSO
iles igtri
igtr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-99 PRELIMINARY SPECIFICATION
Sign ed compare gr eater with imm e diate
SYNTAX
[ IF rguard ] igtri(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 > n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 0
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The igtri ope rat io n se ts the de stinat i on regi st e r, rdest, to 1 if the first argument, rsrc1, is grea te r than th e opco de
modifier, n; other wis e, rdest is set to 0 . The argum e n ts are tr eate d as signed intege r s.
The igtri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 igtri(2) r30 → r80 r80 ← 1
r30 = 3 igtri(3) r30 → r90 r90 ← 0
r30 = 3 igtri(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 igtri(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 igtri(63) r40 → r100 r100 ← 1
r60 = 0x80000000 igtri(-64) r60 → r120 r120 ← 0
SEE ALSO
igtr igeqi
igtri
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-100
Sign ed immediate
SYNTAX
iimm(n) → rdest
FUNCTION
rdest ← n
ATTRIBUTES
Function unit const
Operation code 191
Nu mber of operands 0
Modif ier 32 bits
Modifier ran ge 0x80000 000
..0x7fffffff
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The iimm operation stores the signed 32-bit opcode modifier n into rdest. Note: this operation is not guarded.
EXAMPLES
Initial Values Operation Result
iimm(2) → r10 r10 ← 2
iimm(0x100) → r20 r20 ← 0x100
iimm(0xfffc0000) → r30 r30 ← 0xfffc0000
SEE ALSO
uimm
iimm
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-101 PRELIMINARY SPECIFICATION
Interr uptible indire ct jump on fa lse
SYNTAX
[ IF rguard ] ijmpf rsrc1 rsrc2
FUNCTION
if rguard then {
if (rsrc1 & 1) = 0 the n {
DPC ← rsrc2
if exception is pending then
service exception
elseif interrupt is pending then
service interrupts
else
PC, SPC ← rsrc2
}
}
ATTRIBUTES
Function unit branch
Operation code 181
Nu mber of operands 2
Modifier no
Modifier ran ge —
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The ijmpf operation conditionally changes the program flow and allows pending interrupts or exceptions to be
serviced. If neither interrupts or exceptions are pending and the LSB of rsrc1 is 0, th e DPC , PC , and SP C re gist e rs a re
s et equal to rsrc2. If an i nte r r up t or ex c ep tio n i s pend ing a nd th e LS B of rsrc1 is 0, DPC is se t equal to rsrc2 and the
service r ou ti ne is i nvoked , wh ere exc e ption s have prior i tie s over int errupts. If t h e LSB of rsrc1 i s 1, p rogr am exe c ut i on
continues with the next sequential in stru ct ion.
The ijmpf operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condit ion to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump
wil l not be taken a nd PC, DPC, a nd S PC ar e not modified regar dless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 0, r70 = 0x330 ijmpf r50 r70 program execution continues at 0x330 after
first servicing pending interrupts
r20 = 1, r70 = 0x330 ijmpf r20 r70 sin ce r20 is true, program execution cont in-
ues with next sequential i nstruc t i on
r30 = 0, r50 = 0, r60 = 0x8000 IF r30 ijmpf r50 r60 since guard is false, program execution con-
tinues with next sequential instr uc tio n
r40 = 1, r50 = 0, r60 = 0x8000 IF r40 ijmpf r50 r60 program execution continues at 0x8000 after
first servicing pending interrupts
SEE ALSO
jmpf jmpt jmpi ijmpt ijmpi
ijmpf
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-102
Interruptible jump immediate
SYNTAX
[ IF rguard ] ijmpi(address)
FUNCTION
if rguard then {
DPC ← address
if exception is pending then
service exception
else if interrupt is pending then
service interrupts
else
PC, SPC ← address
}
ATTRIBUTES
Function unit branch
Operation code 179
Nu mber of operands 0
Modif ier 32 bits
Modifier range 0..0xffffffff
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The ijmpi operation changes the program flow and allows pending inter rupts or exceptions to be serviced. If no
interrupts or exceptions are pendin g, the D PC, PC, and SPC registers are set equal to address. If an exception o r
inter ru pts is pend ing, D PC i s set equ al to address and a service routine is invoked, where exceptions have p ri o ri t ies
over interrupts. address is an im med i a te opcode mod i fi er.
The ijmpi operation optiona lly takes a guar d , speci fied in rguard. If a guard is present, its LSB adds a condition to
the jump. If the LSB of r guard is 1, the instructio n executes as previously descr ibed; otherwise, the jump will not be
ta ken an d PC, DPC, and S PC are no t mo dified.
EXAMPLES
Initial Values Operation Result
ijmpi(0x330) program execution continues at 0x330
r30 = 0 IF r30 ijmpi(0x8000) since guard is false, program execution con-
tinues with next sequential instr uc tio n
r40 = 1 IF r40 ijmpi(0x8000) program execution continues at 0x8000
SEE ALSO
jmpf jmpt jmpi ijmpf ijmpt
ijmpi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-103 PRELIMINARY SPECIFICATION
Inter rupt ib le indirect jum p on true
SYNTAX
[ IF rguard ] ijmpt rsrc1 rsrc2
FUNCTION
if rguard then {
if (rsrc1 & 1) = 1 the n {
DPC ← rsrc2
if exception is pending then
service exception
elseif interrupt is pending then
service interrupts
else
PC, SPC ← rsrc2
}
}
ATTRIBUTES
Function unit branch
Operation code 177
Nu mber of operands 2
Modifier no
Modifier ran ge —
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The ijmpt operation conditionally changes the program flow and allows pending interrupts or exceptions to be
s erviced. If no interrupts or exceptions are pending and the LSB of rsrc1 is 1, the DPC, PC, and SPC r egiste rs are set
equal to rsrc2. If an exception or interrupt is pending and the LSB of rsrc1 is 1, DPC is set equal to rsrc2 and a service
ro ut in e is in v ok e d, wh ere ex cep ti ons h a ve pri orit y ove r inte rru pt s . If th e LSB of r src1 is 0, program execution continues
with the next sequential instruction.
The ijmpt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condit ion to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump
wil l not be taken a nd PC, DPC, a nd S PC ar e not modified regar dless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 1, r70 = 0x330 ijmpt r50 r70 program execution continues at 0x330 after
first servicing pending interrupts
r20 = 0, r70 = 0x330 ijmpt r20 r70 since r20 is false, program execution contin-
ues with next sequential i nstruc t i o n
r30 = 0, r50 = 1, r60 = 0x8000 IF r30 ijmpt r50 r60 since guard is false, program execution con-
tinues with next sequential instr uc tio n
r40 = 1, r50 = 1, r60 = 0x8000 IF r40 ijmpt r50 r60 program execution continues at 0x8000 after
first servicing pending interrupts
SEE ALSO
jmpf jmpt jmpi ijmpf ijmpi
ijmpt
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-104
Signed 16-bit load
pseudo-op for ild16d(0)
SYNTAX
[ IF rguard ] ild16 rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[(rsrc1 +(1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 6
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild16 operation is a pseudo operation transformed by the scheduler into an ild16d(0) with the same
argument. (Note: pseudo operat ions cannot be used in assembly source files.)
The ild16 operation loads the 16-bit memory value from the address contained in rsrc1, sig n extend s it to 3 2 bits,
and s tore s the re su lt in r dest. If the m emo r y add ress c ont aine d in rsrc1 is not a multiple of 2, the result of ild16 is
undefine d but no e xce ption will be rai sed. This load operation is perfo rm ed as little-e ndia n or big -endia n depending on
the current setting of the bytesex bit in the PCSW.
The result of an access by ild16 to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The ild16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and ild16 has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd00] = 0x22,
[0xd01] = 0x11 ild16 r10 → r60 r60 ← 0x00002211
r30 = 0, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33 IF r30 ild16 r20 → r70 no change, since guard is false
r40 = 1, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33 IF r40 ild16 r20 → r80 r80 ← 0xffff8433
r50 = 0xd01 ild16 r50 → r90 r90 undefined, since 0xd01 is not a multiple of 2
SEE ALSO
ild16d ild16r ild16x
ild16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-105 PRELIMINARY SPECIFICATION
Signed 16-bit load with displacem ent
SYNTAX
[ IF rguard ] ild16d(d) rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[(rsrc1 + d + ( 1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + d + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 6
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –128..126 by 2
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild16d operat ion l oads t he 16-bi t memory value from the address computed by rsrc1 + d, sign e xt end s it to 32
bi ts, and st or e s th e r es ul t in rdest. The d value is an opcode m odi f ier, mus t be in t he range –128 to 126 inclusive, and
must be a mul tiple of 2. If th e me mo r y addre ss c omp uted b y rsrc1 + d is not a multip le of 2, the result of ild16d is
undefine d but no e xce ption will be rai sed. This load operation is perfo rm ed as little-e ndia n or big -endia n depending on
the current setting of the bytesex bit in the PCSW.
The result of an access by ild16d to the MMIO address aper ture is undefined; access to the MMIO ap er ture is
defined only for 32- bit loads and sto res.
The ild16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and ild16d ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd02] = 0x22,
[0xd03] = 0x11 ild16d(2) r10 → r60 r60 ← 0x00002211
r30 = 0, r20 = 0xd04, [0xd00] = 0x84,
[0xd01] = 0x33 IF r30 ild16d(-4) r20 → r70 no change, since guard is false
r40 = 1, r20 = 0xd04, [0xd00] = 0x84,
[0xd01] = 0x33 IF r40 ild16d(-4) r20 → r80 r80 ← 0xffff8433
r50 = 0xd01 ild16d(-4) r50 → r90 r90 undef ined , since 0xd01 + ( –4) is not a
mu ltip le of 2
SEE ALSO
ild16 uld16 uld16d ild16r
uld16r ild16x uld16x
ild16d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-106
Signed 16- bit load w ith index
SYNTAX
[ IF rguard ] ild16r r src1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[(rsrc1 + rsrc2 +(1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + rsrc2 + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 195
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild16r operation loads the 16-bit memory value from the address computed by rsrc1 + rsrc2, sign e xtends it
to 32 bits, and stores the result in rdest. If the me mor y ad dr ess c omp uted by r src1 + rsrc2 is no t a multip le of 2, the
result of ild16r is undefined but no exception will be raised. This load operation is performed as little-endian or big-
endian dependin g on the current setting of the bytesex bit in the PCSW.
The result of an access by ild16r to the MMIO address aper ture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The ild16r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and ild16r ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r20 = 2, [0xd02] = 0x22,
[0xd03] = 0x11 ild16r r10 r20 → r80 r80 ← 0x00002211
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33 IF r50 ild16r r40 r30 → r90 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33 IF r60 ild16r r40 r30 → r100 r100 ← 0xffff8433
r70 = 0xd01, r30 = 0xfffffffc ild16r r70 r30 → r110 r110 undef ined , since 0xd01 + (–4) is not a
multiple of 2
SEE ALSO
ild16 uld16 ild16d uld16d
uld16r ild16x uld16x
ild16r
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-107 PRELIMINARY SPECIFICATION
Signed 16-bit load with scaled index
SYNTAX
[ IF rguard ] ild16x r src1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[(rsrc1 + (2 × rsrc2) + (1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + (2 × rsrc2) + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 196
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild16x oper ation loa ds the 16- bit memory value fr om the ad dr ess com puted by rsrc1 + 2×rsrc2, s ig n extends
it to 32 b its, and stor es t he resu lt in rdest. If the memory address computed by rsrc1 + 2×rsrc2 is n ot a multi ple of 2,
th e res ul t of ild16x i s u nd efi ned but n o exce ption w il l be rais ed. This lo ad op er at io n is p er for med a s li t tl e -endia n or
big-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by ild16x to the MMIO address aper ture is undefined; access to the MMIO ap er ture is
defined only for 32- bit loads and sto res.
The ild16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and ild16x ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r30 = 1, [0xd02] = 0x22,
[0xd03] = 0x11 ild16x r10 r30 → r100 r100 ← 0x00002211
r50 = 0, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33 IF r50 ild16x r40 r20 → r80 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33 IF r60 ild16x r40 r20 → r90 r90 ← 0xffff8433
r70 = 0xd01, r30 = 1 ild16x r70 r30 → r110 r110 undef ined , sinc e 0xd01 + 2×1 is not a
multiple of 2
SEE ALSO
ild16 uld16 ild16d uld16d
ild16r uld16r uld16x
ild16x
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-108
Signed 8-bit load
pseudo-op for ild8d(0)
SYNTAX
[ IF rguard ] ild8 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← sign_ext8to32(mem[rsrc1])
ATTRIBUTES
Function unit dmem
Operation code 192
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild8 operation is a pseudo operation transformed by the scheduler into an ild8d(0) with the same
argument. (Note: pseudo operat ions cannot be used in assembly source files.)
The ild8 operation loads the 8-bit memory value from the address contained in rsrc1, s ign exte nds i t to 32 b its,
and stores the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a single byte
is loaded.
The result of an access by ild8 to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The ild8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is not
changed and ild8 has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd00] = 0x22 ild8 r10 → r60 r60 ← 0x00000022
r30 = 0, r20 = 0xd04, [0xd04] = 0x84 IF r30 ild8 r20 → r70 no change, since guard i s false
r40 = 1, r20 = 0xd04, [0xd04] = 0x84 IF r40 ild8 r20 → r80 r80 ← 0xffffff84
r50 = 0xd01, [0xd01] = 0x33 ild8 r50 → r90 r90 ← 0x00000033
SEE ALSO
uld8 ild8d uld8d ild8r
uld8r
ild8
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-109 PRELIMINARY SPECIFICATION
Signed 8-bit load with displacement
SYNTAX
[ IF rguard ] ild8d(d) rsrc1 → rdest
FUNCTION
if rguard then
rdest ← sign_ext8to32(mem[rsrc1 + d])
ATTRIBUTES
Function unit dmem
Operation code 192
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild8d operation loads the 8-bit memory value from the address computed by r src1 + d, si gn exten ds it to 32
bit s, and s tores th e r e su lt in rdest. The d value is an opcode modifier in the range -64 to 63, inclusive. This operation
does not depe nd on the b yte se x bit in t he P CS W since onl y a single by te is loaded.
The result of an access by ild8d to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The ild8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is no t
changed and ild8d has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd02] = 0x22 ild8d(2) r10 → r60 r60 ← 0x000022
r30 = 0, r20 = 0xd04, [0xd00] = 0x84 IF r30 ild8d(-4) r20 → r70 no ch ange, since guard is false
r40 = 1, r20 = 0xd04, [0xd00] = 0x84 IF r40 ild8d(-4) r20 → r80 r80 ← 0xffffff84
r50 = 0xd05, [0xd01] = 0x33 ild8d(-4) r50 → r90 r90 ← 0x00000033
SEE ALSO
ild8 uld8 uld8d ild8r
uld8r
ild8d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-110
Signed 8-bit load with index
SYNTAX
[ IF rguard ] ild8r rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← sign_ext8to32(mem[rsrc1 + rsrc2])
ATTRIBUTES
Function unit dmem
Operation code 193
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ild8r operation loads the 8-bit memory value from the address computed by r src1 + rsrc2, si gn extend s it to
32 bits, and stores the result in rdest. T hi s op erat ion does not d epen d on th e byt esex b it in t he PCS W si nce on ly a
si ng le byte is load ed.
The result of an access by ild8r to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The ild8r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is not
changed and ild8r has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r20 = 2, [0xd02] = 0x22 ild8r r10 r20 → r80 r80 ← 0x00000022
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84 IF r50 ild8r r40 r30 → r90 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84 IF r60 ild8r r40 r30 → r100 r100 ← 0xffffff84
r70 = 0xd05, r30 = 0xfffffffc,
[0xd01] = 0x33 ild8r r70 r30 → r110 r110 ← 0x00000033
SEE ALSO
ild8 uld8 ild8d uld8d
uld8r
ild8r
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-111 PRELIMINARY SPECIFICATION
Sig ned compare less or equ al
pseudo -op for igeq
SYNTAX
[ IF rguard ] ileq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 <= rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 14
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ileq operation is a pseudo operation transformed by the scheduler into an igeq with the arguments
exchanged (ileq’s rsrc1 is igeq’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The ileq operation sets the destination register, r dest, to 1 if the first argument, rsrc1, is less than or equa l to the
s econd argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The ileq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ileq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ileq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, 0x100 IF r20 ileq r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 ileq r70 r40 → r100 r100 ← 1
r70 = 0x80000000 ileq r70 r70 → r110 r110 ← 1
SEE ALSO
igeq ileqi
ileq
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-112
Sign ed compa re less or equal with immedia te
SYNTAX
[ IF rguard ] ileqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 <= n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 42
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ileqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to the
opcode modifier, n; otherwise, r dest is set to 0. The arguments are treated as signed integers.
The ileqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ileqi(2) r30 → r80 r80 ← 0
r30 = 3 ileqi(3) r30 → r90 r90 ← 1
r30 = 3 ileqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ileqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ileqi(63) r40 → r100 r100 ← 0
r60 = 0x80000000 ileqi(-64) r60 → r120 r120 ← 1
SEE ALSO
ileq igeqi
ileqi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-113 PRELIMINARY SPECIFICATION
Signed compa re l ess
pseudo-op fo r igtr
SYNTAX
[ IF rguard ] iles rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 < rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 15
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The iles operation is a pseudo operation transformed by the scheduler into an igtr with the arguments
exchanged (iles’s rsrc1 is igtr’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The iles operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the second
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The iles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 iles r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 iles r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, 0x100 IF r20 iles r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 iles r70 r40 → r100 r100 ← 1
r70 = 0x80000000 iles r70 r70 → r110 r110 ← 0
SEE ALSO
igtr ilesi
iles
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-114
Sign ed compa re less with imm edi ate
SYNTAX
[ IF rguard ] ilesi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 < n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 2
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ilesi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the opcode
modifier, n; other wis e, rdest is set to 0 . The argum e n ts are tr eate d as signed intege r s.
The ilesi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ilesi(2) r30 → r80 r80 ← 0
r30 = 3 ilesi(3) r30 → r90 r90 ← 0
r30 = 3 ilesi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ilesi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ilesi(63) r40 → r100 r100 ← 0
r60 = 0x80000000 ilesi(-64) r60 → r120 r120 ← 1
SEE ALSO
iles ileqi
ilesi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-115 PRELIMINARY SPECIFICATION
Signed maximum
SYNTAX
[ IF rguard ] imax rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 > rsrc2 then
rdest ← rsrc1
else
rdest ← rsrc2
}
ATTRIBUTES
Function unit dspalu
Operation code 24
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The imax oper a tio n set s the desti na ti on re gi st er, rdest, to the contents of rsrc1 if rsrc1>rsrc2; otherwise, rdest is set
to th e contents of rsrc2. The ar g uments are tr e ated as signed i ntegers.
The imax operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 imax r30 r20 → r80 r80 ← 2
r10 = 0, r60 = 0x100, r30 = 2 IF r10 imax r60 r30 → r50 no change, since guard is false
r20 = 1, r60 = 0x100, r40 = 0xffffff9c IF r20 imax r60 r40 → r90 r90 ← 0x100
r70 = 0xffffff00, r40 = 0xffffff9c imax r70 r40 → r100 r100 ← 0xffffff9c
SEE ALSO
imin
imax
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-116
Signed minimum
SYNTAX
[ IF rguard ] imin rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 > rsrc2 then
rdest ← rsrc2
else
rdest ← rsrc1
}
ATTRIBUTES
Function unit dspalu
Operation code 23
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The imin oper a tio n set s the desti na ti on re gi st er, rdest, to the contents of rsrc2 if rsrc1>rsrc2; otherwise, rdest is set
to th e contents of rsrc1. The ar g uments are tr e ated as signed i ntegers.
The imin operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 imin r30 r20 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 2 IF r10 imin r60 r30 → r50 no change, since guard is false
r20 = 1, r60 = 0x100, r40 = 0xffffff9c IF r20 imin r60 r40 → r90 r90 ← 0xffffff9c
r70 = 0xffffff00, r40 = 0xffffff9c imin r70 r40 → r100 r100 ← 0xffffff00
SEE ALSO
imax
imin
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-117 PRELIMINARY SPECIFICATION
Sign ed m u ltiply
SYNTAX
[ IF rguard ] imul rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
temp ← (sign_ext32to64(rsrc1) × sign_ext32to64(rsrc2))
rdest ← temp<31:0>
ATTRIBUTES
Function unit ifmul
Operation code 27
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below , the imul opera t io n com pute s th e prod uc t rsrc1×rsrc2 and writ e s th e lea st - sign if i ca nt 32 b its of th e
full 64-bit product into rdest. The operands are considered signed integers. No overflow or underflow detection is
performed.
The imul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 imul r60 r60 → r80 r80 ← 0x10000
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 imul r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x100, r30 = 0xf11 IF r20 imul r60 r30 → r90 r90 ← 0xf1100
r70 = 0xffffff00, r40 = 0xffffff9c imul r70 r40 → r100 r100 ← 0x6400
031
rsrc1 031
rsrc2
031
rdest
×
063 31
64-bit result
signed signed
signed
signed
SEE ALSO
umul imulm umulm dspimul
dspumul dspidualmul
quadumulmsb fmul
imul
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-118
Sign ed multipl y, return mo st -sig nificant 32 bit s
SYNTAX
[ IF rguard ] imulm rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
temp ← (sign_ext32to64(rsrc1) × sign_ext32to64(rsrc2))
rdest ← temp<63:32>
ATTRIBUTES
Function unit ifmul
Operation code 139
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, the imulm operat i o n co mputes the p rodu c t rsrc1×rsrc2 an d wr ites t he m ost-s igni fica nt 3 2 bits o f
the full 64-bit product into rdest. The ope rands a re cons ider e d si gn ed i ntege r s.
The imulm operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x10000 imulm r60 r60 → r80 r80 ← 0x00000001
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 imulm r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x10001000,
r30 = 0xf1100000 IF r20 imulm r60 r30 → r90 r90 ← 0xff10ff11
r70 = 0xffffff00, r40 = 0x64 imulm r70 r40 → r100 r100 ← 0xffffffff
031
rsrc1 031
rsrc2
031
rdest
×
063 31
64-bit result
signed signed
signed
signed
SEE ALSO
umulm dspimul dspumul
dspidualmul quadumulmsb
fmul
imulm
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-119 PRELIMINARY SPECIFICATION
Signed negate
pse udo-op for isub
SYNTAX
[ IF rguard ] ineg rsrc1 → rdest
FUNCTION
if rguard then
rdest ← –rsrc1
ATTRIBUTES
Function unit alu
Operation code 13
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ineg oper atio n is a ps eudo oper ation transfo r med by the s c heduler into a n isub with r0 ( a lw ays contains 0)
as the f ir s t arg um en t and r src1 as the sec on d ar g ument . (No te: pse udo opera t ions ca nn ot be us ed i n assemb ly sourc e
files.)
The ineg operation computes the negative of rsrc1 and writes the result into rdest. The argument is a signed
intege r; the r esult is an un signed int eger. If rsrc1 = 0x80 000000, then ineg returns 0x80000000 since the positive
va lu e is n ot repr es e nta ble.
The ineg operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff ineg r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0xfffffff4 IF r10 ineg r40 → r80 no ch ange, since guard is false
r20 = 1, r40 = 0xfffffff4 IF r20 ineg r40 → r90 r90 ← 0xc
r50 = 0x80000001 ineg r50 → r100 r100 ← 0x7fffffff
r60 = 0x80000000 ineg r60 → r110 r110 ← 0x80000000
r20 = 1 ineg r20 → r120 r120 ← 0xffffffff
SEE ALSO
isub
ineg
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-120
Signed compare not equal
SYNTAX
[ IF rguard ] ineq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 != rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 39
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ineq operation sets the destination register, rdest, to 1 if the two arguments, r src1 and rsrc2, are not equal;
otherwise, rdest is set to 0.
The ineq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ineq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x1000, r30 = 3 IF r10 ineq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x1000 IF r20 ineq r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 ineq r70 r40 → r100 r100 ← 1
r70 = 0x80000000 ineq r70 r70 → r110 r110 ← 0
SEE ALSO
ieql igtr ineqi
ineq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-121 PRELIMINARY SPECIFICATION
Signed compare not equal with immediate
SYNTAX
[ IF rguard ] ineqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 != n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 3
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ineqi operat ion se ts th e des tinatio n r eg is ter, rdest, to 1 if the fir st argu ment, rsrc1, is not equ a l to t h e op co de
modifier, n; other wis e, rdest is set to 0 . The argum e n ts are tr eate d as signed intege r s.
The ineqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ineqi(2) r30 → r80 r80 ← 1
r30 = 3 ineqi(3) r30 → r90 r90 ← 0
r30 = 3 ineqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ineqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ineqi(63) r40 → r100 r100 ← 1
r60 = 0xffffffc0 ineqi(-64) r60 → r120 r120 ← 0
SEE ALSO
ineq igeqi ieqli
ineqi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-122
If no nzero se lect zer o
SYNTAX
[ IF rguard ] inonzero rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 != 0 then
rdest ← 0
else
rdest ← rsrc2
}
ATTRIBUTES
Function unit alu
Operation code 47
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The inonzero operation writes 0 into rdest if the value of rsrc1 is not zero; otherwise, rsrc2 is copied to rdest. Th e
operands are considered signed integers.
The inonzero operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 inonzero r30 r20 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 2 IF r10 inonzero r60 r30 → r50 no change, since guard is f alse
r20 = 1, r60 = 0x100, r40 = 0xffffff9c IF r20 inonzero r60 r40 → r90 r90 ← 0
r10 = 0, r40 = 0xffffff9c inonzero r10 r40 → r100 r100 ← 0xffffff9c
r20 = 1, r60 = 0x100 inonzero r20 r60 → r110 r110 ← 0
r10 = 0, r70 = 0x456789 inonzero r10 r70 → r120 r120 ← 0x456789
SEE ALSO
izero iflip
inonzero
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-123 PRELIMINARY SPECIFICATION
Subtract
SYNTAX
[ IF rguard ] isub rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 – rsrc2
ATTRIBUTES
Function unit alu
Operation code 13
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The isub operation computes the difference rsrc1–rsrc2 and writes the result into rdest. The operands can be
either both signed or unsigned integers. No overflow or underflow detection is performed.
The isub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 isub r30 r40 → r80 r80 ← 0xffffffff
r10 = 0, r60 = 0x100, r30 = 3 IF r10 isub r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 isub r50 r60 → r90 r90 ← 0xf00
r70 = 0x80000000, r40 = 4 isub r70 r40 → r100 r100 ← 0x7ffffffc
SEE ALSO
isubi borrow dspisub
dspidualsub fsub
isub
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-124
Subtract with immediate
SYNTAX
[ IF rguard ] isubi(n) rsrc1 → rdest
FUNCTION
if rguard then
rdest ← rsrc1 – n
ATTRIBUTES
Function unit alu
Operation code 32
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The isubi oper a tio n com pu te s the di f f er e nce o f a si ngle argument in rsrc1 and an imm ediate m odifier n and st ore s
the result in rdest. The value of n must be between 0 and 127, inclusive.
The isubi operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xf11 isubi(127) r30 → r70 r70 ← 0xe92
r10 = 0, r40 = 0xffffff9c IF r10 isubi(1) r40 → r80 no ch ange, since guard is f alse
r20 = 1, r40 = 0xffffff9c IF r20 isubi(1) r40 → r90 r90 ← 0xffffff9b
r50 = 0x1000 isubi(15) r50 → r120 r120 ← 0x0ff1
r60 = 0xfffffff0 isubi(2) r60 → r110 r110 ← 0xffffffee
r20 = 1 isubi(17) r20 → r120 r120 ← 0xfffffff0
SEE ALSO
isub borrow
isubi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-125 PRELIMINARY SPECIFICATION
If zer o select zero
SYNTAX
[ IF rguard ] izero rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 = 0 then
rdest ← 0
else
rdest ← rsrc2
}
ATTRIBUTES
Function unit alu
Operation code 46
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The izero operati on write s 0 into rdest if t he v a lu e of rsrc1 is equal to zero; otherwise, rsrc2 is copi ed to rdest. Th e
operands are considered signed integers.
The izero operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 izero r30 r20 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 2 IF r10 izero r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x100, r40 = 0xffffff9c IF r20 izero r60 r40 → r90 r90 ← 0xffffff9c
r10 = 0, r40 = 0xffffff9c izero r10 r40 → r100 r100 ← 0
r20 = 1, r60 = 0x100 izero r20 r60 → r110 r110 ← 0x100
r20 = 1, r70 = 0x456789 izero r20 r70 → r120 r120 ← 0x456789
SEE ALSO
inonzero iflip
izero
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-126
Indir ect jump on false
SYNTAX
[ IF rguard ] jmpf rsrc1 rsrc2
FUNCTION
if rguard then {
if (rsrc1 & 1) = 0 then
PC ← rsrc2
}
ATTRIBUTES
Function unit branch
Operation code 180
Nu mber of operands 2
Modifier No
Modifier ran ge —
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The jmpf opera tion c on ditiona lly c ha nge s the p r ogram f low. I f th e L SB of rsrc1 is 0, the PC register is set equal to
rsrc2; otherwise, program execution continues with the next sequential instruction.
The jmpf operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condit ion to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump
wil l not be ta ken rega r dl es s of the valu e of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 0, r70 = 0x330 jmpf r50 r70 program execution continues at 0x330
r20 = 1, r70 = 0x330 jmpf r20 r70 sin ce r20 is true, program execution cont in-
ues with next sequential i nstruc t i on
r30 = 0, r50 = 0, r60 = 0x8000 IF r30 jmpf r50 r60 since guard is f alse, program ex ecution con-
tinues with next sequential instr uc tio n
r40 = 1, r50 = 0, r60 = 0x8000 IF r40 jmpf r50 r60 program e xecution continues at 0x8000
SEE ALSO
jmpt jmpi ijmpf ijmpt
ijmpi
jmpf
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-127 PRELIMINARY SPECIFICATION
Jump i mme di at e
SYNTAX
[ IF rguard ] jmpi(address)
FUNCTION
if rguard then
PC ← address
ATTRIBUTES
Function unit branch
Operation code 178
Nu mber of operands 0
Modif ier 32 bits
Modifier range 0..0xffffffff
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The jmpi operation changes the program flow by setting the PC register equal t o the immediate opcode modi fier
address.
The jmpi ope ration optionall y take s a guard, s pecifie d in r guard. If a guard is present, its LSB adds a condition to
the jump. If the LSB of r guard is 1, the instructio n executes as previously descr ibed; otherwise, the jump will not be
taken.
EXAMPLES
Initial Values Operation Result
jmpi(0x330) program ex ecution continues at 0x330
r30 = 0 IF r30 jmpi(0x8000) since guard is false, program execution con-
tinues with next sequential instr uc tio n
r40 = 1 IF r40 jmpi(0x8000) program execution continues at 0x8000
SEE ALSO
jmpf jmpt ijmpf ijmpt
ijmpi
jmpi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-128
In dir ect j um p on true
SYNTAX
[ IF rguard ] jmpt rsrc1 rsrc2
FUNCTION
if rguard then {
if (rsrc1 & 1) = 1 then
PC ← rsrc2
}
ATTRIBUTES
Function unit branch
Operation code 176
Nu mber of operands 2
Modifier no
Modifier ran ge —
Delay 3
Issue slots 2, 3, 4
DESCRIPTION
The jmpt opera tion c on ditiona lly c ha nge s the p r ogram f low. I f th e L SB of rsrc1 is 1, the PC register is set equal to
rsrc2; otherwise, program execution continues with the next sequential instruction.
The jmpt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condit ion to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump
wil l not be ta ken rega r dl es s of the valu e of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 1, r70 = 0x330 jmpt r50 r70 program execution continues at 0x330
r20 = 0, r70 = 0x330 jmpt r20 r70 since r20 is false, program execution contin-
ues with next sequential i nstruc t i o n
r30 = 0, r50 = 1, r60 = 0x8000 IF r30 jmpt r50 r60 since guard is f alse, program ex ecution con-
tinues with next sequential instr uc tio n
r40 = 1, r50 = 1, r60 = 0x8000 IF r40 jmpt r50 r60 program e xecution continues at 0x8000
SEE ALSO
jmpf jmpi ijmpf ijmpt
ijmpi
jmpt
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-129 PRELIMINARY SPECIFICATION
32-bit loa d
pseudo-op for ld3 2d(0)
SYNTAX
[ IF rguard ] ld32 rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
rdest<7:0> ← mem[rsrc1 + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit dmem
Operation code 7
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ld32 operation is a pseudo operation transformed by the scheduler into an ld32d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)
The ld32 operation loads the 32-bit memory value from the address contained in rsrc1 and stores the result in
rdest. If the memory address contained in rsrc1 is not a multiple of 4, the result of ld32 is undefined but no exception
wil l be r aise d. Thi s loa d ope rati on is per for m ed a s littl e-e ndia n or big-endian depending on the current setting of the
bytesex bit in the PCSW.
The ld32 operation can be used to access t he MMIO address aperture (the result of MMIO access by 8- or 16-bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access by ld32.
The ld32 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and ld32 has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
ld32 r10 → r60 r60 ← 0x84332211
r30 = 0, r20 = 0xd04,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r30 ld32 r20 → r70 no change, since guard i s false
r40 = 1, r20 = 0xd04,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r40 ld32 r20 → r80 r80 ← 0x48665544
r50 = 0xd01 ld32 r50 → r90 r90 undefined, since 0xd01 is not a multiple of 4
SEE ALSO
ld32d ld32r ld32x st32
st32d h_st32d
ld32
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-130
32-bit load with displacem ent
SYNTAX
[ IF rguard ] ld32d(d) rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
rdest<7:0> ← mem[rsrc1 + d + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + d + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + d + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + d + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit dmem
Operation code 7
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency 3
Issue slots 4, 5
DESCRIPTION
The ld32d operation loads the 32-bit memory valu e from the add res s computed by rsrc1 + d and stores the result
in rdest. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4. If
th e memory a ddr ess co mputed by rsrc1 + d is no t a mu ltip le of 4, the r e s ult of ld32d is un de fine d but no exc eption
wil l be r aise d. Thi s loa d ope rati on is per for m ed a s littl e-e ndia n or big-endian depending on the current setting of the
bytesex bit in the PCSW.
The ld32d oper ation can be use d to access the MM IO a ddress apert ure (th e re sult of MM IO ac cess b y 8- or 16- bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access b y ld32d.
The ld32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and ld32d has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xcfc,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
ld32d(4) r10 → r60 r60 ← 0x84332211
r30 = 0, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r30 ld32d(-8) r20 → r70 no ch ange, since guard is false
r40 = 1, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r40 ld32d(-8) r20 → r80 r80 ← 0x48665544
r50 = 0xd01 ld32d(-8) r50 → r90 r90 undefined, since 0xd01 +(–8) is not a
multiple of 4
SEE ALSO
ld32 ld32r ld32x st32
st32d h_st32d
ld32d
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-131 PRELIMINARY SPECIFICATION
32-bit load with index
SYNTAX
[ IF rguard ] ld32r rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
rdest<7:0> ← mem[rsrc1 + rsrc2 + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + rsrc2 + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + rsrc2 + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + rsrc2 + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit dmem
Operation code 200
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ld32r op era tion load s the 32-b it me mo ry valu e f rom the a ddres s c omp uted by rsrc1 + rsrc2 and sto res the
result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 4, the result of ld32r is
undefine d but no e xce ption will be rai sed. This load operation is perfo rm ed as little-e ndia n or big -endia n depending on
the current setting of the bytesex bit in the PCSW.
The ld32r oper ation can be use d to access the MM IO a ddress apert ure (the result of MMIO ac cess b y 8- or 16- bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access by ld32r.
The ld32r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and ld32r has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xcfc, r20 = 0x4,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
ld32r r10 r20 → r80 r80 ← 0x84332211
r50 = 0, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r50 ld32r r40 r30 → r90 no ch ange, since guard is false
r60 = 1, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r60 ld32r r40 r30 → r100 r100 ← 0x48665544
r50 = 0xd01, r30 = 0xfffffff8 ld32r r70 r30 → r110 r110 undefined , since 0xd01 +(–8) is not a
multiple of 2
SEE ALSO
ld32 ld32d ld32x st32
st32d h_st32d
ld32r
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-132
32-bit load with scaled index
SYNTAX
[ IF rguard ] ld32x rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
rdest<7:0> ← mem[rsrc1 + (4 × rsrc2) +(3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + (4 × rsrc2) + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + (4 × rsrc2) + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + (4 × rsrc2) + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit dmem
Operation code 201
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The ld32x operation loads t h e 32-bit m em ory val ue fr om t he ad dr ess com puted by rsrc1 + 4×rsrc2 and stores the
result in rdest. If the memory address computed by rsrc1 + 4×rsrc2 is not a multiple of 4, the result of ld32x is
undefine d but no e xce ption will be rai sed. This load operation is perfo rm ed as little-e ndia n or big -endia n depending on
the current setting of the bytesex bit in the PCSW.
The ld32x oper ation can be use d to access the MM IO a ddress apert ure (the result of MMIO ac cess b y 8- or 16- bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access b y ld32x.
The ld32x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and ld32x has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xcfc, r30 = 0x1,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
ld32x r10 r30 → r100 r100 ← 0x84332211
r50 = 0, r40 = 0xd0c, r20 = 0xfffffffe,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r50 ld32x r40 r20 → r80 no ch ange, since guard is false
r60 = 1, r40 = 0xd0c, r20 = 0xfffffffe,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r60 ld32x r40 r20 → r90 r90 ← 0x48665544
r70 = 0xd01, r30 = 0x1 ld32x r70 r30 → r110 r110 undef ined, since 0xd01 + 4×1 is not a
multiple of 4
SEE ALSO
ld32 ld32d ld32r st32
st32d h_st32d
ld32x
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-133 PRELIMINARY SPECIFICATION
Logical shift left
pseudo-op for asl
SYNTAX
[ IF rguard ] lsl rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n ← rsrc2<4:0>
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← 0
if rsrc2<31:5> != 0 {
rd e st < - 0
}
}
ATTRIBUTES
Function unit shifter
Operation code 19
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
The lsl operation is a pseudo operation that is transformed by the scheduler into an asl with the same
arguments. (N ote: pseudo operations cannot be used in assembl y source files.)
As s hown below, the lsl ope r ation ta ke s two ar guments, r src1 and rsrc2. Rsrc2 spec ify an un signed sh if t am ount,
and rdest is set to rsrc1 logically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this as a shift
by 32 or more bits. Zeros are shift ed into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The lsl operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 lsl r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 lsl r60 r30 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x20, r30 = 3 IF r20 lsl r60 r30 → r110 r110 ← 0x100
r70 = 0xfffffffc, r40 = 2 lsl r70 r40 → r120 r120 ← 0xfffffff0
r80 = 0xe, r50 = 0xfffffffe lsl r80 r50 → r125 r125 ← 0x00000000 (shift by more than 32))
r30 = 0x7008000f, r45 = 0x20 lsl r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x80000000 lsl r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x23 lsl r30 r45 → r100 r100 ← 0x00000000
031
rsrc1
031
rsrc2
000
Left shifter
32 bits from rsrc1
031
rdest 3
000
Interm ediate result
(example: n = 3)
rsrc2
SEE ALSO
asl asli asr asri lsli lsr
lsri rol roli
lsl
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-134
Logical shift left immediate
pseudo-op for asli
SYNTAX
[ IF rguard ] lsli(n) rsrc1 → rdest
FUNCTION
if rguard then {
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← 0
}
ATTRIBUTES
Function unit shifter
Operation code 11
Nu mber of operands 1
Modif ier 7 bits
Modifier range 0..31
Latency 1
Issue slots 1, 2
DESCRIPTION
The lsli operation is a pseudo operation that is transformed by the scheduler into an asli with the same
argument and opcode modifier. (Note: pseu do operations cannot b e used in assembly source files.)
As sh o w n belo w, the lsli operat io n take s a single a rg u ment in rsrc1 an d an imm e diate m odifier n and produces a
result in rdest equal to rsrc1 logically shifted left by n bits. The value of n mus t be be tw ee n 0 an d 31, inc lusi ve. Z e ros
are s hi fted int o the LS B s of rdest while the MSBs shi fted out of rsrc1 are lost.
The lsli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 lsli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 lsli(3) r60 → r100 no ch ange, since guard is false
r20 = 1, r60 = 0x20 IF r20 lsli(3) r60 → r110 r110 ← 0x100
r70 = 0xfffffffc lsli(2) r70 → r120 r120 ← 0xfffffff0
r80 = 0xe lsli(30) r80 → r125 r125 ← 0x80000000
031
rsrc1
000
Left shifter
32 bits from rsrc1
031
rdest 3
000
Interm ediate result
(example: n = 3)
Shift amount n
from ope r ation mod if ier
SEE ALSO
asl asli asr asri lsl lsr
lsri rol roli
lsli
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-135 PRELIMINARY SPECIFICATION
Logical shift right
SYNTAX
[ IF rguard ] lsr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n ← rsrc2<4:0>
rdest<31:32–n> ← 0
rdest<31–n:0> ← rsrc1<31:n>
if rsrc2<31:5> != 0 {
rdest <- 0
}
}
ATTRIBUTES
Function unit shifter
Operation code 96
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the lsr operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
am ount, and rsrc1 is logically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as a shift
by 3 2 or more bi ts. Zeros fill vac ate d bits fro m the left .
The lsr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x7008000f, r20 = 1 lsr r30 r20 → r50 r50 ← 0x38040007
r30 = 0x7008000f, r42 = 2 lsr r30 r42 → r60 r60 ← 0x1c020003
r10 = 0, r30 = 0x7008000f, r44 = 4 IF r10 lsr r30 r44 → r70 no ch ange, since guard is false
r20 = 1, r30 = 0x7008000f, r44 = 4 IF r20 lsr r30 r44 → r80 r80 ← 0x07008000
r40 = 0x80030007, r44 = 4 lsr r40 r44 → r90 r90 ← 0x08003000
r30 = 0x7008000f, r45 = 0x1f lsr r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x1f lsr r30 r45 → r100 r100 ← 0x00000001
r30 = 0x7008000f, r45 = 0x20 lsr r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x80000000 lsr r30 r45 → r100 r100 ← 0x00000000
r30 = 0x8008000f, r45 = 0x23 lsr r30 r45 → r100 r100 ← 0x00000000
031
rsrc1 031
rsrc2
000
Right shifter
32 bits from rsrc1
031
rdest 28
000
Intermediate result
(example: n = 3)
rsrc2
S
S
S
SEE ALSO
asl asli asr asri lsl lsli
lsri rol roli
lsr
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-136
Logical shift right immediate
SYNTAX
[ IF rguard ] lsri(n) rsrc1 → rdest
FUNCTION
if rguard then {
rdest<31:32–n> ← 0
rdest<31–n:0> ← rsrc1<31:n>
}
ATTRIBUTES
Function unit shifter
Operation code 9
Nu mber of operands 1
Modif ier 7 bits
Modifier range 0..31
Latency 1
Issue slots 1, 2
DESCRIPTION
As sh o w n belo w, the lsri operat io n take s a single a rg u ment in rsrc1 and an imm e diate m odifier n and produces a
result in rdest that is equal to rsrc1 logically shifted right by n bits. The value of n mu st be bet we en 0 and 31, in clusi v e .
Zer os fi ll vacated bi ts fro m th e lef t.
The lsri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x7008000f lsri(1) r30 → r50 r50 ← 0x38040007
r30 = 0x7008000f lsri(2) r30 → r60 r60 ← 0x1c020003
r10 = 0, r30 = 0x7008000f IF r10 lsri(4) r30 → r70 no ch ange, since guard is false
r20 = 1, r30 = 0x7008000f IF r20 lsri(4) r30 → r80 r80 ← 0x07008000
r40 = 0x80030007 lsri(4) r40 → r90 r90 ← 0x08003000
r30 = 0x7008000f lsri(31) r30 → r100 r100 ← 0x00000000
r40 = 0x80030007 lsri(31) r40 → r110 r110 ← 0x00000001
000
Right shifter
32 bits from rsrc1
031
rdest 28
000
Intermediate result
(example: n = 3) S
S
031
rsrc1
Shift amount n
from ope r ation mod if ier
S
SEE ALSO
asl asli asr asri lsl lsli
lsr rol roli
lsri
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-137 PRELIMINARY SPECIFICATION
mergedual16lsb Merge du al 16-bit lsb bytes
SYNTAX
[ IF rguard ] mergedual16lsb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<31:24> <- rsrc1<23:16>
rdest<23:16> <- rsrc1<7: 0>
rdest<15:8> <- rsrc2<23:16>
rdest<7:0> <- rsrc2<7:0>
}
ATTRIBUTES
Function unit shifter
Operation code 103
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency 1
Issue slots 1,2
DESCRIPTION
The arguments rsrc1 and rsrc2 are vectors of two 16-bit data. The mergedual16lsb operation merges the least
s ignificant b y tes from ea ch 16- bit data rsrc1 and rsrc2 into one 32-bit data in dest register, to convert to quad 8-bit.
Th e me rgedu al 16ls b op erat ion optio nall y t akes a gu ard , sp ecifi ed in rg uard . If a guard is pre sent , it s LS B con tro ls
the modif ication of th e d estination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not chan ged.
EXAMPLES
Initial Values Operation Result
r30 = 0x12345678, r40 = 0xaabbccdd mergedual16lsb r30 r40 -> r50 r50 <- 0x3478bbdd
r10 = 0, r30 = 0x12345678, r40 = 0xaabbccdd IF r10 mergedual16lsb r30 r40 -> r50 no change, since guard is
false
r10 = 1, r30 = 0x01020304, r40 = 0x0a0b0c0d IF r10 mergedual16lsb r30 r40 -> r50 r50 <- 0x02040b0d
0
7
15
23
31
rsrc1 0
7
1523
31
rsrc2
07
152331
rdest
SEE ALSO
mergelsb mergemsb
pack16lsb pack16msb
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-138
Merg e least-significant byte
SYNTAX
[ IF rguard ] mergelsb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<7:0> ← rsrc2<7:0>
rdest<15:8> ← rsrc1<7:0>
rdest<23:16> ← rsrc2<15:8>
rdest<31:24> ← rsrc1<15:8>
}
ATTRIBUTES
Function unit alu
Operation code 57
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As shown bel ow, t he mergelsb operation interleaves the two pairs of least-significant bytes from th e arg uments
rsrc1 and rsrc2 into rdest. The least-significant byte from rsrc2 is packed into the least-significant byte of rdest; the
leas t-sig nific ant by te fro m rsrc1 is packed int o th e se co nd-le as t-si gn ifica nt byt e o f r dest; th e sec ond-l east-si gnifi cant
byte from rsrc2 is packed into the second-most-significant byte of rdest; and the second-least-significant byte from
rsrc1 is p acked into t he mos t -sig nif ic ant byte of rdest.
The mergelsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x12345678, r40 = 0xaabbccdd mergelsb r30 r40 → r50 r50 ← 0x56cc78dd
r10 = 0, r40 = 0xaabbccdd, r30 = 0x12345678 IF r10 mergelsb r40 r30 → r60 no change, since guard i s false
r20 = 1, r40 = 0xaabbccdd, r30 = 0x12345678 IF r20 mergelsb r40 r30 → r70 r70 ← 0xcc56dd78
07152331
rsrc1 07152331
rsrc2
07152331
rdest
SEE ALSO
pack16lsb pack16msb
packbytes mergemsb
mergelsb
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-139 PRELIMINARY SPECIFICATION
Merge most-significant byte
SYNTAX
[ IF rguard ] mergemsb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<7:0> ← rsrc2<23:15>
rdest<15:8> ← rsrc1<23:15>
rdest<23:16> ← rsrc2<31:24>
rdest<31:24> ← rsrc1<31:24>
}
ATTRIBUTES
Function unit alu
Operation code 58
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As shown below, the mergemsb ope rati on in te rleaves th e tw o pa irs o f m ost-s igni fi cant byte s fro m the a rg umen ts
rsrc1 and rsrc2 into rdest. The second-most-significant byte from rsrc2 is packed into the least-significant byte of
rdest; th e sec ond-mo st-si gnif icant byte from rsrc1 is pa cked int o the s econ d-l eas t-s ignif ican t byte of rdest; the most-
significant byte from rsrc2 is packe d int o th e s ec ond-mo st- s ign ific ant byt e o f rdest; and the most-significant byte from
rsrc1 is p acked into t he mos t -sig nif ic ant byte of rdest.
The mergemsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Re sult
r30 = 0x12345678, r40 = 0xaabbccdd mergemsb r30 r40 → r50 r50 ← 0x12aa34bb
r10 = 0, r40 = 0xaabbccdd, r30 = 0x12345678 IF r10 mergemsb r40 r30 → r60 no ch ange, since guard is false
r20 = 1, r40 = 0xaabbccdd, r30 = 0x12345678 IF r20 mergemsb r40 r30 → r70 r70 ← 0xaa12bb34
07152331
rsrc1 07152331
rsrc2
07152331
rdest
SEE ALSO
pack16lsb pack16msb
packbytes mergelsb
mergemsb
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-140
No operation
SYNTAX
nop
FUNCTION
No operation
ATTRIBUTES
Function unit -
Operation code -
Nu mber of operands -
Modifier -
Modifier ran ge -
Latency 1
Issue slots 1-5
DESCRIPTION
The NOP operation does not change any DS PC PU s tate. It is main ly us e d to fill-up the empt y i ssu e slots. On ly tw o
bit s ar e used t o code the N OP op e ration.
EXAMPLES
Initial Values Operation Result
r30 = 0x12345678, r40 =
0xaabbccdd nop No change in any regsiters
SEE ALSO
nop
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-141 PRELIMINARY SPECIFICATION
Pack least-significant 16-bit halfwords
SYNTAX
[ IF rguard ] pack16lsb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<15:0> ← rsrc2<15:0>
rdest<31:16> ← rsrc1<15:0>
}
ATTRIBUTES
Function unit alu
Operation code 53
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As shown below , the pack16lsb opera t io n packs the tw o le ast -si g nifi ca nt half wor d s fro m th e ar gumen t s rsrc1 and
rsrc2 into rdest. The halfword from rsrc1 i s p acke d int o th e m ost- si gn if i ca nt half wor d o f r dest; the halfword from rsrc2
is packed into the least-significant halfword of rdest.
The pack16lsb o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Re sult
r30 = 0x12345678, r40 = 0xaabbccdd pack16lsb r30 r40 → r50 r50 ← 0x5678ccdd
r10 = 0, r40 = 0xaabbccdd, r30 = 0x12345678 IF r10 pack16lsb r40 r30 → r60 no change, since guard is f als e
r20 = 1, r40 = 0xaabbccdd, r30 = 0x12345678 IF r20 pack16lsb r40 r30 → r70 r70 ← 0xccdd5678
01531
rsrc1 01531
rsrc2
01531
rdest
SEE ALSO
pack16msb packbytes
mergelsb mergemsb
pack16lsb
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-142
P ack most-significant 16 bits
SYNTAX
[ IF rguard ] pack16msb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<15:0> ← rsrc2<31:16>
rdest<31:16> ← rsrc1<31:16>
}
ATTRIBUTES
Function unit alu
Operation code 54
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As sh o wn be lo w, the pack16msb operation packs the two most-significant halfwords from the arguments rsrc1 and
rsrc2 into rdest. The halfword from rsrc1 i s p acke d int o th e m ost- si gn if i ca nt half wor d o f r dest; the halfword from rsrc2
is packed into the least-significant halfword of rdest.
The pack16msb o per at ion op tion ally ta kes a g ua r d, sp ec ified i n rguard. If a gu ar d is presen t , its LSB c ontrols the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0x12345678, r40 = 0xaabbccdd pack16msb r30 r40 → r50 r50 ← 0x1234aabb
r10 = 0, r40 = 0xaabbccdd, r30 = 0x12345678 IF r10 pack16msb r40 r30 → r60 no change, since guard i s false
r20 = 1, r40 = 0xaabbccdd, r30 = 0x12345678 IF r20 pack16msb r40 r30 → r70 r70 ← 0xaabb1234
01531
rsrc1 01531
rsrc2
01531
rdest
SEE ALSO
pack16lsb packbytes
mergelsb mergemsb
pack16msb
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-143 PRELIMINARY SPECIFICATION
Pack least-significant byte
SYNTAX
[ IF rguard ] packbytes rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<7:0> ← rsrc2<7:0>
rdest<15:8> ← rsrc1<7:0>
}
ATTRIBUTES
Function unit alu
Operation code 52
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As shown below, the packbytes operation packs the two least-significant bytes from the arguments rsrc1 and
rsrc2 into rdest. The byte from rsrc1 is packed into the second-least-significant byte of rdest; t he byte from rsrc2 is
packed into the lea st- s ignific ant byte of rdest. The two most-significant bytes of rdest are filled with zeros.
The packbytes o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Re sult
r30 = 0x12345678, r40 = 0xaabbccdd packbytes r30 r40 → r50 r50 ← 0x000078dd
r10 = 0, r40 = 0xaabbccdd, r30 = 0x12345678 IF r10 packbytes r40 r30 → r60 no change, since guard is f als e
r20 = 1, r40 = 0xaabbccdd, r30 = 0x12345678 IF r20 packbytes r40 r30 → r70 r70 ← 0x0000dd78
07152331
rsrc1 07152331
rsrc2
07152331
rdest 0000000000000000
SEE ALSO
pack16lsb pack16msb
mergelsb mergemsb
packbytes
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-144
prefetch
pseudo-op for prefd(0)
SYNTAX
[ IF rguard ] pref rsrc1
FUNCTION
if rguard then {
cac he_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + 0) & cache_block_mask]
}
ATTRIBUTES
Function unit dmemspec
Operation code 209
Nu mber of operands 1
Modifier -
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
The pref operation is a pseudo operation transformed by t he scheduler into an prefd(0) with the same arguments.
(N ote: pseudo oper ations cannot be use d in ass embly fi le s. )
Th e p r ef op er at ion l o a ds th e o ne full cache block siz e of m e mory value fr om the addr e s s computed by ((rsrc1+0) &
cac he_block_m ask) and st ores the data into the data cac he. This operation is not guaranteed to be executed. The
prefetch unit will not execute this operation when the data to be prefetched is already in the data cache. A pref
operation will not be ex ecuted when the cache is already occupied with 2 cache misses, when the operation is issued.
The pref operation o ptionally takes a guard, specified in rguard. If a guard is present, its LSB controls the execution
of th e prefetch op era tion. If the L SB of rguard is 1, p refet ch op e r a t ion is ex ecuted ; oth erwis e, it i s not execu t ed.
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guaranteed to be available in future generat ions of Trimedia
products.
Initial Values Operation Result
r10 = 0xabcd,
cache_block_size = 0x40 pref r10 Loads a cache line for the address space from
0xabc0 to 0x0xabff from the main memory. If the data
is already in the cache, the operation is not e xecuted.
r10 = 0xab cd, r11 = 0,
cache_block_size = 0x40 IF r11 pref r10 since guard is false, pref operation is not executed
r10 = 0xabff, r11 = 1,
cache_block_size = 0x40 IF r11 pref r10 Loads a cache line for the address space from
0xabc0 to 0x0xabff from the main memory. If the data
is already in the cache, the operation is not e xecuted.
SEE ALSO
pref16x pref32x prefd
prefr allocd allocr allocx
pref
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-145 PRELIMINARY SPECIFICATION
pref16x prefetch with 16-bit scaled index
SYNTAX
[ IF rguard ] pref16x rsrc1 rsrc2
FUNCTION
if rguard then {
cac he_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + (2 x rscr2)) & cache_block_mask]
}
ATTRIBUTES
Function unit dmemspec
Operation code 211
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
The pref16x operation loads one full cache block from the main memory at the address computed by ((rsrc1+ (2 x
rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will no t execute this operat ion when the data to be prefetched is already in the data cache.
The data cache has hardware to simultaneously sustain two cache misses or prefetches. A pref16x operation will not
be execu ted w hen t h e ca che is alr ead y oc cupied w ith 2 cache miss es, when t h e op er ation is iss ued.
The pref16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guar anteed to be available in future generations of Trim edia
products.
Initial Values Operation Result
r10 = 0xab cd, r12 = 0x c
cache_block_size = 0x40 pref16x r10 r12 Loads a cache line for the address space from
0xabc0 to 0xabff from the main memory. If the data is
alrea dy i n the cache, the oper atio n is not executed .
r10 = 0xabcd, r11 = 0, r12=0xc,
cache_block_size = 0x40 IF r11 pref16x r10 r12 since guard is false, pref16x operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40 IF r11 pref16x r10 r12 Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not executed.
SEE ALSO
pref32x prefd prefr allocd
allocr allocx
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-146
prefetch with 32-bit scaled index
SYNTAX
[ IF rguard ] pref32x rsrc1 rsrc2
FUNCTION
if rguard then {
cac he_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + (4 x rscr2)) & cache_block_mask]
}
ATTRIBUTES
Function unit dmemspec
Operation code 212
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
The pref32x operation loads the one full cache block size of mem ory value from the a ddress compute d by ((r src1+ (4
x rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will no t execute this operat ion when the data to be prefetched is already in the data cache.
A pref32x operation will not be executed when the cache is already occupied with 2 cache misses, when the operation
is issued.
The pref32x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed..
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guar anteed to be available in future generations of Trim edia
products.
Initial Values Operation Result
r10 = 0xab cd, r12 = 0x d
cache_block_size = 0x40 pref32x r10 r12 Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not e xecuted.
r10 = 0xabcd, r11 = 0, r12=0xd,
cache_block_size = 0x40 IF r11 pref32x r10 r12 since guard is false, pref32x operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40 IF r11 pref32x r10 r12 Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not e xecuted.
SEE ALSO
pref16x prefd prefr allocd
allocr allocx
pref32x
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-147 PRELIMINARY SPECIFICATION
prefd prefetch with displacement
SYNTAX
[ IF rguard ] prefd(d) rsrc1
FUNCTION
if rguard then {
cac he_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + d) & cache_block_mask]
}
ATTRIBUTES
Function unit dmemspec
Operation code 209
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency -
Issue slots 5
DESCRIPTION
The prefd operation loads the one full cache block si ze of memor y va lue from the address computed by ((rsrc1+d) &
cac he_block_m ask) and st ores the data into the data cac he. This operation is not guaranteed to be executed. The
prefetch unit will not execute this operation when the data to be prefetched is already in the data cache. A prefd
operation will not be ex ecuted when the cache is already occupied with 2 cache misses, when the operation is issued.
The prefd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the execution
of th e prefetch op era tion. If the L SB o f rgu a rd i s 1, prefet ch ope rat ion is ex e cuted; othe r wis e, it i s not execu te d..
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guar anteed to be available in future generations of Trim edia
products.
Initial Values Operation Result
r10 = 0xabcd,
cache_block_size = 0x40 prefd(0xd) r10 Loads a cache line for the address space from
0xabc0 to 0x0xabff from the main memory. If the data
is already in the cache, the operation is not executed.
r10 = 0xab cd, r11 = 0,
cache_block_size = 0x40 IF r11 prefd(0xd) r10 since guard is false, prefd operation is not executed
r10 = 0xabff, r11 = 1,
cache_block_size = 0x40 IF r11 prefd(ox1) r10 Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not executed.
SEE ALSO
pref16x pref32x prefr
allocd allocr allocx
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-148
pr efetch wit h index
SYNTAX
[ IF rguard ] prefr rsrc1 rsrc2
FUNCTION
i f rguard then {
cac he_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + rscr2) & cache_block_mask]
}
ATTRIBUTES
Function unit dmemspec
Operation code 210
Nu mber of operands 2
Modifier No
Modifier ran ge -
Latency -
Issue slots 5
DESCRIPTION
The prefr operation loads the one full cache block size of memory value from the address computed by
((rsrc1+r scr2) & cache_block_mas k) and st ores the data into th e data cache. This opera ti on is not guaranteed to b e
executed. The prefetch unit will no t execute this operat ion when the data to be prefetched is already in the data cache.
A prefr operation will not be executed when the cache is already occupied with 2 cache misses, when the operation is
issued.
The prefr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed..
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guar anteed to be available in future generations of Trim edia
products.
Initial Values Operation Result
r10 = 0xab cd, r12 = 0x d
cache_block_size = 0x40 prefr r10 r12 Loads a cache line for the address space from
0xabc0 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not e xecuted.
r10 = 0xabcd, r11 = 0, r12=0xd,
cache_block_size = 0x40 IF r11 prefr r10 r12 since guard is false, prefr operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40 IF r11 prefr r10 r12 Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the data
is already in the cache, the operation is not e xecuted.
SEE ALSO
pref16x pref32x prefd
allocd allocr allocx
prefr
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-149 PRELIMINARY SPECIFICATION
Un sig ned byte-wise q ua d avera ge
SYNTAX
[ IF rguard ] quadavg rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← (zero_ext8to32(rsrc1<7:0>) + zero_ext8to32(rsrc2<7:0>) + 1) / 2
rdest<7:0> ← temp<7:0>
temp ← (zero_ext8to32(rsrc1<15:8> ) + zero_ext8to3 2(rsrc2<15:8>) + 1) / 2
rdest<15:8> ← temp<7:0>
temp ← (zero_ext8to32(rsrc1<23:16> ) + zero_ext8to 32( r src2<23:16>) + 1) / 2
rdest<23:16> ← temp<7:0>
temp ← (zero_ext8to32(rsrc1<31:24> ) + zero_ext8to 32( r src2<31:24>) + 1) / 2
rdest<31:24> ← temp<7:0>
}
ATTRIBUTES
Function unit dspalu
Operation code 73
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As sh own below, t he quadavg operation computes four separate averages of the four pairs of corresponding 8-bit
byte s of r src1 and rsrc2. Al l byt es are con side red unsi gned . T he lea st- sig nific ant 8 bit s of e ach averag e is w ri tte n to
the corre spondi ng b y te in rdest. N o overflow or unde r fl ow detectio n is pe r forme d.
The quadavg operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Re sult
r30 = 0x02 01000e, r40 = 0xffffff02 quadavg r30 r40 → r50 r50 ← 0x81808008
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c IF r10 quadavg r60 r70 → r80 no ch ange, since guard is fa l se
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c IF r20 quadavg r60 r70 → r90 r90 ← 0x809c6480
01531
rsrc1 01531
rsrc2
031
rdest
+
+
+
+
23 7 23 7
1
1
1
1
71523
08 0808 08
F our fu ll -pre c is ion
9-bit sums
unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned
unsigned unsigned unsigned unsigned
unsigned unsigned unsigned unsigned
SEE ALSO
iavgonep dspuquadaddui
ifir8ii
quadavg
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-150
Un sign ed byte- wise quad maximum
SYNTAX
[ IF rguard ] quadumax rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<7:0> ← if rsrc1<7:0> > rsrc2<7:0> then rsrc1<7:0> else rsrc2<7:0>
rdest<15:8> ← if rsrc1<15:8> > rsrc2<15:8> then rsrc1<15:8> else rsrc2<15:8>
rdest<23:16> ← if rsrc1<23:16> > rsrc2<23:16> then rsrc1<23:16> else rsrc2<23:16>
rdest<31:24> ← if rsrc1<31:24> > rsrc2<31:24> then rsrc1<31:24> else rsrc2<31:24>
}
ATTRIBUTES
Function unit dspalu
Operation code 81
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1,3
DESCRIPTION
The quadumax op er ation com putes four se para te ma ximum values of the fou r pa ir s of co r r es ponding 8- bit byt es of
rsrc1 and rsrc2. All bytes are considered unsigned. The quadumax operation is particularly suited to implement
median computation on packed pixel data structures:
MEDIAN_Q(a,b ,c) (QUADUMIN( QUADUMAX( QUADUMIN((a),(b)), (c)), QUADUMAX((a),(b))))
The quadumax operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x0201000e, r40 = 0xff00ff02 quadumax r30 r40 → r50 r50 ← 0xff01ff0e
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649d649c IF r10 quadumax r60 r70 → r80 no change, since guard is f als e
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649d649c IF r20 quadumax r60 r70 → r90 r90 ← 0x9c9d649c
SEE ALSO
imax imin quadumin
quadumax
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-151 PRELIMINARY SPECIFICATION
quadumin Unsigned bytewise quad minimum
SYNTAX
[ IF rguard ] quadumin rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
rdest<7:0> ← if rsrc1<7:0> < rsrc2<7:0> then rsrc1<7:0> else rsrc2<7:0>
rdest<15:8> ← if rsrc1<15:8> < rsrc2<15:8> then rsrc1<15:8> else rsrc2<15:8>
rdest<23:16> ← if rsrc1<23:16> < rsrc2<23:16> then rsrc1<23:16> else rsrc2<23:16>
rdest<31:24> ← if rsrc1<31:24> < rsrc2<31:24> then rsrc1<31:24> else rsrc2<31:24>
}
ATTRIBUTES
Function unit dspalu
Operation code 80
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1,3
DESCRIPTION
The quadumin operation computes four separate minimum values of the four pairs of corresponding 8-bit bytes of
rsrc1 and rsrc2. All bytes are considered unsigned. The quadumin operation is particularly suited to implement
median computation on packed pixel data structures:
MEDIAN_Q(a,b,c) (QUADUMIN(QUADUMAX( QUADUMIN((a),(b)), (c)), QU ADUMAX((a),(b))))
The quadumin operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x0201000e, r40 = 0xff00ff02 quadumin r30 r40 → r50 r50 ← 0x02000002
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649d649c IF r10 quadumin r60 r70 → r80 no change, since guard i s false
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649d649c IF r20 quadumin r60 r70 → r90 r90 ← 0x649c6464
SEE ALSO
imin imax quadumax
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-152
Unsigned quad 8-bit mu ltiply most significant
SYNTAX
[ IF rguard ] quadumulmsb rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp ← (zero_ext8to32(rsrc1<7:0>) ×zero_ext8to32(rsrc2<7:0>))
rdest<7:0> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<15:8>) ×zero_ext8to32(rsrc2<15:8>))
rdest<15:8> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<23:16>) ×zero_ext8to32(rsrc2<23:16>))
rdest<23:16> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<31:24>) ×zero_ext8to32(rsrc2<31:24>))
rdest<31:24> ← temp<15:8>
}
ATTRIBUTES
Function unit dspmul
Operation code 89
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As sh o w n belo w, the quadumulmsb o perat i o n com putes fo ur se parat e p roduc t s of the four pairs of c o rrespondi n g
8-b it bytes of rsrc1 an d rsrc2. All bytes are considered unsigned. The most-significant 8 bits of each 16-bit product is
wri tte n to th e co r res pond in g byte i n rdest.
The quadumulmsb op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x02 10800e, r40 = 0xffffff02 quadumulmsb r30 r40 → r50 r50 ← 0x010f7f00
r10 = 0, r60 = 0x80ff1010, r70 = 0x80ff100f IF r10 quadumulmsb r60 r70 → r80 no change, since guard i s false
r20 = 1, r60 = 0x80ff1010, r70 = 0x80ff100f IF r20 quadumulmsb r60 r70 → r90 r90 ← 0x40fe0100
01531
rsrc1 01531
rsrc2
031
rdest
×
×
×
×
23 7 23 7
71523
715
Four full-precision
16-bit products
0 715 0 715 0 715 0
unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned
unsigned unsigned unsigned unsigned
unsigned unsigned unsigned unsigned
SEE ALSO
quadavg dspuquadaddui
ifir8ii
quadumulmsb
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-153 PRELIMINARY SPECIFICATION
Read data cache status bits
SYNTAX
[ IF rguard ] rdstatus(d) rsrc1 → rdest
FUNCTION
if rguard then {
set_addr ← rsrc1 + d
/* set_addr<10:6> selects set */
rdest<9:0> ← dcache_LRU_set(set_addr)
rdest<17:10> ← dcache_dirty_set(set_addr)
rdest<31:18> ← 0
}
ATTRIBUTES
Function unit dmemspec
Operation code 203
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency 3
Issue slots 5
DESCRIPTION
The rdstatus opera t ion read s th e LRU an d dirty bits as soc ia t ed wit h a set in the dat a cach e an d wr ite s the se bit s
into the destination register rdest. T he target s et in the data cache is determined by bit s 10..6 of t he result of rsrc1 + d.
The d value is an opcode modifi er, must be in the range –256 to 252 inclusive, and must be a multiple of 4.
The result of rdstatus con ta i ns LRU inf o rmat i on in bits 9..0 and d irty -bit information in bits 17..10. All other bits of
rdest are set to zero.
rdstatus requires two stall cycles to complete.
The dual-ported data cache uses two separate copies of tag and status information. A rdstatus oper a tio n r eturn s
the LRU and dirty info rmation stored in the cache port that corresponds to the operation slot in which the rdstatus
oper a tio n is is s ue d.
The rdstatus operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
rdstatus(0) r30 → r60
r10 = 0 IF r10 rdstatus(4) r40 → r70 no change, since guard i s false
r20 = 1 IF r20 rdstatus(8) r50 → r80
SEE ALSO
rdtag
rdstatus
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-154
Rea d data cac he addr ess tag
SYNTAX
[ IF rguard ] rdtag(d) rsrc1 → rdest
FUNCTION
if rguard then {
block_addr ← rsrc1 + d
/* block_addr<13:11> selects element, block_addr<10:6> selects set */
rdest<21:0> ← dcache_tag_block(block_addr)
rdest<31:22> ← 0
}
ATTRIBUTES
Function unit dmemspec
Operation code 202
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency 3
Issue slots 5
DESCRIPTION
The rdtag operation read s the address tag associated with a block in the data cache and writes these bits into the
destination register rdest. T he t a rg et blo ck in the da t a c ac h e is d et ermined by bi ts 1 3. . 6 o f the res ul t of rsrc1 + d. Bits
10..6 of rsrc1 + d select the cache set and 13..11 of rsrc1 + d select the element within that set. The d value is an
opcode modifier, must be in the range –256 t o 252 in clus ive, and mus t b e a multiple of 4.
rdtag writes the address tag for the selected block in bits 2 1..0 of rdest. A ll other bits of rdest are set to zero.
rdtag requires no stall cycles to complete.
The dual-ported data cache uses two separate copies of tag and status information. A rdtag operation returns the
address tag information stored in the cache port that corresponds to the operation slot in which the
rdtag operation
is issued.
The rdtag operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
rdtag(0) r30 → r60
r10 = 0 IF r10 rdtag(4) r40 → r70 no ch ange, since guard is false
r20 = 1 IF r20 rdtag(8) r50 → r80
SEE ALSO
rdstatus
rdtag
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-155 PRELIMINARY SPECIFICATION
Re ad de sti na tio n prog ra m counter
SYNTAX
[ IF rguard ] readdpc → rdest
FUNCTION
if rguard then {
rdest ← DPC
}
ATTRIBUTES
Function unit fcomp
Operation code 156
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The readdpc writes the current value of the DPC (Destination Program Counter) processor register to rdest.
Interruptible jumps write their target address to the DPC. If an interrupt or exception is taken at an interruptible jump,
execution of the interrupted program can be resumed by jumping to the value contained in DPC. This operation can be
used to save s tate before idling a tas k in a mult i-ta sking e n v ir onment .
The readdpc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
DPC = 0xbeebee readdpc → r100 r100 ← 0xbeebee
r20 = 0, DPC = 0xabba IF r20 readdpc → r101 no change, since guard is false
r21 = 1, DPC = 0xabba IF r21 readdpc → r102 r102 ← 0xabba
SEE ALSO
writedpc readspc ijmpf
ijmpi ijmpt
readdpc
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-156
Re ad progra m control and sta tus word
SYNTAX
[ IF rguard ] readpcsw → rdest
FUNCTION
if rguard then {
rdest ← PCSW
}
ATTRIBUTES
Function unit fcomp
Operation code 158
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The readpcsw writes the current value of the PCSW (Program Control and Status Word) processor register to
rdest. The layout of PCSW is shown below.
Fields in t he PCSW have two chief purposes: to co ntrol aspects of proc essor ope ration and to record events that
occur during program execution. Thus, readpcsw can be used t o determine current processor operating modes and
what events have occurred; this operation can also be used to save state before idling a task in a multi-tasking
environment.
The readpcsw operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
PCSW = 0x80110 642 readpcsw → r100 r100 ← 0x80110642 (trap on MSE, INV and DBZ
enabled, IEN=1 - interru pts enabled, BSX =1 - littl e
endian mode of operation, OFZ=1 - a denormalized
result was produced somewhere, INX=1 - an inexact
result was produced somewhere)
r20 = 0, PCSW = 0x80000000 IF r20 readpcsw → r101 no change, since guard is false
r21 = 1, PCSW = 0x80000000 IF r21 readpcsw → r102 r102 ← 0x80000000 (trap on MSE enabled)
MSE CS IEN BSX I EEE MODE OFZ IFZ INV OVF UNF INX DBZ
01234567891011121415
Misaligned store exce p tion
Count stalls (1 ⇒ Yes)
FP exception trap-enable bits
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW<31:16>
PCSW<15:0> UNDEF
Misaligned store
exceptio n tr ap enable Trap on first exit
FP exceptions
TRP
MSE TFE TRP
OFZ TRP
IFZ TRP
INV TRP
OVF TRP
UNF TRP
INX TRP
DBZ
1617181920212223252627283031
UNDEF UNDEFINED
13
WBE RSE
Write back error
Reserved exception
TRP
WBE TRP
RSE
Write back error trap enable Reserved exception
trap enabl e
29
SEE ALSO
writepcsw
readpcsw
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-157 PRELIMINARY SPECIFICATION
Rea d sourc e progra m counter
SYNTAX
[ IF rguard ] readspc → rdest
FUNCTION
if rguard then {
rdest ← SPC
}
ATTRIBUTES
Function unit fcomp
Operation code 157
Nu mber of operands 0
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The readspc writes the current value of the SPC (Source Program Counter) processor register to rdest.
An interr u ptible jum p that i s not i nterrupted ( n o N MI, I N T, or EX C event was p endi ng w hen t h e j ump wa s executed )
writes its target address to SPC. The value of SPC allows an exception-handling routine to determine the start
address of the block of scheduled code (called a decision tree) that was executing before the exception was
ta ken. Th is op era tio n ca n be u sed to save state befor e idling a ta sk in a multi-tas king environment.
The readspc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
SPC = 0xbeebee readspc → r100 r100 ← 0xbeebee
r20 = 0, SPC = 0xabba IF r20 readspc → r101 no change , since guard is false
r21 = 1, SPC = 0xabba IF r21 readspc → r102 r102 ← 0xabba
SEE ALSO
writespc readdpc ijmpf
ijmpi ijmpt
readspc
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-158
Rotate left
SYNTAX
[ IF rguard ] rol rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
n ← rsrc2<4:0>
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← rsrc1<31:32–n>
}
ATTRIBUTES
Function unit shifter
Operation code 97
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the rol operation takes two arguments, rsrc1 and rsrc2. The least-significant five bits of rsrc2
speci f y an un si gned rotate a m ou nt, and rdest is set to r src1 ro ta ted le ft by th is amo un t. The m os t-sig ni fic ant n bit s of
rsrc1, where n is the rotate amount, appear as the least-significant n bits in rdest.
The rol operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 rol r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 rol r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x20, r30 = 3 IF r20 rol r60 r30 → r110 r110 ← 0x100
r70 = 0xfffffffc, r40 = 2 rol r70 r40 → r120 r120 ← 0xfffffff3
r80 = 0xe, r50 = 0xfffffffe rol r80 r50 → r125 r125 ← 0x80000003 (r50 is effec tively equal to 0x1e)
031
rsrc1 031
rsrc2 4n
Left rotator
32 bits from rsrc1
031
rdest 9
Intermediate result
(example: n = 9)
Five LSBs of rsrc2
031 32 bits from rsrc1 03123 23
SEE ALSO
roli asr asri lsl lsli lsr
lsri
rol
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-159 PRELIMINARY SPECIFICATION
Rotate left by immediate
SYNTAX
[ IF rguard ] roli(n) rsrc1 → rdest
FUNCTION
if rguard then {
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← rsrc1<31:32–n>
}
ATTRIBUTES
Function unit shifter
Operation code 98
Nu mber of operands 1
Modifier 7 bits
Modifier range 0..31
Latency 1
Issue slots 1, 2
DESCRIPTION
As shown below, the roli opera tion takes a sing le a rg u me n t in rsrc1 and an imm e diate m odifier n and produces a
result in rdest equal to rsrc1 rotated left by n bits. The value of n must be between 0 and 31, inclusive. The most-
significant n bits of rsrc1 appear as the least-significant n bits in rdest.
The roli operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 roli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 roli(3) r60 → r100 no ch ange, since guard is fa l se
r20 = 1, r60 = 0x20 IF r20 roli(3) r60 → r110 r110 ← 0x100
r70 = 0xfffffffc roli(2) r70 → r120 r120 ← 0xfffffff3
r80 = 0xe roli(30) r80 → r125 r125 ← 0x80000003
Rotate am ount n
from ope r ation mod if ier
031
rsrc1
Left rotator
32 bits from rsrc1
031
rdest 9
Intermediate result
(example: n = 9)
031 32 bits from rsrc1 03123 23
SEE ALSO
rol asl asli asr asri lsl
lsli lsr lsri
roli
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-160
Sign extend 16 bits
SYNTAX
[ IF rguard ] sex16 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← sign_ext16to32(rsrc1<15:0>)
ATTRIBUTES
Function unit alu
Operation code 51
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As show n below, t he sex16 operation sign extends the least-significant 16bit halfword of the argument, rsrc1, to 32
bit s an d st or e s the res ult in rdest.
The sex16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of the guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 sex16 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 sex16 r40 → r70 no change, since guard is false
r20 = 1, r40 = 0xff0fff91 IF r20 sex16 r40 → r100 r100 ← 0xffffff91
r50 = 0x00000091 sex16 r50 → r110 r110 ← 0x00000091
01531
rsrc1
031
rdest 15
S
SSSSSSSSSSSSSSSSS
signed
signed
SEE ALSO
zex16 sex8 zex8
sex16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-161 PRELIMINARY SPECIFICATION
Sign extend 8 bits
pseudo-op for ibytesel
SYNTAX
[ IF rguard ] sex8 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← sign_ext8to32(rsrc1<7:0>)
ATTRIBUTES
Function unit alu
Operation code 56
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The sex8 operation is a pseudo operation transformed by the scheduler into a ibytesel with rsrc1 as the first
argument and r0 (always contains 0) as the second. (Note: pseudo operations cannot be used in assembly source
files.)
As shown below, the sex8 operation sign extends the least-significant halfword of the argument, r src1, to 32 bits
and w rites the result in rdest.
The sex8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 sex8 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 sex8 r40 → r70 no change, since guard is false
r20 = 1, r40 = 0xff0fff91 IF r20 sex8 r40 → r100 r100 ← 0xffffff91
r50 = 0x00000091 sex8 r50 → r110 r110 ← 0xffffff91
01531
rsrc1
031
rdest 15 7
7
23
23
S
S
SSSSSSSSSSSSSSSSSSSSSSSS
signed
signed
SEE ALSO
ibytesel sex16 zex8 zex16
sex8
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-162
16-bit store
pseudo-op for h_st16d(0)
SYNTAX
[ IF rguard ] st16 rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
mem[rsrc1 + (1 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + (0 ⊕ bs)] ← rsrc2<15:8>
}
ATTRIBUTES
Function unit dmem
Operation code 30
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st16 operation is a pseudo operation transformed by the scheduler into an h_st16d(0) with the same
arguments. (N ote: ps eudo ope rations cannot be used in assembl y files .)
The st16 operation stores the least-significant 16-bit halfword of rsrc2 into th e m emo ry l oc a tio ns poin ted to by the
ad dres s in r src1. This store operation is performed as little-endian or big-endian depending on the current sett ing of
th e bytesex bit i n the P C SW.
If st16 is misa ligned ( the mem ory addr e ss in r src1 is not a mu ltipl e o f 2), the r e sult of st16 is undefined, and the
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misali gned Stor e E x cep t io n) bi t in P C SW is 1, exc eption pr o ces sing will be r eq ues t ed on the n ext in terr uptibl e jump.
The result of an access by st16 to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The st16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r80 = 0x44332211 st16 r10 r80 [0xd00] ← 0x22, [0xd01] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd IF r50 st16 r20 r70 no change, since guard i s false
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd IF r60 st16 r30 r70 [0xd02] ← 0xcc, [0xd03] ← 0xdd
SEE ALSO
st16d h_st16d st8 st8d
st32 st32d
st16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-163 PRELIMINARY SPECIFICATION
16-bit store with displacement
pseudo-op for h_st16d
SYNTAX
[ IF rguard ] st16d(d) rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<15:8>
}
ATTRIBUTES
Function unit dmem
Operation code 30
Nu mber of operands 2
Modifier 7 bits
Modifier ran ge –128..126 by 2
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st16d operation is a pseudo operation transformed by the scheduler into an h_st16d with the same
arguments. (N ote: ps eudo ope rations cannot be used in assembl y files .)
The st16d oper a tio n st ore s the le as t- s igni fi ca nt 16 -bi t ha lfw o rd of r src2 into the memory locations pointed to by the
ad dre s s in r src1 + d. The d value is an opco de modifier, must be in the ra ng e –128 and 126 inclusive, and must be a
mult ipl e of 2. This stor e op erat ion i s per form ed a s litt le- endi an or big -en dian depe ndin g o n the cur rent setti ng of the
bytesex bit in the PCSW.
If st16d is misa lign ed ( the me mor y ad dre ss co mpu ted by rsrc1 + d is not a multiple of 2), the result of st16d is
undefin ed, an d the MSE (Misaligned Store Exception) bit in the PCSW registe r is set to 1. Additionally, if the TRPMSE
(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next
interruptible jump.
The result of an access by st16d to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The st16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
mod ifi catio n o f t he ad dressed m em or y locatio n s (and the modification of cache if th e locations are cachea ble). If the
LSB of rguard is 1, the store takes eff ect. If the LSB of rguard is 0, st16d has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xcf e, r80 = 0x44332211 st16d(2) r10 r80 [0xd00] ← 0x22, [0xd01] ← 0x11
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd IF r50 st16d(–4) r20 r70 no change, since guard is f alse
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd IF r60 st16d(–4) r30 r70 [0xd02] ← 0xcc, [0xd03] ← 0xdd
SEE ALSO
st16 h_st16d st8 st8d st32
st32d
st16d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-164
32-bit store
pseudo-op for h_st32d(0)
SYNTAX
[ IF rguard ] st32 rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
mem[rsrc1 + (3 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + (2 ⊕ bs)] ← rsrc2<15:8>
mem[rsrc1 + (1 ⊕ bs)] ← rsrc2<23:16>
mem[rsrc1 + (0 ⊕ bs)] ← rsrc2<31:24>
}
ATTRIBUTES
Function unit dmem
Operation code 31
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st32 operation is a pseudo operation transformed by the scheduler into an h_st32d(0) with the same
arguments. (N ote: ps eudo ope rations cannot be used in assembl y files .)
The st32 operation stores all 32 bits of rsrc2 into the memory locations pointed to by t he address in r src1. The d
value is an opcode modifier and must be a multiple of 4. This store operation is performed as little-endian or big-
endian dependin g on the current setting of the bytesex bit in the PCSW.
If st32 is misa ligned ( the mem ory address in rsrc1 is not a multiple of 4), the result of st32 is undefined, and the
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misali gned Stor e E x cep t io n) bi t in P C SW is 1, exc eption pr o ces sing will be r eq ues t ed on the n ext in terr uptibl e jump.
The st32 operation can be used to access t he MMIO address aperture (the result of MMIO access by 8- or 16-bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access b y st32.
The st32 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st32 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r80 = 0x44332211 st32 r10 r80 [0xd00] ← 0x44, [0xd01] ← 0x33,
[0xd02] ← 0x22, [0xd03] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd IF r50 st32 r20 r70 no change, since guard i s false
r60 = 1, r30 = 0xd04,
r70 = 0xaabbccdd IF r60 st32 r30 r70 [0xd04] ← 0xaa, [0xd05] ← 0xbb,
[0xd06] ← 0xcc, [0xd07] ← 0xdd
SEE ALSO
h_st32d st32d st16 st16d
st8 st8d
st32
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-165 PRELIMINARY SPECIFICATION
32-bit store with displacement
pseudo-op for h_st32d
SYNTAX
[ IF rguard ] st32d(d) rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
mem[rsrc1 + d + (3 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + d + (2 ⊕ bs)] ← rsrc2<15:8>
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<23:16>
mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<31:24>
}
ATTRIBUTES
Function unit dmem
Operation code 31
Nu mber of operands 2
Modifier 7 bits
Modifier ran ge –256..252 by 4
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st32d operation is a pseudo operation transformed by the scheduler into an h_st32d with the same
arguments. (N ote: ps eudo ope rations cannot be used in assembl y files .)
The st32d operation stores all 32 bits of rsrc2 into the memory locations pointed to by the address in rsrc1 + d.
The d value is an opcode modi fier, must be in the range –256 and 252 inclusive, and must be a multiple of 4. This
store operation is pe rformed as little-endian or big-endian de pending on the cu rrent s etting of the bytesex b it in the
PCSW.
If st32d is misa lign ed ( the me mor y ad dre ss co mpu ted by rsrc1 + d is not a multiple of 4), the result of st32d is
undefin ed, an d the MSE (Misaligned Store Exception) bit in the PCSW registe r is set to 1. Additionally, if the TRPMSE
(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next
interruptible jump.
The st32d oper ation can be use d to access the MM IO a ddress apert ure (the result of MMIO ac cess b y 8- or 16- bit
memory operations is undefined). The state of th e BSX bit in the PCSW has no effect on MMIO access by st32d.
The st32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
mod ifi catio n o f t he ad dressed m em or y locatio n s (and the modification of cache if th e locations are cachea ble). If the
LSB of rguard is 1, the store takes eff ect. If the LSB of rguard is 0, st32d has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xcfc, r80 = 0x44332211 st32d(4) r10 r80 [0xd00] ← 0x44, [0xd01] ← 0x33,
[0xd02] ← 0x22, [0xd03] ← 0x11
r50 = 0, r20 = 0xd0b,
r70 = 0xaabbccdd IF r50 st32d(–8) r20 r70 no change, since guard is f alse
r60 = 1, r30 = 0xd0c,
r70 = 0xaabbccdd IF r60 st32d(–8) r30 r70 [0xd04] ← 0xaa, [0xd05] ← 0xbb,
[0xd06] ← 0xcc, [0xd07] ← 0xdd
SEE ALSO
h_st32d st32 st16 st16d
st8 st8d
st32d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-166
8-bit store
pseudo-op for h_st8d(0)
SYNTAX
[ IF rguard ] st8 rsrc1 rsrc2
FUNCTION
if rguard then
mem[rsrc1] ← rsrc2<7:0>
ATTRIBUTES
Function unit dmem
Operation code 29
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st8 operation is a pseudo operation transformed by the scheduler into an h_st8d(0) with the same
arguments. (N ote: ps eudo ope rations cannot be used in assembl y files .)
The st8 ope rat i on s to r es t he le as t- s ig n i fi ca nt 8-bit by t e of rsrc2 into the memory location pointed to by the address
in rsrc1. T hi s op er ation doe s no t depend on t h e bytes ex bit i n the P C SW sinc e o nl y a si ngle byte is stored.
The result of an access by st8 t o the MM IO address ape rtu re is undefined; access to the MMIO apertur e is defined
only for 3 2- bit loads and stores.
The st8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifi catio n of the addr e sse d mem ory loca ti o n ( and t he mo di fication of cac h e if the location is cacheable). If the LSB
of rguard is 1, the store takes effect. If the LSB of rguard is 0 , st8 ha s no side effect s wha t ever; in particul ar, the LRU
and other st atus bits in t h e data c ac he a re not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r80 = 0x44332211 st8 r10 r80 [0xd00] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd IF r50 st8 r20 r70 no ch ange, since guard is false
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd IF r60 st8 r30 r70 [0xd02] ← 0xdd
SEE ALSO
h_st8d st8d st16 st16d
st32 st32d
st8
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-167 PRELIMINARY SPECIFICATION
8-bit store with displacement
pseudo-op for h_st8d
SYNTAX
[ IF rguard ] st8d(d) rsrc1 rsrc2
FUNCTION
if rguard then
mem[rsrc1 + d] ← rsrc2<7:0>
ATTRIBUTES
Function unit dmem
Operation code 29
Nu mber of operands 2
Modif ier 7 bits
Modifier ran ge –64..63
Latency n/a
Issue slots 4, 5
DESCRIPTION
The st8d operation is a pseudo operation transformed by the scheduler into an h_st8d with the same arguments.
(N ote: pseudo oper ations cannot be use d in ass embly fi le s. )
The st8d operation stores the least-significant 8-bit byte of rsrc2 into the memory location pointed to by the
address formed from the sum rsrc1 + d. T he val ue of the op code mod ifier d must be in the r ange -6 4 and 63 inclusive.
Th is operat ion does not depend on the bytesex bit in the PC SW since o nly a single byte is st ored.
The result of an access by st8d to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The st8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory location (and the modification of cache if th e loca tion is c acheable). If th e LS B
of rguard is 1 , the sto r e takes effe ct. If th e LSB of rguard is 0, st8d h as no side effects whatever; in partic ular, the LRU
and other st atus bits in t h e data c ac he a re not affected.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r80 = 0x44332211 st8d(3) r10 r80 [0xd03] ← 0x11
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd IF r50 st8d(-4) r20 r70 no change, since guard is fa l se
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd IF r60 st8d(-4) r30 r70 [0xcfe] ← 0xdd
SEE ALSO
h_st8d st8 st16 st16d st32
st32d
st8d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-168
Sele ct uns ign ed byte
SYNTAX
[ IF rguard ] ubytesel rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc2 = 0 then
rdest ← zero_ext8to32(rsrc1<7:0>)
else if rsrc2 = 1 then
rdest ← zero_ext8to32(rsrc1<15:8>)
else if rsrc2 = 2 then
rdest ← zero_ext8to32(rsrc1<23:15>)
else if rsrc2 = 3 then
rdest ← zero_ext8to32(rsrc1<31:24>)
}
ATTRIBUTES
Function unit alu
Operation code 55
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
As sh o wn below, the ubytesel operation selects one byte from the argument, rsrc1, ze ro- ex ten ds t he byte to 32
bits, and stores the result in rdest. The val ue of rsrc2 determin es which byte is selected, w ith rsrc2=0 selecting the
LSB of rsrc1 and rsrc2=3 selecting the MSB of rsrc1. If rsrc2 is not between 0 and 3 inclusive, the result of
ubytesel is undefined.
The ubytesel operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x44332211, r40 = 1 ubytesel r30 r40 → r50 r50 ← 0x00000022
r10 = 0, r60 = 0xddccbbaa, r70 = 2 IF r10 ubytesel r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0xddccbbaa, r70 = 2 IF r20 ubytesel r60 r70 → r90 r90 ← 0x000000cc
r100 = 0xffffff7f, r11 0 = 0 ubytesel r100 r110 → r120 r120 ← 0x0000007f
01531
rsrc1 031
rsrc2
23 7 1
031
rdest 7
0
3210
00000000000000000000000
unsigned unsigned unsigned unsigned
unsigned
SEE ALSO
ibytesel sex8 packbytes
ubytesel
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-169 PRELIMINARY SPECIFICATION
Clip signed to unsigned
SYNTAX
[ IF rguard ] uclipi rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← min(max(rsrc1, 0), rsrc2)
ATTRIBUTES
Function unit dspalu
Operation code 75
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The uclipi op era tion r etur n s the valu e of rsrc1 clipped into the unsigned integer range 0 to rsrc2, inclu sive. T he
argument rsrc1 is considered a signed integer; rsrc2 is co nsidered a n unsigned i n teger.
The uclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x80, r40 = 0x7f uclipi r30 r40 → r50 r50 ← 0x7f
r10 = 0, r60 = 0x12345678,
r70 = 0xabc IF r10 uclipi r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0x12345678,
r70 = 0xabc IF r20 uclipi r60 r70 → r90 r90 ← 0xabc
r100 = 0x80000000, r110 = 0x3fffff uclipi r100 r110 → r120 r120 ← 0
SEE ALSO
iclipi uclipu imin imax
uclipi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-170
Clip un signed to unsigned
SYNTAX
[ IF rguard ] uclipu rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 > rsrc2 then
rdest ← rsrc2
else
rdest ← rsrc1
}
ATTRIBUTES
Function unit dspalu
Operation code 76
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The uclipu op era tion r etur n s the valu e of rsrc1 clipped into the unsigned integer range 0 to rsrc2, inclu sive. T he
arg ume nt s rsrc1 and rsrc2 are c ons idered uns igned intege r s.
The uclipu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x80, r40 = 0x7f uclipu r30 r40 → r50 r50 ← 0x7f
r10 = 0, r60 = 0x12345678,
r70 = 0xabc IF r10 uclipu r60 r70 → r80 no change, since guard is false
r20 = 1, r60 = 0x12345678,
r70 = 0xabc IF r20 uclipu r60 r70 → r90 r90 ← 0xabc
r100 = 0x80000000, r110 = 0x3fffff uclipu r100 r110 → r120 r120 ← 0x3fffff
SEE ALSO
iclipi uclipi imin imax
uclipu
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-171 PRELIMINARY SPECIFICATION
Un sig ned compare equ al
pseudo-op fo r ieq l
SYNTAX
[ IF rguard ] ueql rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 = rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 37
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ueql operation is a pseudo operation transformed by the scheduler into an ieql w ith th e s ame argum ents .
(N ote: pseudo oper ations cannot be use d in ass embly fi le s. )
The ueql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.
The ueql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ueql r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ueql r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x1000 IF r20 ueql r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 ueql r70 r40 → r100 r100 ← 0
r70 = 0x80000000 ueql r70 r70 → r110 r110 ← 1
SEE ALSO
ieql ueqli igeq uneq
ueql
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-172
Un sign ed compa re equa l with imme diat e
SYNTAX
[ IF rguard ] ueqli(n) rsrc1 → rdest
FUNCTION
if rguard then {
if rsrc1 = n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 38
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ueqli ope ration sets th e destination register, rdest, to 1 if the first argument, rsrc1, is equal to the opcode
modifier, n; other wis e, rdest is set to 0 . The argument s are trea te d as un signe d i ntegers.
The ueqli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ueqli(2) r30 → r80 r80 ← 0
r30 = 3 ueqli(3) r30 → r90 r90 ← 1
r30 = 3 ueqli(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ueqli(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ueqli(63) r40 → r100 r100 ← 0
r60 = 0x07f ueqli(127) r60 → r120 r120 ← 1
SEE ALSO
ieqli ueql igeqi uneqi
ueqli
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-173 PRELIMINARY SPECIFICATION
Sum of pr oducts of unsig ned 16-bit halfwords
SYNTAX
[ IF rguard ] ufir16 rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← zero_ext16to32(rsrc1<31:16>) ×zero_ext16to32(rsrc2<31: 16> ) +
zero_ext16to32(rsrc1<15:0>) ×zero_ext16to32(rsrc2<15:0>)
ATTRIBUTES
Function unit dspmul
Operation code 94
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, the ufir16 operation computes two separate products of the two pairs of corresponding 16-bit
halfwords of rsrc1 and rsrc2; the two products are summed, and the result is written to rdest. All halfwords are
considered unsigned; thus, the intermediate products and the final sum of products are unsigned. All intermediate
com puta tions ar e perfor med witho ut los s of preci sion; th e fin al su m of produ cts is clip ped into the ra nge [0 xffff ffff..0]
before being writt en into rdest.
The ufir16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Re sult
r30 = 0x00020003, r40 = 0x00010002 ufir16 r30 r40 → r50 r50 ← 8
r10 = 0, r60 = 0x80000064, r70 = 0x00648000 IF r10 ufir16 r60 r70 → r80 no ch ange, since guard is false
r20 = 1, r60 = 0x80000064, r70 = 0x00648000 IF r20 ufir16 r60 r70 → r90 r90 ← 0x00640000
r30 = 0x00020003, r70 = 0x00648000 ufir16 r30 r70 → r100 r100 ← 0x000180c8
01531
rsrc1 01531
rsrc2
031
rdest
×
×+
unsigned unsigned unsigned unsigned
unsigned
032
Clip to [232–1..0]
Full-precision
33-bit result unsigned
SEE ALSO
ifir16 ifir8ii ifir8ui
ufir8uu
ufir16
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-174
Unsigned sum of products of unsigned bytes
SYNTAX
[ IF rguard ] ufir8uu rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(rsrc1<31:24>) ×zero_ext8to32(rsrc2<31:24>) +
zero_ext8to32(rsrc1<23:16>) ×zero_ext8to32(rsrc2<2 3:16> ) +
zero_ext8to32(rsrc1<15:8>) ×zero_ext8to32(rsrc2<15:8>) +
zero_ext8to32(rsrc1<7:0>) ×zero_ext8to32(rsrc2<7:0>)
ATTRIBUTES
Function unit dspmul
Operation code 90
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As sh o w n belo w, the ufir8uu o perat i on c omp ut e s four se para te produc t s of the four pai r s of co rre spondin g 8-b it
byte s o f r src1 an d rsrc2; the four products are summed, and the result is written to rdest. All values are considered
unsign ed. A ll co m pu t a tio ns a r e pe rfor m e d wi th ou t los s of prec is ion.
The ufir8uu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r70 = 0x0afb14f6, r30 = 0x0a0a1414 ufir8uu r70 r30 → r90 r90 ← 0x1efa
r10 = 0, r70 = 0x0afb14f6, r30 = 0x0a0a1414 IF r10 ufir8uu r70 r30 → r100 no change, since guard i s false
r20 = 1, r80 = 0x649c649c, r40 = 0x9c649c64 IF r20 ufir8uu r80 r40 → r110 r110 ← 0xf3c0
r50 = 0x80808080, r60 = 0xffffffff ufir8uu r50 r60 → r120 r120 ← 0x1fe00
01531
rsrc1 01531
rsrc2
031
rdest
×
×
+
×
×
23 7 23 7
unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned
unsigned
SEE ALSO
ifir8ui ifir8ii ifir16
ufir16
ufir8uu
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-175 PRELIMINARY SPECIFICATION
Co nvert flo atin g- po i nt to un sign ed inte ger usin g
PCSW roun ding m ode
SYNTAX
[ IF rguard ] ufixieee rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (unsigned long) ((float)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 123
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufixieee operation converts the single-precision IEEE floating-point value in rsrc1 to an unsigned integer
and writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If rsrc1 is
deno rmalized, zero is subs tituted before co nversion, and the IF Z f lag in the PCSW is set . I f ufixieee causes an
IEEE exception, such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW
exception f lags ar e sticky : t he flags can be se t as a side- eff ect of any fl oating-point operation but can only be reset by
an explicit writepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is
written. If any other floating-point compute operations update the PCSW at the same time, the net result in each
exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The ufixieeeflags operation computes the exception flags that would result from an individual ufixieee.
The ufixieee operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ufixieee r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ufixieee r35 → r102 r102 ← 3, INX flag set
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ufixieee r40 → r105 no change, since guard i s false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ufixieee r40 → r110 r110 ← 0x0, INV flag set
r45 = 0x7f800000 (+INF)) ufixieee r45 → r112 r112 ← 0xffffffff (232-1), INV flag set
r50 = 0xbfc147ae (-1.51) ufixieee r50 → r115 r115 ← 0, INV flag set
r60 = 0x00400000 (5.877471754e-39) ufixieee r60 → r117 r117 ← 0, IFZ set
r70 = 0xffffffff (QNaN) ufixieee r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ufixieee r80 → r122 r122 ← 0, INV flag set
SEE ALSO
ifixieee ifixrz ufixrz
ufixieee
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-176
IEEE status flags from convert floating-point to
unsigned integer using PCSW rounding mode
SYNTAX
[ IF rguard ] ufixieeeflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((unsigned long) ((float)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 124
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufixieeeflags operation computes the IEEE exceptions that would result from converting the single-
precision IEEE floating-point value in rsrc1 to an unsigned integer, and an integer bit vector representing the
computed exception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according
to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing the
conversion, and the IFZ bit in the result is set.
The ufixieeeflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
cont rol s t he m odif icat ion of t he de st inat ion r egi ster. If the L SB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ufixieeeflags r30 → r100 r100 ← 0
r35 = 0x40247ae1 (2.57) ufixieeeflags r35 → r102 r102 ← 0x02 (INX)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ufixieeeflags r40 → r105 no change, since guard i s false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ufixieeeflags r40 → r110 r110 ← 0x10 (INV)
r45 = 0x7f800000 (+INF)) ufixieeeflags r45 → r112 r112 ← 0x10 (INV)
r50 = 0xbfc147ae (-1.51) ufixieeeflags r50 → r115 r115 ← 0x10 (INV)
r60 = 0x00400000 (5.877471754e-39) ufixieeeflags r60 → r117 r117 ← 0x20 (IFZ)
r70 = 0xffffffff (QNaN) ufixieeeflags r70 → r120 r120 ← 0x10 (INV)
r80 = 0xffbfffff (SNaN) ufixieeeflags r80 → r122 r122 ← 0x10 (INV)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ufixieee ifixieeeflags
ifixrzflags ufixrzflags
ufixieeeflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-177 PRELIMINARY SPECIFICATION
Convert floating-point to unsigned integer with
round toward zero
SYNTAX
[ IF rguard ] ufixrz rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (unsigned long) ((float)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 125
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufixrz op era tion c onver ts the s ingle -p recis ion IE EE floa ting- po int va lue i n rsrc1 to an unsigned integer and
writes t he result into rdest. Rounding toward zero is perfor med; the IEEE rounding mode bits in PCSW are ignored.
This is the preferred rounding mode for ANSI C. If rsrc1 is den or ma lized , ze ro is sub st itute d be fore c onver sion , and
the IFZ flag in the PCSW is set. If ufixrz causes an IEEE exception, such as overflow or underflow, the
corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a
side -ef fect of an y f loati ng -poin t op eratio n but ca n on ly be re set by an explic it writepcsw operation. The update of
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update t h e PCSW at t he sa me time, th e net re sult in ea ch exc eption flag is t h e l og ical OR of all sim ultaneous upd a t es
ORed with the existi ng PCSW value for that exception flag.
The ufixrzflags operation computes the exception flags that would result from an individual ufixrz.
The ufixrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ufixrz r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ufixrz r35 → r102 r102 ← 2, INX flag set
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ufixrz r40 → r105 no ch ange, since guard is false
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ufixrz r40 → r110 r110 ← 0x0, INV flag set
r45 = 0x7f800000 (+INF)) ufixrz r45 → r112 r112 ← 0xffffffff (232-1), INV flag set
r50 = 0xbfc147ae (-1.51) ufixrz r50 → r115 r115 ← 0, INV flag set
r60 = 0x00400000 (5.877471754e-39) ufixrz r60 → r117 r117 ← 0, IFZ s et
r70 = 0xffffffff (QNaN) ufixrz r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ufixrz r80 → r122 r122 ← 0, INV flag set
SEE ALSO
ifixieee ufixieee ifixrz
ufixrz
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-178
IEEE status flags from convert floating-point to
unsi gned i nte ge r wi th round towa rd z ero
SYNTAX
[ IF rguard ] ufixrzflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((unsigned long) ((float)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 126
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufixrzflags opera t io n com pu tes th e I EEE e xc ep ti on s t hat wo uld re su lt from converting the single-precision
IEEE floating-point value in rsrc1 to an unsigned integer, and an integer bit vector representing the computed
except io n flag s is w rit ten i nto r dest. The bit vector stored in rdest ha s the s ame fo rm at as the IEEE exc eption bits in
the PCSW. The excep tion flags in PCSW are lef t unchange d by this operation. Rounding t oward zero is perfor med;
the IEEE rounding mode bits in PCSW are ignored. If an argument is denormalized, zero is substituted before
computing the conversion, and the IFZ bit in the result is set.
The ufixrzflags op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ufixrzflags r30 → r100 r100 ← 0
r35 = 0x40247ae1 (2.57) ufixrzflags r35 → r102 r102 ← 0x02 (INX)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38) IF r10 ufixrzflags r40 → r105 no ch ange, since guard is fa l se
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38) IF r20 ufixrzflags r40 → r110 r110 ← 0x10 (INV)
r45 = 0x7f800000 (+INF)) ufixrzflags r45 → r112 r112 ← 0x10 (INV)
r50 = 0xbfc147ae (-1.51) ufixrzflags r50 → r115 r115 ← 0x10 (INV)
r60 = 0x00400000 (5.877471754e-39) ufixrzflags r60 → r117 r117 ← 0x20 (IFZ)
r70 = 0xffffffff (QNaN) ufixrzflags r70 → r120 r120 ← 0x10 (INV)
r80 = 0xffbfffff (SNaN) ufixrzflags r80 → r122 r122 ← 0x10 (INV)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ufixrz ifixrzflags
ifixieeeflags
ufixieeeflags
ufixrzflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-179 PRELIMINARY SPECIFICATION
Convert un si gn ed int e ger to fl oa ti ng -p oint
SYNTAX
[ IF rguard ] ufloat rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (float) ((unsigned long)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 127
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufloat operation converts the unsigned integer value in rsrc1 to single-precision IEEE floating-point format
and w rit es th e resu lt int o rdest. Ro undin g is acc ord ing to th e IEE E ro undi ng mo de bits i n PC SW . If ufloat causes
an IEEE exception, such as inexact, the corresponding exception flags in the PCSW are set. The PCSW exception
flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw op erat ion. Th e upda te of the PC SW exce pti on fla gs occurs at the s a me tim e a s rdest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneo us upd a tes O R e d wit h th e exis ting P CS W value for that ex ce pt ion f lag.
The ufloatflags operation computes the exception flags that would result from an individual ufloat.
The ufloat operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 3 ufloat r30 → r100 r100 ← 0x40400000 (3.0)
r40 = 0xffffffff (4294967295) ufloat r40 → r105 r105 ← 0x4 f80000 0 (4.294967296 e+ 9), INX flag set
r10 = 0, r50 = 0xfffffffd IF r10 ufloat r50 → r110 no change, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ufloat r50 → r115 r115 ← 0x4 f80000 0 (4.294967296 e+9) , INX flag set
r60 = 0x7fffffff (2147483647) ufloat r60 → r117 r117 ← 0x4f00000 0 (2.147483648 e+9) , INX flag set
r70 = 0x80000000 (2147483648) ufloat r70 → r120 r120 ← 0x4f000000 (2.147483648e+9)
r80 = 0x7ffffff1 (2147483633) ufloat r80 → r122 r122 ← 0x4f00000 0 (2.147483648 e+9) , INX flag set
SEE ALSO
ifloat ifloatrz ufloatrz
ifixieee ufloatflags
ufloat
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-180
IEEE status flags from conver t unsigned integer
to floating-point
SYNTAX
[ IF rguard ] ufloatflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float) ((unsigned long)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 128
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufloatflags operation computes the IEEE exceptions that would result from converting the unsigned
integ er in rsrc1 to a single -precision IE EE floa ting-point value, and an integer bit vector representing the comp uted
except io n flag s is w rit ten i nto r dest. The bit vector stored in rdest ha s the s ame fo rm at as the IEEE exc eption bits in
the PCSW. The excep tion flags in PCSW are left unch anged by this operation. Rounding is accord ing to the IEEE
rounding mode bits in PCSW .
The ufloatflags op era tion op tion al ly t akes a g uar d, spe cifi ed i n rguard. I f a guard is present , its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ufloatflags r30 → r100 r100 ← 0
r40 = 0xffffffff (4294967295) ufloatflags r40 → r105 r105 ← 0x02 (INX)
r10 = 0, r50 = 0xfffffffd IF r10 ufloatflags r50 → r110 no ch ange, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ufloatflags r50 → r115 r115 ← 0x02 (INX)
r60 = 0x7fffffff (2147483647) ufloatflags r60 → r117 r117 ← 0x02 (INX)
r70 = 0x80000000 (2147483648) ufloatflags r70 → r120 r120 ← 0
r80 = 0x7ffffff1 (2147483633) ufloatflags r80 → r122 r122 ← 0x02 (INX)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ufloat ifloatflags
ifloatrzflags
ufloatrzflags
ufloatflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-181 PRELIMINARY SPECIFICATION
Convert unsigned integer to floating-point with
rounding toward zero
SYNTAX
[ IF rguard ] ufloatrz rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (float) ((unsigned long)rsrc1)
}
ATTRIBUTES
Function unit falu
Operation code 119
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufloatrz operation converts the unsigned integer value in rsrc1 to single-precision IEEE floating-point
format and writes t he resu lt into rdest. Ro undi ng is pe r for m ed towa r d zer o; the IE EE ro undi ng mode bit s in PC S W are
igno red . This i s the pre ferred ro undi ng mo de fo r ANSI C. If ufloatrz causes an IEEE exception, such as inexact,
the corresponding exception f lags in the PCSW are set. The PCSW exception fl ags are sticky: the flags can be set as
a side-effect of any floating -p oint operation but can only be reset by an explicit writepcsw operation. The update of
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update t h e PCSW at t he sa me time, th e net re sult in ea ch exc eption flag is t h e l og ical OR of all sim ultaneous upd a t es
ORed with the existi ng PCSW value for that exception flag.
The ufloatrzflags operation computes the exception flags that would result from an individual ufloatrz.
The ufloatrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modifica tion of the destin ation regis ter. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is no t ch an ge d an d the op e ra tio n do es n ot affect t he exception flags i n PC SW.
EXAMPLES
Initial Values Operation Result
r30 = 3 ufloatrz r30 → r100 r100 ← 0x40400000 (3.0)
r40 = 0xffffffff (4294967295) ufloatrz r40 → r105 r105 ← 0x4f7fffff (4.294967040e+9), INX flag set
r10 = 0, r50 = 0xfffffffd IF r10 ufloatrz r50 → r110 no change, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ufloatrz r50 → r115 r115 ← 0x4f7fffff (4.294967040e+9), INX flag set
r60 = 0x7fffffff (2147483647) ufloatrz r60 → r117 r117 ← 0x4effffff (2.147483520e+9), INX flag set
r70 = 0x80000000 (2147483648) ufloatrz r70 → r120 r120 ← 0x4f000000 (2.147483648e+9)
r80 = 0x7ffffff1 (2147483633) ufloatrz r80 → r122 r122 ← 0x4effffff (2.147483520e+9), INX flag set
SEE ALSO
ifloatrz ifloat ufloat
ifixieee ufloatflags
ufloatrz
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-182
IEEE status flags from conver t unsigned integer
to floating-point with rounding toward zero
SYNTAX
[ IF rguard ] ufloatrzflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((float) ((unsigned long)rsrc1))
ATTRIBUTES
Function unit falu
Operation code 120
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 1, 4
DESCRIPTION
The ufloatrzflags operation computes the IEEE exceptions that would result from converting the unsigned
integ er in rsrc1 to a single -precision IE EE floa ting-point value, and an integer bit vector representing the comp uted
except io n flag s is w rit ten i nto r dest. The bit vector stored in rdest ha s the s ame fo rm at as the IEEE exc eption bits in
the PCSW. The ex ception fl ags in PCSW are left unchanged by this ope ration. Rounding is perfor med toward zero;
the IEEE rounding mode bits in PCSW are ignored.
The ufloatrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
cont rol s t he m odif icat ion of t he de st inat ion r egi ster. If the L SB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ufloatrzflags r30 → r100 r100 ← 0
r40 = 0xffffffff (4294967295) ufloatrzflags r40 → r105 r105 ← 0x02 (INX)
r10 = 0, r50 = 0xfffffffd IF r10 ufloatrzflags r50 → r110 no change, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ufloatrzflags r50 → r115 r115 ← 0x02 (INX)
r60 = 0x7fffffff (2147483647) ufloatrzflags r60 → r117 r117 ← 0x02 (INX)
r70 = 0x80000000 (2147483648) ufloatrzflags r70 → r120 r120 ← 0
r80 = 0x7ffffff1 (2147483633) ufloatrzflags r80 → r122 r122 ← 0x02 (INX)
OFZ IFZ INV OVF UNF INX DBZ
0123456731
00
SEE ALSO
ufloatrz ifloatflags
ufloatflags ifloatrzflags
ufloatrzflags
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-183 PRELIMINARY SPECIFICATION
Unsigned compare greater or equal
SYNTAX
[ IF rguard ] ugeq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 >= (unsigned)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 35
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ugeq oper ation set s the dest in ation reg iste r, r dest, to 1 if the fir st argum ent, r src1, is greater than or equal to
the secon d argument, rsrc2; ot he r wis e, rdest is set to 0. The arguments are treated as unsigned integers.
The ugeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ugeq r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ugeq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 ugeq r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 ugeq r70 r40 → r100 r100 ← 1
r70 = 0x80000000 ugeq r70 r70 → r110 r110 ← 1
SEE ALSO
igeq ugeqi
ugeq
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-184
Unsigned comp are greater or equal with
immediate
SYNTAX
[ IF rguard ] ugeqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 >= (unsigned)n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 36
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ugeqi operation sets the de st ina t i o n r egi ster, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the opcode modifier, n; othe r w is e, rdest is se t to 0. The argum en t s are t reated a s un signed integers .
The ugeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ugeqi(2) r30 → r80 r80 ← 1
r30 = 3 ugeqi(3) r30 → r90 r90 ← 1
r30 = 3 ugeqi(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ugeqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ugeqi(63) r40 → r100 r100 ← 1
r60 = 0x80000000 ugeqi(127) r60 → r120 r120 ← 1
SEE ALSO
ugeq igeqi
ugeqi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-185 PRELIMINARY SPECIFICATION
Un sig ned compa re gr eater
SYNTAX
[ IF rguard ] ugtr rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 > (unsigned)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 33
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ugtr operation sets the destination register, rdest, to 1 if the first ar gument , r src1, is grea ter tha n the seco nd
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.
The ugtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ugtr r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ugtr r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 ugtr r50 r60 → r90 r90 ← 1
r70 = 0x80000000, r40 = 4 ugtr r70 r40 → r100 r100 ← 1
r70 = 0x80000000 ugtr r70 r70 → r110 r110 ← 0
SEE ALSO
igtr ugtri
ugtr
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-186
Un sign ed compare gr eate r with immediate
SYNTAX
[ IF rguard ] ugtri(n) rsrc1 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 > (unsigned)n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 34
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ugeqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is grea ter than the op code
modifier, n; other wis e, rdest is set to 0 . The argument s are trea te d as un signe d i ntegers.
The ugeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ugtri(2) r30 → r80 r80 ← 1
r30 = 3 ugtri(3) r30 → r90 r90 ← 0
r30 = 3 ugtri(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ugtri(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ugtri(63) r40 → r100 r100 ← 1
r60 = 0x80000000 ugtri(127) r60 → r120 r120 ← 1
SEE ALSO
igtri ugtr
ugtri
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-187 PRELIMINARY SPECIFICATION
Unsigned immediate
SYNTAX
uimm(n) → rdest
FUNCTION
rdest ← n
ATTRIBUTES
Function unit const
Operation code 191
Nu mber of operands 0
Modif ier 32 bits
Modifier range 0..0xffffffff
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The uimm operation writes the unsigned 32-bit opcode modifier n into rdest. Note: this oper atio n is no t guarded.
EXAMPLES
Initial Values Operation Result
uimm(2) → r10 r10 ← 2
uimm(0x100) → r20 r20 ← 0x100
uimm(0xfffc0000) → r30 r30 ← 0xfffc0000
SEE ALSO
iimm
uimm
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-188
Un sign ed 16-bit load
pseudo-op for uld16d(0)
SYNTAX
[ IF rguard ] uld16 rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[rsrc1 + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 197
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld16 operation is a pseudo operation transformed by the scheduler into an uld16d(0) with the same
argument. (Note: pseudo operat ions cannot be used in assembly source files.)
The uld16 operation loads the 16-bit memory value from the address contained in rsrc1, zero extends it to 32 bits,
and w r ites th e re sult in rdest. If the memor y address contained in rsrc1 is not a multiple of 2, the resul t of uld16 is
undefine d but no e xce ption will be rai sed. This load operation is perfo rm ed as little-e ndia n or big -endia n depending on
the current setting of the bytesex bit in the PCSW.
The result of an access by uld16 to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The uld16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and uld16 has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd00] = 0x22,
[0xd01] = 0x11 uld16 r10 → r60 r60 ← 0x00002211
r30 = 0, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33 IF r30 uld16 r20 → r70 no ch ange, since guard is fa l se
r40 = 1, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33 IF r40 uld16 r20 → r80 r80 ← 0x00008433
r50 = 0xd01 uld16 r50 → r90 r90 undefined (0xd01 is not a m ultiple of 2)
SEE ALSO
uld16d ild16 ild16d uld16r
ild16r uld16x ild16x
uld16
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-189 PRELIMINARY SPECIFICATION
Unsigned 16-bit load with displacement
SYNTAX
[ IF rguard ] uld16d(d) rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[rsrc1 + d + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + d + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 197
Nu mber of operands 1
Modifier 7 bits
Modifier ran ge –128..126 by 2
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld16d operation loads the 16-bit memory value from the address computed by rsrc1 + d, zero ex tends it to
32 bits, and writes the result in rdest. The d value is an opcode modifier, must be in the ra nge –128 and 126 inclusive,
and must be a mul tiple of 2 . If th e memory address computed by rsrc1 + d is not a multiple of 2, the result of uld16d
is u nd efined but n o exce ption w ill b e r ai se d. Th is l oa d op er a tion is p erfor m e d as l ittle-endi an o r b i g -endia n d epen din g
on t h e cu r rent sett i ng o f the byt esex bit in the PCSW.
The result of an access by uld16d to the MMIO address aper ture is undefined; access to the MMIO ap er ture is
defined only for 32- bit loads and sto res.
The uld16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and uld16d ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd02] = 0x22,
[0xd03] = 0x11 uld16d(2) r10 → r60 r60 ← 0x00002211
r30 = 0, r20 = 0xd04, [0xd00] = 0x84,
[0xd01] = 0x33 IF r30 uld16d(-4) r20 → r70 no ch ange, since guard is false
r40 = 1, r20 = 0xd04, [0xd00] = 0x84,
[0xd01] = 0x33 IF r40 uld16d(-4) r20 → r80 r80 ← 0x00008433
r50 = 0xd01 uld16d(-4) r50 → r90 r90 undefined (0xd01 +(–4) is not a multiple
of 2)
SEE ALSO
uld16 ild16 ild16d uld16r
ild16r uld16x ild16x
uld16d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-190
Un sign ed 16-bit load with index
SYNTAX
[ IF rguard ] uld16r rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[rsrc1 + rsrc2 + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + rsrc2 + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 198
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld16r o pe rat i on lo ads the 16 - b it mem ory value f r om th e ad dr e s s c om puted by r src1 + rsrc2, ze ro extend s it
to 32 bits, and w rites the result in rdest. If the memor y address computed by rsrc1 + rsrc2 is not a multiple of 2, the
result of uld16r is undefined but no exception will be raised. This load operation is performed as little-endian or big-
endian dependin g on the current setting of the bytesex bit in the PCSW.
The result of an access by uld16r to the MMIO address aper ture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The uld16r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
th e data c ach e status bits are updated if the ad dres sed lo c a tions are cach eable. if t he L S B of rguard is 0, rdest is not
changed and uld16r ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r20 = 2, [0xd02] = 0x22,
[0xd03] = 0x11 uld16r r10 r20 → r80 r80 ← 0x00002211
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33 IF r50 uld16r r40 r30 → r90 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33 IF r60 uld16r r40 r30 → r100 r100 ← 0x00008433
r70 = 0xd01, r30 = 0xfffffffc uld16r r70 r30 → r110 r110 undefined (0xd01 +(–4) is not a multiple
of 2)
SEE ALSO
uld16 ild16 uld16d ild16d
ild16r uld16x ild16x
uld16r
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-191 PRELIMINARY SPECIFICATION
Unsigned 16-bit load with scaled index
SYNTAX
[ IF rguard ] uld16x rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
temp<7:0> ← mem[rsrc1 + (2 × rsrc2) + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + (2 × rsrc2) + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit dmem
Operation code 199
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld16x operation loads the 16-bit memor y value from the address computed by rsrc1 + 2×rsrc2, zero extends
it to 32 bits, and writes the result in rdest. If th e memor y add ress com pute d by rsrc1 + 2×rsrc2 is not a mu lti ple of 2 ,
th e res ul t of uld16x i s u nd efi ned but n o exce ption w il l be rais ed. This lo ad op er at io n is p er for med a s li t tl e -endia n or
big- e nd ia n de pend ing on th e cur r en t set tin g of the byte s e x bit in t he PCSW .
The result of an access by uld16x to the MMIO address aper ture is undefined; access to the MMIO ap er ture is
defined only for 32- bit loads and sto res.
The uld16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
th e data c ache stat u s bits ar e update d if t he addre sse d locations are ca cheable. if t he L SB of rguard is 0, rdest is not
changed and uld16x ha s no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r30 = 1, [0xd02] = 0x22,
[0xd03] = 0x11 uld16x r10 r30 → r100 r100 ← 0x00002211
r50 = 0, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33 IF r50 uld16x r40 r20 → r80 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33 IF r60 uld16x r40 r20 → r90 r90 ← 0x00008433
r70 = 0xd01, r30 = 1 uld16x r70 r30 → r110 r110 undef ined (0xd01 + 2×1 is not a multi-
ple of 2)
SEE ALSO
uld16 ild16 uld16d ild16d
uld16r ild16r ild16x
uld16x
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-192
Un sign ed 8-bit load
pseudo-op for uld8d(0)
SYNTAX
[ IF rguard ] uld8 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(mem[rsrc1])
ATTRIBUTES
Function unit dmem
Operation code 8
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld8 operation is a pseudo operation transformed by the scheduler into an uld8d(0) with the same
argument. (Note: pseudo operat ions cannot be used in assembly source files.)
The uld8 operation loads the 8-bit memory value from the address contained in rsrc1, zero extends it to 32 bits,
and w rites the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a single byte
is loaded.
The result of an access by uld8 to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The uld8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is not
changed and uld8 has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd00] = 0x22 uld8 r10 → r60 r60 ← 0x00000022
r30 = 0, r20 = 0xd04, [0xd04] = 0x84 IF r30 uld8 r20 → r70 no change, since guard i s false
r40 = 1, r20 = 0xd04, [0xd04] = 0x84 IF r40 uld8 r20 → r80 r80 ← 0x00000084
r50 = 0xd01, [0xd01] = 0x33 uld8 r50 → r90 r90 ← 0x00000033
SEE ALSO
ild8 uld8d ild8d uld8r
ild8r
uld8
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-193 PRELIMINARY SPECIFICATION
Unsigned 8-bit load with displacement
SYNTAX
[ IF rguard ] uld8d(d) rsrc1 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(mem[rsrc1 + d])
ATTRIBUTES
Function unit dmem
Operation code 8
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge –64..63
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld8d operation loads the 8-bit me mor y value from the address computed by r src1 + d, zero extend s it to 32
bit s, and wr ites t he resu lt in rdest. The d value is an opcode modifier in the range –64 to 63 inclusive. This operation
does not depe nd on the b yte se x bit in t he P CS W since onl y a single by te is loaded.
The result of an access by uld8d to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The uld8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is no t
changed and uld8d has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, [0xd02] = 0x22 uld8d(2) r10 → r60 r60 ← 0x000022
r30 = 0, r20 = 0xd04, [0xd00] = 0x84 IF r30 uld8d(-4) r20 → r70 no ch ange, since guard is false
r40 = 1, r20 = 0xd04, [0xd00] = 0x84 IF r40 uld8d(-4) r20 → r80 r80 ← 0x00000084
r50 = 0xd05, [0xd01] = 0x33 uld8d(-4) r50 → r90 r90 ← 0x00000033
SEE ALSO
uld8 ild8 ild8d uld8r
ild8r
uld8d
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-194
Un sign ed 8-bit load with index
SYNTAX
[ IF rguard ] uld8r rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(mem[rsrc1 + rsrc2])
ATTRIBUTES
Function unit dmem
Operation code 194
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 4, 5
DESCRIPTION
The uld8r operation loads the 8-bit memory value from the address computed by rsrc1 + rsrc2, zero e xtends it to
32 bit s, and writes th e result in rdest. This op eration does not de pend on the bytesex bit i n the PCSW since only a
si ng le byte is load ed.
The result of an access by uld8r to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32- bit loads and sto res.
The uld8r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modific ation of the destination register and the occur rence of side effe cts. If t he LSB of rguard is 1, rdest is written and
the data cache status bit s are updated if the addressed locat ion is cacheable. if the LSB of rguard is 0, r dest is not
changed and uld8r has no side effects whatever.
EXAMPLES
Initial Values Operation Result
r10 = 0xd00, r20 = 2, [0xd02] = 0x22 uld8r r10 r20 → r80 r80 ← 0x00000022
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84 IF r50 uld8r r40 r30 → r90 no ch ange, since guard is false
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84 IF r60 uld8r r40 r30 → r100 r100 ← 0x00000084
r70 = 0xd05, r30 = 0xfffffffc,
[0xd01] = 0x33 uld8r r70 r30 → r110 r110 ← 0x00000033
SEE ALSO
uld8 ild8 uld8d ild8d
ild8r
uld8r
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-195 PRELIMINARY SPECIFICATION
Un sig ned co mp are less or equ al
pseud o-op for ug eq
SYNTAX
[ IF rguard ] uleq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 <= (unsigned)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 35
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The uleq operation is a pseudo operation transformed by the scheduler into an ugeq with the arguments
exchanged (uleq’s rsrc1 is ugeq’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The uleq operation sets the destination register, r dest, to 1 if the first argument, rsrc1, is less than or equa l to the
s econd argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned in tegers.
The uleq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 uleq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 uleq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 uleq r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 uleq r70 r40 → r100 r100 ← 0
r70 = 0x80000000 uleq r70 r70 → r110 r110 ← 1
SEE ALSO
ileq uleqi
uleq
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-196
Unsigned compare less or equal with imm ediate
SYNTAX
[ IF rguard ] uleqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 <= (unsigned)n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 43
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The uleqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to the
opcode modifier, n; otherwise, r dest is set to 0. The arguments are treated as unsigned integers.
The uleqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 uleqi(2) r30 → r80 r80 ← 0
r30 = 3 uleqi(3) r30 → r90 r90 ← 1
r30 = 3 uleqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 uleqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 uleqi(63) r40 → r100 r100 ← 0
r60 = 0x80000000 uleqi(127) r60 → r120 r120 ← 0
SEE ALSO
uleq ileqi
uleqi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-197 PRELIMINARY SPECIFICATION
Un sign ed compare less
pseudo-op fo r ugtr
SYNTAX
[ IF rguard ] ules rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 < (unsigned)rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 33
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ules operation is a pseudo operation transformed by the scheduler into an ugtr with the arguments
exchanged (ules’s rsrc1 is ugtr’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
so urce files. )
The ules operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the second
arg um e nt, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.
The ules operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ules r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ules r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x100 IF r20 ules r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 ules r70 r40 → r100 r100 ← 0
r70 = 0x80000000 ules r70 r70 → r110 r110 ← 0
SEE ALSO
iles ugtr
ules
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-198
Unsigned compare less with im mediate
SYNTAX
[ IF rguard ] ulesi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 < (unsigned)n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 41
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The ulesi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the opcode
modifier, n; other wis e, rdest is set to 0 . The argument s are trea te d as un signe d i ntegers.
The ulesi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ulesi(2) r30 → r80 r80 ← 0
r30 = 3 ulesi(3) r30 → r90 r90 ← 0
r30 = 3 ulesi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ulesi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 ulesi(63) r40 → r100 r100 ← 0
r60 = 0x80000000 ulesi(127) r60 → r120 r120 ← 0
SEE ALSO
ules ilesi
ulesi
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-199 PRELIMINARY SPECIFICATION
Un sign ed sum of ab solute valu es
of signed 8-b it diff er en ces
SYNTAX
[ IF rguard ] ume8ii rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← abs_val(sign_ext8to32(rsrc1<31:24>) –sign_ext8to32(rsrc2<31:24>) ) +
abs_val(sign_ext8to32(rsrc1<23:16>) –sign_ext8to32(rsrc2< 23:16>) ) +
abs_val(sign_ext8to32(rsrc1<15:8>) –sign_ext8to32(rsrc2<15:8>)) +
abs_val(sign_ext8to32(rsrc1<7:0>) –sign_ext8to32(rsrc2<7:0>))
ATTRIBUTES
Function unit dspalu
Operation code 64
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the ume8ii operation computes four separate differences of the four pairs of corresponding
signed 8-bit bytes of rsrc1 and rsrc2; the absolute values of the four differences are summed, and the sum is written to
rdest. All computations are performed without loss of precision.
The ume8ii operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Re sult
r80 = 0x0a14f6f6, r30 = 0x1414ecf6 ume8ii r80 r30 → r100 r100 ← 0x14
r10 = 0, r80 = 0x0a14f6f6, r30 = 0x1414ecf6 IF r10 ume8ii r80 r30 → r70 no ch ange, since guard is false
r20 = 1, r90 = 0x64649c9c, r40 = 0x649c649c IF r20 ume8ii r90 r40 → r110 r110 ← 0x190
r40 = 0x649c649c, r90 = 0x64649c9c ume8ii r40 r90 → r120 r120 ← 0x190
r50 = 0x80808080, r60 = 0x7f7f7f7f ume8ii r50 r60 → r125 r125 ← 0x3fc
01531
rsrc1 01531
rsrc2
031
rdest
−
−
+
−
−
| |
| |
| |
| |
23 7 23 7
signed signed signed signed signed signed signed signed
unsigned
SEE ALSO
ume8uu
ume8ii
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-200
Sum of absolute value s of unsigned 8-bit
differences
SYNTAX
[ IF rguard ] ume8uu rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
rdest ← abs_val(zero_ext8to32(rsrc1<31:24>) –zero_ext8to32(rsrc2<31:24>)) +
abs_val(zero_ext8to32(rsrc1<23:16>) –zero_ext8to32(rsrc2<23:16>)) +
abs_val(zero_ext8to32(rsrc1<15:8>) –zero_ext8to32(rsrc2<15:8>) ) +
abs_val(zero_ext8to32(rsrc1<7:0>) –zero_ext8to32(rsrc2<7:0>))
ATTRIBUTES
Function unit dspalu
Operation code 26
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
As shown below, the ume8uu operation computes four separate differences of the four pairs of corresponding
unsigned 8-bit bytes of rsrc1 and rsrc2. The absolute values of the four differences are summed and the result is
wri tte n to rdest. All computations are performed without loss of precision.
The ume8uu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is writt e n; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r80 = 0x0a14f6f6, r30 = 0x1414ecf6 ume8uu r80 r30 → r100 r100 ← 0x14
r10 = 0, r80 = 0x0a14f6f6, r30 = 0x1414ecf6 IF r10 ume8uu r80 r30 → r70 no change, since guard is false
r20 = 1, r90 = 0x64649c9c, r40 = 0x649c649c IF r20 ume8uu r90 r40 → r110 r110 ← 0x70
r40 = 0x649c649c, r90 = 0x64649c9c ume8uu r40 r90 → r120 r120 ← 0x70
r50 = 0x80808080, r60 = 0x7f7f7f7f ume8uu r50 r60 → r125 r125 ← 0x4
01531
rsrc1 01531
rsrc2
031
rdest
−
−
+
−
−
| |
| |
| |
| |
23 7 23 7
unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned
unsigned
SEE ALSO
ume8ii
ume8uu
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-201 PRELIMINARY SPECIFICATION
umin Min im u m of unsign ed values
pseudo-op fo r ucli pu
SYNTAX
[ IF rguard ] umin rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 > rsrc2 then
rdest ← rsrc2
else
rdest ← rsrc1
}
ATTRIBUTES
Function unit dspalu
Operation code 76
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 2
Issue slots 1, 3
DESCRIPTION
The umin operation returns the minimum value of rsrc1 and r src2. The arguments rsrc1 and rsrc2 are considered
unsigned i nt e ger s.
The umin operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x80, r40 = 0x7f umin r30 r40 → r50 r50 ← 0x7f
r10 = 0, r60 = 0x12345678,
r70 = 0xabc IF r10 umin r60 r70 → r80 no change , since guard is false
r20 = 1, r60 = 0x12345678,
r70 = 0xabc IF r20 umin r60 r70 → r90 r90 ← 0xabc
r100 = 0x80000000, r110 = 0x3fffff umin r100 r110 → r120 r120 ← 0x3fffff
SEE ALSO
iclipi uclipi imin imax
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-202
Un sign ed multiply
SYNTAX
[ IF rguard ] umul rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
temp ← zero_ext32to64(rsrc1) × zero_ext32to64(rsrc2)
rdest ← temp<31:0>
ATTRIBUTES
Function unit ifmul
Operation code 138
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below , the umul opera t io n com pute s th e prod uc t rsrc1×rsrc2 and writ e s th e lea st - sign if i ca nt 32 b its of th e
full 64 -bit product into rdest. T he ope rands ar e c onsi dered unsi gned inte ge rs. N o overf low or unde rfl ow d etec tion is
performed.
The umul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 umul r60 r60 → r80 r80 ← 0x10000
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 umul r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x100, r30 = 0xf11 IF r20 umul r60 r30 → r90 r90 ← 0xf1100
r70 = 0x100, r40 = 0xffffff9c umul r70 r40 → r100 r100 ← 0xffff9c00
031
rsrc1 031
rsrc2
031
rdest
×
063 31
64-bit result
unsigned unsigned
unsigned
unsigned
SEE ALSO
imul imulm umulm dspimul
dspumul dspidualmul
quadumulmsb fmul
umul
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-203 PRELIMINARY SPECIFICATION
Unsigned multiply, return most-significant 32
bits
SYNTAX
[ IF rguard ] umulm rsrc1 rsrc2 → rdest
FUNCTION
if rguard then
temp ← zero_ext32to64(rsrc1) × zero_ext32to64(rsrc2)
rdest ← temp<63:32>
ATTRIBUTES
Function unit ifmul
Operation code 140
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 3
Issue slots 2, 3
DESCRIPTION
As shown below, the umulm operat i o n co mputes the p rodu c t rsrc1×rsrc2 an d wr ites t he m ost-s igni fica nt 3 2 bits o f
the 64-bit product into rdest. Th e op er an ds a re cons id ered un s ig ne d int eger s.
The umulm operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x10000 umulm r60 r60 → r80 r80 ← 0x00000001
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 umulm r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r60 = 0x10001000,
r30 = 0xf1100000 IF r20 umulm r60 r30 → r90 r90 ← 0xf110f11
r70 = 0xffffff00, r40 = 0x100 umulm r70 r40 → r100 r100 ← 0xff
031
rsrc1 031
rsrc2
031
rdest
×
063 31
64-bit result
unsigned unsigned
unsigned
unsigned
SEE ALSO
umulm dspimul dspumul
dspidualmul quadumulmsb
fmul
umulm
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-204
Un sign ed compa re not eq ual
pseudo-op for ineq
SYNTAX
[ IF rguard ] uneq rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
if rsrc1 != rsrc2 then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 39
Nu mber of operands 2
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The uneq operation is a pseudo operation transformed by the scheduler into an ineq. (Not e: p seu do op erat ions
ca nn ot b e us ed in assembl y so u r c e f iles .)
The uneq operation sets the destination register, rdest, to 1 if the two arguments, r src1 and rsrc2, are not equal;
otherwise, rdest is set to 0.
The uneq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 uneq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x1000, r30 = 3 IF r10 uneq r60 r30 → r50 no ch ange, since guard is false
r20 = 1, r50 = 0x1000, r60 = 0x1000 IF r20 uneq r50 r60 → r90 r90 ← 0
r70 = 0x80000000, r40 = 4 uneq r70 r40 → r100 r100 ← 1
r70 = 0x80000000 uneq r70 r70 → r110 r110 ← 0
SEE ALSO
ineq igtr uneqi
uneq
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-205 PRELIMINARY SPECIFICATION
Unsigned compare not equal with immediate
SYNTAX
[ IF rguard ] uneqi(n) rsrc1 → rdest
FUNCTION
if rguard then {
if (unsigned)rsrc1 != (unsigned)n then
rdest ← 1
else
rdest ← 0
}
ATTRIBUTES
Function unit alu
Operation code 40
Nu mber of operands 1
Modif ier 7 bits
Modifier ran ge 0..127
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The uneqi operat ion se ts th e des tinatio n r eg is ter, rdest, to 1 if the fir st argu ment, rsrc1, is not equ a l to t h e op co de
modifier, n; other wis e, rdest is set to 0 . The argument s are trea te d as un signe d i ntegers.
The uneqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 uneqi(2) r30 → r80 r80 ← 1
r30 = 3 uneqi(3) r30 → r90 r90 ← 0
r30 = 3 uneqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 uneqi(63) r40 → r50 no change, since guard is false
r20 = 1, r40 = 0x100 IF r20 uneqi(63) r40 → r100 r100 ← 1
r60 = 0x80000000 uneqi(127) r60 → r120 r120 ← 1
SEE ALSO
uneq ineqi ueqli
uneqi
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-206
Write destination program counter
SYNTAX
[ IF rguard ] writedpc rsrc1
FUNCTION
if rguard then {
DPC ← rsrc1
}
ATTRIBUTES
Function unit fcomp
Operation code 160
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The writedpc copies the value of rsrc1 to t h e DP C (D e s tin ation Pr o gram C ou nte r ) pr oc es s or regi s t er. Wheneve r
a hardware update (during an interruptible jump) and a software update (through a writedpc) coincide, the
software update takes precedence.
Interruptible jumps write their target address to the DPC. The value of DPC is intended to be used by an exception-
hand ling routine as a ju mp address to resume execution of the program that was running b efo re the exception was
taken.
The writedpc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of DPC. If the LS B of rguard is 1, DPC is written; otherwise, DPC is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xbeebee writedpc r30 DPC ← 0xbeebee
r20 = 0, r31 = 0xabba IF r20 writedpc r31 no change, since guard is false
r21 = 1, r31 = 0xabba IF r21 writedpc r31 DPC ← 0xabba
SEE ALSO
readdpc writespc ijmpf
ijmpi ijmpt
writedpc
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-207 PRELIMINARY SPECIFICATION
Write program control and status word
SYNTAX
[ IF rguard ] writepcsw rsrc1 rsrc2
FUNCTION
if rguard then {
PCSW ← (PCSW & ~rsrc2) | (rsrc1 & rsrc2)
}
ATTRIBUTES
Function unit fcomp
Operation code 161
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The writepcsw copies the value of rsrc1 to the PCSW (Program Control and Status Word) processor register
using rsrc2 as a mask. A bit in PCSW is affected by writepcsw only if the correspondin g bit i n r s rc2 is set to 1 ; th e
value of any bit in PCSW with a corresponding 0-bit in rsrc2 will not be changed by writepcsw. Whenever a
hardware update (e.g., when a floating-point exception is raised) and a software update (through a writepcsw)
c oinci d e , the PCSW bi t s cu rre ntly b e i ng updated b y har dw ar e wil l ref le ct the hardware-determined value while the bits
not being affected by hardware will reflect the value in the writepcsw operand. The layout of PCSW is shown
below. The programmer should take care not to alter UNDEF fields in the PCSW .
Fields in t he PCSW have two chief purposes: to co ntrol aspects of proc essor ope ration and to record events that
occur during program execution. Thus, writepcsw can be used to effect changes in some aspects of processor
operation and to clear fields that record events; this operation can also be used to restore state before resuming an
idled task in a multi-tasking environment. Note: The latency of writepcsw is 1, i.e. the PCSW reflects the new value in
the next cycle. But it takes additional 3 cycles for updates to the exception flags and exception enable bits to take
effect in the hardware. Therefore 3 delay slot s / nops shall be inser ted between writepcsw and the next interruptible
jump, if exception flags or enable bits are changed. This guarantees that the new state is recognized in the interrup t
logic du r i ng execut ion of the iju mp.
The writepcsw o per ati on op t i on al ly ta kes a g ua r d, sp ec ified i n rguard. If a guar d is presen t , it s LSB contr ols t he
mod ifica tio n of PCSW. If the LSB of rguard i s 1, P CS W is writ ten ; ot h erw i s e, PC S W is un ch an ge d.
EXAMPLES
Initial Values Operation Result
r30 = 0x100, r40 = 0x180 writepcsw r30 r40 PCSW.IEEE MODE = to positive infinity
r20 = 0, r50 = 0x0, r60 = 0x400 IF r20 writepcsw r50 r60 no change, since guard is f alse
r21 = 1, r50 = 0x0, r60 = 0x400 IF r21 writepcsw r50 r60 PCSW.IEN = 0 (disable interrupts)
r70 = 0x80110000, r80 = 0xffff0000 writepcsw r70 r80 enable trap on MSE, INV and DBZ exclusi vely
MSE CS IEN BSX I EEE MODE OFZ IFZ INV OVF UNF INX DBZ
01234567891011121415
Misaligned store exce p tion
Count stalls (1 ⇒ Yes)
FP exception trap-enable bits
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW<31:16>
PCSW<15:0> UNDEF
Misaligned store
exceptio n tr ap enable T rap on first exit
FP exceptions
TRP
MSE TFE TRP
OFZ TRP
IFZ TRP
INV TRP
OVF TRP
UNF TRP
INX TRP
DBZ
1617181920212223252627283031
UNDEF UNDEFINED
13
WBE RSE
Write back error
Reserved exception
TRP
WBE TRP
RSE
Write back error trap enable
Reserved exception
trap enabl e
29
SEE ALSO
readpcsw fadd faddflags
ijmpf cycles hicycles
writepcsw
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-208
Write sour ce progr am counter
SYNTAX
[ IF rguard ] writespc rsrc1
FUNCTION
if rguard then
SPC ← rsrc1
ATTRIBUTES
Function unit fcomp
Operation code 159
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 3
DESCRIPTION
The writespc copies the value of rsrc1 to the SPC (Source Program Counter) processor register. Whenever a
hardware update (during an interruptible jump) and a software update (through a writespc) coincide, the software
update takes p r ec edenc e.
An interr u ptible jum p that i s not i nterrupted ( n o N MI, I N T, or EX C event was p endi ng w hen t h e j ump wa s executed )
wr ites its target address to SPC. T he va lue of S PC i s intend ed to allow an exception-handli ng routi ne to determin e the
start address of the block of scheduled code (called a decision tree) that was executing before the exception was
taken.
The writespc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB co ntrol s the
modification of SPC. If the LSB of rguard is 1, SPC is wri tten; otherwise, SP C is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xbeebee writespc r30 SPC ← 0xbeebee
r20 = 0, r31 = 0xabba IF r20 writespc r31 no change, since guard is false
r21 = 1, r31 = 0xabba IF r21 writespc r31 SPC ← 0xabba
SEE ALSO
readspc writedpc ijmpf
ijmpi ijmpt
writespc
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-209 PRELIMINARY SPECIFICATION
Zer o e x ten d 1 6 bits
pseu do-op for pack16 lsb
SYNTAX
[ IF rguard ] zex16 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← zero_ext16to32(rsrc1<15:0>)
ATTRIBUTES
Function unit alu
Operation code 53
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The zex16 operation is a pseudo operation transformed by the scheduler into a pack16lsb wit h 0 as the first
argument and rsrc1 as t he s ec on d. (N ot e: ps eudo ope r ati on s cann ot be us ed in as sembl y source files .)
As shown below, the zex16 o peration zero extend s t he leas t-significant 16-b it hal fword of t he argument, rsrc1, to
32 bits and writes the result in rdest.
The zex16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; othe r wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 zex16 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 zex16 r40 → r70 no change, since guard is false
r20 = 1, r40 = 0xff0fff91 IF r20 zex16 r40 → r100 r100 ← 0x0000ff91
r50 = 0x00000091 zex16 r50 → r110 r110 ← 0x00000091
01531
rsrc1
031
rdest 15
0000000000000000
unsigned
unsigned
SEE ALSO
sex16 sex8 zex8
zex16
Philips Semiconductors PNX1300/01 / 02/11 DSPCPU Operations
PRELIMINARY SPECIFICATION A-210
Zero extend 8 bits
pseudo-op for ubytesel
SYNTAX
[ IF rguard ] zex8 rsrc1 → rdest
FUNCTION
if rguard then
rdest ← zero_ext8to32(rsrc1<7:0>)
ATTRIBUTES
Function unit alu
Operation code 55
Nu mber of operands 1
Modifier No
Modifier ran ge —
Latency 1
Issue slots 1, 2, 3, 4, 5
DESCRIPTION
The zex8 operation is a pseudo operation transformed by the scheduler into a ubytesel with r0 (always contains
0) as the first argument and rsrc1 as t he second. (N ote: pseudo operations cannot be u sed in ass embly source fi les . )
As shown be low, th e zex8 operation zero extends the least-significant byte of the argument, rsrc1, to 32 bits and
writes the result in rdest.
The zex8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is wri t te n; ot her wis e, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 zex8 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 zex8 r40 → r70 no change, since guard is false
r20 = 1, r40 = 0xff0fff91 IF r20 zex8 r40 → r100 r100 ← 0x00000091
r50 = 0x00000091 zex8 r50 → r110 r110 ← 0x00000091
031
rsrc1
031
rdest 0
7
7
00000000000000000000000
unsigned
unsigned
SEE ALSO
ubytesel sex16 sex8 zex16
zex8
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-211 PRELIMINARY SPECIFICATION
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
A-212 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION B-1
MMIO Register Summary Chapter B
by Gert Slavenburg, an d Sell iah Rathnam
B.1 MMIO REGISTERS
The following table lists all the MMIO registers implemented in PNX1300/01/02/11. The registers are grouped accord-
ing to the unit to which they belong. For compatibility with future devices, any undefined MMIO bits should be ignored
when read, and writt en as zeroes.
MMIO Reg ist er Nam e Offset
(in hex)
Accessibility
Description
DSPCPU External
PCI
Initiators
DSPCPU Re gisters
DRAM_BAS E 10 0000 R/W R/W Start of DRAM address aperture
DRAM_LIMIT 10 0004 R/W R/W End of DRAM address aperture
MMIO_BASE 10 0400 R/W R/W Start of 2-MB MMIO-regi ster address aperture
EXCVEC 10 0800 R/W R/W In terrupt vector (handl er star t addres s) for ex ception s
ISETTING0 10 0810 R/W R/ W Interrupt mode & priority settings for sources 0-7
ISETTING1 10 0814 R/W R/ W Interrupt mode & priority settings for sourc es 8-15
ISETTING2 10 0818 R/W R/ W Interrupt mode & priority settings for sourc es 16-23
ISETT ING3 10 081c R/W R/W Interrupt mode & prio r ity settings for sou r ces 24- 31
IP ENDING 10 0820 R/W R/W Interrupt-pending status bit for all 32 sources
ICLEAR 10 0824 R/W R/W Interrupt-clear bit for all 32 sources
IMASK 10 0828 R/W R/W In terrupt-mask bit fo r all 32 sources
INTVEC0 10 0880 R /W R/W Interru pt vector (handler star t addr ess) for source 0
INTVEC1 10 0884 R /W R/W Interru pt vector (handler star t addr ess) for source 1
INTVEC2 10 0888 R /W R/W Interru pt vector (handler star t addr ess) for source 2
INTV EC3 10 088c R /W R/W Inte rrupt vector (h andler start addr ess) for source 3
INTVEC4 10 0890 R /W R/W Interru pt vector (handler star t addr ess) for source 4
INTVEC5 10 0894 R /W R/W Interru pt vector (handler star t addr ess) for source 5
INTVEC6 10 0898 R /W R/W Interru pt vector (handler star t addr ess) for source 6
INTV EC7 10 089c R /W R/W Inte rrupt vector (h andler start addr ess) for source 7
INTVEC8 10 08a0 R /W R/W Interru pt vector (handler star t addr ess) for source 8
INTVEC9 10 08a4 R /W R/W Interru pt vector (handler star t addr ess) for source 9
INTVEC10 10 08a8 R/W R/W Interrupt vector (handl er star t addres s) for source 10
INTV EC11 10 08ac R/W R/W Interrupt vector (handler start addr ess) for source 11
INTVEC12 10 08b0 R/W R/W Interrupt vector (handl er star t addres s) for source 12
INTVEC13 10 08b4 R/W R/W Interrupt vector (handl er star t addres s) for source 13
INTVEC14 10 08b8 R/W R/W Interrupt vector (handl er star t addres s) for source 14
INTV EC15 10 08bc R/W R/W Interrupt vector (handler start addr ess) for source 15
INTV EC16 10 08c0 R/W R /W Interrupt vector (h andler start address) for source 16
INTV EC17 10 08c4 R/W R /W Interrupt vector (h andler start address) for source 17
INTV EC18 10 08c8 R/W R /W Interrupt vector (h andler start address) for source 18
INTV EC19 10 08cc R/W R/W Inte rr upt vector (handl er start addr ess) for source 19
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
B-2 PRELIMINARY SPECIFICATION
INTVEC20 10 08d0 R/W R/W Interrupt vector (handl er star t addres s) for source 20
INTVEC21 10 08d4 R/W R/W Interrupt vector (handl er star t addres s) for source 21
INTVEC22 10 08d8 R/W R/W Interrupt vector (handl er star t addres s) for source 22
INTV EC23 10 08dc R/W R/W Interrupt vector (handler start addr ess) for source 23
INTVEC24 10 08e0 R/W R/W Interrupt vector (handl er star t addres s) for source 24
INTVEC25 10 08e4 R/W R/W Interrupt vector (handl er star t addres s) for source 25
INTVEC26 10 08e8 R/W R/W Interrupt vector (handl er star t addres s) for source 26
INTV EC27 10 08ec R/W R/W Interrupt vector (handler start addr ess) for source 27
INTV EC28 1 0 08f 0 R/W R/W Interrupt vector (handler start address) for source 28
INTV EC29 1 0 08f 4 R/W R/W Interrupt vector (handler start address) for source 29
INTV EC30 1 0 08f 8 R/W R/W Interrupt vector (handler start address) for source 30
INTV EC31 10 08fc R/W R/W Inte rrupt vector (handler start address) for source 31
TIME R 1_T MO D ULU S 10 0c00 R/W R /W C ontains: (maximum count value for timer 1) + 1
TIMER1_TVALUE 10 0c04 R/W R/W Current value of timer 1 counter
TIMER1_TCTL 10 0c08 R/W R/W Timer 1 control (prescale value, source select, run bit)
TIME R 2_T MO D ULU S 10 0c20 R/W R /W C ontains: (maximum count value for timer 2) + 1
TIMER2_TVALUE 10 0c24 R/W R/W Current value of timer 2 counter
TIMER2_TCTL 10 0c28 R/W R/W Timer 2 control (prescale value, source select, run bit)
TIME R 3_T MO D ULU S 10 0c40 R/W R /W C ontains: (maximum count value for timer 3) + 1
TIMER3_TVALUE 10 0c44 R/W R/W Current value of timer 3 counter
TIMER3_TCTL 10 0c48 R/W R/W Timer 3 control (prescale value, source select, run bit)
SYSTIMER_TMODULUS 10 0c60 R/W R/W Contains: (maximum count value for system timer) + 1
SYSTIMER_TVALUE 10 0c64 R/W R/W Current value of system timer/counter
SYSTIMER_TCTL 10 0c68 R/W R/W System timer control (prescale value, source select, run bit)
BI CTL 10 1000 R/W R/W Inst ru ction breakpoint control
BINSTLOW 10 1004 R/W R/W Start of address range that causes instruction breakpoints
BI NST HIGH 10 1008 R/W R/W End of address range that causes i nstr ucti on br e akpoints
BDCTL 10 1020 R/W R/W Data breakpoint control
BDATAA LOW 10 1030 R/W R/W Start of address range that causes data breakpoints
BDATAA HIGH 10 1034 R/W R/W End of address range that causes data breakpoints
BDATAVAL 10 1038 R/W R/W Compare value for data breakpoints
BD ATAMASK 10 103c R/W R/W Compare mask for compare value f or data breakpoints
Cache And Mem ory System
DRAM_CACHEAB LE_LIMIT 10 0008 R/W R/W Start of non-cac heabl e region in DRA M
MEM_E VE NTS 10 000c R/W R /W Se lects two cache-r elated events for counti ng
DC_LOCK _CTL 10 0010 R/W R/W Enable bit for data-cache locking, also PCI hole disable
DC_LOCK _ADDR 10 0014 R/ W R/W Start of address range that will be locked into the data cache
DC_LOCK_ SIZ E 10 0018 R/W R/W Size of address range that will be locked into the data cache
DC_PARA MS 10 001c R/—R/—Data-cache geometry (blocksize, associativity, # of sets)
IC_PARAMS 10 0020 R/ —R/—Instruction-cache geometry (blocksize, assoc., # of sets)
MM_CONFIG 10 0100 R/—R/—DRAM settings (rank size, bus width, refresh interval)
ARB_BW_C T L 10 0104 R/W R/ W In ternal bu s ar bitration c ontrol (bandwidth /late ncy al locati on)
ARB_RAISE 10 010C R/W R/W Arbiter Priority Raising timer
POWER_DOWN 10 0108 R/W R/W Write to this register to initiate power down
IC_LOCK_ CTL 10 0210 R/W R/W Enable b it for in str uction-cache locking
IC_LOCK_ ADDR 10 0214 R/W R/W Start of address range that will be lock ed into the instruction
cache
MMIO Reg ist er Nam e Offset
(in hex)
Accessibility
Description
DSPCPU External
PCI
Initiators
Philips Semiconductors MMIO Register Summary
PRELIMINARY SPECIFICATION B-3
IC_LOCK_SIZE 10 0218 R/W R/W Size of address range that will be locked into the instruction
cache
PLL_RATIOS 10 0300 R/—R/—S ets ratios of external and internal clock frequencies
BLOCK_POWER_DOWN 10 3428 R/W R/W Powers up and down individual blocks
Video In
VI _STATUS 10 1400 R/—R/—Status of v ideo -in u nit
VI _CTL 10 1404 R/W R/W Sets operation and interrupt modes f or video in
VI _CLO CK 10 1408 R /W R/ W Set s cl ock source (i nte rn al/ext ernal), f r equency
VI_CAP _STA RT 10 140c R/W R/W Se ts captu re start x a nd y offsets
VI_CAP_SIZE 10 1410 R/W R/W Sets capt ure size width and height
VI_BASE1
VI_Y_BASE_ADR 10 1414 R/W R/W Ca pture modes: sets b ase address of Y-value arra y
Mess age/raw modes: sets b ase addres s of buffer 1
VI_BASE2
VI_U_BASE_ADR 10 1418 R/W R/W Capture mod es: s ets b ase address of U-value array
Mess age/raw modes: sets b ase addres s of buffer 2
VI_SIZE
VI_V_BASE_ADR 10 141c R/W R/W C apt ure mode s: sets bas e ad dress of V-value array
Message/raw modes: sets size of buffers
VI_UV_DELTA 10 1420 R/W R/W Ca pture modes: address delta f or adjacent U, V li nes
VI_Y_DELTA 10 1424 R/W R/W Capture modes: address delta f or adjacent Y lines
Video Out
VO_ S TATU S 10 1800 R/—R/—Status of video-out unit
VO_ CTL 10 1804 R/W R/ W Sets operation and interrupt modes for video out
VO_ CLOCK 10 1808 R/W R/W Sets video-out clock frequency
VO_F RAM E 10 180c R /W R/W Se ts f rame parameters (preset, star t, length)
VO_ FIELD 10 1810 R/W R/W Sets field parameters (overlap, field-1 l in e, f ield-2 line)
VO_ LINE 10 1814 R/W R/W Sets field parameters (starting pixel , fram e wi d th)
VO_ IMAGE 10 1818 R/W R/W Sets image p arameters (heigh t, w idth)
VO_Y THR 10 181c R/W R/W Sets thre shold for YT R interr upt, image v/h offsets
VO_ OLSTART 10 1820 R/ W R/ W S et s over lay image parameters (start line/pixel, alpha)
VO_ OLHW 10 1824 R /W R/ W Set s overl ay image parameters (hei ght , w idth)
VO_ YADD 10 1828 R/W R/W Sets Y-component/buffer-1 sta r ting addres s
VO_UADD 10 182c R/W R/W Sets U-component/buffer-2 starting address
VO_ VADD 10 1830 R/W R/W Sets V-component address/buffer-1 length
VO_ OLAD D 10 1834 R/W R/ W S ets o ver l ay i mage address/buffer-2 length
VO_ VUF 10 1838 R/W R/W Sets start-of-line -to-start-of-line address off sets (U, V)
VO_YOLF 10 183c R/W R/W Sets start-of-line-to-start-of-line addr. offsets (Y, overla y)
EVO_CTL 10 1840 R/W R/W Sets operations for enhance video out
EVO_MASK 10 1844 R/W R/W Sets YUV mask values foe the chroma-key process
EVO_CLIP 10 1848 R/W R/W Sets output clip values
EVO_KEY 10 184c R/W R/W Sets YUV chroma-key value s
EVO_SLVDLY 10 1850 R/W R/W Sets delay cycles for genlock mode
Audio In
AI_STATUS 10 1c0 0 R/—R/—St atus of audio-in unit
AI_CT L 10 1c04 R/ W R/W Se ts o peration and interr upt modes for audio in
AI_SERIAL 10 1c08 R/W R/W Sets clock ratios and internal/external clock generation
AI_FRAMING 10 1c0c R/W R/W Sets format of serial data stream
MMIO Reg ist er Nam e Offset
(in hex)
Accessibility
Description
DSPCPU External
PCI
Initiators
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
B-4 PRELIMINARY SPECIFICATION
AI_F REQ 10 1c1 0 R/W R/W Se ts AI_O SCLK frequen cy
AI_BA SE1 10 1c1 4 R/W R/W Se ts base addres s o f buffer 1
AI_BA SE2 10 1c1 8 R/W R/W Se ts base addres s o f buffer 2
AI_SIZE 10 1c1c R /W R/W Se ts num ber of samples in buffe rs
Audio Out
AO_STATUS 10 2000 R/—R/—Status of audio-out unit
AO_CTL 10 2004 R/W R/W Sets operation and interrupt modes for audio out
A O_SERI AL 10 2008 R/ W R/ W Set s cloc k ra tio s and in ternal/ext ern al cl ock generation
AO_FRAMING 10 200c R/W R/W Sets format of serial data stream
AO_FREQ 10 2010 R/W R/W Set AO_ OSCLK frequency
AO_BASE 1 10 2014 R/W R/W Sets base address of buff er 1
AO_BASE 2 10 2018 R/W R/W Sets base address of buff er 2
AO_SIZE 10 201c R /W R/W Se ts num ber of samples in buffe rs
AO_CC 10 2020 R/W R/W Codec control fiel d values
AO_CFC 10 2024 R/W R/W Codec Frame Control
AO_TSTAMP 10 2028 R/—R/W Timestamp of the last buffer
SPDIF Out
SDO_STATUS 10 4C00 R/—R/—Status re gister
SDO_CTL 10 4C04 R/W R/W Control register
SDO_FREQ 10 4C08 R/W R/W Frequency register
SDO_BASE1 10 4C0C R/W R/W Base address of buffer 1
SDO_BASE2 10 4C10 R/W R/W Base address of buffer 2
SDO_SIZE 10 4C14 R/W R/W Number of samples in buffers
SDO_TSTAMP 10 4C18 R/—R/—Timestamp of the last buffer
PCI Interface
BI U_STATUS 10 3004 R/—R/—S tatus of PCI interface (done/busy bits, error bits)
BI U_C TL 10 3008 R/W R/W Sets operation and interrupt modes for PCI
PCI_ADR 10 300c R /W —/—Holds addres s for DS PCP U PCI a ccess
PCI_DATA 10 3010 R/W —/—Hol ds data fo r DSPCP U PCI a cces s
CONFIG _ADR 10 3014 R/W R/W Holds address f or configuration access
CONFIG _DATA 10 3018 R /W R/W Holds data for config uration access
CONF IG_C TL 10 301c R /W R/W Se ts read/wr ite, bus number fo r c onfi guration ac cess
IO_A DR 10 3020 R/ W R/W Ho lds address f or I/O access
IO_DATA 10 3024 R/W R/W Ho lds data for I/O access
IO_CTL 10 3028 R/W R/W Sets read/write, byt e-enable for I/O access
SRC _ADR 10 302c R/W R/W Hol ds source addre ss f or DM A operation
DEST_ADR 10 3030 R/W R/W Holds destination addre ss for DMA operation
DMA_CTL 10 3034 R/W R/W Sets re ad/write, transfe r l ength for DMA operation
INT_CTL 10 3038 R/W R/W Controls interrupt sy stem
XIO_CTL 10 3060 R/W R/W XIO control register
JTAG
JTAG_DATA_IN 10 3800 R/W R/W JTAG data input buff er
JTAG_DATA_OUT 10 3804 R/W R/W JTAG data output buffer
JTAG_CTL 10 3808 R/W R/W JTAG control
Image Co-Processor
MMIO Reg ist er Nam e Offset
(in hex)
Accessibility
Description
DSPCPU External
PCI
Initiators
Philips Semiconductors MMIO Register Summary
PRELIMINARY SPECIFICATION B-5
ICP_MPC 10 2400 R/W R/W MicroProgram Counter
ICP_MIR 10 2404 R/W R/W Micro Instruction Register
ICP_DP 10 2408 R/W R/W Data Pointer
ICP_DR 10 2410 R/W R/W Da ta Regis ter
ICP_SR 10 2414 R/W R/W Status Register
VLD Co-Processor
VLD_COMMA ND 10 2800 R/W R/W Next action to be taken by VLD
VLD_SR 10 2804 R/ —R/—Bitstream shift register
VLD_QS 10 2808 R/ W R/W Quantiza tion Scale Code
VLD_PI 10 280C R/W R/W Picture lay er Information
VLD_STATUS 10 2810 R/W R/W Status Register
VLD_IMASK 10 2814 R/W R/W Controls which status bits causes VLD interrupts
VLD_CTL 10 2818 R/W R/W Control Register
VLD_BIT_ADR 10 281C R/W R/W Current Bitstream Read Address
VLD_BIT_CNT 10 2820 R/W R/W Bitstrea m remaining byte count
VLD_MBH _ADR 10 2824 R/W R/W Macro Block H eader output ad dr ess
VLD_MBH _CNT 10 2828 R/W R/W Macro Block Header output remaining count
VLD_RL_ADR 10 282C R/W R/W Run/Length output address
VLD_RL_CNT 10 2830 R/W R/W Ru n/Length outpu t remai ning cou nt
I2C Interface
IIC_AR 10 3400 R/W R/W Address, Byte count and Direction
IIC_DR 10 3404 R/W R/W Data Register
IIC_STATUS 10 3408 R/—R/—St atus Register
IIC_CTL 10 340C R/W R/W Control Register
Synchronous Serial Interface
SSI_CTL 10 2C00 R/W R/W Control Register
SSI_CS R 10 2C04 R /W R /W Ad diti onal Control and Status register
SSI_TXDR 10 2C10 —/W —/W Transmit Data Register
SSI_RXDR 10 2C20 R/—R/—Receive Data Register
SSI_RXACK 10 2C24 —/W —/W Wr ite a ‘1’ here to ACK read of Receive Data Register
SEM Device
SEM 10 0500 R/W R/W Simple multi-processor semaphore
MMIO Reg ist er Nam e Offset
(in hex)
Accessibility
Description
DSPCPU External
PCI
Initiators
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
B-6 PRELIMINARY SPECIFICATION
PRELIMINARY SPECIFICATION C-1
Endian-ness Appendix C
by Selliah Rathnam, Luis Lucas
C.1 PURPOSE
In th is docum ent, th e gene ric PNX1 300 n ame refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 was designed to support both Little and Big
En dian sy stem s. T h e PCI s yste m bus (co ntr olle d b y t he
PC I Interface Unit (BIU)) operates in Little Endian mode
in both systems. This document describes how the dual
endian-ness feature is handled in PNX1300.
C.2 LI TTLE A ND BIG E NDIAN
ADDRESSING CONVENTIONS
In Big Endian mode, a given word address (32-bit) base
corresponds to the most significant byte (MSB) of the
word. Increasing the byte address generally means de-
cr easi ng the sign if i canc e of t h e by t e being ac ces se d. In
Little E ndian mode, the same word a ddress base refers
to the least significant byte (LSB) of that word. Increasing
the byte address generally means increasing the signifi-
cance of the byte be ing acc essed. T his addressin g con-
vention is shown in Figure C-1.
In Fi gure C-1, ther e is a t wo- l ine ‘C’ code which defines
a 32- bit const ant in hex f ormat as sign ed to th e vari able
‘w’ (assumes ‘int’ i s 32-bit) and its address is copied into
the byte (character) pointer variable ‘cp’. Th e value o f ad-
dress referenced by the ‘cp’ has a va lu e of ‘0x04’ in Big
End ian machi ne and a valu e of ‘0x07’ i n Litt le End ian ma-
chine.
It is possible to transfer from one endian-ness to another
jus t by sw apping the by tes w ith in a word as shown in Fig-
ure C -2 .
int w = 0x04050607;
char *cp = (char *)&w;
Figure C- 1. Big and Little Endian addr ess references
031
04 05 06 07
B ig Endian Mod e Littl e E ndia n Mo de
cp+0
04 05 06 07
cp+3
cp+1 cp+2 cp+3 cp+2 cp+1 cp+0
0
31
Figure C-2. Data conversion from Big Endian to Little Endian (BSW)
int w = 0x04050607;
char *cp = (char *)&w;
031
07 06 05 04
Big Endian Mode
Little Endian Mode
cp+0
04 05 06 07
cp+3
cp+1 cp+2 cp+3
cp+2 cp+1 cp+0
0
31
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
C-2 PRELIMINARY SPECIFICATION
C.3 TEST TO VERIFY THE CORRECT
OPERATION OF PNX1300 IN BIG A ND
LI TTLE ENDI AN SYSTEMS
The following test can be used to verif y the correct oper -
ation of PNX1300 in Little Endian and Big Endian sys-
tems.
1. Store a 32-bit constant ‘0x04050607’ fro m the ho st
CP U to the PN X1300 SDRAM through th e PCI inter-
f a ce . Loa d th e wo rd fr om th e sa me ad dre ss t o one of
the PNX1300’s gl obal regis ter an d che ck f or the same
value.
2. Store a 32-bit constant ‘0x04050607’ fro m the ho st
CPU to the PNX1300 SDRAM through PCI interface.
Load a byte from the same address to one of the
PNX1300 gl obal registers. Check for the value of
‘0x04’ i n B i g End i an syste ms , and chec k f or the va lu e
‘0x07’ in Little Endian systems.
C.4 REQUIREMENT FOR THE PNX1300 TO
OPERATE IN EITHER LITTLE ENDIAN
OR BIG ENDIAN MODE
The endian-ness handling in each PNX1300 unit is de-
scribed in the following sections. Most units use the high-
way /P CI bus to tr an s fer da ta. T h e h ig hw a y/P CI bus h as
four byte lan es. The bit assig nme nt of the highway/PCI
bus lanes is sh o wn in Ta ble C-2.
The PCI b us and P NX1300 highway buses are ad dress-
invariant buses, i.e the data corresponding to address
offset ‘0’ uses the byte-0 lane of the highway/PCI bus,
the data corresponds to a d d re ss off set ‘1’ uses the by t e -
1 lane of t h e h ig hw a y /P CI bus etc .
C.4.1 Data Cache
The PNX1300 PCSW register has a byte-sex (BSX) bit
to configure the PNX1300 in Big Endian or Little Endian
mode. T his bit must be set to ‘1’ for the Little Endian
mode as defined in Chapter 3, “DSPCPU Arc hitecture .”
Thi s B SX bi t is us ed by t he PNX13 00 da t a cac he un it for
the store /load operati on. Data cac he performs thr ee cat-
egor ies of d ata t ransac tions :
•Read/write data from/to DSPCPU registers to/from
data cache or SDRAM
•Rea d/ wri te of MMI O d ata f rom /to D SP CPU regi st ers
to/from MMIO registers
•Read/write data from/to DSPCPU registers to/from
PCI address space through special registers in the
BIU unit.
The DSPCPU endian-ness is determined by the value of
th e BSX b it in t he P C SW re gist er. Table C-1 and Table
C-3 describe the data translation format bein g used by
the data cache to transfer the data to/from DSPCPU reg-
i st er to /fr o m d at a ca c he or SD R AM . Table C-1 and Table
C-3 are restricted to addresses that fall in the
DRAM_BASE and DRAM_LIMIT range.
The r e is no byte- s wa p require d for th e MMIO data trans-
action from/to DSPCPU register to the MMIO registers.
However, one of the special registers, PCI_DATA, does
not follow the normal MMIO transactions. The data
c ache by te -sw ap s the da ta to/f r om the PCI_ DA TA regi s-
ter using the data translation format as defined in Table
C-1 and Table C-3 for the memory cycle.
For the PCI configuration cycle and I/O cycle transac-
tions from the DSPCPU, a programmer can byte-swap
the data in the DSPCPU registers and write to the
PC I_DAT A re giste r using MMIO write operati on s . There
is no byte-swap from the PCI_DATA register in BIU unit
to the PCI bus. Software uses the Ta ble C -1 or Table C-
3 data to byte-swap the data within the CPU register be-
fore writing the data to the PCI_DATA register for the
configur a t io n an d I/O c y cle tr an sac tions .
Table C-1. Little Endian data format in PNX1300 DSPCPU register, highway, SDRAM memory, PCI bus, host
memory, host CPU register
PCSW-
BSX
value
Endian
Mode Data Transaction
type Address
Data in
DSPCPU
register
msb lsb
Data in highway/
Dcache/SDRAM/
PCI-bus
byte3 byte0
[31:24] [7:0]
Data in host
CPU register
msb lsb
Data in host
memory
byte3 byte0
[31:24] [7:0]
1 Little Word r/w 00001000 01020304 01020304 01020304 01020304
1 Li ttle Half-Word r/w 00001000 x xxx0 304 xxxx 0304 xxxx0304 x xxx0 304
1 Li ttle Half-Word r/w 00001 002 x xxx0 304 0304x xxx xxxx0304 03 04x xxx
1 Little Byte read/write 00001000 xxxxxx04 xxxxxx04 xxxxxx04 xxxxxx04
1 Little Byte read/write 00001001 xxxxxx04 xxxx04xx xxxxxx04 xxxx04xx
1 Little Byte read/write 00001002 xxxxxx04 xx04xxxx xxxxxx04 xx04xxxx
1 Little Byte read/write 00001003 xxxxxx04 04xxxxxx xxxxxx04 04xxxxxx
Table C-2. Bit assignment of the highway/PCI bus
lanes
byte 3 byte 2 b yte 1 byte 0
Bits 31:24 23:16 15:8 7:0
Philips Semiconductors Endian-ness
PRELIMINARY SPECIFICATION C-3
C.4.2 Instruction Cache
It is assumed that the instruction cache always operates
in Li t tle E ndian regardless of the host and PNX13 00 en-
dian-ness. Instruction cache does not use the PCSW’s
byte sex bit (BSX). The compiler supports the loading of
instr uction s in mem or y diff e r ently for Big E n dian and Lit-
tle Endian modes.
C.4.3 PNX1300 PCI Interface Unit
The PNX1300 highway bus and the PCI bus are address
invariant buses, i.e. a data corresponding to address
zero is always transferred through the byte-zero line re-
gardless of the endian-ness. The address-invariant na-
ture of the PCI and the highway buses allows data to be
transferred from/to PCI bus directly to/from SDRAM with-
out byte swappi ng in e ithe r Bi g or Litt le Endian mode The
byte swapping of data for Big Endian mode is performed
by the data cache unit. However, MMIO data does not go
thr ough the byte swapper in the Data cache. This result s
in using a byte-swapper in the BIU to byte-swap the
MMIO data in Big Endian mode.
The PNX1300 BIU has a se parate byte sex (SE, Swap
Enabled) flag defined in its control register (BIU_CTL).
This byte-sex flag must be set by the software, i.e. MMIO
writ e op eratio n fro m the ho st CPU . This byt e-se x flag is
used only for MMIO data accesses and none of the
MMIO data accesses is affected by this SE flag. Table C-
4 shows the byte-swap logic that handles the MMIO ac-
cesses from the DSPCPU and host CPU and the non
MMIO data accesses from any source.
The B IU has s eve r al spec ia l regi st e rs t o handl e mem ory,
PCI configuration, I/O and DMA accesses. It does not
byte-swap the I/O data from the special r egisters. The
data cache and software performs the necessary byte
swapping for this data.
When using PNX1300 in Little Endian-based systems,
the first transaction to the PNX1300 is to set the SE bit in
the BI U conf i gur at ion r eg is ter to av oid unn ec ess ary sof t-
ware byte-swapping in the host CPU fo r the subsequent
MMIO read/write accesses. The SE bit in the BIU_CTL
register controls the byte swapping of outgoing and in-
coming data from PCI bus. The default value of SE is ‘0’,
i. e th e BIU byt e-swa ps the MMIO dat a incl uding the wri te
operation to the BIU_CTL register. Software is required
to byte swap the BIU_CTL register value within the host
CPU before storing the value in BIU_CTL register. Once,
the BIU.SE bit has been set, no additional software byte-
swapping is required for furt her read/write operations to
any MMIO registers.
C.4.4 Image Coprocessor (ICP)
Th e inpu t sour ce data for the IC P unit mig ht com e fr om
diffe rent units such as Video I n, the DS PCPU, PC I bus,
etc. via SDRAM. Data consistency needs to be main-
ta in ed when the PNX1 30 0 op er a te s in Li t tl e or Big En di-
an systems/mode. The ICP needs the capability to oper-
ate on the SDRAM as source dat a and SDRAM or PCI
as d estina tion data in ei ther Little or Bi g Endian mode.
Figu re C- 3 , Figure C-4, Figure C-5 and Figure C-6 illus-
trate t he Big and Little Endian memory image format for
the image input fo rmat (Figure C-3) and the three sup-
por te d im age ov er l ay fo rmats.
The ICP can out put the da t a to eith er t he SDRA M or PC I
bus. RGB 8R and RGB 8A pixel formats are byte streams
and t heref ore do no t re quir e an y by te swa ppin g. Figure
C-9 pictures the data format. RGB-24+α, RGB-15+α,
RGB-16 and YUV-4:2:2 pixel formats can be used to out-
put th e pixe ls to P CI or SDRAM in both Endi an mo des.
Output formats are shown, respectively, in Figure C-4,
Figure C-5, Figure C-8, and Figu r e C -7 . Packed RGB-24
cannot be used in Big Endian mode. Little Endian data
format is shown in Figure C-11.
Table C-3. Big Endia n data format in the PNX1300 DSPCPU register, highway, SDRAM memory, PCI bus, host
memory, and host CPU register
PCSW-
BSX
value
Endian
Mode Data transaction
type Address
Data in
DSPCPU
register
msb lsb
Data in highway/
Dcache/SDRAM/
PCI-bus
byte3 byte0
[31:24] [7:0]
Data in Host
CPU register
msb lsb
Data in host
memory
byte0 byte3
[31:24] [7:0]
0 Big Word r/w 00001000 01020304 04030201 01020304 01020304
0 Big Half-word r/w 00001000 xxxx0304 xxxx0403 xxxx0304 0304xxxx
0 Big Half-word r/w 00001002 xxxx0304 0403xxxx xxxx0304 xxxx0304
0 Big Byte read/write 00001000 xxxxxx04 xxxxxx04 xxxxxx04 04xxxxxx
0 Big Byte read/write 00001001 xxxxxx04 xxxx04xx xxxxxx04 xx04xxxx
0 Big Byte read/write 00001002 xxxxxx04 xx04xxxx xxxxxx04 xxxx04xx
0 Big Byte read/write 00001003 xxxxxx04 04xxxxxx xxxxxx04 xxxxxx04
Ta ble C-4. B IU.S E bit usage in processing da ta in
BIU unit
BIU.SE
value Endian
Mode
MMIO
access
from
DSPCPU
MMIO
access from
PCI side
Non MMIO
data
0 Big No byte-swap byte-swap No byte-
swap
1 Little No byte-swap No byte-swap No byte-
swap
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
C-4 PRELIMINARY SPECIFICATION
No t e: A + 0 corres pond s to by te-0 lane of SDR AM/ H w y
and A+ 3 corresponds to byte-3 lane of SDRAM/Hwy
Figure C-3. Byte mask, planar YUV 4:2:0 and YUV 4:2:2 for ICP, VO or VI memory data in Little and Big En-
dia n modes
Y pix el byte data
Y7 Y6 Y5 Y4
Y3 Y2 Y1 Y0
Big Endian Mode Little Endian Mode
in memory
A+3
(same for U, V, B)
Y3 Y2 Y1 Y0
Y7 Y6 Y5 Y4
A+3
A+2 A+1 A+0 A+2 A+1 A+0
31 31 0
0
Figure C-4. RBG-24+α dat a forma t for ICP in Little and Big Endian modes
α0R0G0B0
Pixel word data
α1R1 G1 B1α1R1G1B1
α0R0 G0 B0
Big Endian Mode Little Endian Mode
in memory or P CI
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A +3 c orr e s po nds to by te-3 lan e of SD R AM /H w y /P C I
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
31 31 00
Figure C-5. RBG-15+α data format for ICP in Little and Big Endian modes
Pixel half-word data
in memory or PCI
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
αR0G’0
G0B0αR1G’1
G1B1
αR2G’2
G2B2
αR3G’3G3B3
αR0G’0G0B0
αR1G’1G1B1
αR2G’2G2B2
αR3G’3G3B3
Big Endian Mode Little Endian Mode
Pn+1 Pn+1
PnPn
31 31 00
Note: A+0 c orre s pond s to byte - 0 l an e of SDRAM /Hw y /P CI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
Philips Semiconductors Endian-ness
PRELIMINARY SPECIFICATION C-5
Figure C-6. Packed YUV 4:2 :2+α data format for the ICP or VO in Little and Big Endian modes
Pixel half-word data
Big Endian Mode Little Endian Mode
in memory or PCI
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
Pn+1 Pn+1
PnPn
U0α0 Y0
V0α1 Y1
U1α2 Y2V1α3 Y3
U0α0
Y0
V0α1
Y1
U1α2
Y2V1α3Y3
31 31 00
Not e: A+0 c orrespond s t o by te - 0 la ne of SD RA M / H wy/P C I
and A +3 c orr es ponds to by t e -3 lane of SDRAM/H wy/PC I
Figure C-7. Packed YUV 4:2:2 data format for ICP in Little and Big Endian modes
Pixel half-word data
Big Endian Mode Little Endian Mode
in memory or PCI
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
Pn+1 Pn+1
PnPn
U0 Y0
V0 Y1
U1 Y2
V1 Y3
U0
Y0
V0
Y1
U1
Y2
V1
Y3
31 31 00
Not e: A+0 c orrespond s t o by te - 0 la ne of SD RA M / H wy/P C I
and A +3 c orr es ponds to by t e -3 lane of SDRAM/H wy/PC I
Figur e C-8. RBG- 16 da ta for m at for I CP in Little and Big En d ian mod es
Pixel half-word data
in memory or PCI
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
R0G’0
G0B0R1G’1
G1B1
R2G’2
G2B2
R3G’3G3B3
R0G’0G0B0
R1G’1G1B1
R2G’2G2B2
R3G’3G3B3
Big Endian Mode Little Endian Mode
Pn+1 Pn+1
PnPn
31 31 00
Note: A+0 c orre s pond s to byte - 0 l an e of SDRAM /Hw y /P CI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
C-6 PRELIMINARY SPECIFICATION
Figure C-9. RGB8 A a nd RGB8R data format for ICP in L ittle and Big Endian modes
RGB 8A or 8R
P7 P6 P5 P4
P3 P2 P1 P0
Big Endian Mode Little Endian Mode
in Memory or PCI
A+3
(Same for U, V, B)
P3 P2 P1 P0
P7 P6 P5 P4
A+3
A+2 A+1 A+0 A+2 A+1 A+0
31 31 0
0
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCI
and A +3 c or r es po nds to byte- th ree la ne of S D R AM /H w y /PC I
Figure C-10. Half-word swap within a half-word (BSH)
031
05 04 07 06
Before swap
After Swap
04 05 06 07
0
31
Figure C-11. Packed RBG-24 data format for ICP in Little Endian mode only
Pixel Word Dat a B1 R0 G0 B0
Big Endian Mode Little Endian Mode
in Memor y or PCI
Note: A+0 corresponds to byte- zero lane of SDRAM/Hwy/ PCI
and A +3 c or re s pond s to by t e -t hr ee lane of SD RAM/H w y / P CI
A+3 A+2 A+1 A+0
31 0
R2
G2 B2
NOT SUPPORTED G1
R1
R3 G3 B3
Philips Semiconductors Endian-ness
PRELIMINARY SPECIFICATION C-7
The Table C-5 shows the byte-swap implementation of
vari ous pixe l forma ts us ed in th e ICP u nit. Refe r to Figure
C-2 and F igure C-10 for the byte-swap code used in Ta-
ble C-4 and Table C-5. Byte- sw app in g is per fo rme d onl y
in B ig Endia n mode. No s wappi ng is don e in t he Litt le En-
dian mode.
The ICP has a byte sex bit (L) defined in its MMIO-based
c onfiguration register. T he setting of this bi t a nd the BSX
bit in t he P CSW re giste r s houl d be t he s ame . The L bit
must be set by th e so ftware.
C.4.5 Video In (VI) and Video Out (VO) Units
The VI un it st ore s the YUV pixe ls in pl anar 4:2: 2 or 4:2 : 0
image format as shown in Figure C-3 and stores the raw
8- and 10-bit data as shown in F igure C-12.
The VO unit uses YUV-4:2:2 planar, YUV-4:2:0 planar,
and YUV-4:2:2+α packe d as in put pixe l format s. The pl a-
nar memory image format of the YUV-4:2:2 and YUV-
4:2 : 0 are sh ow n in Fi gu r e C - 3. The YUV-4:2:2+α memo-
ry image format for overlay is pictured in Figure C-6.
The VI and VO units have a byte-sex bit (Little Endian
and LTL_END) defined in the control MMIO registers,
VI_CONTROL and VO_CONTROL. The definition of
these byte-sex bits and the BSX bit in the PCSW register
should be tr eated as same . Little Endian and LTL_E N D
bits must be set by software.
C.4.6 Audio In (AI), Audio-Out (AO), and
SPDIF Out (SDO) Units
The AI unit uses 8-bit mono, 8-bit stereo, 16-bit mono
and 16-bit stereo data. The AO unit uses 16-bit mono,
16-bit stereo, 32-bit mono and 32-bit stereo data. The
SPDO unit uses 32-bit word data. The memory image
form at of t hese data is pr esented in Figure C-13.
Swappi ng ta kes place at the byt e level and th e bits within
a byte are never disturbed. Both the AI and AO units
have a byte sex bit (LITTLE_ENDIAN) defined in each
units MMIO-based configuration register. The definition
of the th e se bits an d the BSX bi t in the PCSW register
s houl d be t rea te d as same . Thi s by te se x bi t must be set
by th e sof tw ar e.
C.4.7 Variable Length Encoder (VLD) Unit
The VLD inputs data from SDRAM in the form of a bit -
str ea m with a by t e -a ligne d star ti ng a dd ress and outputs
a heade r str e am an d a ‘run-level’ data stream. The VLD
unit h as a byte sex bit (LIT TLE_E NDIAN) defined in its
MMIO-based configuration register. The definition of this
Tabl e C-5. ICP byte swapp ing ty p e for input data
En dia n-n ess L bit Pixel Typ e Swap Type
(see Figure C-2
& Fi gu r e C - 1 0)
Big Endian 0 Y,U ,V planar No swap
Big Endian 0 RGB 24+αBSW
Big Endian 0 YUV-4:2:2+αBSH
Big Endian 0 RGB 15+αBSH
Tabl e C-6. ICP byte swapp ing ty p e for output data
Endian-
ness L bit Pixel Type Swap Type
(see Figure C-2 &
Figure C-10)
Big Endian 0 RGB 8A: 233 No swap
Big Endian 0 RGB 8R: 332 No swap
Big Endian 0 RGB 15+αBSH
Big Endian 0 RGB 16 BSH
Big Endian 0 RGB 24+αBSW
Big Endian 0 RGB24
packed No support for Big
Endian
Big Endian 0 YUV- 4:2:2
packed BSH
Figure C-12. Memory image format for raw 8-bit and 10-bit data
Dn+3 Dn+2 Dn+1 Dn
Big Endian Mode Little Endian Mode
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
raw 8-bit data
in memory Dn+3 Dn+2 Dn+1 Dn
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
raw 10-bit data
in memory Dn+1 Dn
lsb msbmsblsb Dn+1 Dnlsbmsbmsb lsb
No te: A + 0 cor r es po nd s to by t e -0 lane of SDR AM/H wy
and A+ 3 corresponds to byte-3 lane of SDRAM/Hwy
lsb is the Least Significant Byte
msb is the Most Significant Byte
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
C-8 PRELIMINARY SPECIFICATION
bit and the BSX bit in the PCSW register should the
same. This byte sex bit must be set by the software.
Figure C-14 desc r ib es the VLD inp ut and outp ut d a t a for -
mat as seen in the SDRAM and highway bus. The input
dat a is by t e oriented and no s wapping is r equ ir ed i n the
VLD unit. However, the output data is read by the
DSPCPU in words, thus the VLD needs to swap the out-
put byt es wit hin a wor d (s how n in F igur e C- 14) to com -
pens ate f or the CPU sw ap .
C.4.8 Synchronous Serial Interface (SSI)
The SSI unit has I/O connections through the external
serial pins and also to the internal 32-bit data highway via
MMIO transactions. The minimum quantity of data to be
analyzed by the CPU is 16-bits (i.e. one half word). The
SSI uses a 16-bit or 1-bit endian-ness; it is detailed in
Section 17.8 on page17-7 . The 3 2-b it quant it y contai ned
in the C PU r eg is ter is wr i tten or read ‘as is’ into/from the
SSI MMIO register. The EMS bit in SSI_CTL determines
which half-word (16-bit) is sent first as pictured in Figure
C-15.
Figur e C-13. Memory image for mat for audio data
Ln+3 Ln+2 Ln+1 Ln
Big Endian Mode Little Endian Mode
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
8-bit data (mono)
in memory Ln+3 Ln+2 Ln+1 Ln
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
16-bit data (mono)
in memory Ln+1 Ln
lsb msbmsblsb Ln+1 Lnlsbmsbmsb lsb
No t e: A+0 corr es pond s to by te- z er o lane of SD RA M /Hw y
a nd A +3 cor respon ds to byte -three lane of SDR A M/H wy
lsb is the least significant byte
msb is the most significant byte
Rn+1 Ln+1 RnLn
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
8-bit data (stereo)
in memory Rn+1 Ln+1 RnLn
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
16-bit data (stereo)
in memory RnLn
lsb msbmsblsb RnLnlsbmsbmsb lsb
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
32-bit data
in memory
msb
lsb lsbmsb
Figure C- 15. SSI data format as seen in highway
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
16-bit half-wo rd data
in CPU/MMIOs Dn+1
DnDn+1 Dnlsbmsbmsb lsb
No te: A+0 corr espo nd s to byte-0 lane of CPU/H wy
and A+3 corresponds to byte-3 lane of CPU/Hwy
lsb is the least significant byte
msb is the most signif icant byte
SSI_CTL.EMS = 0 SSI_CTL.EMS = 1
lsbmsbmsb lsb
Philips Semiconductors Endian-ness
PRELIMINARY SPECIFICATION C-9
C.4.9 Compiler
Th e TC S com pile r s upp orts t he load ing o f ins truc tion in
memory differently for Big Endian and Little Endian
modes.
C.5 SUMMARY
PNX13 00 i s requir ed to ope rat e in the sam e endi an- ness
as the host CPU. At reset, PNX1300 operates in Big En-
dian mode; no special steps are required to set the Endi-
an bi ts . W hen u sing P NX1 300 i n Lit tle En dian syst em s,
the first transaction is to set the S E bit in the BIU_CTL
re gi ster a s de sc rib ed in th e s eco nd parag r aph o f Section
11.6.5 on page11-11.
C.6 REFERENCES
1. PCI Multimed ia D es ign G uide, revisi on 1.0 - date d
Mar c h 29 ,19 94
2. Designing PCI Cards and Drivers for Power Macin-
to sh C o mputer s, By Apple Computer, Inc.; Refer-
ence: R0650LL/A; Phone: 1-800-282-2732
Figure C-14. VLD input and output data format
Byten+3 Byten+2 Byten+1 Byten
Big Endian Mode Little Endian Mode
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
Input data Byten+3 Byten+2 Byten+1 Byten
12 34 56 78
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
Header output
Header = 0x12345678
Note: A+0 correspon ds to byte-0 lane of SDRAM/Hwy
and A +3 c or r es po nds to byte-1 la ne of SDRAM /Hwy
1234
56
78
12 34 56 78
A+3 A+3
A+2 A+1 A+0 A+2 A+1 A+0
Run level output
Run value = 0x1234
Level value = 0x5678 1234
56
78
At word Address A
PNX1300/01/ 02/11 Data Book Philips Sem iconductors
C-10 PRELIMINARY SPECIFICATION
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-1
Index
Numerics
12nc 1-10
A
A/D converte r 8-1
Absolute ma ximum ratings 1-11
AC characteristics 1-11
address fields,instruction cache 5-8
addr e s s lin es
driving capacity 12-7
ad dre s s mapp ing
based on rank si z e12-5, 12-6
DRAM memory syste m12-5
inst ruction cache 5-8
picture 5-9
addr es sing m odes 3-4
AI_BASE1
picture 8-5
AI_BASE2
picture 8-5
AI_CONTROL
fie ld description tabl e8-6
AI_CTL
picture 8-5
AI_FRAMING
picture 8-5
AI_FREQ
picture 8-5
AI_OSCLK
descr i pt i on table 8-1
AI_SCK
descr i pt i on table 8-1
AI_SD
descr i pt i on table 8-1
AI_SERIAL
picture 8-5
AI_SIZE
picture 8-5
AI_STATUS
fie ld description tabl e8-6
picture 8-5
AI_WS
descr i pt i on table 8-1
algorithms
image pr o c es si ng 14-6
of En ha nc ed Vide o Ou t Unit 7-10
algor ith m s, I CP 14-6
alignment 5-4
alloc A-4
allocate on wri te 5-4
allocd A-5
allocr A-6
allocx A-7
alphablending codes 14-5
byte for alpha blending 14-5
keying 14-9
registers 14-5
alpha blendin g7-13, 14-1, 14-9
alpha ble nding code s14-5
table 14-5
alpha value
for overlay pixel 14-9
AO_BASE1
picture 9-8
AO_BASE2
picture 9-8
AO_CC
picture 9-8
AO_CFC
picture 9-8
AO_CONTROL
f iel d de sc r i ption tabl e 9-9, 9-10
AO_CTL
picture 9-8
AO_FRAMING
picture 9-8
AO_FREQ
picture 9-8
AO_OSCLK
description table 9-2
AO_SCK
description table 9-2
AO_SERIAL
picture 9-8
AO_SIZE
picture 9-8
AO_STATUS
f iel d de sc r i ption tabl e 9-9
picture 9-8, 16-2
aperture
DRAM 5-2
memory 12-1
PCI 11-2
aperture,PCI 5-5
APERTURE_CONTROL field 5-5
asi A-8
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-2 PRELIMINARY SPECIFICATION
asli A-9
asr A-10
asri A-11
audio captur e 8-5
audio code c 8-1, 8-3
audio in un it
di agno stic m ode 8-7
memory data formats 8-4
audio inp ut 8-1
audio mem or y fo rm at 8-4
audio ou t uni t
memory data formats 9-7
au di o sa mp le rat e 8-2
audio tes t 8-7
B
bandwidth
requirements of ICP 14-1
base address
PCI interface registers 11-7
BDATAAHIGH
picture 3-14
BDATAALOW
picture 3-14
BDATAMASK
picture 3-14
BDATAVAL
picture 3-14
BDCTL
picture 3-14
BICTL
picture 3-14
binar y com pa t ib il ity 3-4
BINSTHIGH
picture 3-14
BINSTLOW
picture 3-14
bit masking 14-28
bitand A-12
bitandinv A-13
bitinv A-14
bitmap
masking 14-1
bitor A-15
bitxor A-16
BIU_CTL
PCI interface MMIO register 11-11
picture 11-10
BIU_STATUS
PCI interface MMIO register 11-11
picture 11-10
blending
alpha 14-1
blending codes
alpha blendin g14-5
block timing
PCI output 14-16
boolean representation 3-3
borrow A-17
boundary scan 1-1
breakpoints 3-13
built-in self test
PCI interface register 11-7
byte ordering
DSPCPU 3-2
bytesex 3-2
C
cache
address mapping,instruction cache 5-8
alignment 5-3, 5-4
associativity 5-3
bandwidth requirements 5-1
block siz e5-3
blocksize 5-3
byte in word 5-3
coherency 5-3, 5-4, 5-11
copyback 5-4
copyback operation 5-6
CPU s tall 5-8
data cache characteristic s,table 5-3
data cache initialization 5-8
data cache,description 5-3
dcb opco d e5-6
dinvalid opcode 5-6
dirty bit 5-4
dirty bits 5-3
dual port 5-4
endian-ness 5-3, 5-4
hidden concurrency 5-7
iclr operation 5-9
initialization 5-8
instruction cache 5-8
instruction cache coherency 5-9
i ns tr u ction cach e ini t i alization and boot 5-10
instruction cache parameters 5-8
instruction cache summary 5-8
instruction cache tag 5-8
invalida te operation 5-6
latency 5-8
locking 5-3, 5-4
l oc k ing r e gister s 5-5
LRU r eplacem ent 5-11
memory hole 5-5
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-3
miss proc essing o r der 5-4, 5-9
miss transfer order 5-3
MMIO registers summary 5-13
noncachable region 5-3
non- c a ch eable r eg io n 5-5
number of sets 5-3
oper ati on order in g 5-7
overview 5-1
overvi ew ,memo r y s yste m5-1
parameters 5-3
par ti al w or d tran sfer s 5-4
partial words 5-3
performance evaluation suppor t5-12
performance events
table 5-13
ports 5-3
rdstatu s result format 5-6
rdtag re sult forma t5-6
replac ement policies 5-3, 5-4
replac ement policy 5-9
scheduling constraint 5-4
set 5-3
size 5-3
special data cache operations 5-6
sp ec i al op co des 5-4
speci al oper a ti on orde r in g 5-7
st atus op erati ons 5-6, 5-7
summary of characte ristics 5-2
tag field of address 5-3
tag operation s 5-6, 5-7
valid bits 5-3
word in set 5-3
write misses 5-4
cache line size
PCI interface register 11-7
carry A-18
CCCOUNT
definition 3-3
CCIR 656
li ne timing
description 7-4
pi xe l tim ing
description 7-4
video connector on Enhanced Video Out
Unit,picture 7-2
CC IR 656 frame t iming
description 7-6
descr i pt i on table 7-6
CCIR 656 line timing
picture 7-5
CCIR 656 pixel timing
picture 7-5
CCIR656 serial D1 7-2
chroma
keying 14-1
Chroma keying 7-14
ch r oma keyi ng 14-1, 14-9
circuit board design
guidelines 12-7
class code
PCI interface register 11-6
Clipping 7-14
codec 8-1
coherency 5-4
coherency ,ins truction cache 5-9
command ID
PCI interface register 11-3
compatibility
software 3-4
concurrency
PCI interface 11-3
concurrency,hidden 5-7
CONFIG_ADR
PCI interface MMIO register 11-12
picture 11-10
CONFIG_CTL
PCI interface MMIO register 11-13
picture 11-10
CONFIG_DATA
PCI interface MMIO register 11-13
configuration header 11-3
configuration operations
PCI interface 11-2
control word
ICP vertical filter 14-25
of IC P 14-23
conversion
inters pers ed to c o-sit ed 7-11
to RGB 14-1
to YUV composite 14-1
YUV to RGB 14-3, 14-9
copyback 5-4
co-sited s am plin g 6-4
counter 3-12
CPU s tall 5-8
curcycles A-19
cycles A-20
D
D1 seri al 7-2
data address fie lds 5-3
data breakpoint 3-13
data cache
coherency 5-11
dcb operatio n5-6
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-4 PRELIMINARY SPECIFICATION
dinval id ope r ation 5-6
initialization 5-8
LRU replacement 5-11
performance evaluation suppor t5-12
rdstatus operation 5-6
rdt ag operation 5-6
data cache locking registers 5-5
data fo r ma t
planar 14-3
DC/AC Characteristic s1-11
DC_LOCK_ADDR
descr i pt i on table 5-13
register 5-5
DC_LOCK_CTL
descr i pt i on table 5-13
register 5-5
DC_LOCK_SIZE
descr i pt i on table 5-13
register 5-5
DC_PARAMS
descr i pt i on table 5-13
fields 5-3
picture 5-3
DC_PARAMS register 5-3
dcb 5-6, A-21
dcb op er a tion 5-6
DDS 7-3, 8-2
debug fr o nte nd 18-3
debug supp or t 3-13
DEST_ADR
PCI interface MMIO register 11-14
picture 11-10
device control 3-7
device ID
PCI interface register 11-3
device interrupts 3-11
di agno stic m ode 8-7
audio in un it 8-7
dimensions 1-10
dinvalid 5-6, A-22
dinval id ope r ation 5-6
direct digital s ynthesizer 7-3, 8-2
dir t y bit 5-4
dithering 14-10
algorithm 14-10
method 14-10
DMA operations
PCI interface 11-2
DMA_CTL
PCI interface MMIO register 11-14
picture 11-10
downscaling 14-1
DPC
definition 3-3
DR A M aper t ur e 5-2
DRAM base 5-2
DRAM limit 5-2
DR AM mem o ry system
address aperture 12-1
address mapping 12-5
circuit board desig n12-7
ex ample block diag ra ms 12-9
example configurations table 12-3
features 12-1
gr anul arity a nd s izes 12-2
initialization 12-6
mode register setting 12-6
on-chip interleaving 12-6
output drive r capacity 12-7
power down mode 12-7
programming 12-3
refresh 12-6
signal pins 12-5
supported devices 12-2
supported rank configurations 12-2
DRAM_BASE
description table 5-13
PCI interface MMIO register 11-9
PCI interface register 11-7
picture 5-2, 11-10
DRAM_BASE updates 11-10
DRAM_CACHEABLE_LIMIT
description table 5-13
picture 5-5
DRAM_LIMIT
description table 5-13
picture 5-2
DSPCPU
addressing modes 3-4
byte ordering 3-2
register model 3-1
software compatibility 3-4
DSPCPU operations
listed al phabetically A-1
listed by function A-2
dspiabs A-23
dspiadd A-24
dspidualabs A-25
dspidualadd A-26
dspidualmul A-27
dspidualsub A-28
dspimul A-29
dspisub A-30
dspuadd A-31
dspumul A-32
dspuquadaddui A-33
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-5
dspusub A-34
dual port 5-4
E
EAV and SAV codes
description 7-5
EAV format 6-5
edge sensitive interrupts 3-10
endian-ness 5-4
endianness 3-2
En ha nced V ide o Ou t 7-1
En ha nced V ide o Ou t U nit
active video definition
picture 7-7
algorithms,overview 7-10
alpha ble ndin g 7-13
block diagram 7-3
CC IR 656 frame t iming
description 7-6
descr i pt i on table 7-6
CCIR 656 line timing
description 7-4
picture 7-5
CCIR 656 pixel timing
description 7-4
picture 7-5
clock syste m7-25
picture 7-3
connection t o vid e o encode r,p ictu r e7-2
connection to video in unit,pictur e7-3
connection,CCIR656,picture 7-2
data streaming 7-23
data trans fe r ti ming 7-9
dds 7-25
DDS and PLL setting,examples 7-25
error conditions 7-23
field definition
picture 7-7
frame definition
picture 7-7
frame timing signals 7-7
functions,summary 7-1
graphics overlay 7-22
graphics overlay formats 7-10
horizontal timing signals 7-7
image ad dr e s si ng 7-22
imag e definitio n
picture 7-7
imag e t im i ng 7-4
interrupts 7-23
message passin g7-23
MMIO registers 7-14
NTSC 7-23
operating modes 7-13
operation,description 7-21
overlay definition
picture 7-7
PAL 7-23
pixel mirro ring 7-11
PLL filter
block diagram 7-25
pll filter 7-25
p rog r e ss iv e sc an 7-6
sum m ar y of fun cti on s 7-1
timing ge ner atio n
description 7-6
timing regi ster
recommended values 7-23
video image data format s7-9
YUV image format 7-9
YUV planar format 7-10
YUV upscaling 7-11
Enhanced Video Out unit
block diagram 7-3
clock system 7-3
interface pins 7-2
EVOEnhanced Video Out Unit 7-1
EVO_CLIP
f iel d de sc r i ption tabl e 7-21
picture 7-20
EVO_CTL
f iel d de sc r i ption tabl e 7-20
picture 7-20
EVO_KEY
f iel d de sc r i ption tabl e 7-21
picture 7-20
EVO_MASK
f iel d de sc r i ption tabl e 7-21
picture 7-20
EVO_SLVDLY
f iel d de sc r i ption tabl e 7-21
picture 7-20
exceptions
definition 3-9
ex pansion ROM base add ress
PCI interface register 11-9
F
fabsval A-38
fabsvalflags A-39
fadd A-40
faddflags A-41
fdiv A-42
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-6 PRELIMINARY SPECIFICATION
fdivflags A-43
feql A-44
feqlflags A-45
fgeq A-46
fgeqflags A-47
fgtr A-48
fgtrflags A-49
filter 5-tap 14-1
algorithm,ICP horizontal 14-22
algorithm,ICP vertical 14-24
coefficient,loading 14-22
horizontal 14-22
horizontal,parameter table 14-23
ICP vertical 14-24
ICP vertical,parameter table 14-24
parameter table,vertical 14-24
polyphase 14-1
SDRAM to SDRAM 14-24
SDRAM to SDRAM,horizontal 14-22
vertical 14-24
with RG B/ YU V conv ersi on 14-25
filtering
horizontal 14-1, 14-12, 14-15
horizontal,ICP 14-6
horizontal,method 14-11
ICP 14-6
ICP,5-tap 14-6
method 14-11
multi-tap 14-6
two dimensional 14-1
vertical 14-1
fleq A-50
fleqflags A-51
fles A-52
flesflags A-53
floati ng poin t
exception flags 3-2
IEEE rounding mode 3-2
representation 3-4
fmul A-54
fmulflags A-55
fneq A-56
fneqflags A-57
four-way LRU 5-11
frame timing signals 7-7
fsign A-58
fsignflags A-59
fsqrt A-60
fsqrtflags A-61
fsub A-62
fsubflags A-63
fullres capture mode
video in unit 6-1
description 6-4
funshift1 A-64
funshift2 A-65
funshift3 A-66
G
ge n era l pur po s e register s 3-1
general purpose timer/coun ter 3-12
Genlock 7-7
Genlock mode 7-8
granularity
memory 12-2
graphics overlay 7-10, 7-22
graphics overlay formats 7-10
grid input 14-7
output 14-7
guarding
definition 3-5
H
h_dspiabs A-67
h_dspidualabs A-68
h_iabs A-69
h_st16d A-70
h_st32d A-71
h_st8d A-72
halfres capture mode
video in unit 6-1
description 6-9
handshake mechanism
JTAG 18-5
HBE 8-7
header type
PCI interface register 11-7
hicycles A-73
hidden concurrency 5-7
hier arc hic al LR U 5-4
highway latency
audio 8-7
horizontal
filtering 14-12
scaling 14-11, 14-15
horizontal filter 14-22
parameter,table 14-23
timing 14-12
horizontal filter to RGB parameter table 14-26
horizontal filtering 14-1, 14-15
horizontal scaling 14-1, 14-15
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-7
horizontal timing signals 7-7
huffman code 15-1
I
I/O b uffer circuits 1-1
I/O op eratio ns
PCI interface 11-2
i2s 8-1
iabs A-74
iadd A-75
iaddi A-76
iavgonep A-77
ibytesel A-78
IC_LOCK_ADDR
descr i pt i on table 5-13
picture 5-10
IC_LOCK_CTL
descr i pt i on table 5-13
picture 5-10
IC_LOCK_SIZE
descr i pt i on table 5-13
picture 5-10
IC_PARAMS
descr i pt i on table 5-13
picture 5-8
IC_PARAMS fields 5-8
ICLEAR
picture 3-11
iclipi A-79
iclr 5-9, A-80
ICP algorithms 14-6
alpha ble ndin g 14-9
bandwidth requirements 14-1
block diagram 14-1
chroma keying 14-9
coefficients,table 14-22
color keying 14-9
control wo rd format 14-23
dithering 14-10
filter coefficient, loading 14-22
filter SDRA M to SDRAM 14-22
horizontal filter control word 14-27
horizontal filter parameter table 14-22
horizontal filter to RGB parameter table 14-26
horizontal filter with conve rsion 14-25
horizontal filter,alg orithm 14-22, 14-25
horizontal filter,table 14-23
horizontal filtering 14-6, 14-15
horizontal scaling 14-15
imag e f o rma t s 14-3
imag e overlay f or m a ts 14-5
image overlay formats tabl e14-5
image resizing 14-6
image scaling 14-6
intern al structu re 14-1
lines m irrorin g 14-15
microprogram 14-16
missing pi xels,filter ing 14-6
move image 14-1
operation 14-16
output formats 14-5
output sc aling,calculation method 14-8
overlay 14-9
parameter tables 14-22
PCI block timi ng 14-16
pixel mirro ring 14-6
pr io rity de lay 14-20
programming 14-16
registers 14-17
sc aling outp u t resolutio n14-7
SDRAM ti ming 14-15
status register, P D field 14-20
upscaling example 14-7
vertic al fi lter 14-24
vertical filter algori thm 14-24
vertic al fi lter contr o l wor d 14-25
vertical filter parameter table 14-24
vertic al filte r in g 14-6
YUV formats 14-3
YUV sequence counter 14-15
YUV to RGB conversion 14-9
ICP (image co-processor) 14-1
ICP_DP, MMIO register 14-17
ICP_DR, MMIO register 14-17
ICP_MIR, MMIO register 14-17
ICP_MPC, MMIO register 14-17
ICP_SR, MMIO register 14-17
ident A-81
IEEE 1149.1 1-1
IEEE rounding mode 3-2
ieql A-82
ieqli A-83
ifir16 A-84
ifir8ii A-85
ifir8ui A-86
ifixieee A-87
ifixieeeflags A-88
ifixrz A-89
ifixrzflags A-90
iflip A-91
ifloat A-92
ifloatflags A-93
ifloatrz A-94
ifloatrzflags A-95
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-8 PRELIMINARY SPECIFICATION
igeq A-96
igeqi A-97
igtr A-98
igtri A-99
iimm A-100
iis 8-1
ijmpf A-101
ijmpi A-102
ijmpt A-103
ild16 A-104
ild16d A-105
ild16r A-106
ild16x A-107
ild8 A-108
ild8d A-109
ild8r A-110
ileq A-111
ileqi A-112
iles A-113
ilesi A-114
image
ICP input format 14-3
pro c essing algo r it h m s14-6
resizing 14-6
scaling 14-6
scaling factor rang e14-3
si ze r ange 14-3
Image co-processor
block diagram 14-1
imag e co -processor 14-1
block diagram 14-2
imag e f o rma t s 14-3
imag e overlay 14-1, 14-5, 14-9
imag e overlay f or m a ts
of ICP,tab le 14-5
image pr o c es si ng
bandwidth 14-1
IMASK
picture 3-11
imax A-115
imin A-116
imul A-117
imulm A-118
ineg A-119
ineq A-120
ineqi A-121
initialization
DRAM memory syste m12-6
inst ruction cache 5-10
initialization,cache 5-8
inonzero A-122
input format
ICP 14-3
input grid
re la tin g to ou tput grid 14-7
instruction br eakpoi nt 3-13
instruction cache 5-8
address mapping 5-8
picture 5-9
coherency 5-11
in i tia li zati o n an d bo ot 5-10
LRU r eplacem ent 5-11
per f or m a nc e ev al uati o n su pp ort 5-12
instruction cache parameters 5-8
instruction cache set 5-8
instruction cache tag 5-8
instructi on cache ,sum mar y 5-8
INT_CTL
PCI interface MMIO register 11-15
picture 3-12, 11-10
integer representatio n3-4
interleaving
of SDRAM 12-6
interrupt line
PCI interface register 11-9
interrupt mask 3-10
interrupt mode 3-10
interrupt pin
PCI interface register 11-9
interrupt priority 3-10
interrupt vectors 3-9
interrupts 3-9
definition 3-9
DS PC PU enabl e bit 3-2
inters pers ed s ampl ing 6-5
intervals
refresh 12-6
INTVEC[31:0]
picture 3-9
IO_ADR
PCI interface MMIO register 11-13
picture 11-10
IO_CTL
PCI interface MMIO register 11-13
picture 11-10
IO_DATA
PCI interface MMIO register 11-13
picture 11-10
IPENDING
picture 3-11
IS 1117 2-2 references 15-3
IS 1381 8-2 references
table 15-3
ISETTING0
picture 3-10
ISETTING1
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-9
picture 3-10
ISETTING2
picture 3-10
ISETTING3
picture 3-10
isub A-123
isubi A-124
izero A-125
J
jmpf A-126
jmpi A-127
jmpt A-128
JTAG
additional registers
picture 18-4
BYPASS instruction 18-2
communication protoco l18-5
examp le datat t ransfer 18-5
EXTEST instruction 18-2
instruction encodings
table 18-2
instructions
SEL_DATA_IN 18-5
SEL_DATA_OUT 18-5
SEL_IFULL_IN 18-5
SEL_JTAG_CTRL 18-5
SEL_OFULL_OUT 18-5
MACRO instruction 18-3
MMIO registers
table 18-4
overview 18-1
race condition,avoid 18-5
RESET instruction 18-2
SAMPL E/PRELO AD instruction 18-2
SEL_DATA_IN instructio n 18-2
SEL_DATA_OUT instruction 18-3
SEL_IFULL _IN inst ruction 18-3
SEL_JTAG_CTRL instruction 18-3
SEL_OFULL_OUT instruction 18-3
system components 18-3
TAP controller desc ription 18-1
TAP controller state diagram,pic ture 18-2
test access por t 18-1
test clock 18-1, 18-3
test data in 18-1
test data out 18-1
test mode sele ct 18-1
virtual registers 18-4
JTAG_CTRL
register 18-4
JTAG_DATA_IN
register 18-4
JTAG_DATA_OUT
register 18-4
JTAG_IFULL_IN 18-4
JTAG_OFULL_OUT 18-4
K
keying
chroma 14-9
color 14-9
L
latency timer
PCI interface register 11-7
latency,memory operation 5-8
ld32 A-129
ld32d A-130
ld32r A-131
ld32x A-132
level sensitive interrupts 3-10
lines mirroring 14-15
load coefficients parameter table 14-22
load store ordering 3-3, 3-5, 3-7, 5-5, 17-4, 17-6
locking conditions 5-4
lock ing range 5-4
LRU bit definition 5-12
LRU bit definitions,picture 5-12
LRU bit update ordering 5-12
LRU initializ ation 5-12
LRU re placement,cac he 5-11
LRU, hierarc hical 5-4
LRU,four-way 5-11
LRU,two-way 5-11
lsl A-133
lsli A-134
lsr A-135
lsri A-136
M
macro block heade r15-1
macroblock header, standard references 15-3
ma in im age 14-9
max_lat
PCI interface register 11-9
Maximum Ratings 1-11
MEM_EVENTS
description table 5-13
picture 5-12
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-10 PRELIMINARY SPECIFICATION
memory
oper ati on order in g 5-7
memory data formats
audio in un it 8-4
audio ou t uni t 9-7
memory format
audio 8-4
memory hole 5-5
memory map 3-7
picture 3-7
memory mapped devices 3-7
mergelsb A-138
mergemsb A-139
message passing mode
video in un it
description 6-11
message-passing mode
video in un it 6-1
description 6-11
min_gnt
PCI interface register 11-9
mirroring
lines 14-15
pixels 14-12
misaligned
store 3-3
miss proc essing,order 5-9
MM_A[11:0]
descr i pt i on table 12-5
MM_CAS#
descr i pt i on table 12-5
MM_CKE[3:0]
descr i pt i on table 12-5
MM_CLK[1:0]
descr i pt i on table 12-5
MM_CS#[3:0]
descr i pt i on table 12-5
MM_DQ[31:0]
descr i pt i on table 12-5
MM_DQM
descr i pt i on table 12-5
MM_RAS#
descr i pt i on table 12-5
MM_WE#
descr i pt i on table 12-5
mmio 3-7
MMIO aperture
picture 3-8
MMIO refer e nc es ,n on - c ac he d 5-8
MMIO registers
AI_BASE1
picture 8-5
AI_BASE2
picture 8-5
AI_CONTROL
f iel d de sc r i ption tabl e 8-6
AI_CTL
picture 8-5
AI_FRAMING
picture 8-5
AI_FREQ
picture 8-5
AI_SERIAL
picture 8-5
AI_SIZE
picture 8-5
AI_STATUS
f iel d de sc r i ption tabl e 8-6
picture 8-5
AO_BASE1
picture 9-8
AO_BASE2
picture 9-8
AO_CC
picture 9-8
AO_CFC
picture 9-8
AO_CONTROL
f iel d de sc r i ption tabl e 9-9, 9-10
AO_CTL
picture 9-8
AO_FRAMING
picture 9-8
AO_FREQ
picture 9-8
AO_SERIAL
picture 9-8
AO_SIZE
picture 9-8
AO_STATUS
f iel d de sc r i ption tabl e 9-9
picture 9-8, 16-2
BDATAAHIGH
picture 3-14
BDATAALOW
picture 3-14
BDATAMASK
picture 3-14
BDATAVAL
picture 3-14
BDCTL
picture 3-14
BICTL
picture 3-14
BINSTHIGH
picture 3-14
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-11
BINSTLOW
picture 3-14
BIU_CTL 11-11
picture 11-10
BIU_STATUS 11-11
picture 11-10
cache registers summar y5-13
CONFIG_ADR 11-12
picture 11-10
CONFIG_CTL 11-13
picture 11-10
CONFIG_DATA 11-13
DC_LOCK_ADDR
descr i pt i on table 5-13
picture 5-5
DC_LOCK_CTL
descr i pt i on table 5-13
picture 5-5
DC_LOCK_SIZE
descr i pt i on table 5-13
picture 5-5
DC_PARAMS 5-3
descr i pt i on table 5-13
fields 5-3
picture 5-3
DEST_ADR 11-14
picture 11-10
DMA_CTL 11-14
picture 11-10
DRAM_BASE 11-9
descr i pt i on table 5-13
picture 5-2, 11-10
DRAM_CACHEABLE_LIMIT
descr i pt i on table 5-13
picture 5-5
DRAM_LIMIT
descr i pt i on table 5-13
picture 5-2
EVO_CLIP
picture 7-20
EVO_CTL
picture 7-20
EVO_KEY
picture 7-20
EVO_MASKK
picture 7-20
EVO_SLVDLY
picture 7-20
for VLD 15-4
IC_LOCK_ADDR
descr i pt i on table 5-13
picture 5-10
IC_LOCK_CTL
description table 5-13
picture 5-10
IC_LOCK_SIZE
description table 5-13
picture 5-10
IC_PARAMS
description table 5-13
fields 5-8
picture 5-8
ICLEAR
picture 3-11
ICP_DP 14-17
ICP_DR 14-17
ICP_MIR 14-17
ICP_MPC 14-17
ICP_SR 14-17
IMASK
picture 3-11
INT_CTL 11-15
picture 3-12, 11-10
INTVEC[31:0]
picture 3-9
IO_ADR 11-13
picture 11-10
IO_CTL 11-13
picture 11-10
IO_DATA 11-13
picture 11-10
IPENDING
picture 3-11
ISETTING0
picture 3-10
ISETTING1
picture 3-10
ISETTING2
picture 3-10
ISETTING3
picture 3-10
JTAG registers 18-4
JTAG_CTRL 18-4
JTAG_DATA_IN 18-4
JTAG_DATA_OUT 18-4
MEM_EVENTS
description table 5-13
picture 5-12
MM_CONFIG
picture 12-4
MMIO_BASE 11-9
description table 5-13
picture 11-10
of Enha nced Vi deo Out Unit 7-14
of IC P 14-17
PCI interface
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-12 PRELIMINARY SPECIFICATION
accessibility 11-11
PCI_ADR 11-12
picture 11-10
PCI_DATA 11-12
picture 11-10
PLL_RATIOS
picture 12-4
SCR_ADR
picture 11-10
se tu p of SSI_C TL 17-6
SPDO_BASE1
picture 10-5
SPDO_BASE2
picture 10-5
SPDO_CTL
picture 10-5
SPDO_FREQ
picture 10-5
SPDO_SIZE
picture 10-5
SPDO_STATUS
picture 10-5
SPDO_TSTAMP
picture 10-5
SRC_ADR 11-14
SSI_CSR
fields description 17-11
SSI_CTL
fields description 17-9
su m mar y table B-1
TCTL
picture 3-13
TMODULUS
picture 3-13
TVALUE
picture 3-13
VI_BASE1
alignment 6-11
picture 6-10
VI_BASE2
alignment 6-11
picture 6-10
VI_CAP_SIZE
picture 6-8
VI_CAP_START
picture 6-8
VI_CLOCK
picture 6-8, 6-10
VI_CTL
picture 6-8, 6-10
VI_SIZE
picture 6-10
VI_STATUS
picture 6-8, 6-10
VI_U_BASE_ADR
picture 6-8
VI_UV_DELTA
picture 6-8
VI_V_BASE_ADR
picture 6-8
VI_Y_BASE_ADR
picture 6-8
VI_Y_DELTA
picture 6-8
video in, vi ew in raw and message passing mode
picture 6-10
video in,YUV capture 6-8
V LD unit,picture 15-6
VO_CLOCK
common valu es 7-23
picture 7-15
VO_CTL
f ields des cription table 7-17
picture 7-15
VO_FIELD
default values 7-23
picture 7-15
VO_FRAME
default values 7-23
picture 7-15
VO_IMAGE
default values 7-23
picture 7-15
VO_LINE
default values 7-23
picture 7-15
VO_OLADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_OLHW
picture 7-15
VO_OLSTART
picture 7-15
VO_STATUS
picture 7-15
VO_UADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_VADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_VUF
picture 7-15
VO_YADD
picture 7-15
VO_YOLF
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-13
fie ld description tabl e7-19
picture 7-15
VO_YTHR
picture 7-15
VO_YUF
fie ld description tabl e7-19
MMIO_BASE
descr i pt i on table 5-13
PCI interface MMIO register 11-9
PCI interface register 11-7
picture 11-10
MMIO_BASE updates 11-10
MPEG bitstream 15-1
MPEG-1 macroblock header 15-3
MP EG -1 m ac rob lock h ea der ,o utpu t form at 15-4
MPEG-1 stan dard referenc es 15-3
MPEG-2 macroblock header 15-3
MP EG -2 m ac rob lock h ea der ,o utpu t form at 15-2
MP EG - 2 st an dar d
references
table 15-3
mult i- ta p FIR fil te ring 14-6
N
New features 1-1
no n ca ch ea ble r eg io n 5-5
noncachable region 5-3
non- int er lac ed s ca n 7-6
non- m ask able interr upt 3-10
nop A-140
NTSC 7-23
O
offset byte in set 5-8
operation ordering,special 5-7
operations
DSPCPU A-1, A-2
order,miss processing 5-9
ordering
memory operations 5-7
Ordering Informa tion 1-10
ordering,special operation 5-7
output formats
ICP 14-5
output grid
relating to input grid 14-7
output scaling
calculation 14-8
overlap c onfiguration of w indo w s14-1
overlay
blending 14-9
of image 14-1
overlay formats
of IC P 14-5
overlay image 14-9
ov erlay, image 14-5, 14-9
overlays
computer generated 14-9
ove r s am p lin g A /D co nv erter 8-2
P
pack16lsb A-141
pack16msb A-142
package out line 1-10
package,BGA package 1-10
packbytes A-143
PAL 7-23
parameter table
ICP horizontal filter 14-23
parameter tables
horizontal filter to RGB 14-26
ICP 14-22
vertic al fi lter 14-24
Part Numbe r 1-10
partial words 5-4
PCI aperture 11-2
output block timing 14-16
space 11-2
PCI aperture 5-5
PCI configuration space 11-3
PCI header 11-3
PCI interface
char acteristics ove rview 11-1
concurrency 11-3
configuration header 11-3
configuration operations 11-2
configuration registers 11-3
DMA operations 11-2
I/O operations 11-2
initiator 11-2
limitations 11-17
ordering 11-3
priorities 11-3
registers
base addresses 11-7
built-in self test 11-7
cache line size 11-7
class code 11-6
command
fields 11-5
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-14 PRELIMINARY SPECIFICATION
command I D 11-3
device ID 11-3
DRAM_BASE 11-7
expansion ROM base address 11-9
header type 11-7
interrupt line 11-9
interrupt pin 11-9
laten c y tim e r 11-7
max_lat 11-9
min_gnt 11-9
MMIO_BASE 11-7
revision ID 11-6
status 11-5
fields 11-6
vendor ID 11-3
single word load/store 11-2
target of op erations 11-3
PCI references,non-cached 5-8
PCI_ADR
PCI interface MMIO register 11-12
picture 11-10
PCI_DATA
PCI interface MMIO register 11-12
picture 11-10
PCSW
definition 3-2
performance events,cach e5-13
Philips Pa rt N um be r 1-10
pins AI_OSCLK
descr i pt i on table 8-1
AI_SCK
descr i pt i on table 8-1
AI_SD
descr i pt i on table 8-1
AI_WS
descr i pt i on table 8-1
AO_OSCLK
descr i pt i on table 9-2
AO_SCK
descr i pt i on table 9-2
complete list 1-2
DC/AC Characteristic s1-11
I/O c ircu it summary 1-1
MM_CAS#
descr i pt i on table 12-5
MM_CLK[1:0]
descr i pt i on table 12-5
MM_CS#[3:0]
descr i pt i on table 12-5
MM_DQ[31:0]
descr i pt i on table 12-5
MM_DQM
description table 12-5
MM_RAS#
description table 12-5
MM_WE#
description table 12-5
package 1-10
SPDO
description table 10-1
timing 1-18, 1-19, 1-20
VI_CLK
description table 6-2
VI_DATA[7:0]
description table 6-2
VI_DATA[8] 6-11
VI_DATA[9:8]
description table 6-2
VI_DATA[9] 6-11
VI_DVALID
description table 6-2
VO_CLK
description table 7-3
VO_DATA[7:0]
description table 7-3
VO_IO1
description table 7-3
VO_IO2
description table 7-3
pixel mirroring 14-6
missing 14-6
shift bypassing for downscaling 14-8
transformation,scaling 14-7
pixel mirro ring 7-11
pixels
mirroring 14-12
planar
da ta format 14-3
PLL filter
of video ou t7-25
polyphase filter 14-1
power down mode
DR AM mem o ry syste m 12-7
of SDRAM 12-7
pref A-144
pref16x A-145
pref32x A-146
prefd A-147
prefr A-148
pr io rity de lay 14-20
Progr essive scan 7-6
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-15
Q
quadavg A-149, A-150
quadumulmsb A-151, A-152
quasi-dual 5-4
R
rank size
vs. address mapping 12-5, 12-6
raw capture m o des
video in un it
description 6-10
raw10s capture mode
video in un it 6-1
raw10u c aptur e mode
video in un it 6-1
raw8 capture mode
video in un it 6-1
rdstatus A-153
result format 5-6
rdstatus operation 5-6
result format picture 5-6
rdtag A-154
result format 5-6
rdt ag operation 5-6
result format picture 5-6
readdpc A-155
readpcsw A-156
readspc A-157
refresh
DRAM memory syste m12-6
intervals 12-6
region
noncachable 5-3
region,non-cacheable 5-5
register model 3-1, 4-1
replacement 5-4
representation
boolean 3-3
floati ng poin t 3-4
integer 3-4
rescaling of images 14-1
resizing
horizontal 14-1
in IC P 14-6
vertical 14-1
revision ID
PC I register 11-6
RGB conversion 14-1
rol A-158
roli A-159
run -le vel ou tput dat a 15-1
S
sample rate 8-1, 8-2
SAV and EAV codes
description 7-5
description table 7-6
format
picture 7-5
SAV format 6-5
scaling 14-6
algorithm 14-8
horizontal 14-1, 14-11, 14-15
horizontal,method 14-11
method 14-11
range 14-3
shift bypassing 14-8
two dimensional 14-1
vertical 14-1, 14-13
SDRAM 12-2
supported devices 12-2, 13-7
S D RAM memory sys tem
timing budget 12-8
sequence counter
YUV 14-15
serial CCIR656 7-2
serial frame 8-1, 8-3
Seri al Interface 17-1
sex16 A-160
sex8 A-161
SGRAM 12-2
supported devices 12-2, 13-7
size of image,range 14-3
software compatibility 3-4
software interrupt 3-11
SPCdefinition 3-3
SPDO
description table 10-1
SPDO_BASE1
picture 10-5
SPDO_BASE2
picture 10-5
SPDO_CTL
picture 10-5
SPDO_FREQ
picture 10-5
SPDO_SIZE
picture 10-5
SPDO_STATUS
picture 10-5
SPDO_TSTAMP
picture 10-5
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-16 PRELIMINARY SPECIFICATION
specu lativ e load s 3-3, 3-5, 3-7, 5-5, 17-4, 17-6
SRC_ADR
PCI interface MMIO register 11-14
picture 11-10
SSI_CTL
field descriptio n17-9
st16 A-162
st16d A-163
st32 A-164
st32d A-165
st8 A-166
st8d A-167
stall,CPU 5-8
status
PCI interface register 11-5
st atus op erati ons,ca che 5-6, 5-7
stereo 8-1
st ere o A /D co nver t er 8-1
storemisaligned 3-3
subsampling
horizontal 14-1
vertical 14-1
Synchronous Serial Interface 17-1
synthesizer 8-2
synthesizer,digital 7-3
T
tag operation s 5-6, 5-7
TAP controller 18-1
description 18-1
TAP,test access port 18-1
TCTL
picture 3-13
termination
guidelines 12-7
test access por t 18-1
TFE definition 3-3
timer 3-12
timing 1-18
SDRAM block 14-15
vertical filter 14-15
timing ref erence codes 6-5
TMODULUS
picture 3-13
translucent
background 14-9
foreground 14-9
TVALUE
picture 3-13
two-way LRU 5-11
U
ubytesel A-168
uclipi A-169
uclipu A-170
ueql A-171
ueqli A-172
ufir16 A-173
ufir8uu A-174
ufixieee A-175
ufixieeeflags A-176
ufixrz A-177
ufixrzflags A-178
ufloat A-179
ufloatflags A-180
ufloatrz A-181
ufloatrzflags A-182
ugeq A-183
ugeqi A-184, A-186
ugtr A-185
uimm A-187
uld16 A-188
uld16d A-189
uld16r A-190
uld16x A-191
uld8 A-192
uld8d A-193
uld8r A-194
uleq A-195
uleqi A-196
ules A-197
ulesi A-198
ume8ii A-199
ume8uu A-200
umul A-202
umulm A-203
uneq A-204
uneqi A-205
upsampling
horizontal 14-1
vertical 14-1
upscaling 7-11, 14-1
V
V.34 interface
block diagram 17-2, 17-3, 17-4
external pins,table 17-1
prog ramming model 17-8
setup of S SI_ C TL registe r17-5
te st m o des 17-8
transmitter logic model 17-5
used as general purpose I/O
ABC HEDFGIJKLMNOPQRSTUVWXYZ
PRELIMINARY SPECIFICATION Index-17
17-1, 17-2, 17-3
V.34 mode m 17-1
vector e d interrup t s 3-9
vendor ID
PCI interface register 11-3
vertical filter
ICP 14-24
verti ca l fil ter param e ter tabl e 14-24
vertical filtering 14-1
ve rtical sc ali n g 14-1, 14-13
VI_BASE1
alignment 6-11
picture 6-10
VI_BASE2
alignment 6-11
picture 6-10
VI_CAP_SIZE
picture 6-8
VI_CAP_START
picture 6-8
VI_CLK
descr i pt i on table 6-2
VI_CLOCK
picture 6-8, 6-10
VI_CTL
picture 6-8, 6-10
VI_DATA
VI_DATA[8] 6-11
VI_DATA[9] 6-11
VI_DATA[7:0]
descr i pt i on table 6-2
VI_DATA[9:8]
descr i pt i on table 6-2
VI_DVALID
descr i pt i on table 6-2
VI_SIZE
picture 6-10
VI_STATUS
picture 6-8, 6-10
VI_U_BASE_ADR
picture 6-8
VI_UV_DELTA
picture 6-8
VI_V_BASE_ADR
picture 6-8
VI_Y_BASE_ADR
picture 6-8
VI_Y_DELTA
picture 6-8
vi ctim of re placem ent 5-4
video im age da t a fo r ma ts 7-9
video in un it
captur e parameters
explanation 6-6
picture 6-5
clock generator 6-4
clocking modes 6-4
common source par ameter s 6-6
connected to 10bit A/D converter
picture 6-4
connected to 8bit CCIR656 camera
picture 6-3
connected to video out
picture 6-3
connected to video recorder
picture 6-3
co-sited sampling 6-4
diagnostic mode 6-2
format of SAV and EAV codes 6-5
full res capture mod e6-1
description 6-4
halfres capture mode 6-1
description 6-9
halfres co-sited sample capture
picture 6-9
halfre s interspers ed samp le capture
picture 6-9
halfre s planar memory form at
picture 6-9
highway latency requirements 6-13
highway latency,HBE description 6-13
interface pins
description table 6-2
inters pers ed s ampl ing 6-5
mess age pa ss ing
major states diagram 6-12
mess age pa ss ing m od e
description 6-11
example signal diagram 6-12
mess age-pass in g mode 6-1
description 6-11
power down 6-2
raw and message passing modes
MMIO register view , pi cture 6-10
raw capture modes
description 6-10
raw mode ,major states,diagram 6-11
ra w 10s capture mod e6-1
raw10u capture mode 6-1
ra w 8 ca ptur e m od e 6-1
reset 6-2
YUV 4:2:2 planar memory format
picture 6-7
YUV capture view of MMIO registers 6-8
virtual regi sters 18-4
VLD
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-18 PRELIMINARY SPECIFICATION
command regist er 15-1
command register,description 15-7
commands 15-1
CPU interaction 15-2
error handling,description 15-8
flush output command 15-1
input,description 15-2
interrupt description 15-8
introduction 15-1
MMIO registers 15-4
picture 15-6
operational registers,description 15-7
output,description 15-3
parse command 15-1
par s ing ac tio n15-2
pi ct ur e in f o r e gister ,des cripti o n 15-8
quantizer scale register,description 15-7
reset command 15-1
reset description 15-8
se arch c ommand 15-1
s hift command 15-1
shift register,description 15-7
software reset procedure 15-8
st op r eas ons 15-1
VO Video Out Unit 7-1
VO_CLK
descr i pt i on table 7-3
VO_CLOCK
co m mo n va l u es 7-23
fie ld description tabl e7-18
picture 7-15
VO_CTL
fields 7-17
picture 7-15
VO_DATA[7:0]
descr i pt i on table 7-3
VO_FIELD
default values 7-23
fie ld description tabl e7-18
picture 7-15
VO_FRAME
default values 7-23
fie ld description tabl e7-18
picture 7-15
VO_IMAGE
default values 7-23
fie ld description tabl e7-19
picture 7-15
VO_IO1
descr i pt i on table 7-3
VO_IO2
descr i pt i on table 7-3
VO_LINE
default values 7-23
f iel d de sc r i ption tabl e 7-18
picture 7-15
VO_OLADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_OLHW
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_OLSTART
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_STATUS
f iel d de sc r i ption tabl e 7-16
picture 7-15
VO_UADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_VADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_VUF
picture 7-15
VO_YADD
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_YOLF
f iel d de sc r i ption tabl e 7-19
picture 7-15
VO_YTHR
f iel d de sc r i ption tabl e 7-7, 7-19
picture 7-15
VO_YUF
f iel d de sc r i ption tabl e 7-19
W
write misses 5-4
writedpc A-206
writepcsw A-207
writespc A-208
Y
YUVfor m at s of IC P14-3
sequence counter 14-15
YUV capture
view of video in MMIO registers 6-8
YUV conversion 14-1
YUV image format 7-9
ABC HEDFGIJKLMNOPQRSTUVWXYZ
Index-20 PRELIMINARY SPECIFICATION
© Philips El ectroni cs N.V. SCA
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Internet: http://www.semiconductors.philips.com
2001 69
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India: Ph ilips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Develop ment Corporation, Semic onductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 7940080
Ireland: Newstead, Clonskeagh, DUBLIN14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPACElectronics, 7KehilatSalonikiSt, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-
8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No.76JalanUniversiti, 46200PETALINGJAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-
5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealan d: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo V illage, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
So u th A f r i ca : S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th fl oor, 04547-
130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2Sanpavuth-
Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 8126 0Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semic onductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
Date of release: 2001 Oct 12 Document order number: xxxx xxx xxxxx
2001 Oct 12
Philips Se m ico nducto rs Produ ct S pe cifi ca tion
Media Processor PNX1300/01/02/11
