SDLS965 − O C TOBER 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSingle 5-V Supply
D±100-mV Sensitivity
DFor Application as:
− Single-Ended Line Receiver
− Gated Oscillator
− Level Comparator
DAdjustable Reference Voltage
DTTL Outputs
DTTL-Compatible Strobe
DDesigned for Party-Line (Data-Bus)
Applications
DCommon Reference-Voltage Pin
DCommon Strobe
description/ordering information
This device consists of a dual single-ended line receiver with TTL-compatible strobes and outputs. The
reference voltage (switching threshold) is applied externally and can be adjusted from 1.5 V to 3.4 V, making
it possible to optimize noise immunity for a given system design. Due to the low input current (less than 100 µA),
the device is suited ideally for party-line (data-bus) systems.
The SN74LS2323 has a common reference-voltage pin and a common strobe.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
0°C to 70°C
SOIC − D
Tube SN74LS2323D
LS2323
0°C to 70°CSOIC − D Tape and reel SN74LS2323DR LS2323
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each receiver)
LINE INPUT STROBE OUTPUT
≤(VREF − 100 mV) L H
≥(VREF + 100 mV) X L
X H L
H = high level, L = low level, X = irrelevant
Copyright 2004, Texas Instruments Incorporated
!" #$
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
1OUT
COMSTRB
1LINE
GND
VCC
2OUT
COMREF
2LINE
D PACKAGE
(TOP VIEW)
SDLS965 − O C TOBER 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2
3
6
5
1
7
1OUT
2OUT
COMSTRB
1LINE
COMREF
2LINE
_
+
+
_
schematic (each receiver)
750 Ω
Line
VREF
1.8 kΩ
VCC VCC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
1.8 kΩ
6 kΩ
5.5 kΩ
3.5 kΩ
2.5 kΩ
1.5 kΩ
20 kΩ
10 kΩ50 Ω
15 kΩ25 kΩ
3 kΩ
OU
T
COMSTRB
SDLS965 − O C TOBER 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage, VREF 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line input voltage range with respect to GND −2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line input voltage with respect to VREF ±5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strobe input voltage, VI(S) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2) 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
Vref Reference input voltage 1.8 ‡V
VI(L) High-level line input voltage 0 VCC − 1 V
VI(S) High-level strobe input voltage 0 7 V
TAOperating free-air temperature range 0 70 °C
‡Max = VCC−1.5 V u VREF t 3.4 V
SDLS965 − O C TOBER 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VCC = 5 V ±10%, VREF = 1.5 V to 3.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VIH(L)
High-level line input voltage
VI(S) = 0.8 V, IOL = 12 mA, VREF = 2.5 V,
VOL ≤ 0.6 V VCC = 4.5 V 2.62 6
V
VIH(L) High-level line input voltage VI(S) = 0.8 V, IOL = 16 mA, VREF = 3.4 V,
VOL ≤ 0.5 V VCC = 5.5 V 3.5 7 V
VIL(L)
Low-level line input voltage
VI(S) = 0.8 V, IOH = −0.4 mA,VREF = 2.5 V,
VOH ≥ 2 V VCC = 4.5 V −2 2.38
V
VIL(L) Low-level line input voltage VI(S) = 0.8 V, IOH = −0.4 mA,VREF = 3.4 V,
VOH ≥ 3.2 V VCC = 5.5 V −2 3.3 V
VIH(S) High-level output control input voltage VI(L) = 1.8 V, VREF = 2.5 V, VO ≤ 0.4 V VCC = 4.5 V 2 V
VIL(S) Low-level output control input voltage VI(L) = 1.8 V, VREF = 2.5 V, VO ≥ 2.4 V VCC = 4.5 V 0.8 V
VI(L) = 1.4 V, VI(S) = 0.8 V, IOH = −1 mA,
VCC = 4.5 V 2
V
OH
High-level output voltage VI(L) = 1.4 V, VI(S) = 0.8 V, IOH = −1 mA
,
VREF = 2.5 V
VCC = 5 V 2.7 V
VOH
High-level output voltage
VREF = 2.5 V
VCC = 5.5 V 2.7
V
VCC = 4.5 V,
IOL = 16 mA 0.6
VOL Low-level output voltage VI(L) = 3.8 V, VI(S) = 0.8 V, VREF = 2.5 V VCC = 5 V,
IOL = 24 mA 0.5 V
VCC = 5.5 V,
IOL = 24 mA 0.5
IIH(S)
High-level input current
VI(L) = 3.8 V, VREF = 2.5 V
VCC = 5.5 V,
VI(S) = 2.4 V 20
A
IIH(S) High-level input current VI(L) = 3.8 V, VREF = 2.5 V VCC = 5.5 V,
VI(S) = 7 V 100 µA
IIH(L)
High-level input current
VI(S) = 2.4 V, VREF = 2.5 V
VCC = 5 V,
VI(L) = 5 V 100 µA
IIH(L) High-level input current VI(S) = 2.4 V, VREF = 2.5 V VCC = 5 V,
VI(L) = 5.5 V 2 mA
IIH(REF) High-level input current VI(S) = 2.4 V, VREF = 3.4 V VCC = 5.5 V,
VI(L) = 2.5 V 500 µA
IIL(S) Low-level input current VI(L) = 1.8 V, VREF = 0.1 V VCC = 5.5 V,
VI(S) = 0.4 V −400 µA
IIL(L) Low-level input current at Line input VI(L) = 0.1 V, VREF = 1.8 V VCC = 5.5 V,
VI(S) = 0.4 V −100 µA
IIL(REF) Low-level input current at REF pin VI(L) = 1.8 V, VREF = 0.1 V VCC = 5.5 V,
VI(S) = 0.4 V −100 µA
IOS Short-circuit output current‡VI(L) = 1.8 V, VREF = 2.8 V VCC = 5.5 V
VI(S) = 0.4 V −30 −130 mA
ICCH Supply current, output high VI(S) = 0, VCC = 5.5 V
VI(L) = VREF − 100 mV 12 mA
ICCL Supply current, output low VI(S) = 0, VCC = 5.5 V
VI(L) = VREF + 100 mV 16 mA
†Only one output should be shorted at a time, and duration of the short circuit should not exceed one second.
SDLS965 − O C TOBER 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V ±10%, VREF = 2.5 V, TA = 0°C to 70°C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tPLH(L) Propagation delay time, low- to high-level output from LINE CL = 50 pF, RL = 500 Ω,
See Figure 1 10 25 35 ns
tPHL(L) Propagation delay time, high- to low-level output from LINE CL = 50 pF, RL = 500 Ω,
See Figure 1 10 25 35 ns
tPLH(S) Propagation delay time,
low- to high-level output from COMSTRB CL = 50 pF, RL = 500 Ω,
See Figure 1 11 22 ns
tPHL(S) Propagation delay time,
high- to low-level output from COMSTRB CL = 50 pF, RL = 500 Ω,
See Figure 1 8 15 ns
†All typical values are at VCC = 5 V, TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr and tf ≤ 2 ns, and
duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. All diodes are 1N914 (or equivalent).
D. The outputs are measured one at a time, with one input transition per measurement.
VOLTAGE WAVEFORMS
tPLH(S
)
tPLH(L)
3 V
2 V
3 V
0 V
VOH
VOL
tPHL(L)
OUTPUT
D.U.T.
TEST CIRCUIT
T.P.
ÎÎÎ
tPHL(S)
COMSTRB
LINE2.5 V
0.8 V 2 V 0.8 V 2 V
1.5 V 1.5 V
CL = 50 pF
VCC
500 W
Figure 1. Load Circuit and Voltage Waveforms
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS2323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS2323DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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