ACPL-M21L, ACPL-021L, ACPL-024L,
ACPL-W21L and ACPL-K24L
Low Power, 5 MBd Digital CMOS Optocoupler
Data Sheet
A 0.1 μF bypass capacitor must be connected between pins Vdd and GND
TRUTH TABLE (POSITIVE LOGIC)
LED VO
ON HIGH
OFF LOW
Features
• CMOS output
• Wide supply voltage: 2.7 V – 5.5 V
• Low power supply current IDD: 1.1 mA/channel max.
• Low forward current IF: 1.6 mA min
• Speed: 5 MBd typ
• Pulse width distortion (PWD): 200 ns max
• Propagation delay skew (tpsk): 220 ns max
• Propagation delay (tp): 250 ns max
• Common mode rejection: 25 kV/μs min at VCM = 1000 V
• Hysteresis: 0.2 mA typ
• Temperature range: -40 °C to 105 °C
• Safety and regulatory approvals
– UL 1577 recognized – 3750 Vrms for 1 minute for
ACPL-M21L/021L/024L and 5000 Vrms for 1 minute
for ACPL-W21L/K24L
– CSA Approval
– IEC/EN 60747-5-5, Approval for Reinforced Insulation
Applications
• Low isolation of high speed logic systems
• Computer peripheral interface
• Microprocessor system interface
• Ground loop elimination
• Pulse transformer replacement
• High speed line receiver
• Power control systems
Description
ACPL-M21L (single channel SO-5 package), ACPL-021L
(single channel SO-8 package), ACPL-024L (dual channel
SO-8 package), ACPL-W21L (single channel stretched SO-6
package) and ACPL-K24L (dual channel stretched SO-8
package) are optically-coupled logic gates. The detector
IC has CMOS output stage and optical receiver input stage
with built-in Schmitt trigger to provide logic-compatible
waveforms, eliminating the need for additional wave-
shaping.
An internal shield on the ACPL-M21L/021L/024L/W21L/
K24L guarantees common mode transient immunity of 25
kV/µs at a common mode voltage of 1000 V. The ACPL-x2xL
optocouplers' series operates from a 2.7 V to 5.5 V
supply with guaranteed AC and DC performance from an
extended temperature range of -40 °C to 105 °C. Glitches
free output upon power-up and power-down of optocou-
pler.
Functional Diagram
NC 2
ACPL-021L
6
4
Anode VDD
GND
VO
Shield
1
3
5
Cathode
2
3
8
5
6
Anode
VDD
GND
VO
Shield
1
NC
NC 4
7
Cathode NC
ACPL-M21L
ACPL-024L/K24L
4
1
VDD
V01
Anode1
Cathode1
V02
GND
Cathode2
Anode2
Shield
3
2
5
8
6
7
6
4
Anode VDD
GND
VO
Shield
1
3
5
Cathode
ACPL-W21L
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Ordering Information
ACPL-M21L, ACPL-024L and ACPL-021L are UL Recognized with 3750 Vrms for 1 minute per UL1577.
ACPL-W21L and ACPL-K24L are UL Recognized with 5000 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount
Tape &
Reel
UL1577
5000 Vrms /
1 Minute Rating
IEC/EN
60747-5-5 QuantityRoHS Compliant
ACPL-M21L -000E SO-5 X 100 per tube
-060E X X 100 per tube
-500E X X 1500 per reel
-560E X X X 1500 per reel
ACPL-024L -000E SO-8 X 100 per tube
-060E X X 100 per tube
-500E X X 1500 per reel
-560E X X X 1500 per reel
ACPL-021L -000E SO-8 X 100 per tube
-060E X X 100 per tube
-500E X X 1500 per reel
-560E X X X 1500 per reel
ACPL-W21L -000E Stretched
SO6
X X 100 per tube
-060E X X X 100 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
ACPL-K24L -000E Stretched
SO8
X X 80 per tube
-060E X X X 80 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-M21L-500E to order product of SO-5 package in Tape and Reel packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawings
ACPL-M21L SO-5 Package
ACPL-024L/021L SO-8 Package
NNNN 7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)BSC
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028) MIN
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
Dimensions in millimeters (inches).
Note: Foating Lead Protrusion is 0.15 mm (6 mils) max.
* Maximum Mold ash on each side is 0.15 mm (0.006).
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
8.26
(0.325)
1.80
(0.071)
2.54
(0.10)
1.27
(0.05)
0.64
(0.025)
4.39
(0.17)
LAND PATTERN RECOMMENDATION
0.33
(0.013)
ROHS-COMPLIANCE
INDICATOR PART NUMBER
DATE CODE
YYWW
EEE
Lot ID
8 7 6 5
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050) BSC
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
PART NUMBER
DATE CODE
0.305
(0.012) MIN.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
* Total package length (inclusive of mold ash)
5.207 ± 0.254 (0.205 ± 0.010)
Dimensions in Millimeters (Inches).
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
Lead coplanarity = 0.10 mm (0.004 inches) max.
Option number 500 not marked.
LAND PATTERN RECOMMENDATION
7.49
(0.295)
1.91
(0.075)
0.64
(0.025)
3.95
(0.156)
1.27
(0.5)
ROHS-COMPLIANCE
INDICATOR
NNNN
YYWW
EEE
Lot ID
4
ACPL-W21L Stretched SO-6 Package
ACPL-K24L Stretched SO-8 Package
4.580±0.254
(0.180±0.010)
45°
0.381±0.127
(0.015±0.005)
1.27 (0.050) BSG
0.20±0.10
(0.008±0.004)
0.45 (0.018)
0.750±0.250
(0.0295±0.010)
11.50±0.250
(0.453±0.010)
6.807
0.268
Dimensions in Millimeters (Inches).
Lead coplanarity = 0.1 mm (0.004 inches).
7°
12.65 (0.498)
LAND PATTERN RECOMMENDATION
3.180±0.127
(0.125±0.005)
1.590±0.127
(0.063±0.005)
7°
1.91 (0.075)
3
2
1
4
5
6
0.76 (0.030)
+0.127
0
+0.005
- 0.000 )(
PART NUMBER
DATE CODE
ROHS-COMPLIANCE
INDICATOR
NNNN
YYWW
EEE Lot ID
4
0.381±0.13
(0.015±0.005)
1.270 (0.050) BSG
12.650
(0.5)
1.905
(0.1)
3
2
1
5678
5.850±0.254
(0.230±0.010)
LAND PATTERN RECOMMENDATION
Dimensions in Millimeters (Inches).
Lead coplanarity = 0.1 mm (0.004 inches).
7° 45°
0.254±0.100
(0.010±0.004)
0.450
(0.018)
0.750±0.250
(0.0295±0.010)
11.5±0.250
(0.453±0.010)
7°
1.590±0.127
(0.063±0.005)
PART NUMBER
ROHS-COMPLIANCE
INDICATOR
6.807±0.127
(0.268±0.005)
3.180±0.127
(0.125±0.005)
NNNN
YYWW
EEE
DATE CODE
Lot ID
5
Insulation and Safety Related Specications
Parameter Symbol ACPL-M21L
ACPL-024L
/021L
ACPL-W21L
/K24L Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 5 4.9 8 mm Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(102) 5 4.8 8 mm Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
Gap
(Internal Clearance)
0.08 0.08 0.08 mm Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI 175 175 175 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Solder Reow Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-M21L/024L/021L/W21L/K24L is approved by the following organizations:
UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS for
ACPL-M21L/024L/021L and VISO = 5000 VRMS for ACPL-W21L/K24L
CSA Approval under CSA Component Acceptance Notice #5.
IEC/EN 60747-5-5 (Option 060 and 560 only)
6
IEC/EN 60747-5-5 Insulation Characteristics* (Option 060 and 560 only)
Description Symbol
Characteristic
Unit
ACPL-M21L/
024L/021L
ACPL-W21L/
K24L
Installation classication per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I – IV
I – III
I – II
I – IV
I – IV
I – III
I – III
Climatic Classication 55/105/21 55/105/21
Pollution Degree (DIN VDE 0110/39) 2 2
Maximum Working Insulation Voltage VIORM 567 1140 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test
with tm = 1 sec, Partial discharge < 5 pC
VPR 1063 2137 Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test,
tm = 10 sec, Partial discharge < 5 pC
VPR 896 1824 Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec) VIOTM 6000 8000 Vpeak
Safety-limiting values – maximum values allowed in the
event of a failure.
Case Temperature
Input Current**
Output Power**
TS
IS, INPUT
PS, OUTPUT
150
150
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS>109>109W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,
(IEC/EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test proles.
** Refer to the following gure for dependence of PS and IS on ambient temperature.
Absolute Maximum Ratings
Parameter Symbol Min Max Units Condition
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 105 °C
Reverse Input Voltage VR5 V
Supply Voltage VDD 6.5 V
Average Forward Input Current IF8 mA
Peak Forward Input Current IF(TRAN) 1 A ≤ 1 μs Pulse Width,
< 300 pulses per second
Output Current IO10 mA At max VDD
Output Voltage VO-0.5 VDD +0.5 V
Lead Solder Temperature TLS 260 °C for 10 sec., 1.6 mm below seating plane
Solder Reow Temperature Prole See Package Outline Drawings section
7
Recommended Operating Conditions
Parameter Symbol Min Max Units
Operating Temperature TA-40 105 °C
Input Current, Low Level IFL 0 250 μA
Input Current, High Level IFH 1.6* 6 mA
Power Supply Voltage VDD 2.7 5.5 V
Forward Input Voltage VF (OFF) 0.8 V
* The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% LED degradation guardband.
Electrical Specications (DC)
Over recommended temperature (TA = -40 °C to 105 °C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications
are at VDD = 2.7 V, TA = 25 °C, unless otherwise specied.
Parameter Symbol Channel Min Typ Max Units Test Conditions
Input Forward Voltage VF1.5 2.0 V IF = 2.2 mA (Figure 1 & 2)
Input Reverse
Breakdown Voltage
BVR8 11 V IR = 10 μA
Logic High Output Voltage VOH VDD - 0.1 V IF = 2.2 mA, IO = -20 μA
VDD - 1.0 V IF = 2.2 mA, IO = -3.2 mA
(Figure 3)
Logic Low Output Voltage VOL 0.001 0.1 V IF = 0 mA, IO = 20 μA
0.15 0.4 V IF = 0 mA, IO = 3.2 mA
(Figure 4)
Input Threshold Current ITH 0.5 1.4 mA Figure 5
Logic Low Output Supply
Current
IDDL Single 0.6 1.1 mA VF = 0 V, VDD = 5.5 V,
IO = Open (Figure 6)
Dual 1.2 2.2
Logic High Output Supply
Current
IDDH Single 0.5 1.1 mA IF = 2.2 mA, VDD = 5.5 V,
IO = Open (Figure 7)
Dual 1.0 2.2
Input Capacitance CIN 77 pF f = 1 MHz, VF = 0 V
Input Diode Temperature
Coecient
ΔVF/ΔTA-1.9 mV/°CIF = 2.2 mA
8
Switching Specications (AC)
Over recommended temperature (TA = -40° C to +105° C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications
are at VDD = 2.7 V, TA = 25° C
Parameter Symbol Min Typ Max Units Test Conditions
Propagation Delay Time
to Logic Low Output [1]
tPHL 130 250 ns IF=2.2mA, CL=15pF (Figure 8, 12)
CMOS Signal Levels
Propagation Delay Time
to Logic High Output [1]
tPLH 115 250 ns IF=2.2mA, CL=15pF (Figure 9, 12)
CMOS Signal Levels
Pulse Width Distortion [2] PWD 200 ns CMOS Signal Levels
Propagation Delay Skew [3] tPSK 220 ns
Output Rise Time
(10% – 90%)
tR11 ns IF = 2.2 mA, CL= 15 pF,
CMOS Signal Levels.
Output Fall Time
(90% – 10%)
tF11 ns IF = 2.2 mA, CL= 15 pF,
CMOS Signal Levels.
Static Common Mode
Transient Immunity at
Logic High Output [4]
|CMH| 25 40 kV/μsVCM = 1000 V, TA = 25° C,
IF = 2.2 mA, CL= 15 pF, VI = 5 V
(RT = 1.6 kW) or VI = 3.3 V
(RT = 840 W)
CMOS Signal Levels
Figure 13
Static Common Mode
Transient Immunity at
Logic Low Output [5]
|CML| 25 40 kV/μsVCM = 1000 V, TA = 25° C,
IF = 0 mA, CL= 15 pF, VI = 0 V
(RT = 1.6 kW) or (RT = 840 W)
CMOS Signal Levels
Figure 13
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% VDD of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal
2. PWD is dened as |tPHL - tPLH|
3. tPSK is equal to the magnitude of the worst case dierence in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.
6. Use of a 0.1 μF bypass capacitor connected between Vdd and ground is recommended.
Package Characteristics
All typical at TA = 25° C
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Input-Output Insulation VISO ACPL-M21L
/024L/021L
3750 Vrms RH < 50% for 1 min.
TA = 25° C
ACPL-W21L
/K24L
5000
Input-Output Resistance RI-O 1012 WVI-O = 500 V
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, TA = 25° C
9
Figure 1. Forward Voltage vs. Temperature Figure 2. Forward Current vs Forward Voltage
Figure 3. Logic High Output voltage vs Supply Voltage Figure 4. Logic Low Output Voltage vs. Temperature
Figure 5. Input Threshold Current vs. Temperature Figure 6. Logic Low Output Supply Current vs. Temperature
1.2
1.3
1.4
1.5
1.6
1.7
1.8
-40 -20 0 20 40 60 80 100
VF - FORWARD VOLTAGE - V
TA - TEMPERATURE - °C
0.01
0.1
1
10
100
1.3 1.4 1.5 1.6 1.7 1.8
IF - FORWARD CURRENT - mA
VF - FORWARD VOLTAGE - V
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
VOH - HIGH LEVEL OUTPUT VOLTAGE - V
VDD - SUPPLY VOLTAGE - V
0
0.05
0.1
0.15
0.2
0.25
-40 -20 0 20 40 60 80 100
VOL - LOW LEVEL OUTPUT VOLTAGE - V
TA - TEMPERATURE - °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-40 -20 0 20 40 60 80 100
Ith - INPUT THRESHOLD CURRENT - mA
TA - TEMPERATURE - °C
ITH_3.3 V
ITH_5.0 V
IO = -3.2 mA
IDDL @ 3.3 V
IDDL @ 5.0 V
VDD = 3.3 V
VF = 0 V
IO = 3.2 mA
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40 -20 0 20 40 60 80 100
IDDL - LOGIC LOW OUTPUT SUPPLY
CURRENT - mA
TA - TEMPERATURE - °C
10
Figure 7. Logic High Output Supply Current vs. Temperature Figure 8. Propagation Delay, tPHL vs. Temperature
Figure 9. Propagation Delay, tPLH vs. Temperature
Figure 11. Output Voltage vs Input Current @ Vdd = 5 VFigure 10. Output Voltage vs Input Current @ Vdd = 3.3 V
VDD = 3.3 V VDD = 5.0 V
VDD = 2.7 V
IDDH_3.3 V
IDDH_5.0 V VDD = 2.7 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IDDH - LOGIC HIGH OUTPUT SUPPLY
CURRENT - mA
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
-40 -20 0 20 40 60 80 100
50
60
70
80
90
100
110
120
130
140
150
Tp - PROPAGATION DELAY - ns
IF = 1.6, 2.2 and 6 mA
50
60
70
80
90
100
110
120
130
140
150
TPLH - PROPAGATION DELAY - ns
-40 -20 0 20 40 60 80 100
IF = 1.6 mA
IF = 2.2 mA
IF = 6.0 mA
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008
Vo - OUTPUT VOLTAGE - V
IF - INPUT CURRENT - A IF - INPUT CURRENT - A
0
1
2
3
4
5
6
0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008
Vo - OUTPUT VOLTAGE - V
11
Figure 12. Circuit for tPLH, tPHL, tr, tf
* 0.1 µF BYPASS — SEE NOTE 6 above. [6]
PULSE GEN
tr = tf = 11 ns
f = 1.0 MHz
50% DUTY
CYCLE Vdd
*
OUTPUT VO
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
CL = 15 pF
IF
PULSE GEN
tr = tf = 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
Vdd
OUTPUT VO
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
CL = 15 pF
IF
PULSE GEN
tr = tf = 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
*
Vdd
OUTPUT VO
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
CL = 15 pF
IF
ACPL-M21L
ACPL-021L ACPL-024L/K24L
INPUT IF
OUTPUT VO
IF (ON)
0 mA
50% IF (ON)
VOH
VOL
50%
tPLH tPHL
6
4
Shield
1
3
5
4
1
Shield
3
2
5
8
6
7
2
3
8
5
6
Shield
1
4
7
*
PULSE GEN
tr = tf = 11 ns
f = 1.0 MHz
50% DUTY
CYCLE Vdd
*
OUTPUT VO
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
CL = 15 pF
IF
ACPL-W21L
6
4
Shield
1
3
5
2
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-3462EN - December 6, 2013
Figure 13. Recommended printed circuit board layout and input current limiting resistor selection
ACPL-M21L, ACPL-021L, ACPL-024L, ACPL-W21L, ACPL-K24L :
VI = 3.3 V: R1 = 510 W ± 1%, R2 = 330 W ± 1%
VI = 5.0 V: R1 = 1 kW ± 1%, R2 = 600 W ± 1%
RT = R1 + R2 R1 / R2 ≈ 1.5
5
4
6
3
1
NNNN
YYWW
IF
GND1
Vo
VDD
C
GND
2
VI
R1
R2
ACPL-M21L
ACPL-021L
5
3
4
27
6
81
NNNN
YYWW
IFVo
VDD
C
GND2
VI
R1
GND2
R2
NC
ACPL-024L/K24L
5
3
4
27
6
81
NNNN
YYWW
IF
GND
1
V
o1
VDD
C
GND2
VI
R1
R2
IF
GND2
VI
R
1
R2
Vo2
C = 0.1µF
5
4
6
3
1
NNNN
YYWW
IF
GND1
Vo
VDD
C
GND
2
VI
R1
R2
ACPL-W21L
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Avago Technologies:
ACPL-M21L-500E ACPL-M21L-560E ACPL-024L-560E ACPL-024L-000E ACPL-024L-060E ACPL-024L-500E
ACPL-021L-000E ACPL-021L-560E ACPL-K24L-000E ACPL-K24L-500E ACPL-W21L-500E ACPL-021L-500E
ACPL-W21L-000E ACPL-021L-060E