80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz)
Product specification
IC28 Data Handbook 2000 Aug 07
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2
2000 Aug 07 853–2213 24293
DESCRIPTION
The Philips 80C31/32 is a high-performance static 80C51 design
fabricated with Philips high-density CMOS technology with operation
from 2.7 V to 5.5 V.
The 80C31/32 ROMless devices contain a 128 × 8 RAM/256 ×8
RAM, 32 I/O lines, three 16-bit counter/timers, a six-source,
four-priority level nested interrupt structure, a serial I/O port for
either multi-processor communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock circuits.
In addition, the device is a low power static design which offers a
wide range of operating frequencies down to zero. Two software
selectable modes of power reduction—idle mode and power-down
mode are available. The idle mode freezes the CPU while allowing
the RAM, timers, serial port, and interrupt system to continue
functioning. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative. Since the design is static, the clock can be stopped
without loss of user data and then the execution resumed from the
point the clock was stopped.
SELECTION TABLE
For applications requiring more ROM and RAM, see the 8XC54/58
and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.
ROM/EPROM
Memory Size
(X by 8)
RAM Size
(X by 8) Programmable
Timer Counter
(PCA)
Hardware
W atch Dog
Timer
80C31/8XC51
0K/4K 128 No No
80C32/8XC52/54/58
0K/8K/16K/32K 256 No No
80C51RA+/8XC51RA+/RB+/RC+
0K/8K/16K/32K 512 Yes Yes
8XC51RD+
64K 1024 Yes Yes
FEATURES
•8051 Central Processing Unit
–128 × 8 RAM (80C31)
–256 × 8 RAM (80C32)
–Three 16-bit counter/timers
–Boolean processor
–Full static operation
–Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
•Memory addressing capability
–64k ROM and 64k RAM
•Power control modes:
–Clock can be stopped and resumed
–Idle mode
–Power-down mode
•CMOS and TTL compatible
•TWO speed ranges at VCC = 5 V
–0 to 16 MHz
–0 to 33 MHz
•Three package styles
•Extended temperature ranges
•Dual Data Pointers
•4 level priority interrupt
•6 interrupt sources
•Four 8-bit I/O ports
•Full–duplex enhanced UART
–Framing error detection
–Automatic address recognition
•Programmable clock out
•Asynchronous port reset
•Low EMI (inhibit ALE)
•W ake-up from Power Down by an external interrupt
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 3
80C51/87C51 AND 80C31 ORDERING INFORMATION
ROMless TEMPERATURE RANGE °C
AND PACKAGE VOLTAGE
RANGE FREQ.
(MHz) DRAWING
NUMBER
P80C31SBPN
0 to +70 Plastic Dual In line Package
27Vto55V
0to16
SOT129 1
P80C31SBPN
0
to
+
70
,
Plastic
D
u
al
In
-
line
Package
2
.
7
V
to
5
.
5
V
0
to
16
SOT129
-
1
P80C31SBAA
0 to +70 Plastic Leaded Chi
p
Carrier
27Vto55V
0to16
SOT187 2
P80C31SBAA
0
to
+
70
,
Plastic
Leaded
Chip
Carrier
2
.
7
V
to
5
.
5
V
0
to
16
SOT187
-
2
P80C31SBBB
0 to +70 Plastic Quad Flat Pack
27Vto55V
0to16
SOT307 2
P80C31SBBB
0
to
+
70
,
Plastic
Q
u
ad
Flat
Pack
2
.
7
V
to
5
.
5
V
0
to
16
SOT307
-
2
P80C31SFPN
40 to +85 Plastic Dual In line Package
27Vto55V
0to16
SOT129 1
P80C31SFPN
–
40
to
+
85
,
Plastic
D
u
al
In
-
line
Package
2
.
7
V
to
5
.
5
V
0
to
16
SOT129
-
1
P80C31SFAA
40 to +85 Plastic Leaded Chi
p
Carrier
27Vto55V
0to16
SOT187 2
P80C31SFAA
–
40
to
+
85
,
Plastic
Leaded
Chip
Carrier
2
.
7
V
to
5
.
5
V
0
to
16
SOT187
-
2
P80C31SFBB
40 to +85 Plastic Quad Flat Pack
27Vto55V
0to16
SOT307 2
P80C31SFBB
–
40
to
+
85
,
Plastic
Q
u
ad
Flat
Pack
2
.
7
V
to
5
.
5
V
0
to
16
SOT307
-
2
PART NUMBER DERIVATION
DEVICE NUMBER OPERATING FREQUENCY, MAX (S) TEMPERATURE RANGE (B) PACKAGE (AA)
P80C31 S = 16 MHz B = 0_ to +70_CAA = PLCC
P80C32 U = 33 MHz F = –40_C to +85_CBB = PQFP
PN = PDIP
80C32 ORDERING INFORMATION
ROMless TEMPERATURE RANGE °C
AND PACKAGE FREQ
MHz DRAWING
NUMBER
P80C32SBP N 0 to +70, Plastic Dual In-line Package 16 SOT129-1
P80C32SBA A 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2
P80C32SBB B 0 to +70, Plastic Quad Flat Pack 16 SOT307-2
P80C32SFP N –40 to +85, Plastic Dual In-line Package 16 SOT129-1
P80C32SFA A –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2
P80C32SFB B –40 to +85, Plastic Quad Flat Pack 16 SOT307-2
P80C32UBA A 0 to +70, Plastic Leaded Chip Carrier 33 SOT187-2
P80C32UBP N 0 to +70, Plastic Dual In-line Package 33 SOT129-1
P80C32UBB B 0 to +70, Plastic Quad Flat Pack 33 SOT307-2
P80C32UFA A –40 to +85, Plastic Leaded Chip Carrier 33 SOT187-2
P80C32UFP N –40 to +85, Plastic Dual In-line Package 33 SOT129-1
P80C32UFB B –40 to +85, Plastic Quad Flat Pack 33 SOT307-2
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 4
BLOCK DIAGRAM
SU00845
PSEN
EAVPP
ALE/PROG
RST
XTAL1 XTAL2
VCC
VSS
PORT 0
DRIVERS PORT 2
DRIVERS
RAM ADDR
REGISTER RAM PORT 0
LATCH PORT 2
LATCH ROM/EPROM
REGISTER
BACC STACK
POINTER
TMP2 TMP1
ALU
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
PD
OSCILLATOR
PSW
PORT 1
LATCH PORT 3
LATCH
PORT 1
DRIVERS PORT 3
DRIVERS
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
PROGRAM
COUNTER
DPTR’S
MULTIPLE
P1.0–P1.7 P3.0–P3.7
P0.0–P0.7 P2.0–P2.7
SFRs
TIMERS
8
8 16
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 5
LOGIC SYMBOL
PORT 0
PORT 1PORT 2
PORT 3
ADDRESS AND
DATA BUS
ADDRESS BUS
T2
T2EX
RxD
TxD
INT0
INT1
T0
T1
WR
RD
SECONDARY FUNCTIONS
RST
EA/VPP
PSEN
ALE/PROG
VSS
VCC
XTAL1
XTAL2
SU00830
PIN CONFIGURATIONS
SU01063
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P1.7
WR/P3.6
RD/P3.7
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
DUAL
IN-LINE
PACKAGE
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
SU01062
LCC
6140
7
17
39
29
18 28
Pin Function
1 NIC*
2 P1.0/T2
3 P1.1/T2EX
4 P1.2
5 P1.3
6 P1.4
7 P1.5
8 P1.6
9 P1.7
10 RST
11 P3.0/RxD
12 NIC*
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
Pin Function
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 VSS
23 NIC*
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
Pin Function
31 P2.7/A15
32 PSEN
33 ALE
34 NIC*
35 EA/VPP
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 VCC
* NO INTERNAL CONNECTION
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
SU01064
PQFP
44 34
1
11
33
23
12 22
Pin Function
1 P1.5
2 P1.6
3 P1.7
4 RST
5 P3.0/RxD
6 NIC*
7 P3.1/TxD
8 P3.2/INT0
9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
Pin Function
16 VSS
17 NIC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12
23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE
28 NIC*
29 EA/VPP
30 P0.7/AD7
Pin Function
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 VCC
39 NIC*
40 P1.0/T2
41 P1.1/T2EX
42 P1.2
43 P1.3
44 P1.4
* NO INTERNAL CONNECTION
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 6
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
VSS 20 22 16 I Ground: 0 V reference.
VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins
that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7 1–8 2–9 40–44,
1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate
functions for Port 1 include:
1 2 40 I/O T2 (P1.0):
T imer/Counter 2 external count input/clockout (see Programmable Clock-Out)
2 3 41 I T2EX (P1.1): T imer/Counter 2 Reload/Capture/Direction control
P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-up s wh e n e m itting 1s. During accesses to external
da ta memo ry that use 8-bit add resses (MOV @Ri), port 2 emits the contents of the P2
special function register.
P3.0–P3.7 10–17 11,
13–19 5,
7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source
current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves
the special features of the 80C51 family, as listed below:
10 11 5 I RxD (P3.0): Serial input port
11 13 7 O TxD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt
13 15 9 I INT1 (P3.3): External interrupt
14 16 10 IT0 (P3.4): T imer 0 external input
15 17 11 IT1 (P3.5): Timer 1 external input
16 18 12 OWR (P3.6): External data memory write strobe
17 19 13 ORD (P3.7): External data memory read strobe
RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VCC.
ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN 29 32 26 OProgram Store Enable: The read strobe to external program memory. When the 80C31/32
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program memory.
EA/VPP 31 35 29 IExternal Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH.
XTAL1 19 21 15 ICrystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2 18 20 14 OCrystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 7
Table 1. 8XC51/80C31 Special Function Registers
SYMBOL DESCRIPTION DIRECT
ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB RESET
VALUE
ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
AUXR# Auxiliary 8EH – – – – – – – AO xxxxxxx0B
AUXR1# Auxiliary 1 A2H – – – – WUPD20 – DPS xxx000x0B
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR: Data Pointer (2 bytes)
DPH Data Pointer High 83H 00H
DPL Data Pointer Low 82H 00H
AF AE AD AC AB AA A9 A8
IE* Interrupt Enable A8H EA – ET2 ES ET1 EX1 ET0 EX0 0x000000B
BF BE BD BC BB BA B9 B8
IP* Interrupt Priority B8H – – PT2 PS PT1 PX1 PT0 PX0 xx000000B
B7 B6 B5 B4 B3 B2 B1 B0
IPH# Interrupt Priority High B7H – – PT2H PSH PT1H PX1H PT0H PX0H xx000000B
87 86 85 84 83 82 81 80
P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH
97 96 95 94 93 92 91 90
P1* Port 1 90H – – – – – – T2EX T2 FFH
A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 FFH
B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH
PCON#1Power Control 87H SMOD1 SMOD0 – POF GF1 GF0 PD IDL 00xx0000B
D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 000000x0B
RACAP2H#Timer 2 Capture High CBH 00H
RACAP2L#Timer 2 Capture Low CAH 00H
SADDR# Slave Address A9H 00H
SADEN# Slave Address Mask B9H 00H
SBUF Serial Data Buffer 99H xxxxxxxxB
9F 9E 9D 9C 9B 9A 99 98
SCON* Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H
SP Stack Pointer 81H 07H
8F 8E 8D 8C 8B 8A 89 88
TCON* T imer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
CF CE CD CC CB CA C9 C8
T2CON* T imer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H
T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B
TH0 T imer High 0 8CH 00H
TH1 T imer High 1 8DH 00H
TH2# Timer High 2 CDH 00H
TL0 T imer Low 0 8AH 00H
TL1 T imer Low 1 8BH 00H
TL2# T imer Low 2 CCH 00H
TMOD T imer Mode 89H GATE C/T M1 M0 GA TE C/T M1 M0 00H
NOTE:
Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incor rectly.
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1. Reset value depends on reset source.
2. Not available on 80C31.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 8
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle Mode
In idle mode (see Table 2), the CPU puts itself to sleep while all of
the on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
For the 80C31 or 80C32, either a hardware reset or external
interrupt can be used to exit from Power Down. Reset redefines all
the SFRs but does not change the on-chip RAM. An external
interrupt allows both the SFRs and the on-chip RAM to retain their
values. WUPD (AUXR1.3–W akeup from Power Down) enables or
disables the wakeup from power down with external interrupt.
Where:
WUPD = 0 Disable
WUPD = 1 Enable
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 or INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
For the 80C31, wakeup from power down is always enabled.
Design Consideration
•When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 80C31/32 is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE PROGRAM MEMOR Y ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 9
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at
a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of T imer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
Oscillator Frequency
4 (65536 *RCAP2H,RCAP2L)
Where:
(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode T imer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use T imer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
TIMER 2 OPERATION
Timer 2
T imer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). T imer 2 has three operating
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the T imer 2 interrupt bit in the
IE register). If EXEN2= 1, T imer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the T imer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as T imer 2 overflow interrupt.
The T imer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, T imer 2 can be configured (as either
a timer or counter (C/T2* in T2CON)) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means T imer 2
will default to counting up. If DCEN bit is set, T imer 2 can count up
or down depending on the value of the T2EX pin.
Figure 4 shows T imer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
T imer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The T imer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1 which enables T imer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX T imer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes T imer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. T imer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
The external flag EXF2 toggles when T imer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
Table 3. Timer 2 Operating Modes
RCLK + TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud rate generator
X X 0 (off)
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2000 Aug 07 10
(MSB) (LSB)
Symbol Position Name and Significance
TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When T imer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes T imer 1 overflow to be used for the receive clock.
TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes T imer 1 overflows to be used for the transmit clock.
EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if T imer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2 T2CON.1 T imer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2 T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with T imer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on T imer 2 overflow.
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
OSC ÷ 12 C/T2 = 0
C/T2 = 1
TR2
Control
TL2
(8-bits) TH2
(8-bits) TF2
RCAP2L RCAP2H
EXEN2
Control
EXF2
Timer 2
Interrupt
T2EX Pin
Transition
Detector
T2 Pin
Capture
SU00066
Figure 2. Timer 2 in Capture Mode
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2000 Aug 07 11
Not Bit Addressable
Symbol Function
— Not implemented, reserved for future use.*
T2OE Timer 2 Output Enable bit.
DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
— — — — — — T2OE DCEN
SU00729
76543210
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
Bit
T2MOD Address = 0C9H Reset Value = XXXX XX00B
Figure 3. Timer 2 Mode (T2MOD) Control Register
OSC ÷ 12 C/T2 = 0
C/T2 = 1
TR2
CONTROL
TL2
(8-BITS) TH2
(8-BITS)
TF2
RCAP2L RCAP2H
EXEN2
CONTROL
EXF2
TIMER 2
INTERRUPT
T2EX PIN
TRANSITION
DETECTOR
T2 PIN
RELOAD
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
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2000 Aug 07 12
÷12 C/T2 = 0
C/T2 = 1
TL2 TH2
TR2
CONTROL
T2 PIN
SU00730
FFH FFH
RCAP2L RCAP2H
(UP COUNTING RELOAD VALUE) T2EX PIN
TF2 INTERRUPT
COUNT
DIRECTION
1 = UP
0 = DOWN
EXF2
OVERFLOW
(DOWN COUNTING RELOAD VALUE)
TOGGLE
OSC
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
OSC ÷ 2 C/T2 = 0
C/T2 = 1
TR2
Control
TL2
(8-bits) TH2
(8-bits)
÷ 16
RCAP2L RCAP2H
EXEN2
Control
EXF2 Timer 2
Interrupt
T2EX Pin
Transition
Detector
T2 Pin
Reload
NOTE: OSC. Freq. is divided by 2, not 12. ÷ 2
“0” “1”
RX Clock
÷ 16 TX Clock
“0”“1”
“0”“1”
Timer 1
Overflow
Note availability of additional external interrupt.
SMOD
RCLK
TCLK
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
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2000 Aug 07 13
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port
transmit and receive baud rates to be derived from either T imer 1 or
T imer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
T imer 1, the other by Timer 2.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode, in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
The baud rates in modes 1 and 3 are determined by T imer 2’s
overflow rate given below:
Modes 1 and 3 Baud Rates +Timer 2 Overflow Rate
16
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
T imer operation is different for Timer 2 when it is being used as a
baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Oscillator Frequency
[32 [65536 *(RCAP2H,RCAP2L)]]
Modes 1 and 3 Baud Rates =
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
The T imer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the T imer 2 interrupt does not have to be disabled when
T imer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(T imer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator , T2EX
can be used as an additional external interrupt, if needed.
When T imer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the T imer 2 or RCAP2 registers.
Table 4 shows commonly used baud rates and how they can be
obtained from T imer 2.
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Ba d Rate
Osc Freq
Timer 2
Ba
u
d
Rate
Osc
Freq
RCAP2H RCAP2L
375 K 12 MHz FF FF
9.6 K 12 MHz FF D9
2.8 K 12 MHz FF B2
2.4 K 12 MHz FF 64
1.2 K 12 MHz FE C8
300 12 MHz FB 1E
110 12 MHz F2 AF
300 6 MHz FD 8F
110 6 MHz F9 57
Summary Of Baud Rate Equations
T imer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Baud Rate +Timer 2 Overflow Rate
16
If T imer 2 is being clocked internally, the baud rate is:
Baud Rate +fOSC
[32 [65536 *(RCAP2H,RCAP2L)]]
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
RCAP2H,RCAP2L +65536 *ǒfOSC
32 Baud RateǓ
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. See Table 5 for set-up
of T imer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a
counter.
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2000 Aug 07 14
Table 5. Timer 2 as a Timer
MODE
T2CON
MODE
INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2)
16-bit Auto-Reload 00H 08H
16-bit Capture 01H 09H
Baud rate generator receive and transmit same baud rate 34H 36H
Receive only 24H 26H
T ransmit only 14H 16H
Table 6. Timer 2 as a Counter
MODE
TMOD
MODE
INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2)
16-bit 02H 0AH
Auto-Reload 03H 0BH
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when T imer 2 is used in the baud rate
generator mode.
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of
Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers
. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The 80C31/32 UART also fully supports multiprocessor
communication.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0
Slave 1 SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1 SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
Slave 2 SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
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and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
SCON Address = 98H Reset Value = 0000 0000B
SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl
Bit Addressable
(SMOD0 = 0/1)*
Symbol Function
FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1 Serial Port Mode Bit 1
SM0 SM1 Mode Description Baud Rate**
0 0 0 shift register fOSC/12
0 1 1 8-bit UART variable
1 0 2 9-bit UART fOSC/64 or fOSC/32
1 1 3 9-bit UART variable
SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl T ransmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**fOSC = oscillator frequency
SU00043
Bit: 76543210
Figure 7. SCON: Serial Port Control Register
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SMOD1 SMOD0 – POF GF1 GF0 PD IDL PCON
(87H)
SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON
(98H)
D0 D1 D2 D3 D4 D5 D6 D7 D8
STOP
BIT
DATA BYTE ONLY IN
MODE 2, 3
START
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU01191
Figure 8. UART Framing Error Detection
SM0 SM1 SM2 REN TB8 RB8 TI RI SCON
(98H)
D0 D1 D2 D3 D4 D5 D6 D7 D8
1
11
0
COMPARATOR
11 X
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
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Interrupt Priority Structure
The 80C31 and 80C32 have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x IP.x
INTERRUPT
PRIORITY
LEVEL
0 0 Level 0 (lowest priority)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7. Interrupt Table
SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS
X0 1 IE0 N (L)1Y (T)203H
T0 2 TP0 Y 0BH
X1 3 IE1 N (L) Y (T) 13H
T1 4 TF1 Y 1BH
SP 5 RI, TI N 23H
T2 6 TF2, EXF2 N 2BH
NOTES:
1. L = Level activated
2. T = T ransition activated
EX0IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT SYMBOL FUNCTION
IE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6 — Not implemented. Reserved for future use.
IE.5 ET2 T imer 2 interrupt enable bit.
IE.4 ES Serial Port interrupt enable bit.
IE.3 ET1 T imer 1 interrupt enable bit.
IE.2 EX1 External interrupt 1 enable bit.
IE.1 ET0 T imer 0 interrupt enable bit.
IE.0 EX0 External interrupt 0 enable bit.
SU00571
ET0EX1ET1ESET2—EA
01234567
Figure 10. IE Registers
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PX0IP (0B8H)
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT SYMBOL FUNCTION
IP.7 — Not implemented, reserved for future use.
IP.6 — Not implemented, reserved for future use.
IP.5 PT2 T imer 2 interrupt priority bit.
IP.4 PS Serial Port interrupt priority bit.
IP.3 PT1 T imer 1 interrupt priority bit.
IP.2 PX1 External interrupt 1 priority bit.
IP.1 PT0 T imer 0 interrupt priority bit.
IP.0 PX0 External interrupt 0 priority bit.
SU00572
PT0PX1PT1PSPT2—— 01234567
Figure 11. IP Registers
PX0HIPH (B7H)
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT SYMBOL FUNCTION
IPH.7 — Not implemented, reserved for future use.
IPH.6 — Not implemented, reserved for future use.
IPH.5 PT2H Timer 2 interrupt priority bit high.
IPH.4 PSH Serial Port interrupt priority bit high.
IPH.3 PT1H Timer 1 interrupt priority bit high.
IPH.2 PX1H External interrupt 1 priority bit high.
IPH.1 PT0H Timer 0 interrupt priority bit high.
IPH.0 PX0H External interrupt 0 priority bit high.
SU01058
PT0HPX1HPT1HPSHPT2H——
01234567
Figure 12. IPH Registers
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2000 Aug 07 19
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
765432 1 0
– – – – – – – AO
AUX R.0 AO T urns off ALE output.
Dual DPTR
The dual DPTR structure (see Figure 13) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
•New Register Name: AUXR1#
•SFR Address: A2H
•Reset Value: xxx000x0B
AUXR1 (A2H)
76543210
– – – – WUPD 0 – DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg DPS
DPTR0 0
DPTR1 1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WOPD or LPEP bits.
DPS
DPTR1
DPTR0
DPH
(83H) DPL
(82H) EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 13.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 20
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER RATING UNIT
Operating temperature under bias 0 to +70 or –40 to +85 °C
Storage temperature range –65 to +150 °C
Voltage on EA pin to VSS 0 to +13.0 V
Voltage on any other pin to VSS –0.5 to +6.5 V
Maximum IOL per I/O pin 15 mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C
CLOCK FREQUENCY
RANGE –f
SYMBOL FIGURE PARAMETER MIN MAX UNIT
1/tCLCL 29 Oscillator frequency
Speed versions : S (16 MHz)
U (33 MHz) 0
016
33 MHz
MHz
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 21
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 2.7 V to 5.5 V, VSS = 0 V (16 MHz devices)
SYMBOL
PARAMETER
TEST LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS MIN TYP1MAX
UNIT
V
In
p
ut low voltage
4.0 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V
V
IL
Inp
u
t
lo
w v
oltage
2.7 V<VCC< 4.0 V –0.5 0.7 V
VIH Input high voltage (ports 0, 1, 2, 3, EA)0.2 VCC+0.9 VCC+0.5 V
VIH1 Input high voltage, XTAL1, RST 0.7 VCC VCC+0.5 V
VOL Output low voltage, ports 1, 2, 8VCC = 2.7 V
IOL = 1.6 mA20.4 V
VOL1 Output low voltage, port 0, ALE, PSEN8, 7VCC = 2.7 V
IOL = 3.2 mA20.4 V
VO
Out
p
ut high voltage
p
orts 1 2 3 3
VCC = 2.7 V
IOH = –20 µAVCC – 0.7 V
V
OH
O
u
tp
u
t
high
v
oltage
,
ports
1
,
2
,
33
VCC = 4.5 V
IOH = –30 µAVCC – 0.7 V
VOH1 Output high voltage (port 0 in external bus
mode), ALE9, PSEN3VCC = 2.7 V
IOH = –3.2 mA VCC – 0.7 V
IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 µA
ITL Logical 1-to-0 transition current, ports 1, 2, 36VIN = 2.0 V
See note 4 –650 µA
ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA
ICC Power supply current (see Figure 21): See note 5
Active mode @ 16 MHz µA
Idle mode @ 16 MHz µA
Power-down mode or clock stopped (see
Fi 25 f diti )
Tamb = 0°C to 70°C 3 50 µA
Figure 25 for conditions) Tamb = –40°C to +85°C 75 µA
RRST Internal reset pull-down resistor 40 225 kΩ
CIO Pin capacitance10 (except EA) 15 pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt T rigger, or use an address latch with a Schmitt Trigger STROBE input. I OL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
5. See Figures 22 through 25 for ICC test conditions.
Active mode: ICC = 0.9 × FREQ. + 1.1 mA
Idle mode: ICC = 0.18 × FREQ. +1.01 mA; See Figure 21.
6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µA.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 15 mA (*NOTE: This is 85°C specification.)
Maximum IOL per 8-bit port: 26 mA
Maximum total IOL for all outputs: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 22
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, 33 MHz devices; 5 V ±10%; VSS = 0 V
SYMBOL
PARAMETER
TEST LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS MIN TYP1MAX
UNIT
VIL Input low voltage 4.5 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V
VIH Input high voltage (ports 0, 1, 2, 3, EA)0.2 VCC+0.9 VCC+0.5 V
VIH1 Input high voltage, XTAL1, RST 0.7 VCC VCC+0.5 V
VOL Output low voltage, ports 1, 2, 3 8VCC = 4.5 V
IOL = 1.6mA20.4 V
VOL1 Output low voltage, port 0, ALE, PSEN 7, 8VCC = 4.5 V
IOL = 3.2mA20.4 V
VOH Output high voltage, ports 1, 2, 3 3VCC = 4.5 V
IOH = –30µAVCC – 0.7 V
VOH1 Output high voltage (port 0 in external bus
mode), ALE9, PSEN3VCC = 4.5 V
IOH = –3.2mA VCC – 0.7 V
IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 µA
ITL Logical 1-to-0 transition current, ports 1, 2, 36VIN = 2.0 V
See note 4 –650 µA
ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA
ICC Power supply current (see Figure 21): See note 5
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see Fig-
25 f diti )
Tamb = 0°C to 70°C 3 50 µA
ure 25 for conditions) Tamb = –40°C to +85°C 75 µA
RRST Internal reset pull-down resistor 40 225 kΩ
CIO Pin capacitance10 (except EA) 15 pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt T rigger, or use an address latch with a Schmitt Trigger STROBE input. I OL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
5. See Figures 22 through 25 for ICC test conditions.
Active mode: ICC(MAX) = 0.9 × FREQ. + 1.1 mA
Idle mode: ICC(MAX) = 0.18 × FREQ. +1.0 mA; See Figure 21.
6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µA.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 15 mA (*NOTE: This is 85°C specification.)
Maximum IOL per 8-bit port: 26 mA
Maximum total IOL for all outputs: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 23
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7 V to +5.5 V, VSS = 0 V1, 2, 3
16 MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/tCLCL 14 Oscillator frequency5
Speed versions :S 3.5 16 MHz
tLHLL 14 ALE pulse width 85 2tCLCL–40 ns
tAVLL 14 Address valid to ALE low 22 tCLCL–40 ns
tLLAX 14 Address hold after ALE low 32 tCLCL–30 ns
tLLIV 14 ALE low to valid instruction in 150 4tCLCL–100 ns
tLLPL 14 ALE low to PSEN low 32 tCLCL–30 ns
tPLPH 14 PSEN pulse width 142 3tCLCL–45 ns
tPLIV 14 PSEN low to valid instruction in 82 3tCLCL–105 ns
tPXIX 14 Input instruction hold after PSEN 0 0 ns
tPXIZ 14 Input instruction float after PSEN 37 tCLCL–25 ns
tAVIV 414 Address to valid instruction in 207 5tCLCL–105 ns
tPLAZ 14 PSEN low to address float 10 10 ns
Data Memory
tRLRH 15, 16 RD pulse width 275 6tCLCL–100 ns
tWLWH 15, 16 WR pulse width 275 6tCLCL–100 ns
tRLDV 15, 16 RD low to valid data in 147 5tCLCL–165 ns
tRHDX 15, 16 Data hold after RD 0 0 ns
tRHDZ 15, 16 Data float after RD 65 2tCLCL–60 ns
tLLDV 15, 16 ALE low to valid data in 350 8tCLCL–150 ns
tAVDV 15, 16 Address to valid data in 397 9tCLCL–165 ns
tLLWL 15, 16 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns
tAVWL 15, 16 Address valid to WR low or RD low 122 4tCLCL–130 ns
tQVWX 15, 16 Data valid to WR transition 13 tCLCL–50 ns
tWHQX 15, 16 Data hold after WR 13 tCLCL–50 ns
tQVWH 16 Data valid to WR high 287 7tCLCL–150 ns
tRLAZ 15, 16 RD low to address float 0 0 ns
tWHLH 15, 16 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns
External Clock
tCHCX 18 High time 20 20 tCLCL–tCLCX ns
tCLCX 18 Low time 20 20 tCLCL–tCHCX ns
tCLCH 18 Rise time 20 20 ns
tCHCL 18 Fall time 20 20 ns
Shift Register
tXLXL 17 Serial port clock cycle time 750 12tCLCL ns
tQVXH 17 Output data setup to clock rising edge 492 10tCLCL–133 ns
tXHQX 17 Output data hold after clock rising edge 8 2tCLCL–117 ns
tXHDX 17 Input data hold after clock rising edge 0 0 ns
tXHDV 17 Clock rising edge to input data valid 492 10tCLCL–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 80C31 and 80C32 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 24
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0 V1, 2, 3
VARIABLE CLOCK4
16 MHz to fmax 33 MHz CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
tLHLL 14 ALE pulse width 2tCLCL–40 21 ns
tAVLL 14 Address valid to ALE low tCLCL–25 5 ns
tLLAX 14 Address hold after ALE low tCLCL–25 ns
tLLIV 14 ALE low to valid instruction in 4tCLCL–65 55 ns
tLLPL 14 ALE low to PSEN low tCLCL–25 5 ns
tPLPH 14 PSEN pulse width 3tCLCL–45 45 ns
tPLIV 14 PSEN low to valid instruction in 3tCLCL–60 30 ns
tPXIX 14 Input instruction hold after PSEN 0 0 ns
tPXIZ 14 Input instruction float after PSEN tCLCL–25 5 ns
tAVIV 14 Address to valid instruction in 5tCLCL–80 70 ns
tPLAZ 14 PSEN low to address float 10 10 ns
Data Memory
tRLRH 15, 16 RD pulse width 6tCLCL–100 82 ns
tWLWH 15, 16 WR pulse width 6tCLCL–100 82 ns
tRLDV 15, 16 RD low to valid data in 5tCLCL–90 60 ns
tRHDX 15, 16 Data hold after RD 0 0 ns
tRHDZ 15, 16 Data float after RD 2tCLCL–28 32 ns
tLLDV 15, 16 ALE low to valid data in 8tCLCL–150 90 ns
tAVDV 15, 16 Address to valid data in 9tCLCL–165 105 ns
tLLWL 15, 16 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns
tAVWL 15, 16 Address valid to WR low or RD low 4tCLCL–75 45 ns
tQVWX 15, 16 Data valid to WR transition tCLCL–30 0 ns
tWHQX 15, 16 Data hold after WR tCLCL–25 5 ns
tQVWH 16 Data valid to WR high 7tCLCL–130 80 ns
tRLAZ 15, 16 RD low to address float 0 0 ns
tWHLH 15, 16 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns
External Clock
tCHCX 18 High time 0.38t CLCL tCLCL–tCLCX ns
tCLCX 18 Low time 0.38t CLCL tCLCL–tCHCX ns
tCLCH 18 Rise time 5 ns
tCHCL 18 Fall time 5 ns
Shift Register
tXLXL 17 Serial port clock cycle time 12tCLCL 360 ns
tQVXH 17 Output data setup to clock rising edge 10tCLCL–133 167 ns
tXHQX 17 Output data hold after clock rising edge 2tCLCL–80 ns
tXHDX 17 Input data hold after clock rising edge 0 0 ns
tXHDV 17 Clock rising edge to input data valid 10tCLCL–133 167 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 80C31 and 80C32 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
“AC Electrical Characteristics”, page 23.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 25
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
Q – Output data
R–RD
signal
t – Time
V – Valid
W– WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL =Time for ALE low to PSEN low.
tPXIZ
ALE
PSEN
PORT 0
PORT 2 A0–A15 A8–A15
A0–A7 A0–A7
tAVLL
tPXIX
tLLAX
INSTR IN
tLHLL
tPLPH
tLLIV
tPLAZ
tLLPL
tAVIV
SU00006
tPLIV
Figure 14. External Program Memory Read Cycle
ALE
PSEN
PORT 0
PORT 2
RD
A0–A7
FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH
tWHLH
tLLDV
tLLWL tRLRH
tLLAX
tRLAZ
tAVLL tRHDX
tRHDZ
tAVWL
tAVDV
tRLDV
SU00025
Figure 15. External Data Memory Read Cycle
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 26
tLLAX
ALE
PSEN
PORT 0
PORT 2
WR
A0–A7
FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH
tWHLH
tLLWL tWLWH
tAVLL
tAVWL
tQVWX tWHQX
tQVWH
SU00026
Figure 16. External Data Memory Write Cycle
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
VALID VALID VALID VALID VALID VALID VALID VALID
SET TI
SET RI
tXLXL
tQVXH tXHQX
tXHDX
tXHDV
SU00027
12304567
Figure 17. Shift Register Mode Timing
VCC–0.5
0.45V 0.7VCC
0.2VCC–0.1
tCHCL
tCLCL
tCLCH
tCLCX
tCHCX
SU00009
Figure 18. External Clock Drive
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 27
VCC–0.5
0.45V
0.2VCC+0.9
0.2VCC–0.1
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00717
Figure 19. AC Testing Input/Output
VLOAD
VLOAD+0.1V
VLOAD–0.1V
VOH–0.1V
VOL+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00718
Figure 20. Float Waveform
SU01413
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
MAX ACTIVE
MODE
ICCMAX = 0.9 X FREQ. + 1.1
5
481216
FREQ AT XTAL1 (MHz)
20 24 28 32 36
15
25
30
ICC(mA)
10
20
35
Figure 21. ICC vs. FREQ
Valid only within frequency specifications of the device under test
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 28
VCC
P0
EA
RST
XTAL1
XTAL2
VSS
VCC
VCC
VCC
ICC
(NC)
CLOCK SIGNAL
SU00719
Figure 22. ICC Test Condition, Active Mode
All other pins are disconnected
VCC
P0
EA
RST
XTAL1
XTAL2
VSS
VCC
VCC
ICC
(NC)
CLOCK SIGNAL
SU00720
Figure 23. ICC Test Condition, Idle Mode
All other pins are disconnected
VCC–0.5
0.45V 0.7VCC
0.2VCC–0.1
tCHCL
tCLCL
tCLCH
tCLCX
tCHCX
SU00009
Figure 24. Clock Signal W aveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VCC
P0
EA
RST
XTAL1
XTAL2
VSS
VCC
VCC
ICC
(NC)
SU00016
Figure 25. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2 V to 5.5 V
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 29
DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 30
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 31
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
Philips Semiconductors Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07 32
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 08-00
Document order number: 9397 750 07403
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
