© 2007 Microchip Technology Inc. DS22001C-page 1
MCP1827/MCP1827S
Features
• 1.5A Output Current Capability
• Input Operating Voltage Range: 2.3V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1827 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 330 mV Typical at 1.5A
• Typical Output Voltage Tolerance: 0.5%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast response to Load Transients
• Low Supply Current: 120 µA (typ)
• Low Shutdown Supply Current: 0.1 µA (typ)
(MCP1827 only)
• Fixed Delay on Power Good Output
(MCP1827 only)
• Short Circuit Current Limiting and
Overtemperature Protection
• 5-Lead Plastic DDPAK, 5-Lead TO-220 Package
Options (MCP1827)
• 3-Lead Plastic DDPAK, 3-Lead TO-220 Package
Options (MCP1827S)
Applications
• High-Speed Driver Chipset Power
• Networking Backplane Cards
• Notebook Computers
• Network Interface Cards
• Palmtop Computers
• 2.5V to 1.XV Regulators
Description
The MCP1827/MCP1827S is a 1.5A Low Dropout
(LDO) linear regulator that provides high current and
low output voltages. The MCP1827 comes in a fixed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 1.5A output current
capability, combined with the low output voltage
capability, make the MCP1827 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands. The MCP1827S is a 3-pin fixed
voltage version. The MCP1827/MCP1827S is based
upon the MCP1727 LDO device.
The MCP1827/MCP1827S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1827/MCP1827S is typically
less than 120 µA over the entire input voltage range,
making it attractive for portable computing applications
that demand high output current. The MCP1827
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
On the MCP1827 fixed output versions the
scaled-down output voltage is internally monitored and
a power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 200 µs (typical).
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
Package Types
Fixed/Adjustable 3-LD DDPAK
5-LD DDPAK
3-LD TO-220
5-LD TO-220
12345
12345
123
123
PWRGD
SHDN
VIN
GND(TAB)
VOUT
ADJ
SHDN
VIN
GND(TAB)
VOUT
VIN
GND(TAB)
VOUT
VIN
GND(TAB)
VOUT
MCP1827
MCP1827
MCP1827S MCP1827S
1.5A, Low Voltage, Low Quiescent Current LDO Regulator
MCP1827/MCP1827S
DS22001C-page 2 © 2007 Microchip Technology Inc.
Typical Application
MCP1827 Adjustable Output Voltage
MCP1827 Fixed Output Voltage
VOUT = 1.8V @ 1A
VIN = 2.3V to 2.8V
On
Off
1µF
100 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
PWRGD
20 kΩ
R2
VADJ
12345
VOUT = 1.2V @ 1A
VIN = 2.3V to 2.8V
On
Off
1µF
40 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
12345
© 2007 Microchip Technology Inc. DS22001C-page 3
MCP1827/MCP1827S
Functional Block Diagram - Adjustable Output
EA
+
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
ADJ
Undervoltage
Lock Out
VIN
Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
MCP1827/MCP1827S
DS22001C-page 4 © 2007 Microchip Technology Inc.
Functional Block Diagram - Fixed Output (5 pin)
EA
+
–
VOUT
PMOS
Rf
Cf
ISNS
VREF
Comp
92% of VREF
TDELAY
VIN
GND
Soft-Start
Sense
VIN
Reference
SHDN
SHDN
SHDN
PWRGD
Overtemperature
Driver w/limit
and SHDN
Undervoltage
Lock Out
Sensing
(UVLO)
© 2007 Microchip Technology Inc. DS22001C-page 5
MCP1827/MCP1827S
Functional Block Diagram - Fixed Output (3-Pin)
EA
+
–
VOUT
PMOS
Rf
Cf
ISNS
VREF
Comp
92% of VREF
TDELAY
VIN
GND
Soft-Start
Sense
VIN
Reference
SHDN
SHDN
SHDN
Overtemperature
Driver w/limit
and SHDN
Undervoltage
Lock Out
Sensing
(UVLO)
MCP1827/MCP1827S
DS22001C-page 6 © 2007 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN ....................................................................................6.5V
Maximum Voltage on Any Pin ..(GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ...........................+150°C
ESD protection on all pins (HBM/MM) ........... ≥ 2kV; ≥ 200V
† Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of
-40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Input Operating Voltage VIN 2.3 6.0 VNote 1
Input Quiescent Current Iq— 120 220 µA IL = 0 mA, VIN = Note 1,
VOUT = 0.8V to 5.0V
Input Quiescent Current for
SHDN Mode
ISHDN —0.1 3µA SHDN = GND
Maximum Output Current IOUT 1.5 —— AV
IN = 2.3V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation ΔVOUT/
(VOUT x ΔVIN)
—0.050.16 %/V (Note 1) ≤ VIN ≤ 6V
Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 %I
OUT = 1 mA to 1.5A,
VIN = Note 1, (Note 4)
Output Short Circuit Current IOUT_SC —2.2— AV
IN = Note 1, RLOAD <0.1Ω,
Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 VV
IN = 2.3V to VIN =6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ =0Vto6V
Adjust Temperature Coefficient TCVOUT —40—ppm/°CNote 3
Fixed-Output Characteristics (Fixed Output Only)
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUTMAX + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2007 Microchip Technology Inc. DS22001C-page 7
MCP1827/MCP1827S
Voltage Regulation VOUT VR - 2.5% VR
±0.5%
VR + 2.5% VNote 2
Dropout Characteristics
Dropout Voltage VIN-VOUT — 330 600 mV Note 5, IOUT = 1.5A,
VIN(MIN) =2.3V
Power Good Characteristics
PWRGD Input Voltage Operat-
ing Range
VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
1.2 —6.0 TA = -40°C to +125°C
For VIN < 2.3V, ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)
VPWRGD_TH %VOUT Falling Edge
89 92 95 VOUT < 2.5V Fixed, VOUT = Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L —0.20.4 VI
PWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage PWRGD_LK —1—nAV
PWRGD = VIN = 6.0V
PWRGD Time Delay TPG — 200 — µs Rising Edge
RPULLUP = 10 kΩ
Detect Threshold to PWRGD
Active Time Delay
TVDET-PWRGD — 200 — µs VADJ or VOUT = VPWRGD_TH +
20 mV to VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 %VIN VIN = 2.3V to 6.0V
Logic Low Input VSHDN-LOW 15 %VIN VIN = 2.3V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN = 6V, SHDN =VIN,
SHDN = GND
AC Performance
Output Delay From SHDN TOR 100 µs SHDN = GND to VIN
VOUT = GND to 95% VR
Output Noise eN—2.0—µV/√Hz IOUT = 200 mA, f = 1 kHz, COUT
= 10 µF (X7R Ceramic), VOUT =
2.5V
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of
-40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUTMAX + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1827/MCP1827S
DS22001C-page 8 © 2007 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Power Supply Ripple Rejection
Ratio
PSRR — 60 — dB f = 100 Hz, COUT = 10 µF,
IOUT = 10 mA,
VINAC = 30 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis ΔTSD —10—°CI
OUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Junction Temperature Range TJ-40 — +125 °C Steady State
Maximum Junction Temperature TJ— — +150 °C Transient
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5LD DDPAK θJA — 31.2 — °C/W 4-Layer JC51 Standard Board
Thermal Resistance, 3LD DDPAK θJA — 31.4 — °C/W 4-Layer JC51 Standard Board
Thermal Resistance, 5LD TO-220 θJA — 29.3 — °C/W 4-Layer JC51 Standard Board
Thermal Resistance, 3LD TO-220 θJA — 29.4 — °C/W 4-Layer JC51 Standard Board
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of
-40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUTMAX + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2007 Microchip Technology Inc. DS22001C-page 9
MCP1827/MCP1827S
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to
the desired Junction temperature. The test time is small enough such that the rise in Junction temperature over the
Ambient temperature is not significant.
FIGURE 2-1: Quiescent Current vs. Input
Voltage (1.2V Adjustable).
FIGURE 2-2: Ground Current vs. Load
Current (1.2V Adjustable).
FIGURE 2-3: Quiescent Current vs.
Junction Temperature (1.2V Adjustable).
FIGURE 2-4: Line Regulation vs.
Temperature (1.2V Adjustable).
FIGURE 2-5: Load Regulation vs.
Temperature (Adjstable Version).
FIGURE 2-6: Adjust Pin Voltage vs.
Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
90
100
110
120
130
140
150
23456
Input Voltage (V)
Quiescent Current (μA)
130°C
-45°C
25°C
90°C
VOUT = 1.2V Adj
IOUT = 0 mA
100
110
120
130
140
150
160
170
180
190
200
0 250 500 750 1000 1250 1500
Load Current (mA)
Ground Current (µA)
VIN=3.3V
VOUT = 1.2V Adj
VIN=5.0V
VIN=2.3V
100
105
110
115
120
125
130
135
140
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (μA)
VIN=5.0V VIN=2.5V
VIN=4.0V
IOUT = 0 mA
VOUT = 1.2V Adj
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
-45-20 5 305580105130
Temperature (°C)
Line Regulation (%/V)
VOUT
= 1.2V adj
VIN
= 2.3V to 6.0V
IOUT = 1 mA
IOUT = 500 mA
IOUT = 1000 mA
IOUT = 100 mA
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
-45-205 305580105130
Temperature (°C)
Load Regulation (%)
IOUT = 1.0 mA to 1500 mA
VOUT = 5.0V
VOUT = 3.3V
VOUT = 0.8V VOUT = 1.8V
0.408
0.409
0.409
0.410
0.410
0.411
-45 -20 5 30 55 80 105 130
Temperature (°C)
Adjust Pin Voltage (V)
IOUT = 1.0 mA
VIN = 6.0V
VIN = 2.3V
VIN = 5.0V
MCP1827/MCP1827S
DS22001C-page 10 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
FIGURE 2-7: Dropout Voltage vs. Load
Current (Adjustable Version).
FIGURE 2-8: Dropout Voltage vs.
Temperature (Adjustable Version).
FIGURE 2-9: Power Good (PWRGD)
Time Delay vs. Temperature (Adjustable
Version).
FIGURE 2-10: Quiescent Current vs. Input
Voltage (0.8V Fixed).
FIGURE 2-11: Quiescent Current vs. Input
Voltage (2.5V Fixed).
FIGURE 2-12: Ground Current vs. Load
Current.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0 250 500 750 1000 1250 1500
Load Current (mA)
Dropout Voltage (V)
VOUT = 2.5V Adj
VOUT = 5.0V Adj
0.30
0.32
0.34
0.36
0.38
0.40
0.42
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
VOUT = 3.3V Adj
VOUT = 5.0V Adj
VOUT = 2.5V Adj
IOUT = 1.5A
300
310
320
330
340
350
360
370
-45 -20 5 30 55 80 105 130
Temperature (°C)
Power Good Time Delay (µs)
VOUT = 3.3V Fixed
VIN = 3.9V
VIN = 5.0V
VIN = 4.5V
80
90
100
110
120
130
140
150
23456
Input Voltage (V)
Quiescent Current (μA)
-45°C
+130°C
+85°C
+25°C
VOUT = 0.8V
IOUT = 0 mA
80
90
100
110
120
130
140
150
33.544.555.56
Input Voltage (V)
Quiescent Current (μA)
VOUT = 2.5V
IOUT = 0 mA
+130°C
-45°C
+25°C
+90°C
0.00
50.00
100.00
150.00
200.00
250.00
0 250 500 750 1000 1250 1500
Load Current (mA)
Ground Current (μA)
VIN = 2.3V for VR
=0.8V
VIN = 3.1V for VR
=2.5V
VOUT=0.8V
VOUT=2.5V
© 2007 Microchip Technology Inc. DS22001C-page 11
MCP1827/MCP1827S
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
FIGURE 2-13: Quiescent Current vs.
Temperature.
FIGURE 2-14: ISHDN vs. Temperature.
FIGURE 2-15: Line Regulation vs.
Temperature (0.8V Fixed).
FIGURE 2-16: Line Regulation vs.
Temperature (2.5V Fixed).
FIGURE 2-17: Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
FIGURE 2-18: Load Regulation vs.
Temperature (VOUT ≥ 2.5V Fixed).
95
100
105
110
115
120
125
130
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (μA)
VOUT = 0.8V
VOUT = 2.5V
IOUT = 0 mA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-45 -20 5 30 55 80 105 130
Temperature (°C)
Ishdn (μA)
VIN = 2.3V
VIN = 4.0V
VIN = 6.0V
VR = 0.8V
0.00
0.02
0.04
0.06
0.08
0.10
-45-20 5 305580105130
Temperature (°C)
Line Regulation (%/V)
VOUT = 0.8V
VIN = 2.3V to 6.0V
IOUT = 1 mA
IOUT = 100 mA
IOUT = 500mA
IOUT = 1A
0.015
0.020
0.025
0.030
0.035
0.040
0.045
-45-205 305580105130
Temperature (°C)
Line Regulation (%/V)
IOUT = 1000 mA
IOUT = 1 mA
IOUT = 100 mA
IOUT = 1500 mA
IOUT = 500 mA
VR = 2.5V
VIN = 3.1 to 6.0V
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 0.8V
IOUT = 1 mA to 1500 mA
VIN
= 2.3V
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 2.5V
VOUT = 5.0V
IOUT = 1 mA to 1500 mA
MCP1827/MCP1827S
DS22001C-page 12 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
FIGURE 2-19: Dropout Voltage vs. Load
Current.
FIGURE 2-20: Dropout Voltage vs.
Temperature.
FIGURE 2-21: Short Circuit Current vs.
Input Voltage.
FIGURE 2-22: Output Noise Voltage
Density vs. Frequency.
FIGURE 2-23: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adj.).
FIGURE 2-24: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adj.).
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0 250 500 750 1000 1250 1500
Load Current (mA)
Dropout Voltage (V)
VOUT = 5.0V
VOUT = 2.5V
Temperature = 25°C
0.25
0.30
0.35
0.40
0.45
-45-20 5 305580105130
Temperature (°C)
Dropout Voltage (V)
IOUT
= 1.5A
VOUT = 2.5V
VOUT = 5.0V
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage (V)
Short Circuit Current (A)
VOUT
= 2.5V
Temperature = 25°
C
0.010
0.100
1.000
10.000
0.01 0.1 1 10 100 1000
Frequency (kHz)
Noise (µV/ √Hz)
VR=0.8V, VIN=2.3V
VR=3.3V, VIN=4.1V
COUT=1 μF ceramic X7R
CIN=10 μF ceramic
IOUT=200 mA
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
COUT=10 μF ceramic X7R
VIN=3.1V
CIN=0 μF
IOUT=10 mA
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
COUT=22 μF ceramic X7R
VIN=3.1V
CIN=0 μF
IOUT=10 mA
© 2007 Microchip Technology Inc. DS22001C-page 13
MCP1827/MCP1827S
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
FIGURE 2-25: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 3.3V
Fixed).
FIGURE 2-26: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 3.3V
Fixed).
FIGURE 2-27: 2.5V (Adj.) Startup from VIN.
FIGURE 2-28: 2.5V (Adj.) Startup from
Shutdown.
FIGURE 2-29: Power Good (PWRGD)
Timing.
FIGURE 2-30: Dynamic Line Response
(3.3V Fixed).
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=3.3V Fixed
COUT=10 μF ceramic X7R
VIN=3.9V
CIN=0 μF
IOUT=10 mA
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=3.3V Fixed
COUT=22 μF ceramic X7R
VIN=3.9V
CIN=0 μF
IOUT=10 mA
MCP1827/MCP1827S
DS22001C-page 14 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.
FIGURE 2-31: Dynamic Load Response
(3.3V Fixed, 10 mA to 1500 mA).
FIGURE 2-32: Dynamic Load Response
(3.3V Fixed, 100 mA to 1500 mA).
© 2007 Microchip Technology Inc. DS22001C-page 15
MCP1827/MCP1827S
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications have switching or noisy inputs tie the
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 200 µs (typical) from the
time the LDO output is within 92% + 3% (max
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed.
3.5 Output Voltage Adjust Input (ADJ)
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.6 Regulated Output Voltage (VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1827/MCP1827S is
stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
3.7 Exposed Pad (EP)
The DDPAK and TO-220 package have an exposed tab
on the package. A heat sink may be mount to the tab to
aid in the removal of heat from the package during
operation. The exposed tab is at the ground potential of
the LDO.
3-Pin Fixed
Output
5-Pin Fixed
Output
Adjustable
Output Name Description
—1 1 SHDN Shutdown Control Input (active-low)
122V
IN Input Voltage Supply
233GNDGround
344V
OUT Regulated Output Voltage
—5—PWRGD Power Good Output
—— 5 ADJ Voltage Adjust/Sense Input
Pad Pad Pad EP Exposed Pad of the Package (ground potential)
MCP1827/MCP1827S
DS22001C-page 16 © 2007 Microchip Technology Inc.
4.0 DEVICE OVERVIEW
The MCP1827/MCP1827S is a high output current,
Low Dropout (LDO) voltage regulator. The low dropout
voltage of 330 mV typical at 1.5A of current makes it
ideal for battery-powered applications. Unlike other
high output current LDOs, the MCP1827/MCP1827S
only draws a maximum of 220 µA of quiescent current.
The MCP1827 has a shutdown control input and a
power good output.
4.1 LDO Output Voltage
The 5-pin MCP1827 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for both versions.
The 3-pin MCP1827S LDO is available as a fixed
voltage device.
4.1.1 ADJUST INPUT
The adjustable version of the MCP1827 uses the ADJ
pin (pin 5) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1827. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
FIGURE 4-1: Typical adjustable output
voltage application circuit.
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving the equation for R1
yields the following equation:
EQUATION 4-2:
4.2 Output Current and Current
Limiting
The MCP1827/MCP1827S LDO is tested and ensured
to supply a minimum of 1.5A of output current. The
MCP1827/MCP1827S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
The MCP1827/MCP1827S also incorporates an output
current limit. If the output voltage falls below 0.7V due
to an overload condition (usually represents a shorted
load condition), the output current is limited to 2.2A
(typical). If the overload condition is a soft overload, the
MCP1827/MCP1827S will supply higher load currents
of up to 3A. The MCP1827/MCP1827S should not be
operated in this condition continuously as it may result
in failure of the device. However, this does allow for
device usage in applications that have higher pulsed
load currents having an average output current value of
1.5A or less.
Output overload conditions may also result in an
over-temperature shutdown of the device. If the
junction temperature rises above 150°C, the LDO will
shut down the output voltage. See Section 4.8
“Overtemperature Protection” for more information
on overtemperature shutdown.
4.3 Output Capacitor
The MCP1827/MCP1827S requires a minimum output
capacitance of 1 µF for output voltage stability. Ceramic
capacitors are recommended because of their size,
cost and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1827/MCP1827S to improve dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low-temperature applications of ≤ 25°C.
VOUT VADJ
R1R2
+
R2
------------------
⎝⎠
⎛⎞
=
Where:
VOUT = LDO Output Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
SHDN
GND
ADJ
2
1µF
VOUT
4.7 µF
VIN
On
Off R1
R2
C1
C2
MCP1827-ADJ
1345
R1R2
VOUT VADJ
–
VADJ
--------------------------------
⎝⎠
⎛⎞
=
Where:
VOUT = LDO Output Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
© 2007 Microchip Technology Inc. DS22001C-page 17
MCP1827/MCP1827S
4.4 Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 200 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
4.6 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
TPG
TVDET_PWRGD
VPWRGD_TH
VOUT
PWRGD
VOL
VOH
VIN
SHDN
VOUT
30 µs 70 µs
TOR
PWRGD
TPG
MCP1827/MCP1827S
DS22001C-page 18 © 2007 Microchip Technology Inc.
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See Figure 4-4 for a timing diagram of
the SHDN input.
FIGURE 4-4: Shutdown Input Timing
Diagram.
4.7 Dropout Voltage and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.6V differential applied. The
MCP1827/MCP1827S LDO has a very low dropout
voltage specification of 330 mV (typical) at 1.5A of out-
put current. See Section 1.0 “Electrical Characteris-
tics” for maximum dropout voltage specifications.
The MCP1827/MCP1827S LDO operates across an
input voltage range of 2.3V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that keeps
the LDO output voltage off until the input voltage
reaches a minimum of 2.18V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 2.04V (typical).
Since the MCP1827/MCP1827S LDO undervoltage
lockout activates at 2.04V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.9V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.3V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8 Overtemperature Protection
The MCP1827/MCP1827S LDO has tempera-
ture-sensing circuitry to prevent the junction tempera-
ture from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Cir-
cuits/Issues” for more information on LDO power
dissipation and junction temperature.
SHDN
VOUT
30 µs 70 µs
TOR
400 ns (typ)
© 2007 Microchip Technology Inc. DS22001C-page 19
MCP1827/MCP1827S
5.0 APPLICATION
CIRCUITS/ISSUES
5.1 Typical Application
The MCP1827/MCP1827S is used for applications that
require high LDO output current and a power good
output.
FIGURE 5-1: Typical Application Circuit.
5.1.1 APPLICATION CONDITIONS
5.2 Power Calculations
5.2.1 POWER DISSIPATION
The internal power dissipation within the
MCP1827/MCP1827S is a function of input voltage,
output voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipation for the LDO.
EQUATION 5-1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the
MCP1827/MCP1827S as a result of quiescent or
ground current. The power dissipation as a result of the
ground current can be calculated using the following
equation:
EQUATION 5-2:
The total power dissipated within the
MCP1827/MCP1827S is the sum of the power dissi-
pated in the LDO pass device and the P(IGND) term.
Because of the CMOS construction, the typical IGND for
the MCP1827/MCP1827S is 120 µA. Operating at a
maximum of 3.465V results in a power dissipation of
0.49 milli-Watts. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1827/MCP1827S is
+125°C. To estimate the internal junction temperature
of the MCP1827/MCP1827S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
EQUATION 5-3:
Package Type = TO-220-5
Input Voltage Range = 3.3V ± 5%
VIN maximum = 3.465V
VIN minimum = 3.135V
VDROPOUT (max) = 0.550V
VOUT (typical) = 2.5V
IOUT = 1.5A maximum
PDISS (typical) = 1.2W
Temperature Rise = 35.2°C
10 µF
VOUT = 2.5V @ 1.5A
R1C2
10 kΩ
PWRGD
SHDN
GND
2
4.7 µF
On
Off
C1
MCP1827-2.5
1345
3.3V VIN
PLDO VIN MAX)()
VOUT MIN()
–()IOUT MAX)()
×=
Where:
PLDO = LDO Pass device internal
power dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage
PIGND()
VIN MAX()
IVIN
×=
Where:
PI(GND = Power dissipation due to the
quiescent current of the LDO
VIN(MAX) = Maximum input voltage
IVIN = Current flowing in the VIN pin
with no LDO output current
(LDO quiescent current)
TJMAX()
PTOTAL RθJA
×TAMAX
+=
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
TAMAX = Maximum ambient temperature
MCP1827/MCP1827S
DS22001C-page 20 © 2007 Microchip Technology Inc.
The maximum power dissipation capability for a
package can be calculated given the
junction-to-ambient thermal resistance and the maxi-
mum ambient temperature for the application.
Equation 5-4 can be used to determine the package
maximum internal power dissipation.
EQUATION 5-4:
EQUATION 5-5:
EQUATION 5-6:
5.3 Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1 POWER DISSIPATION EXAMPLE
5.3.1.1 Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
PDMAX()
TJMAX()
TAMAX()
–()
RθJA
---------------------------------------------------=
PD(MAX) = Maximum device power dissipation
TJ(MAX) = maximum continuous junction
temperature
TA(MAX) = maximum ambient temperature
RθJA = Thermal resistance from junction to
ambient
TJRISE()
PDMAX()
RθJA
×=
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PD(MAX) = Maximum device power dissipation
RθJA = Thermal resistance from junction to
ambient
TJTJRISE()
TA
+=
TJ= Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA= Ambient temperature
Package
Package Type = TO-220-5
Input Voltage
VIN = 3.3V ± 5%
LDO Output Voltage and Current
VOUT = 2.5V
IOUT = 1.5A
Maximum Ambient Temperature
TA(MAX) =60°C
Internal Power Dissipation
PLDO(MAX) =(V
IN(MAX) – VOUT(MIN)) x IOUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 1.5A
PLDO =1.54 Watts
TJ(RISE) =P
TOTAL x RθJA
TJRISE = 1.54 W x 29.3° C/W
TJRISE = 45.12°C
© 2007 Microchip Technology Inc. DS22001C-page 21
MCP1827/MCP1827S
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
As you can see from the result, this application will be
operating within the maximum operating junction
temperature of 125°C.
5.3.1.3 Maximum Package Power
Dissipation at 60°C Ambient
Temperature
From this table you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.
TJ =T
JRISE + TA(MAX)
TJ = 45.12°C + 60.0°C
TJ = 105.12°C
TO-220-5 (29.3° C/W RθJA):
PD(MAX) = (125°C – 60°C) / 29.3° C/W
PD(MAX) = 2.218W
DDPAK-5 (31.2°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 31.2° C/W
PD(MAX) = 2.083W
MCP1827/MCP1827S
DS22001C-page 22 © 2007 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Example:
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3-Lead DDPAK (MCP1827S)
5-Lead DDPAK (Fixed) (MCP1827)
3-Lead TO-220 (MCP1827S)
5-Lead TO-220 (Adj) (MCP1827)
12345
12345
123
123
XXXXXXXXX
XXXXXXXXX
YYWWNNN
XXXXXXXXX
XXXXXXXXX
YYWWNNN
XXXXXXXXX
XXXXXXXXX
YYWWNNN
XXXXXXXXX
XXXXXXXXX
YYWWNNN
123
MCP1827S
0.8EEB^^
0630256
123
MCP1827S
12EAB^^
0630256
12345
MCP1827
1.0EET^^
0630256
12345
MCP1827
08EAT^^
0630256
Example:
Example:
Example:
3
e
3
e
3
e
© 2007 Microchip Technology Inc. DS22001C-page 23
MCP1827/MCP1827S
3-Lead Plastic (EB) [DD PAK]
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 3
Pitch e .100 BSC
Overall Height A .160 – .190
Standoff § A1 .000 – .010
Overall Width E .380 – .420
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Lead Thickness c .014 – .029
Pad Thickness C2 .045 – .065
Lower Lead Width b .020 – .039
Upper Lead Width b1 .045 – .070
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ0° – 8°
EE1
H
L1
D
D1
N
1
e
b
b1
c
C2
L
A
A1
BOTTOM VIEW
TOP VIEW
CHAMFER
OPTIONAL
φ
Microchip Technology Drawing C04-011B
MCP1827/MCP1827S
DS22001C-page 24 © 2007 Microchip Technology Inc.
3-Lead Plastic Transistor Outline (AB) [TO- 220]
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits M IN NOM MAX
Number of Pins N 3
Pitch e .100 BSC
Overall Pin Pitch e1 .200 BSC
Overall Height A .140 – .190
Tab Thickness A1 .020 – .055
Base to Lead A2 .080 – .115
Overall Width E .357 – .420
Mounting Hole Center Q .100 – .120
Overall Length D .560 – .650
Molded Package Length D1 .330 – .355
Tab Length H1 .230 – .270
Mounting Hole Diameter φP .139 – .156
Lead Length L .500 – .580
Lead Shoulder L1 – – .250
Lead Thickness c .012 – .024
Lead Width b .015 .027 .040
Shoulder Width b2 .045 .057 .070
E
Q
D
D1
L1
L
12
e
e1
b
b2
N
A2
c
H1
A1
A
P
CHAMFER
OPTIONAL
φ
Microchip Technology Drawing C04-034B
© 2007 Microchip Technology Inc. DS22001C-page 25
MCP1827/MCP1827S
5-Lead Plastic (ET) [DDPAK]
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and t oleranc ing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e .067 BSC
Overall Height A .160 – .190
Standoff § A1 .000 – . 010
Overall Width E .380 – .420
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Lead Thickness c .014 – . 029
Pad Thickness C2 .045 – .065
Lead Width b .020 – .039
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ0° – 8°
E
L1
D
D1
H
N
1
be
TOP VIEW
BOTTOM VIEW
A
A1 cL
C2
CHAMFER
OPTIONAL
E1
φ
Microchip Technology Drawing C04-012B
MCP1827/MCP1827S
DS22001C-page 26 © 2007 Microchip Technology Inc.
5-Lead Plastic Transistor Outline (AT) [TO- 220]
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e .067 BSC
Overall Pin Pitch e1 .268 BSC
Overall Height A .140 – .190
Overall Width E .380 – .420
Overall Length D .560 – .650
Molded Package Length D1 .330 – .355
Tab Length H1 .204 – .293
Tab Thickness A1 .020 – .055
Mounting Hole Center Q .100 – .120
Mounting Hole Diameter φP .139 – .156
Lead Length L .482 – .590
Base to Bottom of Lead A2 .080 – .1 15
Lead Thickness c .012 – .025
Lead Width b .015 .027 .040
E
Q
D
D1
H1
A
A1
A2
c
N
e
e1
b
123
L
CHAMFER
OPTIONAL
Pφ
Microchip Technology Drawing C04-036B
© 2007 Microchip Technology Inc. DS22001C-page 27
MCP1827/MCP1827S
APPENDIX A: REVISION HISTORY
Revision C (February 2007)
• Figure 2-22: Revised label on Y-axis.
•Section 2.0 “Typical Performance Curves”:
Added note on Junction Temperature.
• Pages 9-14: Revised notes.
Revision B (September 2006)
• Correction to maximum Dropout Voltage in
Section 1.0.
• Added additional graphs in Section 2.0.
• Added disclaimer to package outline drawings.
Revision A (July 2006)
• Original Release of this Document.
MCP1827/MCP1827S
DS22001C-page 28 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS22001C-page 29
MCP1827/MCP1827S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP1827: 1.5A Low Dropout Regulator
MCP1827T: 1.5A Low Dropout Regulator
Tape and Reel
MCP1827S: 1.5A Low Dropout Regulator
MCP1827ST: 1.5A Low Dropout Regulator
Tape and Reel
Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard”
18 = 1.8V “Standard”
25 = 2.5V “Standard”
30 = 3.0V “Standard”
33 = 3.3V “Standard”
50 = 5.0V “Standard”
*Contact factory for other output voltage options
Extra Feature Code: 0 = Fixed
Tolerance: 2 = 2.0% (Standard)
Temperature: E = -40°C to +125°C
Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead
AT = Plastic Transistor Outline, TO-220, 5-lead
EB = Plastic, DDPAK, 3-lead
ET = Plastic, DDPAK, 5-lead
PART NO. XXX
Output Feature
Code
Device
Voltage
X
Tolerance
X/
Temp.
XX
Package
Examples:
a) MCP1827-0802E/AT: 0.8V LDO Regulator
5LD TO-220
b) MCP1827-1002E/ET: 1.0V LDO Regulator
5LD DDPAK
c) MCP1827-1202E/AT: 1.2V LDO Regulator
5LD TO-220
d) MCP1827-1802E/AT: 1.8V LDO Regulator
5LD TO-220
e) MCP1827-2502E/ET: 2.5V LDO Regulator
5LD DDPAK
f) MCP1827-3002E/ET: 3.0V LDO Regulator
5LD DDPAK
g) MCP1827-3302E/AT 3.3V LDO Regulator
5LD TO-220
h) MCP1827-5002E/ET: 5.0V LDO Regulator
5LD DDPAK
i) MCP1827-ADJE/AT: ADJ LDO Regulator
5LD TO-220
a) MCP1827S-0802E/EB:0.8V LDO Regulator
3LD DDPAK
b) MCP1827S-0802E/AB:0.8V LDO Regulator
3LD TO-220
c) MCP1827S-1002E/EB:1.0V LDO Regulator
3LD DDPAK
d) MCP1827S-1202E/AB 1.2V LDO Regulator
3LD TO-220
e) MCP1827S-1802E/EB 1.8V LDO Regulator
3LD DDPAK
f) MCP1827S-2502E/EB 2.5V LDO Regulator
3LD DDPAK
g) MCP1827S-2502E/EB 3.0V LDO Regulator
3LD DDPAK
h) MCP1827S-3302E/AB 3.3V LDO Regulator
3LD TO-220
i) MCP1827S-5002E/EB 5.0V LDO Regulator
3LD DDPAK
j) MCP1827S-ADJE/AB ADJ LDO Regulator
3LD TO-220
MCP1827/MCP1827S
DS22001C-page 30 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS22001C-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS22001C-page 32 © 2007 Microchip Technology Inc.
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