SPICE Device Model Si4860DY Vishay Siliconix N-Channel Reduced Qg, Fast Switching MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70905 06-May-02 www.vishay.com 1 SPICE Device Model Si4860DY Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250A 1.7 ID(on) VDS 5V, VGS = 10V 694 VGS = 10V, ID = 16A 0.0065 0.0066 VGS = 4.5V, ID = 15A 0.0090 0.0090 Unit Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage Dynamic rDS(on) V A gfs VDS = 15V, ID = 16A 46 60 S VSD IS = 3A, VGS = 0V 0.74 0.70 V 14 13 b Total Gate Charge Qg Gate-Source Charge Qgs 5 5 Gate-Drain Charge Qgd 4 4 Turn-On Delay Time td(on) 16 18 20 12 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDS = 15V, VGS = 4.5V, ID = 16A VDD = 15V, RL = 15 ID 1A, VGEN = 10V, RG = 6 IF = 3A, di/dt = 100 A/s 45 46 69 19 35 40 nC Ns Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70905 06-May-02 SPICE Device Model Si4860DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70905 06-May-02 www.vishay.com 3