SPICE Device Model Si4860DY
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70905 www.vishay.com
06-May-02 1
N-Channel Reduced Qg, Fast Switching MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-to-10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
g
d model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model Si4860DY
Vishay Siliconix
www.vishay.com Document Number: 70905
206-May-02
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA1.7 V
On-State Drain CurrentaID(on) VDS ≥ 5V, VGS = 10V 694 A
VGS = 10V, ID = 16A 0.0065 0.0066
Drain-Source On-State ResistancearDS(on) VGS = 4.5V, ID = 15A 0.0090 0.0090 Ω
Forward Transconductanceagfs VDS = 15V, ID = 16A 46 60 S
Diode Forward VoltageaVSD IS = 3A, VGS = 0V 0.74 0.70 V
Dynamicb
Total Gate Charge Qg14 13
Gate-Source Charge Qgs 55
Gate-Drain Charge Qgd
VDS = 15V, VGS = 4.5V, ID = 16A
44
nC
Turn-On Delay Time td(on) 16 18
Rise Time tr20 12
Turn-Off Delay Time td(off) 45 46
Fall Time tf
VDD = 15V, RL = 15Ω
ID ≅ 1A, VGEN = 10V, RG = 6Ω
69 19
Source-Drain Reverse Recovery Time trr IF = 3A, di/dt = 100 A/µs35 40
Ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
SPICE Device Model Si4860DY
Vishay Siliconix
Document Number: 70905 www.vishay.com
06-May-02 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
