DUAL EPAD® PRECISION HIGH SLEW RATE CMOS OPERATIONAL AMPLIFIER
ADVANCED
LINEAR
DEVICES, INC.
ALD2724E/ALD2724
GENERAL DESCRIPTION
The ALD2724E/ALD2724 is a dual monolithic operational amplifier with
MOSFET input that has rail-to-rail input and output voltage ranges. The
input voltage range and output voltage range are very close to the positive
and negative power supply voltages. Typically the input voltage can be
beyond positive power supply voltage V+ or the negative power supply
voltage V- by up to 300mV. The output voltage swings to within 60mV of
either positive or negative power supply voltages at rated load.
With high impedance load, the output voltage of the ALD2724E/ALD2724
approaches within 1mV of the power supply rails. This device is designed
as an alternative to the popular J-FET input operational amplifier in
applications where lower operating voltages, such as 9V battery or ±3.25V
to ±5V power supplies are being used. The ALD2724E/ALD2724 offers
high slew rate of 5.0V/µs.
The rail-to-rail input and output feature of the ALD2724E/ALD2724 ex-
pands signal voltage range for a given operating supply voltage and allows
numerous analog serial stages to be implemented without losing operat-
ing voltage margin. The output stage is designed to drive up to 10mA into
400pF capacitive and 1.5KΩ resistive loads at unity gain and up to 4000pF
at a gain of 5. Short circuit protection to either ground or the power supply
rails is at approximately 15mA clamp current. Due to complementary
output stage design, the output can source and sink 10mA into a load with
symmetrical drive and is ideally suited for applications where push-pull
voltage drive is desired.
For each of the operational amplifier, the offset voltage is trimmed on-chip
to eliminate the need for external nulling in many applications. For
precision applications, the output is designed to settle to 0.1% in 2 µs. In
large signal buffer applications, the operational amplifier can function as
KEY FEATURES
• Factory pre-trimmed VOS
•V
OS = 25µV @ IOS = 0.01pA
• 5 V / µs slew rate
• EPAD ( Electrically Programmable Analog Device)
• Rail-to-rail input/output
• Each amplifier VOS can be user trimmed to
a different Vos level (optional)
• System level “calibration” capable
APPLICATIONS
• Sensor interface circuits
• Transducer biasing circuits
• Capacitive and charge integration circuits
• Biochemical probe interface
• Signal conditioning
• Portable instruments
• High source impedance electrode
amplifiers
• Precision Sample and Hold amplifiers
• Precision current to voltage converter
• Error correction circuits
• Sensor compensation circuits
• Precision gain amplifiers
• Periodic In-system calibration
• System output level shifter
PIN CONFIGURATION
* Contact factory for industrial temperature range
BENEFITS
• Ready to use off the shelf standard part
• Custom automated trimming optional
• Remote controlled automated trimming
• In-System Programming capable
• No external components
• No internal clocking noise source
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
• Low system implementation cost
©2002 Advanced Linear De vices, Inc. 415 T asman Dr ive, Sunn yvale , California 94089 -1706 T el: (408) 747-1155 F ax: (408) 747-1286 http://www .aldinc.com
ORDERING INFORMATION
Operating Temperature Range
-55°C to +125°C0°C to +70°C0°C to +70°C
14-Pin 14-Pin 14-Pin
CERDIP Small Outline Plastic Dip
Package Package (SOIC) Package
ALD2724E DB ALD2724E SB ALD2724E PB
ALD2724 DB ALD2724 SB ALD2724 PB
VE
2A
VE
1A
OUT
A
V+
OUT
B
VE
1B
VE
2B
+IN
A
N/C
V-
+IN
B
1
2
3
4
5
6
78
9
10
11
12
13
14
-IN
A
N/C
-IN
B
TOP VIEW
DB, PB, SB PACKAGE
2 Advanced Linear Devices ALD2724E/ALD2724
GENERAL DESCRIPTION (cont'd)
an ultra-high input impedance voltage follower/buffer that
allows input and output voltage swings from positive to
negative supply voltages. This feature is intended to greatly
simplify systems design and eliminate higher voltage power
supplies in many applications.
Each ALD2724E/ALD2724 operational amplifier features
individual, user-programmable offset voltage trimming re-
sulting in significantly enhanced total system performance
and user flexibility. EPAD technology is an exclusive ALD
design which has been refined for analog applications where
precision voltage trimming is necessary to achieve a desired
performance. It utilizes CMOS FETs as in-circuit elements
for trimming of offset voltage bias characteristics with the aid
of a personal computer under software control. Once
programmed, the set parameters are stored indefinitely.
EPAD offers the circuit designer a convenient and cost-
effective trimming solution for achieving the very highest
amplifier/system performance.
FUNCTIONAL DESCRIPTION
The ALD2724E/ALD2724 utilizes EPADs as in-circuit ele-
ments for trimming of offset voltage bias characteristics.
Each ALD2724E/ALD2724 operational amplifier has a pair of
EPAD-based circuits connected such that one circuit is used
to adjust VOS in one direction and the other circuit is used
to adjust VOS in the other direction. While each of the basic
EPAD device is a monotonically adjustable (offset voltage
trimming) programmable device, the VOS of the ALD2724E
can be adjusted many times in both directions. Once pro-
grammed, the set VOS levels are stored permanently, even
when the device power is removed.
Functional Description of ALD2724E/ALD2724
The ALD2724E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage pro-
gram range, which is ideal for applications that require
electrical offset voltage programming.
The ALD2724E is an operational amplifier that can be
trimmed stand-alone, with user application-specific pro-
gramming or in-system programming conditions. User appli-
cation-specific circuit programming refers to a situation
where the Total Input Offset Voltage of the ALD2724E can be
trimmed with the actual intended operating conditions.
Take the example of an application circuit that uses + 5V and
-5V power supplies, an operational amplifier input biased at
+1V, and an average operating temperature at +85°C; the
circuit can be wired up to these conditions within an environ-
mental chamber with the ALD2724E inserted into a test
socket while it is being electrically trimmed. Any error in VOS
due to these bias conditions can be automatically zeroed out.
The Total VOS error, VOST, is now limited only by the
adjustable range and the stability of VOS, and the input noise
voltage of the operational amplifier. This Total Input Offset
Voltage now includes VOS, as VOS is traditionally specified;
plus the VOS error contributions from PSRR, CMRR,
TCVOS, and noise. Typically, VOST ranges approximately
±25µV for the ALD2724E.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD2724E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD2724E to operate in both normal
mode and in programming mode. One of the benefits of in-
system programming is that not only the ALD2724E offset
voltage from operating bias conditions has been accounted
for, any residual errors introduced by other circuit compo-
nents, such as resistor or sensor induced voltage errors, can
also be programmed and corrected. In this way, the “in-
system” circuit output can be adjusted to a desired level
eliminating need for another trimming function.
The ALD2724 is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. The ALD2724 offers similar programmable
features as the ALD2724E, but with more limited offset
voltage program range. It is intended for standard
operational amplifier applications where little or no electrical
programming by the user is necessary.
USER PROGRAMMABLE VOS FEATURE
Each ALD2724E/ALD2724 has four additional pins,
compared to a conventional dual operational amplifier which
has eight pins. These four additional pins are named VE1A,
VE2A for op amp A and VE1B, VE2B for op amp B. Each of
these pins VE1A, VE2A, VE1B, VE2B (represented by
VExx) are connected to a separate, internal offset bias
circuit. VExx pins have initial internal bias voltage values of
approximately 1 to 2 Volts. The voltage on these pins can be
programmed using the ALD E100 EPAD Programmer and
the appropriate Adapter Module. The useful programming
range of voltages on VExx pins are 1 Volt to 4 Volts.
VExx pins are programming pins, used during electrical
programming mode to inject charge into the internal EPADs.
Increasing voltage on VE1A/VE1B decreases the offset
voltage whereas increasing voltage on VE2A/VE2B in-
creases the offset voltage of op amp A and op amp B,
respectively.
During programming, voltages on VExx pins are increased
incrementally to program the offset voltage of the opera-
tional amplifier to the desired VOS. Note that desired V OS
can be any value within the offset voltage programmable
ranges, and can be either equal zero, a positive value or a
negative value. This VOS value can also be reprogrammed
to a different value at a later time, provided that the useful
VE1x or VE2x programming voltage range has not been
exceeded. The injected charge is then permanently stored.
After programming, VExx pins must be left open in order for
these voltages to remain at the programmed levels.
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
While programming, V+, VE1 and VE2 pins may be alter-
nately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD2722E application circuit to accommodate these
programming pulses. If needed, this requirement can be
accomplished by adding resistors at certain appropriate
circuit nodes.
ALD2724E/ALD2724 Advanced Linear Devices 3
Supply voltage, V+ 13.2V
Differential input voltage range -0.3V to V+ +0.3V
Power dissipation 600 mW
Operating temperature range PB,SB package 0°C to +70°C
DB package -55°C to +125°C
Storage temperature range -65°C to +150 °C
Lead temperature, 10 seconds +260°C
ABSOLUTE MAXIMUM RATINGS
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25oC VS = ±5.0V unless otherwise specified
2724E 2724
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Supply Voltage VS±3.25 ±5.25 ±3.25 ±5.25 V
V+6.5 10.5 6.5 10.5 V Single Supply
Input Offset Voltage1VOS i 25 100 40 150 µVR
S
≤ 100KΩ
Offset Voltage Program Range 2∆VOS ±5±7±0.5 ±2mV
Programmed Input Offset VOS 25 100 40 150 µV At user specified
Voltage Error3target offset voltage
Total Input Offset Voltage 4VOST 25 100 40 150 µV At user specified
target offset voltage
Input Offset Current 5IOS 0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C
Input Bias Current 5IB0.01 10 0.01 10 pA TA = 25°C
240 240 pA 0°C ≤ TA ≤ +70°C
Input Voltage Range 6VIR -0.3 5.3 -0.3 5.3 V V+ = +5V
-2.8 +2.8 -2.8 +2.8 V VS = ±2.5V
Input Resistance RIN 1014 1014 Ω
Input Offset Voltage Drift 7TCVOS 55µV/°CR
S ≤ 100KΩ
Initial Power Supply PSRR i85 85 dB RS ≤ 100KΩ
Rejection Ratio 8
Initial Common Mode CMRR i90 90 dB RS ≤ 100KΩ
Rejection Ratio 8
Large Signal Voltage Gain AV150 150 V/mV RL =10KΩ
V/mV 0°C ≤ TA ≤ +70°C
VO low -4.998 -4.99 -4.998 -4.99 V RL =1MΩ V =5V
Output Voltage Range VO high 4.99 4.998 4.99 4.998 V 0°C ≤ TA ≤ +70°C
VO low -4.96 -4.90 -4.96 -4.90 V RL =10KΩ
VO high 4.90 4.95 4.90 4.95 V 0°C ≤ TA ≤ +70°C
Output Short Circuit Current ISC 15 15 mA
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
4 Advanced Linear Devices ALD2724E/ALD2724
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
TA = 25oC VS = ±5.0V unless otherwise specified
2724E 2724
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Supply Current IS5.0 6.5 5.0 6.5 mA VIN = 0V
No Load
Power Dissipation PD65 65 mW VS = ±2.5V
Input Capacitance CIN 11
pF
Maximum Load Capacitance CL 400 400 pF Gain = 1
4000 4000 pF Gain = 5
Equivalent Input Noise Voltage en26 26 nV/√Hz f = 1KHz
Equivalent Input Noise Current in0.6 0.6 fA/√Hz f =10Hz
Bandwidth BW2.1 2.1 MHz
Slew Rate SR5.0 5.0 V/µsA
V
= +1
RL = 2KΩ
Rise time tr0.1 0.1 µsR
L = 2KΩ
Overshoot Factor 15 15 % RL=2KΩ
CL=100pF
Settling Time tS22µs 0.1% AV = -1
RL= 5KΩ
CL = 50pF
Channel Separation CS 140 140 dB AV = 100
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
TA = 25oC VS = ±5.0V unless otherwise specified
2724E 2724
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Average Long Term Input Offset ∆ VOS 0.02 0.02 µV/
Voltage Stability 9∆ time 1000 hrs
Initial VE Voltage VE1 i, VE2 i1.4 2.5 V
Programmable Change of ∆VE1, ∆VE2 1.5 2.0 0.5 V
VE Range
Programmed VE Voltage Error e(VE1-VE2) 0.1 0.1 %
VE Pin Leakage Current ieb -5 -5 µA
ALD2724E/ALD2724 Advanced Linear Devices 5
VS = ±5.0V -55°C ≤ TA ≤ +125°C unless otherwise specified
2724E 2724
Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions
Initial Input offset Voltage VOS i 0.7 0.7 mV RS ≤ 100KΩ
Input Offset Current IOS 2.0 2.0 nA
Input Bias Current IB2.0 2.0 nA
Initial Power Supply PSRR i85 85 dB RS ≤ 100KΩ
Rejection Ratio 8
Initial Common Mode CMRR i97 97 dB RS ≤ 100KΩ
Rejection Ratio 8
Large Signal Voltage Gain AV10 25 10 25 V/mV RL = 10KΩ
Output Voltage Range VO low -4.9 -4.8 -4.9 -4.8 V
VO high 4.8 4.9 4.8 4.9 V RL = 10KΩ
6 Advanced Linear Devices ALD2724E/ALD2724
TYPICAL PERFORMANCE CHARACTERISTICS
CHANGE IN INPUT OFFSET VOLTAGE AS
A FUNCTION OF CHANGE IN VE1 AND VE2
CHANGE IN INPUT OFFSET
VOLTAGE ∆V
OS
(mV)
0 0.5 1.0 1.5 2.0 2.5 3.0
-10
-8
-6
-4
-2
0
2
4
6
8
10
VE2
VE1
CHANGE IN VE1 AND VE2 (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1000
100
10
0.1
1.0
INPUT BIAS CURRENT (pA)
100-25 0 75 1255025-50
V
S
= ±5.0V
10000
OPEN LOOP VOLTAGE AS A FUNCTION
OF FREQUENCY
FREQUENCY (Hz)
1 10 100 1K 10K 1M 10M100K
120
100
80
60
40
20
0
-20
OPEN LOOP VOLTAGE
GAIN (dB)
90
0
45
180
135
PHASE SHIFT IN DEGREES
V
S
= ±5.0V
T
A
= 25°C
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
COMMON MODE INPUT
VOLTAGE RANGE (V)
±7
±6
±5
±4
±3
±2±2 ±3 ±4 ±5 ±6 ±7
T
A
= 25°C
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE
(
V
)
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
0 ±2 ±4 ±6
RL = 10KΩ
R
L
= 5KΩ
} -55°C
} +25°C
} +125°C
±8
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
0±1±2±3±4±5±6
INPUTS GROUNDED
OUTPUT UNLOADED
+80°C
+25°C
T
A
= -55°C
-25°C
±7
1
2
3
4
5
6
7
8
+125°C
ALD2724E/ALD2724 Advanced Linear Devices 7
TYPICAL PERFORMANCE CHARACTERISTICS
-2500 -2000 -1500 -1000 -500 0500 1000 1500 2000 2500
TOTAL INPUT OFFSET VOLTAGE (µV)
100
80
60
40
20
0
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
EXAMPLE B:
V
OST
AFTER EPAD
PROGRAMMING
V
OST
TARGET = -750µV
EXAMPLE A:
V
OST
AFTER EPAD
PROGRAMMING
V
OST
TARGET = 0.0µV
V
OST
BEFORE EPAD
PROGRAMMING
PERCENTAGE OF UNITS (%)
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
LOAD RESISTANCE (Ω)
1K 10K 1000K100K
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
V
S
= ±5.0V
T
A
= 25°C
LARGE - SIGNAL TRANSIENT
RESPONSE
V
S
= ±5.0V
T
A
= 25°C
R
L
= 1KΩ
C
L
= 50pF
5V/div
5V/div 2µs/div
SMALL - SIGNAL TRANSIENT
RESPONSE
V
S
= ± 5.0V
T
A
= 25°C
R
L
= 1.0KΩ
C
L
= 50pF
100mV/div
50mV/div 1µs/div
RL = 10KΩ
OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
±3
0±1±2±3±4±5±6±7
R
L
= 2KΩ
±6
±5
±4
±2
±7
±25°C ≤ T
A
≤ 125°C
R
L
= 10KΩ
8 Advanced Linear Devices ALD2724E/ALD2724
0123456789 10
500
400
300
200
100
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE (µV)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
PSRR = 80 dB
EXAMPLE B:
V
OS
EPAD
PROGRAMMED
AT V
SUPPLY
= +8V
EXAMPLE A:
V
OS
EPAD PROGRAMMED
AT V
SUPPLY
= +5V
-5 -4 -3 -2 -1 012345
COMMON MODE VOLTAGE (V)
500
400
300
200
100
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VIN = 0V
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VIN = -4.3V
EXAMPLE C:
VOS EPAD PROGRAMMED
AT VIN = +5V
VSUPPLY = ±5V
CMRR = 80dB
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
COMMON MODE VOLTAGE (V)
50
40
30
20
10
0
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
V
OS
EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
CMRR = 80dB
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
COMMON MODE VOLTAGE RANGE OF 0.5V
ALD2724E/ALD2724 Advanced Linear Devices 9
Total Input V
OS
after EPAD
Programming
+
Device input V
OS
PSRR equivalent V
OS
CMRR equivalent V
OS
T
A
equivalent V
OS
Noise equivalent V
OS
External Error equivalent V
OS
X
EXAMPLE A
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
+
X
EXAMPLE B
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
EXAMPLE C
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
V
OS
BUDGET AFTER
EPAD PROGRAMMING
EXAMPLE D
TOTAL INPUT OFFSET VOLTAGE (µV)
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
+
X
V
OS
BUDGET AFTER
EPAD PROGRAMMING
V
OS
BUDGET BEFORE
EPAD PROGRAMMING
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
10 Advanced Linear Devices ALD2724E/ALD2724
DEFINITIONS AND APPLICATION NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD2724E/ALD2724 operational amplifier when shipped from
the factory. The device has been pre-programmed and tested
for programmability.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the negative or positive direction of the input offset
voltage from an initial input offset voltage. The input offset
programming pins, VE1A/VE1B or VE2A/VE2B change the
input offset voltages in the negative or positive direction, for
each of the amplifier A or B, respectively. User specified target
offset voltage can be any offset voltage within this programming
range.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVOS and noise. It can also include errors
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD2724E/
ALD2724, the switching point between the two stages occur at
approximately 1.5V above negative supply voltage.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25 °C, assuming activation energy of
1.0eV. This parameter is sample tested.
DESIGN NOTES:
A. The ALD2724E/ALD2724 is internally compensated for unity
gain stability using a novel scheme which produces a single pole
role off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD2724E/ALD2724 will typically drive 400pF
of external load capacitance.
B. The ALD2724E/ALD2724 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail-to-rail input common mode voltage range. The
switching point between the two differential stages is 1.5V
above negative supply voltage. For applications such as invert-
ing amplifier or non-inverting amplifier with a gain larger than 2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
does take place if the operational amplifier is connected as a rail-
to-rail unity gain buffer and the design must allow for input offset
voltage variations.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail-
to-rail input and output feature, makes the ALD2724E/ALD2724
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.
D. The ALD2724E/ALD2724 has static discharge protection.
Care must be exercised when handling the device to avoid
strong static fields that may degrade a diode junction, causing
increased input leakage currents. The user is advised to power
up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
E. VExx are high impedance terminals, as the internal bias
currents are set very low to a few microamperes to conserve
power. For some applications, these terminals may need to be
shielded from external coupling sources. For example, digital
signals running nearby may cause unwanted offset voltage
fluctuations. Care during the printed circuit board layout to place
ground traces around these pins and to isolate them from digital
lines will generally eliminate such coupling effects. In addition,
optional decoupling capacitors of 1000pF or greater value can
be added to VExx terminals.
F. The ALD2724E/ALD2724 is designed for use in low voltage,
micropower circuits. The maximum operating voltage during
normal operation should remain below 10 Volts at all times. Care
should be taken to insure that the application in which the device
is used do not experience any positive or negative transient
voltages that will cause any of the terminal voltages to exceed
this limit.
G. All inputs or unused pins except VExx pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.
