DRB-8 D-8 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B DGN-8 DBV-5 D-16 www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES FEATURES APPLICATIONS * * * * * * 1 2 * * * * * * * * * 70-m High-Side MOSFET 500-mA Continuous Current Thermal and Short-Circuit Protection Accurate Current Limit (0.75 A min, 1.25 A max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up Maximum Standby Supply Current: 1-A (Single, Dual) or 2-A (Triple, Quad) Ambient Temperature Range: -40C to 85C UL Recognized, File Number E169910 Additional UL Recognition for TPS2042B and TPS2052B for Ganged Configuration Heavy Capacitive Loads Short-Circuit Protections TPS2041B/TPS2051B D AND DGN PACKAGES (TOP VIEW) TPS2041B/TPS2051B DBV PACKAGE (TOP VIEW) OUT GND IN IN IN GND OC EN TPS2042B/TPS2052B DRB PACKAGES (TOP VIEW) OC1 GND 1 8 IN 2 7 OUT1 EN1 3 6 OUT2 EN2 4 5 OC2 EN 1 8 2 7 3 6 4 5 OUT OUT OUT OC TPS2043B/TPS2053B D PACKAGE (TOP VIEW) GND IN1 EN1 1 16 2 15 3 14 EN2 GND IN2 EN3 4 13 5 12 6 11 7 10 NC 8 9 OC1 OUT1 OUT2 OC2 OC3 OUT3 NC NC TPS2042B/TPS2052B D AND DGN PACKAGES (TOP VIEW) GND IN EN1 EN2 1 8 2 7 3 6 4 5 OC1 OUT1 OUT2 OC2 TPS2044B/TPS2054B D PACKAGE (TOP VIEW) GND IN1 EN1 1 16 2 15 3 14 EN2 GND IN2 EN3 4 13 5 12 EN4 6 11 7 10 8 9 OC1 OUT1 OUT2 OC2 OC3 OUT3 OUT4 OC4 All enable inputs are active high for the TPS205xB series. NC - No connect DESCRIPTION The TPS204xB/TPS205xB power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. These devices incorporates 70-m N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A typically. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2008, Texas Instruments Incorporated TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTION AND ORDERING INFORMATION TA ENABLE -40C to 85C (1) (2) TYPICAL SHORTCIRCUIT CURRENT LIMIT AT 25C RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT PACKAGED DEVICES (1) (2) NUMBER OF SWITCHES MSOP (DGN) SOIC (D) SOT-23 (DBV) SON (DRB) Active low Single TPS2041BDGN TPS2041BD TPS2041BDBV Active high Single TPS2051BDGN TPS2051BD TPS2051BDBV Active low Dual TPS2042BDGN TPS2042BD TPS2042BDRB Active high Dual TPS2052BDGN TPS2052BD TPS2052BDRB Triple -- TPS2043BD Active high Triple -- TPS2053BD Active low Quad -- TPS2044BD Active high Quad -- TPS2054BD 0.5 A Active low 1A The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2042BDR) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Input voltage range, VI(IN), VI(INx) (2) -0.3 V to 6 V Output voltage range, VO(OUT), VO(OUTx) (2) -0.3 V to 6 V Input voltage range, VI(EN), VI(ENx), VI(EN), VI(ENx) -0.3 V to 6 V Voltage range, VI(/OC), VI(OCx) -0.3 V to 6 V Continuous output current, IO(OUT), IO(OUTx) Internally limited Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ -40C to 125C Storage temperature range, Tstg -65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds Electrostatic discharge (ESD) protection (1) (2) 260C Human body model MIL-STD-883C 2 kV Charge device model (CDM) 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATING RATING TABLE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING DGN-8 1712.3 mW 17.123 mW/C 941.78 mW 684.93 mW D-8 585.82 mW 5.8582 mW/C 322.20 mW 234.32 mW D-16 898.47 mW 8.9847 mW/C 494.15 mW 359.38 mW PACKAGE THERMAL RESISTANCE, JA 285 mW 2.85 mW/C 155 mW 114 mW DRB-8 (Low-K) (1) DBV-5 270 CW 370 mW 3.71 mW/C 203 mW 148 mW DRB-8 (High-K) (2) 60 CW 1600 mW 16.67 mW/C 916 mW 866 mW (1) (2) 2 Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details. Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 RECOMMENDED OPERATING CONDITIONS MIN MAX Input voltage, VI(IN), VI(INx) UNIT 2.7 5.5 Input voltage, VI(EN), VI(ENx), VI(EN), VI(ENx) 0 5.5 V Continuous output current, IO(OUT), IO(OUTx) 0 500 mA -40 125 C Operating virtual junction temperature, TJ V ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT POWER SWITCH Static drain-source on-state VI(IN) = 5 V or 3.3 V, IO = 0.5 A, resistance, 5-V operation -40C TJ 125C and 3.3-V operation rDS(on) tr (2) tf D and DGN packages 70 135 DBV package only 95 140 Static drain-source on-state VI(IN) = 2.7 V, IO = 0.5 A, resistance, 2.7-V -40C TJ 125C operation (2) D and DGN packages 75 150 m Static drain-source on-state VI(IN) = 5 V, IO = 1.0 A, OUT1 and OUT2 resistance, 5-V operation connected, 0C TJ 70C DGN package, TPS2042B/52B 49 (3) m Rise time, output (2) Fall time, output VI(IN) = 5.5 V VI(IN) = 2.7 V VI(IN) = 5.5 V 0.6 CL = 1 F, RL = 10 1.5 0.4 TJ = 25C VI(IN) = 2.7 V m 1 0.05 0.5 0.05 0.5 ms ENABLE INPUT EN AND ENx VIH High-level input voltage 2.7 V VI(IN) 5.5 V VIL Low-level input voltage 2.7 V VI(IN) 5.5 V II 2 0.8 Input current VI(ENx) = 0 V or 5.5 V (2) Turnon time CL = 100 F, RL = 10 3 toff (2) Turnoff time CL = 100 F, RL = 10 10 ton -0.5 0.5 V A ms CURRENT LIMIT IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit TJ = 25C VI(IN) = 5 V, OUT1 and OUT2 connected to GND, device enabled into short-circuit, measure at IN 0C TJ 70C TPS2042B/52B, DGN package -40C TJ 125C 0.75 1 1.25 0.7 1 1.3 A 1.5 (3) SUPPLY CURRENT (TPS2041B, TPS2051B) Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V, or VI(ENx) = 0 V TJ = 25C 0.5 1 -40C TJ 125C 0.5 5 Supply current, high-level output No load on OUT, VI(ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25C 43 60 -40C TJ 125C 43 70 Leakage current OUT connected to ground, VI(ENx) = 5.5 V, or VI(ENx) = 0 V -40C TJ 125C 1 A TJ = 25C 0 A Reverse leakage current (1) (2) (3) VI(OUTx) = 5.5 V, IN = ground (2) A A Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Not tested in production, specified by design. Estimated value. Final value pending characterization. Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 3 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT SUPPLY CURRENT (TPS2042B, TPS2052B) TJ = 25C 0.5 1 -40C TJ 125C 0.5 5 TJ = 25C 50 70 -40C TJ 125C 50 90 A Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V Supply current, high-level output No load on OUT, VI(ENx) = 0 V Leakage current OUT connected to ground, VI(ENx) = 5.5 V -40C TJ 125C 1 A Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (4) TJ = 25C 0.2 A TJ = 25C 0.5 2 -40C TJ 125C 0.5 10 TJ = 25C 65 90 -40C TJ 125C 65 110 A SUPPLY CURRENT (TPS2043B, TPS2053B) A Supply current, low-level output No load on OUT, VI(ENx) = 0 V Supply current, high-level output No load on OUT, VI(ENx) = 5.5 V Leakage current OUT connected to ground, VI(ENx) = 0 V -40C TJ 125C 1 A Reverse leakage current VI(OUTx) = 5.5 V, INx = ground (4) TJ = 25C 0.2 A A SUPPLY CURRENT (TPS2044B, TPS2054B) Supply current, low-level output No load on OUT, VI(ENx) = 5.5 V, or VI(ENx) = 0 V TJ = 25C 0.5 2 -40C TJ 125C 0.5 10 Supply current, high-level output No load on OUT, VI(ENx) = 0 V, or VI(ENx) = 5.5 V TJ = 25C 75 110 -40C TJ 125C 75 140 Leakage current OUT connected to ground, VI(ENx) = 5.5 V, or VI(ENx) = 0 V -40C TJ 125C 1 A Reverse leakage current VI(OUTx) = 5.5 V, INx = ground (4) TJ = 25C 0.2 A A A UNDERVOLTAGE LOCKOUT Low-level input voltage, IN, INx Hysteresis, IN, INx 2 TJ = 25C 2.5 75 V mV OVERCURRENT OC and OCx Output low voltage, VOL(/OCx) IO(OCx) = 5 mA Off-state current (4) VO(OCx) = 5 V or 3.3 V OC deglitch (4) THERMAL SHUTDOWN OCx assertion or deassertion 4 8 0.4 V 1 A 15 ms (5) Thermal shutdown threshold (4) 135 C Recovery from thermal shutdown (4) 125 C Hysteresis (4) (5) 4 (4) 10 C Not tested in production, specified by design. The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 DEVICE INFORMATION Terminal Functions (TPS2041B and TPS2051B) TERMINAL D AND DGN PACKAGE NAME DBV PACKAGE I/O DESCRIPTION TPS2041B TPS2051B TPS2041B TPS2051B EN 4 - 4 - I Enable input, logic low turns on power switch EN - 4 - 4 I Enable input, logic high turns on power switch GND 1 1 2 2 IN 2, 3 2, 3 5 5 I Input voltage OC 5 5 3 3 O Overcurrent open-drain output, active-low 6, 7, 8 6, 7, 8 1 1 O Power-switch output OUT Ground Functional Block Diagram (TPS2041B and TPS2051B) (See Note A) CS IN OUT Charge Pump EN (See Note B) Driver Current Limit OC UVLO GND Thermal Sense Deglitch Note A: Current sense Note B: Active low (EN) for TPS2041B; Active high (EN) for TPS2051B Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 5 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Terminal Functions (TPS2042B and TPS2052B) TERMINAL D, DGN, and DRB PACKAGES NAME I/O DESCRIPTION TPS2042B TPS2052B EN1 3 - I Enable input, logic low turns on power switch IN-OUT1 EN2 4 - I Enable input, logic low turns on power switch IN-OUT2 EN1 - 3 I Enable input, logic high turns on power switch IN-OUT1 EN2 - 4 I Enable input, logic high turns on power switch IN-OUT2 GND 1 1 IN 2 2 I Input voltage OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 7 O Power-switch output, IN-OUT1 OUT2 6 6 O Power-switch output, IN-OUT2 PowerPADTM - - Ground Internally connected to GND; used to heat-sink the part to the circuit board traces. Should be connected to GND pin. Functional Block Diagram (TPS2042B and TPS2052B) OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit Charge Pump (See Note A) CS OUT1 UVLO (See Note A) IN CS OUT2 Charge Pump Driver Current Limit OC2 EN2 (See Note B) Thermal Sense Deglitch Note A: Current sense Note B: Active low (ENx) for TPS2042B; Active high (ENx) for TPS2052B 6 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 Terminal Functions (TPS2043B and TPS2053B) TERMINAL NAME I/O DESCRIPTION TPS2043B TPS2053B EN1 3 -- I Enable input, logic low turns on power switch IN1-OUT1 EN2 4 -- I Enable input, logic low turns on power switch IN1-OUT2 EN3 7 -- I Enable input, logic low turns on power switch IN2-OUT3 EN1 -- 3 I Enable input, logic high turns on power switch IN1-OUT1 EN2 -- 4 I Enable input, logic high turns on power switch IN1-OUT2 EN3 -- 7 I Enable input, logic high turns on power switch IN2-OUT3 GND 1, 5 1, 5 IN1 2 2 I Ground Input voltage for OUT1 and OUT2 IN2 6 6 I Input voltage for OUT3 NC 8, 9, 10 8, 9, 10 OC1 16 16 O No connection Overcurrent, open-drain output, active low, IN1-OUT1 OC2 13 13 O Overcurrent, open-drain output, active low, IN1-OUT2 OC3 12 12 O Overcurrent, open-drain output, active low, IN2-OUT3 OUT1 15 15 O Power-switch output, IN1-OUT1 OUT2 14 14 O Power-switch output, IN1-OUT2 OUT3 11 11 O Power-switch output, IN2-OUT3 Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 7 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Functional Block Diagram (TPS2043B and TPS2053B) OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit (See Note A) CS OUT1 UVLO (See Note A) IN1 OUT2 CS Driver Current Limit OC2 EN2 (See Note B) VCC Selector Thermal Sense Deglitch Charge Pump (See Note A) IN2 CS EN3 Driver OUT3 Current Limit (See Note B) OC3 UVLO GND Deglitch Thermal Sense Note A: Current sense Note B: Active low (ENx) for TPS2043B; Active high (ENx) for TPS2053B 8 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 Terminal Functions (TPS2044B and TPS2054B) TERMINAL NAME I/O DESCRIPTION TPS2044B TPS2054B EN1 3 - I Enable input, logic low turns on power switch IN1-OUT1 EN2 4 - I Enable input, logic low turns on power switch IN1-OUT2 EN3 7 - I Enable input, logic low turns on power switch IN2-OUT3 EN4 8 - I Enable input, logic low turns on power switch IN2-OUT4 EN1 - 3 I Enable input, logic high turns on power switch IN1-OUT1 EN2 - 4 I Enable input, logic high turns on power switch IN1-OUT2 EN3 - 7 I Enable input, logic high turns on power switch IN2-OUT3 EN4 - 8 I Enable input, logic high turns on power switch IN2-OUT4 GND 1, 5 1, 5 IN1 2 2 I Input voltage for OUT1 and OUT2 IN2 6 6 I Input voltage for OUT3 and OUT4 OC1 16 16 O Overcurrent, open-drain output, active low, IN1-OUT1 OC2 13 13 O Overcurrent, open-drain output, active low, IN1-OUT2 OC3 12 12 O Overcurrent, open-drain output, active low, IN2-OUT3 OC4 9 9 O Overcurrent, open-drain output, active low, IN2-OUT4 OUT1 15 15 O Power-switch output, IN1-OUT1 OUT2 14 14 O Power-switch output, IN1-OUT2 OUT3 11 11 O Power-switch output, IN2-OUT3 OUT4 10 10 O Power-switch output, IN2-OUT4 Ground Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 9 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Functional Block Diagram (TPS2044B and TPS2054B) OC1 Thermal Sense GND Deglitch EN1 (See Note B) Driver Current Limit (See Note A) CS OUT1 UVLO Power Switch (See Note A) IN1 CS Driver OUT2 Current Limit OC2 EN2 (See Note B) Thermal Sense VCC Selector Deglitch Charge Pump OC3 Thermal Sense Deglitch EN3 (See Note B) Driver Current Limit (See Note A) CS OUT3 UVLO Power Switch (See Note A) IN2 CS Driver OUT4 Current Limit OC4 EN4 (See Note B) GND Thermal Sense Deglitch Note A: Current sense Note B: Active low (ENx) for TPS2044B; Active high (ENx) for TPS2054B 10 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 1 mF TA = 255C VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 1 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 500 ms/div Figure 2. Turnon Delay and Rise Time With 1-F Load Copyright (c) 2004-2008, Texas Instruments Incorporated t - Time - 500 ms/div Figure 3. Turnoff Delay and Fall Time With 1-F Load Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 11 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) RL = 10 W, CL = 100 mF TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 100 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t - Time - 500 ms/div t - Time - 500 ms/div Figure 4. Turnon Delay and Rise Time With 100-F Load Figure 5. Turnoff Delay and Fall Time With 100-F Load VI = 5 V, RL = 10 W, TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div 220 mF 470 mF IO(OUT) 500 mA/div IO(OUT) 500 mA/div 100 mF t - Time - 500 ms/div Figure 6. Short-Circuit Current, Device Enabled Into Short 12 Submit Documentation Feedback t - Time - 500 ms/div Figure 7. Inrush Current With Different Load Capacitance Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) VO(OC) 2 V/div VO(OC) 2 V/div IO(OUT) 500 mA/div IO(OUT) 500 mA/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 8. 3- Load Connected to Enabled Device Figure 9. 2- Load Connected to Enabled Device TYPICAL CHARACTERISTICS TURNON TIME vs INPUT VOLTAGE TURNOFF TIME vs INPUT VOLTAGE 1.0 3.3 CL = 100 mF, RL = 10 W, TA = 255C 0.9 0.8 CL = 100 mF, RL = 10 W, TA = 255C 3.2 Turnoff Time - ms Turnon Time - ms 0.7 0.6 0.5 0.4 3.1 3 0.3 0.2 2.9 0.1 0 2 3 4 5 VI - Input Voltage - V Figure 10. Copyright (c) 2004-2008, Texas Instruments Incorporated 6 2.8 2 3 4 5 6 VI - Input Voltage - V Figure 11. Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 13 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 0.25 0.6 0.5 0.2 0.4 Fall Time - ms Rise Time - ms CL = 1 mF, RL = 10 W, TA = 255C CL = 1 mF, RL = 10 W, TA = 255C 0.3 0.15 0.1 0.2 0.05 0.1 0 2 3 4 5 VI - Input Voltage - V 0 6 2 Figure 13. TPS2041B/2051B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2042B/TPS2052B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE I I (IN) - Supply Current, Output Enabled - A I I (IN) - Supply Current, Output Enabled - A 6 70 VI = 5.5 V 50 VI = 5 V 40 30 VI = 2.7 V 20 VI = 3.3 V 10 0 50 100 TJ - Junction Temperature - 5C Figure 14. 14 4 5 VI - Input Voltage - V Figure 12. 60 0 -50 3 Submit Documentation Feedback 150 VI = 5.5 V 60 50 VI = 5 V VI = 3.3 V 40 30 VI = 2.7 V 20 10 0 -50 0 50 100 150 TJ - Junction Temperature - 5C Figure 15. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) TPS2043B/TPS2053B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2044B/2054B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE 120 80 I I (IN) - Supply Current, Output Enabled - A I I (IN) - Supply Current, Output Enabled - A 90 VI = 5.5 V 70 VI = 5 V 60 VI = 3.3 V 50 40 VI = 2.7 V 30 20 10 0 -50 80 60 VI = 2.7 V 40 VI = 3.3 V 20 -50 150 0 50 100 Figure 16. Figure 17. TPS2041B/2051B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE TPS2042B/TPS2052B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE VI = 5.5 V 0.45 VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 50 100 TJ - Junction Temperature - 5C Figure 18. Copyright (c) 2004-2008, Texas Instruments Incorporated 150 TJ - Junction Temperature - 5C I I (IN) - Supply Current, Output Disabled - A I I (IN) - Supply Current, Output Disabled - A VI = 5 V 0 0 50 100 TJ - Junction Temperature - 5C 0.5 0 -50 VI = 5.5 V 100 150 0.5 0.45 VI = 5.5 V VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 -50 0 50 100 TJ - Junction Temperature - 5C 150 Figure 19. Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 15 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TPS2043B/TPS2053B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE TPS2044B/2054B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE 0.45 VI = 5 V 0.4 0.35 VI = 3.3 V 0.3 VI = 2.7 V 0.25 0.2 0.15 0.1 0.05 r DS(on) - Static Drain-Source On-State Resistance - m 0 -50 0 50 100 TJ - Junction Temperature - 5C 0.45 VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 -50 150 VI = 5.5 V 0 50 100 TJ - Junction Temperature - 5C Figure 20. Figure 21. STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 150 1.08 120 IO = 0.5 A VI = 2.7 V 100 80 VI = 3.3 V 60 VI = 5 V 40 20 0 -50 0 50 100 TJ - Junction Temperature - 5C Figure 22. 16 I I (IN) - Supply Current, Output Disabled - A 0.5 VI = 5.5 V I OS - Short-Circuit Output Current - A I I (IN) - Supply Current, Output Disabled - A 0.5 Submit Documentation Feedback 150 1.06 1.04 VI = 2.7 V VI = 3.3 V 1.02 1.0 0.98 VI = 5 V 0.96 VI = 5.5 V 0.94 0.92 0.9 -50 0 50 100 TJ - Junction Temperature - 5C 150 Figure 23. Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) THRESHOLD TRIP CURRENT vs INPUT VOLTAGE THRESHOLD TRIP CURRENT vs INPUT VOLTAGE 2 2 TPS2041B, TPS2042B, TPS2051B, TPS2052B Threshold Trip Current - A 1.8 TA = 255C Load Ramp = 1A/10 ms Threshold Trip Current - A TA = 255C Load Ramp = 1A/10 ms 1.6 1.4 1.2 1 2.5 1.8 1.6 1.4 1.2 3 3.5 4 4.5 5 5.5 1 2.5 6 TPS2043B, TPS2044B, TPS2053B, TPS2054B 3 3.5 4 4.5 5 VI - Input Voltage - V VI - Input Voltage - V Figure 24. Figure 25. UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE CURRENT-LIMIT RESPONSE vs PEAK CURRENT 6 100 2.3 VI = 5 V, TA = 255C UVLO Rising 2.26 Current-Limit Response - s UVLO - Undervoltage Lockout - V 5.5 2.22 UVLO Falling 2.18 80 60 40 20 2.14 2.1 -50 0 0 50 100 TJ - Junction Temperature - 5C Figure 26. Copyright (c) 2004-2008, Texas Instruments Incorporated 150 0 2.5 5 7.5 Peak Current - A 10 12.5 Figure 27. Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 17 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com APPLICATION INFORMATION POWER-SUPPLY CONSIDERATIONS TPS2042B 2 Power Supply 2.7 V to 5.5 V IN OUT1 0.1 F 8 3 5 4 7 Load 0.1 F 22 F 0.1 F 22 F OC1 EN1 OUT2 OC2 6 Load EN2 GND 1 Figure 28. Typical Application (Example, TPS2042B) A 0.01-F to 0.1-F ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-F to 0.1-F ceramic capacitor improves the immunity of the device to short-circuit transients. OVERCURRENT A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 14 through Figure 17). The TPS204xB/TPS205xB senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 18 through Figure 21). The TPS204xB/TPS205xB is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS204xB/TPS205xB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown. 18 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 V+ TPS2042B GND Rpullup OC1 IN OUT1 EN1 OUT2 EN2 OC2 Figure 29. Typical Circuit for the OC Pin (Example, TPS2042B) POWER DISSIPATION AND JUNCTION TEMPERATURE The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 22. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) x I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: TJ = PD x RJA + TA Where: TA= Ambient temperature C RJA = Thermal resistance PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 19 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com UNIVERSAL SERIAL BUS (USB) APPLICATIONS The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: * Hosts/self-powered hubs (SPH) * Bus-powered hubs (BPH) * Low-power, bus-powered functions * High-power, bus-powered functions * Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. TPS204xB/TPS205xB can provide-power distribution solutions to many of these classes of devices. The HOST/SELF-POWERED AND BUS-POWERED HUBS Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 30 and Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Power Supply 3.3 V Downstream USB Ports 5V TPS2041B 2, 3 IN D+ D- 6, 7, 8 0.1 F VBUS OUT 0.1 F 5 USB Control 4 120 F GND OC EN GND 1 Figure 30. Typical One-Port USB Host / Self-Powered Hub 20 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 Downstream USB Ports D+ Power Supply D- 3.3 V 5V + TPS2044B 2 6 IN1 OUT1 IN2 VBUS 33 F 15 D+ 0.1 F D- 14 OUT2 16 3 13 4 USB Controller 12 7 9 8 OC1 OUT3 GND + VBUS 33 F GND 11 EN1 D+ OC2 D- EN2 + 10 OC3 VBUS 33 F GND OUT4 EN3 OC4 D+ EN4 D- GND GND 1 5 + VBUS 33 F GND Figure 31. Typical Four-Port USB Host / Self-Powered Hub Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 and 10 F at power up, the device must implement inrush current limiting (see Figure 32). Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 21 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Power Supply 3.3 V D+ D- VBUS TPS2042B 2 10 F 0.1 F IN OUT1 GND 8 USB Control 3 5 4 7 0.1 F 10 F Internal Function 0.1 F 10 F Internal Function OC1 EN1 OC2 EN2 OUT2 GND 1 6 Figure 32. High-Power Bus-Powered Function (Example, TPS2042B) USB POWER-DISTRIBUTION REQUIREMENTS USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. * Hosts/self-powered hubs must: - Current-limit downstream ports - Report overcurrent conditions on USB VBUS * Bus-powered hubs must: - Enable/disable power to downstream ports - Power up at <100 mA - Limit inrush current (<44 and 10 F) * Functions must: - Limit inrush currents - Power up at <100 mA The feature set of the TPS204xB/TPS205xB allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 33 through Figure 36). 22 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 TUSB2041B Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041B EN Input D+ A C B D GND OC 5V IN 33 F DM3 A C B D TPS76333 4.7 F 5V DP3 OUT 0.1 F SN75240 D+ D- Ferrite Beads GND DP4 IN 3.3 V 4.7 F D- GND DM2 5-V Power Supply EN 1 F Ferrite Beads SN75240 DP2 TPS2041B Downstream Ports VCC DM4 5V TPS2041B GND GND PWRON1 EN OVRCUR1 OC IN 33 F 0.1 F OUT D+ TPS2041B 48-MHz Crystal XTAL1 PWRON2 EN OVRCUR2 OC D- IN Ferrite Beads 0.1 F GND OUT Tuning Circuit 5V XTAL2 OCSOFF TPS2041B PWRON3 EN OVRCUR3 OC IN 33 F 0.1 F OUT D+ GND TPS2041B PWRON4 EN OVRCUR4 OC Ferrite Beads IN D- GND 0.1 F OUT 5V 33 F USB rev 1.1 requires 120 F per hub. Figure 33. Hybrid Self / Bus-Powered Hub Implementation, TPS2041B/TPS2051B Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 23 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TUSB2040 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041B EN Input D+ A C B D GND OC 5V IN 5V 33 F DP3 OUT DM3 A C B D 1 F TPS76333 4.7 F SN75240 D+ D- Ferrite Beads GND DP4 IN 3.3 V 4.7 F VCC DM4 5V TPS2042B GND PWRON1 GND OVRCUR1 48-MHz Crystal XTAL1 33 F EN1 OUT1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 D+ IN 0.1 F Tuning Circuit D- GND DM2 5-V Power Supply EN 0.1 F Ferrite Beads SN75240 DP2 TPS2041B Downstream Ports XTAL2 OCSOFF GND D- Ferrite Beads GND TPS2042B PWRON3 EN1 OUT1 OVRCUR3 OC1 OUT2 PWRON4 EN2 OVRCUR4 OC2 5V 33 F IN D+ 0.1 F Ferrite Beads D- GND 5V 33 F USB rev 1.1 requires 120 F per hub. Figure 34. Hybrid Self / Bus-Powered Hub Implementation, TPS2042B/TPS2052B 24 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 TUSB2040 Hub Controller 1/2 SN75240 BUSPWR A C B D GANGED Upstream Port D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041B EN Input D+ A C B D GND OC 5V IN 5V 47 F DP3 OUT DM3 A C B D 1 F TPS76333 4.7 F D- GND DM2 5-V Power Supply EN 0.1 F Ferrite Beads SN75240 DP2 TPS2041B Downstream Ports 1/2 SN75240 D+ D- Ferrite Beads GND IN 3.3 V 4.7 F VCC 5V TPS2053B GND PWRON1 GND OVRCUR1 48-MHz Crystal XTAL1 Tuning Circuit XTAL2 47 F EN1 OUT1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 D+ IN1 0.1 F D- Ferrite Beads GND PWRON3 OVRCUR3 EN3 OUT3 5V OC3 47 F OCSOFF IN2 0.1 F GND GND GND USB rev 1.1 requires 120 F per hub. Figure 35. Hybrid Self / Bus-Powered Hub Implementation, TPS2043B/TPS2053B Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 25 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com TUSB2040 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2041B EN Input D+ A C B D GND OC 5V IN 5V 33 F DP3 OUT DM3 A C B D 1 F TPS76333 4.7 F SN75240 D+ D- Ferrite Beads GND DP4 IN 3.3 V 4.7 F D- GND DM2 5-V Power Supply EN 0.1 F Ferrite Beads SN75240 DP2 TPS2041B Downstream Ports VCC DM4 5V TPS2044B GND PWRON1 GND OVRCUR1 48-MHz Crystal XTAL1 Tuning Circuit XTAL2 33 F EN1 OUT1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 D+ IN1 0.1 F D- Ferrite Beads GND OCSOFF PWRON3 EN3 OUT3 OVRCUR3 OC3 OUT4 PWRON4 EN4 OVRCUR4 OC4 5V 33 F IN2 D+ 0.1 F GND Ferrite Beads GND1 D- GND GND2 5V 33 F USB rev 1.1 requires 120 F per hub. Figure 36. Hybrid Self / Bus-Powered Hub Implementation, TPS2044B/TPS2054B 26 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B www.ti.com .................................................................................................................................................. SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 GENERIC HOT-PLUG APPLICATIONS In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS205xB, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS204xB/TPS205xB also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module. PC Board TPS2042B OC1 GND Power Supply 2.7 V to 5.5 V 1000 F Optimum 0.1 F IN EN1 EN2 Block of Circuitry OUT1 OUT2 OC2 Block of Circuitry Overcurrent Response Figure 37. Typical Hot-Plug Implementation (Example, TPS2042B) By placing the TPS204xB/TPS205xB between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. DETAILED DESCRIPTION Power Switch The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 500 mA. Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. Driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. Enable (ENx) The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 A or 2 A when a logic high is present on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Copyright (c) 2004-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B 27 TPS2041B,, TPS2042B TPS2043B, TPS2044B, TPS2051B TPS2052B, TPS2053B, TPS2054B SLVS514J - APRIL 2004 - REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com Enable (ENx) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 A or 2 A when a logic low is present on ENx. A logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Overcurrent (OCx) The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OCx is asserted instantaneously. Current Sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. Thermal Sense The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises to approximately 140C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. 28 Submit Documentation Feedback Copyright (c) 2004-2008, Texas Instruments Incorporated Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2041BD ACTIVE SOIC D 8 TPS2041BDBVR ACTIVE SOT-23 DBV TPS2041BDBVRG4 ACTIVE SOT-23 TPS2041BDBVT ACTIVE TPS2041BDBVTG4 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDGN-ASY OBSOLETE MSOPPower PAD DGN 8 TBD Call TI TPS2041BDGNG4 ACTIVE MSOPPower PAD DGN 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2041BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 80 Addendum-Page 1 Call TI PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2042BDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2042BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2043BD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2043BDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2043BDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2043BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2044BD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2044BDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2044BDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2044BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BD ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2051BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 75 Addendum-Page 2 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2052BDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2052BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2053BD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2053BDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2053BDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2053BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2054BD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2054BDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2054BDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2054BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2009 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS2041B, TPS2042B, TPS2051B : * Automotive: TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) TPS2041BDBVR SOT-23 3000 179.0 TPS2041BDBVT TPS2041BDGNR A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 3.2 3.2 1.4 4.0 DBV 5 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 TPS2041BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2042BDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2042BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2042BDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2042BDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2043BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2044BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2051BDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS2051BDBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS2051BDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS2051BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 6-Dec-2008 Package Package Pins Type Drawing TPS2052BDGNR MSOPPower PAD TPS2052BDR TPS2052BDRBR SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2052BDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2053BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2054BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2041BDBVR SOT-23 DBV 5 3000 195.0 200.0 45.0 TPS2041BDBVT SOT-23 DBV 5 250 195.0 200.0 45.0 TPS2041BDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2041BDR SOIC D 8 2500 340.5 338.1 20.6 TPS2042BDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2042BDR SOIC D 8 2500 340.5 338.1 20.6 TPS2042BDRBR SON DRB 8 3000 370.0 355.0 55.0 TPS2042BDRBT SON DRB 8 250 195.0 200.0 45.0 TPS2043BDR SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2008 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2044BDR SOIC D 16 2500 333.2 345.9 28.6 TPS2051BDBVR SOT-23 DBV 5 3000 195.0 200.0 45.0 TPS2051BDBVT SOT-23 DBV 5 250 195.0 200.0 45.0 TPS2051BDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2051BDR SOIC D 8 2500 340.5 338.1 20.6 TPS2052BDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2052BDR SOIC D 8 2500 340.5 338.1 20.6 TPS2052BDRBR SON DRB 8 3000 370.0 355.0 55.0 TPS2052BDRBT SON DRB 8 250 195.0 200.0 45.0 TPS2053BDR SOIC D 16 2500 333.2 345.9 28.6 TPS2054BDR SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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