PCF8576CT/1,118 - NXP Semiconductors

1. General description

The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments and can easily

be cascaded for larger LCD applications. The PCF8576C is compatible with most

microprocessors or microcontrollers and communicates via a two-line bidirectional

I2C-bus. Communication overheads are minimized by a display RAM with

auto-incremented addressing and by hardware subaddressing.

2. Features and benefits

Single-chip LCD controller and driver

40 segment dr ive s:

Up to twenty 7-segment alphanumeric characters

Up to ten 14-segment alphanumeric characters

Any graphics of up to 160 elements

Versatile blinking modes

No external components required (even in multiple device applications)

Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

Selectable display bias configuration: static, 1⁄2, or 1⁄3

Internal LCD bias generation with voltage-follower buffers

40 4-bit RAM for display data storage

Auto-incremented display data loading across device subaddress boundaries

Display memory bank switching in static and duplex drive modes

Wide logic LCD supply range:

From 2 V for low-threshold LCDs

Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs

Low power consum ption

May be cascaded for large LCD applications (up to 2560 segments possible)

No external components

Separate or combined LCD and logic supplies

Optimized pinning for plane wiring in bo th and multiple PCF8576C applications

Power-saving mode for extremely low power consumption in battery-operated and

telephone applications

PCF8576C

Universal LCD driver for low multiplex rates

Rev. 11 — 30 March 2012 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.

Product data sheet Rev. 11 — 30 March 2012 2 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

3. Ordering information

[1] Delivery form: chip in tray.

4. Marking

Table 1. Ordering information

Type number Package

Name Description Version

PCF8576CHL/1 LQFP64 plastic low profile quad flat package;

64 leads; body 10 10 1.4 mm SOT314-2

PCF8576CT/1 VSO56 plastic very small outline package, 56 leads SOT190-1

PCF8576CTT/1 HTSSOP56 plastic thermal enhanced thin shrink small

outline package, 56 leads; body width 6.1 mm;

exposed die pad

SOT793-1

PCF8576CU/F1 PCF8576CU wire bond die; 56 bonding pads; 3.2  2.92  0.38 mm[1] PCF8576CU

PCF8576CU/2/F2 PCF8576CU/2 bare die; 56 bumps; 3.2  2.92  0.40 mm[1] PCF8576CU/2

Table 2. Marking codes

Type number Marking code

PCF8576CHL/1 PCF8576CHL

PCF8576CT/1 PCF8576CT

PCF8576CTT/1 PCF8576CTT

PCF8576CU/F1 PC8576C-1

PCF8576CU/2/F2 PC8576C-2

Product data sheet Rev. 11 — 30 March 2012 3 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

5. Block diagram

Fig 1. Block diagram of PCF8576C

013aaa094

LCD

VOLTAGE

SELECTOR

VLCD

VDD

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS I2C-BUS

CONTROLLER

POWER-

RESET

CLK

SYNC

OSC

VSS

SCL

SDA

SA0

DISPLAY

CONTROLLER

COMMAND

DECODER

BACKPLANE

OUTPUTS

BP0 BP2 BP1 BP3

INPUT

BANK

SELECTOR

DISPLAY

RAM

40 × 4 BITS

OUTPUT

BANK

SELECTOR

DATA

POINTER

SUB-

ADDRESS

COUNTER

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

S0 to S39

A0 A1 A2

PCF8576C

LCD BIAS

GENERATOR

Product data sheet Rev. 11 — 30 March 2012 4 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

Top view. For mechanical details, see Figure 34.

Fig 2. Pin configura tio n for LQF P6 4 (PCF8576CHL/1)

PCF8576CHL

n.c. n.c.

S34 S17

S35 S16

S36 S15

S37 S14

S38 S13

S39 S12

n.c. S11

n.c. S10

SDA S9

SCL S8

SYNC S7

CLK S6

OSC S4

A0 n.c.

A1 S33

A2 S32

SA0 S31

S30

LCD

S29

n.c. S28

n.c. S27

n.c. S26

BP0 S25

BP2 S24

BP1 S23

BP3 S22

S0 S21

S1 S20

S2 S19

S3 S18

013aaa272

Product data sheet Rev. 11 — 30 March 2012 5 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Top view. For mechanical details, see Figure 35.

Fig 3. Pin configura tio n for VS O56 (PCF8 5 76C T/ 1 )

PCF8576CT

SDA S39

SCL S38

SYNC S37

CLK S36

S35

OSC S34

A0 S33

A1 S32

A2 S31

SA0 S30

S29

LCD

S28

BP0 S27

BP2 S26

BP1 S25

BP3 S24

S0 S23

S1 S22

S2 S21

S3 S20

S4 S19

S5 S18

S6 S17

S7 S16

S8 S15

S9 S14

S10 S13

S11 S12

001aag240

Product data sheet Rev. 11 — 30 March 2012 6 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Top view. For mechanical details, see Figure 36.

Fig 4. Pin configuration for HTSSOP56 (PCF8576CTT/1)

PCF8576CTT

SDA S39

SCL S38

SYNC S37

CLK S36

VDD S35

OSC S34

A0 S33

A1 S32

A2 S31

SA0 S30

VSS S29

VLCD S28

BP0 S27

BP2 S26

BP1 S25

BP3 S24

S0 S23

S1 S22

S2 S21

S3 S20

S4 S19

S5 S18

S6 S17

S7 S16

S8 S15

S9 S14

S10 S13

S11 S12

013aaa095

Product data sheet Rev. 11 — 30 March 2012 7 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Viewed from pin side. For mechanical details, see Figure 37 and Figure 38.

Fig 5. Pin locations of PCF8576CU/F1 and PCF8576CU/2/F2

S33

S32

S31

S29

S30

S28

S26

S25

S27

S24

S23

S22

S20

S21

S19

S18

S10

S11

S12

S13

S15

S14

S16

S17

OSC

VDD

SYNC

SCL

CLK

SDA

S39

S38

S36

S37

S35

S34

SA0

VSS

VLCD

BP0

BP2

BP1

BP3

PCF8576CU

013aaa096

1565554535251

35 20

29 28 27 26 25 24 23 22 213031323334

234567

Product data sheet Rev. 11 — 30 March 2012 8 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

6.2 Pin description

[1] The die paddle (exposed pad) is connected to VDD and should be electrically isolated.

[2] The substrate (rear side of the die) is connected to VDD and should be electrically isolated.

Table 3. Pin de scription

Symbol Pin Description

LQFP64

(PCF8576CHL) VSO56

(PCF8576CT) HTSSOP56

(PCF8576CTT) PCF8576CU Type

SDA 10 1 1 1 input/output I2C-bus serial data input and

output

SCL 11 2 2 2 input I2C-bus serial clock input

SYNC 12 3 3 3 input/output cascade synchronization input

and output

CLK 13 4 4 4 input/output external clock input/output

VDD 14 5 5[1] 5[2] supply supply voltage

OSC 15 6 6 6 input internal oscillator enable input

A0 to A2 16 to 18 7to9 7to9 7to9 input subaddress inputs

SA0 19 10 10 10 input I2C-bus address input; bit 0

VSS 20 11 11 11 supply ground supply voltage

VLCD 21 12 12 12 supply LCD supply voltage

BP0, BP2,

BP1, BP3 25 to 28 13 to 16 13 to 16 13 to 16 output LCD backplane outputs

S0 to S39 2 to 7, 29 to 32,

34 to 47, 49 to

17 to 56 17 to 56 17 to 56 output LCD segment outputs

n.c. 1, 8, 9,

22 to 24, 33, 48 - - - - not connected; do not connect

and do not use as feed

through

Product data sheet Rev. 11 — 30 March 2012 9 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8576C is a versatile peripheral device designed to interface between any

microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays

(see Figure 6). It can directly drive any static or multiplexed LCD containi ng up to four

backplanes and up to 40 segments.

The possible display configurations of the PCF8576C depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 4. All

of these configurations can be implemented in the typical system shown in Figure 7.

Fig 6. Example of displays suitable for PCF8576C

Table 4. Selection of po ssible display configurations

Number of

Backplanes Icons Digits/Characters Dot matrix/

Elements

7-segment 14-segment

4 160 20 10 160 dots (4  40)

3 120 15 7 120 dots (3  40)

28010580dots (2 40)

1405240dots (140)

7-segment with dot 14-segment with dot and accent

013aaa312

dot matrix

Product data sheet Rev. 11 — 30 March 2012 10 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8576C.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.

7.1 Power-On-Reset (POR)

At power-on the PCF8576C resets to the following starting conditions:

•All backplane and segment outputs are set to VDD

•The selected drive mode is 1:4 multiplex with 1⁄3 bias

•Blinking is switched off

•Input and output bank selectors are reset (as defined in Table 8)

•The I2C-bus interface is initialized

•The data pointer and the subaddress counter are cleared

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

The full-scale LCD voltage (Voper) is obtained from VDD VLCD. The LCD voltage may be

temperature compensated externally through the VLCD supply to pin VLCD.

Fractional LCD biasing voltages are obtained from an internal voltage divider comprising

three series res isto rs connected between VDD and VLCD. The center resistor can be

switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex

configuration.

Fig 7. Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

R≤t

SDA

SCL

OSC

40 segment drives

4 backplanes

LCD PANEL

(up to 160

elements)

PCF8576C

A0 A1 A2 SS

SA0 V

VLCD

013aaa098

Product data sheet Rev. 11 — 30 March 2012 11 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.3 LCD voltage selector

The LCD voltage selector coord ina te s th e mu ltiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltag e selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of o per ation, to gether with the biasing cha racteri stics as functions o f

VLCD and the resulting discrimination ratios (D) are given in Table 5.

A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD

threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is VLCD >3V

th.

Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and

hence the contrast ratios are smaller.

Bias is calculated by , where the values for a are

a = 1 for 1⁄2 bias

a = 2 for 1⁄3 bias

The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:

(1)

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:

(2)

Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:

(3)

Table 5. Biasing characteristics

LCD drive

mode Number of: LCD bias

configuration

Backplanes Levels

static 1 2 static 0 1 

1:2 multiplex 2 3 1⁄20.354 0.791 2.236

1:2 multiplex 2 4 1⁄30.333 0.745 2.236

1:3 multiplex 3 4 1⁄30.333 0.638 1.915

1:4 multiplex 4 4 1⁄30.333 0.577 1.732

Voff RMS

VLCD

-------------------------

Von RMS

VLCD

------------------------

DVon RMS

Voff RMS

-------------------------=

1a+

-------------

Von RMS a22a n++

n1a+



------------------------------

VLCD

Voff RMS a22a–n+

n1a+



------------------------------

VLCD

DVon RMS

Voff RMS

-----------------------a1+

2n1–+

a1–

2n1–+

--------------------------------------------==

Product data sheet Rev. 11 — 30 March 2012 12 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Using Equation 3, the discrimination for an LC D drive mode of 1:3 multiplex with

1⁄2bias is and the discrimination for an LCD drive mode of 1:4 multiplex with

1⁄2bias is .

The advanta ge of these LCD drive modes is a reduction of the LCD full scale volta ge VLCD

as follows:

•1:3 multiplex (1⁄2 bias):

•1:4 multiplex (1⁄2 bias):

These compare with when 1⁄3 bias is used.

It should be noted that VLCD is sometimes referred as the LCD operating voltage.

7.3.1 Electro-optical performance

Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at Vth(off)) and the other at 90 % re lat ive tran sm iss i on (at Vth(on)), see

Figure 8. For a good contrast performance, the following rules should be followed:

(4)

(5)

Von(RMS) and Voff(RMS) are properties of the display driver and are af fected by the selection

of a (see Equation 1), n (see Equation 3), and the VLCD voltage.

Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module

manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation

voltage Vsat.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

3 1.732=

---------- 1.528=

VLCD 6V

off RMS

2.449Voff RMS

VLCD 43

----------------------2.309Voff RMS

VLCD 3Voff RMS

Von RMS

Vth on



Voff RMS

Vth off



Product data sheet Rev. 11 — 30 March 2012 13 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 8. Electro-optical characteristic: relative transmission curve of the liquid

VRMS [V]

100 %

90 %

10 %

OFF

SEGMENT GREY

SEGMENT ON

SEGMENT

Vth(off) Vth(on)

Relative T ransmission

013aaa494

Product data sheet Rev. 11 — 30 March 2012 14 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 9.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = VLCD.

Vstate2(t) = VSn+1(t)  VBP0(t).

Voff(RMS) = 0 V.

Fig 9. Static drive mode wavefo rms

mgl745

VSS

VLCD

VSS

VLCD

VSS

VLCD

−VLCD

VLCD

state 1 0 V

BP0

Sn+1

state 2 0 V

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 1

(on) state 2

(off)

Tfr

Product data sheet Rev. 11 — 30 March 2012 15 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backpla ne s ar e pr ov ide d in the LCD , the 1:2 multiple x mo d e ap plie s. The

PCF8576C allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 10 and Figure 11).

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.791VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.354VLCD

Fig 10. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias

mgl746

state 1

BP0

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 2

state 1

VSS

VLCD

VLCD / 2

VSS

VLCD

VSS

VLCD

0 V

VLCD / 2

−VLCD

−VLCD / 2

Sn+1

Tfr

Product data sheet Rev. 11 — 30 March 2012 16 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.745VLCD

Vstate2(t) = VSn(t)  VBP1(t)

Voff(RMS) = 0.333VLCD.

Fig 11. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias

mgl747

state 1

BP0

(a) Waveforms at driver.

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

Sn+1

Tfr

VSS

VLCD

2VLCD / 3

VLCD / 3

Product data sheet Rev. 11 — 30 March 2012 17 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 12.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.638VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 12. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias

mgl748

state 1

BP0

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

(a) Waveforms at driver.

BP2

Sn+1

Sn+2

Tfr

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

VSS

VLCD

2VLCD / 3

VLCD / 3

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

0 V

VLCD

2VLCD / 3

−2VLCD / 3

VLCD / 3

−VLCD / 3

−VLCD

VSS

VLCD

2VLCD / 3

VLCD / 3

Product data sheet Rev. 11 — 30 March 2012 18 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 13.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.577VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 13. Waveforms for the 1:4 multiplex mode with 1⁄3 bias

mgl749

state 1

BP0

(b) Resultant waveforms

at LCD segment.

LCD segments

state 2

BP1

state 1

state 2

BP2

(a) Waveforms at driver.

BP3

Sn+1

Sn+2

Sn+3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

LCD

/ 3

0 V

LCD

/ 3

−2V

LCD

/ 3

LCD

/ 3

−V

LCD

/ 3

−V

LCD

0 V

LCD

/ 3

−2V

LCD

/ 3

LCD

/ 3

−V

LCD

/ 3

−V

LCD

/ 3

LCD

/ 3

Product data sheet Rev. 11 — 30 March 2012 19 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic a nd the LCD dr ive signals o f the PCF857 6C are timed by the freque ncy

fclk, which equals either the built-in oscillator frequency fosc or the external clock fr equency

fclk(ext).

The clock frequency (fclk) d etermines the LCD frame frequen cy (ffr) and the ma ximum rate

for data recep tion from the I2C-bus. To allow I2C-bus transmissions at their maximum data

rate of 100 kHz, fclk should be chosen to be above 125 kHz.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8576C in the system.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clo ck source. Pin CLK then becomes the

external clock input.

Remark: A clock signal must always be supplied to the device. Removing the clock,

freezes the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The timing of the PCF8576C seque nces the internal dat a flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCF8576Cs in the system. The timing also generates the LCD

frame frequency which is derived as an integer division of the clock frequency (see

Table 6). The frame frequency is set by the mode-set command (see Table 9) when an

internal clock is used o r by the frequency app lied to the pin CL K when an external cloc k is

used.

[1] The possible values for fclk see Table 16.

[2] For fclk = 200 kHz.

[3] For fclk = 31 kHz.

The ratio between the clock frequency and the LCD frame frequency depends on the

power mode in which the device is operating. In the power-saving mode the reduction

ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six.

The reduced clock frequency results in a significant reduction in power consumption.

Table 6. LC D frame frequencies [1]

PCF8576C mode Fra m e fr equency Nominal frame frequency (Hz)

Normal-pow er mo de 69 [2]

Power-savin g mo de 65 [3]

ffr fclk

2880

-------------

ffr fclk

480

----------

Product data sheet Rev. 11 — 30 March 2012 20 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The lower clock frequency has the disadvantage of increasing the response time when

large amounts of display data are transmitted on the I2C-bus. When a device is unable to

process a display data byte before the next one arrives, it holds the SCL line LOW until

the first display data byte is stored. This slows down the transmission rate of the I2C-bus

but no data loss occurs.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Shift register

The shift register transfers display information from the display RAM to the display reg ister

while previous data is displayed.

7.9 Segment outputs

The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data residing in the display register. When less than

40 segment outputs are required, the unused segment outputs should be left open-circuit.

7.10 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

•In 1:4 multiplex drive mode: BP0 to BP3 must be connecte d directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left as an

open-circuit.

•In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, there fore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

•In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

•In static drive mode: the same signal is carried by all four ba ckplane outpu t s and they

can be connected in parallel for very high drive requirements.

7.11 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

•the bits in the RAM bitmap and the LCD elements

•the RAM columns and the se gm e nt outp u ts

•the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a log ic 0 indic at es th e off-state.

Product data sheet Rev. 11 — 30 March 2012 21 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The display RAM bit map Figure 14 shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

When display data is transmitted to the PCF8576C, the display b ytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as wi th the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples or

quadruples. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 15; the RAM filling organization depicted

applies equally to other LCD types.

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 14. Display RAM bit map

1 2 3 4 35 36 37 38 39

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

mbe525

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 11 — 30 March 2012 22 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

x = data bit unchanged.

Fig 15. Relationsh ip between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus

001aaj646

acbDPfegd

MSB LSB

bDPcadgfe

MSB LSB

abfgecdDP

MSB LSB

cbafgedDP

MSB LSB

drive mode

static

1:2

multiplex

1:3

multiplex

1:4

multiplex

LCD segments LCD backplanes display RAM filling order transmitted display byte

BP0

BP1

BP0

BP1 BP2

BP1

BP2

BP3

BP0

n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7

rows

display RAM

rows/backplane

outputs (BP)

byte1

columns

display RAM address/segment outputs (s)

n + 1 n + 2 n + 3

byte1 byte2

rows

display RAM

rows/backplane

outputs (BP)

columns

display RAM address/segment outputs (s)

n + 1 n + 2

byte1 byte2 byte3

rows

display RAM

rows/backplane

outputs (BP)

columns

display RAM address/segment outputs (s)

n + 1

byte1 byte2 byte3 byte4 byte5

rows

display RAM

rows/backplane

outputs (BP)

columns

display RAM address/segment outputs (s)

Sn+2

Sn+3

Sn+1

Sn+2

Sn+1

Sn+7

Sn+3

Sn+5

Sn+6

Sn+4

Sn+1

Sn+2

Sn+1

Product data sheet Rev. 11 — 30 March 2012 23 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The following applies to Figure 15:

•In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

•In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of fo ur succ es sive 4-bit RAM words.

•In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be t aken to avoid overwriting adjace nt data because al ways full bytes are

transmitted.

•In the 1:4 multiplex mode, the eight transmitted dat a bits a re placed in quadrup les into

row 0, 1, 2, and 3 of two successive 4-bit RAM words.

7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 10). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 15).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD configuration.

The contents of the data pointer are incremented as follows:

•In static drive mode by eight.

•In 1:2 multiplex drive mode by four.

•In 1:3 multiplex drive mode by three.

•In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminate s ea rly, the state of the data pointer is unknown .

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddr ess applied to A0, A1 and A2. The subaddress counter value is

defined by the device-select command (see Table 11). If the contents of the subaddress

counter and the hardware subaddress do not match then data storage is blocked but the

data pointer will be incremented as if data storage had taken place. The subaddress

counter is also incremented when the data pointer overflows.

The storage arrange men ts described lead to extremely ef ficien t data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the ne xt PCF8 576C occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

Product data sheet Rev. 11 — 30 March 2012 24 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.14 Bank selector

7.14.1 Output bank selector

The output bank selector (see Table 12), selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends o n the LCD

drive mode in operation and on the instant in the multiplex sequence.

•In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequen tially

by the contents of row 1, row 2, and then row 3.

•In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially.

•In 1:2 multiplex mode: rows 0 an d 1 ar e se lect ed .

•In the static mode: row 0 is selected.

The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This

enables preparation of display information in an alternative bank and the ability to switch

to it once it has been assem b led .

7.14.2 Input bank selector

The input bank selector (see Table 12) loads display data into the disp lay RAM ba se d on

the selected LCD drive configuration. Using the bank-select command, display data can

be loaded in row 2 into static drive mode or in rows 2 and 3 into 1:2 multiplex drive mode.

The input bank selector functions independently of the output bank selector.

7.15 Blinking

The display blinking capabilities of the PCF8576C are very versatile. The whole display

can be blinked at frequencies selected by the blink-select command. The blinking

frequencies are integer fractions of the clock frequency; the ratios between the clock and

blinking frequencies depend on the mode in which the device is operating (see Table 7).

An additional feature is for an arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. Usin g the output ban k selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

specified by the blin k-select command (see Table 13).

Table 7. Blink frequencies

Blinking mode Normal-power mode

ratio Power-saving mode

ratio Blink frequency

off - - blinking off

12 Hz

21 Hz

30.5 Hz

fblink fclk

92160

----------------

fblink fclk

15360

----------------

fblink fclk

184320

--------------------

fblink fclk

30720

----------------

fblink fclk

368640

--------------------

fblink fclk

61440

----------------

Product data sheet Rev. 11 — 30 March 2012 25 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at fixed time

intervals.

If the entire display needs to be blinked at a frequen cy other than the nominal blink

frequency, this can be done using the mode-set command to set and reset the display

enable bit E at the required rate (see Table 9).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidire ctional, two-line communication between dif ferent ICs or modules.

The two lines are a Serial DAt a line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.16.1 Bit transfer

One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 16.

7.16.2 START and STOP conditions

Both data an d clock lines remain HIGH when the bus is not b usy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P). The START and ST OP conditions are illustrated in Figure 17.

Fig 16. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 17. Definitio n of START and STOP condit ion s

mbc622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 11 — 30 March 2012 26 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.16.3 System configuration

A device generating a message is a transmitter and a device receiving a message is the

receiver. The device that controls the message is the master and the de vices which are

controlled by the master are the slaves. The system configuration is illustrated in

Figure 18.

7.16.4 Acknowledge

The number of data bytes tran sf er re d be tween the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

•A master receiver must generate an acknowledge after the reception of each byte that

has been clocke d ou t of th e sl av e tra n sm i tte r.

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is illustrated in Figure 19.

Fig 18. System configuration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Product data sheet Rev. 11 — 30 March 2012 27 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.16.5 PCF8576C I2C-bus controller

The PCF8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8576C are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1, and A2 are normally

tied to VSS which defines the hardware subaddress 0. In multiple device applications

A0, A1, and A 2 ar e tie d to VSS or VDD using a binary coding scheme so that no two

devices with a common I2C-bus slave address have the same hardware subaddress.

In the power-saving mode it is possible that the PCF8576C is not ab le to keep up wi th the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I2C-bus and serves

to slow down fast transmitters. Data loss does not occur.

7.16.6 Input filter

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.17 I2C-bus protocol

Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.

The least significant bit of the slave address that a PCF8576C responds to is defined by

the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on

the same I2C-bus which allows:

•Up to 16 PCF8576Cs on the same I2C-bus for very large LCD applications.

•The use of two types of LCD multiplex on the same I2C-bus.

Fig 19. Acknowledgement of the I2C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 11 — 30 March 2012 28 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The I2C-bus protocol is shown in Figure 20. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two PCF8576C

slave addresses available. All PCF8576Cs with the corr esponding SA0 level acknowledge

in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore

the whole I2C-bus transfer.

After ackn owledgement, one or more command bytes fo llow which define the statu s of the

addressed PCF8576Cs.

The last command byte is t agged with a cleared most significant bit, the continuation bit C.

The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.

After the last command byte, a series of display data bytes may follow. These display

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data p ointer and subadd ress counter are auto matically updated

and the data is directed to the intended PCF8576C device. The acknowledgement after

each byte is made only by the (A0, A1, and A2) addressed PCF8576C. After the last

display byte, the I2C-bus master issues a STOP condition (P).

7.18 Command decoder

The command decoder identifies command bytes that arrive on the I2C-bus. All available

commands carry a continuation bit C in their most significant bit position as shown in

Figure 21. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive

will also represent a command. If this bit is set logic 0, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data.

The five commands available to the PCF8576C are defined in Table 8.

Fig 20. I2C-bus protocol

mbe538

S011100 0ACCOMMAND AP

ADISPLAY DATA

slave address R/W

acknowledge by

all addressed

PCF8576Cs

acknowledge

by A0, A1 and A2

selected

PCF8576C only

n ≥ 1 byte(s) n ≥ 0 byte(s)

1 byte

update data pointers

and if necessary,

subaddress counter

(1) C = 0; last command

(2) C = 1; commands continue

Fig 21. General format of the comman d byte

msa833

REST OF OPCODE

MSB LSB

PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 11 — 30 March 2012  29 of 61
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
 
7.18.1 Mode-set command
 
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Bit B is not applicable for the static LCD drive mode.
7.18.2 Load-data-pointer command
 
Table 8. Definition of PCF8576C commands
Command Operation Code Reference
Bit 7 6 5 4 3 2 1 0
mode-set C 1 0 LP E B M[1:0] Section 7.18.1
load-data-pointer C 0 P[5:0] Section 7.18.2
device-select C1100A[2:0] Section 7.18.3
bank-select C11110I OSection 7.18.4
blink-select C 1 1 1 0 AB BF[1:0] Section 7.18.5
Table 9. Mode-set command bit description
Bit Symbol Value Description
7C0, 1see Figure 21
6 to 5 - 10 fixed value
4LP power dissi pation (see Table 6)
0 nor ma l-p o w er mo de
1 powe r-sa v i n g mo de
3E display status
0 disabled[1]
1 enabled
2B LCD bias configuration[2]
01⁄3 bias
11⁄2 bias
1 to 0 M[1:0] LCD drive mode selection
01 static; BP0
10 1:2 multiplex; BP0, BP1
11 1:3 multiplex; BP0, BP1, BP2
00 1:4 multiplex; BP0, BP1, BP2, BP3
Table 10. Load-data-pointer command bit description
Bit Symbol Value Description
7C0, 1see Figure 21
6 - 0 fixed value
5 to 0 P[5:0] 000000 to
100111 6 bit binary value, 0 to 39; transferred to the data pointer to 
define one of forty display RAM addresses

Product data sheet Rev. 11 — 30 March 2012 30 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.18.3 Device-select command

7.18.4 Bank-select command

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

7.18.5 Blink-select command

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.19 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCF8576C and coordinates their effects. The

controller is also responsible for loading display data into the display RAM as required by

the filling order.

Table 11. Device-select comman d bit description

Bit Symbol Value Description

7C0, 1see Figure 21

6 to 4 - 1100 fixed value

3 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress

counter to define one of eight hardware subaddresses

Table 12. Bank-select command bit description

Bit Symbol Value Description

Static 1:2 multiplex[1]

7 C 0, 1 see Figure 21

6 to 2 - 11110 fixed value

1I input bank selection; storage of arriving display data

0 RAM bit 0 RAM bits 0 and 1

1 RAM bit 2 RAM bits 2 and 3

0O output bank sele c tion ; retrieval of LCD display data

0 RAM bit 0 RAM bits 0 and 1

1 RAM bit 2 RAM bits 2 and 3

Table 13. Blink-select command bit description

Bit Symbol Value Description

7C0, 1see Figure 21

6 to 3 - 1110 fixed value

2AB blink mode selection

0 normal blinkin g[1]

1 alternate RAM bank blinking[2]

1 to 0 BF[1:0] blink frequency selection

00 off

01 1

10 2

11 3

Product data sheet Rev. 11 — 30 March 2012 31 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

8. Internal circuitry

Fig 22. Device protection diagram

013aaa109

VLCD

VSS

SYNC

CLK, OSC, A0 to A2,

SA0,

VDD

BP0 to BP3,

S0 to S39

SDA, SCL

PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 11 — 30 March 2012  32 of 61
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
9. Limiting values
 
 
[1] Values with respect to VDD.
[2] Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”.
[3] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”.
[4] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.
[5] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[6] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be 
stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products 
deviant conditions are described in that document.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage 
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted 
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed togeth er.
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol  Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +8.0 V
VLCD LCD supply voltage [1] VDD 8.0 VDD V
VIinput voltage on each of the pin s  SCL, SDA, 
CLK, SYNC, SA0, OSC and 
A0 to A2
0.5 +8.0 V
VOoutput voltage on each of the pins 
S0 to S39 and BP0 to BP3 [1] 0.5 +8.0 V
IIinput current 20 +20 mA
IOoutput current 25 +25 mA
IDD supply current 50 +50 mA
ISS ground supply current 50 +50 mA
IDD(LCD) LCD supply current 50 +50 mA
Ptot total power dissipation - 400 mW
Pooutput power - 100 mW
VESD electrostatic discharge 
voltage HBM [2] -4000 V
MM [3] -200 V
CDM [4]
PCF8576CHL
all pins - 500 V
corner pins - 1000 V
Ilu latch-up current [5] - 150 mA
Tstg storage temperature [6] 65 +150 C
Tamb ambient temperature operating device 40 +85 C

Product data sheet Rev. 11 — 30 March 2012 33 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

10. Static characteristics

Table 15. Static characteristics

VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD



6.0 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.0 - 6.0 V

VLCD LCD supply voltage [1] VDD  6.0 - VDD  2.0 V

IDD supply current: fclk = 200 kHz [2] --120A

IDD(lp) low-power mode supply

current VDD = 3.5 V; VLCD =0V; f

clk =35kHz;

A0, A1 and A2 connected to VSS

--60A

Logic

VIL LOW-level input voltage on pins CLK, SYNC, OSC,

A0 to A2 and SA0 VSS -0.3V

DD V

VIH HIGH-level input voltage on pins CLK, SYNC,OSC,

A0 to A2 and SA0 0.7VDD -V

DD V

VOL LOW-level output voltage IOL = 0 mA - - 0.05 V

VOH HIGH-level output voltage IOH = 0 mA VDD  0.05 - - V

IOL LOW-level output current output sink current;

VOL =1.0V; V

DD =5.0V;

on pins CLK and SYNC

1--mA

ILleakage current VI=V

DD or VSS; on pins

CLK, SCL, SDA, A0 to A2 and SA0 1-+1A

IL(OSC) leakage current on pin OSC VI=V

DD 1-+1A

Ipd pull-down current VI= 1.0 V; VDD =5.0V;

on pins A0 to A2 and OSC 15 50 150 A

RSYNC_N SYNC resistance 20 50 150 k

VPOR power-on reset voltage [3] -1.01.6V

CIinput capacitance [4] --7pF

I2C-bus; pins SDA and SCL

VIL LOW-level input voltage VSS -0.3V

DD V

VIH HIGH-level input voltage 0.7VDD -6.0 V

IOH(CLK) HIGH-level output current on

pin CLK output source current;

VOH =4.0V; V

DD =5.0V 1--mA

IOL(SDA) LOW-level output current on

pin SDA output sink current;

VOL =0.4V; V

DD =5.0V 3--mA

Product data sheet Rev. 11 — 30 March 2012 34 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

[1] VLCD  VDD  3 V for 1⁄3 bias.

[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3] Resets all logic when VDD < VPOR.

[4] Periodically sampled, not 100 % tested.

[5] Outputs measured one at a time.

10.1 Typical supply current characteristics

LCD outputs

VBP voltage on pin BP Cbpl = 35 nF; on pins BP0 to BP3 20 - +20 mV

VSvoltage on pin S Csgm = 5 nF; on pins S0 to S39 20 - +20 mV

RBP resistance on pin BP VLCD =V

DD 5 V; on pins BP0 to BP3 [5] --5k

RSresistance on pin S VLCD =V

DD 5 V; on pins S0 to S39 [5] --7.5k

Table 15. Static characteristics …continued

VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD



6.0 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VDD = 5 V; VLCD = 0 V; Tamb = 25 CV

DD = 5 V; VLCD = 0 V; Tamb = 25 C

Fig 23. ISS as a function of ffr Fig 24. IDD(LCD) as a function of ffr

mbe530

0 200

100

ISS

(μA)

ffr (Hz)

normal

mode

power-saving

mode

mbe529

0 200

100 ffr (Hz)

−IDD(LCD)

(μA)

Product data sheet Rev. 11 — 30 March 2012 35 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

10.2 Typical LCD output characteristics

VLCD = 0 V; external clock; Tamb = 25 CV

LCD = 0 V; external clock; Tamb = 25 C

Fig 25. ISS as a function of VDD Fig 26. IDD(LCD) as a function of VDD

010

mbe528

ISS

(μA)

VDD (V)

power-saving mode

fclk = 35 kHz

normal mode

fclk = 200 kHz

mbe527

010

5VDD (V)

85 °C

25 °C

−40 °C

−IDD(LCD)

(μA)

VLCD = 0 V; Tamb = 25 CV

DD = 5 V; VLCD = 0 V

Fig 27. RO(max) as a function of VDD Fig 28. RO(max) as a function of Tamb

−1

mbe532

(V)

O(max)

(kΩ)

−40 0 40 120

2.5

2.0

mbe526

1.5

1.0

0.5

RBP

RO(max)

(kΩ)

Tamb (°C)

Product data sheet Rev. 11 — 30 March 2012 36 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

11. Dynamic characteristics

[1] fclk < 125 kHz, I2C-bus maximum transmission speed is derated.

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 16. Dynam ic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Timin g characteristics: driver timing waveforms (see Figure 29)

fclk clock frequency normal-power mode;

VDD = 5 V [1] 125 200 315 kHz

power-saving mode;

VDD =3 V 21 31 48 kHz

tclk(H) clock HIGH time 1 - - s

tclk(L) clock LOW time 1 - - s

tPD(SYNC_N) SYNC propagation delay - - 400 ns

tSYNC_NL SYNC LOW time 1 - - s

tPD(drv) driver propagation delay VLCD = 5 V --30s

Timin g characteristics: I2C-bus (see Figure 30)[2]

tBUF bus free time between a STOP and START

condition 4.7 - - s

tHD;STA hold time (repeated) START condition 4.0 - - s

tSU;STA set-up time for a repeate d START condition 4.7 - - s

tLOW LOW period of the SCL clock 4.7 - - s

tHIGH HIGH period of the SCL clock 4.0 - - s

trrise time of both SDA and SCL signals - - 1 s

tffall time of both SDA and SCL signals - - 0.3 s

Cbcapacitive load for each bus line - - 400 pF

tSU;DAT data set-up time 250 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP condition 4.0 - - s

Product data sheet Rev. 11 — 30 March 2012 37 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 29. Driver timing waveforms

Fig 30. I2C-bus timing waveforms

mce424

0.7VDD

0.3VDD

0.7VDD

0.3VDD

SYNC

CLK

0.5 V

tPD(drv)

tPD(SYNC_N)

BP0 to BP3,

and S0 to S39

tPD(SYNC_N)

tSYNC_NL

(VDD = 5 V)

1/fCLK tclk(L)

tclk(H)

SDA

mga728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

Product data sheet Rev. 11 — 30 March 2012 38 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

12. Application information

12.1 Cascaded operation

In large display configurations, up to 16 PCF8576Cs can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I2C-bus slave address (SA0).

Cascaded PCF8576Cs are synchronized. The y can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through - pla te d to

the backplane electrodes of the display. The other PCF8576Cs of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 31).

Table 17. Addressing cascaded PCF8576C

Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

Product data sheet Rev. 11 — 30 March 2012 39 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8576Cs. This synch ro niz at i on is guara nt e ed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs

with differing SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor . A PCF8576C asserts the SYNC line and

monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is

restored by the first PCF8576C to assert SYNC. The timing relationship between the

backplane wave forms and the SYNC signal for the var ious drive modes o f the PCF857 6C

are shown in Figure 32.

Fig 31. Cascaded PCF8576C configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC 4 backplanes

40 segment drives

LCD PANEL

(up to 2560

elements)

PCF8576C

A0 A1 A2 SA0 VSS

VDD

VSS

VLCD

VDD VLCD

013aaa299

SDA

SCL

SYNC

CLK

OSC BP0 to BP3

(open-circuit)

A0 A1 A2 SAO VSS

VDD VLCD

PCF8576C

BP0 to BP3

40 segment drives

Rtr

2Cb

≤

Product data sheet Rev. 11 — 30 March 2012 40 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous

synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an

external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse

can be countered by an external pull-up resistor.

Fig 32. Syn chronization of the cascade for the various PCF8576C drive mod es

Tfr =ffr

BP0

SYNC

BP0

(1/2 bias)

SYNC

BP0

(1/3 bias)

(a) static drive mode.

(b) 1:2 multiplex drive mode.

(d) 1:4 multiplex drive mode.

BP0

(1/3 bias)

SYNC

BP0

(1/3 bias)

mgl755

Product data sheet Rev. 11 — 30 March 2012 41 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 33. Single plan e wiring of packaged PCF8576CT

PCF8576CT

SDA

SCL

SYNC

CLK

VDD

VSS

VLCD

OSC

SA0

BP0

BP2

BP1

BP3

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S17

S10

S11

S16

S15

S13

S14

S12

PCF8576CT

BP0

BP2

BP1

BP3

S40

S41

S42

S43

S79

S78

S77

S76

S75

S74

S73

S72

S71

S70

S69

S68

S67

S66

S65

S64

S63

S62

S61

S57

S47

S48

S49

S50

S51

S51 S52 S53

S56

S55

S53

S54

S52

S50S39 S40S13S12

open

S10 S11S0 S79

backplanes segments mbe537

SDA

SCL

SYNC

CLK

VDD

VSS

VLCD

Product data sheet Rev. 11 — 30 March 2012 42 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

13. Package outline

Fig 34. Package outline SOT314-2 (LQFP64) of PCF8576CHL/1

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 10.1

9.9 0.5 12.15

11.85 1.45

1.05 7

0.12 0.11 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2 MS-026136E10 00-01-19

03-02-25

D(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

EA1

detail X

(A )

HA2

vMB

vMA

48 33

pin 1 index

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

Product data sheet Rev. 11 — 30 March 2012 43 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 35. Package outline SOT190-1 (VSO56) of PCF8576CT/1

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

0.3

0.1 3.0

2.8 0.25 0.42

0.30 0.22

0.14 21.65

21.35 11.1

11.0 0.75 15.8

15.2 1.45

1.30 0.90

0.55 7

0.1 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

1.6

1.4

SOT190-1 97-08-11

03-02-19

detail X

vMA

(A )

56 29

281

pin 1 index

0.012

0.004 0.12

0.11 0.017

0.012 0.0087

0.0055 0.85

0.84 0.44

0.43 0.0295

2.25

0.089

0.62

0.60 0.057

0.051 0.035

0.022

0.004

0.2

0.008 0.004

0.063

0.055

0.01

0 5 10 mm

scale

VSO56: plastic very small outline package; 56 leads SOT190-1

max.

3.3

0.13

Notes

1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Product data sheet Rev. 11 — 30 March 2012 44 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 36. Package outline SOT793-1 (HTSSOP56) of PCF8576CTT/1

UNIT A

max. A1A2A3bpceH

ELL

pywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.2 0.15

0.05 1.05

0.80 0.25 0.27

0.17 0.20

0.09 4.3

4.1 0.5 8.3

7.9 0.4

0.1 8

0.08 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.8

0.4

SOT793-1 143E36T MO-153 03-03-04

D(1)

14.1

13.9

E(2)

6.2

6.0

DhZ(1)

4.3

4.1

vMA

D E

detail X

(A3)

yexposed die pad

pin 1 index

bpwM

HTSSOP56: plastic thermal enhanced thin shrink small outline package; 56 leads;

body width 6.1 mm; exposed die pad SOT793-1

0 2.5 5 mm

scale

Product data sheet Rev. 11 — 30 March 2012 45 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

14. Bare die outline

Fig 37. Bare die outline of PCF8576CU/F1

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

PCF8576CU

pcf8576cu_do

Unit

mm max

nom

min 0.38 2.92 0.610

0.096 0.110 0.097 0.110

Dimensions

Note

1. Pad size

2. Passivation opening

3. Dimension not drawn to scale

4. Marking code: PC8576C-1

Wire bond die; 56 bonding pads; 3.2 x 2.92 x 0.38 mm PCF8576CU

3.2

e(3) P1(1) P2(2) P3(1) P4(2)

0.097

0 0.5 1 mm

scale

detail X

00y

(4)

51 56 1 7

2134

09-06-02

12-03-22

Product data sheet Rev. 11 — 30 March 2012 46 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 38. Bare die outline of PCF8576CU/2/F 2

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

PCF8576CU/2

pcf8576cu_2_do

Unit

mm max

nom

min 0.398 0.0175 0.094 2.92 3.2 0.610

0.096

Dimensions

Note

1. Dimension not drawn to scale

2. Marking code: PC8576C-2

Bare die; 56 bumps; 3.2 x 2.92 x 0.40 mm PCF8576CU/2

A1A2

0.380

bDEe

(1) L

0.094

0 0.5 1 mm

scale

detail X

00y

(2)

51 56 1 7

2134

detail Y

AA2

09-06-02

12-03-22

Product data sheet Rev. 11 — 30 March 2012 47 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Table 18. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol Pad X (m) Y (m) Description

SDA 1 74 1380 I2C-bus serial data input/output

SCL 2 148 1380 I2C-bus serial clock input

SYNC 3 355 1380 cascade synchronization input/output

CLK 4 534 1380 external clock input/output

VDD 5 742 1380 supply voltage

OSC 6 913 1380 internal oscillator enable input

A0 7 1087 1380 subaddress input

A1 8 1290 1284 subaddress input

A2 9 1290 1116 subaddress input

SA0 10 1290 945 subaddress input

VSS 11 1290 751 logic ground

VLCD 12 1290 485 LCD supply voltage

BP0 13 1290 125 LCD backplane output

BP2 14 1290 285 LCD backplane output

BP1 15 1290 458 LCD backplane output

BP3 16 1290 618 LCD backplane output

S0 17 1290 791 LCD segment output

S1 18 1290 951 LCD segment output

S2 19 1290 1124 LCD segment output

S3 20 1290 1284 LCD segmen t output

S4 21 1074 1380 LCD segmen t output

S5 22 914 1380 LCD segment output

S6 23 741 1380 LCD segment output

S7 24 581 1380 LCD segment output

S8 25 408 1380 LCD segment output

S9 26 248 1380 LCD segment output

S10 27 75 1380 LCD segment output

S11 28 85 1380 LCD segment output

S12 29 258 1380 LCD segment ou tput

S13 30 418 1380 LCD segment ou tput

S14 31 591 1380 LCD segment ou tput

S15 32 751 1380 LCD segment ou tput

S16 33 924 1380 LCD segment ou tput

S17 34 1084 1380 LCD segmen t output

S18 35 1290 1243 LCD segmen t output

S19 36 1290 1083 LCD segmen t output

S20 37 1290 910 LCD segment output

S21 38 1290 750 LCD segment output

S22 39 1290 577 LCD segment output

Product data sheet Rev. 11 — 30 March 2012 48 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

S23 40 1290 417 LCD segment output

S24 41 1290 244 LCD segment output

S25 42 1290 84 LCD segment output

S26 43 1290 89 LCD segment output

S27 44 1290 249 LCD segment output

S28 45 1290 422 LCD segment output

S29 46 1290 582 LCD segment output

S30 47 1290 755 LCD segment output

S31 48 1290 915 LCD segment output

S32 49 1290 1088 LCD segment output

S33 50 1290 1248 LCD segment output

S34 51 1083 1380 LCD segment output

S35 52 923 1380 LCD segment outp ut

S36 53 750 1380 LCD segment outp ut

S37 54 590 1380 LCD segment outp ut

S38 55 417 1380 LCD segment outp ut

S39 56 257 1380 LCD segment outp ut

Table 19. Alignment marks

Symbol X (m) Y (m)

C1 1290 1385

C2 1295 1385

F 1305 1405

Table 18. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol Pad X (m) Y (m) Description

Product data sheet Rev. 11 — 30 March 2012 49 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

16. Packing information

16.1 Tray information

Tray information for the PCF8576CU/F1 and PCF8576CU/2/F2 is shown in Figure 39,

Figure 40 and Table 20.

Fig 39. T ray details

001aai237

A C

Product data sheet Rev. 11 — 30 March 2012 50 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 40. Tray alignment

Table 20. Tray dimensions

Symbol Description Value

A pocket pitch; x direction 5.59 mm

B pocket pitch; y direction 6.35 mm

C pocket width; x direction 3.22 mm

D pocket width; y direction 3.50 mm

E tray width; x direction 50.67 mm

F tray width; y direction 50.67 mm

G cut corner to pocket 1,1 center 5.78 mm

H cut corner to pocket 1,1 center 6.29 mm

J tray thickness 3.94 mm

K tray cross section 1.76 mm

L tray cross section 2.46 mm

M pocket depth 0.89 mm

x number of pockets; x direction 8

y number of pockets; y direction 7

001aaj619

marking code

Product data sheet Rev. 11 — 30 March 2012 51 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 11 — 30 March 2012 52 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

17.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 41) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low en ough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 21 and 22

Moisture sensitivity precautions, as indicated on the packin g, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 41.

Table 21. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 22. Lead-free process (from J-STD-020C)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 11 — 30 March 2012 53 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 41. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 11 — 30 March 2012 54 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

18. Abbreviations

Table 23. Abbreviations

Acronym Description

CDM Charged-Device Model

DC Direct Current

HBM Human Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LCD Liquid Crystal Display

LSB Least Significant Bit

MM Machine Model

MOS Metal-Oxide Semiconductor

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

POR Power-On Reset

RC Resistance-Capacitance

RAM Random Access Memory

RMS Root Mean S qu a re

SCL Serial CLock line

SDA Serial DAta line

SMD Surface-Mount Device

Product data sheet Rev. 11 — 30 March 2012 55 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

19. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10365 — Surface mount reflow soldering description

[3] AN10706 — Handling bare die

[4] IEC 60 13 4 — Rating syst ems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/R eflow Sensitivity Classific ation for

Nonhermetic Solid State Surface Mount Devices

[7] JESD 22 -A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD 22 -A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[10] JESD78 — IC Latch-Up Test

[11] NX3-00092 — NXP store and transport requirements

[12] SNV-FA-01-02 — Marking Formats Integrated Circuits

[13] UM10204 — I2C-bus specification and user manual

Product data sheet Rev. 11 — 30 March 2012 56 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

20. Revision history

Table 24. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8576C v.11 20120330 Product data sheet - PCF8576C v.10

Modifications: •Adjusted die size information

•Added Section 7.3.1

PCF8576C v.10 20100722 Product data sheet - PCF8576C v.9

PCF8576C v.9 20090709 Product data sheet - PCF8576C v.8

PCF8576C v.8 20041122 Product specification - PCF8576C v.7

PCF8576C v.7 20011002 Product specification - PCF8576C v.6

PCF8576C v.6 19980730 Product specification - PCF8576C v.5

PCF8576C v.5 19971114 Product specification - PCF8576C v.4

PCF8576C v.4 19970402 Product specification - PCF8576C v.3

PCF8576C v.3 19970203 Product specification - PCF8576C v.2

PCF8576C v.2 19961209 Product specification - PCF8576C v.1

PCF8576C v.1 19950630 Product specification - -

Product data sheet Rev. 11 — 30 March 2012 57 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

21. Legal information

21.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

21.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full dat a

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

21.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, lif e-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe propert y or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property right s.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains dat a from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the prod uct specification.

Product data sheet Rev. 11 — 30 March 2012 58 of 61

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever cust omer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English version s.

Bare die — All die are tested on compliance with their related tech nical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditione d upon and sub ject to the custo mer enter ing into a

written die sale agreement with NXP Semiconductors through its legal

department.

21.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 11 — 30 March 2012  59 of 61
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
23. Tables
Table 1.  Ordering information  . . . . . . . . . . . . . . . . . . . . .2
Table 2.  Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3.  Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4.  Selecti on of possible display configurations. . . .9
Table 5.  Biasing characteristics . . . . . . . . . . . . . . . . . . .11
Table 6.  LCD frame frequencies [1]  . . . . . . . . . . . . . . . .19
Table 7.  Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .24
Table 8.  Defi nition of PCF8576C commands . . . . . . . . .29
Table 9.  Mode-set command bit description  . . . . . . . . .29
Table 10.  Load-data-pointer command bit description . . .29
Table 11.  Device-select command bit description . . . . . .30
Table 12.  Bank-select command bit description  . . . . . . .30
Table 13.  Blink-select comma nd  bit description . . . . . . . .30
Table 14.  Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 15.  Static characteristics  . . . . . . . . . . . . . . . . . . . .33
Table 16.  Dynamic characteristics . . . . . . . . . . . . . . . . . .36
Table 17.  Addressing cascaded PCF8576C . . . . . . . . . .38
Table 18.  Pad and bump descri ption for PCF8576CU . . .47
Table 19.  Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .48
Table 20.  Tray dimensions   . . . . . . . . . . . . . . . . . . . . . . .50
Table 21.  SnPb eutectic process (from J-STD-020C) . . .52
Table 22.  Lead-free process (from J-STD-020C)  . . . . . .52
Table 23.  Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 24.  Revision history . . . . . . . . . . . . . . . . . . . . . . . .56

PCF8576C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 11 — 30 March 2012  60 of 61
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
24. Figures
Fig 1.  Block diagram of PCF8576C .  . . . . . . . . . . . . . . . .3
Fig 2.  Pin configuration for LQFP64 
(PCF8576CHL/1). . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 3.  Pin configuration for VSO56 
(PCF8576CT/1) . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fig 4.  Pin configuration for HTSSOP56 
(PCF8576CTT/1) . . . . . . . . . . . . . . . . . . . . . . . . . .6
Fig 5.  Pin locations of PCF8576CU/F1 and 
PCF8576CU/2/F2 . . . . . . . . . . . . . . . . . . . . . . . . .7
Fig 6.  Example of displays suitable for PCF8576C . . . . .9
Fig 7.  Typical system configuration . . . . . . . . . . . . . . . .10
Fig 8.  Electro-optical characteristic: relative 
transmission curve of the liquid . . . . . . . . . . . . . .13
Fig 9.  Static drive mode waveforms. . . . . . . . . . . . . . . .14
Fig 10.  Waveforms for the 1:2 multiplex drive mode 
with 1⁄2 bias  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 11.  Waveforms for the 1:2 multiplex drive mode 
with 1⁄3 bias  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Fig 12.  Waveforms for the 1:3 multiplex drive mode 
with 1⁄3 bias  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 13.  Waveforms for the 1:4 multiplex mode 
with 1⁄3 bias  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Fig 14.  Display RAM bit map. . . . . . . . . . . . . . . . . . . . . .21
Fig 15.  Relationship between LCD layout, drive mode, 
display RAM filling order, and display data 
transmitte d ove r  th e I 2C-bus . . . . . . . . . . . . . . . .22
Fig 16.  Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 17.  Definition of START and STOP conditions. . . . . .25
Fig 18.  System configuration . . . . . . . . . . . . . . . . . . . . . .26
Fig 19.  Acknowledgement of the I2C-bus  . . . . . . . . . . . .27
Fig 20.  I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .28
Fig 21.  General format of the command byte  . . . . . . . . .28
Fig 22.  Device protection diagram. . . . . . . . . . . . . . . . . .31
Fig 23.  ISS as a function of ffr . . . . . . . . . . . . . . . . . . . . . .34
Fig 24.  -IDD(LCD) as a function of ffr. . . . . . . . . . . . . . . . . .34
Fig 25.  ISS as a function of VDD . . . . . . . . . . . . . . . . . . . .35
Fig 26.  -IDD(LCD) as a function of VDD. . . . . . . . . . . . . . . .35
Fig 27.  RO(max) as a function of VDD. . . . . . . . . . . . . . . . .35
Fig 28.  RO(max) as a function of Tamb . . . . . . . . . . . . . . . .3 5
Fig 29.  Driver timing waveforms  . . . . . . . . . . . . . . . . . . .3 7
Fig 30.  I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .37
Fig 31.  Cascaded PCF8576C configuration  . . . . . . . . . .39
Fig 32.  Synchronization of the cascade for the  various 
PCF8576C drive modes  . . . . . . . . . . . . . . . . . . .40
Fig 33.  Single plane wiring of packaged PCF8576CT.  . .41
Fig 34.  Package outline SOT314-2 (LQFP64) of 
PCF8576CHL/1 . . . . . . . . . . . . . . . . . . . . . . . . . .42
Fig 35.  Package outline SOT190-1 (VSO56) of 
PCF8576CT/1 . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Fig 36.  Package outline SOT793-1 (HTSSOP56) of 
PCF8576CTT/1 . . . . . . . . . . . . . . . . . . . . . . . . . .44
Fig 37.  Bare die outline of PCF8576CU/F1. . . . . . . . . . .45
Fig 38.  Bare die outline of PCF8576CU/2/F2 . . . . . . . . .46
Fig 39.  Tray details  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 40.  Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Fig 41.  Tempera ture  profiles for large and small 
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 March 2012
Document identifier: PCF8576C
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’. 
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features and benefits . . . . . . . . . . . . . . . . . . . .  1
Ordering information. . . . . . . . . . . . . . . . . . . . .  2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
1  Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
2  Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  8
Functional description . . . . . . . . . . . . . . . . . . .  9
1  Power-On-Reset (POR) . . . . . . . . . . . . . . . . .  10
2  LCD bias generator  . . . . . . . . . . . . . . . . . . . .  10
3  LCD voltage selector  . . . . . . . . . . . . . . . . . . .  11
3.1  Electro-optical performance . . . . . . . . . . . . . .  12
4  LCD drive mode waveforms. . . . . . . . . . . . . .  14
4.1  Static drive mode . . . . . . . . . . . . . . . . . . . . . .  14
4.2  1:2 Multiplex drive mode. . . . . . . . . . . . . . . . .  15
4.3  1:3 Multiplex drive mode. . . . . . . . . . . . . . . . .  17
4.4  1:4 multiplex drive mode. . . . . . . . . . . . . . . . .  18
5  Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
5.1  Internal clock  . . . . . . . . . . . . . . . . . . . . . . . . .  19
5.2  External clock. . . . . . . . . . . . . . . . . . . . . . . . .  19
6  Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
7  Display register. . . . . . . . . . . . . . . . . . . . . . . .  20
8  Shift register . . . . . . . . . . . . . . . . . . . . . . . . . .  20
9  Segment outputs. . . . . . . . . . . . . . . . . . . . . . .  20
10  Backplane outputs . . . . . . . . . . . . . . . . . . . . .  20
11  Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . .  20
12  Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . .  23
13  Sub-address counte r  . . . . . . . . . . . . . . . . . . .  23
14  Bank selector . . . . . . . . . . . . . . . . . . . . . . . . .  24
14.1  Output bank selector  . . . . . . . . . . . . . . . . . . .  24
14.2  Input bank selector. . . . . . . . . . . . . . . . . . . . .  24
15  Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
16  Characteristics of the I2C-bus. . . . . . . . . . . . .  25
16.1  Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
16.2  START and STOP conditions . . . . . . . . . . . . .  25
16.3  System configuration . . . . . . . . . . . . . . . . . . .  26
16.4  Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .  26
16.5 PCF8576C I2C-bus controller. . . . . . . . . . . . .  27
16.6  Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
17 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .  27
18  Command decoder. . . . . . . . . . . . . . . . . . . . .  28
18.1  Mode-set command . . . . . . . . . . . . . . . . . . . .  29
18.2  Load-data-pointer command. . . . . . . . . . . . . .  29
18.3  Device-select command. . . . . . . . . . . . . . . . .  30
18.4  Bank-select command . . . . . . . . . . . . . . . . . .  30
18.5  Blink-select command  . . . . . . . . . . . . . . . . . .  30
19  Display controller . . . . . . . . . . . . . . . . . . . . . .   30
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .   31
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .   32
Static characteristics . . . . . . . . . . . . . . . . . . .   33
1  Typical supply current characteristics  . . . . . .   34
2  Typical LCD output characteristics. . . . . . . . .   35
Dynamic characteristics. . . . . . . . . . . . . . . . .   36
Application information . . . . . . . . . . . . . . . . .   38
1  Cascaded operation. . . . . . . . . . . . . . . . . . . .   38
Package outline. . . . . . . . . . . . . . . . . . . . . . . .   42
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .   45
Handling information . . . . . . . . . . . . . . . . . . .   49
Packing information . . . . . . . . . . . . . . . . . . . .   49
1  Tray information. . . . . . . . . . . . . . . . . . . . . . .   49
Soldering of SMD packages. . . . . . . . . . . . . .   51
1  Introduction to soldering. . . . . . . . . . . . . . . . .   51
2  Wave and reflow soldering. . . . . . . . . . . . . . .   51
3  Wave soldering  . . . . . . . . . . . . . . . . . . . . . . .   51
4  Reflow soldering  . . . . . . . . . . . . . . . . . . . . . .   52
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .   54
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .   55
Revision history  . . . . . . . . . . . . . . . . . . . . . . .   56
Legal information . . . . . . . . . . . . . . . . . . . . . .   57
1  Data sheet status. . . . . . . . . . . . . . . . . . . . . .   57
2  Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .   57
3  Disclaimers  . . . . . . . . . . . . . . . . . . . . . . . . . .   57
4  Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .   58
Contact information . . . . . . . . . . . . . . . . . . . .   58
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   59
Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   60
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   61