MM74HC00 — Quad 2-Input NAND Gate
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0
February 2008
MM74HC00
Quad 2-Input NAND Gate
Features
■
Typical propagation delay: 8ns
■
Wide power supply range: 2V–6V
■
Low quiescent current: 20µA maximum (74HC Series)
■
Low input current: 1µA maximum
■
Fanout of 10 LS-TTL loads
General Description
The MM74HC00 NAND gates utilize advanced silicon-
gate CMOS technology to achieve operating speeds
similar to LS-TTL gates with the low power consumption
of standard CMOS integrated circuits. All gates have
buffered outputs. All devices have high noise immunity
and the ability to drive 10 LS-TTL loads. The 74HC logic
family is functionally as well as pin-out compatible with
the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to V
CC
and ground.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
Order Number
Package
Number Package Description
MM74HC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 2
MM74HC00 — Quad 2-Input NAND Gate
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5 to +7.0V
V
IN
DC Input Voltage –1.5 to V
CC
+1.5V
V
OUT
DC Output Voltage –0.5 to V
CC
+0.5V
I
IK
, I
OK
Clamp Diode Current ±20mA
I
OUT
DC Output Current, per pin ±25mA
I
CC
DC V
CC
or GND Current, per pin ±50mA
T
STG
Storage Temperature Range –65°C to +150°C
P
D
Power Dissipation
Note 2 600mW
S.O. Package only 500mW
T
L
Lead Temperature (Soldering 10 seconds) 260°C
Symbol Parameter Min. Max. Units
V
CC
Supply Voltage 2 6 V
V
IN
, V
OUT
DC Input or Output Voltage 0 V
CC
V
T
A
Operating Temperature Range –40 +85 °C
t
r
, t
f
Input Rise or Fall Times
V
CC
=
2.0V 1000 ns
V
CC
=
4.5V 500 ns
V
CC
=
6.0V 400 ns
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 3
MM74HC00 — Quad 2-Input NAND Gate
DC Electrical Characteristics
(3)
Note:
3. For a power supply of 5V ±10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and I
OZ
) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
T
A
=
–40°C
to 85°C
T
A
=
–55°C
to 125°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
2.0 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
IL
Maximum LOW Level
Input Voltage
2.0 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
V
OH
Minimum HIGH Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
2.0 1.9 1.9 1.9 V
4.5 4.5 4.4 4.4 4.4
6.0 6.0 5.9 5.9 5.9
4.5 V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
4.2 3.98 3.84 3.7
6.0 V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
5.2mA
5.7 5.48 5.34 5.2
V
OL
Maximum LOW Level
Output Voltage
2.0 V
IN
=
V
IH
,
|I
OUT
|
≤
20µA
0 0.1 0.1 0.1 V
4.5 0 0.1 0.1 0.1
6.0 0 0.1 0.1 0.1
4.5 V
IN
=
V
IH
,
|I
OUT
|
≤
4.0mA
0.2 0.26 0.33 0.4
6.0 V
IN
=
V
IH
,
|I
OUT
|
≤
5.2mA
0.2 0.26 0.33 0.4
I
IN
Maximum Input
Current
6.0 V
IN
=
V
CC
or GND ±0.1 ±1.0 ±1.0 µA
I
CC
Maximum Quiescent
Supply Current
6.0 V
IN
=
V
CC
or GND,
I
OUT
=
0µA
2.0 20 40 µA
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 4
MM74HC00 — Quad 2-Input NAND Gate
AC Electrical Characteristics
V
CC
= 5V, T
A
= 25°C, C
L
= 15pF, t
r
= t
f
= 6ns
AC Electrical Characteristics
V
CC
= 2.0V to 6.0V, C
L
= 50pF, t
r
= t
f
= 6ns (unless otherwise specified)
Note:
4. C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
=
C
PD
V
CC
f + I
CC
.
Symbol Parameter Conditions Typ.
Guaranteed
Limit Units
t
PHL
, t
PLH
Maximum Propagation Delay 8 15 ns
Symbol Parameter VCC (V) Conditions
TA = 25°C
TA = –40°C
to 85°C
TA = –55°C
to 125°C
UnitsTyp. Guaranteed Limits
tPHL, tPLH Maximum
Propagation Delay
2.0 45 90 113 134 ns
4.5 9 18 23 27
6.0 8 15 19 23
tTLH, tTHL Maximum Output
Rise and Fall Time
2.0 30 75 95 110 ns
4.5 8 15 19 22
6.0 7 13 16 19
CPD Power Dissipation
Capacitance(4) (per gate) 20 pF
CIN Maximum Input
Capacitance
510 10 10 pF
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 5
MM74HC00 — Quad 2-Input NAND Gate
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25 0.25
0.10 0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 6
MM74HC00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 7
MM74HC00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 8
MM74HC00 — Quad 2-Input NAND Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC00 Rev. 1.3.0 9
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Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
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This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
MM74HC00 — Quad 2-Input NAND Gate
