1
P/N:PM0669 REV. 0.1, AUG. 07, 2000
MX98727BEC
3.3V SINGLE-CHIP 10/100 Mbps ETHERNET
CARDBUS CONTROLLER
Feature
10/100 M Ethernet Interface
• Fully comply to IEEE 802.3 and ANSI 8802-3 Ethernet
standards
• Operates over 100 meters of STP and category 5 UTP
cable
• Support full duplex operation in both 100 Base-TX and
10 Base-T modes
• Support 802.3x "Frame Based Flow Control" scheme
in full duplex mode
• Support network and communication device class
OnNow requirements for Microsoft's PC99 specifica-
tions, including all wake-up events:
1. Magic PacketTM
2. Wake-up Frames
3. Link Change
4. Modem Phone Ring
• Support 10 Mb/s and 100 Mb/s NWAY auto negotiation
function
• Support a variety of flexible address filtering modes
with 16 CAM addresses and 64 bits hash
• Support up to 5 LED output for various network activity
indications
• Support TX traffic prioritization for QoS feature
• Support 802.1Q tagged frames
General Description
The MX98727BEC, single chip 10/100M fast Ethernet
controller, is designed to interface directly with 3.3V
CardBus bus and 10/100 Base-T F ast Ethernet network
without external transceiver .
High speed CardBus master interface is implemented
to support 100Mb/s fast Ethernet with fast packet buffer
management. On chip control registers and CardBus
configuration registers provide interface to host system
for automatic bus master configuration and driver con-
trols. As a CardBus bus master, MX98727BEC incor-
porates large on chip FIFOs which provides effective
local packet buffers, therefore no external local buffer
memory is needed.
The MX98727BEC implements all Media Access Con-
trol (MAC) layer functions for transmission, reception,
NWAY auto-negociation and 10/100M transceivers in ac-
cordance with the IEEE 802.3/802.3u standard.
Full duplex and half duplex are both supported for differ-
ent applications. A packet buffer is located in the host
memory that is used by software driver for all incoming
and outgoing packets. This buffer area is shared by both
transmit process and receive process. During reception,
the MX98727BEC stores packets in the receive buffer
area, then indicates receive status and control informa-
tion in the descriptor area.
Cardbus Features
• Compliant to CardBus specification of PC Card Stan-
dard 6.1
• Bus master architecture with linked host buffers deliv-
ers world class performance
• 32-bit bus master DMA channel provides ultra low CPU
utilization
• Support CardBus Card Information Structure (CIS)
body stored in a 4k-bit Serial EEPROM or Flash ROM.
• Support CardBus unlimit burst, read line, read multiple,
write and invalidate commands
• Support CardBus clock control through CLKRUNB pin
• Support CardBus CSTSCHG pin and Status Changed
registers
Modem Interface
• Provides an interface to a wide range of modem
chipsets available in the market
• Large on chip FIFOs for both transmit and receive
operations without external local memory
• Support up to 128K bytes boot ROM interface
• MicroWire interface to Serial EEPROM containing
Subsystem ID, Card Information Structure (CIS) pointer,
Ethernet address and so on
• 3.3V operating power , 128-pin LQFP package with
standard CMOS technology
• Support dual Function Cardbus for 10/100 Mb/s
Ethernet and Modem interface
• Support early interrupt for transmit and receive
Other Features
( Magic PacketTM Technology is a trademark of Ad-
vanced Micro Device Corp. )
PRELIMINARY
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
2.0 Pin Configuration
This packet buffer is also used by transmit process which
can transmit multiple packets from a single transmit com-
mand. Minimum-sized back-to-back packets at full line
speed with interframe gap ( IPG ) of 0.96us in 100 Base-
TX mode is eff ortless with MX98727BEC .
Furthermore, advanced power management not only
save electric energy but also network maintenance effi-
ciency through the application of Wake-On-LAN and Re-
mote-Power-On.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
BPA4(MDMDTA2)
BPA3(MDMDTA1)
BPA2(MDMDTA0)
BPA1(EEDI)(MDMADR2)
BPA0(EECK)(MDMADR1)
EECS
BPD0(EED0)
BPD1(MDMADR0)
BPD2(MDMPWRDN)
BPD3(MDMDTA7)
BPD4(MDMINT)
BPD5(MDMRING)
BPD6(MDMWAITB)
BPD7(MDMADR4)
GND
VDD
AD0
AD1
GND
AD2
AD3
VDD
AD4
AD5
GND
AD6
VDDA
GNDA
VDDR
GNDR
CLKRUNB
NC
CSTSCHG
PMEB
INTAB
RSTB
CBCLK
GNTB
REQB
AD31
AD30
GND
AD29
AD28
VDD
AD27
GND
AD26
AD25
GND
AD24
CBEB3
GND
GND
AD23
AD22
GND
AD21
AD20
VDD
AD19
AD18
GND
AD17
AD16
CBEB2
FRAMEB
GND
IRDYB
TRDYB
DEVSELB
STOPB
VDD
PERRB
SERRB
PAR
CBEB1
AD15
GND
AD14
AD13
VDD
AD12
AD11
AD10
GND
AD9
AD8
CBEB0
AD7
RTX
RTX2EQ
GNDA
TXOP
TXON
VDDA
GNDA
GNDR
VDDR
RXIP
RXIN
VDDR
GNDR
VDDA
GNDA
XO
XI/CKREF
VDDA
RDA
GNDA
VDDA
FOEB(LED3)
BPA16(LED2)
BPA15(LED1)
BPA14(LED0)
BPA13(LED4)
GND
VDD
BPA12(MDMSPKEN)
BPA11(MDMRSTB)
BPA10(MDMRDB)
BPA9(MDMADR3)
FCSB(MDMCSB)
FWEB(MDMWRB)
BPA8(MDMDTA6)
BPA7(MDMDTA5)
BPA6(MDMDTA4)
BPA5(MDMDTA3)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
MX98727BEC
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
3.0.1 Pin Description
T/S: tri-state, S/T/S : Sustained tri-state, I : input, O :output, O/D : open drain)
PIN NAME TYPE PIN NO. DE SCRIPTION
AD[31:0] T/S 116,117,119, CardBus address/data bus: shared CardBus address/data bus lines.
120,122,124 Little or big endian byte ordering are supported.
125, 127, 3, 4,
6,7,9,10,
12,13,26,28,
29,31,32,33,
35,36,38,39
41,42,44,45,
47,48
CBEB[3:0] T/S 128,14,25,37 CardBus command and byte enable bus: shared CardBus command
and byte enable bus, during the address phase of the transaction,
these four bits provide the bus command. During the data phase, these
four bits provide the byte enable.
FRAMEB S/T/S 15 CardBus FRAME# signal: shared CardBus cycle start signal, asserted
to indicate the beginning of a bus transaction. As long as FRAMEB is
asserted, data transf ers continue.
TRDYB S/T/S 18 CardBus Target ready: issued by the target agent, a data phase is
completed on the rising edge of CBCLK when both IRD YB and TRD YB
are asserted.
IRDYB S/T/S 18 CardBus Master ready: indicates the bus master's ability to complete
the current data phase of the transaction. A data phase is completed
on any rising edge of CBCLK when both IRDYB and TRDYB are as-
serted.
DEVSELB S/T/S 19 CardBus slav e device select: asserted by the target of the current bus
access. When 98727BEC is the initiator of current bus access, the
target must assert DEVSELB within 5 bus cycles , otherwise cycle is
aborted.
CBCLK I 113 CardBus clock input: CardBus clock range from 16MHZ up to 33MHZ.
RSTB I 112 CardBus reset: host system hardware reset.
INTAB O/D 111 CardBus interrupt request signal: wired to INT A# line.
SERRB O/D 23 CardBus system error signal: If an address parity error is detected
and CFCS bit 8 is enabled, SERR# and CFCS's bit 30 will be as-
serted.
PERRB S/T/S 22 CardBus data error signal: As a bus master , when a data parity error
is detected and CFCS bit 8 is enabled, PERR# and CFCS bit 24 and
CSR5 bit 13 will be asserted. As a bus target, a data parity error
cause PERR# to be asserted.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
PIN NAME TYPE PIN NO . DESCRIPTION
PAR T/S 2 4 CardBus parity bit: shared CardBus bus even parity bit for 32 bits AD
bus and CBE bus.
STOPB S/T/S 20 CardBus Target requested transfer stop signal: as b us master, asser-
tion of STOPB cause MX98727BEC either to retry, disconnect, or
abort.
REQB T/S 115 CardBus request signal: to initiate a bus master cycle request.
GNTB I 114 CardBus grant acknowledge signal: host asserts to inform
MX98727BEC that access to the bus is granted
PMEB O / D 11 0 Pow e r Management event: Asserted low to wake up host system when
the follow condition are met:
(1) PMC<8> is set or both EVENTMR<14> and EVENTMR<4> are
set.
(2) The po wer state is not in D0.
(3) One of the wake-up events occurred. Including
a. A magic packet is received.
b . A wake-up fr ame is receiv ed.
c. Link speed change.
d. MDMRING is asserted.
CSTSCHG O 109 Status Change pin
CLKRUNB I/O 107 CardBus clock run: indicates the CardBus cloc k status. When nor-
mal operation, the host system asserts the signal low . It is deasserted
by the host system when the clock is going to be slowed down to
another operational frequency.
The MX98727BEC samples the signal. When it is found deasserted,the
MX98727BEC asserts CLKRUNB, requesting normal clock operation
to be maintained.
FCSB/ O 7 0 BPCSB(MDMEN=0): Boot ROM or external latch chip select
MDMCSB MDMCSB(MDMEN=1): Modem chip select.
MDMEN is bit 0 of Func1_HW options in serial ROM, which is auto
loaded during booting up.
EECS O 59 Serial ROM chip select.
BPA0/EECK O 6 0 MDMEN=0: Boot ROM address line 0. MX98727BEC supports
MDMADR1 up to 32 KB boot ROM or serial PROM EECK pin
MDMEN=1: Modem address line 1. Address lines that
are not needed should be left unconnected.
BPA1/EEDI O 6 1 MDMEN=0: Boot ROM address line 1. MX98727BEC supports
MDMADR2 up to 32 KB boot ROM or serial PROM EEDI pin.
MDMEN=1: Modem address line 2. Address lines that
are not needed should be left unconnected.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
PIN NAME TYPE PIN NO . DESCRIPTION
BPA2/ O 62 MDMEN=0:Boot ROM address line 2. MX98727BEC supportsup
MDMDTA0 to 32 KB boot ROM.
MDMEN=1:Modem data line 0.
BPA3/ O 63 MDMEN=0:Boot ROM address line 3. MX98727BEC supportsup
MDMDTA1 to 32 KB boot ROM.
MDMEN=1:Modem data line 1.
BPA4/ O 64 MDMEN=0:Boot ROM address line 4. MX98727BEC supportsup
MDMDTA2 to 32 KB boot ROM.
MDMEN=1:Modem data line 2.
BPA5/ O 6 5 MDMEN=0: Boot ROM address line 5. MX98727BEC supportsup
MDMDTA3 to 32 KB boot ROM.
MDMEN=1: Modem data line 3.
BPA6/ O 6 6 MDMEN=0:Boot ROM address line 6. MX98727BEC supportsup
MDMDTA4 to 32 KB boot ROM.
MDMEN=1:Modem data line 4.
BPA7/ O 6 7 MDMEN=0 : Boot ROM address line 7. MX98727BEC supportsup
MDMDTA5 to 32 KB boot ROM.
MDMEN=1: Modem data line 5.
BPA8/ O 6 8 MDMEN=0 : Boot ROM address line 8. MX98727BEC supportsup
MDMDTA6 to 32 KB boot ROM.
MDMEN=1: Modem data line 6.
BPA9/ I/O 7 1 MDMEN=0 : Boot ROM address 9/Serial ROM output data pin.
MDMADR3 MDMEN=1: Modem address line 3. Address lines that are not needed
should be left unconnected.
BPA10/ I/O 7 2 MDMEN=0 : Boot ROM address line10/Serial ROM input data pin.
MDMRDB MDMEN=1 : Modem read line. This pin is activ e lo w.
BPA11/ O 7 3 MDMEN=0 : Boot ROM address line 11/Serial ROM clock pin.
MDMRSTB MDMEN=1 : Modem reset. This pin is activ e low upon hardware
reset.
BPA12/ O 7 4 MDMEN=0 : Boot ROM address line12.
MDMSPKEN MDMEN=1 : Modem speak er enable. This pin reflects the audio
enable bits of the modem function Status Changed Registers.
If Func1_HwOptions<7> bit in the Serial ROM is set, the value of the
Function Event Mask Register<6> is driven on the MDMSPKEN pin.
If Func1_HwOptions<7> is cleared, the value of Function Event Mask
Register<5> is driven on this pin.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
PIN NAME TYPE PIN NO . DESCRIPTION
BPA13/ O 7 7 Boot ROM address line13 or LED4 pin.
LED4
BPA14/ O 7 8 Boot ROM address line 14 or LED0 pin.
LED0
BPA15/ O 7 9 Boot ROM address line 15 or LED1pin
LED1
BPA16/ O 8 0 Boot ROM address line 16 or LED2 pin.
LED2
FOEB/ O 8 1 Flash/Boot PROM Output Enable pin or LED3 pin
LED3
BPD0/EEDO O 58 Boot ROM data line 0 or Serial ROM EEDO pin.
BPD1/ O 57 MDMEN=0 : Boot ROM data line 1.
MDMADR0 MDMEN=1 : Modem address line 0. Address lines that are not needed
should be left unconnected.
BPD2/ O 56 MDMEN=0 : Boot ROM data line 2.
MDMPWRDN MDMEN=1 : Modem power down. This pin is asserted when the
MX98727BEC is in D3 power state. It can be used by the modem
chipset power control. The polarity of this pin is determined by the
Func1_HwOption<5> bit is the Serial ROM.
BPD3/ O 55 MDMEN=0 : Boot ROM data line 3.
MDMDTA7 MDMEN=1 : Modem data line 7.
BPD4/ I/O 54 MDMEN=0 : Boot ROM data line 4.
MDMINT MDMEN=1: Modem interrupt line . When asserted, MX98727BEC
asserts the INTAB pin. This pin is active high.
BPD5/ I/O 53 MDMEN=0 : Boot ROM data line 5.
MDMRING MDMEN=1: Modem ring indicator . The assertion of this pin in power
down mode(D1, D2, D3) will assert PMEB to wak e up the host.
BPD6/ I/O 52 MDMEN=0 : Boot ROM data line 6.
MDMWAITB MDMEN=1: Modem wait pin. This pin's functionality is determined by
the Func1_HwOption<3> bit in the serial ROM.
When Func1_HwOption<3> is set, the modem can insert wait state
in modem chipset read and write transactions. In this mode,
MX98727BEC ignores this pin before starting the transactions and
examine its value only during the transaction.
When Func1_HwOption<3> is cleared, MX98727BEC examines the
pin after modem reset and won't start any transactions to the modem
chipsets bef ore this pin is deasserted.
This pin is active low . It is internally pulled up and can be left
unconnected.
BPD7/ O 51 MDMEN=0 : Boot ROM data line 7.
MDMADR4 MDMEN=1: Modem address line 4. Address lines that are not needed
should be left unconnected.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
PIN NAME TYPE PIN NO . DESCRIPTION
RTX O 10 2 Connecting an external 1K ohm resistor to ground
RTX2EQ O 101 Test Pin
RXIP I 9 3 Twisted pair receive differential input for 100BaseT
RXIN I 92 Twitsed pair receive differential input for 100BaseT
R D A O 8 4 Connecting an external 10K ohm resistor to ground
TXOP O 9 9 Twisted pair transmit differential output: Support both 10 BaseT and
100 Base-TX transmit differential output
TXON O 98 Twisted pair transmit differential output: Support both 10 BaseT and
100 Base-TX transmit differential output
XI/CKREF I 86 Reference clock: 25MHZ oscillator clock input or crystal input
XO O 8 7 25Mhz Crystal output pin
VDD A I 82,85,89, Analog power pins.
97,103,
GND A I 83,88, Analog Ground pins.
96,100,104,
VDDR I 91,94,105 RX analog Vdd
GNDR I 90,95,106 RX analog ground
VDD I 8,21,30, P ower for Core logic
43,49,75,121
G ND I 1,2,5,11, Ground for Core logic
16,27,34,40,
46,50,76,118,
123,126
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4. PROGRAMMING INTERFACE
4.1 NIC CARDBUS CONFIGURA TION REGISTERS (Function 0 ) :
4.1.1 NIC CARDBUS ID REGISTER ( CBID ) ( Offset 03h-00h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
4.1.2 NIC CARDBUS COMMAND AND ST ATUS REGISTER ( CBCS ) ( Offset 07h-04h )
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 enable IO access
bit 1 : Memory Space Access, set to 1 to enable memory access
bit 2 : Master Operation, set to 1 to support bus master mode
bit 5-3 : not used
bit 6 : P arity Error Response, set to 1 to enab le assertion of CSR<13> bit if parity error detected.
bit 7 : not used
bit 8 : System Error Enable, set to 1 to enable SERRB when parity error is detected on address lines and CBEB[3:0].
bit 20 : Ne w capability. Set to support CARDBUS pow er management.
bit 22,bit21,bit19 : not used
bit 23 : Fast Back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus
device.
This register can be loaded from external serial EEPROM or use a MXIC preset value of "10D9" and "0532" for vendor
ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's
vendor ID and device ID respectively . If location 3Eh contains"FFFF" value then MXIC's vendor ID and device ID will
be set in this register , otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Detect Parity Error
Signal System Error
Data Parity Report
New Capability
Receive Master Abort
Receive Target Abort
Deceive Select Timing
Fast Back-to-back
System Error Enable
Parity Error Response
Master Operation
Memory Space Access
IO Space Access
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4.1.3 NIC CARDBUS REVISION REGISTER ( CBR V ) ( Offset 0Bh-08h )
bit 3 - 0 : Step Number, range from 0 to Fh.
bit 7 - 4 : Re vision Number, fixed to 7h f or MX98727BEC
bit 15 - 8 : not used
bit 23 - 16 : Subclass, fixed to 0h.
bit 31 - 24 : Base Class, fixed to 2h.
4.1.4 NIC CARDBUS LA TENCY TIMER REGISTER ( CBL T ) (Offset 0Fh-0Ch)
bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.
bit 8 - bit 15 : Configuration Latency Timer, when MX98727BEC assert FRAMEB, it enables its latency timer to count.
If MX98727BEC desser ts FRAMEB prior to timer expiration, then timer is ignored. Otherwise, after timer expires,
MX98727BEC initiates transaction termination as soon as its GNTB is deserted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Class
Step Number
Subclass
Revision Number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Latency Timer
System cache line size
PFLT Register (0Fh-0Ch)
bit 24:Data Parity Report, is set to 1 only if PERRB active and PFCS<6> is also set.
bit 26-25:De vice Select Timing of DEVSELB pin.
bit 27:not used
bit 28:Receiv e Target Abort, is set to indicate a transaction is terminated by a target abort.
bit 29:Receiv e Master Abort, is set to indicate a master transaction with Master abort.
bit 30:Signal System Error, is set to indicate assertion of SERRB.
bit 31:Detected P arity Error , is set whenev er a parity error detected regardless of PFCS<6>.
4.1.5 NIC CARDBUS BASE IO ADDRESS REGISTER ( CBIO ) ( Offset 13h-10h )
bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field.
bit 7 - 1 : not used, all 0 when read
bit 31 - 8 : Defines the address assignment mapping of MX98727BEC CSR registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base IO Address
IO/Memory Spec Indicator
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4.1.6 NIC CARDBUS Base Memory Address Register ( CBMA ) ( Offset 17h-14h )
bit 0 : Memory Space Indicator, fix ed to 0 in this field will map into the memory space. This is a read only field.
bit 7 - 1 : not used, all 0 when read
bit 31 - 7 : Defines the address assignment mapping of MX98727BEC CSR registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base Memory Address
Memory Spec Indicator
4.1.7 NIC CardBus Card Information Structure (CBCIS) ( Offset 2Bh-28h )
CBCIS Register( 28h-2Bh )
bit 31 - bit 28: R OM Image. The 4-bit ROM image field value when the CBCIS resides in an e xpansion R OM.
bit 27 - bit 3: Address Space Offset. The field conatins the address offset which is loaded from EEPR OM within the
address space indicator field (CBCIS<2:0>).
bit 2 - bit 0: Address Space Indicator. The field indicates the location of the CBCIS base address When the value is 7,
the content of CIS is stored in the expansion ROM. Ohterwise, if the value is 2, the CIS content is
stored in the serial ROM.
The register is read only. It is loaded from the serial ROM after a hardware reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Space Offset
Address Space Indicator
ROM Image
4.1.8 NIC CARDBUS SUBSYSTEM ID REGISTER ( CBSID ) ( Offset 2Fh-2Ch )
This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. V alues in
this register are loaded directly from e xternal serial EEPROM after system reset automatically. Word location 00h of
EEPROM is subsystem vendor ID and location 01h is subsystem device ID.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subsystem device ID (31:16)
Subsystem Vendor ID (bit 15:0)
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4.1.9 NIC CARDBUS BASE EXP ANSION ROM ADDRESS REGISTER ( CBROM ) ( Offset 33h-30h )
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 16 - 1 : not use
bit 31 - 17 : Defines the upper 21 bits of expansion ROM base address.
4.1.11 NIC CARDBUS INTERRUPT REGISTER ( CBIT ) ( Offset 3Fh-3Ch )
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector.
bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to CARDBUS bus.
bit 23 - 16 : Min_Gnt which is the maximum period that MX98727BEC needs to finish a burst CARDBUS cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Pin
Max_Lat
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0
Interrupt Line
4.1.10 NIC CARDBUS CAPABILITY POINTER REGISTER ( CBCP ) ( Offset 37h-34h )
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h.
bit 31- 8 : reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capability Pointer (Set to 44h)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4.1.12 NIC CARDBUS DRIVER AREA REGISTER ( CBD A ) ( 43h-40h )
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
4.1.13 NIC CARDBUS PO WER MANAGEMENT CAP ABILITY REGISTER ( CPMC ) ( 47h-44h )
bit 31- 27 : PME_Support, read only indicates the pow er states in which the function ma y assert LANWAKE pin.
bit 31 ---- PME_D3cold (value depending on Vaux / FCSB pin )
bit 30 ---- PME_D3hot
bit 29 ---- PME_D2
bit 28 ---- PME_D1
bit 27 ---- PME_D0
bit 26 : D2 mode support, read only, set to 1.
bit 25 : D1 mode support, read only, set to 1.
bit 24-22 : AUX_I bits . Auxiliary current field, set to 000.
bit 21 : DSI, read only, reset to 0.
bit 20 : A uxiliary power source, supporting D3cold, set to 1. This bit is valid only when bit 31 is a '1'.
bit 19 : PME Clock, read only, reset to 0.
bit 18-16 : CARDBUS power management version1.1, set to 010, read only.
bit 15-8 : Ne xt Pointer , all bits reset to 0.
bit 7-0 : Capability ID, read only, set to 1 indicates support of power management
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D2_Support
D1_Support
PME_Support
0 0 0 0 0 0 0 0
AUX_I
DSI
Auxiliary Power Source
PME Clock
Version
Next Pointer
Capability ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Board Type
Driver Special Use
13
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
4.1.14 NIC CARDBUS PO WER MANAGEMENT COMMAND AND ST ATUS REGISTER ( PMCSR ) ( 4Bh-48h )
bit 1-0 : Power_State, read/write, D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11.
bit7-2 : all 0. Reserved.
bit8 : PME_EN, set 1 to enable PMEB and LANWAKE pins. Set 0 to disab le PMEB and LANWAKE assertion.
bit 12-9 : Data_Select f or report in the Data register located at bit 31:24. Not supported, reset to 0.
bit 14-13 : Data_Scale , read only, not supported, reset to 0.
bit 15 : PME_Status independent of the state of PME_EN. Cleared during power up.
When set, indicates a PME event.
Write 1 to clear the PMEB and LANW AKE assertion, PME-Status become 0. Write 0, no effect.
bit 21-16 : Reserved.
bit 22 : B2_B3# = 0, BPCC_EN = 1, read only, not support.
bit 23 : BPCC_EN = 0, Bus P o wer/Cloc k Control Enab le, read only, not support.
bit 31-24 : Data = 0, read only, not support.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bridge Extension Support
PME_Status
Data
Data_Scale
Data_Select
PME_EN
Reserved
Power State
0 0 0 0 0 00 0 0 0 0 0 0 0
14
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.1 Modem Function Configuration Registers (Function 1)
5.1.1 Modem CardBus ID Register(CBID)
CBID Register ( 0103h-0100h)
bit 31-16 :Device ID . Provide the unique ID number .
bit 15-0 :Vendor ID. Specifies the manuf acture of the MX98727BEC.
These two IDs must be loaded from external serial ROM. No default values are implemented in MX98727BEC.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
5.1.2 Modem CardBus Command and Status Register (CBCS)
CBCS Register ( 0107h-0104h)
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 to enable IO access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device Select Timing
IO Space Access
Memory Space Access
Detected Parity Error
Signal System Error
Data Parity Report
Fast Back-to-back
System Error Enable
Parity Error Response
Master Operation
bit 1: Memory Space Access, set to 1 to enable memory access
bit 2: Master Oper ation, Tied to 0 and no master capability is pro vided in modem function.
bit 3- bit 5 :not used
bit 6: P arity Error Response, set to 1 to enable assertion of MX98727BEC's CSR5<13> bit if parity error detected.
bit 7 : not used
bit 8: System Error Enable, set to 1 to enable MX98727BEC to assert SERRB when parity error is detected on
address lines and CBEB[3:0] .
bit 22 - bit 9: not used
bit 23 : F ast Bac k-to-back, alwa ys set by MX98727BEC to accept f ast back-to-bac k transactions that are not sent to
the same bus device.
bit 24 : Data Parity Report, is set to 1 by MX98727BEC only if MX98727BEC is bus master, it sends or causes
PERRB active and CBCS<6> is also set.
bit 26 -25 : De vice Select Timing, fixed at 01 which indicates a medium assertion of DEVSELB.
bit 27- 29 : not used.
bit 30 : Signal System Error, is set to indicate MX98727BEC asserted SERRB .
bit 31 : Detected P arity Error, is set whene ver a parity error detected regardless of CBCS<6>.
15
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.1.3 Modem CardBus Revision Register (CBRV)
CBRV Register ( 010Bh-0108h)
bit 7 - bit 0 : Revision Number, Fix to 0/h.
bit 15 - bit 8 : not used
bit 23 - bit 16 : Subclass, auto loaded from serial ROM.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Class
Subclass
Revision Number
bit 31 - bit 24 : Base Class, fixed to 07/h.
5.1.4 Modem CardBus Latency Timer Register(CBLT)
CBL T Register ( 010Fh-010Ch)
bit 0 - bit 7 : System cache line size Not accessable in modem function.
bit 8 - bit 15 : Configuration Latency Timer , Not accessible in modem function.
<Note> Cache line size and latency timer are only useful in master , so modem function doesn't allow to access these
two fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Latency Timer
System cache line size
16
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.1.5 Modem CardBus I/O Address Register(CBIO)
CBIO Register ( 0113h-0110h)
bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field.
bit 4 - 1 : not used, all 0 when read
bit 31- 5 : Defines the base address mapping to modem registers.
5.1.6 Modem CardBus Memory Address Register(CBMEM)
CBMEM Register ( 0117h-0114h)
bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field
bit 6 - bit 1 : not used, all 0 when read
bit 31 - bit 10 : Define the base address mapping to modem registers, and status changed registers.
5.1.7 Modem CardBus Card Information Structure(CBCIS)
CBCIS Register( 012Bh-0128h )
It is read only and is loaded from serial ROM after a hardware reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Space Offset
Address Space Indicator
ROM Image
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base IO Address
IO/Memory Space Indicator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base IO Address
Memory Space Indicator
000 0
17
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.1.8 Modem CardBus Subsystem ID Register(CBSID)
CBSID Register ( 012Fh-012Ch)
bit 15-0 :Subsystem ID. The value of this field is read from the serial ROM.
bit 31-16 Subsystem Vendor ID . The v alue of this field is read from the serial ROM.
5.1.9. Modem CardBus Base Expansion ROM Address Register(CBROM)
CBROM Register ( 0133h- 0130h)
bit 0 : Address Decode Enable, It is tied to 0, indicating expansion R OM is not supported in modem function.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subsystem ID
Subsystem V endor ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Decode Enable
5.1.10 Modem CardBus Interrupt Register(CBIT)
CBIT Register ( 013Fh - 013Ch)
bit 7 - bit 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this informa-
tion to determine priority and interrupt vector .
bit 15 - bit 8 : Interrupt Pin, fixed to 01h which use INTAB.
bit 23 - bit 16 : Min_Gnt which is the maximum period that MX98727BEC needs to finish a b urst CardBus cycle. The
value is 08h.
bit 31 - bit 24 : Max_Lat which is a maximum of every 17us for a access to PCI b us. The v alue is 38h.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Line
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0
Max_Lat
Interrupt Pin
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2 HOST INTERF A CE REGISTERS
MX98727BEC CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32
bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register Meaning Offset from CSR Base
Address ( CBIO and CBMA )
CSR0 Bus mode 0 0
CSR1 Transmit poll demand 08h
CSR2 Receive poll demand 10h
CSR3 Receive list base address 1 8 h
CSR4 Transmit list base address 2 0 h
CSR5 Interrupt status 2 8h
CSR6 Operation mode 30h
CSR7 Interrupt enable 38h
CSR8 Missed frame counter 40h
CSR9 Serial ROM and MII management 48h
CSR10 Flash Memory Address Register 50h
CSR11 General Purpose timer 58h
CSR12 10 Base-T status port 6 0h
CSR13 SIA Reset Register 6 8 h
CSR14 10 Base-T control port 7 0 h
CSR15 Watchdog timer 7 8h
CSR16 ( Reserved ) Test Operation port 8 0h
CSR17 ( Reserved ) IC Test Port-1 8 8 h
CSR18 ( Reserved ) IC Test P ort-2 9 0 h
CSR19 ( Reserved ) IC test P ort-3 9 8 h
CSR20 Auto compensation A0h
CSR21 Flow control Register A4h
CSR22 MAC ID Byte 3-0 A8 h
CSR23 Magic ID 5, 4 / MAC ID Byte 5, 4 ACh
CSR24 Magic ID Byte 3-0 B0 h
CSR25 Filter 0 Byte Mask B4h
CSR26 Filter 1 Byte Mask B8h
CSR27 Filter 2 Byte Mask BCh
CSR28 Filter 3 Byte mask C0h
CRS29 Filter Offset C4h
CSR30 Filter 1&0 CRC-16 C8h
CSR31 Filter 3&2 CRC-16 CCh
19
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
CSR32 Reserved A Register 1 D 0h
CSR33 Reserved A Register 2 D 4h
CSR34 Reserved A Register 3 D 8h
CSR35 Reserved A Register 4 D C h
CSR36 Reserved A Register 5 E0 h
CSR37 Reserved P Register E4h
CSR38 Power Management Register E8h
CSR39 VLAN T ag Register ECh
CSR40 Function Event Register F0h
CSR41 Function Event Mask Register F 4 h
CSR42 Function Present State Register F8h
CSR43 Function Force Event Register FCh
20
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.1 BUS MODE REGISTER ( CSR0 )
Field Name Description
0 SWR Software Reset, when set, MX98727BEC resets all internal hardware with the exception of
the configuration area and port selection.
1 BAR0 Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected b y programming this bit. Set
for lower threshold, reset for normal threshold.
6:2 D SL Descriptor Skip Length, specifies the number of longwords to skip between two descrip-
tors.
7 BLE Big/Little Ending, set for big ending byte ordering mode, reset for little ending byte ordering
mode, this option only applies to data buffers
13:8 PBL Programmable Burst Length, specifies the maximum number of longwords to be trans-
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
15:14 CAL Cache Alignment, programmable address boundaries of data burst stop, MX98727BEC
can handle non-cache- aligned fragment as well as cache-aligned fragment efficiently.
16 BAR2 Reset to use RX dominate arbitration. Set to use TX dominant arbitration in fast forward
mode or round Robin in store/forward mode. Must be reset to zero for normal operation.
18:17 TAP Transmit Auto-P olling time interval, defines the time interval f or MX98727BEC to performs
transmit poll command automatically at transmit suspended state.
2 1 R ME CARDBUS Memory Read Multiple command enable, indicates bus master may intend to
fetch more than one cache lines disconnecting.
2 3 RLE CARDBUS Memory Read Line command enable, indicating bus master intends to fetch a
complete cache line.
2 4 WIE CARDBUS Memory Write and Invalidate command enable, guarantees a minimum transf er
of one complete cache.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAP-Transmit Automatic Polling
WIE-Write and Invalidate Enable
RLE-Read Line Enable
RME-Read Multiple Enable
BAR2
DSL-Descriptor Skip Length
SWR-Software Reset
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
BAR0-Bus Arbitration bit 0
21
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.2 TRANSMIT POLL COMMAND ( CSR1 )
Field Name Description
31:0 TPC Write only , when written with any value, MX98727BEC read transmit descriptor list in host
memory pointed by CSR4 and processes the list.
5.2.3 RECEIVE POLL COMMAND ( CSR2 )
Field Name Description
31:0 RPC Write only, when written with any v alue, MX98727BEC read receiv e descriptor list in host
memory pointed by CSR3 and processes the list.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit Poll command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive Poll command
TABLE 5.2.0 TRANSMIT AUTO POLLING BITS
CSR<18:17> Time Interval
0 0 No transmit auto-polling, a write to CSR1 is required to poll
0 1 auto-poll every 200 us
1 0 auto-poll every 800 us
1 1 auto-poll every 1.6 ms
22
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.4 DESCRIPT OR LIST ADDRESS ( CSR3, CSR4 )
CSR3 Receive List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Receive List Address
CSR4 Transmit List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Transmit List Address
23
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.5 INTERRUPT STATUS REGISTER ( CSR5 )
Field Name Description
2 8 WKUPI W ake Up event interrupt. Set if wake-up ev ent occurs in power-down mode.
27 LC 100 Base-TX link status has changed either from pass to fail or fail to pass.
Read CSR12<1> for 100 Base-TX link status.
25:23 EB Error Bits, read only, indicating the type of error that caused fatal b us error .
22:20 TS Transmit Process State, read only bits indicating the state of transmit process.
19:17 RS Receive Process State, read only bits indicating the state of receive process.
1 6 NIS Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and
CSR5<14>, CSR5<28>.
1 5 AIS Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<4>,
CSR5<5>,CSR5<7>, CSR5<8>, CSR5<9>, CAR5<10>, CSR5<11>, CSR5<12> and
CSR5<13>, CSR5<27>.
14 ERI Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes
has been received in chain mode.
1 3 FBE F atal Bus Error , indicating a system error occurred, MX98727BEC will disable all b us
access.
12 L F Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when
CSR6<18>=0, CSR14<8>=1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RS-Receive Process State
NIS-Normal Interrupt Summary
LF-Link Fail
ETI-Early Transmit Interrupt
AIS-Abnormal Interrupt Summary
ERI-Early Receive Interrupt
FBE-Fatal Bus Error
GTE-General Purpose Timer Expired
WKUPI-Wake Up event Interrupt
LC-Link Change
RPS-Receive Process Stopped
RI-Receive Interrupt
EB-Error Bits
TS-Transmit Process State
RWT-Receiv e W atchdog Timeout
RU-Receive Buffer Unavailable
LPANCI-Link Pass/Autonegotiation
Completed Interrupt
UNF-Transmit Underflow
TJT-Transmit Jabber Timeout
TU-Transmit Buffer Unavailable
TPS-Transmit Process Stopped
TI-Transmit Interrupt
24
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
1 1 GTE General Purpose Timer Expired, indicating CSR11 counter has expired.
10 ETI Early Transmit Interrupt, indicating the pack et to be transmitted was fully transf erred to
internal TX FIFO. CSR5<0> will automatically clears this bit.
9 R WT Receive W atchdog Time-out, reflects the network line status where receive watchdog
timer has expired while the other node is still active on the network.
8 RP S Asserts when the receive process enters the stop state.
7 RU Receive Buffer Unavailable, the receive process is suspended due to the next
descriptor in the receive list is owned by host. If no receive poll command is issued, the
reception process resumes when the next recognized incoming frame is received.
6 RI Receive Interrupt, indicating the completion of a frame reception.
5 U N F Transmit Underflow , indicating transmit FIFO has run empty bef ore the completion of a
packet transmission.
4 LPANCI When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10
Base-T link integrity test has completed successfully, after the link was down. This bit is
also set as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read f or a link status report.
This bit is only v alid when CSR6<18>=0, i.e. 10 Base-T port is selected Link F ail interrupt
( CSR5<12> ) will automatically clears this bit.
3 TJT Transmit Jabber Timeout, indicating the MX98727BEC has been e xcessiv ely active . The
transmit process is aborted and placed in the stopped state. TDES0<14> is also set.
2 TU Transmit Buffer Una v ailable , transmit process is suspended due to the ne xt descriptor in
the transmit list is owned by host.
1 TPS Transmit Process Stopped.
0 TI Transmit Interrupt. indicating a frame transmission was completed.
25
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
T ABLE 5.2.1 F AT AL BUS ERROR BITS
CSR5<25:23> Process State
0 00 parity error for either SERR# or PERR#, cleared by software reset.
001 master abort
010 target abort
011 reserved
1XX reserved
TABLE 5.2.2 TRANSMIT PR OCESS ST ATE
CSR5<22:20> Process State
000 Stopped- reset or transmit jabber expired.
001 Fetching transmit descriptor
0 1 0 W aiting for end of transmission
01 1 filling transmit FIFO
100 reserved
1 0 1 Setup packet
110 Suspended, either FIFO underflow or unavailable transmit descriptor
1 11 closing transmit descriptor
TABLE 5.2.3 RECEIVE PROCESS STATE
CSR5<19:17> Process State
0 00 Stopped- reset or stop receive command. Fetching receive descriptor
0 10 checking for end of receive packet
0 1 1 Waiting f or receiv e pack et
100 Suspended, receive buffer unavailable
101 closing receive descriptor
1 10 Purging the current frame from the receive FIFO due to unavailable receive buffer
1 1 1 queuing the receive frame from the receive FIFO into host receive buffer
26
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.6 OPERATION MODE REGISTER ( CSR6 )
Field Name Description
2 4 SCR Scrambler Mode, default is set to enable scrambler function. Not affected by software
reset.
23 PCS Default is set to enable PCS functions. CSR6<18> must be set in order to operate in
symbol mode.
2 2 TT M Transmit Threshold Mode, set f or 10 Base-T and reset for 100 Base-TX.
21 SF Store and F orward, when set, tr ansmission starts only if a full pac k et is in transmit FIFO.
the threshold values defined in CSR6<15:14> are ignored
19 H B D Heartbeat Disable , set to disable SQE function in 10 Base-T mode .
18 PS P ort Select, default is 0 which is 10 Base-T mode , set for 100 Base-TX mode.
A software reset does not affect this bit.
1 7 C OE Collision Offset Enable, set to enable a modified backoff algorithm during low collision
situation, reset for normal backoff algorithm.
15:14 TR Threshold Control Bits, these bits controls the selected threshold level for MX98727BEC's
transmit FIFO, transmission starts when frame siz e within the transmit FIFO is larger
than the selected threshold. Full frames with a length less than the threshold are also
transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COE-Collision Offset Enable
FC-Force collision mode
LOM-Loopback Operation Mode
TR-Threshold Control Bits
ST-Start/Stop Transmission Command
TTM-Transmit Threshold Mode
SF-Store and Forward
PR-Promiscuous Mode
HBD-Hearbeat Disable
PS-Port Select
FD-Full Duplex Mode
PM-Pass All Multicast
SB-Start/Stop Backoff Counter
IF-Inverse Filtering
PB-Pass Bad Frame
HO-Hash-Only Filtering Mode
SR-Start/Stop Receive
HP-Hash/Perfect Receive Filtering Mode
PCS-PCS function
SCR-Scrambler Mode
FKD
27
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
1 3 ST Start/Stop Transmission Command, set to place tr ansmission process in running state
and will try to transmit current descriptor in transmit list. When reset, transmit process is
placed in stop state.
12 F C Force Collision Mode, used in collision logic test in internal loopback mode, set to force
collision during next tr ansmission attempt. This can result in e xcessiv e collision reported
in TDES0<8> if 16 or more collision.
11:10 LOM Loopback Operation Mode, see table 5.2.6.
9 F D Full-Duple x Mode , set for simultaneous tr ansmit and receive operation, heart beat check
is disabled, TDES0<7> should be ignored, and internal loopback is not allo wed. This bit
controls the value of bit 6 of link code word .
8 F KD Reserved for internal test for back off speeding up
7 PM Pass All Multicast, set to accept all incoming fr ames with a multicast destination address
are received. Incoming frames with physical address are filtered according to the CSR6<0>
bit.
6 P R Promiscuous Mode, any incoming valid frames are accepted, default is reset and not
affected by software reset.
5 SB Start/Stop Back off Counter, when reset, the back off timer is not affected by the netw ork
carrier activity. Otherwise , timer will start counting when carrier drops.
4 IF Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during
perfect filtering mode.
3 PB P ass Bad Frames , set to pass bad frame mode, all incoming frames passed the address
filtering are accepted including runt frames, collided fragments, truncated frames caused
b y FIFO o verflow.
2 H O Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both
physical and multicast addresses.
1 S R Start/Stop Receiv e, set to place receiv e process in running state where descriptor
acquisition is attempted from current position in the receive list. Reset to place the
receive process in stop state.
0 HP Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames. If CSR6<2> is also set, then the physical addresses are
imperf ect address filtered too . If CSR6<2> is reset, then physical addresses are perf ect
address filtered, according to a single physical address as specified in setup frame.
28
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
T ABLE 5.2.4 TRANSMIT THRESHOLD
CSR6<21> CSR6<15:14> CSR6<22>=0 CSR6<22>=1 (Threshold bytes)
(for 100 Base-TX) (for 10 Base-T)
0 00 128 72
0 01 256 96
0 10 512 128
0 11 1024 160
1 XX ( Store and Forward )
T ABLE 5.2.5 D A T A PORT SELECTION
CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> Port
1 0 X X X Nway Auto-negotiation
0 0 1 X X 10 Base-T
0 1 0 1 1 100 Base-TX
T ABLE 5.2.6 LOOPBACK OPERA TION MODE
CSR6<11:10> Operation Mode
00 Normal
0 1 Internal loopback at FIFO port
11 Internal loopback at the PHY level
10 External loopback at the PMD level
T ABLE 5.2.7 FILTERING MODE
CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode
PM PR IF HO HP
0 0 0 0 0 CAM 16-entry perfect filtering
0 0 0 0 1 64-bit hash (mulitcast=1) + 1perfect (entry 0)
filtering. (multicast=0)
0 0 0 1 1 64-bit hash for multicast
0 0 1 X 0 Inverse filtering. Only valid with CSR6<0>=0
X 1 X X X Promiscuous (P ass all kind)
1 0 X X X Pass All Multicast
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.7 INTERRUPT MASK REGISTER ( CSR7 )
Field Name Description
2 8 WKUPIE Wake Up Event Interrupt Enable, enables CSR5<28>.
2 7 LCE Link Changed Enable, enables CSR5<27>.
1 6 NIE Normal Interrupt Summary Enable, set to enable CSR5<0>, CSR5<2>, CSR5<6>,
CSR5<14>, CSR5<28>
1 5 AIE Abnormal Interrupt Summary enable, set to enable CSR5<1>, CSR5<3>,
CSR5<4>, CSR5<5>, CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11>, CSR5<12> CSR5<13>,
AND CSR5<27>
1 4 ERIE Early Receive Interrupt Enable
1 3 FBE F atal Bus Error Enable, set together with with CSR7<15> enab les CSR5<13>.
1 2 LFE Link F ail Interrupt Enable, enables CSR5<12>
1 1 GPTE General Purpose Timer Enable, set together with CSR7<15> enables CSR5<11>.
1 0 ETIE Early T ransmit Interrupt Enable, enables CSR5<10>
9 RWE Receive Watchdog Timeout Enable, set together with CSR7<15> enables CSR5<9>.
8 RSE Receive Stopped Enable, set together with CSR7<15> enables CSR5<8>.
7 R U E Receive Buffer Unavailable Enable, set together with CSR7<15> enables CSR5<7>.
6 RIE Receive Interrupt Enable, set together with CSR7<16> enables CSR5<6>.
5 UNE Underflow Interrupt Enable, set together with CSR7<15> enables CSR5<5>.
4 LPANCIE Link Pass/Autonegotiation Completed Interrupt Enable
3 TJE Transmit Jabber Timeout Enable, set together with CSR7<15> enables CSR5<3>.
2 TU E Transmit Buffer Unavailab le Enable, set together with CSR7<16> enables CSR5<2>.
1 TSE Transmit Stop Enab le, set together with CSR7<15> enables CSR5<1>.
0 TIE Transmit Interrupt Enable, set together with CSR7<16> enables CSR5<0>.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIE-Normal interrupt Summary Enable
FBE-Fatal Bus Error Enable
LFE-Link Fail Enable
AIE-Abnormal Interrupt Summary Enable
ERIE-Early Receive Interrupt Enable
ETIE-Early Transmit Interrupt Enable
RIE-Receive Interrupt Enable
RWE-Receiv e W atchdog Enable
RSE-Receive Stopped Enable
GPTE-General-Purpose Timer Enable
RUE-Receive Buffer Unavailable Enable
UNE-Underflow Interrupt Enable
LPANCIE-Link Pass
/Nway Complete Interrupt Enable
TJE-Transmit Jabber Timeout Enable
TUE-Transmit Buffer Unavailable Enable
TSE-Transmit Stopped Enable
TIE-Transmit Interrupt Enable
LCE-Link Changed Enable
WKUPIE-Wake Up event interrupt Enable
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.8 MISSED FRAME COUNTER ( CSR8 )
Field Name Description
1 6 M FO Missed F rame Ov erflow , set when missed frame counter o verflo ws, reset when CSR8
is read.
15:0 MFC Missed F rame Counter , indicates the number of frames discarded because no host
receive descriptors were available.
5.2.9 NONV OLA TILE MEMORY CONTROL REGISTER ( CSR9 )
Field Name Description
31 LED3SEL 0:Default v alue. Set LED3 as RX LED.
1:Set LED3 as F/H duple x LED.
30 LED2SEL 0: Default v alue. Set LED2 as SPEED LED.
1: Set LED2 as 100 Good LinkLED
29 LED1SEL 0:Default v alue. Set LED1 as Good Link LED .
1: Set LED1 as Link/Activity LED.
28 LED0SEL 0:Default value. Set LED0 as Activity LED.
1: Set LED0 as Link Speed (10/100) LED .
24 LED4SEL 0: Default value. Set LED4 as PMEB LED.
1: Set LED4 as 10 Good Link LED.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Missed Frame Overflow
Missed Frame Counter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR-Boot ROM Select
Data-Boot ROM data
or Serial ROM control
LED1SEL
LED4SEL
LED2SEL
LED3SEL
LED0SEL
WKFCAT
RD-Read Operation
Reload
SR-Serial ROM Select
31
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
26:25 WKF ACT Wake up frame catenation option bits.
CRS21<4> CSR<26> CSR<25> W ake up event
0 X X CH0+CH1+CH2+CH3
1 0 0 (CH0*CH1)+(CH2*CH3)
1 0 1 (CH0*CH1)+CH2+CH3
1 1 0 (CH0*CH1*CH2)+CH3
1 1 1 CH0*CH1*CH2*CH3
1 4 R D Boot ROM/EEPROM read operation select bit
1 3 W R EEPROM reload operation select bit.
Operation definition:
RD WR Operation
1 0 Boot ROM/EEPROM Read
0 1 Boot ROM/EEPROM write
1 1 EEPROM reload operation ( bit 11, SR=1)
12 BR Boot ROM Select, set to select boot ROM only if CSR9<11>=0.
1 1 SR Serial ROM Select, set to select serial ROM for either read or write operation.
7:0 Data If boot ROM is selected ( CSR9<12> is set ), this field contains the data to be read from
and written to the boot ROM. If serial ROM is selected , CSR9<3:0> are defined as
follows :
3 SD O Serial ROM data out from serial ROM into MX98727BEC.
2 SDI Serial ROM data input to serial ROM from MX98727BEC.
1 SCLK Serial clock output to serial ROM.
0 SCS Chip select output to serial ROM.
Notice : CSR9<11> and CSR9<12> should be mutually exclusive for correct operations.
01
LED0SEL ACT SPEED
LED1SEL LINK LINK/ACT
LED2SEL SPEED 100 LINK
LED3SEL RX FULL/HALF
LED4SEL* PMEB 10 LINK
LED DISPLAY Option Summary Table
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
1 6 C ON When set, the general purpose timer is in continuous operating mode. When reset, the
timer is in one-shot mode.
15:0 Timer Value contains the timer value in a cycle time of 204.8us.
GENERAL PURPOSE TIMER ( CSR11 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CON-Continuous Mode
Timer V alue
5.2.10 FLASH MEMOR Y PROGRAMMING ADDRESS REGISTER ( CSR10 )
Field Name Description
16:0 MA Flash Memory Address : Address bit 16 to 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.11 10 BASE-T ST ATUS Port ( CSR12 )
Field Name Description
31:16 LPC Link P artner's Link Code W ord, where bit 16 is S0 ( selector field bit 0 ) and bit31 is NP
( Ne xt P age ). Effectiv e only when CSR12<15> is read as a logical 1.
1 5 LP N Link Partner Negotiable, set when link partner support NWA Y algorithm and CSR14<7>
is set.
14:12 ANS Autonegotiation Arbitration State, arbitration states are defined
000 = Autonegotiation disable
001 = Transmit disable
010 = ability detect
011 = Acknowledge detect
100 = Complete acknowledge detect
101 = FLP link good; autonegotiation complete
110 = Link check
When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write
001 into this field can restart the autonegotiation sequence if CSR14<7> is set.
Otherwise, these bits should be 0.
1 1 TRF Transmit Remote Fault
3 APS A utopolarity State , set when polarity is positive . When reset, the 10 Base-T polarity is
negative . The receiv ed bit stream is in v erted by the receiv er .
2 LS10B Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in
pass state.
1 LS100B Link state of 100 Base-TX, this bit reflects the state of SD pin, effective only when
CSR6<23>= 1 ( PCS is set ). Set to indicate a fail condition .i.e. SD=0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPC-Link Partner's Link Code Word
LPN-Link Partner Negotiable
ANS-Autonegotiation Arbitration State
TRF-Transmit Remote Fault
APS-Autopolarity State
LS10B-Link Status of 10 Base-T
LS100B-Link Status of 100 Base-TX
*Software reset has no effect on this register
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.12 VLAN & HomeLAN Register (CSR13)
Field Name Description
11 HPNA2EN Home PNA 2.0 MII Interface Enable, default=0
10 Htxr ise Reset to send signal in rising edge, set to send signal in falling edge, default=0.
9 Hlinkb Home PNA Link status, low is good link, high is bad link, default=0.
8 HPNA1EN Home PNA 1.0 7-wire interface Enable, default=0.
7 VLANEN Set to enable VLAN function, reset to disab le VLAN function, def ault=0.
6 VLAN TX S/H While VLANEN=1, reset this bit f or software VLAN TX function,
set this bit for hardw are VLAN TX function, def ault=0.
5 VLAN RX S/H While VLANEN=1, reset this bit f or software VLAN RX function,
set this bit f or hardware VLAN RX function, default=0.
0 Nway Reset While writing 0 to this bit, resets the CSR12 & CSR14, default=0.
5.2.13 10 Base-T Control PORT (CSR14)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T4-100 Base-T4 (link code word)
PAUSE-Pause (link code word)
TXF-100 Base-TX full duplex
(link code word)
TXH-100 Base-TX half duplex
(link code word)
LTE-Link Test Enable
RSO-Receive Squelch Enable
ANE-Autonegotiation Enable
HDE-Half Duplex Enable)
LBK-Loopback (MCC)
*The software reset bit (bit0 of CSR0) has no effect to this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nway Reset-
Nway and 10 Base-T PHY level reset
HPNA2EN
Htxrise
Hlinkb
HPNA1EN
VLANEN
VLAN TX S/H
VLAN RX S/H
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
19 PA U SE Bit 10 of link code word for 100 Base-TX pause mode.
18 T 4 Bit 9 of link code word f or T4 mode. (allwa ys 0 after reset)
17 TXF Bit 8 of link code word for 100 Base-TX full duplex mode.
16 TXH Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7>
( ANE ) is set.
12 LTE Link Test Enable, when set the 10 Base-T port link test function is enabled.
8 R S Q Receive Squelch Enab le for 10 Base-T port. Set to enable .
7 ANE Autonegotiation Enable, .
6 HDE Half-Duplex Enable, this is the bit 5 of link code word, only meaningful when CSR14<7> is
set.
1 LBK Loop back enable for 10 Base-T MCC.
5.2.14 W A TCHDOG TIMER ( CSR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBZ-Must Be Zero
RWR-Receiv e W atchdog Release
PWD-Receive W atchdog Disable
JCK-Jabber Clock
HUJ-Host Unjabber
JAB-Jabber Disable
Field Name Description
8 FJT Internal test for jab ber timer . Must be zero . Def ault = 0
5 R W R Defines the time interval no carrier from receive watchdog expiration until re-enabling the
receive channel. When set, the receiv e watchdog is release 40-48 bit times from the last
carrier desertion. When reset, the receive watchdog is released 16 to 24 bit times from
the last carrier desertion.
4 R W D When set, the receiv e watchdog counter is disable. When reset, receive carriers longer
than 2560 bytes are guaranteed to cause the watchdog counter to time out. Packets shorter
than 2048 bytes are guaranteed to pass.
2 JCK When set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted,
When reset, transmission f or the 10 Base-T port is cut off after a range of 26 ms to 33ms.
When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to
3.3ms.
1 HU J Defines the time interval between transmit jabber expiration until reenabling of the
transmit channel. When set, the transmit channel is released immediately after the jabber
e xpiration. When reset, the jabber is released 365ms to 420 ms after jabber expiration for
10 Base-T port. When reset, the jabber is released 36.5ms to 42ms after the jabber e xplo
ration f or 100 Base-TX port.
0 JBD Jabber Disable, set to disable transmit jabber function.
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.15 NW AY Status Internal test Register (CSR20)
Field Name Description
3 1 PA US E Flow Control PA USE mode is accepted, read only.
30 100TXF 100 base-T full duple x mode selection indication : After NW AY autonegotiation , a 1
in this bit indicate the IC has settled down in this mode. Otherwise 0.
29 100TXH 100 base-T half duple x mode selection indication : After NW AY autonegotiation , a 1
in this bit indicate the IC has settled down in this mode. Otherwise 0.
2 8 10TXF 10 base-T full duple x mode selection indication : After NW AY autonegotiation , a 1
in this bit indicate the IC has settled down in this mode. Otherwise 0.
2 7 10TXH 10 base-T half duple x mode selection indication : After NW AY autonegotiation , a 1
in this bit indicate the IC has settled down in this mode. Otherwise 0.
26 100GLT 100 TX NWAY good link test speed option, set for fast, reset f or normal.
25 LOCKT Descrambler lock speed test, set for fast, reset for normal
24 SYNM1INT Sync. modem function 1 Interrupt
19 RESERVED Fixed to 1 by chip
1 7 RXSIZE1 Must be 0 for normal operation
16 RESERVED Default is 0.
15 BAR1 RX FIFO arbitration option control bit 1, together with CSR0<1> BAR0 define a internal
RX almost full threshold, definition as followed
BAR0 BAR1 RX Near full threshold
0 0 1K bytes
0 1 256
1 0 512
1 1 128
Device driver can determine these values to reduce over-flow error rate, option 00 is least
likely to ha ve o verflow b ut would reduce TX perf ormance, while option 11 is near
round-robin type of arbitration
1 4 TXSIZE1 Must be zero for normal operation
1 3 TXSIZE0 Must be zero for normal operation
1 1 RXSIZE0 Must be zero for normal operation
10 SELIDLE Set for 200-250 ns idle pulse width detection, reset for 175-225 ns idle pulse detection
Default is 0.
8:0 RBCNT RX DMA Byte Count f or driver's early interrupt assertion control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAUSE
100TXF
100TXH
10TXF
10TXH
100GLT
LOCKT
RESERVED
RESERVED
SYCM1INT
RXSIZE1
BAR1
TXSIZE1
TXSIZE0
RXSIZE0
SELIDLE
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.16 Flow Control Register (CSR21)
Field Name Description
31:16 TMVAL Timer value in the flow control frame for receive flow control.
15 TEST Test the flow control timer .
14 RESTART Set the receive flow control into the restart mode, the RXFCEN should be asserted. The
default value is 0.
13 RESTOP Set the receive flow control into the restop mode, the RXFCEN should be asserted. The
default value is 0.
12 TXFCEN Transmit flow control enab le . The default value is 1.
11 RXFCEN Receive flow control enab le . The default v alue is 0.
10 RUFCEN Send flow control frame control when the receive descriptor is unavailable, the RXFCEN
should be asserted. The def ault v alue is 0.
9 STOPTX Indicate the transmit status. If the receive flow control stop the transmission, this bit is
set. After recovering transmission, this bit is clear.
8 REJECTFC Abort the receive flow control fr ame when set. The def ault v alue is 1.
7 RXFCTH1 Receive flow control threshold 1. Default = 0
6 RXFCTH0 Receive flow control threshold 0. Default = 1
5 NFCEN Accept flow control from the auto-negotiation result. Default = 1
4 WKFCATEN Enable the wake up frame concatenation feature. loadable from EEPROM offset 77h bit
3, See CSR9 for details
3 LNKCHGDIS Set to disable link change detection in power down mode, loadable from EEPROM
offset 77h bit 1
2 MPHITDIS Set to disable magic packet address matching, loadable from EEPROM offset 77h bit 0
1 FSTEE Set to speed up EEPROM clk for test, reset for normal EEPROM clock.
Receive Flow Contr ol Threshold T able
FCTH1 1100
FCTH0 1010
Threshold V alue (Byte) 5 1 2 2 5 6 1 2 8 overflow
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMVAL-Flow Control timer Value
TEST-Test Flow Counter Timer
RESTART-Set Reset Mode
RESTOP-Set Restop Mode
TXFCEN-Transmit Flow Control Enable
RXFCEN-Receive Flow Control
STOPTX-Indicate the transmit is stoped
REJECTFC-Abort the Receive Flow Control Frame
FCTH1-Flow Control Thresold 1
FCTH0-Flow Control Thresold 0
RUFCEN-Receive Flow Control Enable
while Receive Descriptor is Unavailable
NFCEN-NWAY Flow Control
FSTEE
WKFCATEN-Wake up Frame Catenation Enable
LNKCHGDIS - Link change indication disable
MPHITDIS - magic packet hit disable
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.17 MAC ID Byte 3-0 Register (CSR22)
5.2.18 Magic ID Byte 5,4/ MA C ID Byte 5,4 (CSR23)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAC ID byte 3
MAC ID byte 2
MAC ID byte 0
MAC ID byte 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Magic ID byte 5
Magic ID byte 4
MAC ID byte 4
MAC ID byte 5
5.2.19 Magic ID Byte 3-0 (CSR24)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Magic ID byte 3
Magic ID byte 2
Magic ID byte 0
Magic ID byte 1
5.2.20 Filter 0 Byte Mask Register 0 (CSR25)
Filter 1 Byte Mask Register 1 (CSR26)
Filter 2 Byte Mask Register 2 (CSR27)
Filter 3 Byte Mask Register 3 (CSR28)
CSR25 to CSR28 are Filter N ( N=0 to 3 ) Byte Mask Register N ( N=0 to 3 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte Mask
Field Name Description
31:0 Byte Mask If bit number j of the byte mask is set, byte number (offset+j) of the incoming frame is
checked.
39
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.21 Filter Offset Register (CSR29)
Field Name Description
6:0 Pattern 0 Offset The offset defines the location of first byte that should be checked by filter 0 in the
frame. Offset is always greater than 12.
7 Filter 0 Enable This bit is set to enable the filter 0. If it is reset, filter 0 is disabled for the wake-up
frame checking.
14:8 Pattern 1 Offset The offset defines the location of first byte that should be checked by filter 1 in the
frame. Offset is always greater than 12.
1 5 Filter 1 Enable This bit is set to enable the filter 1. If it is reset, filter 1 is disabled for the wake-up
frame checking.
22:16 Pattern 2 Offset The offset defines the location of first byte that should be checked by Filter 2 in
the frame. Offset is always greater than 12.
2 3 Filter 2 Enable This bit is set to enable the filter 2. If it is reset, filter 2 is disabled for the wake-up
frame checking.
30:24 Pattern 3 Offset The offset defines the location of first byte that should be checked by Filter 3 in
the frame. Offset is always greater than 12.
3 1 Filter 3 Enable This bit is set to enable the filter 3. If it is reset, filter 3 is disabled for the wake-up
frame checking.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 3 Offset
Filter 3 Enable
Filter 2 Enable
Filter 2 Offset
Filter 1 Enable
Filter 1 Offset
Filter 0 Enable
Filter 0 Offset
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
15:0 Filter 0 CRC-16 The 16-bit CRC value is programmed by the driver to be matched against the
current result from the CRC-16's remainder at the location specified by Filter 0
offset and Filter 0 Byte Mask register . if matched, the incoming frame is a wakeup
frame.
31:0 Filter 1 CRC-16 Same description as Filter 0 CRC-16.
5.2.22 Filter 1 and 0 CRC-16 Register (CSR30)
5.2.23 Filter 3 and 2 CRC-16 Register (CSR31)
Field Name Description
15:0 Filter 2 CRC-16 Same description as Filter 0 CRC-16.
31:0 Filter 3 CRC-16 Same description as Filter 0 CRC-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 1 CRC-16
Filter 0 CRC-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter 3 CRC-16
Filter 2 CRC-16
41
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.25 PMDCTRL2 Register (CSR33)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 1 0
PMDUG40[1:0]M
PMDUG60[1:0]M
PMDUG100[1:0]M
PMDUG120[1:0]M
MLDTHRE3[5:0]
MLDTHRE2[5:0]
MLDTHRE1[5:0]
MLENGTH[5:0]
5.2.24 PMDCTRL1 Register (CSR32)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0
FULLSCAL15M
FULLSCAL16M
FULLSCAL17M
PMDB40[1:0]M
PMDB60[1:0]M
PMDB100[1:0]M
PMDB120[1:0]M
PMDGS3[2:0]
PMDGS2[2:0]
PMDGS1[2:0]
PMDB2[1:0]
PMDGS4[2:0]
PMDB3[2:1]
PMDB5[2:0]
PMDPZ[1:0]
Field Name Description
20:18 PMDGS3 Read only bits
17:15 PMDGS2 Read only bits
14:12 PMDGS1 Read only bits
11:10 PMDB2 Read only bits
Field Name Description
5:0 MLENGTH Read only bits
42
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.26 PMDCTRL3 Register (CSR34)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 1 1 0
PMDUG40[1:0]M
PMDUG60[1:0]M
PMDUG100[1:0]M
PMDUG120[1:0]M
MGCTHRE2[5:0]
MGCTHRE1[5:0]
MVCPTHRE2[5:0]
MVCPTHRE1[5:0]
5.2.27 PMDCTRL4 Register (CSR35)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1
UGDFT[1:0]M
TDFT[1:0]M
PMDB[2:0]P
PMDGS[2:0]
PMDBP2:0]
MGAINCAL[5:0]
MNORMAL[5:0]
MPLLVCP[5:0]
Field Name Description
26:24 PMDB Read only bits
23:21 PMDGS Read only bits
20:18 PMDBP Read only bits
17:12 MGAINCAL Read only bits
11:6 MNORMAL Read only bits
5:0 MPLLVCP Read only bits
43
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.31 VLan T ag Register (CSR38)
VLan T ag Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
User Priority
QTga
CFI
VID
Field Name Description
31:16 QTag 802.1QTag header which is used in insertion of VLan tag in TX packet,default
value is 8100h.
15:13 Priority Qos priority bit, 000 to 111
1 2 CFI Counonical format lndicator, default=0
11:0 VID VLan ID, default value is 0h.
5.2.28 PMDCTRL5 Register (CSR36)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1
BLBYPS
CHECK_DISBM
PMDGS40[2:0]M
PMDGS60[2:0]M
PMDGS100[2:0]M
PMDGS120[2:0]M
SDIS1M
SDIS2M
SCH1M
SCH2M
FLAGM
TRFM[3:1]
VPPGM[6:1]
R1_10
R1_100
SDBPSB
AUTOCALB
5.2.29 PLLCTRL Register (CSR37)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1
CTU10[5:0]
CTD10[5:0]
CTU100[5:0]
CTD100[5:0]
44
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P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.32 Power Management Register (CSR39)
Power Management Register
Field Name Description
0 FORCEPM Default is 0 after host hardware reset, which means NWAY autonegotiation is
enabled. Set this bit to 1 will enable manual controls ( bit 8 :1 ) over chip power
saving features.
1 RST10B Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 and write 0 followed by write 1 to RST10B will
reset 10 base-T analog module.
2 RST100B Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 and write 0 followed by write 1 to RST100B will
reset 100 base-TX analog module.
3 PD10 Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 and write 1 to PD10 will power down 10 base-T
analog module's core except the 10 base-T line drivers.
4 PD100 Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 and write 1 to PD100 will power down 100 base-TX
analog module's core except the 100 base-TX line drivers.
5 LDD10 Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 and write 1 to LDD10 will power down 10 base-TX
analog module's line drivers.
6 LDD100 Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 then write 1 in LD100 will power down 100 base-TX
analog module's line drivers.
7 ENTXCLK Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 then write 0 in ENTXCLK will stop TXC 25/2.5
MHz clock in the MAC core.
8 ENRXCLK Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM)
is set to 1. When FORCEPM=1 then write 0 in ENRXCLK will stop RXC 25/2.5
MHz clock in the MAC core.
9 AUTOPM Default is 0 after host hardware reset, which means NWAY autonegotiation is
enabled. Set this bit high will enable automatic power saving mode which depends
on the status of PCI configuration's D0 - D3cold bits and will result in different
level of power saving.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOPM
ENRXCLK
ENTXCLK
LDD100
LDD10
PD100
RST100B
PD10
RST10B
FORCEPM
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.33 NIC CardBus Status Changed Registers
5.2.33.1 Function Event Register (CSR40)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read / Write
Interrupt
General W ake-up Event
Field Name Description
1 5 I nte rru pt The bit is set when there is an interrupt pending.
This bit is cleared by write 1.
4 GE W General Wake-up Event. This bit is set when the MX98727 has detected a power
management ev ent. The bit is cleared upon power-up reset and by writing 1.
When the PMCSR<15>, PME status, in the CardBus configuration is cleared, the
bit is automatically cleared as well.
5.2.33.2 Function Event Mask Register (CSR41)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read / Write
Interrupt Register Enable
Wake-up Event Summary Enable
General Wake-up Event Enable
Field Name Description
15 IRE Interrupt Register Enable. If set, enables the assertion of the interrupt pin when
the wak e up e v ents occur.
14 WESEN Wake-up Event Summary Enable. When set together with the SCR1<4>, GWEN,
enables the asertion of the PMEB pin.
To disable the assertion of this pin, the PMCSR<8>, PME Enable, must be cleared
as well.
4 GWEN General W ake-up Event Enable. When set together with the SCR1<14>, WESEN,
enables the asertion of the PMEB pin.
To disable the assertion of this pin, the PMCSR<8>, PME Enable, must be cleared
as well.
The bit is cleared upon power-up reset and by writing1.
When the PMCSR<15>, PME status, in the CradBus configuration is cleared, the
bit is automatically cleared as well.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.2.33.3 Function Present State Register (CSR42)
Field Name Description
15 In t er r u pt The bit reflects the internal state of a function specific interrupt.
It is cleared when the event that caused the interrupt was either masked in CSR7,
or cleared in CSR5.
4 GEW Reflects the current state of the wake-up event. This bit is cleared when either
SCR0<4>, GWE, is cleared or when PMCSR<15>, PME status, is cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read only
Interrupt
General W ake-up Event
5.2.33.4 Function Force Event Register (CSR43)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read / Write
Force Interrupt
Force W ak e-up Event
Field Name Description
15 FINT Force Interrupt. Writing 1 to this bit sets the Interrupt field in SCR0<15>, but not in
SCR<2>.
4 FWU F orce W ake-up . Writing 1 to this bit sets the wak e-up field in SCR0<4>, but not in
SCR2<4>.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
5.3 A CPI Power Management Support
The Advanced Configuration and Power Interface (ACPI)
Specification defines a flexible and abstract hardware
interface for a wide variety of PC systems to implement
pow er and thernal management functions . This chip is
fully compliant with the OnNow Network Device Class
Power Management spec. rev .1.0, the CARDBUS power
management interface spec. rev .1.1 and the A CPI spec.
rev.1.0.
Four power states defined for a CARDBUS function are:
* D0-Fully On.
The device is completely active and respon-
sive.
* D1-Light Sleep.
Save a little power than D0 state. The
CARDBUS clock is running.
* D2-Deeper Sleep:
Save more power than D1 state. The
CARDBUS clock can be stopped.
* D3hot-Deepest Sleep:
Save more power than D2 state. The
CARDBUS clock is stopped.
* D3cold-Power Down:
In this state, the main system power is re-
moved from the chip but will preserve their PME
context when transition from the D3cold to the
D0 state. Such function requires an auxiliary
power source other than main system power
plane.
This chip also supports the OnNow Network Device Class
Specification based on the ACPI specification defines
the power management requirements of a network de-
vice. It defines the following wake-up events:
* Reception of a Magic P ac k et.
* Reception of a Network wake-up frame.
* Detection of change in the network link state.
To put MX98727BEC into the sleep mode and enable
the wake-up events detection are done as following:
1. Write 1 to PPMCSR[8] to enable power management
feature.
2. Write the value to PPMCSR[1:0] to determine which
power state to enter.
If D1, D2 or D3hot state is set, the PC is still turned on
and is commonly called entering the Remote Wak e-up
mode. Otherwise if the main power on a PC is totally
shut off, we call that it is in the D3cold state or Remote
Power-On mode. To sustain the operation of the LAN
card, a 3.3V standby power is required. Once the PC is
turned on, MX98727BEC loads the Magic ID from
EEPROM and set it up automatically. No registers is
needed to be programmed. After then, simply turn of
PC to enter D3cold state. In either Remote Wake-up mode
or Remote P ower-On mode. The transceiver and the RX
block are still alive to monitor the network activity. If
one of the three wake-up events occurred, the following
status is changed:
1. PPMCSR[15] (PME status) is set to 1.
2. CRS5[28] (WKUPI) is set to 1.
3. CARDBUS interrupt pin INTA# is asserted low .
4. PMEB pin is asserted low.
5. In MX98727BEC , CSTSCHG are also asserted.
5.3.1 Magic Packet
The Magic Packet(TM) technology, proposed by AMD, is
used to remotely wake up a sleeping or powered off PC
on a network. This is accomplished by sending a spe-
cific pack et, called Magic Pac ket, to a node on the net-
work. When a NIC capable of recognizing the specific
frame goes to sleep (entering D1, D2 or D3 state), it
scans all incoming frames addressed to the node for a
specific data sequence, which indicates to the control-
ler that this is a Magic Packet frame. The specific se-
quence consists of 16 duplications of the IEEE address
of this node, with no breaks or interruptions. This se-
quence can be located anywhere within the packet, but
must be preceded by a synchronization stream. The
synchronization stream is defined as 6 bytes of FFh.
For example, if the IEEE address for a particular node
on the network was 11h 22h 33h 44h 55h 66h, then the
Magic P ac ket for this node would be:
D A SA MISC. FF FF FF FF FF FF 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
MISC. CRC.
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
This chip can automatically loads the IEEE address into
the internal registers from EEPROM while booting up.
the magic packet detection scheme is not active while
chip is in normal running state (D0). After entering into
the sleep mode(D1, D2, D3) by host, the chip begins to
scan the incoming packet but does not load the packet
into RX FIFO . If a magic pack et is detected, the PMEB
is asserted to notify the host.
Magic packet event occurs when the following condi-
tions are approved:
* The destination address of the received packet
matches.
* The PMEN bit (PPMCSR[8]) is set to 1.
* Not in D0 state.
* The magic packet patter n matches, i.e., 6*FFh +
16* Destination ID .
<Note>: The CRC value is not checked during magic
packet detection.
5.3.2 Wake-up Frames
A network wake-up frame is typically a frame that is
sent by existing network protocols, such as ARP re-
quests or IP frames addressed to the machine. Before
putting the network adapter into the wake-up state, the
system passes to the adapter's driver a list of sample
frames and corresponding byte masks. Each sample
frame is an example of a frame that should wake up the
system. Each byte mask defines which bytes of the
incoming frames should be compared with correspond-
ing sample frame in order to determine whether or not to
accept the incoming frame as a wake-up event.
The on-chip Wake-up logic provides four programmable
filters that allow support of many different receive packet
patterns. Specifically, these filters allow suppor t of IP
and IPX protocols which currently are the only protocols
targeted to be power manageable. Each filter relates to
32 contiguous bytes in the incoming frame.
When a frame is received from the network, the chip
examines its content to determine whether the pattern
matches to a wake-up frame. To know which byte of the
frame should be checked, a programmable byte-mask
and a programmable pattern offset are used for each
one of the f our supported filters. The pattern offset de-
fines the location of the first byte in the frame that should
be checked. Beginning with the pattern offset, if bit j in
the byte mask is set, byte offset+j in the frame is checked.
The chip implements imperfect pattern matching by cal-
culating a CRC-16 on all bytes of the received frame
that where specified by the pattern's offset and the byte
mask and comparing to a programmable pre-calculated
CRC-16 remainder value. The CRC calculation uses the
following polynomial:
G(X)=X16 + X15 + X2 +1
The calculated CRC-16 value is compared with four pos-
sible CRC-16 values stored in CSR30 and CSR31. if the
result matches any one and the enable bit of the corre-
sponding filter also set, then we call a Wakeup frame
received.
Table1 shows the wake-up frame register block. This
block is accessed through CSR registers mapping.
Filter 0 Byte Mask CSR25
Filter 1 Byte Mask CSR26
Filter 2 Byte Mask CSR27
Filter 3 Byte Mask CSR28
Filter 3 Filter 2 Filter 1 Filter 0 CSR29
Filter 1 CRC-16 Filter 0 CRC-16 CSR30
Filter 3 CRC-16 Filter 2 CRC-16 CSR31
The four filters can operate independently to match four
32-byte wake up frames. They also can be programmed
to catenate each other to support longer wake up frames,
ranging from 32 bytes up to 128 bytes. The following
table shows the possible combination.
CSR21.4 CSR9.26 CSR9.25 Wake up event
WKFCATEN WKFCAT1 WKFCAT0
0 X X CH0+CH1+CH2+CH3
1 0 0 (CH0*CH1)+(CH2*CH3)
1 0 1 (CH0*CH1)+CH2+CH3
1 1 0 (CH0*CH1*CH2)+CH3
1 1 1 CH0*CH1*CH2*CH3
If WAKCATEN (CSR21.4) is not set, the four filters are
independent and simultaneous to match the incoming
frame. When WKFCATEN is set, the catenation options
are determined by WKFCAT<1:0> (CSR<26:25>). For
example, if WKFCAT<1:0>=00, wake up event is oc-
curred only if either both of channel 0 and channel 1
match or both of channel 2 and channel 3 match. If the
49
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
* Not in D0 state.
* The destination address of the received wakeup
frame matches.
* No CRC-32 error is detected in the wakeup frame.
* The PMEN bit (PPMCSR[8]) is set to 1.
* The enable bit in the wakeup frame register block
must be set.
* The CRC value calculated from the bytes in the
pre-designated locations equals to the respectively
stored CRC-16 value.
* If catenation must be met. enable bit WKFCATEN
is set, the condition in table 2.
5.3.3 Link Change
Link change wakeup event occurs when the following
conditions are met:
* Not in D0 state.
* The PMEN bit (PMCSR[8]) is set to 1.
* The cable is reconnected.
The Remote Power-on (RPO) feature is a mechanism
can be used to remotely power up a sleeping station.
When the PC turned on, MX98727BEC loads the net-
work ID from serial ROM automatically. Once the PC is
turned off, MX98727BEC enters the RPO mode.
MX98727BEC monitors the network for receipt of a
wakeup packet. If a magic packet or wake up frame is
received, it asserts PMEB, signal to wake up the sys-
tem. After main power is on, PMEB is deserted by
CARDBUS RSTB signal. After the desertion,
MX98727BEC can enter RPO mode again if the main
power is switched off.
driver sets filter 0 and filter 1 be contiguous and also
sets filter 2 and filter 3 be contiguous by adjusting the
offsets, then two 64-byte wake up frames are supported.
Another example is that if WKFCAT<1:0>=11 and the
driver sets filter 0,1,2,3 as contiguous, a 128-byte wake
up frame is supported.
Wakeup Frames event occurs when following conditions
are met:
6. Modem Interface:
The MX98727BEC implements an interface for modem
which enables connection of a non-CardBus modem
chipsets to a CardBus system. It could integrate the
LAN and Modem functions on a single Cardbus card,
reducing the slot requirement and cost of a notebook
PC.
The modem function is enabled when
Func1_HwOption<0> bit in the serial ROM is set. While
CardBus is accessing the modem, the MX98727BEC
acts as a bus slave, translating the address and data,
and issuing a read/write cycle to the modem chipsets. A
read or write cycle to the modem could only access one
modem register of 8 bit-wide. The MX98727BEC can
support up to 32 modem registers. The possible value of
registers which can be accessed is determined by PCI
configuration register CBIO[4:3].
A write access to the modem chipset is executed as
following and the timing waveform is shown in Figure
6.1.
1. The host initiates a write cycle on the CardBus and
writes the data to the MX98727BEC.
2. The MX98727BEC drives the address on the
MDMADR[4:0] lines.
3. The MX98727BEC drives the data on the
MDMDTA[7:0] lines.
4. The MX98727BEC asserts the MDMCSB line.
5. The MX98727BEC asserts the MDMWRB line.
6. The modem chipset may assert the MDMWAITB
line to insert wait states.
7. The MX98727BEC deasserts the MDMWRB line.
8. The MX98727BEC deasserts the MDMCSB
line.Tcss
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
6.1 Modem write access timing diagram
A read access to the modem chipset is executed as
following and the timing diagram is shown in Figure 6.2.
1. The host initiates a read cycle on the CardBus.
2.The MX98727BEC drives the address on the
MDMADR[4:0] lines.
3. The MX98727BEC asserts the MDMCSB line.
4. The MX98727BEC asserts the MDMRDB line.
5. The modem chipset may assert the MDMWAITB
line to insert wait states.
6. The modem chipset drives the data on the
MDMDTA[7:0].
7. The MX98727BEC samples the data on the
MDMDTA[7:0] lines.
8. The MX98727BEC deasserts the MDMRDB line.
9. The MX98727BEC deasserts the MDMCSB line.
MDMCSB
MDMADR[4:0]
Tcss
Twpw
Twd
Tads
w/wh
Tdss
MDMWRB
MDMWAITB
MDMADR[4:0]
Tadh
Tcsh
Tcsh
Fig 6.2 Modern Write Access Timing Diagram
MDMCSB
MDMADR[4:0]
Tcss
Twpw
Twd
Tads
R/Wh
Tdss Tdd
MDMWRB
MDMWAITB
Fig 6.2 Modern Read Access Timing Diagram
MDMADR[7:0]
Tadh
Tcsh
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
T able 6.1 shows the timing parameters for modem interface.
T able 6.1 Modem Interface Timing Parameter
Symbol Parameter Minimum Maximum Unit
Tcss Chip Select Set_up 6 0 ns
Tads Address Set_up 8 0 ns
Tadh Address Hold 6 0 ns
W/Wh Write Pulse Width 160 ns
R/Wh Read Pulse Width 16 0 ns
Tdss Data Set_up 8 0 ns
Tdh Data Hold 40 ns
Tdd Data Delay 9 0 ns
Tcsh Chip Select Hold 4 0 ns
d Wait Delay 120 ns
Tw p w Wait Pulse Width 240 ns
10Base-T Link Pulse Timing
Symbol Parameter Min Max Units
tip Time between Link Output Pulses 8 2 4 ms
tipw Link Integrity Output Pulse Width 8 0 1 3 0 ns
6.2 Modem Function Address mapping
The MX98727BEC modem function supports 8,16, or 32 byte-wide CSRs that can be mapped to either the I/O space
through CBIO or to the memory space through CBMA. These CSRs are the modem chipset registers. In addition, the
modem function can access the four CardBus Status Changed Registers which defined in NIC function through the
memory space CSR40(SCR0), CSR41(SCR1), CSR42(SCR2), CSR43(SCR3), and shared by both modem function &
NIC function. However, there are still three(CSR41, bit5~bit7) bits in Function Event Mask Register that are useful
only in modem function. Here we just present this register all other 3 registers are the same as defined in NIC
function.
Function Event Mask Register(SCR1)
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt Register Enable
Wake-up Event Summary Enable
MINTE-Modem Interrupt Enable
Binary Audio Enable
General Wake-up Event Enable
Pulse Width Modulation Enable
52
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
Field Name Description
1 5 IRE Interrupt Register Enable. If set, enables the assertion of the interrupt pin when the wake-
up e v ents occur.
14 WESEN Wake-up Event Summary Enable. When set together with the SCR1<4> ,GWEN, enables
the assertion of the PMEB pin. To disable the assertion of this pin, Enable, must be
cleared as well.
6 PWME* Pulse Width Modulation Enable . If Func1_HwOption<7> is set, the Pulse Width Modula-
tion Enable bit is driven on the MDMSPKEN pin. This bit is cleared upon hardware or
software reset.
7 MINTE Modem interrupt enable. If the bit is set, the interrupt from modem will issue INTAB pin. The
default value is set.
5 BAE* Binary Audio Enable. If Func1_HwOption<7> is cleared, the Binary Audio Enable bit is
driven on the MDMSPKEN pin. This bit is cleared upon hardware or software reset.
4 GWEN General Wake-up Event Enable. When set together with the SCR1<14> WESEN, enables
the assertion of the PMEB pin. To disable the assertion of this pin, the PMCSR<8>, PME
Enable, must be cleared as well. The bit is cleared upon power-up reset and by writing 1
When the PMCSR<15>, PME status, in the CardBus configuration is cleared , the bit is
automatically cleared as well.
* These two bits are accessib le only in modem function.
Figure 6.3 shows a I/O-based and a memory-based address map of the modem function. The offset addresses from
A0h to 3FFh are reserved for both I/O and memory mapping, and 80h to 98h are reserved only for I/O mapping.
I/O based offest
0h
01h
02h
0h
01h
02h
1Fh
1Fh
Memory based offset
80h
88h
90h
98h
200h
3FF
Modem REG0
Reserved
Reserved
Reserved
Fig 6.3 I/O and Memory based address map of the modern function
Modem REG1
:::
:
Reserved
Modem REG31
SCR0
SCR1
SCR2
SCR3
EEPROM
53
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
7. AC/DC CHARACTERISTICS
7.1 BOOT ROM READ TIMING
7.2 AC CHARACTERISTICS
SYMBOL DESCRIPTION MINIMUM TYPICAL MAXIMUM UNITS
TRC Read Cycle 8 - - CARDBUS Cycle
TC E Chip Enab le Access Time - - 7 CARDBUS Cycle
TACC Address Access Time - - 7 CARDBUS Cycle
T O ES Output Enable Access Time - - 7 CARDBUS Cycle
TO H Output Hold from Address, CEB, or OEB 0 - - ns
CARDBUS cycle range:66ns (16MHz)~30ns (33MHz)
TRC
BPA 15-0
TOES
TCE
FCEB
FOEB
(CE&OE is typical shorted)
TOH
BPD 7:0
TACC
TOOLZ
TCOLZ
TOH
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MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
7.3 ABSOLUTE OPERA TION CONDITION
Supply Voltage (VCC) -0.5V to +7.0V
DC Input Voltage (Vin) 3.15 V to 3.45 V
DC Output Voltage (Vout) -0.5V to VCC + 0.5V
Storage T emperature Range (Tstg) -55°C to +150°C
Operating T emperature Range 0°C to 70°C
Operating Surface T emperature(25°C) 48 °C(TYP)
Power Dissipation (PD) 750 mW (Typ.)
Lead Temp. (TL) (Soldering, 10 sec) 260°C
ESD Rating (Rzap = 1.5k, Czap = 100pF) 3kV
Clamp Diode Current 20mA
7.4 DC CHARACTERISTICS
Symbol Parameter Conditions Min Max Units
TTL/CARDBUS Input/Output
Voh Minimum High Level Output V oltage Ioh = -3mA 2.4 V
V ol Maximum Low Le vel Output V oltage Iol = +6mA 0. 4 V
Vih Minimum High Le v el Input Voltage ( 3.3V/5V tolerant ) 2. 0 V
Vil Maximum Lo w Lev el Input Voltage ( 3.3V/5V tolerant ) 0. 8 V
Iin Input Current Vi = VCC or GND - 1.0 + 1.0 uA
Ioz Minimum TRI-STATE Output Leakage Current V out = VCC or GND -10 +10 uA
LED output Driver
Vlol LED turn on Output V oltage Iol = 16mA 0.4 V
Supply
Idd Average Supply Current CKREF =25MHz
CARDBUSCLK = 33MHz
D0 (100Mbps) 1 50 185 mA
D1 (100Mbps) 1 50 185
D2 (100Mbps) 1 50 180
D3 (100Mbps) 1 50 180
D0 (10Mbps) 1 70 200
D1 (10Mbps) 1 70 195
D2 (10Mbps) 1 70 195
D3 (10Mbps) 1 70 195
Vdd Average Supply V oltage 3.3V 5% tolerant
55
MX98727BEC
P/N:PM0669 REV. 0.1, AUG. 07, 2000
8.0 PACKAGE INFORMATION
128-Pin Plastic Quad Flat Pack
A
eL
A1
L1
E3 aE
38
1
64
65
102
103
128 39
IH
D3
D
ZD
b
c
d
ZE
ITEM MILLIMETERS INCHES
a 14.00±.05 5.512±.002
b .20 [Typ.] .08 [Typ.]
c 20.00±.05 7.87±.002
d 1.346 .530
e .50 [Typ.] .20 [Typ.]
L1 1.60±.1 .63±.04
L .80±.1 .31±.04
ZE .75 [Typ.] .30 [Typ.]
E3 12.50 [Typ.] 4.92 [Typ.]
E 17.20±.2 6.77±.08
ZD .75 [Typ.] .30 [Typ.]
D3 18.50 [Typ.] 7.28 [Typ.]
D 23.20±.2 9.13±.08
A1 .25±.1 min. .01±.04 min.
A 3.40±.1 max. 1.34±.04 max.
Note Short Lead Short Lead
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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TEL:+81-44-246-9100
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FAX:+65-348-8096
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TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
MX98727BEC
MX98727BEC
M0030
T63165C0B6
TAIWAN
TOP SIDE MARKING
line 1 : MX98727B is MXIC parts No.
"E" :PQFP
"C" : commercial grade
line 2 : Assembly Date Code.
line 3 : W af er Lot No .
line 4 : State
