General Description
The MAX6365–MAX6368 supervisory circuits simplify
power-supply monitoring, battery-backup control func-
tions, and memory write protection in microprocessor
(µP) systems. The circuits significantly improve the size,
accuracy, and reliability of modern systems with an ultra-
small integrated solution.
These devices perform four basic system functions:
1) Provide a µP reset output during VCC supply power-
up, power-down, and brownout conditions.
2) Internally control VCC to backup-battery switching to
maintain data or low-power operation for CMOS
RAM, CMOS µPs, real-time clocks, and other digital
logic when the main supply fails.
3) Provide memory write protection through internal
chip-enable gating during supply or processor faults.
4) Include one of the following options: a manual reset
input (MAX6365), a watchdog timer function
(MAX6366), a battery-on output (MAX6367), or an
auxiliary user-adjustable reset input (MAX6368).
The MAX6365–MAX6368 operate from VCC supply volt-
ages as low as 1.2V. The factory preset reset threshold
voltages range from 2.32V to 4.63V (see Ordering
Information). In addition, each part is offered in three
reset output versions: push-pull active low, open-drain
active low, or open-drain active high (see Selector
Guide). The MAX6365–MAX6368 are available in minia-
ture 8-pin SOT23 packages.
Applications
Critical µP/µC Power Portable/Battery-
Monitoring Powered Equipment
Fax Machines Set-Top Boxes
Industrial Control POS Equipment
Computers/Controllers
Features
♦Low +1.2V Operating Supply Voltage (VCC or VBATT)
♦Precision Monitoring of +5.0V, +3.3V, +3.0V, and
+2.5V Power-Supply Voltages
♦On-Board Gating of Chip-Enable Signals, 1.5ns
Propagation Delay
♦Debounced Manual Reset Input (MAX6365)
♦Watchdog Timer, 1.6s Timeout (MAX6366)
♦Battery-On Output Indicator (MAX6367)
♦Auxiliary User-Adjustable RESET IN (MAX6368)
♦Low 10µA Quiescent Supply Current
♦Three Available Output Structures
Push-Pull RESET
Open-Drain RESET
Open-Drain RESET
♦RESET/RESET Valid Down to 1.2V Guaranteed
(VCC or VBATT)
♦Power-Supply Transient Immunity
♦150ms min Reset Timeout Period
♦Miniature 8-Pin SOT23 Package
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
________________________________________________________________ Maxim Integrated Products 1
OUT
VCC
MR
1
2
8
7
CE OUT
BATTCE IN
GND
RESET, RESET
SOT23
TOP VIEW
3
4
6
5
MAX6365
Pin Configurations
19-1658; Rev 2; 5/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
*These parts offer a choice of reset threshold voltages. From the
Reset Threshold Ranges table, insert the desired threshold volt-
age code in the blank to complete the part number. SOT parts
come in tape-and-reel only and must be ordered in 2500-piece
increments. See Device Marking Codes for a complete parts list,
including SOT top marks and standard threshold versions. See
Selector Guide for a listing of device features.
Pin Configurations continued at end of data sheet. Typical Operating Circuit appears at end of data sheet.
PART* TEMP RANGE PIN-
PACKAGE
M A X6 3 6 5 LK A_ _-T
-40°C to +85°C 8 SOT23-8
MAX6365PKA_ _-T -40°C to +85°C 8 SOT23-8
MAX6365HKA_ _-T
-40°C to +85°C 8 SOT23-8
M A X6 3 6 6 LK A_ _-T
-40°C to +85°C 8 SOT23-8
M A X 6 36 6P K A_ _-T -40°C to +85°C 8 SOT23-8
M A X 6 36 6H K A_ _-T -40°C to +85°C 8 SOT23-8
M A X6 3 6 7 LK A_ _-T
-40°C to +85°C 8 SOT23-8
M A X 6 36 7P K A_ _-T
-40°C to +85°C 8 SOT23-8
M A X 6 36 7H K A_ _-T
-40°C to +85°C 8 SOT23-8
M A X6 3 6 8 LK A_ _-T
-40°C to +85°C 8 SOT23-8
M A X 6 36 8P K A_ _-T
-40°C to +85°C 8 SOT23-8
M A X 6 36 8H K A_ _-T
-40°C to +85°C 8 SOT23-8
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +2.4V to +5.5V, VBATT = +3.0V, CE IN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltages (with respect to GND)
VCC, BATT, OUT.......................................................-0.3V to +6V
RESET (open drain), RESET (open drain) ................-0.3V to +6V
BATT ON, RESET (push-pull), RESET IN,
WDI, CE IN, CE OUT ...........................-0.3V to (VOUT + 0.3V)
MR ..............................................................-0.3V to (VCC + 0.3V)
Input Current
VCC Peak ..............................................................................1A
VCC Continuous .............................................................250mA
BATT Peak .....................................................................250mA
BATT Continuous .............................................................40mA
GND ...............................................................................75mA
Output Current
OUT ...............................Short-Circuit Protected for up to 10s
RESET, RESET, BATT ON, CE OUT...............................20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.75mW/°C above +70°C)........700mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Operating Voltage Range
(Note 2)
VCC, VBATT
No load 0 5.5 V
VCC = 2.8V 10 30
VCC = 3.6V 12 35
Supply Current
(Excluding IOUT)ICC
No load, VCC > VTH
VCC = 5.5V 15 50
µA
TA = +25°C1
Supply Current in Battery-
Backup Mode (Excluding IOUT)
IBACK VBATT = 2.8V,
VCC = 0 TA = -40°C to +85°C3
µA
TA = +25°C
-0.1 0.02
BATT Standby Current IBATT
5.5V > VCC > (VBATT
+ 0.2V) TA = -40°C to +85°C
-1.0 0.02
µA
VCC = 4.75V, IOUT = 150mA 3.1
VCC = 3.15V, IOUT = 65mA 3.7VCC to OUT On-Resistance RON
VCC = 2.38V, IOUT = 25mA 4.6
Ω
VBATT = 4.5V, IOUT = 20mA VBATT -
0.2
VBATT = 3.0V, IOUT = 10mA VBATT -
0.15
Output Voltage in Battery-
Backup Mode VOUT
VBATT = 2.25V, IOUT = 5mA VBATT -
0.15
V
Power-up 20
Battery-Switchover Threshold
(VCC - VBATT) VSW VCC < VTH Power-down -20 mV
MAX636_ _KA46
4.50 4.63 4.75
MAX636_ _KA44
4.25 4.38 4.50
MAX636_ _KA31
3.00 3.08 3.15
MAX636_ _KA29
2.85 2.93 3.00
MAX636_ _KA26
2.55 2.63 2.70
Reset Threshold VTH
MAX636_ _KA23
2.25 2.32 2.38
V
VCC Falling Reset Delay tRD VCC falling at 10V /ms 20 µs
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +5.5V, VBATT = +3.0V, CE IN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reset Active Timeout Period tRP 150
280
ms
ISINK = 1.6mA,
VCC
>
2.1V
0.3
VOL Reset asserted,
VBATT = 0 ISINK = 100µA,
VCC
>
1.2V
0.4
RESET Output Voltage
VOH Reset not asserted
(MAX636_L only)
ISOURCE = 500µA,
VCC
>
VTH(MAX)
0.8 ✕
VCC
V
VOL Reset not asserted ISINK = 1.6mA,
VCC
>
VTH (MAX)
0.3
ISOURCE = 1mA,
VCC
>
1.8V
0.7 ✕
VCC
RESET Output Voltage
VOH
Reset not asserted,
VBATT = 0
(MAX636_H only)
(Note 3)
ISOURCE = 200µA,
VCC
>
1.2V
0.8 ✕
VCC
V
RESET Outp ut Leakag e C ur r ent ILKG MAX636_P and MAX636_H only 1 µA
MANUAL RESET (MAX6365 only)
VIL 0.3 ✕
VCC
MR Input Voltage
VIH 0.7 ✕
VCC
V
Pullup Resistance 20 kΩ
Minimum Pulse Width 1µs
Glitch Immunity VCC = 3.3V
100
ns
MR to Reset Delay VCC = 3.3V
120
ns
WATCHDOG (MAX6366 only)
Watchdog Timeout Period tWD 1.00
1.65 2.25
s
Minimum WDI Input Pulse Width
tWDI 100 ns
VIL 0.3 ✕
VCC
WDI Input Voltage
VIH 0.7 ✕
VCC
V
WDI Input Current -1.0
1.0
µA
BATT ON (MAX6367 only)
Output Voltage VOL ISINK = 3.2mA, VBATT = 2.1V
0.4
V
Sink current, VCC = 5V 60 mA
Output Short-Circuit Current Source current, VBATT
>
2V 10 30
100
µA
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
4 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
8
10
9
12
11
15
14
13
16
-40 0-20 20 40 60 80
SUPPLY CURRENT
vs. TEMPERATURE (NO LOAD)
MAX6365/8-01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VCC = 5.0V
VBATT = 0
0
0.2
0.6
0.4
0.8
1.0
1.2
BATTERY SUPPLY CURRENT
(BACKUP MODE) vs. TEMPERATURE
MAX6365/8-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (µA)
-40 20 40-20 0 60 80
VBATT = 2.0V
VCC = 0
VBATT = 2.8V
0
2
1
4
3
7
6
5
8
-40 0-20 20 40 60 80
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX6365/8-03
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE (Ω)
VBATT = 5.0V
VBATT = 2.0V
VBATT = 2.8V
IOUT = 25mA
VCC = 0
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +5.5V, VBATT = +3.0V, CE IN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET IN (MAX6368 only)
RESET IN Threshold VRTH
1.185 1.235 1.285
V
RESET IN Leakage Current
±0.01 ±25
nA
RESET IN to Reset Delay VOD = 50mV, RESET IN falling 1.5 µs
CHIP-ENABLE GATING
CE IN Leakage Current Reset asserted
±1
µA
CE IN to CE OUT Resistance Reset not asserted (Note 4) 20
100
Ω
CE OUT Short-Circuit Current Reset asserted, CE OUT = 0
0.75 2.0
mA
VCC = 4.75V 1.5 7
CE IN to CE OUT Propagation
Delay
50Ω source,
CLOAD = 50pF VCC = 3.15V 2 9 ns
VCC = 5V, VCC
>
VBATT, ISOURCE = 100µA
0.8 ✕ VCC
CE OUT Output Voltage High
VCC = 0, VBATT
>
2.2V, ISOURCE = 1µA VBATT -
0.1
V
Reset-to-CE OUT Delay 12 µs
Note 1: All devices are 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2: VBATT can be 0 anytime, or VCC can go down to 0 if VBATT is active (except at startup).
Note 3: RESET is pulled up to OUT. Specifications apply for OUT = VCC or OUT = BATT.
Note 4: The chip-enable resistance is tested with VCC = VTH(MAX) and CE IN = VCC/2.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0
0.4
0.2
0.8
0.6
1.2
1.0
1.4
-40 0 20-20 40 60 80
VCC TO OUT ON-RESISTANCE
vs. TEMPERATURE
MAX6365/8-04
TEMPERATURE (°C)
VCC TO OUT ON-RESISTANCE (Ω)
VCC = 3.0V
IOUT = 65mA
VCC = 4.5V
IOUT = 150mA
VCC = 2.3V
IOUT = 25mA
190
195
205
200
210
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX6365/8-05
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
-40 20 40-20 0 60 80
0
30
15
75
60
45
135
120
105
90
MAX6365/8-06
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
-40 20 40-20 0 60 80
VCC TO RESET PROPAGATION DELAY
vs. TEMPERATURE
VCC FALLING
0.25V/ms
1V/ms
10V/ms
2.0
3.0
2.5
5.0
4.5
4.0
3.5
RESET THRESHOLD
vs. TEMPERATURE
MAX6365/8-07
TEMPERATURE (°C)
THRESHOLD (V)
-40 20 40-20 0 60 80
MAX636_ 46 (VTH = 4.63V)
MAX636_ 26 (VTH = 2.63V)
1 10010 1000 10,000
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
MAX6365/8-08
RESET THRESHOLD OVERDRIVE VTH - VCC (mV)
MAXIMUM TRANSIENT DURATION (µs)
400
300
350
250
200
0
50
150
100
MAX636_ 26
(VTH = 2.63V)
MAX636_ 46
(VTH = 4.63V)
RESET OCCURS
ABOVE CURVE
0
3
2
1
5
4
9
8
7
6
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
BATTERY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6365/8-09
VCC (V)
BATTERY SUPPLY CURRENT (µA)
VTH = 2.93V
VBATT = 2.8V
VBATT = 2.5V
VBATT = 2.3V
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
6 _______________________________________________________________________________________
1.234
1.235
1.236
MAX6368
RESET IN THRESHOLD
vs. TEMPERATURE
MAX6365/8 -10
TEMPERATURE (°C)
VRTH (V)
-40 20 40-20 0 60 80
1.0
1.9
1.6
1.3
2.8
2.5
2.2
MAX6368
RESET IN TO RESET PROPAGATION DELAY
vs. TEMPERATURE
MAX6365/8-11
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
-40 20 40-20 0 60 80
VOD = 50mV
0
1
3
2
4
5
MAX6365/8-12
CLOAD (pF)
PROPAGATION DELAY (ns)
0 10050 150 200
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
CE IN = 0 TO VCC
DRIVER SOURCE
IMPEDANCE = 50Ω
VCC = 3V
VCC = 5V
0
5
15
10
20
25
-40 0-20 20 40 60 80
MAX6365/8-13
TEMPERATURE (°C)
CE IN TO CE OUT ON-RESISTANCE (Ω)
CE IN TO CE OUT ON-RESISTANCE
vs. TEMPERATURE
V
CC = 3.0V
VCC = 5.0V
VCE IN = VCC/2
VBATT = 0
1.0
1.3
1.2
1.1
1.5
1.4
1.9
1.8
1.7
1.6
2.0
-40 -20 0 20 40 60 80
MAX6365/8-14
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (s)
MAX6366
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
VCC = 5.0V
VBATT = 0
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
RESET
Acti ve- H i g h Reset Outp ut. RE S E T asser ts hi g h conti nuousl y w hen V
C C
i s b el ow the r eset thr eshol d ( V
TH
) ,
MR i s l ow , or RE S E T IN i s l ow . It asser ts i n p ul ses w hen the inter nal w atchd og ti m es out. RE S E T r em ai ns
asser ted for the r eset ti m eout p er i od ( tRP
) after V
C C
r i ses ab ove the r eset thr eshol d , after the m anual r eset
i np ut g oes fr om l ow to hi g h, after RE S E T IN g oes hi g h, or after the w atchd og tr i g g ers a r eset event.
RE S E T i s an op en- d r ai n acti ve- hi g h r eset outp ut.
1
RESET
Active-Low Reset Output. RESET asserts low continuously when V
C C is below the reset threshold
(VTH), the manual reset input is low, or RESET IN is low. It asserts low in pulses when the internal
watchdog times out. RESET remains asserted low for the reset timeout period (tRP) after V
C C
rises above the reset threshold, after the manual reset input goes from low to high, after RESET
IN goes high, or after the watchdog triggers a reset event. The MAX636_L is an active-low push-
pull output, while the MAX636_P is an active-low open-drain output.
2CE IN
Chip-Enable Input. The input to chip-enable gating circuitry. Connect to GND or OUT if not used.
3 GND Ground
MR
MAX6365 Manual-Reset Input. Maintaining logic low on MR asserts a reset. Reset output
remains asserted as long as MR is low and for the reset timeout period (tRP) after MR transitions
from low to high. Leave unconnected, or connect to VCC if not used. MR has an internal 20kΩ
pullup to VCC.
WDI
MAX6366 Watchdog Input. If WDI remains high or low for longer than the watchdog timeout
period (t
W D ), the internal watchdog timer runs out and a reset pulse is triggered for the reset
timeout period (tRP). The internal watchdog clears whenever reset asserts or whenever WDI sees
a rising or falling edge (Figure 2).
BATT ON MAX6367 Battery-On Output. BATT ON goes high when in battery backup mode.
4
RESET IN MAX6368 Reset Input. When RESET IN falls below 1.235V, reset asserts. Reset output remains
asserted as long as RESET IN is low and for at least tRP after RESET IN goes high.
5V
CC
Supply Voltage, 1.2V to 5.5V. Reset asserts when V
C C drops below the reset threshold voltage
(VTH). Reset remains asserted until V
C C rises above VTH and for at least tRP after V
C C rises
above VTH.
6 OUT Output. OUT sources from V
C C when not in reset and from the greater of VCC or BATT when V
C C
is below the reset threshold.
7 BATT
Backup-Battery Input. When V
C C falls below the reset threshold, OUT switches to BATT if VBATT
is 20mV greater than V
C C . When V
C C rises 20mV above VBATT, OUT switches to V
C C . The 40mV
hysteresis prevents repeated switching if VCC falls slowly.
8CE OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE
IN is low when reset is asserted, CE OUT will stay low for 12µs (typ) or until CE IN goes high,
whichever occurs first.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
8 _______________________________________________________________________________________
MAX6365
MAX6366
MAX6367
MAX6368
CHIP-ENABLE
OUTPUT
CONTROL
VCC
BATT
CE IN
20k
MR
(MAX6365 ONLY)
WDI
(MAX6366 ONLY)
RESET IN
(MAX6368 ONLY)
RESET
GENERATOR
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
1.235V
GND
1.235V
RESET
(RESET)
CE OUT
OUT
BATT ON (MAX6367 ONLY)
Detailed Description
The Typical Operating Circuit shows a typical connec-
tion for the MAX6365–MAX6368. OUT powers the static
random-access memory (SRAM). If VCC is greater than
the reset threshold (VTH), or if VCC is lower than VTH
but higher than VBATT, VCC is connected to OUT. If
VCC is lower than VTH and VCC is less than VBATT,
BATT is connected to OUT. OUT supplies up to 150mA
from VCC. In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of backup-battery voltage
and is shown in the BATT-to-OUT On-Resistance vs.
Temperature graph in the Typical Operating Char-
acteristics.
Chip-Enable Signal Gating
The MAX6365–MAX6368 provide internal gating of CE
signals to prevent erroneous data from being written to
CMOS RAM in the event of a power failure. During nor-
mal operation, the CE gate is enabled and passes all
CE transitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. All of these devices use a series trans-
mission gate from CE IN to CE OUT. The 2ns propaga-
tion delay from CE IN to CE OUT allows the devices to
be used with most µPs and high-speed DSPs.
During normal operation, CE IN is connected to CE
OUT through a low on-resistance transmission gate.
This is valid when reset is not asserted. If CE IN is high
when reset is asserted, CE OUT remains high regard-
less of any subsequent transitions on CE IN during the
reset event.
If CE IN is low when reset is asserted, CE OUT is held
low for 12µs to allow completion of the read/write oper-
ation (Figure 1). After the 12µs delay expires, the CE
Functional Diagram
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
_______________________________________________________________________________________ 9
OUT goes high and stays high regardless of any sub-
sequent transitions on CE IN during the reset event.
When CE OUT is disconnected from CE IN, CE OUT is
actively pulled up to OUT.
The propagation delay through the chip-enable circuit-
ry depends on both the source impedance of the drive
to CE IN and the capacitive loading at CE OUT. The
chip-enable propagation delay is production tested
from the 50% point of CE IN to the 50% point of CE
OUT, using a 50Ωdriver and 50pF load capacitance.
Minimize the capacitive load at CE OUT to minimize
propagation delay, and use a low-output-impedance
driver.
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of the RAM. With a backup bat-
tery installed at BATT, the MAX6365–MAX6368 auto-
matically switch the RAM to backup power when VCC
falls. The MAX6367 has a BATT ON output that goes
high in battery-backup mode. These devices require
two conditions before switching to battery-backup
mode:
1) VCC must be below the reset threshold.
2) VCC must be below VBATT.
Table 1 lists the status of the inputs and outputs in bat-
tery-backup mode. The devices do not power up if the
only voltage source is on BATT. OUT only powers up
from VCC at startup.
Manual Reset Input (MAX6365 Only)
Many µP-based products require manual reset capabili-
ty, allowing the user or external logic circuitry to initiate a
reset. For the MAX6365, a logic low on MR asserts reset.
Reset remains asserted while MR is low and for a mini-
mum of 150ms (tRP) after it returns high. MR has an inter-
nal 20kΩpullup resistor to VCC. This input can be driven
with TTL/CMOS logic levels or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to pro-
vide additional noise immunity.
Figure 1. Reset and Chip-Enable Timing
VCC OR BATT
RESET
THRESHOLD VTH
RESET
CE IN
CE OUT
RESET
*
tRD tRD
tRP tRP
IF CE IN GOES HIGH BEFORE RESET ASSERTS,
CE OUT GOES HIGH WITHOUT DELAY AS
CE IN GOES HIGH.
RESET-TO-CE OUT DELAY (12µs)
*
PIN STATUS
VCC Disconnected from OUT
OUT Connected to BATT
BATT
Connected to OUT. Current drawn from
the battery is less than 1µA (at VBATT =
2.8V, excluding IOUT) when VCC = 0.
RESET/RESET Asserted
BATT ON High state
MR, RESET IN,
CE IN, WDI Inputs ignored
CE OUT Connected to OUT
Table 1. Input and Output Status in
Battery-Backup Mode
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
10 ______________________________________________________________________________________
Watchdog Input (MAX6366 Only)
The watchdog monitors µP activity through the watch-
dog input (WDI). If the µP becomes inactive, reset
asserts. To use the watchdog function, connect WDI to
a bus line or µP I/O line. A change of state (high to low,
low to high, or a minimum 100ns pulse) resets the
watchdog timer. If WDI remains high or low for longer
than the watchdog timeout period (tWD), the internal
watchdog timer runs out and a reset pulse is triggered
for the reset timeout period (tRP). The internal watchdog
timer clears whenever reset asserts or whenever WDI
sees a rising or falling edge. If WDI remains in either a
high or low state, a reset pulse asserts periodically after
every tWD (Figure 2).
BATT ON Indicator (MAX6367 Only)
BATT ON is a push-pull output that drives high when in
battery-backup mode. BATT ON typically sinks 3.2mA
at 0.1V saturation voltage. In battery-backup mode, this
terminal sources approximately 10µA from OUT. Use
BATT ON to indicate battery-switchover status or to
supply base drive to an external pass transistor for
higher current applications (Figure 3).
RESET IN Comparator (MAX6368 Only)
RESET IN is compared to an internal 1.235V reference.
If the voltage at RESET IN is less than 1.235V, reset
asserts. Use the RESET IN comparator as an undervolt-
age detector to signal a failing power supply or as a
secondary power-supply reset monitor.
To program the reset threshold (VRTH) of the secondary
power supply, use the following (see Typical Operating
Circuit):
VRTH = VREF (R1 / R2 + 1)
where VREF = 1.235V. To simplify the resistor selection,
choose a value for R2 and calculate R1:
R1 = R2 [(VRTH / VREF) - 1]
Since the input current at RESET IN is 25nA (max),
large values (up to 1MΩ) can be used for R2 with no
significant loss in accuracy. For example, in the Typical
Operating Circuit, the MAX6368 monitors two supply
voltages. To monitor the secondary 5V logic or analog
supply with a 4.60V nominal programmed reset thresh-
old, choose R2 = 100kΩ, and calculate R1 = 273kΩ.
Reset Output
A µP’s reset input starts the µP in a known state. The
MAX6365–MAX6368 µP supervisory circuits assert a
reset to prevent code-execution errors during power-
up, power-down, and brownout conditions. RESET is
guaranteed to be a logic low or logic high, depending
on the device chosen (see Ordering Information).
RESET or RESET asserts when VCC is below the reset
threshold and for at least 150ms (tRP) after VCC rises
above the reset threshold. RESET or RESET also
asserts when MR is low (MAX6365) and when RESET IN
is less than 1.235V (MAX6368). The MAX6366 watch-
dog function will cause RESET (or RESET) to assert in
pulses following a watchdog timeout (Figure 2).
Applications Information
Operation Without
a Backup Power Source
The MAX6365–MAX6368 provide battery-backup func-
tions. If a backup power source is not used, connect
BATT to GND and OUT to VCC.
Watchdog Software Considerations
One way to help the watchdog timer monitor the soft-
ware execution more closely is to set and reset the
watchdog at different points in the program rather than
pulsing the watchdog input periodically. Figure 4
shows a flow diagram in which the I/O driving the
Figure 2. MAX6366 Watchdog Timeout Period and Reset Active Time
RESET
WDI
tRP
tRP
tWD
tWD = WATCHDOG TIMEOUT PERIOD
tRP = RESET TIMEOUT PERIOD
tWD
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
______________________________________________________________________________________ 11
watchdog is set low in the beginning of the program,
set high at the beginning of every subroutine or loop,
and set low again when the program returns to the
beginning. If the program should hang in any subrou-
tine, the problem would be quickly corrected.
Replacing the Backup Battery
When VCC is above VTH, the backup power source can
be removed without danger of triggering a reset pulse.
The device does not enter battery-backup mode when
VCC stays above the reset threshold voltage.
Negative-Going VCC Transients
These supervisors are relatively immune to short-dura-
tion, negative-going VCC transients. Resetting the µP
when VCC experiences only small glitches is usually not
desirable.
The Typical Operating Characteristics section has a
Maximum Transient Duration vs. Reset Threshold
Overdrive graph for which reset is not asserted. The
graph was produced using negative-going VCC pulses,
starting at VCC and ending below the reset threshold by
the magnitude indicated (reset threshold overdrive).
The graph shows the maximum pulse width that a neg-
ative-going VCC transient can typically have without
triggering a reset pulse. As the amplitude of the tran-
sient increases (i.e., goes further below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a VCC transient that goes 100mV
below the reset threshold and lasts for 30µs will not trig-
ger a reset pulse.
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
BATT
BATT ON
OUT
CMOS RAM
0.1µF
GND RESET
CE IN
CE
RESET
CE OUT
MAX6367
VCC
A0–A15
µP
+2.4V TO +5.5V
ADDRESS
DECODE
Figure 3. MAX6367 BATT ON Driving an External Pass
Transistor
Figure 4. Watchdog Flow Diagram
START
SET
WDI
LOW
RETURN
END
SUBROUTINE
OR PROGRAM LOOP
SET WDI
HIGH
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
12 ______________________________________________________________________________________
RESET THRESHOLD RANGES (V)
SUFFIX MIN TYP MAX
46 4.50 4.63 4.75
44 4.25 4.38 4.50
31 3.00 3.08 3.15
29 2.85 2.93 3.00
26 2.55 2.63 2.70
23 2.25 2.32 2.38
PART TOP MARK PART TOP MARK PART TOP MARK
MAX6365LKA23 AAAM MAX6366PKA23 AABK MAX6367HKA23 AACI
MAX6365LKA26 AAAL MAX6366PKA26 AABJ MAX6367HKA26 AACH
MAX6365LKA29* AAAK MAX6366PKA29* AABI MAX6367HKA29 AACG
MAX6365LKA31 AAAJ MAX6366PKA31 AABH MAX6367HKA31 AACF
MAX6365LKA44 AAAI MAX6366PKA44 AABG MAX6367HKA44 AACE
MAX6365LKA46* AAAH MAX6366PKA46* AABF MAX6367HKA46* AACD
MAX6365PKA23 AAAS MAX6366HKA23 AABQ MAX6368LKA23 AACO
MAX6365PKA26 AAAR MAX6366HKA26 AABP MAX6368LKA26 AACN
MAX6365PKA29* AAAQ MAX6366HKA29 AABO MAX6368LKA29* AACM
MAX6365PKA31 AAAP MAX6366HKA31 AABN MAX6368LKA31 AACL
MAX6365PKA44 AAAO MAX6366HKA44 AABM MAX6368LKA44 AACK
MAX6365PKA46* AAAN MAX6366HKA46* AABL MAX6368LKA46* AACJ
MAX6365HKA23 AAAY MAX6367LKA23 AABW MAX6368PKA23 AACU
MAX6365HKA26 AAAX MAX6367LKA26 AABV MAX6368PKA26 AACT
MAX6365HKA29 AAAW MAX6367LKA29* AABU MAX6368PKA29* AACS
MAX6365HKA31 AAAV MAX6367LKA31 AABT MAX6368PKA31 AACR
MAX6365HKA44 AAAU MAX6367LKA44 AABS MAX6368PKA44 AACQ
MAX6365HKA46* AAAT MAX6367LKA46* AABR MAX6368PKA46* AACP
MAX6366LKA23 AABE MAX6367PKA23 AACC MAX6368HKA23 AADA
MAX6366LKA26 AABD MAX6367PKA26 AACB MAX6368HKA26 AACZ
MAX6366LKA29* AABC MAX6367PKA29* AACA MAX6368HKA29 AACY
MAX6366LKA31 AABB MAX6367PKA31 AABZ MAX6368HKA31 AACX
MAX6366LKA44 AABA MAX6367PKA44 AABY MAX6368HKA44 AACW
MAX6366LKA46* AAAZ MAX6367PKA46* AABX MAX6368HKA46* AACV
Reset Threshold Ranges
Device Marking Codes
*These standard versions are available in small quantities through Maxim Distribution. Sample stock is generally held on
standard versions only. Contact factory for availability of nonstandard versions.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
______________________________________________________________________________________ 13
Pin Configurations (continued)
OUT
VCC
WDI
1
2
8
7
CE OUT
BATTCE IN
GND
RESET, RESET
SOT23
TOP VIEW
3
4
6
5
MAX6366
OUT
VCC
BATT ON
1
2
8
7
CE OUT
BATTCE IN
GND
RESET, RESET
SOT23
3
4
6
5
MAX6367
OUT
VCC
RESET IN
1
2
8
7
CE OUT
BATTCE IN
GND
RESET, RESET
SOT23
3
4
6
5
MAX6368
Selector Guide
PART
MANUAL
RESET
INPUT
WATCH-
DOG
INPUT
BATT
ON
RESET
IN
RESET
PUSH-
PULL
RESET
OPEN-
DRAIN
RESET
OPEN-
DRAIN
CHIP-
ENABLE
GATING
MAX6365LKA__
MAX6365PKA__
MAX6365HKA__
MAX6366LKA__
MAX6366PKA__
MAX6366HKA__
MAX6367LKA__
MAX6367PKA__
MAX6367HKA__
MAX6368LKA__
MAX6368PKA__
MAX6368HKA__
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
14 ______________________________________________________________________________________
CE IN
*RESET IN APPLIES TO MAX6368 ONLY.
BATT
RESET
I/O
OUT
R1
R2
CMOS
RAM
RESET
WDI**
CE OUT
0.1µF
0.1µF
GND
MAX6366
MAX6368
VCC
ADDRESS
DECODE
REAL-
TIME
CLOCK
A0–A15
µP
+2.4V TO +5.5V
SECONDARY
DC VOLTAGE
RESET IN*
**WDI APPLIES TO MAX6366 ONLY.
CE
Typical Operating Circuit
Chip Information
TRANSISTOR COUNT: 729
PROCESS: CMOS
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
MAX6365–MAX6368
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SOT23, 8L .EPS
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
3.002.60E
C
E1
E
BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.
8. MEETS JEDEC MO178.
8
0.60
1.75
0.30
L2
0
e1
e
L
1.50E1
0.65 BSC.
1.95 REF.
0.25 BSC.
GAUGE PLANE
SEATING PLANE C
C
L
PIN 1
I.D. DOT
(SEE NOTE 6)
L
C
L
C
A2
e1
D
DETAIL "A"
5. COPLANARITY 4 MILS. MAX.
NOTE:
7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD
6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1.
4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.
3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.
HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.
2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF
1. ALL DIMENSIONS ARE IN MILLIMETERS.
L2
L
A1
A
0.45
1.30
0.15
1.45
MAX
0.28b
0.90A2
0.00A1
0.90
A
MIN
SYMBOL
3.00
0.20
2.80D
0.09
C
SEE DETAIL "A"
L
C
be
D1
21-0078 1
PACKAGE OUTLINE, SOT-23, 8L BODY
0
0
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
