REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 1 of 12
RNA51957A,B
Voltage Detecting, System Resetting IC Series REJ03D0912-0200
Rev.2.00
Mar 02, 2009
Description
RNA51957A,B are semiconductor integrated circuits for resetting of all types of logic circuits such as CPUs, and
has the feature of setting the detection voltage by adding external resistance.
They include a built-in delay circuit to provid e the desired retardation time simply by adding an external capacitor.
They fined extensive applications, including battery checking circuit, level detecting circuit and waveform shaping
circuit.
Features
• Few external parts
• Large delay time with a capacitor of small capacitance (td ≈ 100 ms, at 0.33 µF)
• Low threshold operating voltage (Supply voltage to keep low-state at low supply voltage):
0.6 V (Typ) at RL = 22 kΩ
• Wide supply voltage range: 2 V to 17 V
• Wide application range
• Ordering Information
Part Name Package Type Package Code Package
Abbreviation Taping Abbreviation
(Quantity) Surface
Treatment
RNA51957AFPH0 SOP-8 pin PRSP0008DE-C FP H (2,500 pcs / Reel) 0 (Ni/Pd/Au)
RNA51957BFPH0 SOP-8 pin PRSP0008DE-C FP H (2,500 pcs / Reel) 0 (Ni/Pd/Au)
Application
• Reset circuit of Pch, Nch, CMOS, microcomputer, CPU and MCU, Reset of logic circuit, Battery check circuit,
switching circuit back-up voltage, level detecting circuit, waveform shaping circuit, delay waveform generating
circuit, DC/DC converter, over voltage protection circuit
Recommended Operating Condition
• Supply voltage range: 2 V to 17 V
Outline and Article Indication
• RNA51957A, B
Y : Year Code
(the last digit of year)
M : Month Code
W : Week Code
C : Control Code
Lot No.
Trace Code
Pin No.1
SOP-8
R 9 5 7 B
YMWC
CCC
Type No.
R 9 5 7 A
YMWC
CCC
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 2 of 12
Pin Arrangement
RNA51957AFP/BFP
8
5
6
7
NC
Delay capacito
r
NC: No Connection
Output
Power-supply
NC
GND
NC
Input
1
4
3
2
(Top view)
Outline: PRSP0008DE-C
Block Diagram
GND
Output
Delay capacitor
–
+–
25µA
Typ
5µA
Typ
A: Built-in Load
B: Open Collector
RNA51957A, B
Input
1.25V
Power-
supply
Operating Waveform
RNA51957A, B
1.25V
Input voltageOutput state
H
L
t
t
td ≈ 0.34 × Cd(pF) µs
td td
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 3 of 12
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item Symbol Ratings Unit Conditions
Supply voltage VCC 18 V
Output sink current Isink 6 mA
VCC Type A (output with constant current load)
Output voltage VO 18 V Type B (open collector output)
Power dissipation Pd 400 mW 8-pin SOP (PRSP0008DE-C)
Thermal derating Kθ 4.4 mW/°C Refer to the
thermal derating
curve. 8-pin SOP (PRSP0008DE-C)
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
–0.3 to VCC V
CC ≤ 7 V
Input voltage range VIN –0.3 to +7 V VCC > 7 V
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
• “L” reset type
Item Symbol Min Typ Max Unit Test Conditions
Detecting voltage VS 1.20 1.25 1.30 V
Hysteresis voltage ∆VS 9 15 23 mV VCC = 5V
Detecting voltage
temperature coefficient VS/∆T — 0.01 — %/°C
Supply voltage range VCC 2 — 17 V
–0.3 — VCC VCC ≤ 7V
Input voltage range Vin –0.3 — 7.0 V VCC > 7V
Input current IIN — 100 500 nA VIN = 1.25V
— 390 590 Type A, VCC = 5V
Circuit current ICC — 360 540 µA Type B, VCC = 5V
Delay time tpd 1.6 3.4 7.0 ms Cd = 0.01µF *
Output saturation
voltage Vsat — 0.2 0.4 V L reset type, VCC = 5V, VIN < 1.2V, Isink = 4mA
— 0.67 0.8 RL = 2.2kΩ, Vsat ≤ 0.4V
Threshold operating
voltage VOPL — 0.55 0.7 V L reset type minimum supply
voltage for IC operation RL = 100kΩ, Vsat ≤ 0.4V
Output leakage
current IOH — — 30 nA Type B
Output load current IOC –40 –25 –17 µA Type A, VCC = 5V, VO = 1/2 × VCC
Output high voltage VOH V
CC–0.2 VCC–0.06 — V Type A
Note: Please set the desired delay time by attaching capacitor of the range between 4700 pF and 10 µF.
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 4 of 12
Typical Characteristics
250
0
50
100
150
200
1.28
1.22
–40 0–20 20 40 8060 100
1.23
1.24
1.25
1.26
1.27
1.28
1.22
1.23
1.24
1.25
1.26
1.27
V
SH
V
SL
V
IN
= 1.25V
0 4 8 12 16 20 048121620
V
SH
V
SL
Ta = –40°C
Ta = 85°C
Ta = 25°C
–40 0–20 20 40 8060 100
6
0
3
2
1
5
4
V
CC
= 5V
10V
V
CC
= 15V
0.1 3 5 7 3 5 735711073 5 100 1000
10
7
5
3
7
5
3
7
5
3
7
5
3
0.001
0.1
0.01
1
V
CC
= 5V C
D
= 0.01µF
Supply Voltage VCC (V) Supply Voltage VCC (V)
Ambient Temperature Ta (°C)
Delay Time tpd (ms) Input Current IIN (nA)
Detection Voltage VS (V)
Detection Voltage vs. Ambient Temperature
Detection Voltage vs. Supply Voltage Input Current vs. Supply Voltage
Ambient Temperature Ta (°C)
Detection Voltage VS (V)
Delay Time vs. Ambient Temperature
Delay Time tpd (ms)
Delay Capacitance Cd (µF)
Delay Capacitance vs. Delay Time
500
00255075
85 100 125
100
200
300
400
Thermal Derating
Ambient Temperature Ta (°C)
Power Dissipation Pd (mW)
8-pin SOP
(PRSP0008DE-C)
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 5 of 12
1.0
00 0.2 0.4 0.6 0.8 1.0
0.2
0.4
0.6
0.8
Ta = 25°C
R
L
= 2.2kΩ
R
L
= 22kΩ
R
L
= 100kΩ
–40 0–20 20 40 8060 100
–12
0
–4
–8
–6
–2
–10
V
CC
= 5V
V
CC
= 15V
0.3
0021 3456
0.1
0.2
V
CC
= 5V V
CC
= 15VV
CC
= 10V
00 4 8 12 16
–10
–20
–30
–40
00481216
200
400
600
800
Ta = –40°C
Ta = 25°C
Ta = 85°C
Supply Voltage VCC (V)
Threshold Operating Voltage
Output Voltage V
OUT
(V)
Supply Voltage V
CC
(V)
Output Load Current vs. Output Voltage
(RNA51957A)
Output Voltage V
O
(V)
Output Load Current I
CC
(µA)
Circuit Current vs. Supply Voltage
(RNA51957B)
Circuit Current I
CC
(µA)
Output Sink Current Isink (mA)
Output Saturation Voltage Vsat (V)
Output Saturation Voltage vs. Output Sink Current
Supply voltage detecting "L" reset type
: VCC = 4V
Except above mentioned
: VCC = 5V
Ambient Temperature Ta (°C)
Canstant Current at Cd pin Ipd (µA)
Canstant Current at Cd pin vs. Ambient Temperature
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 6 of 12
Example of Application Circuit
Reset Circuit of RNA51957
RL
VCC
R1
R2
RNA51957x RESET
Logic circuit
Input
GND GNDDelay capacitor
Cd
Power-
supply
Power-
supply
Output
Figure 1 Reset Circuit of RNA51957
Notes: 1. When the detecting supply voltage is 4.25 V, RNA51953 are used. In this case, R1 and R2 are not necessary.
When the voltage is anything except 4.25 V, RNA51957 and RNA51958 are used. In thi s case, the detect ing
supply voltage is 1.25 × (R1 +R2)/R2 (V) approximately.
The detecting supply voltage can be set between 2 V and 15 V.
2. If a longer delay time is necessary, RNA51953, RNA51957, RNA51958 are used. In this case, the delay
time is about 0.34 × Cd (pF) µs.
3. If the RNA51957 and the logic circuit share a common power source, type A (built-in load type) can be used
whether a pull-up resistor is included in the logic circuit or not.
4. The logic circuit preferably should not have a pull -down resist or, but i f one i s present, add load resi st or R L to
overcome the pull-down resistor.
5. When the reset terminal in the logic circuit is of the low reset type, RNA51953 and RNA51957 are used and
when the terminal is of the high reset type, RNA51958 are used.
6. When a negative supply voltage is used, the supply voltage side of RNA51957 and the GND side are
connected to negative supply voltage respectively.
Case of Using Reset Signal except Supply Voltage in the RNA51957
(a) Reset at ON (b) Reset at transistor ON
Input
R
L
V
CC
RESET
Logic circuit
Input
GND Delay capacitor GND
Cd
R
1
R
2
R
L
V
CC
RESET
Logic circuit
GND Delay capacitor GND
Cd
R
1
R
2
Out
put
Out
put
RNA51957x RNA51957x
Control
signal
Power-
supply
Power-
supply
Power-
supply
Power-
supply
Figure 2 Case of Using Reset Signal except Supply Voltage in the RNA51957
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 7 of 12
Delay Waveform Generating Circuit
When RNA51957 are used, a waveform with a large delay time can generate only by adding a small capacitor.
Power-supply
RNA51957
GND Delay capacito
r
Cd
R
1
R
2
OutputInput
Figure 3 Delay Waveform Generating Circuit
Operating Waveform
Output
td
Input
(V
CC
partial
pressure)
td ≈ 0.34 × Cd(pF) µs
Figure 4 Operating Waveform
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 8 of 12
Notice for use
About the Power Supply Line
1. About bypass capacitor
Because the ripple and the spike of the high frequency noise and the low frequency are superimposed to the power
supply line, it is necessary to remove these.
Therefore, please install C1 and C2 for the low frequency and for the high frequency between the power supply line
and the GND line as shown in following figure 5.
Power-supply
Output
R
1
V
CC
R
2
Vin RNA51957
Input
GND
C
2
C
1
+
Delay capacito
r
Cd
Example of ripple
noise measures
Figure 5 Example of Ripple Noise Measures
2. The sequence of voltage impression
Please do not impress the voltages to the input terminals earlier than the power supply terminal. Moreover, please
do not open the power supply terminal with the voltage impressed to the input terminal.
(The setting of the bias o f an internal circuit collapses, and a parasitic element might operate.)
About the Input Terminal
1. Setting range of input voltage
The following voltage is recommended to be input to the input terminal (pin 2).
about 0.8 (V) < Vin < VCC – 0.3 (V) ... at VCC ≤ 7 V
about 0.8 (V) < Vin < 6.7 (V) ............. at VCC > 7 V
2. About using input terminal
Please do an enough verification to the transition characteristic etc. of the power supply when using independent
power supply to input terminal (pin 2).
Power-supply
Output
Vin RNA51957
Input
GND
V
CC
Delay capacitor
Cd
Vin is decided to the V
CC
subordinating,
and operates in the range
about 0.8 (V) < Vin < V
CC
– 0.3 (V).
Figure 6 Recommended Example
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 9 of 12
Power-supply
Output
Vin RNA51957
Input
GND
V
CC
1 V
CC
2
Independent
Delay capacitor
Cd
Independent Power-supply
Output
RNA51957
Input
GND
V
CC
Vin
GND
V
CC
Delay capacito
r
Cd
Example 1. Independent power supply system
Please do enough verifying about
transition characteristic of V
CC
1
and V
CC
2.
Example 2. Logic pulse input
(not recommended)
Figure 7
3. Calculation of detecting voltage
Detecting voltage Vs can be calculated by the following expression.
However, the error margin is caused in the detecting voltage because input current Iin (standard 100 nA) exists if it
sets too big resistance.
Please set the constant to disregard this error margin.
VS = 1.25 ×+ Iin × R1
error margin
R1 + R2
R2
Power-supply
Output
Vin
Iin
→RNA51957
GND
Input
V
CC
R
1
R
2
Delay capacito
r
Cd
Figure 8 Influence of Input Current
4. About the voltage input outside ratings
Please do not input the voltage outside ratings to the input terminal.
An internal protection diode becomes order bias, and a large current flows.
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 10 of 12
Setting of Delay Capacity
Please use capacitor Cd for the delay within the range of 10 µF or less.
When a value that is bigger than this is set, the p roblem such as following (1), (2), and (3) becomes remarkable.
t
V
CC
Output
tpd
tPHL
Figure 9 Time Chart at Momentary Voltage-Decrease
(1) The difference at delay time becomes remarkable.
A long delay setting of tens of seconds is fundamentally possible. However, when set delay time is lengthened, the
range of the difference relatively grows, too. When a set value is assumed to be ‘tpd’, the difference occurs in the
range from 0.47 × tpd to 2.05 × tpd. For instance, 34 seconds can be calculated at 100 µF. However, it is likely to
vary within the ranges of 16-70 seconds.
(2) Difficulty to react to a momentary voltage decrease.
For example, the reaction time tPHL is 10 µs when delay capacitor Cd = 0.1 µF.
The momentary voltage-decrease that is longer than such tPHL are occurs, the detection becomes possible. When the
delay capacitance is enlarged, tPHL also becomes long. For instance, it becomes about 100 to 200 µs in case of
circuit constant C1 = 100 µF.
(Characteristic graph 1 is used and extrapolation in case of Cd = 100 µF.)
Therefore, it doesn't react to momentary voltage-decrease that is shorter than this.
(3) Original delay time is not obtained.
When the momentary voltage-decrease time ‘t’ is equivalent to tPHL, the discharge becomes insufficient and the
charge starts at that state. This phenomenon occurs at large capacitance. And, original delay time tpd is not
obtained.
Please refer to characteristic graph 2. (Delay time versus input pulse width)
0.01 0.1 1
Delay Capacitance Cd (µF)
10 100
1000
1
10
100
200
1 10 100
Pulse Width (µs)
Characteristic Graph 2
Delay Time vs. Momentary Voltage Decrease Pulse Width
(Example data)
Characteristic Graph 1
Reaction Time vs. Delay Capacitance
(Example data)
Delay Time tpd (ms)
Reaction Time tPHL (µs)
1000 10000
10000
1000
100
10
1
0.01µF
Delay Capacitance
0.033µF
0.1µF
0.33µF
1µF
2.2µF
3.3µF
Figure 10 Characteristic Graph
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 11 of 12
Setting of Output Load Resistance (RNA51957B)
High level output voltage can be set without depending on the power-supply voltage because the output terminal is an
open collector type. However, please guard the following notes.
1. Please set it in value (2 V to 17 V) within the range of the power-supply voltage recommendation.
Moreover, please never impress the voltage of maximum ratings 18 V or more even momentarily either.
2. Please set output load resistance (pull-up resistance) RL so that the output current (output inflow current IL) at L
level may become 4 mA or less. Moreover, please never exceed absolute maximum rating (6 mA).
V
CC
(2V to 17V)
I
L
≤ 4mA
6
R
L
Figure 11 Output Load Resistance RL
Others
1. Notes when IC is handled are published in our reliability handbook, and please refer it.
The reliability handbook can be downloaded from our homepage (following URL).
http://www.renesas.com/fmwk.jsp?cnt=reliability_root.jsp&fp=/products/common_info/reliability
2. Additionally, please inquire of our company when there is an uncertain point on use.
RNA51957A,B
REJ03D0912-0200 Rev.2.00 Mar 02, 2009
Page 12 of 12
Package Dimensions
A
L
e
c
1
b
1
D
E
A
2
b
p
c
θ
x
y
H
E
Z
L
1
4.854.65
0.90
0.12
0° 8°
6.2
0.15 0.20 0.25
1.12 1.42
0.46
0.00 0.1 0.20
4.4
1.85
4.64.2
0.25 0.45 0.65
2.03
Reference
Symbol
Dimension in Millimeters
Min Nom Max
5.05
A
1
0.34 0.4
6.55.7
1.27
0.10
0.75
58
4
F
*1
*2
*3
p
Mx
y
1
Index mark
E
A
Zb
E
H
D
p
Terminal cross section
( Ni/Pd/Au plating )
c
b
1
Detail F
A
θ
2
A
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
P-SOP8-4.4x4.85-1.27 0.1g
MASS[Typ.]
—PRSP0008DE-C
RENESAS CodeJEITA Package Code Previous Code
1
L
L
Notes:
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