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LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

LMH6629 Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown

1 Features 3 Description

The LMH6629 is a high-speed, ultra-low noise

1• Specified for VS=5V,RL= 100 Ω, AV= 10V/V amplifier designed for applications requiring wide

WSON-8 Package, unless Specified. –3dB bandwidth with high gain and low noise such as in

Bandwidth 900 MHz communication, test and measurement, optical and

• Input Voltage Noise 0.69 nV/√Hz ultrasound systems.

• Input Offset Voltage Max. Over Temperature ±0.8 The LMH6629 operates on 2.7-V to 5.5-V supply with

mV an input common mode range that extends below

• Slew Rate 1600 V/ μsground and outputs that swing to within 0.8 V of the

rails for ease of use in single supply applications.

• HD2 @ f = 1 MHz, 2VPP −90 dBc Heavy loads up to ±250 mA can be driven by high-

• HD3 @ f = 1 MHz, 2VPP −94 dBc frequency large signals with the LMH6629's –3dB

• Supply Voltage Range 2.7 V to 5.5 V bandwidth of 900 MHz and 1600 V/µs slew rate. The

LMH6629 (WSON-8 package only) has user-

• Typical Supply Current 15.5 mA selectable internal compensation for minimum gains

• Selectable Min. Gain ≥4 or ≥10 V/V of 4 or 10 controlled by pulling the COMP pin low or

• Enable Time: 75 ns high, thereby avoiding the need for external

• Output Current ±250 mA compensation capacitors required in competitive

devices. Compensation for the SOT-23-5 package is

• WSON-8 and SOT-23-5 Packages internally set for a minimum stable gain of 10 V/V.

The WSON-8 package also provides the power-down

2 Applications enable/disable feature.

• Instrumentation Amplifiers The low-input noise (0.69 nV/√Hz and 2.6 pA/√Hz),

• Ultrasound Pre-amps low distortion (HD2/HD3 = −90 dBc/−94 dBc) and

• Wide-band Active Filters ultra-low DC errors (800 µV VOS maximum over

temperature, ±0.45 µV/°C drift) allow precision

• Opto-Electronics operation in both ac- and dc-coupled applications.

• Medical Imaging Systems The LMH6629 is fabricated in Texas Instruments'

• Base-Station Amplifiers proprietary SiGe process and is available in a 3 mm ×

• Low-Noise Single Ended to Differential 3 mm 8-pin WSON package as well as the SOT-23-5

Conversion package.

• Trans-Impedance Amplifier Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SOT-23 (5) 2.90 mm × 1.60 mm

LMH6629 WSON (8) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Transimpedance Amplifier

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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Table of Contents

7.3 Feature Description................................................. 20

1 Features.................................................................. 17.4 Device Functional Modes........................................ 31

2 Applications ........................................................... 18 Application and Implementation ........................ 32

3 Description............................................................. 18.1 Application Information............................................ 32

4 Revision History..................................................... 28.2 Typical Application.................................................. 32

5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 34

6 Specifications......................................................... 410 Layout................................................................... 35

6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 35

6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 36

6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 38

6.4 Thermal Information.................................................. 411.1 Documentation Support ........................................ 38

6.5 Electrical Characteristics 5V .................................... 511.2 Trademarks........................................................... 38

6.6 Electrical Characteristics 3.3V ................................. 811.3 Electrostatic Discharge Caution............................ 38

6.7 Typical Performance Characteristics ...................... 11 11.4 Glossary................................................................ 38

7 Detailed Description............................................ 19 12 Mechanical, Packaging, and Orderable

7.1 Overview................................................................. 19 Information........................................................... 38

7.2 Functional Block Diagram....................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (October 2014) to Revision I Page

• Updated ESD Ratings table. .................................................................................................................................................. 4

• Revised paragraph beginning with "The optimum value of "CFin the Low-Noise Transimpedance Amplifier section........ 29

• Updated Related Documentation section............................................................................................................................. 38

Changes from Revision G (March 2013) to Revision H Page

• Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions,

Application and Implementation;Power Supply Recommendations;Layout;Device and Documentation Support;

Mechanical, Packaging, and Ordering Information................................................................................................................. 1

Changes from Revision F (March 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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OUT

COMP

IN+

IN-

V-

V+

V-

DAP

OUT

V-

+IN

V+

-IN

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

5 Pin Configuration and Functions

5-Pin 8-Pin

Package DBV Package NGQ08A

Top View Top View

Pin Functions

NUMBER

NAME I/O DESCRIPTION

DBV NGQ08A

COMP 6 I Compensation

FB 2 I/O Feedback

-IN 4 3 I Inverting input

+IN 3 4 I Non-inverting input

OUT 1 7 O Output

PD 1 I Power Down

V-2 5 I Negative supply

V+5 8 I Positive supply

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3)

MIN MAX UNIT

Positive Supply Voltage −0.5 6.0 V

Differential Input Voltage 3 V

Input current ±10 mA

Analog Input Voltage −0.5 to VSV

Digital Input Voltage −0.5 to VSV

Junction Temperature +150 °C

Storage Temperature (Tstg)−65 +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under

conditions of internal self-heating where TJ> TA.

6.2 ESD Ratings VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

Machine model ±200

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22- ±750

C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)

MIN NOM MAX UNIT

Supply Voltage (V+- V−) 2.7 5.5 V

Operating Temperature Range −40 +125 °C

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the Electrical Characteristics.

6.4 Thermal Information DBV NGQ08A

THERMAL METRIC(1) UNIT

5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 179 71 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics 5V

The following specifications apply for single supply with VS= 5 V, RL= 100 Ωterminated to 2.5 V, gain = 10V/V, VO= 2VPP,

VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

DYNAMIC PERFORMANCE

VO= 200 mVPP, WSON-8 package 900

Small Signal VO= 200 mVPP, SOT-23-5 package 1000

SSBW MHz

−3dB bandwidth AV= 4, VO= 200 mVPP,800

COMP Pin = LO

VO= 2VPP 380

Large signal −3dB

LSBW MHz

bandwidth COMP Pin = LO, AV= 4, VO= 2VPP 190

AV= 10, VO= 200 mVPP, WSON-8 package 330

AV= 10, VO= 200 mVPP, SOT-23-5 package 190

0.1 dB bandwidth MHz

AV= 4, VO= 200 mVPP,95

COMP Pin = LO

VO= 200 mVPP, WSON-8 package 0

Peaking dB

VO= 200 mVPP, SOT-23-5 package 2

AV= 10, 2 V step 1600

SR Slew rate V/μs

AV= 4, 2 V step, COMP Pin = LO 530

AV= 10, 2 V step, 10% to 90%, 0.90

WSON-8 package

AV= 10, 2 V step, 10% to 90%,

tr/ tfRise/fall time 0.95

SOT-23-5 package

AV= 4, 2 V step, 10% to 90%, ns

2.8

COMP Pin = LO, (Slew Rate Limited)

TsSettling time AV= 10, 1 V step, ±0.1% 42

Overload VIN = 1 VPP 2

recovery

NOISE and DISTORTION

fc = 1 MHz, VO= 2 VPP −90

COMP Pin = LO, AV= 4, fc = 1 MHz, −88

VO= 2 VPP

2nd Order

HD2 dBc

distortion fc = 10 MHz, VO= 2 VPP −70

COMP Pin = LO, fc = 10 MHz, −65

AV= 4 V, VO= 2 VPP

fc = 1 MHz, VO= 2VPP −94

COMP Pin = LO, AV= 4, −87

3rd Order fc = 1 MHz, VO= 2 VPP

HD3 dBc

distortion fc = 10 MHz, VO= 2 VPP −82

COMP Pin = LO, fc = 10 MHz, VO= 2VPP −75

Two-tone 3rd fc = 25 MHz, VO= 2 VPP composite 31

OIP3 order intercept dBm

fc = 75 MHz, VO= 2 VPP composite 27

point

enNoise voltage 0.69 nV/√Hz

Input referred f > 1MHz

inNoise current 2.6 pA/√Hz

NF Noise figure RS= RT= 50 Ω8.0 dB

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under

conditions of internal self-heating where TJ> TA.

(2) All limits are ensured by testing or statistical analysis

(3) Typical numbers are the most likely parametric norm.

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Electrical Characteristics 5V (continued)

The following specifications apply for single supply with VS= 5 V, RL= 100 Ωterminated to 2.5 V, gain = 10V/V, VO= 2VPP,

VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

ANALOG I/O

CMRR > 70 dB, WSON-8 package −0.30 3.8

Input voltage

CMVR V

range CMRR > 70 dB, SOT-23-5 package −0.30 to 3.8

0.89 0.82 to 4.19 4.0

RL= 100 Ωto VS/2 -40°C ≤TJ≤+125°C 0.95 3.9

Output voltage

VOV

range 0.76 0.72 to 4.28 4.1

No Load -40°C ≤TJ≤+125°C 0.85 4.0

Linear output

IOUT VO= 2.5 V (4) 250 mA

current ±150 ±780

Input offset

VOS µV

voltage -40°C ≤TJ≤+125°C ±800

Input offset

TcVOS voltage See (5) ±0.45 μV/°C

temperature drift

−15 −23

IBI Input bias current See (6) μA

-40°C ≤TJ≤+125°C −37

±0.1 ±1.8

Input offset

IOS μA

current -40°C ≤TJ≤+125°C ±3.0

Input offset

TCIOS voltage See (5) ±2.8 nA/°C

temperature drift

CCM Common Mode 1.7

Input capacitance pF

CDIFF Differential Mode(7) 4

RCM Input resistance Common Mode 450 kΩ

MISCELLANEOUS PARAMETERS

82 87

VCM from 0 V to 3.7 V, WSON-8

Common mode package

CMRR -40°C ≤TJ≤+125°C 70

rejection ratio VCM from 0 V to 3.7 V, SOT-23-5 package 87

81 83

Power supply

PSRR dB

rejection ratio -40°C ≤TJ≤+125°C 78

74 78

WSON-8 package

AVOL Open loop gain -40°C ≤TJ≤+125°C 72

SOT-23-5 package 78

(4) The maximum continuous output current (IOUT) is determined by device power dissipation limitations. Continuous short circuit operation

at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C

(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(6) Negative input current implies current flowing out of the device

(7) Simulation results.

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

Electrical Characteristics 5V (continued)

The following specifications apply for single supply with VS= 5 V, RL= 100 Ωterminated to 2.5 V, gain = 10V/V, VO= 2VPP,

VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

DIGITAL INPUTS/TIMING

Logic low-voltage

VIL PD and COMP pins, WSON-8 package 0.8

threshold V

Logic high-voltage

VIH PD and COMP pins, WSON-8 package 2.5

threshold

−23 −28 −34

Logic Low-bias PD and COMP pins = 0.8 V,

IIL current WSON-8 package(6) -40°C ≤TJ≤+125°C −19 −38 µA

−16 −22 −27

Logic High-bias PD and COMP pins = 2.5 V,

IIH current WSON-8 package(6) -40°C ≤TJ≤+125°C −14 −29

Ten Enable time 75

WSON-8 package ns

Tdis Disable time 80

POWER REQUIREMENTS

No Load, Normal Operation (PD 15.5 16.7

Pin = HI or open for WSON-8 -40°C ≤TJ≤+125°C 18.2

package)

ISSupply current mA

1.1 1.85

No Load, Shutdown (PD Pin =LO

for WSON-8 package) -40°C ≤TJ≤+125°C 2.0

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6.6 Electrical Characteristics 3.3V

The following specifications apply for single supply with VS= 3.3 V, RL= 100 Ωterminated to 1.65 V, gain = 10V/V, VO= 1

VPP, VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

DYNAMIC PERFORMANCE

VO= 200 mVPP, WSON-8 package 820

Small signal −3dB VO= 200 mVPP, SOT-23-5 package 950

SSBW MHz

bandwidth COMP Pin = LO, AV= 4, 730

VO= 200 mVPP

VO= 1VPP 540

Large signal −3dB

LSBW MHz

bandwidth COMP Pin = LO, AV= 4, VO= 1VPP 320

AV= 10, VO= 200 mVPP,330

WSON-8 package

AV= 10, VO= 200 mVPP,

0.1 dB Bandwidth 190 MHz

SOT-23-5 package

COMP Pin = LO, AV= 4, 85

VO= 200 mVPP

VO= 200 mVPP, WSON-8 package 0

Peaking dB

VO= 200 mVPP, SOT-23-5 package 1.8

AV= 10, 1.3V step 1100

SR Slew rate V/µs

COMP Pin = LO, AV= 4, 1.3V step 500

AV= 10, 1V step, 10% to 90%, 0.7

WSON-8 package

AV= 10, 1V step, 10% to 90%,

tr/ tfRise/fall time 0.55

SOT-23-5 package

AV= 4, COMP Pin = LO, 1V step, 10% to 90% (Slew Rate ns

1.3

Limited)

TsSettling time AV= 10, 1V step, ±0.1% 70

Overload VIN = 1VPP 2

recovery

NOISE and DISTORTION

fc = 1MHz, VO= 1VPP -82

COMP Pin = LO, AV= 4, -88

fc = 1MHz, VO= 1VPP

2nd Order

HD2 dBc

distortion fc = 10 MHz, VO= 1VPP -67

COMP Pin = LO, fc = 10 MHz, -74

AV= 4V, VO= 1VPP

fc = 1MHz, VO= 1VPP -94

COMP Pin = LO, AV= 4, -112

fc = 1MHz, VO= 1VPP

3rd Order

HD3 dBc

distortion fc = 10 MHz, VO= 1VPP -79

COMP pin = LO, fc = 10 MHz, -96

VO= 1VPP

Two-tone 3rd fc = 25 MHz, VO= 1VPP composite 30

OIP3 order intercept dBm

fc = 75 MHz, VO= 1VPP composite 26

point

enNoise voltage 0.69 nV/√Hz

Input referred, f > 1MHz

inNoise current 2.6 pA/√Hz

NF Noise figure RS= RT= 50 Ω8.0 dB

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under

conditions of internal self-heating where TJ> TA.

(2) All limits are ensured by testing or statistical analysis.

(3) Typical numbers are the most likely parametric norm.

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Electrical Characteristics 3.3V (continued)

The following specifications apply for single supply with VS= 3.3 V, RL= 100 Ωterminated to 1.65 V, gain = 10V/V, VO= 1

VPP, VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

ANALOG I/O

CMRR > 70 dB, WSON-8 package -0.30 2.1

Input voltage

CMVR range CMRR > 70 dB, SOT-23-5 package -0.30 to 2.1

0.90 0.79 to 2.50 2.4 V

RL= 100 Ωto VS/2 -40°C ≤TJ≤+125°C 0.95 2.3

Output voltage

VOrange 0.76 0.70 to 2.60 2.5

No load -40°C ≤TJ≤+125°C 0.80 2.4

Linear output

IOUT VO= 1.65 V(4) 230 mA

current ±150 ±680 µV

Input offset

VOS voltage -40°C ≤TJ≤+125°C ±700

Input offset

TcVOS voltage See (5) ±1 µV/°C

temperature drift -15 -23

IBI Input bias current See (6) -40°C ≤TJ≤+125°C -35 µA

±0.13 ±1.8

Input offset

IOS current -40°C ≤TJ≤+125°C ±3.0

Input offset

TCIOS voltage See (5) ±3.2 nA/°C

temperature drift

CCM Common Mode 1.7

Input capacitance pF

CDIFF Differential Mode(7) 4

RCM Input resistance Common Mode 1 MΩ

MISCELLANEOUS PARAMETERS

84 87

VCM from 0 V to 2.0 V, WSON-8

package

Common mode -40°C ≤TJ≤+125°C 81

CMRR rejection ratio VCM from 0 V to 2.0 V, 87

SOT-23-5 package 82 84

Power supply dB

PSRR rejection ratio -40°C ≤TJ≤+125°C 79

78 79

WSON-8 package

AVOL Open loop gain -40°C ≤TJ≤+125°C 73

SOT-23-5 package 79

(4) The maximum continuous output current (IOUT) is determined by device power dissipation limitations. Continuous short circuit operation

at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C

(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(6) Negative input current implies current flowing out of the device.

(7) Simulation results.

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Electrical Characteristics 3.3V (continued)

The following specifications apply for single supply with VS= 3.3 V, RL= 100 Ωterminated to 1.65 V, gain = 10V/V, VO= 1

VPP, VCM = VS/2, COMP Pin = HI (WSON-8 package), unless otherwise noted.(1)

TA= 25°C

PARAMETER TEST CONDITIONS UNIT

MIN(2) TYP(3) MAX(2)

DIGITAL INPUTS/TIMING

Logic low-voltage

VIL 0.8

threshold PD and COMP pins, WSON-8 package V

Logic high-voltage

VIH 2.0

threshold -17 -23 -28

Logic low-bias PD and COMP pins = 0.8 V,

IIL current WSON-8 package(6) -40°C ≤TJ≤+125°C -14 -32 µA

-16 -22 -27

Logic high-bias PD and COMP pins = 2.0 V,

IIH current WSON-8 package(6) -40°C ≤TJ≤+125°C -13 -31

Ten Enable time 75

WSON-8 package ns

Tdis Disable time 80

POWER REQUIREMENTS

No Load, Normal Operation (PD 13.7 14.9

Pin = HI or open for WSON-8 -40°C ≤TJ≤+125°C 16.0

package)

ISSupply current mA

0.89 1.4

No Load, Shutdown (PD Pin = LO

for WSON-8 package) -40°C ≤TJ≤+125°C 1.5

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100k 1M 10M 100M 1G 10G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

Av = 100 V/V

Av = 30 V/V

Av = 4 V/V

(COMP Pin = LO)

Av = 10 V/V

100k 1M 10M 100M 1G 10G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Av = 80 V/V

Av = 115 V/V

Av = 35 V/V

Av = 10 V/V

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Av = 200 V/V

Av = 100 V/V

Av = 30 V/V

Av = 4 V/V

Av = 10 V/V

(COMP Pin = LO)

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Av = 200 V/V

Av = 100 V/V

Av = 30 V/V

Av = 10 V/V

(COMP Pin = LO)

Av = 4 V/V

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Av = 100 V/V

Av = -60 V/V

Av = -40 V/V

Av = -20 V/V

Av = -4 V/V

(COMP Pin = LO)

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

(COMP Pin = LO)

Av = 100 V/V

Av = -60 V/V

Av = -40 V/V

Av = -20 V/V

Av = -4 V/V

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6.7 Typical Performance Characteristics

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

Vo = 2 Vpp Vo = 1 Vpp Vs = ±1.5V

Figure 1. Inverting Frequency Response Figure 2. Inverting Frequency Response

Vo = 2 Vpp Vo = 1 Vpp Vs = ±1.5 V

Figure 3. Non-Inverting Frequency Response Figure 4. Non-Inverting Frequency Response

Vo = 0.2 Vpp

Figure 6. Non-Inverting Frequency Response,

Figure 5. Non-Inverting Frequency Response, SOT-23-5 Package

WSON-8 Package

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0.1 1 10 100 1,000

f (MHz)

Normalized Gain (dB)

-2

-4

-6

-8

-10

-12

Vo = 80 mVpp

Vo = 0.8 Vpp

0.1 1 10 100 1,000

f (MHz)

Normalized Gain (dB)

-2

-4

-6

-8

-10

-12

Vo = 80 mVpp

Vo = 0.8 Vpp

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Vo = 0.2 Vpp

Vo = 1 Vpp

Vo = 0.2 Vpp

Vo = 1 Vpp

f (Hz)

Normalized Gain (dB)

100k

-5 1M 10M 100M 1G 10G

-4

-3

-2

-1

100k 1M 10M 100M 1G

f (Hz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

Vo = 0.2 Vpp

Vo = 2 Vpp

100k 1M 10M 100M 1G 10G

-1

-2

-3

-4

-5

Vo = 0.2 Vpp

Vo = 2 Vpp

f (Hz)

Normalized Gain (dB)

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

Av=10 V/V

Av = 10 V/V

Figure 8. Non-Inverting Frequency Response

Figure 7. Non-Inverting Frequency Response with Varying VO, SOT-23-5 Package

with Varying VO, WSON-8 Package

Av=10 V/V Vs= +/-1.5 V

Av = 10 V/V Vs = +/-1.5 V

Figure 10. Non-Inverting Frequency Response

Figure 9. Non-Inverting Frequency Response with Varying VO, SOT-23-5 Package

with Varying VO, WSON-8 Package

Av = 4 V/V COMP Pin = LO Av = 4 V/V Vs = ±1.5 V COMP Pin = LO

Figure 11. Non-Inverting Frequency Response Figure 12. Non-Inverting Frequency Response

with Varying VO, WSON-8 Package with Varying VO, WSON-8 Package

Product Folder Links: LMH6629

f (Hz)

Normalized Gain (dB)

-2

-4

-6

-8

100k 1M 10M 100M 1G

1.5 k:

750 :

240 :

511 :

f (Hz)

Normalized Gain (dB)

1.5 kÖ

750 Ö

240 Ö1 kÖ

100M 1G10M1M100k

-8

-6

-4

-2

f (Hz)

Normalized Gain (dB)

-2

-4

-6

-8

100k 1M 10M 100M 1G

1.5 k:

750 :

1 k:

240 :

f (Hz)

Normalized Gain (dB)

750 Ö

1 kÖ

240 Ö

100M 1G10M1M100k

-8

-6

-4

-2

21.5 kÖ

10 100 1,000

f (MHz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

-6

-7

-8

10 pF, Riso = 40 :

4.7 pF, Riso = 72 :

33 pF, Riso = 17 :

10 100 1,000

f (MHz)

Normalized Gain (dB)

-1

-2

-3

-4

-5

-6

-7

-8

33 pF, Riso = 17 :

4.7 pF, Riso = 72 :

10 pF, Riso = 40 :

LMH6629

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

RL= 100 Ω|| CLRL= 100 Ω|| CL, AV= 4 V/V

RISO as noted (measured @ CL) COMP Pin = LO

RISO as noted (measured @ CL)

Figure 13. Frequency Response with Cap. Loading Figure 14. Frequency Response Cap. Loading,

WSON-8 Package

Figure 16. Frequency Response vs. Rf, SOT-23-5 Package

Figure 15. Frequency Response vs. Rf, WSON-8 Package

VS= ± 1.5 V VO= 1 VPP

VS= ±1.5 V VO= 1 VPP

Figure 18. Frequency Response vs. Rf, SOT-23-5 Package

Figure 17. Frequency Response vs. Rf, WSON-8 Package

Product Folder Links: LMH6629

0 20 40 60 80 100

Av (V/V)

HD (dBc)

-65

-70

-75

-80

-85

-90

-95

HD2

HD3

0 20 40 60 80 100

Av (V/V)

HD (dBc)

-60

-65

-70

-75

-80

-85

-90

-95

HD2

HD3

1.0 1.5 2.0 2.5 3.0

Vo (Vpp)

HD (dBc)

-85

-90

-95

-100

HD2

HD3

1.0 1.5 2.0 2.5 3.0

Vo (Vpp)

HD (dBc)

-80

-85

-90

-95

-100

-105

HD2

HD3

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vo (Vpp)

HD (dBc)

-50

-60

-70

-80

-90

-100

-110

HD2

HD3

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vo (Vpp)

HD (dBc)

-60

-70

-80

-90

-100

-110

HD2

HD3

LMH6629

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

20 MHz 20 MHz

Figure 19. Distortion vs. Swing, WSON-8 Package Figure 20. Distortion vs. Swing, SOT-23-5 Package

1 MHz 1 MHz

Figure 21. Distortion vs. Swing, WSON-8 Package Figure 22. Distortion vs. Swing, SOT-23-5 Package

1 MHz Vout = 2 Vpp 1 MHz Vout = 2 Vpp

Figure 23. Distortion vs. Gain, WSON-8 Package Figure 24. Distortion vs. Gain, SOT-23-5 Package

Product Folder Links: LMH6629

0.1 1 10 100 1,000 10,000

f (kHz)

in (pA/Hz)

0.5 1.0 1.5 2.0 2.5 3.0 3.5

Vo (Vpp Composite)

IMD3 (dBc)

-30

-40

-50

-60

-70

-80

25 MHz

75 MHz

0.1 1 10 100 1,000 10,000

f (kHz)

en (nV/Hz)

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0 10 20 30 40 50

f (MHz)

HD (dBc)

-40

-50

-60

-70

-80

-90

-100

HD2

HD3

0 10 20 30 40 50

f (MHz)

HD (dBc)

-40

-50

-60

-70

-80

-90

-100

HD2

HD3

LMH6629

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

Vo = 2 Vpp Vo = 2 Vpp

Figure 25. Distortion vs. Frequency, WSON-8 Package Figure 26. Distortion vs. Frequency, SOT-23-5 Package

Figure 28. Input Noise Voltage vs. Frequency

Figure 27. 3rd Order Intermodulation Distortion

vs. Output Voltage

Figure 29. Input Noise Current vs. Frequency Figure 30. PSRR vs. Frequency

Product Folder Links: LMH6629

100 150 200 250 300 350 400

Isink (mA)

Vo from V- (V)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

25°C

125°C

-40°C

TIME (10 ns/DIV)

Vo (0.5V/DIV)

100 150 200 250 300 350 400

Isource (mA)

Vo from V+ (V)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

25°C

125°C

-40°C

100 150 200 250 300 350 400

Isink (mA)

Vo from V- (V)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

25°C

125°C

-40°C

100 150 200 250 300 350 400

Isource (mA)

Vo from V+ (V)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

125°C

-40°C

25°C

100k 1M 10M 100M 1G

Phase (°)

f (Hz)

Gain (dB)

Gain, COMP HI

Gain, COMP LO

Phase, COMP LO

Phase, COMP HI

160

120

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

Figure 31. Open Loop Gain/Phase Response Figure 32. Output Source Current, WSON-8 Package

Figure 33. Output Sink Current WSON-8 Package Figure 34. Output Source Current, SOT-23-5 Package

Figure 36. Large Signal Step Response

Figure 35. Output Sink Current, SOT-23-5 Package

Product Folder Links: LMH6629

PD\ (V)

-1

-2

-3

Time (50 ns/DIV)

Vo (V)

1.0

0.5

0.0

-0.5

-1.0

PD\

Time (2 ns/DIV)

Vo (0.05 V/DIV)

Time (4 ns/DIV)

Vo (0.2 V/DIV)

Time (2 ns/Div)

Vo (0.05V/Div)

Time (10 ns/DIV)

Vo (0.5 V/DIV)

Time (4 ns/Div)

Vo (0.2V/Div)

LMH6629

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

AV= 4V/V COMP Pin = LO

Figure 37. Large Signal Step Response Figure 38. Large Signal Step Response

Vs = 3.3 V

Figure 39. Large Signal Step Response Figure 40. Small Signal Step Response, WSON-8 Package

Vs = 3.3 V

Figure 41. Small Signal Step Response, WSON-8 Package Figure 42. Turn-On Waveform, WSON-8 Package

Product Folder Links: LMH6629

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Vs (V)

IOS (PA)

1.0

0.5

0.0

-0.5

-1.0

-1.5

125°C

-40°C

25°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Vs (V)

IB (PA)

125°C

-40°C

25°C

2.5 3.0 3.5 4.0 4.5 5.0 5.5

400

350

300

250

200

150

100

-50

25°C

85°C

-40°C

VOS ( V)

VS (V)

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Vs (V)

Is (mA)

18.0

17.0

16.0

15.0

14.0

13.0

125°C

25°C

-40°C

PD\ (V)

-1

-2

-3

Time (50 ns/DIV)

Vo (V)

1.0

0.5

0.0

-0.5

-1.0

PD\

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= ±2.5V, Rf= 240 Ω, RL= 100 Ω, VO= 2 VPP, COMP pin = HI, AV= +10 V/V, WSON-8 and

SOT-23-5 packages (unless specifically noted).

Figure 43. Turn-Off Waveform, WSON-8 Package Figure 44. Supply Current vs. Supply Voltage

Figure 45. Offset Voltage vs. Supply Voltage Figure 46. Input Bias Current vs. Supply Voltage

(Typical Unit) (Typical Unit)

Figure 47. Input Offset Current vs. Supply Voltage (Typical Unit)

Product Folder Links: LMH6629

OUT

COMP

IN+

IN-

V-

V+

V-

DAP

V+

4 5

-IN

+IN

OUT

COMP

V-

LMH6629

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7 Detailed Description

7.1 Overview

The LMH6629 is a high gain bandwidth, ultra low-noise voltage feedback operational amplifier. The excellent

noise and bandwidth enables applications such as medical diagnostic ultrasound, magnetic tape and disk

storage and fiberoptics to achieve maximum high frequency signal-to-noise ratios. The following discussion will

enable the proper selection of external components to achieve optimum system performance.

7.2 Functional Block Diagram

The LMH6629 (WSON-8 package only) has some additional features to allow maximum flexibility. As shown in

Figure 48, there are provisions for low-power shutdown and two internal compensation settings, which are

discussed in more detail in Compensation. Also provided is a feedback (FB) pin which allows the placement of

the feedback resistor directly adjacent to the inverting input (IN-) pin. This pin simplifies printed circuit board

layout and minimizes the possibility of unwanted interaction between the feedback path and other circuit

elements.

Figure 48. 8-Pin WSON Pinout Diagram

The WSON-8 package requires the bottom-side Die Attach Paddle (DAP) to be soldered to the circuit board for

proper thermal dissipation and to get the thermal resistance number specified. The DAP is tied to the V-potential

within the LMH6629 package. Thus, the circuit board copper area devoted to DAP heatsinking connection should

be at the V- potential as well. Please refer to the package drawing for the recommended land pattern and

recommended DAP connection dimensions.

Figure 49. WSON–8 DAP(Top View)

Product Folder Links: LMH6629

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7.3 Feature Description

7.3.1 WSON-8 Control Pins and SOT-23-5 Comparison

The LMH6629 WSON-8 package has two digital control pins; PD and COMP pins. The PD pin, used for power

down, floats high (device on) when not driven. When the PD pin is pulled low, the amplifier is disabled and the

amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the

output impedance of the circuit. The other control pin, the COMP pin, allows control of the internal compensation

and defaults to the lower gain mode or logic 0.

The SOT-23-5 package has the following differences relative to the WSON-8 package:

1. No power down (shutdown) capability.

2. No COMP pin to set the minimum stable gain. SOT-23–5 package minimum stable gain is internally fixed to

be 10V/V.

3. No feedback (FB) pin.

From a performance point of view, the WSON-8 and the SOT-23-5 packages perform very similarly except in the

following areas:

1. SSBW, Peaking, and 0.1 dB Bandwidth: These differences are highlighted in the Typical Performance

Characteristics and the Electrical Characteristics 5V tables. Most notable differences are with small signal

(0.2 Vpp) and close to the minimum stable gain of 10V/V.

2. Distortion: It is possible to get slightly different distortion performance. The board layout and decoupling

capacitor return current routing strongly influence distortion performance.

3. Output Current: In heavy current applications, there will be differences between these package types

because of the difference in their respective Thermal Resistances (RθJA).

7.3.2 Compensation

The LMH6629 has two compensation settings that can be controlled by the COMP pin (WSON-8 package only).

The default setting is set through an internal pulldown resistor and places the COMP pin at the logic 0 state. In

this configuration the on-chip compensation is set to the maximum and bandwidth is reduced to enable stability

at gains as low as 4V/V.

When this pin is driven to the logic 1 state, the internal compensation is decreased to allow higher bandwidth at

higher gains. In this state, the minimum stable gain is 10V/V. Due to the reduced compensation, slew rate and

large signal bandwidth are significantly enhanced for the higher gains.

NOTE

As mentioned earlier, the SOT-23-5 package does not offer the two compensation settings

that the WSON-8 offers. The SOT-23-5 is internally set for a minimum gain of 10 V/V.

It is possible to externally compensate the LMH6629 for any of the following reasons, as shown in Figure 50.

• To operate the SOT-23-5 package (which does not offer the COMP pin) at closed loop gains < 10V/V.

• To operate the WSON-8 package at gains below the minimum stable gain of 4V /V when the COMP pin is

LO. NOTE: In this case, Figure 50 “Constraint 1” may be changed to ≥4 V/V instead of ≥10 V/V.

• To operate either package at low gain and need maximum slew rate (COMP pin HI).

Product Folder Links: LMH6629

VIN Rp

VIN

a) Non-inverting b) Inverting

HIpin =COMP

RRR sg +=

gfEQ RRR ||=

Tsp RRR ||=

: 1 Constraint

: 2Costraint MHz90

RC cc

V/V))(

(g101 t

+ +

1RR EQp +

LMH6629

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Feature Description (continued)

Figure 50. External Compensation

This circuit operates by increasing the Noise Gain (NG) beyond the minimum stable gain of the LMH6629 while

maintaining a positive loop gain phase angle at 0 dB. There are two constraints shown in Figure 50: “Constraint

1” ensures that NG has increased to at least 10 V/V when the loop gain approaches 0dB, and “Constraint 2”

places an upper limit on the feedback phase lead network frequency to make sure it is fully effective in the

frequency range when loop gain approaches 0dB. These two constraints allow one to estimate the “starting

value” for Rcand Ccwhich may need to be fine tuned for proper response.

Here is an example worked out for more clarification:

• Assume that the objective is to use the SOT-23-5 version of the LMH6629 for a closed loop gain of +3.7 V/V

using the technique shown in Figure 50.

• Selecting Rf= 249 Ω → Rg= 91 Ω → REQ= 66.6 Ω.

• For 50-Ωsource termination (Rs= 50 Ω), select RT= 50 Ω → Rp= 25 Ω.

• Using “Constraint 1” (= 10V/V) allows one to compute Rc ≊56 Ω. Using “Constraint 2” (= 90 MHz) defines the

appropriate value of Cc≊33 pF.

• The frequency response plot shown in Figure 51 is the measured response with Rcand Ccvalues computed

above and shows a -3 dB response of about 1 GHz.

Product Folder Links: LMH6629

zero"" Gain Noise #1

CEQpC C)RR(R2 ++S

4.0

2.0

0.0

-2.0

-4.0

-6.0

f (MHz)

Normalized Gain (dB)

Cf ¶

1 10 100 1,000 10,000

LMH6629

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Feature Description (continued)

Cf= 1.5 pF

RA= 33 Ω

RB= 91 Ω

Figure 51. SOT-23-5 Package Low Closed Loop Gain Operation

with External Compensation

For the Figure 51 measured results, a compensation capacitor (Cf') was used across Rfto compensate for the

summing node net capacitance due to the board and the SOT-23–5 LMH6629. The RAand RBcombination

reduces the effective capacitance of Cf‘ by the ratio of 1+RB/ RA, with the constraint that RB<< Rf, thereby

allowing a practical capacitance value (> 1pF) to be used. The WSON-8 package does not need this

compensation across Rfdue to its lower parasitics.

With the COMP pin HI (WSON-8 package only) or with the SOT-23–5 package, this circuit achieves high slew

rate and takes advantage of the LMH6629’s superior low-noise characteristics without sacrificing stability, while

enabling lower gain applications. It should be noted that the Rc, Cccombination does lower the input impedance

and increases noise gain at higher frequencies. With these values, the input impedance reduces by 3 dB at 490

MHz. The Noise Gain transfer function “zero” is given by Equation 1 and it has a 3-dB increase at 32.8 MHz with

these values:

External Compensation Noise Gain Increase:

(1)

Product Folder Links: LMH6629

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Feature Description (continued)

7.3.3 Cancellation of Offset Errors Due to Input Bias Currents

The LMH6629 offers exceptional offset voltage accuracy. In order to preserve the low offset voltage errors, care

must be taken to avoid voltage errors due to input bias currents. This is important in both inverting and non-

inverting applications.

The non-inverting circuit is used here as an example. To cancel the bias current errors of the non-inverting

configuration, the parallel combination of the gain setting (Rg) and feedback (Rf) resistors should equal the

equivalent source resistance (Rseq) as defined in Figure 52. Combining this constraint with the non-inverting gain

equation also seen in Figure 52 allows both Rfand Rgto be determined explicitly from Equation 2:

Rf= AVRseq and Rg= Rf/(AV-1) (2)

Figure 52. Non-Inverting Amplifier Configuration

When driven from a 0-Ωsource, such as the output of an op amp, the non-inverting input of the LMH6629 should

be isolated with at least a 25-Ωseries resistor.

As seen in Figure 53, bias current cancellation is accomplished for the inverting configuration by placing a

resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf|| (Rg+Rs)).

Rbshould to be no less than 25 Ωfor optimum LMH6629 performance. A shunt capacitor (not shown) can

minimize the additional noise of Rb.

Figure 53. Inverting Amplifier Configuration

Product Folder Links: LMH6629

(Noiseless)

Noiseless Op

Amp

eni

(Noiseless)

VSRT

(Noiseless)

Rseq = RS || RT

Set RSeq = Rf || Rg for bias current offset

cancellation

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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Feature Description (continued)

7.3.4 Total Input Noise vs. Source Resistance

To determine maximum signal-to-noise ratios from the LMH6629, an understanding of the interaction between

the amplifier’s intrinsic noise sources and the noise arising from its external resistors is necessary. Figure 54

describes the noise model for the non-inverting amplifier configuration showing all noise sources. In addition to

the intrinsic input voltage noise (en) and current noise (in= in+= in−) source, there is also thermal voltage noise (et

=√(4KTR)) associated with each of the external resistors.

Figure 54. Non-Inverting Amplifier Noise Model

Equation 3 provides the general form for total equivalent input voltage noise density (eni).

General Noise Equation:

(3)

Equation 4 is a simplification of Equation 3 that assumes Rf|| Rg= Rseq for bias current cancellation:

Equation 4: Noise Equation with Rf|| Rg= Rseq (4)

Figure 55 schematically shows eni alongside VIN (the portion of VSsource which reaches the non-inverting input

of Figure 52) and external components affecting gain (Av=1+Rf/ Rg), all connected to an ideal noiseless

amplifier.

Figure 55. Non-Inverting Amplifier Equivalent Noise Source Schematic

Product Folder Links: LMH6629

1 10 100 1k 10k 100k

RSEQ (:)

Voltage Noise Density (nV/ Hz)

1000

100

0.1

eni

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Feature Description (continued)

Figure 56 illustrates the equivalent noise model using this assumption. Figure 57 is a plot of eni against

equivalent source resistance (Rseq) with all of the contributing voltage noise source of Equation 4. This plot gives

the expected eni for a given (Rseq) which assumes Rf||Rg= Rseq for bias current cancellation. The total equivalent

output voltage noise (eno) is eni*AV.

Figure 56. Noise Model with Rf||Rg= Rseq

As seen in Figure 57, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source

resistances below 15 Ω. Between 15 Ωand 2.5 kΩ, eni is dominated by the thermal noise (et=√(4kT(2Rseq)) of

the equivalent source resistance Rseq. Incidentally, this is the range of Rseq values where the LMH6629 has the

best (lowest) Noise Figure (NF) for the case where Rseq = Rf|| Rg.

Above 2.5 kΩ, eni is dominated by the amplifier’s current noise (in=√2 * inRseq). When Rseq = 190 Ω(that is, Rseq

= en/√2 * in), the contribution from voltage noise and current noise of LMH6629 is equal. For example, configured

with a gain of +10V/V giving a −3dB of 825 MHz and driven from Rseq = Rf|| Rg= 20 Ω(eni = 1.07 nV√Hz from

Figure 57), the LMH6629 produces a total equivalent output noise voltage (eni * 10 V/V * √(1.57 * 825 MHz)) of

385 μVrms.

RSEQ = RF|| RG

Figure 57. Voltage Noise Density vs. Source Resistance

Product Folder Links: LMH6629

NF = 10 log ¸

§G(Ni + Na)

Ni= 10 log 1 + Ni

LMH6629

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Feature Description (continued)

If bias current cancellation is not a requirement, then Rf|| Rgdoes not need to equal Rseq. In this case, according

to Equation 3, Rf|| Rgshould be as low as possible to minimize noise. Results similar to Equation 3 are obtained

for the inverting configuration of Figure 53 if Rseq is replaced by Rband Rgis replaced by Rg+ Rs. With these

substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is

easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains (1+Rg/ Rf).

7.3.5 Noise Figure

Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.

General Noise Figure Equation:

(5)

Looking at the two parts of the NF expression (inside the log function) yields:

• Si/ So→Inverse of the power gain provided by the amplifier

• No/ Ni→Total output noise power, including the contribution of RS, divided by the noise power at the input

due to RS

• To simplify this, consider Naas the noise power added by the amplifier (reflected to its input port):

• Si/ So→1/ G

• No/ Ni→G * (Ni+Na)/Ni(where G*(Ni+Na)=No)

Substituting these two expressions into the NF expression:

(6)

The noise figure expression has simplified to depend only on the ratio of the noise power added by the amplifier

at its input (considering the source resistor to be in place but noiseless in getting Na) to the noise power

delivered by the source resistor (considering all amplifier elements to be in place but noiseless in getting Ni).

For a given amplifier with a desired closed loop gain, to minimize noise figure:

• Minimize Rf|| Rg

• Choose the Optimum RS(ROPT)

ROPT is the point at which the NF curve reaches a minimum and is approximated by:

ROPT ≈en/ in(7)

Product Folder Links: LMH6629

10 100 1k 10k 100k

RS (:)

Noise Figure (dB)

0Unterminated

Terminated

LMH6629

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Feature Description (continued)

Figure 58 is a plot of NF vs RSwith the circuit of Figure 52 (Rf= 240 Ω, AV= +10V/V). The NF curves for both

Unterminated (RT= open) and Terminated systems (RT= RS) are shown. Table 1 indicates NF for various source

resistances including RS= ROPT.

f > 1 MHz

Figure 58. Noise Figure vs. Source Resistance

Table 1. Noise Figure for Various Rs

RS(Ω) NF (TERMINATED) (dB) NF (UNTERMINATED) (dB)

50 8 3.2

ROPT 4.1 1.1

(ROPT = 750 Ω) (ROPT = 350 Ω)

7.3.6 Single-Supply Operation

The LMH6629 can be operated with single power supply as shown in Figure 59. Both the input and output are

capacitively coupled to set the DC operating point.

Figure 59. Single-Supply Operation

Product Folder Links: LMH6629

NOISE GAIN (NG)

OP AMP OPEN

LOOP GAIN

I-V GAIN (:)

GAIN (dB)

0 dB

FREQUENCY

1 + sRF (CIN + CF)

1 + sRFCF

1 + CIN

GBWP

fz #

2SRFCIN fP = 1

2SRFCF

1.2k

500

+5VDC

CD = 10 pF

+5VDC R2

0.1 PFR1

LMH

6629

0.6 pF

(1.2 pF (2) series)

Vout = 3VDC - 1200 x ID

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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7.3.7 Low-Noise Transimpedance Amplifier

Figure 60 implements a high-speed, single-supply, low-noise Transimpedance amplifier commonly used with

photo-diodes. The transimpedance gain is set by RF.

Figure 60. 200 MHz Transimpedance Amplifier Configuration

Figure 61 shows the Noise Gain (NG) and transfer function (I-V Gain). As with most Transimpedance amplifiers,

it is required to compensate for the additional phase lag (Noise Gain zero at fZ) created by the total input

capacitance ( CD(diode capacitance) + CCM (LMH6629 CM input capacitance) + CDIFF (LMH6629 DIFF input

capacitance) ) looking into RF. This is accomplished by placing CFacross RFto create enough phase lead (Noise

Gain pole at fP) to stabilize the loop.

Figure 61. Transimpedance Amplifier Noise Gain and Transfer Function

Product Folder Links: LMH6629

(Noiseless)

+5VDC

CD = 10 pF

Noiseless Op Amp

ini

100 1k 10k

Rf (:)

Current Noise Density (pA/ Hz)

ini

en/RF

dB3- GBWP

INFCRS2

R)GBWP(2S

C =

LMH6629

www.ti.com

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

The optimum value of CFis given by Equation 8 resulting in the I-V -3dB bandwidth shown in Equation 9, or

around 200 MHz in this case (assuming GBWP= 4GHz with COMP pin = HI for WSON-8 package). This CF

value is a “starting point” and CFneeds to be tuned for the particular application as it is often less than 1 pF and

thus is easily affected by board parasitics. For maximum speed, the LMH6629 COMP pin should be HI (or use

the SOT-23 package).

Optimum CFValue:

(8)

Resulting -3dB Bandwidth

(9)

Equation 10 provides the total input current noise density (ini) equation for the basic Transimpedance

configuration and is plotted against feedback resistance (RF) showing all contributing noise sources in Figure 62.

The plot indicates the expected total equivalent input current noise density (ini) for a given feedback resistance

(RF). This is depicted in the schematic of Figure 63 where total equivalent current noise density (ini) is shown at

the input of a noiseless amplifier and noiseless feedback resistor (RF). The total equivalent output voltage noise

density (eno) is ini*RF.

Noise Equation for Transimpedance Amplifier:

(10)

Figure 62. Current Noise Density vs. Feedback Resistance

Figure 63. Transimpedance Amplifier Equivalent Input Source Model

Product Folder Links: LMH6629

VIN

21211 )RR(C)K1(CR ++-

ppQZ

2121 CCRR

ppQ

1 +

RSVO

VIN -

50:

RF = RB

RG = RS||R

VO #VIN KO

sRSC;KO = 1 + RF

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

From Figure 62, it is clear that with LMH6629’s extremely low-noise characteristics, for RF< 2.5 kΩ, the noise

performance is entirely dominated by RFthermal noise. Only above this RFthreshold, LMH6629’s input noise

current (in) starts being a factor and at no RFsetting does the LMH6629 input noise voltage play a significant

role. This noise analysis has ignored the possible noise gain increase, due to photo-diode capacitance, at higher

frequencies.

7.3.8 Low-Noise Integrator

Figure 64 shows a deBoo integrator implemented with the LMH6629. Positive feedback maintains integration

linearity. The LMH6629’s low input offset voltage and matched inputs allow bias current cancellation and provide

for very precise integration. Keeping RGand RSlow helps maintain dynamic stability.

Figure 64. Low-Noise Integrator

7.3.9 High-Gain Sallen-Key Active Filters

The LMH6629 is well suited for high-gain Sallen-Key type of active filters. Figure 65 shows the 2nd order Sallen-

Key low-pass filter topology. Using component predistortion methods discussed in OA-21, Component Pre-

Distortion for Sallen Key Filters (SNOA369), enables the proper selection of components for these high-

frequency filters.

Figure 65. Low Pass Sallen-Key Active Filter Topology

Product Folder Links: LMH6629

LMH6629

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

7.4 Device Functional Modes

With an industry-leading low noise voltage operating off a supply voltage as low as 2.7-V and a common mode

input voltage range that extends 0.3 V below V−, the LMH6629 finds applications in single supply, high

bandwidth, ultra-low noise applications. With a GBWP of 4GHz, the LMH6629 can operate at large gains and

deliver exceptional speed and low noise. Choose the WSON(8) package for the ultimate flexibility (including

Power Down and COMP pin which allows tailoring internal compensation to the operating gain conditions), or the

SOT23-5 package if Power Down is not needed and closed loop gain is ≥20dB.

Product Folder Links: LMH6629

VIN

470, KRg

200, Rin

47, Rg

LMH6629

0.417V

Vset

COVin-

Vin+

VREF

470, KRg

1k, RfADC

2.5V

GND 3Vpp 2.5V

2.5V

3Vpp

2.32k

464

600 mVpp

RinK 200 1k Let R,10 f:=o:==VV CMo ;5.2

Vset = V417.0=

V5.22 x 2

10 +

VppV diffo ;6

mVppVin 600=

:Example

K= Vdiff_o

Vin

2Rf

Rin

:sExpressionGoverning

=Vset V2 CM_o 2K +

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following discussion details some of the applications that can benefit from the LMH6629’s ultra-low noise,

wide bandwidth, and single supply capability.

Note that It is essential to use a low-noise / low-distortion device to drive a high resolution ADC. This will

minimize the impact on the quantization noise and to make sure that the driver’s distortion does not dominate the

acquired data.

Equation 11 demonstrates the converter noise expression and Equation 12 shows the converter noise

expression evaluated for the example depicted in Figure 66.Figure 67 shows a high-performance low-noise

equalizer for such applications as magnetic tape channels using the LMH6629. Figure 68 shows the circuit’s

simulated frequency response.

8.2 Typical Application

Many high-resolution data converters (ADC’s) require a differential input driver. In order to preserve the ADC’s

dynamic range, the analog input driver must have a noise floor which is lower than the ADC’s noise floor.

Figure 66 shows a ground referenced bipolar input (symmetrical swing around 0V) SE to differential converter

used to drive a high resolution ADC. The combination of LMH6629’s low noise and the converter architecture

reduces the impact on the ADC noise.

Figure 66. Low-Noise Single-Ended (SE) to Differential Converter

Product Folder Links: LMH6629

¶C = 2S LC

Vnoise #@ > @ > @

RtHznVRtHznVRtHznV 10/88.02.5/82.12.6/69 2

2x+x+x

>.0 RtHznV/4.23=

Vnoise #>@> @ > @2

2))(2.)2/)(2.

)2/1( KeKe

Ke thermalRg

thermalRin

n++

LMH6629

www.ti.com

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

Typical Application (continued)

8.2.1 Design Requirements

For an ADC with N bits, the quantization Signal-to-noise ratio (SNR) is 6.02* N + 1.76 in dB. For example, a 12-

bit ADC has a SNR of 74 dB (= 5000 V/V). Assuming a full-scale differential input of 2Vpp (0.707 V_RMS), the

quantization oise referred to the ADC’s input is ~140 μV_RMS (= 0.707 V_RMS / 5000 V/V) over the bandwidth

“visible” to the ADC. Assuming an ADC input bandwidth of 20 MHz, this translates to just 25 nV/RtHz (= 141

µV_RMS / SQRT(20 MHz * π/2)) noise density at the output of the driver. Using an amplifier to form the single-

ended (SE) to Differential converter / driver for such an application is challenging, especially when there is some

gain required. In addition, the input driver’s linearity (harmonic distortion) must also be high enough such that the

spurs that get through to the ADC input are below the ADC’s LSB threshold or -73 dBc (= 20*log (1/ 212)) or

lower in this case. Therefore, it is essential to use a low-noise / low-distortion device to drive a high resolution

ADC in order to minimize the impact on the quantization noise and to make sure that the driver’s distortion does

not dominate the acquired data.

8.2.2 Detailed Design Procedure

In the circuit depicted in Figure 66, the required gain dictates the resistor ratio “K”. With “K” and the driver output

CM voltage (VO_CM) known, VSET can be established. Reasonable values for Rfand Rgcan be set to complete

the design.

In terms of output swing, with the LMH6629 output swing capability which requires ~0.85 V of headroom from

either rail, the maximum total output swing into the ADC is limited to 6.6 VPP (=(5 – 2 x 0.85V) x 2); that is true

with VO_CM set to mid-rail between V+and V-. It should also be noted that the LMH6629’s input CMVR range

includes the lower rail (V-) and that is the reason there is great flexibility in setting Vo_CM by controlling VSET.

Another feature is that A1 and A2 inputs act like “virtual grounds” and thus do not see any signal swing. Note that

due to the converter’s biasing, the source, VIN, needs to sink a current equal to VSET / RIN.

The converter example shown in Figure 66 operates with a noise gain of 6 (=1+ K / 2) and thus requires that the

COMP pin to be tied low (WSON-8 package only). The 1st order approximated small signal bandwidth will be 280

MHz (=1.7 GHz / 6 V/V) which is computed using 1.7 GHz as the GBWP with COMP pin LO.

From a noise point of view, concentrating only on the dominant noise sources involved, here is the expression for

the expected differential noise density at the input of the ADC.

Converter Noise Expression:

(11)

enis the LMH6629 input noise voltage and eRin_thermal is the thermal noise of RIN. The “23” and the “22” multipliers

account for the different instances of each noise source (2 for en, and 1 for eRin_thermal).

Equation 11, evaluated for the circuit example of Figure 66, is shown in Equation 12:

(12)

Because of the LMH6629’s low input noise voltage (en), noise is dominated by the thermal noise of RIN. It is

evident that the input resistor, RIN, can be reduced to lower the noise with lower input impedance as the trade-

off.

8.2.2.1 Low-Noise Magnetic Media Equalizer

Figure 67 shows a high-performance low-noise equalizer for such applications as magnetic tape channels using

the LMH6629. The circuit combines an integrator (used to limit noise) with a bandpass filter (used to boost the

response centered at a frequency or over a band of interest) to produce the low-noise equalization. The circuit’s

simulated frequency response is illustrated in Figure 68.

In this circuit, the bandpass filter center frequency is set by Equation 13:

(13)

For higher selectivity, use high C values; for wider bandwidth, use high L values, while keeping the product of L

and C values the same to keep fcintact. The integrator’s -3dB roll-off is set by

Product Folder Links: LMH6629

2SC1R1

< < C

2SC1(R1 + R)

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

Typical Application (continued)

(14)

If:

(15)

The integrator and the bandpass filter frequency interaction is minimized so that the operating frequencies of

each can be set independently. Lowering the value of R2 increases the bandpass gain (boost) without affecting

the integrator frequencies. With the LMH6629’s wide Gain Bandwidth (4 GHz), the center frequency could be

adjusted higher without worries about loop gain limitation. This increases flexibility in tuning the circuit.

Figure 67. Low-Noise Magnetic Media Equalizer

8.2.3 Application Curves

Figure 68. Equalizer Frequency Response

9 Power Supply Recommendations

The LMH6629 can operate off a single supply or with dual supplies. The input CM capability of the part (CMVR)

extends all the way down to the V- rail to simplify single supply applications. Supplies should be decoupled with

low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground

plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to

device sensitive pins such as the inputs.

Product Folder Links: LMH6629

LMH6629

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SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

10 Layout

10.1 Layout Guidelines

Texas Instruments offers evaluation board(s) to aid in device testing and characterization and as a guide for

proper layout. As is the case with all high-speed amplifiers, accepted-practice RF design technique on the PCB

layout is mandatory. Generally, a good high-frequency layout exhibits a separation of power supply and ground

traces from the inverting input and output pins. Parasitic capacitances between these nodes and ground may

cause frequency response peaking and possible circuit oscillations. See Application Note OA-15, Frequent Faux

Pas in Applying Wideband Current Feedback Amplifiers (SNOA367) for more information. Use high-quality chip

capacitors with values in the range of 1000 pF to 0.1 µF for power supply bypassing. One terminal of each chip

capacitor is connected to the ground plane and the other terminal is connected to a point that is as close as

possible to each supply pin as allowed by the manufacturer’s design rules. In addition, connect a tantalum

capacitor with a value between 4.7 μF and 10 μF in parallel with the chip capacitor.

Harmonic Distortion, especially HD2, is strongly influenced by the layout and in particular can be affected by

decoupling capacitors placed between the V+and V-terminals as close to the device leads as possible.

Signal lines connecting the feedback and gain resistors should be as short as possible to minimize inductance

and microstrip line effect. Place input and output termination resistors as close as possible to the input/output

pins. Traces greater than 1 inch in length should be impedance matched to the corresponding load termination.

Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to

minimize the imbalance of amplitude and phase of the differential signal.

Component value selection is another important parameter in working with high-speed / high-performance

amplifiers. Choosing external resistors that are large in value compared to the value of other critical components

will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic

capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board

layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.

Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low

value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion.

Product Folder Links: LMH6629

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

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10.2 Layout Example

Figure 69. Evaluation Board Top Layer, Figure 70. Evaluation Board Bottom Layer,

WSON-8 Package WSON-8 Package

Figure 71. Evaluation Board Layer 2, Figure 72. Evaluation Board Layer 3,

WSON-8 Package WSON-8 Package

Product Folder Links: LMH6629

LMH6629

SNOSB18I –APRIL 2010–REVISED DECEMBER 2014

www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

•Absolute Maximum Ratings for Soldering (SNOA549)

•Component Pre-Distortion for Sallen Key Filters, Application Note OA-21 (SNOA369)

•Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)

•Semiconductor and IC Package Thermal Metrics (SPRA953)

11.2 Trademarks

All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMH6629

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH6629MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AE7A

LMH6629MFE/NOPB ACTIVE SOT-23 DBV 5 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AE7A

LMH6629MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AE7A

LMH6629SD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L6629

LMH6629SDE/NOPB ACTIVE WSON NGQ 8 250 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L6629

LMH6629SDX/NOPB ACTIVE WSON NGQ 8 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L6629

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH6629MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMH6629MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMH6629MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMH6629SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LMH6629SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

LMH6629SDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Apr-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH6629MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMH6629MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0

LMH6629MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LMH6629SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0

LMH6629SDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0

LMH6629SDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Apr-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

8X 0.3

0.2

2 0.1

8X 0.5

0.3

1.5

1.6 0.1

6X 0.5

0.8

0.7

0.05

0.00

B3.1

2.9 A

3.1

2.9

(0.1) TYP

WSON - 0.8 mm max heightNGQ0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214922/A 03/2018

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

(1.6)

6X (0.5)

(2.8)

8X (0.25)

8X (0.6)

(2)

(R0.05) TYP ( 0.2) VIA

TYP

(0.75)

WSON - 0.8 mm max heightNGQ0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214922/A 03/2018

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

8X (0.25)

8X (0.6)

6X (0.5)

(1.79)

(1.47)

(2.8)

(R0.05) TYP

WSON - 0.8 mm max heightNGQ0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214922/A 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 9:

82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

METAL

TYP

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/E 09/2019

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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