®
Altera Corporation 1
Configuration Devices
for APEX & FLEX Devices
November 1999, ver. 10.03 Data Sheet
A-DS-EPROM-10.03
Features
■
Serial device family for configuring FLEX
®
and APEX
TM
devices
■
Easy-to-use 4-pin interface to FLEX and APEX devices
■
Low current during configuration and near-zero standby current
■
5.0-V and 3.3-V operation
■
Software design support with the Altera
®
Quartus
TM
and
MAX+PLUS
®
II development systems for Windows-based PCs as
well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
■
Programming support with Altera’s Master Programming Unit
(MPU) and programming hardware from Data I/O, BP
Microsystems, and other manufacturers
■
Available in compact plastic packages (see Figures 1 and 2)
– 8-pin plastic dual in-line package (PDIP)
– 20-pin plastic J-lead chip carrier (PLCC) package
– 32-pin plastic thin quad flat pack (TQFP) package
■
EPC2 has reprogrammable FLASH configuration memory
– 5.0-V and 3.3-V in-system programmability (ISP) through the
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)
interface
– Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
– Supports programming through Serial Vector Format Files
(
.svf
), Jam
TM
Files (
.jam
), Jam Byte-Code Files (
.jbc
), and the
MAX+PLUS II software via the BitBlaster
TM
, ByteBlaster
TM
, or
ByteBlasterMV
TM
download cable (the ByteBlaster cable is
obsolete and is replaced by the ByteBlasterMV cable, which can
program or configure 2.5-V, 3.3-V, or 5.0-V devices)
–
nINIT_CONF
pin allows a JTAG instruction to initiate FLEX or
APEX configuration
– Can be programmed with Programmer Object Files (
.pof
) for
EPC1 and EPC1441 devices (except when configuring FLEX 8000
devices)
– Available in 20-pin PLCC and 32-pin TQFP packages
2 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 1. EPC1, EPC1441, EPC1213, EPC1064 & EPC1064V Package Pin-Out Diagrams
Note:
(1) The
nCASC
pin is available on EPC1 and EPC1213 devices. On the EPC1064, EPC1064V, and EPC1441 devices, it is
a reserved pin and should not be connected.
Figure 2. EPC2 Package Pin-Out Diagrams
8-Pin PDIP 32-Pin TQFP
EPC1441
EPC1064
EPC1064V
20-Pin PLCC
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
DATA
DCLK
OE
nCS
VCC
VCC
nCASC
(1)
GND
1
2
3
4
8
7
6
5
123
4
5
6
7
8
20 19
111091213
18
17
16
15
14
OE
N.C.
N.C.
DCLK
N.C.
N.C.
N.C.
DATA
N.C.
VCC
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(1)
nCASC
nCS
GND
303132
1
2
3
4
5
29 28
N.C.
N.C.
DCLK
N.C.
N.C.
N.C.
N.C.
nCS
N.C.
GND
N.C.
N.C.
N.C.
24
23
22
21
20
N.C.
VCC
N.C.
N.C.
19
18
17
N.C.
N.C.
DATA
N.C.
N.C.
N.C.
VCC
N.C.
25
916
8
N.C.
OE
N.C.
N.C.
N.C.
N.C.
6
7
10 11 12 13 14 15
27 26
N.C.
32-Pin TQFP
20-Pin PLCC
123
4
5
6
7
8
20 19
111091213
18
17
16
15
14
OE
N.C.
VCCSEL
DCLK
N.C.
TMS
TCK
DATA
TDO
VCC
VPP
N.C.
N.C.
N.C.
VPPSEL
TDI
nCASC
nCS
GND
303132
1
2
3
4
5
29 28
N.C.
N.C.
DCLK
N.C.
VCCSEL
TDI
N.C.
nCS
N.C.
GND
nINIT_CONF
N.C.
N.C.
24
23
22
21
20
N.C.
VPP
N.C.
N.C.
19
18
17
TDO
TCK
DATA
N.C.
N.C.
TMS
VCC
N.C.
25
916
8
N.C.
OE
N.C.
VPPSEL
N.C.
N.C.
6
7
10 11 12 13 14 15
27 26
nCASC
nINIT_CONF
Altera Corporation 3
Configuration Devices for APEX & FLEX Devices Data Sheet
Functional
Description
With SRAM-based devices, configuration data must be reloaded each
time the system initializes, or when new configuration data is needed.
Altera configuration devices store configuration data for SRAM-based
FLEX and APEX devices. Table 1 lists Altera’s configuration devices.
Table 2 lists the configuration device used with each FLEX device.
Table 1. Configuration Devices
Device Description
EPC2 1,695,680
×
1-bit device with 5.0-V or 3.3-V operation
EPC1 1,046,496
×
1-bit device with 5.0-V or 3.3-V operation
EPC1441 440,800
×
1-bit device with 5.0-V or 3.3-V operation
EPC1213 212,942
×
1-bit device with 5.0-V operation
EPC1064 65,536
×
1-bit device with 5.0-V operation
EPC1064V 65,536
×
1-bit device with 3.3-V operation
4 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 2. Appropriate Configuration Device for Each FLEX & APEX Device
APEX & FLEX Device Configuration Device
EP20K60E EPC2 or EPC1
EP20K100, EP20K100E EPC2 or EPC1
EP20K160E EPC2
EP20K200, EP20K200E Two EPC2 devices
EP20K300E Two EPC2 devices
EP20K400, EP20K400E Three EPC2 devices
EP20K600E Four EPC2 devices
EP20K1000E Six EPC2 devices
EP20K1500E Eight EPC2 devices
EPF10K10, EPF10K10A EPC2, EPC1, or EPC1441
EPF10K20 EPC2, EPC1, or EPC1441
EPF10K30E EPC2 or EPC1
EPF10K30, EPF10K30A EPC2, EPC1, or EPC1441
EPF10K40 EPC2 or EPC1
EPF10K50, EPF10K50V, EPF10K50E EPC2 or EPC1
EPF10K70 EPC2 or EPC1
EPF10K100, EPF10K100A, EPF10K100B, EPF10K100E EPC2 or two EPC1 devices
EPF10K130V EPC2 or two EPC1 devices
EPF10K130E Two EPC2 or two EPC1 devices
EPF10K200E Two EPC2 or three EPC1 devices
EPF10K250A Two EPC2 or four EPC1 devices
EPF8282A EPC1, EPC1441, or EPC1064
EPF8282AV EPC1, EPC1441, or EPC1064V
EPF8452A EPC1, EPC1441, EPC1064, or EPC1213
EPF8636A EPC1, EPC1441, or EPC1213
EPF8820A EPC1, EPC1441, or EPC1213
EPF81188A EPC1, EPC1441, or EPC1213
EPF81500A EPC1, or EPC1441
EPF6010A EPC2, EPC1, or EPC1441
EPF6016, EPF6016A EPC1, or EPC1441
EPF6024A EPC1, or EPC1441
Altera Corporation 5
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 3 shows which configuration devices can be used with which APEX
and FLEX families.
Figure 3 shows the configuration device block diagram.
Table 3. Configuration Device & PLD Compatibility
PLD Configuration Device
EPC1064V
EPC1064
EPC1213
EPC1
EPC1441
EPC2
APEX 20K
vv
FLEX 10K
vv
FLEX 8000
v
FLEX 6000
v
6 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 3. Configuration Device Block Diagram
Device
Configuration
The control signals for configuration devices—
nCS
,
OE
, and
DCLK
—
interface directly with FLEX and APEX device control signals. All FLEX
and APEX devices can be configured by a configuration device without
requiring an external intelligent controller.
DCLK
nCS
OE
Decode
Logic
Address
DATA
DATA
nCASC
(1)
Shift
Register
EPROM
Array
nCS
Decode
Logic
Address
Oscillator
Oscillator
Control
EPROM
Array
Shift
Register
DATA
DATA
DCLK
nCASC
(1)
APEX 20K, FLEX 10K & FLEX 6000 Device Configuration Using an EPC2, EPC1, or EPC1441
FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V
Address
Counter
CLK
ENA
nRESET
Address
Counter
CLK
ENA
nRESET
Error
Detection
Circuitry
OE
(2)
Notes:
(1) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213
devices support data cascading.
(2) The OE pin is a bidirectional open-drain pin.
Altera Corporation 7
Configuration Devices for APEX & FLEX Devices Data Sheet
The configuration device’s
OE
and
nCS
pins control the tri-state buffer on
the
DATA
output pin, and enable the address counter (and the oscillator in
EPC2, EPC1, and EPC1441 devices). When
OE
is driven low, the
configuration device resets the address counter and tri-states its
DATA
pin.
The
nCS
pin controls the output of the configuration device. If
nCS
is held
high after the
OE
reset pulse, the counter is disabled and the
DATA
output
pin is tri-stated. When
nCS
is driven low, the counter and
DATA
output pin
are enabled. When
OE
is driven low again, the address counter is reset and
the
DATA
output pin is tri-stated, regardless of the state of
nCS
.
1
The EPC2, EPC1, and EPC1441 devices determine the operation
mode and whether the APEX 20K, FLEX 10K, FLEX 8000, or
FLEX 6000 protocols should be used when
OE
is driven high.
When the configuration device has driven out all of its data and has
driven
nCASC
low, the device tri-states the
DATA
pin to avoid contention
with other configuration devices. Upon power-up, the address counter is
reset automatically.
The EPC2 device allows the user to initiate configuration of the FLEX or
APEX device via an additional pin, called
nINIT_CONF
, that can be tied to
the
nCONFIG
pin of the FLEX or APEX device(s) to be configured. A JTAG
instruction causes the EPC2 device to drive
nINIT_CONF
low, which in
turn pulls
nCONFIG
low. The EPC2 device then drives
nINIT_CONF
high to
start configuration. When the JTAG state machine exits this state,
nINIT_CONF
releases
nCONFIG
and configuration is initiated.
1
An EPC2 device can be programmed with a POF generated for
an EPC1 or EPC1441 device (except when configuring
FLEX 8000 devices). In addition, an EPC1 device can be
programmed using a POF
generated for an EPC1441 device.
APEX 20K, FLEX 10K & FLEX 6000 Device Configuration
APEX 20K and FLEX 10K devices can be configured with EPC2, EPC1, or
EPC1441 devices. FLEX 6000 devices can be configured with EPC1 or
EPC1441 devices. The EPC2, EPC1, or EPC1441 device stores
configuration data in its EPROM array and serially clocks data out with
an internal oscillator. The
OE
,
nCS
, and
DCLK
pins supply the control
signals for the address counter and the output tri-state buffer. The
configuration device sends a serial bitstream of configuration data to its
DATA
pin, which is routed to the
DATA0
or
DATA
input pin on the
APEX 20K, FLEX 10K, or FLEX 6000 device. One EPC1441 device can
configure an EPF10K10, EPF10K20, or EPF10K30 device. Figure 4 shows
an APEX 20K, FLEX 10K, or FLEX 6000 device configured with a single
EPC2, EPC1, or EPC1441 device.
8 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 4. APEX 20K, FLEX 10K, or FLEX 6000 Device Configured with an EPC2,
EPC1, or EPC1441 Configuration Device
Table 4 describes EPC2, EPC1, and EPC1441 pin functions during
APEX 20K, FLEX 10K, and FLEX 6000 device configuration.
APEX 20K, FLEX 10K,
or FLEX 6000 Device
(2)
Configuration
Device
DCLK
DATA
OE
nCS
nINIT_CONF
(3)
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND GND
(1) (1)
nCE
VCC
(1)
Notes:
(1) All pull-up resistors are 1 kΩ. The OE, nCS, and nINIT_CONF pins on EPC2 devices
have internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors
are used, external pull-up resistors should not be used on these pins. This EPC2
feature is available in MAX+PLUS II software versions 9.2 and higher. In
MAX+PLUS II version 9.1, this feature is not available and the internal pull-up
resistors on these pins are disabled.
(2) The diagram shows an APEX 20K or FLEX 10K device, which has MSEL0 and
MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground and the
DATA0 pin is named DATA. All other connections are the same for APEX 20K,
FLEX 10K, and FLEX 6000 devices.
(3) The nINIT_CONF pin is available on EPC2 devices only. If nINIT_CONF is not
available or not used, nCONFIG must be pulled to VCC either directly or through a
1-kΩ resistor.
Altera Corporation 9
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 4. EPC2, EPC1 & EPC1441 Pin Functions During APEX 20K, FLEX 10K & FLEX 6000 Configuration
(Part 1 of 2)
Pin Name Pin Number Pin
Type
Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
DATA 1 2 31 Output Serial data output. The DATA pin is tri-stated before
configuration when the nCS pin is high, and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK 242I/ODCLK is a clock output when configuring with a single
configuration device or when the configuration device is
the first device in a configuration device chain. DCLK is a
clock input for subsequent configuration devices in a
configuration device chain. Rising edges on DCLK
increment the internal address counter and present the
next bit of data to the DATA pin. The counter is
incremented only if the OE input is held high, the nCS input
is held low, and all configuration data has not been
transferred to the target device. When configuring with the
first EPC2 or EPC1 device in a configuration device chain
or with a single EPC1441 device, the DCLK pin drives low
after configuration is complete or when OE is low.
OE
(3)
3 8 7 Output Output enable (active high) and reset (active low). A low
logic level resets the address counter. A high logic level
enables DATA and permits the address counter to count.
If this pin is low (reset) during configuration, the internal
oscillator becomes inactive and DCLK drives low. See
“Error Detection Circuitry” on page 17.
nCS
(3)
4 9 10 Input Chip select input (active low). A low input allows DCLK to
increment the address counter and enables DATA to drive
out. If the EPC1 or EPC2 is reset with nCS low, the device
initializes as the first device in a configuration chain. If the
EPC1 or EPC2 device is reset with nCS high, the device
initializes as the subsequent device in the chain.
nCASC
(4)
6 12 15 Output Cascade select output (active low). This output goes low
when the address counter has reached its maximum
value. In a chain of EPC1 or EPC2 devices, the nCASC pin
of one device is connected to the nCS pin of the next
device, which permits DCLK to clock data from the next
EPC1 or EPC2 device in the chain.
10 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Notes:
(1) This package is available for EPC1 and EPC1441 devices only.
(2) This package is available for EPC2 and EPC1441 devices only.
(3) The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable 1-kΩ pull-up resistors. If
internal pull-up resistors are used, external pull-up resistors should not be used on these pins. This EPC2 feature is
available in the MAX+PLUS II version 9.2 software. In MAX+PLUS II version 9.1, the internal pull-up resistors on
these pins are disabled.
(4) The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading.
(5) This pin applies to EPC2 devices only.
(6) This instruction is supported by MAX+PLUS II software versions 9.2 and higher.
nINIT_CONF
(3), (5), (6)
– 13 16 Output Allows the INIT_CONF JTAG instruction to initiate
configuration. This pin is connected to the nCONFIG pin of
the FLEX or APEX device to initiate configuration from the
EPC2 via a JTAG instruction. If a chain of EPC2 devices
is used, only the first EPC2 has its nINIT_CONF pin tied
to the FLEX device’s nCONFIG pin.
(6)
TDI
(5)
– 11 13 Input JTAG data input pin. Connect this pin to VCC if the JTAG
circuitry is not used.
TDO
(5)
– 1 28 Output JTAG data output pin. Do not connect this pin if the JTAG
circuitry is not used.
TMS
(5)
– 19 25 Input JTAG mode select pin. Connect this pin to VCC if the
JTAG circuitry is not used.
TCK
(5)
– 3 32 Input JTAG clock pin. Connect this pin to ground if the JTAG
circuitry is not used.
VCCSEL – 5 3 Input Mode select for VCC supply. VCCSEL must be connected
to ground if the device uses a 5.0-V power supply (i.e.,
VCC = 5.0 V). VCCSEL must be connected to VCC if the
device uses a 3.3-V power supply (i.e., VCC = 3.3 V).
VPPSEL – 14 17 Input Mode select for VPP. VPPSEL must be connected to
ground if VPP uses a 5.0-V power supply
(i.e., VPP = 5.0 V). VPPSEL must be connected to VCC if
VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V).
VPP – 18 23 Power Programming power pin. For the EPC2 device, this pin is
normally tied to VCC. If the EPC2 VCC is 3.3 V, VPP can be
tied to 5.0 V to improve in-system programming times. For
EPC1 and EPC1441 devices, VPP must be tied to VCC.
VCC 7, 8 20 27 Power Power pin.
GND 5 10 12 Ground Ground pin. A 0.2-µF decoupling capacitor must be
placed between the VCC and GND pins.
Table 4. EPC2, EPC1 & EPC1441 Pin Functions During APEX 20K, FLEX 10K & FLEX 6000 Configuration
(Part 2 of 2)
Pin Name Pin Number Pin
Type
Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
Altera Corporation 11
Configuration Devices for APEX & FLEX Devices Data Sheet
APEX 20K, FLEX 10K & FLEX 6000 Configuration with Multiple
EPC2 or EPC1 Configuration Devices
When configuration data for APEX 20K, FLEX 10K, or FLEX 6000 devices
exceeds the capacity of a single EPC2 or EPC1 device, multiple EPC2 or
EPC1 devices can be cascaded together. (The EPC1441 device does not
support data cascading.) If multiple EPC2 or EPC1 devices are required,
the nCASC and nCS pins provide handshaking between the devices.
When configuring APEX 20K, FLEX 10K, or FLEX 6000 devices with
cascaded EPC2 or EPC1 devices, the position of the EPC2 or EPC1 device
in the chain determines its operation. When the first or master device in a
configuration device chain is powered up or reset and the nCS pin is
driven low, the master device controls configuration. The master device
supplies all clock pulses to one or more APEX or FLEX devices and to any
subsequent slave devices during configuration. The master EPC2 or EPC1
device also provides the first stream of data to the APEX or FLEX devices
during multi-device configuration. After the master EPC2 or EPC1 device
finishes sending configuration data, it drives its nCASC pin low, which
drives the nCS pin of the first slave EPC2 or EPC1 device low. This action
causes the slave EPC2 or EPC1 device to send configuration data to the
APEX or FLEX devices.
The master EPC2 or EPC1 device clocks all subsequent slave devices until
configuration is complete. Once all configuration data is transferred and
the nCS pin on the master EPC2 or EPC1 device is driven high by the
APEX or FLEX device’s CONF_DONE pin, the master EPC2 or EPC1 device
clocks 16 additional cycles to initialize the APEX or FLEX device(s). The
master EPC2 or EPC1 device then goes into zero-power (idle) state. If nCS
on the master EPC2 or EPC1 device is driven high before all configuration
data is transferred, or if nCS is not driven high after all configuration data
is transferred, the master EPC2 or EPC1 device drives the APEX or FLEX
device’s nSTATUS pin low, indicating a configuration error.
Configuration automatically restarts if the project is compiled with the
Auto-Restart Configuration on Frame Error option turned on in the
MAX+PLUS II software’s Global Project Device Options dialog box
(Assign menu).
Figure 5 shows an APEX 20K, FLEX 10K or FLEX 6000 device configured
with two EPC2 or EPC1 devices. Additional EPC2 or EPC1 devices can be
added by connecting nCASC to nCS of the subsequent slave EPC2 or EPC1
device in the chain and connecting DCLK, DATA, and OE in parallel.
12 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
1A mixture of FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and
3.3-V FLEX 6000 devices can be configured in the same chain. A
mixture of APEX 20K and APEX 20KE devices can be configured
in the same chain. See “Configuration Chain with Multiple
Voltage Levels” on page 19.
Figure 5. APEX 20K, FLEX 10K, or FLEX 6000 Device Configured with Two EPC2 or EPC1 Configuration
Devices
Notes:
(1) All pull-up resistors are 1 kΩ. The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable
1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these
pins. This EPC2 feature is available in MAX+PLUS II software versions 9.2 and higher. In MAX+PLUS II
version 9.1, this feature is not available and the internal pull-up resistors on these pins are disabled.
(2) The diagram shows a FLEX 10K or APEX 20K device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000
devices, MSEL is tied to ground and the DATA0 pin is named DATA. All other connections are the same for APEX 20K,
FLEX 10K, and FLEX 6000 devices.
(3) The nINIT_CONF pin is available on EPC2 devices only. If nINIT_CONF is not available or not used, nCONFIG must
be pulled to VCC either directly or through a 1-kΩ resistor.
Figure 6 shows two APEX 20K, FLEX 10K, or FLEX 6000 devices
configured with two EPC2 or EPC1 devices.
Configuration
Device 1
DCLK
DATA
OE
nCS
nINIT_CONF
(3)
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC
VCC
GND GND
(1)
nCE
VCC
DCLK
DATA
nCS
OE
Configuration
Device 2
(1)
(1)
nCASC
APEX 20K, FLEX 10K,
or FLEX 6000 Device
(2)
Altera Corporation 13
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 6. Two APEX 20K, FLEX 10K, or FLEX 6000 Devices Configured with Two EPC2 or EPC1 Configuration
Devices
Notes:
(1) All pull-up resistors are 1 kΩ. The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable
1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these
pins. This EPC2 feature is available in the MAX+PLUS II version 9.2 software. In MAX+PLUS II version 9.1, this
feature is not available and the internal pull-up resistors on these pins are disabled.
(2) The diagram shows a FLEX 10K device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL
is tied to ground and the DATA0 pin is named DATA.
(3) The nINIT_CONF pin is available on EPC2 devices only. If nINIT_CONF is not available or not used, nCONFIG must
be pulled to VCC either directly or through a 1-kΩ resistor.
f
For more information on FLEX 10K or FLEX 6000 device configuration, go
to Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000
Devices).
FLEX 8000 Device Configuration
FLEX 8000 devices differ from APEX 20K, FLEX 10K, and FLEX 6000
devices in that they have internal oscillators that can provide a DCLK
signal to the configuration device. The configuration device sends
configuration data out as a serial bitstream on the DATA output pin. This
data is routed into the FLEX 8000 device via the DATA0 input pin. The
EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V configuration devices
support this type of configuration.
Configuration
Device 1
DCLK
DATA
OE
nCS
nINIT_CONF
(3)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND
GND
nCE
VCC
DCLK
DATA
nCS
OE
Configuration
Device 2
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
GND
nCE
MSEL0
MSEL1
nCEO
(1) (1)(1)
nCASC
APEX 20K, FLEX 10K,
or FLEX 6000 Device
(2)
APEX 20K, FLEX 10K,
or FLEX 6000 Device
(2)
14 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
The EPC1 and EPC1441 can replace the EPC1213, EPC1064, and
EPC1064V configuration devices. The EPC1 or EPC1441 device
automatically emulates the EPC1213, EPC1064, or EPC1064V when it is
programmed with the appropriate POF. When the EPC1 or EPC1441
device is programmed with an EPC1213, EPC1064, or EPC1064V POF, the
FLEX 8000 device drives the EPC1 or EPC1441 device’s OE pin high and
clocks the EPC1 or EPC1441 device. One EPC1 device can store more
configuration data than the EPC1064, EPC1064V, EPC1213, or EPC1441
device. Therefore, designers can use one type of configuration device for
all FLEX devices. In addition, a single EPC1 or EPC1441 device can
configure any FLEX 8000 device.
For multi-device configuration of FLEX 8000 devices, the nCASC and nCS
pins provide handshaking between multiple configuration devices,
allowing several cascaded EPC1 or EPC1213 devices to serially configure
multiple FLEX 8000 devices. The EPC1441, EPC1064, and EPC1064V do
not support data cascading. Figure 7 shows a FLEX 8000 device
configured with a single EPC1, EPC1441, EPC1213, EPC1064, or
EPC1064V configuration device.
Figure 7. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213,
EPC1064, or EPC1064V Configuration Device
Note:
(1) All pull-up resistors are 1 kΩ.
FLEX 8000 Device
“0”
“0”
“0”
Configuration
Device
VCC
nCS
OE
DCLK
nS/P
MSEL1
MSEL0
DATA0
nCONFIG
CONF_DONE
nSTATUS
DCLK DATA
VCC
(1)
VCC
(1)
Altera Corporation 15
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 8 shows three FLEX 8000 devices configured with two EPC1 or
EPC1213 configuration devices.
Figure 8. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices
Note:
(1) All pull-up resistors are 1 kΩ.
FLEX 8000 Device 1
“0”
“0”
“0”
Configuration
Device 1
VCC
nCS
OE
DCLK
nS/P
MSEL1
MSEL0
DATA0
nCONFIG
CONF_DONE
nSTATUS
DCLK
nCASC
DATA
VCC
(1)
VCC
VCC
FLEX 8000 Device 2
“0”
“1”
“0”
nS/P
MSEL1
MSEL0
DCLK
DATA0
nCONFIG
CONF_DONE
nSTATUS
FLEX 8000 Device 3
“0”
“1”
“0”
nS/P
MSEL1
MSEL0
DCLK
DATA0
nCONFIG
CONF_DONE
nSTATUS
Configuration
Device 2
nCS
OE
DCLK
DATA
VCC
VCC
VCC
(1)
(1)
(1)
(1)
(1)
16 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 5 describes the pin functions of all configuration devices during
FLEX 8000 device configuration.
Notes:
(1) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.
(2) This package is available for EPC1441, EPC1064, and EPC1064V devices only.
(3) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices
support data cascading for FLEX 8000 devices.
Table 5. Configuration Device Pin Functions During FLEX 8000 Device Configuration
Pin Name Pin Number Pin
Type
Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
DATA 12 31 Output Serial data output. The DATA pin is tri-stated before
configuration when the nCS pin is high and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK 24 2
Input DCLK is a clock input when using EPC1, EPC1213,
EPC1064, and EPC1064V configuration devices. Rising
edges on DCLK increment the internal address counter
and present the next bit of data to the DATA pin. The
counter is incremented only if the OE input is held high,
the nCS input is held low, and all configuration data has
not been transferred to the target device.
OE 38 7
Input Output enable (active high) and reset (active low). A low
logic level resets the address counter. A high logic level
enables DATA and permits the address counter to count.
nCS
(3)
4 9 10 Input Chip-select input (active low). A low input allows DCLK to
increment the address counter and enables DATA.
nCASC 6 12 15 Output Cascade-select output (active low). This output goes low
when the address counter has reached its maximum
value. The nCASC output is usually connected to the nCS
input of the next device in a configuration chain, so the
next DCLK clocks data out of the next device.
VCC 7, 8 20 27 Power Power pin.
GND 5 10 12 Ground Ground pin. A 0.2-µF decoupling capacitor must be
placed between the VCC and GND pins.
Altera Corporation 17
Configuration Devices for APEX & FLEX Devices Data Sheet
f
For more information on FLEX 8000 device configuration, go to the
following documents:
■Application Note 33 (Configuring FLEX 8000 Devices)
■Application Note 38 (Configuring Multiple FLEX 8000 Devices)
Power &
Operation
The following section describes Power-On Reset (POR) delay, error
detection, and 3.3-V and 5.0-V operation of Altera configuration devices.
Power-On Reset
During initial power-up, a POR delay occurs to permit voltage levels to
stabilize. When configuring an APEX 20K, FLEX 10K, or FLEX 6000
device with an EPC2, EPC1, or EPC1441 device, the POR delay occurs
inside the configuration device. However, when configuring a FLEX 8000
device with an EPC1213, EPC1064, or EPC1064V device, the POR delay
occurs inside the FLEX 8000 device. In either case, the POR delay is
typically 100 ms, with a maximum of 200 ms.
Error Detection Circuitry
The EPC2, EPC1, and EPC1441 configuration devices have built-in error
detection circuitry for configuring APEX 20K, FLEX 10K, and FLEX 6000
devices only.
Built-in error-detection circuitry uses the nCS pin of the configuration
device, which monitors the CONF_DONE pin on the APEX 20K, FLEX 10K,
or FLEX 6000 device. An error condition occurs if the CONF_DONE pin does
not go high after all the configuration data has been sent, or if the
CONF_DONE pin goes high before the configuration device has completed
sending configuration data. When an error condition occurs, the
configuration device drives its OE pin low, which drives the APEX 20K,
FLEX 10K, or FLEX 6000 device’s nSTATUS pin low, indicating an error.
After an error, configuration automatically restarts if the Auto-Restart
Configuration on Frame Error option is turned on in the Global Project
Device Options dialog box (Assign menu) in the MAX+PLUS II software.
For APEX 20K devices, the Quartus software provides a similar option.
In addition, if the APEX 20K, FLEX 10K, or FLEX 6000 device detects a
cyclic redundancy code (CRC) error in the received data, it may also flag
the error by driving nSTATUS low. This low signal on nSTATUS resets the
configuration device, allowing reconfiguration. CRC checking is
performed when configuring all APEX 20K, FLEX 10K, and FLEX 6000
devices.
18 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
3.3-V or 5.0-V Operation
EPC2, EPC1, and EPC1441 devices can configure 5.0-V, 3.3-V, or 2.5-V
devices. For each configuration device, an option must be set for 5.0-V or
3.3-V operation. For EPC1 and EPC1441 configuration devices, the Use
Low-Voltage Configuration EPROM option in the Global Project Device
Options dialog box (Assign menu) in the MAX+PLUS II software sets this
parameter. (For APEX 20K devices, the Quartus software provides a
similar option.) For EPC2 devices, this option is set externally by the
VCCSEL pin. In addition, the EPC2 device has an externally controlled
option, set by the VPPSEL pin, to adjust the programming voltage to 5.0 V
or 3.3 V.
The functions of the VCCSEL and VPPSEL pins are described below.
■VCCSEL pin—For EPC2 configuration devices, 5.0-V or 3.3-V
operation is controlled by the VCCSEL option pin. The device
functions in 5.0-V mode when VCCSEL is connected to GND; the device
functions in 3.3-V mode when VCCSEL is connected to VCC.
■VPPSEL pin—The EPC2 VPP programming power pin is normally tied
to VCC. For EPC2 devices operating with a 3.3-V supply, it is possible
to improve EPC2 in-system programming times by providing VPP
with a 5.0-V supply. For all other devices, VPP must be tied to VCC.
The EPC2 device’s VPPSEL pin must be set in accordance with the
EPC2 VPP pin. If the VPP pin is supplied by a 5.0-V supply, VPPSEL
must be connected to GND; if the VPP pin is supplied by a 3.3-V power
supply, VPPSEL must be connected to VCC.
Table 6 describes the relationship between the VCC and VPP voltage levels
and the required logic level for VCCSEL and VPPSEL (i.e., high or low logic
level).
Table 6. VCCSEL & VPPSEL Pin Functions on the EPC2
VCC Voltage Level
(V)
VPP Voltage Level
(V)
VCCSEL Pin Logic
Level
VPPSEL Pin Logic
Level
3.3 3.3 High High
3.3 5.0 High Low
5.0 5.0 Low Low
Altera Corporation 19
Configuration Devices for APEX & FLEX Devices Data Sheet
For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is
controlled by a programming bit in the POF. The programming bit value
is determined by the core supply voltage of the targeted device during
design compilation with the MAX+PLUS II software. For example, EPC1
devices are programmed automatically to operate in 3.3-V mode when
configuring FLEX 10KA devices, which have a VCC voltage of 3.3 V. In
this example, the EPC1 device’s VCC pin is connected to a 3.3-V power
supply.
Designers may choose to set the configuration device for low voltage
when using the MultiVoltTM feature, which allows an APEX or FLEX
device to bridge between systems operating with different voltages.
When compiling for 3.3-V FLEX 6000 devices, set the configuration device
for low-voltage operation. To set the EPC1 and EPC1441 configuration
devices for low-voltage operation, turn on the Low-Voltage I/O option in
the Global Project Device Options dialog box (Assign menu) in the
MAX+PLUS II software.
Configuration Chain with Multiple Voltage Levels
An EPC2 or EPC1 device can configure a device chain with multiple
voltage levels. All 3.3-V and 2.5-V FLEX and APEX devices can be driven
by higher-voltage signals.
When configuring a mixed-voltage device chain, the FLEX and APEX
devices’ VCCINT and VCCIO pins may be connected to 2.5 V, 3.3 V, or 5.0 V,
depending upon the device. The configuration device may be powered at
3.3 V or 5.0 V. If an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V
configuration device is powered at 3.3 V, the nSTATUS and CONF_DONE
pull-up resistors must be connected to 3.3 V. If these configuration devices
are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors can
be connected to 3.3 V or 5.0 V.
At 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except DATA, DCLK,
nCASC, and TDO. The DATA, DCLK, and nCEO pins are used only to interface
between the EPC2 and the APEX 20K, FLEX 10K, or FLEX 6000 device it
is configuring; TDO is an output only. The voltage tolerances of all EPC2
pins at 5.0 V and 3.3 V are listed in Table 7.
20 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
f
For more information on APEX 20K, FLEX 10K, FLEX 8000, and
FLEX 6000 devices, go to the following documents in this data book:
■APEX 20K Programmable Logic Device Family Data Sheet
■FLEX 10K Embedded Programmable Logic Family Data Sheet
■FLEX 10KE Embedded Programmable Logic Family Data Sheet
■FLEX 8000 Programmable Logic Device Family Data Sheet
■FLEX 6000 Programmable Logic Device Family Data Sheet
Programming
& Configuration
File Support
The Quartus and MAX+PLUS II development systems provide
programming support for Altera configuration devices. The Quartus and
MAX+PLUS II software automatically generates a POF to program each
configuration device in a project. In a multi-device project, the software
can combine the programming files for multiple APEX or FLEX devices
into one or more configuration devices. The software allows you to select
the appropriate configuration device to most efficiently store the data for
each APEX and FLEX device. Moreover, when compiling for FLEX 10KA
or FLEX 10KE devices, the MAX+PLUS II software automatically defaults
to generate the EPC1 or EPC1441 POF with the programming bit set for
3.3-V operation.
All of Altera’s configuration devices are programmable using Altera
programming hardware in conjunction with the Quartus or
MAX+PLUS II software. In addition, many manufacturers offer
programming hardware that supports other Altera configuration devices.
Table 7. EPC2 Input & Bidirectional Pin Voltage Tolerance
Pin 5.0-V Operation 3.3-V Operation
5.0-V
Tolerant
3.3-V
Tolerant
5.0-V
Tolerant
3.3-V
Tolerant
DATA vv v
DCLK vv v
nCASC vv v
OE vvv v
nCS vvv v
VCCSEL vvv v
VPPSEL vvv v
nINIT_CONF vvv v
TDI vvv v
TMS vvv v
TCK vvv v
TDO vv v
Altera Corporation 21
Configuration Devices for APEX & FLEX Devices Data Sheet
The EPC2 configuration device can be programmed in-system through its
industry-standard 4-pin JTAG interface. ISP capability in the EPC2
provides ease in prototyping and updating FLEX and APEX device
functionality. The EPC2 configuration device can be programmed
in-system via test equipment using SVF Files, Jam Files (.jam), or Jam
Byte-Code Files (.jbc), embedded processors using the Jam programming
and test language, and the MAX+PLUS II software via the
ByteBlasterMV, ByteBlaster, or BitBlaster download cables. When
programming multiple EPC2 devices in a JTAG chain, the Quartus and
MAX+PLUS II software and other programming methods employ
concurrent programming to simultaneously program multiple devices
and reduce programming time. EPC2 devices can be programmed and
erased up to 100 times.
After programming an EPC2 device in-system, FLEX or APEX device
configuration can be initiated by including the EPC2 JTAG configuration
instruction. See Table 8 on page 22.
f
For more information, go to the following documents:
■Altera Programming Hardware Data Sheet
■Programming Hardware Manufacturers
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■ByteBlaster Parallel Port Download Cable Data Sheet
■BitBlaster Serial Download Cable Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Testing
The EPC2 provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. JTAG boundary-scan testing can be performed
before or after configuration, but not during configuration. The EPC2
supports the JTAG instructions shown in Table 8.
22 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
f
For more information, see Application Note 39 (IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
Figure 9 shows the timing requirements for the JTAG signals.
Table 8. EPC2 JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows a snapshot of a signal at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing results at the input pins.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during
normal device operation.
IDCODE Selects the device IDCODE register and places it between TDI and TDO, allowing the
device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2 is
shown below:
0000 0001000000000010 00001101110 1
USERCODE Selects the USERCODE register and places it between TDI and TDO, allowing the
USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a
programmable user-defined pattern.
ISP Instructions These instructions are used when programming an EPC2 device via JTAG ports with
a ByteBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam File
(.jam), Jam Byte-Code File (.jbc), or SVF File via an embedded processor.
INIT_CONF This function allows the user to initiate the FLEX configuration process by tying
nINIT_CONF to the FLEX device(s) nCONFIG pin(s). After this instruction is updated,
the nINIT_CONF pin is driven low. When the Initiate Configuration instruction is
cleared, nINIT_CONF is released, which starts the FLEX device configuration. This
instruction is used by the MAX+PLUS II software, Jam Files, and JBC Files.
Altera Corporation 23
Configuration Devices for APEX & FLEX Devices Data Sheet
Figure 9. EPC2 JTAG Waveforms
Table 9 shows the timing parameters and values for configuration
devices.
Operating
Conditions
Tables 10 through 17 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for configuration devices.
Table 9. JTAG Timing Parameters & Values
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clock high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid output 25 ns
tJPXZ JTAG port valid output to high impedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high-impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
24 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 10. Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground
(2)
–2.0 7.0 V
VIDC input voltage With respect to ground
(2)
–2.0 7.0 V
IMAX DC VCC or ground current 50 mA
IOUT DC output current, per pin –25 25 mA
PDPower dissipation 250 mW
TSTG Storage temperature No bias –65 150 ° C
TAMB Ambient temperature Under bias –65 135 ° C
TJJunction temperature Under bias 135 ° C
Table 11. Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage for 5.0-V operation
(3), (4)
4.75 (4.50) 5.25 (5.50) V
Supply voltage for 3.3-V operation
(3), (4)
3.0 (3.0) 3.6 (3.6) V
VIInput voltage With respect to ground –0.3 VCC + 0.3
(5)
V
VOOutput voltage 0V
CC V
TAOperating temperature For commercial use 0 70 ° C
For industrial use –40 85 ° C
tRInput rise time 20 ns
tFInput fall time 20 ns
Table 12. DC Operating Conditions
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage 2.0 VCC + 0.3
(5)
V
VIL Low-level input voltage –0.3 0.8 V
VOH 5.0-V mode high-level TTL output voltage IOH = –4 mA DC
(6)
2.4 V
3.3-V mode high-level CMOS output
voltage IOH = –0.1 mA DC
(6)
VCC – 0.2 V
VOL Low-level output voltage IOL = 4 mA DC
(6)
0.4 V
IIInput leakage current VI = VCC or ground –10 10 µA
IOZ Tri-state output off-state current VO = VCC or ground –10 10 µA
Altera Corporation 25
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 13. EPC1213, EPC1064 & EPC1064V Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
ICC0 VCC supply current (standby) 100 200 µA
ICC1 VCC supply current
(during configuration) 10 50 mA
Table 14. EPC2 Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
ICC0 VCC supply current (standby) VCC = 5.0 V or 3.3 V 50 100 µA
ICC1 VCC supply current (during configuration) VCC = 5.0 V or 3.3 V 18 50 mA
Table 15. EPC1 Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
ICC0 VCC supply current (standby) 50 100 µA
ICC1 VCC supply current (during configuration) VCC = 5.0 V 30 50 mA
VCC = 3.3 V 10 16.5 mA
Table 16. EPC1441 Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
ICC0 VCC supply current (standby) 30 60 µA
ICC1 VCC supply current (during configuration) VCC = 5.0 V 15 30 mA
ICC1 VCC supply current (during configuration) VCC = 3.3 V 5 10 mA
Table 17. Capacitance Note (7)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF
COUT Output pin capacitance VOUT = 0 V, f = 1.0 MHz 10 pF
26 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods shorter than 20 ns under no-load conditions.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms.
(5) Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V VCC. See Table 7 on page 20.
(6) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or
CMOS output current.
(7) Capacitance is sample-tested only.
Tables 18 through 22 show the device configuration parameters for
FLEX 10K, FLEX 8000, and FLEX 6000 devices.
Table 18. FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V
Symbol Parameter Conditions Min Typ Max Unit
tCE OE high to first clock delay 200 ns
tOEZX OE high to data output enabled 50 ns
tCO DCLK to data out delay 20 ns
tMCH DCLK high time for the first device in the
configuration chain 30 50 75 ns
tMCL DCLK low time for the first device in the
configuration chain 30 50 75 ns
fCK Clock frequency 6.7 10 16 MHz
tSCH DCLK high time for subsequent devices 30 ns
tSCL DCLK low time for subsequent devices 30 ns
tCASC CLK rising edge to nCASC 20 ns
tCCA nCS to nCASC cascade delay 10 ns
fCDOE CLK to data enable/disable 20 ns
tOEC OE low to CLK disable delay 20 ns
tNRCAS OE low (reset) to nCASC delay 25 ns
tNRR OE low time (reset) minimum 100 ns
Altera Corporation 27
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 19. APEX 20K & FLEX 10K Device Configuration Parameters Using EPC2 Devices at 3.3-V
Symbol Parameter Conditions Min Typ Max Unit
tCE OE high to first clock delay 300 ns
tOEZX OE high to data output enabled 80 ns
tCO DCLK to data out delay 30 ns
tMCH DCLK high time for the first device in the
configuration chain 40 65 100 ns
tMCL DCLK low time for the first device in the
configuration chain 40 65 100 ns
fCK Clock frequency 5 7.7 12.5 MHz
tSCH DCLK high time for subsequent devices 40 ns
tSCL DCLK low time for subsequent devices 40 ns
tCASC CLK rising edge to nCASC 25 ns
tCCA nCS to nCASC cascade delay 15 ns
fCDOE CLK to data enable/disable 30 ns
tOEC OE low to CLK disable delay 30 ns
tNRCAS OE low (reset) to nCASC delay 30 ns
tNRR OE low time (reset) minimum 100 ns
Table 20. FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at
5.0-V
Symbol Parameter Conditions Min Typ Max Unit
tCE OE high to first clock delay 200 ns
tOEZX OE high to data output enabled 50 ns
tCO DCLK to data out delay 20 ns
tMCH DCLK high time for the first device in the
configuration chain 30 50 75 ns
tMCL DCLK low time for the first device in the
configuration chain 30 50 75 ns
fCK Clock frequency 6.7 10 16 MHz
tSCH DCLK high time for subsequent devices 30 ns
tSCL DCLK low time for subsequent devices 30 ns
tCASC CLK rising edge to nCASC 20 ns
tCCA nCS to nCASC cascade delay 10 ns
fCDOE CLK to data enable/disable 20 ns
tOEC OE low to CLK disable delay 20 ns
tNRCAS OE low (reset) to nCASC delay 25 ns
tNRR OE low time (reset) minimum 100 ns
28 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Table 21. FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at
3.3-V
Symbol Parameter Conditions Min Typ Max Unit
tCE OE high to first clock delay 300 ns
tOEZX OE high to data output enabled 80 ns
tCO DCLK to data out delay 30 ns
tMCH DCLK high time for the first device in the
configuration chain 50 125 250 ns
tMCL DCLK low time for the first device in the
configuration chain 50 125 250 ns
fCK Clock frequency 2 4 10 MHz
tSCH DCLK high time for subsequent devices 50 ns
tSCL DCLK low time for subsequent devices 50 ns
tCASC CLK rising edge to nCASC 25 ns
tCCA nCS to nCASC cascade delay 15 ns
fCDOE CLK to data enable/disable 30 ns
tOEC OE low to CLK disable delay 30 ns
tNRCAS OE low (reset) to nCASC delay 30 ns
tNRR OE low time (reset) minimum 100 ns
Altera Corporation 29
Configuration Devices for APEX & FLEX Devices Data Sheet
Revision
History
The information contained in the Configuration Devices for APEX & FLEX
Devices Data Sheet version 10.03 supersedes information published in
previous versions.
Version 10.03
Version 10.03 of the Configuration Devices for APEX & FLEX Devices Data
Sheet contains the following changes:
■APEX devices in Table 2 were updated.
■Table 3 was added.
Table 22. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
EPC1064V Devices
Symbol Parameter Conditions EPC1064V EPC1064
EPC1213
EPC1
EPC1441
Unit
Min Max Min Max Min Max
tOEZX OE high to DATA output enabled 75 50 50 ns
tCSZX nCS low to DATA output enabled 75 50 50 ns
tCSXZ nCS high to DATA output disabled 75 50 50 ns
tCSS nCS low setup time to first DCLK rising edge 150 100 50 ns
tCSH nCS low hold time after DCLK rising edge 0 0 0 ns
tDSU Data setup time before rising edge on DCLK 75 50 50 ns
tDH Data hold time after rising edge on DCLK 000ns
t
CO DCLK to DATA out delay 100 75 75 ns
tCK Clock period 240 160 100 ns
fCK Clock frequency 4 6 8 MHz
tCL DCLK low time 120 80 50 ns
tCH DCLK high time 120 80 50 ns
tXZ OE low or nCS high to DATA output disabled 75 50 50 ns
tOEW OE pulse width to guarantee counter reset 150 100 100 ns
tCASC Last DCLK + 1 to nCASC low delay 90 60 50 ns
tCKXZ Last DCLK + 1 to DATA tri-state delay 75 50 50 ns
tCEOUT nCS high to nCASC high delay 150 100 100 ns
30 Altera Corporation
Configuration Devices for APEX & FLEX Devices Data Sheet
Version 10.02
Version 10.02 of the Configuration Devices for APEX & FLEX Devices Data
Sheet contains the following changes:
■Table 2 was updated.
■The IDCODE for the EPC2 configuration device was corrected in
Table 8.
Version 10.01
Version 10.01 of the Configuration Devices for APEX & FLEX Devices Data
Sheet contains updates to Tables 4, 11, 12, 20, and 21.
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