Si88x2x Data Sheet Dual Digital Isolators with DC-DC Converter The Si88xx integrates Silicon Labs' proven digital isolator technology with an on-chip isolated dc-dc converter that provides regulated output voltages of 3.3 or 5.0 V (or >5 V with external components) at peak output power levels of up to 5 W. These devices provide up to two digital channels. The dc-dc converter has user-adjustable frequency for minimizing emissions, a soft-start function for safety, a shutdown option and loop compensation. The device requires only minimal passive components and a miniature transformer. The ultra-low-power digital isolation channels offer substantial data rate, propagation delay, size and reliability advantages over legacy isolation technologies. Data rates up to 100 Mbps max are supported, and all devices achieve propagation delays of only 23 ns max. Ordering options include a choice of dc-dc converter features, isolation channel configurations and a fail-safe mode. All products are certified by UL, CSA, VDE, and CQC. KEY FEATURES * High-speed isolators with integrated dc-dc converter * Fully-integrated secondary sensing feedback-controlled converter with dithering for low EMI * dc-dc converter peak efficiency of 83% with external power switch * Up to 5 W isolated power with external power switch * Options include dc-dc shutdown, frequency control, and soft start * Standard Voltage Conversion * 3/5 V to isolated 3/5 V * 24 V to isolated 3/5 V * 3/5 V to isolated 24 V Applications: * * * * Industrial automation systems Hybrid electric and electric vehicles Isolated power supplies Inverters * 24 V to isolated 24 V * Data acquisition * Motor control * PLCs, distributed control systems * 18 ns typical prop delay * Highly-reliable: 100 year lifetime * High electromagnetic immunity and ultralow emissions * RoHS compliant packages * SOIC-20 wide body Safety Approval (Pending): * UL 1577 recognized * Up to 5000 Vrms for 1 minute * CSA component notice 5A approval * IEC 60950 * Precise timing on digital isolators * 0 - 100 Mbps * VDE certification conformity * VDE0884-10 * CQC certification approval * GB4943.1 * SOIC-16 wide body * Isolation of up to 5000 Vrms * High transient immunity of 100 kV/s (typical) * AEC-Q100 qualified * Wide temp range * -40 to +125 C silabs.com | Building a more connected world. Rev. 1.02 Table of Contents 1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Digital Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 DC-DC Converter Application Information . . . 3.3.1 Shutdown . . . . . . . . . . . . 3.3.2 Soft-Start . . . . . . . . . . . . 3.3.3 Programmable Frequency. . . . . . . 3.3.4 External Transformer Driver . . . . . . 3.3.5 VREGA, VREGB . . . . . . . . . . 3.3.6 Output Voltage Control . . . . . . . . 3.3.7 Compensation. . . . . . . . . . . 3.3.8 Thermal Protection . . . . . . . . . 3.3.9 Cycle Skipping . . . . . . . . . . 3.3.10 Low-Voltage Configuration . . . . . . 3.3.11 Low-Voltage to High-Voltage Configuration 3.3.12 High-Voltage to Low-Voltage Configuration 3.3.13 High-Voltage to High-Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 8 . 8 . 8 . 8 . 8 . 8 . 9 . 9 . 9 .10 .11 .12 .13 3.4 Transformer Design . . . . . . . . . . . . . . . . . . .14 . . . 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Calculating Total Current Consumption . . . . . . . . . . . . . . . . . . . . . .28 5. Digital Isolator Device Operation . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.3 Layout Recommendations . 5.3.1 Supply Bypass . . . 5.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 .29 .29 5.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.5 Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . .30 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 Package Outline: 20-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . .39 7.2 Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . .41 8. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Land Pattern: 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . .43 8.2 Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . .44 9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 silabs.com | Building a more connected world. Rev. 1.02 | 2 9.1 Si88x2x Top Marking: 20-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . .45 9.2 Si88x2x Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . .46 10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 silabs.com | Building a more connected world. Rev. 1.02 | 3 Si88x2x Data Sheet Features List 1. Features List * High-speed isolators with integrated dc-dc converter * Fully-integrated secondary sensing feedback-controlled converter with dithering for low EMI * dc-dc converter peak efficiency of 83% with external power switch * Up to 5 W isolated power with external power switch * Options include dc-dc shutdown, frequency control, and soft start * Standard Voltage Conversion * 3/5 V to isolated 3/5 V * 24 V to isolated 3/5 V * 3/5 V to isolated 24 V * 24 V to isolated 24 V * Precise timing on digital isolators * 0 - 100 Mbps * 18 ns typical prop delay silabs.com | Building a more connected world. * Highly-reliable: 100 year lifetime * High electromagnetic immunity and ultra-low emissions * RoHS compliant packages * SOIC-20 wide body * SOIC-16 wide body * Isolation of up to 5000 Vrms * High transient immunity of 100 kV/s (typical) * AEC-Q100 qualified * Wide temp range * -40 to +125 C Rev. 1.02 | 4 Si88x2x Data Sheet Ordering Guide 2. Ordering Guide Table 2.1. Si88x2x Ordering Guide1,2,3,4 DC-DC Shutdown Soft Start Frequency Control External Switch Forward Digital Reverse Digital Insulation Rating (kVrms) Package Si88220BC-IS Y N N N 2 0 3.75 WB SOIC-16 Si88221BC-IS Y N N N 1 1 3.75 WB SOIC-16 Si88222BC-IS Y N N N 0 2 3.75 WB SOIC-16 Si88320BC-IS Y Y Y N 2 0 3.75 WB SOIC-20 Si88321BC-IS Y Y Y N 1 1 3.75 WB SOIC-20 Si88322BC-IS Y Y Y N 0 2 3.75 WB SOIC-20 Si88420BC-IS N N N Y 2 0 3.75 WB SOIC-16 Si88421BC-IS N N N Y 1 1 3.75 WB SOIC-16 Si88422BC-IS N N N Y 0 2 3.75 WB SOIC-16 Si88620BC-IS Y Y Y Y 2 0 3.75 WB SOIC-20 Si88621BC-IS Y Y Y Y 1 1 3.75 WB SOIC-20 Si88622BC-IS Y Y Y Y 0 2 3.75 WB SOIC-20 Si88220EC-IS Y N N N 2 0 3.75 WB SOIC-16 Si88221EC-IS Y N N N 1 1 3.75 WB SOIC-16 Si88222EC-IS Y N N N 0 2 3.75 WB SOIC-16 Si88320EC-IS Y Y Y N 2 0 3.75 WB SOIC-20 Si88321EC-IS Y Y Y N 1 1 3.75 WB SOIC-20 Si88322EC-IS Y Y Y N 0 2 3.75 WB SOIC-20 Si88420EC-IS N N N Y 2 0 3.75 WB SOIC-16 Si88421EC-IS N N N Y 1 1 3.75 WB SOIC-16 Si88422EC-IS N N N Y 0 2 3.75 WB SOIC-16 Si88620EC-IS Y Y Y Y 2 0 3.75 WB SOIC-20 Si88621EC-IS Y Y Y Y 1 1 3.75 WB SOIC-20 Si88622EC-IS Y Y Y Y 0 2 3.75 WB SOIC-20 Si88220BD-IS Y N N N 2 0 5.0 WB SOIC-16 Si88221BD-IS Y N N N 1 1 5.0 WB SOIC-16 Si88222BD-IS Y N N N 0 2 5.0 WB SOIC-16 Si88320BD-IS Y Y Y N 2 0 5.0 WB SOIC-20 Si88321BD-IS Y Y Y N 1 1 5.0 WB SOIC-20 Si88322BD-IS Y Y Y N 0 2 5.0 WB SOIC-20 Ordering Part Number Available Now Sampling Now silabs.com | Building a more connected world. Rev. 1.02 | 5 Si88x2x Data Sheet Ordering Guide Ordering Part Number DC-DC Shutdown Soft Start Frequency Control External Switch Forward Digital Reverse Digital Insulation Rating (kVrms) Package Si88420BD-IS N N N Y 2 0 5.0 WB SOIC-16 Si88421BD-IS N N N Y 1 1 5.0 WB SOIC-16 Si88422BD-IS N N N Y 0 2 5.0 WB SOIC-16 Si88620BD-IS Y Y Y Y 2 0 5.0 WB SOIC-20 Si88621BD-IS Y Y Y Y 1 1 5.0 WB SOIC-20 Si88622BD-IS Y Y Y Y 0 2 5.0 WB SOIC-20 Si88220ED-IS Y N N N 2 0 5.0 WB SOIC-16 Si88221ED-IS Y N N N 1 1 5.0 WB SOIC-16 Si88222ED-IS Y N N N 0 2 5.0 WB SOIC-16 Si88320ED-IS Y Y Y N 2 0 5.0 WB SOIC-20 Si88321ED-IS Y Y Y N 1 1 5.0 WB SOIC-20 Si88322ED-IS Y Y Y N 0 2 5.0 WB SOIC-20 Si88420ED-IS N N N Y 2 0 5.0 WB SOIC-16 Si88421ED-IS N N N Y 1 1 5.0 WB SOIC-16 Si88422ED-IS N N N Y 0 2 5.0 WB SOIC-16 Si88620ED-IS Y Y Y Y 2 0 5.0 WB SOIC-20 Si88621ED-IS Y Y Y Y 1 1 5.0 WB SOIC-20 Si88622ED-IS Y Y Y Y 0 2 5.0 WB SOIC-20 Notes: 1. All packages are RoHS-compliant with peak solder reflow temperatures of 260C according to the JEDEC industry standard classifications. 2. "Si" and "SI" are used interchangeably. 3. AEC-Q100 qualified. 4. All Si88xxxEx product options are default output high on input power loss. All Si88xxxBx product options are default low. See Section 5. Digital Isolator Device Operation for more details about default output behavior. silabs.com | Building a more connected world. Rev. 1.02 | 6 Si88x2x Data Sheet Functional Description 3. Functional Description 3.1 Theory of Operation The Si88xx family of products is capable of transmitting and receiving digital data signals from an isolated power domain to a local system power domain with up to 5 kV of isolation. Each part has four unidirectional digital isolation channels. In addition, Si88xx products include an integrated controller and switches for a dc-dc converter which regulates output voltage by sensing it on the isolated side. 3.2 Digital Isolation The operation of an Si88xx digital channel is analogous to that of a digital buffer, except an RF carrier transmits data across the isolation barrier. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at startup. A simplified block diagram for a single Si88xx channel is shown in Figure 3.1 Simplified Si88xx Channel Diagram on page 7. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 3.1. Simplified Si88xx Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a silicon dioxide capacitive isolation barrier. In the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See the figure below for more details. Input Signal Modulation Signal Output Signal Figure 3.2. Modulation Scheme silabs.com | Building a more connected world. Rev. 1.02 | 7 Si88x2x Data Sheet Functional Description 3.3 DC-DC Converter Application Information The Si88xx isolated dc-dc converter is based on a modified fly-back topology and uses an external transformer and Schottky rectifying diode for low cost and high operating efficiency. The PWM controller operates in closed-loop, peak current mode control and generates isolated output voltages with 2 W average output power at 5.0 V. Options are available for up to 24 Vdc input or output operation and externally configured switching frequency. The dc-dc controller modulates a pair of internal primary-side power switches (see Figure 3.3 Si883xx Block Diagram: 3 V-5 V Input to 3 V-5 V Output on page 10) to generate an isolated voltage at external diode D1 cathode. Closed-loop feedback is provided by a compensated error amplifier, which compares the voltage at the VSNS pin to an internal voltage reference. The resulting error voltage is fed back through the isolation barrier via an internal feedback path to the controller, thus completing the control loop. For higher input supply voltages than 5 V, an external FET Q2 is modulated by a driver pin ESW as shown in (see Figure 3.5 Si886xx Block Diagram: 24 V Input to 5 V Output on page 12). A shunt resistor based voltage sense pin RSN provides current sensing capability to the controller. Additional features include an externally-triggered shutdown of the converter functionality using the SH pin and a programmable soft start configured by a capacitor connected to the SS pin. The Si88xx can be used in low- or high-voltage configurations. These features and configurations are explained in more detail below. 3.3.1 Shutdown This feature allows the operation of the dc-dc converter to be shut down when asserted high. This function is provided by pin 6 (labeled "SH" on the Si882xx) and pin 7 (labeled "SH_FC" on the Si883xx and Si886xx). This feature is not available on the Si884xx. Pin 6 or pin 7 provide the exact same functionality and shut down the dc-dc converter when asserted high. For normal operation, pins 6 and 7 should be connected to ground. 3.3.2 Soft-Start The dc-dc controller has an internal timer that controls the power conversion start-up to limit inrush current. There is also the Soft Start option where users can program the soft start up by an external capacitor connected to the SS pin. This feature is available on the Si883xx and the Si886xx. 3.3.3 Programmable Frequency The frequency of the PWM modulator is set to a default of 250 kHz for Si882xx/4xx. Users can program their desired frequency within a given band of 200 kHz to 800 kHz by controlling the time constant of an external RC connected to the SH_FC and SS pins for Si883xx/ 6xx. 3.3.4 External Transformer Driver The dc-dc controller has internal switches (VSW) for driving the transformer with up-to a 5.5 V voltage supply. For higher voltages on the primary side, a driver output (ESW) is provided that can drive an external NMOS power transistor for driving the transformer. When this configuration is used, a shunt resistor based voltage sense pin (RSN) provides current sensing to the controller. 3.3.5 VREGA, VREGB For supporting voltages greater than 5.5 V, an internal voltage regulator (VREGA, VREGB) needs to be used in conjunction with an external NPN transistor, a resistor and a capacitor to provide regulated voltage to the IC. 3.3.6 Output Voltage Control The isolated output voltage (VOUT) is sensed by a resistor divider that provides feedback to the controller through the VSNS pin. The voltage error is encoded and transmitted back to the primary side controller across the isolation barrier, which in turn changes the duty cycle of the transformer driver. The equation for VOUT is as follows: ( VOUT = VSNS x 1 + silabs.com | Building a more connected world. ) R1 + R1 x I OFFSET R2 Rev. 1.02 | 8 Si88x2x Data Sheet Functional Description 3.3.7 Compensation The dc-dc converter uses peak current mode control. The loop is compensated by connecting an external resistor in series with a capacitor from the COMP pin to GNDB. The compensation resistance, RCOMP is fixed at 49.9 k for Si882xx/3xx and 100 k for Si884xx/6xx to match internal resistance. Capacitance value is given by the following equation, where fC is crossover frequency: CCOMP = 6 2 x x f C x RCOMP For more details on the calculations involved, see AN892: Design Guide for Isolated DC/DC Using the Si882xx/883xx. 3.3.8 Thermal Protection A thermal shutdown circuit is included to protect the system from over-temperature events. The thermal shutdown is activated at a junction temperature that prevents permanent damage from occurring. 3.3.9 Cycle Skipping Cycle skipping is included to reduce switching power losses at light loads. This feature is transparent to the user and is activated automatically at light loads. The product options with integrated power switches (Si882xx/3xx) may never experience cycle skipping during operation even at light loads while the external power switch options (Si884xx/6xx) are likely to have cycle skipping start at light loads. silabs.com | Building a more connected world. Rev. 1.02 | 9 Si88x2x Data Sheet Functional Description 3.3.10 Low-Voltage Configuration The low-voltage configuration is used for converting 3.0 V to 5.5 V. All product options of the Si882xx and Si883xx are intended for this configuration. An advantage of Si88xx devices over other converters that use this same topology is that the output voltage is sensed on the secondary side without requiring additional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line and load regulation while reducing external components and increasing lifetime reliability. In a typical digital signal isolation application, the dc-dc powers the Si882xx and Si883xx VDDB as shown in the figure below. In addition to powering the isolated side of the dc-dc, it can deliver up to 2 W of power to external loads. The dc-dc requires an input capacitor, C2, blocking capacitor, C1, transformer, T1, rectifying diode, D1, and an output capacitor, C3. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions. More details can be found in AN892: Design Guide for Isolated DC-DC Using the Si882xx/883xx. Vin C1 T1 Vout D1 C3 C2 R1 Si8832x VSW RFSW VDDB UVLO Power FET Power FET SH_FC SS UVLO CMOS Isolation VDDA DC-DC Controller Freq. Control and Shutdown Soft Start CSS Rev. Digital Channels R2 HVREG Reference VREG Used in applications where converter output is > 5.5 V VSNS Error Amp and Compensation COMP Encoder CCOMP RCOMP HF RX HF TX A1 HF TX HF RX B1 A2 HF TX HF RX B2 Fwd. Digital Channels Figure 3.3. Si883xx Block Diagram: 3 V-5 V Input to 3 V-5 V Output silabs.com | Building a more connected world. Rev. 1.02 | 10 Si88x2x Data Sheet Functional Description 3.3.11 Low-Voltage to High-Voltage Configuration The low-voltage to high-voltage configuration is used for converting 3.0 V - 5.5 V up to 24 V. In a typical digital signal isolation application, the dc-dc powers the Si882xx and Si883xx VOUT as shown in the figure below. In addition to powering the isolated side of the dc-dc, it can deliver up to 2 W of power to external loads. The dc-dc requires an input capacitor, C2, blocking capacitor, C1, transformer, T1, rectifying diode, D1, and an output capacitor, C3. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier. To supply VDDB, Q3 transistor is biased and filtered by R5 and C4. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions. More details can be found in AN892: Design Guide for Isolated DC-DC Using the Si882xx/883xx. Vin C1 T1 Vout D1 C3 C2 Si8832x R5 VSW RFSW Power FET Power FET SH_FC SS VREG Reference UVLO CMOS Isolation VDDA DC-DC Controller Freq. Control and Shutdown Soft Start CSS Rev. Digital Channels UVLO VREGB Q3 VDDB C4 R1 VSNS Error Amp and Compensation COMP Encoder CCOMP R2 RCOMP HF RX HF TX A1 HF TX HF RX B1 A2 HF TX HF RX B2 Fwd. Digital Channels Figure 3.4. Si883xx Block Diagram: 3 V - 5 V Input to up to 24 V Output silabs.com | Building a more connected world. Rev. 1.02 | 11 Si88x2x Data Sheet Functional Description 3.3.12 High-Voltage to Low-Voltage Configuration The high-voltage configuration is used for converting up to 24 V to 3.3 V or 5.0 V. All product options of the Si884xx and Si886xx are intended for this configuration. Si884xx and Si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 V. The dc-dc converter uses the isolated flyback topology. With this topology, the switch and sense resistor are external, allowing higher switching voltages. Digital isolator supply VDDA of the Si884xx and Si886xx require a supply less than or equal to 5.5 V. If a suitable supply is not available on the primary side, the VREGA voltage reference with external NPN transistor can supply VDDA. This eliminates the need to design an additional linear regulator circuit. Like the Si882xx and Si883xx, the output voltage is sensed on the secondary side without requiring additional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line and load regulation. The figure below shows the block diagram of an Si886xx with external components. Si886xx is different from the Si882xx/883xx as it has externally-controlled switching frequency and soft start. The dc-dc requires input capacitor C2, transformer T1, switch Q1, sense resistor R4, rectifying diode D1 and an output capacitor C3. To supply VDDA, Q2 transistor is biased and filtered by R3 and C1. External frequency and soft start behavior is set by CSS and RFSW. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not necessary for normal operation, we recommend to use a snubber, to minimize high-frequency emissions. For further details, see AN901: Design Guide for Isolated DC-DC Using the Si884xx/886xx. T1 Vin VOUT D1 C3 C2 Si8862x R3 VDDA C1 Q1 ESW VREG Reference VREG Reference UVLO FET Driver UVLO RSN R4 GNDP RFSW FC_SH SS Current Sensing Used in applications where converter output is > 5.5 V VDDB Freq. Control and Shutdown VSNS R1 R2 Error Amp and Compensation COMP Soft Start CSS Rev. Digital Channel VREGB DC-DC Controller CMOS Isolation VREGA Q2 Encoder CCOMP RCOMP HF RX HF TX A1 HF TX HF RX B1 A2 HF RX HF TX B2 Fwd. Digital Channel Figure 3.5. Si886xx Block Diagram: 24 V Input to 5 V Output silabs.com | Building a more connected world. Rev. 1.02 | 12 Si88x2x Data Sheet Functional Description 3.3.13 High-Voltage to High-Voltage Configuration The high-voltage configuration is used for converting up to 24 V to up to 24 V. Si884xx and Si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 V. The dcdc converter uses the isolated flyback topology. With this topology, the switch and sense resistor are external, allowing higher switching voltages. Digital isolator supply VDDA of the Si884xx and Si886xx require a supply less than or equal to 5.5 V. If a suitable supply is not available on the primary side, the VREGA voltage reference with external NPN transistor can supply VDDA. This eliminates the need to design an additional linear regulator circuit. Like the Si882xx and Si883xx, the output voltage is sensed on the secondary side without requiring additional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line and load regulation. The figure below shows the block diagram of an Si886xx with external components. Si886xx is different from the Si882xx/883xx as it has externally-controlled switching frequency and soft start. The dc-dc requires input capacitor C2, transformer T1, switch Q1, sense resistor R4, rectifying diode D1 and an output capacitor C3. To supply VDDA, Q2 transistor is biased and filtered by R3 and C1. External frequency and soft start behavior is set by CSS and RFSW. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier. To supply VDDB, Q3 transistor is biased and filtered by R5 and C4. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not necessary for normal operation, we recommend to use a snubber, to minimize high-frequency emissions. For further details, see AN901: Design Guide for Isolated DC-DC Using the Si884xx/886xx. T1 Vin VOUT D1 C3 C2 Si8862x R5 R3 Q2 VDDA C1 Q1 ESW VREG Reference VREG Reference UVLO UVLO GNDP RFSW FC_SH SS Current Sensing VDDB Freq. Control and Shutdown R1 VSNS R2 Error Amp and Compensation COMP Soft Start CSS Rev. Digital Channel Q3 DC-DC Controller RSN R4 VREGB C4 FET Driver CMOS Isolation VREGA Encoder CCOMP RCOMP HF RX HF TX A1 HF TX HF RX B1 A2 HF RX HF TX B2 Fwd. Digital Channel Figure 3.6. Si886xx Block Diagram: Up to 24 V Input to up to 24 V Output silabs.com | Building a more connected world. Rev. 1.02 | 13 Si88x2x Data Sheet Functional Description 3.4 Transformer Design The table below provides a list of transformers and their parametric characteristics that have been validated to work with Si882xx/3xx products (input voltage of 3 to 5 V) and Si884xx/Si886xx products (input voltage of 24 V). It is recommended that users order the transformers from the vendors per the part numbers given below. Refer to AN892: Design Guide for Isolated DC/DC using the Si882xx/ 883xx and AN901: Design Guide for Isolated DC/DC using the Si884xx/886xx for voltage translation applications not listed below. To manufacture transformers from your preferred suppliers that may not be listed below, please specify to supplier the parametric characteristics as specified in the table below for a given input voltage and isolation rating. Table 3.1. Transformer Specifications Transformer Supplier Ordering Part # Input Voltage Output Voltage Turns Ratio P:S Leakage Inductance Primary Inductance Primary Resistance Isolation Rating UMEC (http:// www.umecusa.com) UTB02185s 4.5 - 5.5 V 3.0 - 5.5V 1.0:4.0 100 nH max 2 H 5% 0.05 max 2.5 kVRMS UMEC (http:// www.umecusa.com) UTB02205s 12V, 24V 3.3 - 5.0V, 15V 3.0:1.0 800 nH max 25 H 5% 0.135 max 2.5 kVRMS UMEC (http:// www.umecusa.com) UTB02240s 4.5 - 5.5V 3.0 - 5.5V 1.0:4.0 100 nH max 2 H 5% 0.05 max 5 kVRMS UMEC (http:// www.umecusa.com) UTB02250s 7 - 24 V 3.3 - 5.5V 3.0:1.0 600 nH max 25 H 5% 0.135 max 5 kVRMS Coilcraft1 (http:// www.coilcraft.com) TA7608-AL 4.5 - 5.5 V 3.0 - 5.5V 1.0:4.0 60 nH max 2 H 5% 0.033 max 2.5 kVRMS Coilcraft1 (http:// www.coilcraft.com) TA7618-AL 4.5 - 5.5V 3.0 - 5.5V 1.0:4.0 64 nH max 2.0 H 5% 0.031 max 5 kVRMS Coilcraft1 (http:// www.coilcraft.com) TA7788-AL 12V 5V, 15V 1.00 : 1.25 : 0.75 554 nH max 25 H 5% 0.49 max 5 kVRMS Coilcraft1 (http:// www.coilcraft.com) UA7902 12V 5V, 15V 3.0:1.0 971 nH max 25 H 5% 0.075 max 5 kVRMS P100940_A1 4.5 - 5.5V 3.0 - 5.5V 1.0:4.0 40 nH max 2.0 H 10% 0.1 max 2.4 kVRMS Mentech1 (http:// www.mnctek.com) TTER09-0457S1 8 - 24 V 15V, 24V 1.0:1.0 550 nH max 25 H 10% 0.4 max 2.5 kVRMS Mentech1 (http:// www.mnctek.com) TTER09-0458S1 8 - 24 V 8 - 24 V 1.0:1.0 550 nH max 25 H 10% 0.4 max 5 kVRMS TDK (http:// www.tdk.com) silabs.com | Building a more connected world. Rev. 1.02 | 14 Si88x2x Data Sheet Functional Description Transformer Supplier Ordering Part # Input Voltage Output Voltage Turns Ratio P:S Leakage Inductance Primary Inductance Primary Resistance Isolation Rating Mentech1 (http:// www.mnctek.com) TTEP09-0568S1 3.0 - 5.5 V 5.0 V 1.0:4.0 100 nH max 1.5 H 8% 0.05 max 5 kVRMS Pulse (http:// www.pulseelectronics.com/) PA4896NL 8 - 24 V 7 - 24 V 1.0:1.0 650 nH max 25 H 10% 0.25 max 2.5 kVRMS Pulse (http:// www.pulseelectronics.com/) PA4897NL 8 - 24 V 7 - 24 V 1.0:1.0 650 nH max 25 H 10% 0.25 max 5 kVRMS Notes: 1. AEC-Q200 qualified. 2. For reference design details, see AN892: Design Guide for Isolated DC/DC using the Si882xx/883xx or AN901: Design Guide for Isolated DC/DC using the Si884xx/886xx. silabs.com | Building a more connected world. Rev. 1.02 | 15 Si88x2x Data Sheet Electrical Specifications 4. Electrical Specifications Table 4.1. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit TA -40 25 125 C Power Input Voltage VDDP 3.0 -- 5.5 V Supply Voltage VDDA 3.0 -- 5.5 V VDDB 3.0 -- 5.5 V Ambient Operating Temperature Table 4.2. Electrical Characteristics1 VIN = 24 V; VDDA = VDDP = 3.0 to 5.5 V (see Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23) for all Si8822x/32x; VDDA = 4.3 V (see Figure 4.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx on page 23) for all Si8842x/62x; TA = -40 to 125 C unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit FSW -- 225 250 275 kHz 180 200 220 kHz 450 500 550 kHz 810 900 990 kHz 1.002 1.05 1.097 V -500 -- 500 nA -5 -- +5 % DC/DC Converter Switching Frequency Si8822x, Si8842x RFSW = 23.3 k FSW = 1025.5/(RFSW x CSS) CSS = 220 nF (see Figure 3.5 Si886xx Block Diagram: 24 V Input to 5 V Output on page 12) (1% tolerance on BOM) Switching Frequency Si8832x, Si8862x RFSW = 9.3 k FSW = 1025.5/(RFSW x CSS) FSW CSS = 220 nF (see Figure 3.5 Si886xx Block Diagram: 24 V Input to 5 V Output on page 12) (1% tolerance on BOM) RFSW = 5.18 k, CSS = 220 nF (see Figure 3.5 Si886xx Block Diagram: 24 V Input to 5 V Output on page 12) VSNS voltage VSNS VSNS current offset Ioffset Output Voltage Accuracy2 -- ILOAD = 0 A See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 ILOAD = 0 mA silabs.com | Building a more connected world. Rev. 1.02 | 16 Si88x2x Data Sheet Electrical Specifications Parameter Test Condition Min Typ Max Unit See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 -- 1 -- mV/V -- 0.1 -- % -- 100 -- mV p-p -- 2 -- % -- 400 -- -- 400 -- -- 250 -- -- 550 -- 24.0 to 5.0 V -- 1000 -- 24.0 to 3.3 V -- 1500 -- -- 3 -- A -- 30 -- mA Line Regulation Symbol VOUT(line)/ VDDP ILOAD = 50 mA VDDP varies from 4.5 to 5.5 V Load Regulation VOUT(load)/ VOUT See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 ILOAD = 50 to 400 mA ILOAD = 100 mA Output Voltage Ripple -- Si8822x, Si8832x See Figure 4.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx on page 23 Si8842x, Si8862x Turn-on overshoot See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 VOUT(start) See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 CIN = COUT = 0.1 F in parallel with 10 F, ILOAD = 0 A Continuous Output Current Si8822x, Si8832x 5.0 V to 5.0 V 3.3 V to 3.3 V 3.3 V to 5.0 V ILOAD(max) 5.0 V to 3.3 V See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 mA Si8842x, Si8862x Cycle-by-cycle average current limit ILIM Si8822x, Si8832x No Load Supply Current IDDP Si8822x, Si8832x See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 Output short circuited See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, IDDPQ_DCDC3 Si883xx on page 23 VDDP = VDDA = 5 V silabs.com | Building a more connected world. Rev. 1.02 | 17 Si88x2x Data Sheet Electrical Specifications Parameter No Load Supply Current IDDA Si8822x, Si8832x Symbol Test Condition See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, IDDAQ_DCDC4 Si883xx on page 23 Min Typ Max Unit -- 5.7 -- mA -- 0.8 -- mA -- 5.8 -- mA -- 78 -- VDDP = VDDA = 5 V No Load Supply Current IDDP Si8842x, Si8862x See Figure 4.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, IDDPQ_DCDC3 Si886xx on page 23 VIN = 24 V No Load Supply Current IDDA Si8842x, Si8862x See Figure 4.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, IDDAQ_DCDC4 Si886xx on page 23 VIN = 24 V Peak Efficiency Si8822x, Si8832x Si8842x, Si8862x Voltage Regulator Reference Voltage Si8842x, Si8862x VREG tempco VREG input current See Figure 4.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx on page 23 % -- 83 -- -- 4.8 -- V IREG = 600 A VREGA, VREGB See Figure 5.11 Efficiency vs. Load Current over Temperature (5.0 to 5.0 V) on page 31 for typical I-V curve KTVREG -- -- -0.43 -- mV/C IREG -- 350 -- 950 A tSST See Figure 5.16 24 V-5 V VOUT Startup vs.Time, No Load Current on page 32 through Figure 5.21 5 V-5 V VOUT Startup vs.Time (400 mA Load Current) on page 33 for typical soft start times over load conditions. -- 25 -- -- 50 -- Soft start time, full load Si8822x, Si8842x Si8832x, Si8862x Restart Delay from fault event See Figure 4.2 Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx on page 23 ms tOTP -- -- 21 -- s VDD Undervoltage Threshold VDDUV+ VDDA, VDDB rising -- 2.7 -- V VDD Undervoltage Threshold VDDUV- VDDA, VDDB falling -- 2.6 -- V VDD Undervoltage Hysteresis VDDHYS -- -- 100 -- mV Positive-Going Input Threshold VT+ All inputs rising -- 1.67 -- V Negative-Going Input Threshold VT- All inputs falling -- 1.23 -- V Input Hysteresis VHYS -- -- 0.44 -- V VIH -- 2.0 -- -- V Digital Isolator High Level Input Voltage silabs.com | Building a more connected world. Rev. 1.02 | 18 Si88x2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Low Level Input Voltage VIL -- -- -- 0.8 V High Level Output Voltage VOH lOH = -4 mA VDDA, VDDB - 0.4 -- -- V Low Level Output Voltage VOL lOL = 4 mA -- -- 0.4 V Input Leakage Current IL -- -- -- 10 A Output Impedance ZO -- -- 50 -- VDDA -- All inputs = 0 4.2 7.2 10.2 VDDB -- All inputs = 0 2.5 4.5 6.5 VDDA -- All inputs = 1 1.8 4.8 7.8 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 2.7 5.7 8.7 VDDB -- All inputs = 0 3.9 5.9 7.9 VDDA -- All inputs = 1 1.8 4.8 7.8 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 0.8 3.8 6.8 VDDB -- All inputs = 0 5.3 7.3 9.3 VDDA -- All inputs = 1 1.8 4.8 7.8 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 1.8 4.8 7.8 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 4.2 7.2 10.2 VDDB -- All inputs = 1 2.5 4.5 6.5 VDDA -- All inputs = 0 1.8 4.8 7.8 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 2.7 5.7 8.7 VDDB -- All inputs = 1 3.9 5.9 7.9 Supply Current, CLOAD = 15 pF DC, VDDx = 3.3 V 10% Si88x20ED mA Si88x21ED mA Si88x22ED mA Si88x20BD mA Si88x21BD mA Si88x22BD silabs.com | Building a more connected world. Rev. 1.02 | 19 Si88x2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDDA -- All inputs = 0 1.8 4.8 7.8 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 0.8 3.8 6.8 VDDB -- All inputs = 1 5.3 7.3 9.3 VDDA -- All inputs = 0 6.5 9.5 12.5 VDDB -- All inputs = 0 2.5 4.5 6.5 VDDA -- All inputs = 1 3.0 6.0 9.0 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 5.0 8.0 11.0 VDDB -- All inputs = 0 4.0 6.0 8.0 VDDA -- All inputs = 1 3.0 6.0 9.0 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 3.5 6.5 9.5 VDDB -- All inputs = 0 5.5 7.5 9.5 VDDA -- All inputs = 1 3.0 6.0 9.0 VDDB -- All inputs = 1 2.0 4.0 6.0 VDDA -- All inputs = 0 3.0 6.0 9.0 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 6.5 9.5 12.5 VDDB -- All inputs = 1 2.5 4.5 6.5 VDDA -- All inputs = 0 3.0 6.0 9.0 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 5.0 8.0 11.0 VDDB -- All inputs = 1 4.0 6.0 8.0 VDDA -- All inputs = 0 3.0 6.0 9.0 VDDB -- All inputs = 0 2.0 4.0 6.0 VDDA -- All inputs = 1 3.5 6.5 9.5 VDDB -- All inputs = 1 5.5 7.5 9.5 Unit mA DC, VDDx = 5 V 10% Si88x20ED mA Si88x21ED mA Si88x22ED mA Si88x20BD mA Si88x21BD mA Si88x22BD silabs.com | Building a more connected world. mA Rev. 1.02 | 20 Si88x2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: For calculating total current, including the dynamic component, see Calculating Total Current Consumption. Timing Characteristics Data Rate -- -- 0 -- 100 Mbps Minimum Pulse Width -- -- 10 -- -- ns tPHL See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 12.0 17.0 22.0 ns 11.0 15.0 20.0 ns 13.0 18.0 23.0 ns 10.0 13.0 18.0 ns -- 2.5 5.0 ns -- 4.5 7.0 ns Propagation Delay VDDx = 3.3 V tPLH Propagation Delay See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 VDDx = 3.3 V tPHL Propagation Delay See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 VDDx = 5.0 V tPLH Propagation Delay See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 VDDx = 5.0 V Pulse Width Distortion |tPLH - tPHL| PWD See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 VDDx = 3.3 V Pulse Width Distortion |tPLH - tPHL| PWD See Figure 4.1 Propagation Delay Timing for Digital Channels on page 22 VDDx = 5.0 V tPSK(P-P) -- -- 3.0 10.0 ns tPSK -- -- 2.0 4.0 ns Output Rise Time tr CL = 15 pF -- 2.5 -- ns Output Fall Time tf CL = 15 pF -- 2.5 -- ns 40 100 -- kV/s -- 55 -- s Propagation Delay Skew6 Channel-Channel Skew VI = VDDx or 0 V Common Mode Transient Immunity CMTI Startup Time7 silabs.com | Building a more connected world. tSU VCM = 1500 V (See Figure 4.4 CommonMode Transient Immunity Test Circuit on page 24) -- Rev. 1.02 | 21 Si88x2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Over recommended operating conditions as noted in Table 4.1 Recommended Operating Conditions on page 16. 2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset 3. VDDP current needed for dc-dc circuits. 4. VDDA current needed for dc-dc circuits. 5. The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output. 1.4 V Input tPLH 1.4 V Output tPHL 90% 90% 10% 10% tr tf Figure 4.1. Propagation Delay Timing for Digital Channels silabs.com | Building a more connected world. Rev. 1.02 | 22 Si88x2x Data Sheet Electrical Specifications IIN C1 + VIN R4 DB2440100L 100 10 F C2 10 F _ ILOAD D1 T1 10 F C5 100 pF UTB02185S VSW _ VDDB VDDP R1 49.9 k ISOLATION VDDA IDDA VOUT IDDB U1 IDDP + C3 SH VSNS COMP R3 49.9 k R2 13.3 k C4 GNDA 1.5 nF GNDB GNDP Figure 4.2. Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx IDDP IIN + V IN _ C2 10 F R8 SBRT5A50SA 27.4 R9 82 IDDA C7 UTB02205S ESW Q2 MMBT2222LT1 0.1 F C8 10 F VDDA SS 0.22 F VSNS GNDP C5 C1 R1 49.9 k R5 0.1 VREG _ VDDB ISOLATION 19.6 k + VOUT IDDB U2 RSNS R7 C3 22 F C6 100 pF 68 pF Q1 FDT3612 ILOAD D1 T1 COMP R3 100 k R2 13.3 k C4 GNDB 1.5 nF SH_FC R6 18 k GNDA Figure 4.3. Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx silabs.com | Building a more connected world. Rev. 1.02 | 23 Si88x2x Data Sheet Electrical Specifications Si88xx VSW VDDB VDDP/VDDA Isolated Supply + _ Forward Channel Input Forward Channel Ouput Reverse Channel Output Reverse Channel Input GNDA GNDB DC-DC Output Powers B-side Referenced to Earth Ground Oscilloscope Reverse Channel Measured by Forward Channel in Loopback High Voltage Differential Probe High Voltage Transient Generator Figure 4.4. Common-Mode Transient Immunity Test Circuit Table 4.3. Regulatory Information1,2 CSA The Si88xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. VDE The Si88xx is certified according to VDE 0884-10. For more details, see certificate 40018443. VDE 0884-10: Up to 891 Vpeak for basic insulation working voltage. UL The Si88xx is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si88xx is certified under GB4943.1-2011. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. Notes: 1. Regulatory Certifications apply to 3.75 and 5.0 kVrms rated devices, which are production tested to 4.5 and 6.0 kVrms for 1 sec, respectively. 2. All certifications are pending. silabs.com | Building a more connected world. Rev. 1.02 | 24 Si88x2x Data Sheet Electrical Specifications Table 4.4. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit WB SOIC-20 WB SOIC-16 Nominal External Air Gap (Clearance) CLR 8.01 mm Nominal External Tracking (Creepage) CPG 8.01 mm Minimum Internal Gap (Internal Clearance) DTI 0.014 mm 600 V Tracking Resistance PTI or CTI IEC60112 Erosion Depth ED 0.019 mm Resistance (Input-Output)2 RIO 1012 Capacitance (Input-Output)2 CIO 1.4 pF 4.0 pF Input Capacitance3 f = 1 MHz CI Notes: 1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage limits as 8.5 mm minimum for the WB SOIC-20 and WB SOIC-16 packages. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 7.6 mm minimum for the WB SOIC-20 and WB SOIC-16 packages. 2. To determine resistance and capacitance, the Si88xx is converted into a 2-terminal device. Pins 1-8 are shorted together to form the first terminal and pins 9-16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input to ground. Table 4.5. IEC 60664-1 Ratings Parameter Test Condition Specification WB SOIC-20 WB SOIC-16 Basic Isolation Group Installation Classification silabs.com | Building a more connected world. Material Group I Rate Mains Voltages <150 VRMS I-IV Rate Mains Voltages <300 VRMS I-IV Rate Mains Voltages <400 VRMS I-III Rate Mains Voltages <600 VRMS I-III Rev. 1.02 | 25 Si88x2x Data Sheet Electrical Specifications Table 4.6. VDE 0884-10 Insulation Characteristics1 Parameter Symbol Maximum Working Insulation Voltage Input to Output Test Voltage Test Condition VIORM VPR Characteristic Unit WB SOIC-20, WB SOIC-16 891 V peak 1671 V peak t = 60 sec 6000 V peak Tested per IEC 60065 with surge voltage of 1.2 s/50 s 3077 V peak Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) Transient Overvoltage Surge Voltage VIOTM VIOSM Tested with 4000 V Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V 2 RS >109 Note: 1. Maintenance of the safety data is ensured by protective circuits. The Si88xx provides a climate classification of 40/125/21. Table 4.7. IEC Safety Limiting Values1 Parameter Symbol Safety Temperature TS Safety Input Current IS Device Power Dissipation PS Test Condition JA = 55 C/W (WB SOIC-20, WB SOIC-16), VDDA = 5.5 V, TJ = 150 C, TA = 25 C WB SOIC-20, WB SOIC-16 Unit 150 C 413 mA 2.27 W Note: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 4.5 WB SOIC-16/20 Thermal Derating Curve Dependence of Safety Limiting Values per VDE 0884-10 on page 27. silabs.com | Building a more connected world. Rev. 1.02 | 26 Si88x2x Data Sheet Electrical Specifications Table 4.8. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Symbol WB SOIC-20, WB SOIC-16 Unit JA 55 C/W Figure 4.5. WB SOIC-16/20 Thermal Derating Curve Dependence of Safety Limiting Values per VDE 0884-10 silabs.com | Building a more connected world. Rev. 1.02 | 27 Si88x2x Data Sheet Electrical Specifications Table 4.9. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit Storage Temperature TSTG -65 +150 C Junction Temperature TJ -- +150 C VDDA -0.6 6.0 V VDDB -0.6 6.0 V VIN -0.5 VDD + 0.5 V 10 mA -- 1 mA -- 260 C HBM -- 4 kV CDM -- 2 kV -- 6500 VRMS Input-side Supply Voltage VDDP Output supply Voltage on any Pin with respect to Ground Output Drive Current per Channel IO Input Current for VREGA, VREGB IREG Lead Solder Temperature (10 s) ESD per AEC-Q100 Maximum Isolation (Input to Output) (1 sec) WB SOIC-20, WB SOIC-24 Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.1 Calculating Total Current Consumption For calculating dynamic supply current, use the following guidelines: The dynamic current is calculated as follows: ( ) ( ) x (V ) x ( D2 ) x 1E -3 IDD ac = C L Where IDD(ac) is the dynamic component of current, per output channel, in mA D is the data-rate of that channel, in Mbps CL is the load capacitance connected to the output, in pF V is the VDD on the output side, in Volts For example, for the Si88x21ED-IS, the total current can be calculated as follows: The average DC IDDA/B is the average of the DC current values at input 0 and input 1, for VDDA and VDDB respectively, as stated in the table above for Si88x21ED. CL, pF VDD, Data-rate, V MBps IDD(ac), per Total IDDA output (ac), mA channel, mA Total IDDB (ac), mA Average DC Average DC Total IDDA, IDDA, mA IDDB, mA mA Total IDDB, mA 20.00 5.00 10.00 0.50 0.50 0.50 8.25 6.95 8.75 7.45 20 100 3.30 3.30 3.30 8.25 6.95 11.55 10.25 3.3 silabs.com | Building a more connected world. Rev. 1.02 | 28 Si88x2x Data Sheet Digital Isolator Device Operation 5. Digital Isolator Device Operation Table 5.1. Si88xx Logic Operation VI Input VDDI 1,2,3,4 VDDO 1,2,3,4 VO Output H P P H L P P L X UP P L4 H4 Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI. X P UP Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI. Comments Normal operation. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. P = powered; UP = unpowered. 3. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. This situation should be avoided. We recommend that I/O's not be driven high when primary side supply is turned off or when in dc-dc shutdown mode. 4. See Section 2. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). When VDDB is powered via the primary side and the integrated dc-dc, the default outputs are undetermined as secondary side power is not available when primary side power shuts off. 5.1 Device Startup Outputs are held low during power up until VDDx is above the UVLO threshold for time period tSU. Following this, the outputs follow the states of inputs. 5.2 Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDDx is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDDA falls below VDDUV- and exits UVLO when VDDA rises above VDDUV+. Side B operates the same as Side A with respect to its VDD supply. 5.3 Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.4 Insulation and Safety-Related Specifications on page 25 and Table 4.6 VDE 0884-10 Insulation Characteristics1 on page 26 detail the working voltage and creepage/ clearance capabilities of the Si88xx. These tables also detail the component standards (UL1577, VDE0884-10, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 5.3.1 Supply Bypass The Si88xx family requires a 0.1 F bypass capacitor between all VDDx and their associated GNDx. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50-300 ) in series with the inputs and outputs if the system is excessively noisy. 5.3.2 Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the onchip series termination resistor and channel resistance of the output driver FET. When driving high-impedance terminated PCB traces, output pins should be source-terminated to minimize reflections. silabs.com | Building a more connected world. Rev. 1.02 | 29 Si88x2x Data Sheet Digital Isolator Device Operation 5.4 Fail-Safe Operating Mode Si88xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 5.1 Si88xx Logic Operation on page 29 and Table 2.1 Si88x2x Ordering Guide1,2,3,4 on page 5 for more information. 5.5 Typical Performance Characteristics The typical performance characteristics are for information only. Refer to Table 4.2 Electrical Characteristics1 on page 16 for specification limits. The data below is for all channels switching. Figure 5.1. Si88620 Typical VDDA Supply Current vs. Data Rate Using VREGA (4.3 V) Figure 5.2. Si88620 Typical VDDB Supply Current vs. Data Rate (5 and 3.3 V Operation) Figure 5.3. Si88621 Typical VDDA Supply Current vs. Data Rate Using VREGA (4.3 V) Figure 5.4. Si88621 Typical VDDB Supply Current vs. Data Rate (5 and 3.3 V Operation) Figure 5.5. Si88622 Typical VDDA Supply Current vs. Data Rate Using VREGA (4.3 V) Figure 5.6. Si88622 Typical VDDB Supply Current vs. Data Rate (5 and 3.3 V Operation) silabs.com | Building a more connected world. Rev. 1.02 | 30 Si88x2x Data Sheet Digital Isolator Device Operation Figure 5.7. Propagation Delay vs. Temperature Figure 5.8. Efficiency vs. Load Current over Temperature (3.3 to 3.3 V) Figure 5.9. Efficiency vs. Load Current over Temperature (3.3 to 5.0 V) Figure 5.10. Efficiency vs. Load Current over Temperature (5.0 to 3.3 V) Figure 5.11. Efficiency vs. Load Current over Temperature (5.0 to 5.0 V) Figure 5.12. Efficiency vs. Load Current over Temperature (24 V to 5 V) silabs.com | Building a more connected world. Rev. 1.02 | 31 Si88x2x Data Sheet Digital Isolator Device Operation Figure 5.13. Efficiency vs. Load Current over Temperature (24 V to 3.3 V) Figure 5.14. Efficiency vs. Load Current over Temperature (12 V to 5 V) Figure 5.15. Efficiency vs. Load Current over Temperature (7 V to 24 V) Figure 5.16. 24 V-5 V VOUT Startup vs.Time, No Load Current Figure 5.17. 24 V-5 V VOUT Startup vs.Time, 50 mA Load Current Figure 5.18. 24 V-5 V VOUT Startup vs.Time, 400 mA Load Current silabs.com | Building a more connected world. Rev. 1.02 | 32 Si88x2x Data Sheet Digital Isolator Device Operation Figure 5.19. 5 V-5 V VOUT Startup vs.Time (No Load) Figure 5.20. 5 V-5 V VOUT Startup vs.Time (50 mA Load Current) Figure 5.21. 5 V-5 V VOUT Startup vs.Time (400 mA Load Current) Figure 5.22. 24 V-5 V VOUT Load Transient Response (10% to 90% Load) Figure 5.23. 5 V-5 V VOUT Load Transient Response (10% to 90% Load) Figure 5.24. Typical I-V Curve for VREGA/B silabs.com | Building a more connected world. Rev. 1.02 | 33 Si88x2x Data Sheet Pin Descriptions 6. Pin Descriptions 16 GNDB GNDP 1 16 GNDB VSW 2 15 VDDB VSW 2 15 VDDB VDDP 3 14 DNC/VREGB VDDP 3 14 DNC/VREGB VDDA 4 13 VSNS VDDA 4 13 VSNS GNDA 5 12 COMP GNDA 5 12 COMP SH 6 11 NC SH 6 11 NC A1 7 HF XMTR HF RCVR 10 B1 A1 7 HF XMTR HF RCVR 10 B1 A2 8 HF XMTR HF RCVR 9 B2 A2 8 HF RCVR HF XMTR 9 B2 Isolation Barrier 1 Isolation Barrier GNDP Si88220 Si88221 1 16 GNDB VSW 2 15 VDDB VDDP 3 14 DNC/VREGB VDDA 4 13 VSNS GNDA 5 12 COMP SH 6 11 NC A1 7 HF RCVR HF XMTR 10 B1 A2 8 HF RCVR HF XMTR 9 B2 Isolation Barrier GNDP Si88222 Figure 6.1. Si8822x Pin Configurations silabs.com | Building a more connected world. Rev. 1.02 | 34 Si88x2x Data Sheet Pin Descriptions 20 GNDB GNDP 1 20 GNDB VSW 2 19 VDDB VSW 2 19 VDDB VDDP 3 18 DNC/VREGB VDDP 3 18 DNC/VREGB VDDA 4 17 NC VDDA 4 17 NC GNDA 5 16 VSNS GNDA 5 16 VSNS SH_FC 6 15 COMP SH_FC 6 15 COMP SS 7 14 NC SS 7 14 NC A1 8 HF XMTR HF RCVR 13 B1 A1 8 HF XMTR HF RCVR 13 B1 A2 9 HF XMTR HF RCVR 12 B2 A2 9 HF RCVR HF XMTR 12 B2 11 NC NC 10 11 NC NC 10 Isolation Barrier 1 Isolation Barrier GNDP Si88321 Si88320 1 20 GNDB VSW 2 19 VDDB VDDP 3 18 DNC/VREGB VDDA 4 17 NC GNDA 5 16 VSNS SH_FC 6 15 COMP SS 7 14 NC A1 8 HF RCVR HF XMTR 13 B1 A2 9 HF RCVR HF XMTR 12 B2 11 NC Isolation Barrier GNDP NC 10 Si88322 Figure 6.2. Si8832x Pinout Diagrams silabs.com | Building a more connected world. Rev. 1.02 | 35 Si88x2x Data Sheet Pin Descriptions 20 GNDB GNDP 1 16 GNDB RSN 2 15 VDDB RSN 2 15 VDDB ESW 3 14 DNC/VREGB ESW 3 14 DNC/VREGB VDDA 4 13 VSNS VDDA 4 13 VSNS GNDA 5 12 COMP GNDA 5 12 COMP VREGA 6 11 NC VREGA 6 11 NC A1 7 HF XMTR HF RCVR 10 B1 A1 7 HF XMTR HF RCVR 10 B1 A2 8 HF XMTR HF RCVR 9 B2 A2 8 HF RCVR HF XMTR 9 B2 Isolation Barrier 1 Isolation Barrier GNDP Si88421 Si88420 1 16 GNDB RSN 2 15 VDDB ESW 3 14 DNC/VREGB VDDA 4 13 VSNS GNDA 5 12 COMP VREGA 6 11 NC A1 7 HF RCVR HF XMTR 10 B1 A2 8 HF RCVR HF XMTR 9 B2 Isolation Barrier GNDP Si88422 Figure 6.3. Si8842x Pinout Diagrams silabs.com | Building a more connected world. Rev. 1.02 | 36 Si88x2x Data Sheet Pin Descriptions 20 GNDB GNDP 1 20 GNDB RSN 2 19 VDDB RSN 2 19 VDDB ESW 3 18 DNC/VREGB ESW 3 18 DNC/VREGB VDDA 4 17 NC VDDA 4 17 NC GNDA 5 16 VSNS GNDA 5 16 VSNS VREGA 6 15 COMP VREGA 6 15 COMP SH_FC 7 14 NC SH_FC 7 14 NC SS 8 13 NC SS 8 13 NC A1 9 9 A2 10 HF XMTR HF RCVR 12 B1 A1 HF XMTR HF RCVR 11 B2 A2 10 Isolation Barrier 1 Isolation Barrier GNDP Si88620 HF XMTR HF RCVR 12 B1 HF RCVR HF XMTR 11 B2 Si88621 1 20 GNDB RSN 2 19 VDDB ESW 3 18 DNC/VREGB VDDA 4 17 NC GNDA 5 16 VSNS VREGA 6 15 COMP SH_FC 7 14 NC SS 8 13 NC A1 9 A2 10 Isolation Barrier GNDP HF RCVR HF XMTR 12 B1 HF RCVR HF XMTR 11 B2 Si88622 Figure 6.4. Si8862x Pinout Diagrams silabs.com | Building a more connected world. Rev. 1.02 | 37 Si88x2x Data Sheet Pin Descriptions Table 6.1. Si88x2x Pin Descriptions Pin Name Description DC-DC Input Side VDDP VREGA GNDP Power stage primary power supply. Voltage reference output for external voltage regulator pin. Power stage ground. ESW Power stage external switch driver output. VSW Power stage internal switch output. SS SH, SH_FC RSN Soft startup control. Shutdown and Switch frequency control. Power stage current sense input. DC-DC Output Side VSNS Power stage feedback input. COMP Power stage compensation. DNC/VREGB NC Voltage reference output for external voltage regulator pin. This pin has a Zener connected internally. Use this pin as reference only when output voltage from dc-dc is > 5.5 V. If output voltage is 5.5 V, this pin should be read as DNC or Do Not Connect. No connect; this pin is not connected to the silicon. Digital Isolator VDDA Side VDDA Primary side signal power supply. A1-A2 I/O signal channel 1-4. GNDA Primary side signal ground. Digital Isolator VDDB Side VDDB Secondary side signal power supply. B1-B2 I/O signal channel 1-4. GNDB Secondary side signal ground. silabs.com | Building a more connected world. Rev. 1.02 | 38 Si88x2x Data Sheet Package Outlines 7. Package Outlines 7.1 Package Outline: 20-Pin Wide Body SOIC The figure below illustrates the package details for the 20-pin wide-body SOIC package. The table below lists the values for the dimensions shown in the illustration. Figure 7.1. 20-Pin Wide Body SOIC silabs.com | Building a more connected world. Rev. 1.02 | 39 Si88x2x Data Sheet Package Outlines Table 7.1. 20-Pin Wide Body SOIC Package Diagram Dimensions Dimension Min Max A -- 2.65 A1 0.10 0.30 A2 2.05 -- b 0.31 0.51 c 0.20 0.33 D 12.80 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0 8 aaa -- 0.10 bbb -- 0.33 ccc -- 0.10 ddd -- 0.25 eee -- 0.10 fff -- 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AC. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. silabs.com | Building a more connected world. Rev. 1.02 | 40 Si88x2x Data Sheet Package Outlines 7.2 Package Outline: 16-Pin Wide Body SOIC The figure below illustrates the package details for the Si864x Digital Isolator. The table below lists the values for the dimensions shown in the illustration. Figure 7.2. 16-Pin Wide Body SOIC silabs.com | Building a more connected world. Rev. 1.02 | 41 Si88x2x Data Sheet Package Outlines Table 7.2. Package Diagram Dimensions Dimension Min Max A -- 2.65 A1 0.10 0.30 A2 2.05 -- b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0 8 aaa -- 0.10 bbb -- 0.33 ccc -- 0.10 ddd -- 0.25 eee -- 0.10 fff -- 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components. silabs.com | Building a more connected world. Rev. 1.02 | 42 Si88x2x Data Sheet Land Patterns 8. Land Patterns 8.1 Land Pattern: 20-Pin SOIC The figure below illustrates the PCB land pattern details for the 20-pin SOIC package. The table below lists the values for the dimensions shown in the illustration. Figure 8.1. 20-Pin SOIC PCB Land Pattern Table 8.1. 24-Pin SOIC PCB Land Pattern Dimensions Dimension mm C1 9.40 E 1.27 X1 0.60 Y1 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 design guidelines for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC), and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.02 | 43 Si88x2x Data Sheet Land Patterns 8.2 Land Pattern: 16-Pin Wide-Body SOIC The figure below illustrates the recommended land pattern details for the Si864x in a 16-pin wide-body SOIC. The table below lists the values for the dimensions shown in the illustration. Figure 8.2. 16-Pin SOIC Land Pattern Table 8.2. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.02 | 44 Si88x2x Data Sheet Top Markings 9. Top Markings 9.1 Si88x2x Top Marking: 20-Pin Wide Body SOIC Figure 9.1. 20-Pin Wide Body SOIC Table 9.1. Top Marking Explanation (20-Pin Wide Body SOIC) Si88x2 = 5 kV rated channel digital isolator with dc-dc converter X = 3, 6 3 = Full-featured dc-dc with integrated FET 6 = full featured dc-dc with external FET Base Part Number Line 1 Marking: Ordering Options See 2. Ordering Guide for more information. Y = Number of reverse channels Z = E, B E = default high B = default low R = C, D C = 3.75 kVrms isolation rating D = 5 kVrms isolation rating YY = Year Line 2 Marking: WW = Workweek Line 3 Marking: Assigned by the Assembly House. Corresponds to the year and workweek of the mold date. TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Circle = 1.5 mm Diameter (Center Justified) "e4" Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan silabs.com | Building a more connected world. Rev. 1.02 | 45 Si88x2x Data Sheet Top Markings 9.2 Si88x2x Top Marking: 16-Pin Wide Body SOIC Figure 9.2. 16-Pin Wide Body SOIC Table 9.2. Top Marking Explanation (16-Pin Wide Body SOIC) Si88x2 = 5kV rated 2 channel digital isolator with dc-dc converter X = 2, 4 2 = dc-dc shutdown 4 = external FET Base Part Number Line 1 Marking: Ordering Options See 2. Ordering Guide for more information. Y = Number of reverse channels Z = E, B E = default high B = default low R = C, D C = 3.75 kVrms isolation rating D = 5 kVrms isolation rating YY = Year Line 2 Marking: WW = Workweek Line 3 Marking: Assigned by the Assembly House. Corresponds to the year and workweek of the mold date. TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Circle = 1.5 mm Diameter (Center Justified) "e4" Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan silabs.com | Building a more connected world. Rev. 1.02 | 46 Si88x2x Data Sheet Revision History 10. Revision History Rev. 1.02 March 2019 * Corrected Transformer Specification table Rev. 1.01 November 2018 * Updated Transformer Specification table Rev. 1.0 February 2018 * Updated Ordering Guide Table 2.1 * Updated Transformer Table 3.1 * Updated Spec Table 4.2 * Added section 4.1 (Calculating total current) * Corrected pin-outs Fig 6.1, 6.3 Rev. 0.6 May 11, 2017 * Updated format to current style guide. * Added WB-SOIC-16 to Table 4.7 IEC Safety Limiting Values1 on page 26. * Updated Table 3.1 Transformer Specifications on page 14. * Updated 5.5 Typical Performance Characteristics. * Updated pinouts and pin description table in Section 6. Pin Descriptions. Rev. 0.5 July 22, 2015 * Initial release. silabs.com | Building a more connected world. Rev. 1.02 | 47 Smart. Connected. Energy-Friendly. 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