2N5640 - ON Semiconductor

Motorola Small–Signal Transistors, FETs and Diodes Device Data

 

N–Channel — Depletion

Rating Symbol Value Unit

Drain–Source Voltage VDS 30 Vdc

Drain–Gate Voltage VDG 30 Vdc

Reverse Gate–Source Voltage VGSR 30 Vdc

Forward Gate Current IGF 10 mAdc

Total Device Dissipation @ TA = 25°C

Derate above 25°CPD350

2.8 mW

mW/°C

Thermal Resistance, Junction to Ambient R

JA 357 °C/W

Junction Temperature Range TJ–65 to +150 °C

Storage Temperature Range Tstg –65 to +150 °C

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Gate–Source Breakdown Voltage (IG = 10 µAdc, VDS = 0) V(BR)GSS 30 — Vdc

Gate Reverse Current

(VGS = –15 Vdc, VDS = 0)

(VGS = –15 Vdc, VDS = 0, TA = 100°C)

IGSS —

—1.0

1.0 nAdc

µAdc

Drain Cutoff Current

(VDS = 15 Vdc, VGS = –6.0 Vdc)

(VDS = 15 Vdc, VGS = –6.0 Vdc, TA = 100°C)

ID(off) —

—1.0

1.0 nAdc

µAdc

ON CHARACTERISTICS

Zero–Gate–Voltage Drain Current(1)

(VDS = 20 Vdc, VGS = 0) IDSS 5.0 — mAdc

Drain–Source On–V oltage

(ID = 3.0 mAdc, VGS = 0) VDS(on) —0.5 Vdc

Static Drain–Source On Resistance

(ID = 1.0 mAdc, VGS = 0) rDS(on) —100 Ohms

1. Pulse Test: Pulse Width

300

s, Duty Cycle

3.0%.

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SEMICONDUCTOR TECHNICAL DATA

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CASE 29–04, STYLE 5

TO–92 (TO–226AA)

123

 Motorola, Inc. 1997

1 DRAIN

GATE

2 SOURCE

REV 1

2N5640

2 Motorola Small–Signal Transistors, FETs and Diodes Device Data

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)

Characteristic Symbol Min Max Unit

SMALL–SIGNAL CHARACTERISTICS

Static Drain–Source “ON” Resistance

(VGS = 0, ID = 0, f = 1.0 kHz) rds(on) —100 Ohms

Input Capacitance

(VDS = 0, VGS = –12 Vdc, f = 1.0 MHz) Ciss —10 pF

Reverse T ransfer Capacitance

(VDS = 0, VGS = –12 Vdc, f = 1.0 MHz) Crss —4.0 pF

SWITCHING CHARACTERISTICS

Turn–On Delay Time

VDD =10Vdc

ID(on) = 3.0 mAdc td(on) —8.0 ns

Rise T ime

DD =

Vdc

VGS

(

)

= 0, ID(on) = 3.0 mAdc tr— 10 ns

T urn–Off Delay Time

GS(on) ,

VGS(off) = –10 Vdc,

′

=50Ω

ID(on) = 3.0 mAdc td(off) —15 ns

Fall T ime

′

Ω

ID(on) = 3.0 mAdc tf— 30 ns

2N5640

Motorola Small–Signal Transistors, FETs and Diodes Device Data

tf, FALL TIME (ns) tr, RISE TIME (ns)

td(on), TURN–ON DELAY TIME (ns)

1000

1.0

2.0

5.0

100

200

500

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN CURRENT (mA)

Figure 1. Turn–On Delay Time

RK = 0

TJ = 25

VGS(off) = 12 V

RK = RD

′

1000

1.0

2.0

5.0

100

200

500

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN CURRENT (mA)

Figure 2. Rise Time

RK = RD

′

RK = 0

TJ = 25

VGS(off) = 12 V

1000

1.0

2.0

5.0

100

200

500

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN CURRENT (mA)

Figure 3. Turn–Off Delay Time

RK = RD

′

RK = 0

td(off), TURN–OFF DELAY TIME (ns)

1000

1.0

2.0

5.0

100

200

500

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN CURRENT (mA)

Figure 4. Fall Time

RK = RD

′

RK = 0

TYPICAL SWITCHING CHARACTERISTICS

NOTE 1

The switching characteristics shown above were measured using a

test circuit similar to Figure 5. At the beginning of the switching

interval, the gate voltage is at Gate Supply Voltage (–VGG). The

Drain–Source Voltage (VDS) is slightly lower than Drain Supply

Voltage (VDD) due to the voltage divider. Thus Reverse Transfer

Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to

VGG + VDS.

During the turn–on interval, Gate–Source Capacitance (Cgs)

discharges through the series combination of RGen and RK. Cgd

must discharge to VDS(on) through RG and RK in series with the

parallel combination of effective load impedance (R′D) and

Drain–Source Resistance (rds). During the turn–off, this charge flow

is reversed.

Predicting turn–on time is somewhat difficult as the channel

resistance rds is a function of the gate–source voltage. While Cgs

discharges, VGS approaches zero and rds decreases. Since Cgd

discharges through rds, turn–on time is non–linear . During turn–off,

the situation is reversed with rds increasing as Cgd charges.

The above switching curves show two impedance conditions;

1) RK is equal to RD, which simulates the switching behavior of

cascaded stages where the driving source impedance is normally

the load impedance of the previous stage, and 2) RK = 0 (low

impedance) the driving source impedance is that of the generator.

RGEN

Ω

VGEN

INPUT RK

Ω

RGG

VGG

Ω

OUTPUT

+VDD

SET VDS(off) = 10 V

INPUT PULSE

PULSE WIDTH

DUTY CYCLE

≤

0.25 ns

≤

0.5 ns

= 2.0

≤

2.0%

RGG

Ȁ+

(RT

)

50)

)

Figure 5. Switching Time Test Circuit

TJ = 25

VGS(off) = 12 V TJ = 25

VGS(off) = 12 V

2N5640

4 Motorola Small–Signal Transistors, FETs and Diodes Device Data

rds(on), DRAIN–SOURCE ON–ST ATE

RESISTANCE (OHMS)

NOTE 2

The Zero–Gate–Voltage Drain Current (IDSS), is the principle

determinant of other J-FET characteristics. Figure 10 shows

the relationship of Gate–Source Off Voltage (VGS(off) and

Drain–Source On Resistance (rds(on)) to IDSS. Most of the

devices will be within ±10% of the values shown in Figure 10.

This data will be useful in predicting the characteristic

variations for a given part number.

yfs, FORWARD TRANSFER ADMITTANCE (mmhos)

C, CAPACITANCE (pF)

rds(on), DRAIN–SOURCE ON–ST ATE

RESISTANCE (OHMS)

rds(on), DRAIN–SOURCE ON–ST ATE

RESIST ANCE (NORMALIZED)

2.0

3.0

5.0

7.0

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

ID, DRAIN CURRENT (mA)

Figure 6. Typical Forward Transfer Admittance

1.0

1.5

2.0

3.0

5.0

7.0

0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30

VR, REVERSE VOLTAGE (VOLTS)

Figure 7. Typical Capacitance

200

160

120

00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, GATE–SOURCE VOLTAGE (VOLTS)

Figure 8. Effect of Gate–Source Voltage

On Drain–Source Resistance

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

–70 –40 –10 20 50 80 110 140 170

Tchannel, CHANNEL TEMPERATURE (

Figure 9. Effect of Temperature On

Drain–Source On–State Resistance

Tchannel = 25

VDS = 15 V

Cgs

Cgd

Tchannel = 25

(Cds IS NEGLIGIBLE)

IDSS

= 10

mA 50 mA 75 mA 100 mA 125 mA

Tchannel = 25

ID = 1.0 mA

VGS = 0

10 IDSS, ZERO–GATE–VOLT AGE DRAIN CURRENT (mA)

Figure 10. Effect of IDSS On Drain–Source

Resistance and Gate–Source Voltage

20 30 40 50 60 70 80 90 100 110 120 130 140 150

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

100

VGS, GATE–SOURCE VOLTAGE (VOLTS)

Tchannel = 25

rDS(on) @ VGS = 0

VGS(off)

2N5640

Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSION D AND J APPLY BETWEEN L AND K

MINIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIMENSION K MINIMUM.

HSECTION X–X

SEATING

PLANE DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.175 0.205 4.45 5.20

B0.170 0.210 4.32 5.33

C0.125 0.165 3.18 4.19

D0.016 0.022 0.41 0.55

F0.016 0.019 0.41 0.48

G0.045 0.055 1.15 1.39

H0.095 0.105 2.42 2.66

J0.015 0.020 0.39 0.50

K0.500 ––– 12.70 –––

L0.250 ––– 6.35 –––

N0.080 0.105 2.04 2.66

P––– 0.100 ––– 2.54

R0.115 ––– 2.93 –––

V0.135 ––– 3.43 –––

CASE 029–04

(TO–226AA)

ISSUE AD

STYLE 5:

PIN 1. DRAIN

2. SOURCE

3. GATE

2N5640

6 Motorola Small–Signal Transistors, FETs and Diodes Device Data

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