HEF4011BP,652\"\" - NXP SEMICONDUCTORS

1. General description

The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the

highest noise immunity and pattern insensitivity to output impedance.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to V SS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +125 C

Complies with JEDEC standard JESD 13-B

Inputs and outputs are protected against electrostatic effects

3. Ordering information

4. Functional diagram

HEF4011B

Quad 2-input NAND gate

Rev. 5 — 21 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4011BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4011BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig 1. Functional di ag ram Fig 2. Logic diagram (one ga te)

001aan874

1A 1Y

2A 2Y

910

3A 3Y

13 11

4A 4Y

001aan875

Product data sheet Rev. 5 — 21 November 2011 2 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

Fig 3. Pin configuratio n

HEF4011B

1A VDD

1B 4B

1Y 4A

2Y 4Y

2A 3Y

2B 3B

VSS 3A

001aan876

7 8

Table 2. Pin description

Symbol Pin Description

nA 1, 5, 8, 12 input

nB 2, 6, 9, 13 input

nY 3, 4, 10, 11 output

VSS 7 ground (0 V)

VDD 14 supply voltage

Table 3. Function table[1]

Input Output

nA nB nY

LLH

LHH

HLH

HHL

Product data sheet Rev. 5 — 21 November 2011 3 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

7. Limiting values

[1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.

[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.

8. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping curre nt VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +125 C

Ptot total power dissipation Tamb = 40 C to + 125 C

DIP14 [1] -750mW

SO14 [2] -500mW

P power dissipation per output - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +125 C

t/V input transition rise and fall rate VDD = 5 V --3.75s/V

VDD = 10 V --0.5s/V

VDD = 15 V --0.08s/V

Product data sheet Rev. 5 — 21 November 2011 4 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

9. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI=V

SS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 CUnit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V7.0-7.0-7.0- 7.0 -V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3 .0 V

15 V - 4.0 - 4.0 - 4.0 - 4 .0 V

VOH HIGH-level

output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

IOH HIGH-level

output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

IOL LOW-level

output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

IIinput leakage

current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

IDD supply current all valid input

combinations;

IO=0A

5 V - 0.25 - 0.25 - 7.5 - 7.5 A

10 V - 0.5 - 0.5 - 15.0 - 15.0 A

15 V - 1.0 - 1.0 - 30.0 - 30.0 A

CIinput

capacitance ---7.5-- - -pF

Product data sheet Rev. 5 — 21 November 2011 5 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

10. Dynamic characteristics

[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

[2] tpd is the same as tPLH and tPHL.

Table 7. Dynamic characteristics

Tamb = 25



C; for wavefo rms see Figure 4; for test circuit see Figure 5; unless otherwise specified.

Symbol Parameter Extrapolation formula[1] VDD Min Typ Max Unit

tpd propagation delay 28 + 0.55  CL5 V [2] - 55 110 ns

14 + 0.23  CL10 V - 25 45 ns

12 + 0.16  CL15 V - 20 35 ns

tTHL HIGH to LOW output transition time 10 + 1.00  CL5 V - 60 120 ns

9 + 0.42  CL10 V - 30 60 ns

6 + 0.28  CL15 V - 20 40 ns

tTLH LOW to HIGH output transition time 10 + 1.00  CL5 V - 60 120 ns

9 + 0.42  CL10 V - 30 60 ns

6 + 0.28  CL15 V - 20 40 ns

Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical form ula Where

PDdynamic power dissipation 5 V PD = 1300  fi + (fo  CL)  VDD2 (W) fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

(fo  CL) = sum of the outputs;

VDD = supply voltage in V.

10 V PD = 6000  fi + (fo  CL)  VDD2 (W)

15 V PD = 20100  fi + (fo  CL)  VDD2 (W)

Product data sheet Rev. 5 — 21 November 2011 6 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

11. Waveforms

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. Prop a ga tio n de la y, output transition time

001aag197

input

output

tPLH

tPHL

0 V

VOH

VOL tTLH

tTHL

90 %

10 %

90 %

trtf

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL= load capacitance including jig and probe capacitance.

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 5. Test circuit for measuring switching times

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD 20 ns 5 0 pF

Product data sheet Rev. 5 — 21 November 2011 7 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

12. Package outline

Fig 6. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 5 — 21 November 2011 8 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

Fig 7. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 5 — 21 November 2011 9 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

13. Abbreviations

14. Revision history

Table 11. Abbreviations

Acronym Description

DUT Device Under Test

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4011B v. 5 20111121 Product data sheet - HEF4011B v.4

Modifications: •Legal pages updated.

•Changes in “General description” and “Features and benefits”.

•Section “Applications” removed.

HEF4011B v. 4 20110330 Product data sheet - HEF4011B_CNV v.3

HEF4011B_CNV v.3 19950101 Product specification - HEF4011B_CNV v.2

HEF4011B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 5 — 21 November 2011 10 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

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with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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products are sold subject to the general terms and conditions of commercial

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 5 — 21 November 2011 11 of 12

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

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In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

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15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4011B

Quad 2-input NAND gate

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 21 Novem ber 2011

Document iden tifier: HE F4011B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional description . . . . . . . . . . . . . . . . . . . 2

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 3

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

16 Contact information. . . . . . . . . . . . . . . . . . . . . 11

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12