1
LT1160/LT1162
11602fb
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
Half-/Full-Bridge
N-Channel
Power MOSFET Drivers
■
Floating Top Driver Switches Up to 60V
■
Drives Gate of Top N-Channel MOSFET
above Load HV Supply
■
180ns Transition Times Driving 10,000pF
■
Adaptive Nonoverlapping Gate Drives Prevent
Shoot-Through
■
Top Drive Protection at High Duty Cycles
■
TTL/CMOS Input Levels
■
Undervoltage Lockout with Hysteresis
■
Operates at Supply Voltages from 10V to 15V
■
Separate Top and Bottom Drive Pins
The LT
®
1160/LT1162 are cost effective half-/full-bridge
N-channel power MOSFET drivers. The floating driver can
drive the topside N-channel power MOSFETs operating off
a high voltage (HV) rail of up to 60V.
The internal logic prevents the inputs from turning on the
power MOSFETs in a half-bridge at the same time. Its
unique adaptive protection against shoot-through cur-
rents eliminates all matching requirements for the two
MOSFETs. This greatly eases the design of high efficiency
motor control and switching regulator systems.
During low supply or start-up conditions, the undervoltage
lockout actively pulls the driver outputs low to prevent the
power MOSFETs from being partially turned on. The 0.5V
hysteresis allows reliable operation even with slowly vary-
ing supplies.
The LT1162 is a dual version of the LT1160 and is available
in a 24-pin PDIP or in a 24-pin SO Wide package.
■
PWM of High Current Inductive Loads
■
Half-Bridge and Full-Bridge Motor Control
■
Synchronous Step-Down Switching Regulators
■
3-Phase Brushless Motor Drive
■
High Current Transducer Drivers
■
Class D Power Amplifiers
SV+
PV+
UV OUT
IN TOP
IN BOTTOM
14
13
12
11
9
8
1
10
4
2
3
BOOST
T GATE DR
T GATE FB
T SOURCE
B GATE DR
B GATE FB
LT1160
1N4148 HV = 60V MAX
CBOOST
1µF
10µF
25V
12V
PWM
0Hz TO 100kHz
1160 TA01
IRFZ44
IRFZ44
56
1000µF
100V
SGND PGND
IN TOP IN BOTTOM T GATE DR B GATE DR
LL L L
LH L H
HL H L
HH L L
+
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LT1160/LT1162
11602fb
ABSOLUTE MAXIMUM RATINGS
W
WW
U
Supply Voltage (Note 2) ......................................... 20V
Boost Voltage ......................................................... 75V
Peak Output Currents (< 10µs) .............................. 1.5A
Input Pin Voltages .......................... – 0.3V to V
+
+ 0.3V
Top Source Voltage ..................................... –5V to 60V
Boost to Source Voltage ........................... –0.3V to 20V
Operating Temperature Range
Commercial .......................................... 0°C to 70°C
Industrial ......................................... – 40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PACKAGE/ORDER INFORMATION
W
UU
ORDER PART
NUMBER
LT1162CSW
LT1162ISW
ORDER PART
NUMBER
LT1160CN
LT1160CS
LT1160IN
LT1160IS
T
JMAX
= 125°C, θ
JA
= 58°C/ W (N)
T
JMAX
= 125°C, θ
JA
= 80°C/ W (SW)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test Circuit, TA = 25°C, V + = VBOOST = 12V, VTSOURCE = 0V, CGATE =
3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S
DC Supply Current (Note 4) V
+
= 15V, V
INTOP
= 0.8V, V
INBOTTOM
= 2V 7 11 15 mA
V
+
= 15V, V
INTOP
= 2V, V
INBOTTOM
= 0.8V 7 10 15 mA
V
+
= 15V, V
INTOP
= 0.8V, V
INBOTTOM
= 0.8V 7 11 15 mA
I
BOOST
Boost Current (Note 4) V
+
= 15V, V
TSOURCE
= 60V, V
BOOST
= 75V, 3 4.5 6 mA
V
INTOP
= V
INBOTTOM
= 0.8V
V
IL
Input Logic Low ●1.4 0.8 V
V
IH
Input Logic High ●2 1.7 V
I
IN
Input Current V
INTOP
= V
INBOTTOM
= 4V ●725 µA
V
+UVH
V
+
Undervoltage Start-Up Threshold 8.4 8.9 9.7 V
V
+UVL
V
+
Undervoltage Shutdown Threshold 7.8 8.3 8.8 V
V
BUVH
V
BOOST
Undervoltage Start-Up Threshold V
TSOURCE
= 60V (V
BOOST
– V
TSOURCE
) 8.8 9.3 9.8 V
V
BUVL
V
BOOST
Undervoltage Shutdown Threshold V
TSOURCE
= 60V (V
BOOST
– V
TSOURCE
) 8.2 8.7 9.2 V
ELECTRICAL CHARACTERISTICS
T
JMAX
= 125°C, θ
JA
= 70°C/ W (N)
T
JMAX
= 125°C, θ
JA
= 110°C/ W (S)
1
2
3
4
5
6
7
TOP VIEW
N PACKAGE
14-LEAD PDIP
S PACKAGE
14-LEAD PLASTIC SO
14
13
12
11
10
9
8
SV+
IN TOP
IN BOTTOM
UV OUT
SGND
PGND
NC
BOOST
T GATE DR
T GATE FB
T SOURCE
PV+
B GATE DR
B GATE FB
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
N PACKAGE
24-LEAD PDIP
24
23
22
21
20
19
18
17
16
15
14
13
SW PACKAGE
24-LEAD PLASTIC SO WIDE
SV
+
A
IN TOP
A
IN BOTTOM
A
UV
OUT
A
GND A
B GATE FB A
SV
+
B
IN TOP B
IN BOTTOM B
UV
OUT
B
GND B
B GATE FB B
BOOST A
T GATE DR A
T GATE FB A
T SOURCE A
PV
+
A
B GATE DR A
BOOST B
T GATE DR B
T GATE FB B
T SOURCE B
PV
+
B
B GATE DR B
(Note 1)
OBSOLETE
PART NUMBERS
LT1162CN
LT1162IN
3
LT1160/LT1162
11602fb
I
UVOUT
Undervoltage Output Leakage V
+
= 15V ●0.1 5 µA
V
UVOUT
Undervoltage Output Saturation V
+
= 7.5V, I
UVOUT
= 2.5mA ●0.2 0.4 V
V
OH
Top Gate ON Voltage V
INTOP
= 2V, V
INBOTTOM
= 0.8V ●11 11.3 12 V
Bottom Gate ON Voltage V
INTOP
= 0.8V, V
INBOTTOM
= 2V ●11 11.3 12 V
V
OL
Top Gate OFF Voltage V
INTOP
= 0.8V, V
INBOTTOM
= 2V ●0.4 0.7 V
Bottom Gate OFF Voltage V
INTOP
= 2V, V
INBOTTOM
= 0.8V ●0.4 0.7 V
t
r
Top Gate Rise Time V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V, ●130 200 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Rise Time V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V, ●90 200 ns
Measured at V
BGATE DR
(Note 5)
t
f
Top Gate Fall Time V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V, ●60 140 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Fall Time V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V, ●60 140 ns
Measured at V
BGATE DR
(Note 5)
t
D1
Top Gate Turn-On Delay V
INTOP
(+) Transition, V
INBOTTOM
= 0.8V, ●250 500 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Turn-On Delay V
INBOTTOM
(+) Transition, V
INTOP
= 0.8V, ●200 400 ns
Measured at V
BGATE DR
(Note 5)
t
D2
Top Gate Turn-Off Delay V
INTOP
(–) Transition, V
INBOTTOM
= 0.8V, ●300 600 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Turn-Off Delay V
INBOTTOM
(–) Transition, V
INTOP
= 0.8V, ●200 400 ns
Measured at V
BGATE DR
(Note 5)
t
D3
Top Gate Lockout Delay V
INBOTTOM
(+) Transition, V
INTOP
= 2V, ●300 600 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Lockout Delay V
INTOP
(+) Transition, V
INBOTTOM
= 2V, ●250 500 ns
Measured at V
BGATE DR
(Note 5)
t
D4
Top Gate Release Delay V
INBOTTOM
(–) Transition, V
INTOP
= 2V, ●250 500 ns
Measured at V
TGATE DR
(Note 5)
Bottom Gate Release Delay V
INTOP
(–) Transition, V
INBOTTOM
= 2V, ●200 400 ns
Measured at V
BGATE DR
(Note 5)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.Test Circuit, TA = 25°C, V+ = VBOOST = 12V, VTSOURCE = 0V, CGATE =
3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: For the LT1160, Pins 1, 10 should be connected together. For the
LT1162, Pins 1, 7, 14, 20 should be connected together.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LT1160CN/LT1160IN: T
J
= T
A
+ (P
D
)(70°C/W)
LT1160CS/LT1160IS: T
J
= T
A
+ (P
D
)(110°C/W)
LT1162CN/LT1162IN: T
J
= T
A
+ (P
D
)(58°C/W)
LT1162CS/LT1162IS: T
J
= T
A
+ (P
D
)(80°C/W)
Note 4: I
S
is the sum of currents through SV
+
, PV
+
and Boost pins.
I
BOOST
is the current through the Boost pin. Dynamic supply current is
higher due to the gate charge being delivered at the switching frequency.
See Typical Performance Characteristics and Applications Information
sections. The LT1160 = 1/2 LT1162.
Note 5: See Timing Diagram. Gate rise times are measured from 2V to 10V
and fall times are measured from 10V to 2V. Delay times are measured
from the input transition to when the gate voltage has risen to 2V or
decreased to 10V.
4
LT1160/LT1162
11602fb
TYPICAL PERFORMANCE CHARACTERISTICS
UW
INPUT FREQUENCY (kHz)
1
SUPPLY CURRENT (mA)
60
50
40
30
20
10
010 100 1000
1160/62 G04
CGATE = 10000pF
CGATE = 1000pF
50% DUTY CYCLE
V+ = 12V
CGATE = 3000pF
TEMPERATURE (°C)
–50
V
BOOST
– V
TSOURCE
VOLTAGE (V)
100
13
12
11
10
9
8
7
6
5
4
1160/62 G06
0–25 25 50 75 125
SHUTDOWN THRESHOLD
START-UP THRESHOLD
V
TSOURCE
= 60V
TEMPERATURE (°C)
–50
INPUT CURRENT (µA)
14
13
12
11
10
9
8
7
6
5
4050 75
1160/62 G08
–25 25 100 125
V
+
= 12V
V
IN
= 4V
DC Supply Current
vs Temperature
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
100
14
13
12
11
10
9
8
7
6
5
1160/62 G02
0–25 25 50 75 125
BOTH INPUTS
HIGH OR LOW
V
INTOP
= HIGH
V
INBOTTOM
= LOW
V
INTOP
= LOW
V
INBOTTOM
= HIGH
V
+
= 12V
INPUT FREQUENCY (kHz)
1
SUPPLY CURRENT (mA)
60
50
40
30
20
10
010 100 1000
1160/62 G03
V+ = 20V
50% DUTY CYCLE
CGATE = 3000pF
V+ = 15V
V+ = 10V
DC + Dynamic Supply Current
vs Input Frequency
DC Supply Current
vs Supply Voltage
DC + Dynamic Supply Current
vs Input Frequency
TEMPERATURE (°C)
–50
SUPPLY VOLTAGE (V)
100
13
12
11
10
9
8
7
6
5
4
1160/62 G05
0–25 25 50 75 125
SHUTDOWN THRESHOLD
START-UP THRESHOLD
Undervoltage Lockout (V+)Undervoltage Lockout (VBOOST)
Input Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–50
INPUT THRESHOLD VOLTAGE (V)
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
1160/62 G07
0–25 25 50 75 125
V
LOW
V
HIGH
V
+
= 12V
INPUT VOLTAGE (V)
4
INPUT CURRENT (mA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
89
1160/62 G09
567 10 11 12
V
+
= 12V
Top or Bottom Input Pin Current
vs Input Voltage
(LT1160 or 1/2 LT1162)
SUPPLY VOLTAGE (V)
8
SUPPLY CURRENT (mA)
20
14
13
12
11
10
9
8
7
6
5
1160/62 G01
1210 14 16 18 22
BOTH INPUTS
HIGH OR LOW
V
INTOP
= LOW
V
INBOTTOM
= HIGH
V
INTOP
= HIGH
V
INBOTTOM
= LOW
Top or Bottom Input Pin Current
vs Temperature
5
LT1160/LT1162
11602fb
TYPICAL PERFORMANCE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
BOTTOM GATE RISE TIME (ns)
100
230
210
190
170
150
130
110
90
70
50
1160/62 G10
0–25 25 50 75 125
C
LOAD
= 10000pF
C
LOAD
= 3000pF
C
LOAD
= 1000pF
V
+
= 12V
Bottom Gate Rise Time
vs Temperature
TEMPERATURE (°C)
–50
BOTTOM GATE FALL TIME (ns)
100
210
190
170
150
130
110
90
70
50
30
1160/62 G11
0–25 25 50 75 125
C
LOAD
= 10000pF
C
LOAD
= 3000pF
V
+
= 12V
C
LOAD
= 1000pF
Bottom Gate Fall Time
vs Temperature
TEMPERATURE (°C)
–50
TOP GATE RISE TIME (ns)
100
300
280
260
240
220
200
180
160
140
120
100
80
1160/62 G12
0–25 25 50 75 125
C
LOAD
= 10000pF
C
LOAD
= 3000pF
V
+
= 12V
C
LOAD
= 1000pF
Top Gate Rise Time
vs Temperature
TEMPERATURE (°C)
–50
TOP GATE FALL TIME (ns)
100
11160/62 G13
050
180
160
140
120
100
80
60
40
20
–25 25 75 125
CLOAD = 10000pF
CLOAD = 3000pF
V+ = 12V
CLOAD = 1000pF
TEMPERATURE (°C)
–50
TURN OFF DELAY TIME (ns)
100
400
350
300
250
200
150
100
1160/62 G15
0–25 25 50 75 125
BOTTOM DRIVER
TOP DRIVER
V
+
= 12V
C
LOAD
= 3000pF
Turn-On Delay Time
vs Temperature
TEMPERATURE (°C)
–50
TURN ON DELAY TIME (ns)
100
400
350
300
250
200
150
100
1160/62 G14
0–25 25 50 75 125
BOTTOM DRIVER
TOP DRIVER
V
+
= 12V
C
LOAD
= 3000pF
Turn-Off Delay Time
vs Temperature
TEMPERATURE (°C)
–50
LOCKOUT DELAY TIME (ns)
100
400
350
300
250
200
150
100
1160/62 G16
0–25 25 50 75 125
BOTTOM DRIVER
TOP DRIVER
V
+
= 12V
C
LOAD
= 3000pF
Lockout Delay Time
vs Temperature
TEMPERATURE (°C)
–50
RELEASE DELAY TIME (ns)
100
400
350
300
250
200
150
100
1160/62 G17
0–25 25 50 75 125
BOTTOM DRIVER
TOP DRIVER
V
+
= 12V
C
LOAD
= 3000pF
Release Delay Time
vs Temperature
(LT1160 or 1/2 LT1162)
Top Gate Fall Time
vs Temperature
6
LT1160/LT1162
11602fb
PIN FUNCTIONS
UUU
LT1162
SV
+
(Pins 1, 7): Main Signal Supply. Must be closely
decoupled to ground Pins 5 and 11.
IN TOP (Pins 2, 8): Top Driver Input. The Input Top is
disabled when the Input Bottom is high. A 3k input resistor
followed by a 5V internal clamp prevents saturation of the
input transistors.
IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input
Bottom is disabled when the Input Top is high. A 3k input
resistor followed by a 5V internal clamp prevents satura-
tion of the input transistors.
UV OUT (Pins 4, 10): Undervoltage Output. Open collector
NPN output which turns on when V
+
drops below the
undervoltage threshold.
GND (Pins 5, 11): Ground Connection.
B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must
connect directly to the bottom power MOSFET gate. The
top MOSFET turn-on is inhibited until Bottom Gate Feed-
back pins have discharged to below 2.5V.
B GATE DR (Pins 13, 19): Bottom Gate Drive. The high
current drive point for the bottom MOSFET. When a gate
resistor is used it is inserted between the Bottom Gate
Drive pin and the gate of the MOSFET.
PV
+
(Pins 14, 20): Bottom Driver Supply. Must be con-
nected to the same supply as Pins 1 and 7.
T SOURCE (Pins 15, 21): Top Driver Return. Connects to
the top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pins 16, 22): Top Gate Feedback. Must
connect directly to the top power MOSFET gate. The
bottom MOSFET turn-on is inhibited until V
TGF
– V
TSOURCE
has discharged to below 2.9V.
T GATE DR (Pins 17, 23): Top Gate Drive. The high current
drive point for the top MOSFET. When a gate resistor is
used it is inserted between the Top Gate Drive pin and the
gate of the MOSFET.
BOOST (Pins 18, 24): Top Driver Supply. Connects to the
high side of the bootstrap capacitor.
LT1160
SV
+
(Pin 1): Main Signal Supply. Must be closely decoupled
to the signal ground Pin 5.
IN TOP (Pin 2): Top Driver Input. Pin 2 is disabled when Pin
3 is high. A 3k input resistor followed by a 5V internal
clamp prevents saturation of the input transistors.
IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled
when Pin 2 is high. A 3k input resistor followed by a 5V
internal clamp prevents saturation of the input transistors.
UV OUT (Pin 4): Undervoltage Output. Open collector NPN
output which turns on when V
+
drops below the
undervoltage threshold.
SGND (Pin 5): Small Signal Ground. Must be routed
separately from other grounds to the system ground.
PGND (Pin 6): Bottom Driver Power Ground. Connects to
source of bottom N-channel MOSFET.
B GATE FB (Pin 8): Bottom Gate Feedback. Must connect
directly to the bottom power MOSFET gate. The top
MOSFET turn-on is inhibited until Pin 8 has discharged to
below 2.5V.
B GATE DR (Pin 9): Bottom Gate Drive. The high current
drive point for the bottom MOSFET. When a gate resistor
is used it is inserted between Pin 9 and the gate of the
MOSFET.
PV
+
(Pin 10): Bottom Driver Supply. Must be connected to
the same supply as Pin 1.
T SOURCE (Pin 11): Top Driver Return. Connects to the
top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pin 12): Top Gate Feedback. Must connect
directly to the top power MOSFET gate. The bottom
MOSFET turn-on is inhibited until V
12
– V
11
has discharged
to below 2.9V.
T GATE DR (Pin 13): Top Gate Drive. The high current drive
point for the top MOSFET. When a gate resistor is used it
is inserted between Pin 13 and the gate of the MOSFET.
BOOST (Pin 14): Top Driver Supply. Connects to the high
side of the bootstrap capacitor.
7
LT1160/LT1162
11602fb
+
V
SV
+
PV
+
IN TOP
IN BOTTOM
UV OUT
SGND
PGND
BOOST
T GATE DR
T GATE FB
T SOURCE
B GATE DR
B GATE FB
3k
50Ω
50Ω
1µF
1µF3000pF
3000pF
1160/62 TC01
(LT1160)
+
V/I
+
V/I
+
V
+
V
TEST CIRCUIT
–
+
–
+
SV+
IN TOP
IN BOTTOM
BOOST
T GATE DR
T GATE FB
T SOURCE
PV+
B GATE DR
B GATE FB
1160/62 BD
SGND
PGND
GND
1/2 LT1162
LT1160
BIAS
3k
3k
TOP
UV LOCK
BOTTOM
UV LOCK
2.9V
2.5V
5V
5V
UV OUT
FUNCTIONAL DIAGRA
UU
W
(LT1160 or 1/2 LT1162)
(LT1160 or 1/2 LT1162)
8
LT1160/LT1162
11602fb
TI I G DIAGRA
UWW
OPERATIO
U
(Refer to Functional Diagram)
The LT1160 (or 1/2 LT1162) incorporates two indepen-
dent driver channels with separate inputs and outputs. The
inputs are TTL/CMOS compatible; they can withstand
input voltages as high as V
+
. The 1.4V input threshold is
regulated and has 300mV of hysteresis. Both channels are
noninverting drivers. The internal logic prevents both
outputs from simultaneously turning on under any input
conditions. When both inputs are high both outputs are
actively held low.
The floating supply for the top driver is provided by a
bootstrap capacitor between the Boost pin and the Top
Source pin. This capacitor is recharged each time the
negative plate goes low in PWM operation.
The undervoltage detection circuit disables both channels
when V
+
is below the undervoltage trip point. A separate
UV detect block disables the high side channel when
V
BOOST
– V
TSOURCE
is below its own undervoltage trip
point.
The top and bottom gate drivers in the LT1160 each utilize
two gate connections: 1) a gate drive pin, which provides
the turn on and turn off currents through an optional series
gate resistor, and 2) a gate feedback pin which connects
directly to the gate to monitor the gate-to-source voltage.
Whenever there is an input transition to command the
outputs to change states, the LT1160 follows a logical
sequence to turn off one MOSFET and turn on the other.
First, turn-off is initiated, then V
GS
is monitored until it has
decreased below the turn-off threshold, and finally the
other gate is turned on.
10V
2V
IN TOP
IN BOTTOM
TOP GATE
DRIVER
BOTTOM
GATE
DRIVER
2V
0.8V
2V
0.8V
12V
0V
12V
0V
tr
tD1
tD3
10V
2V
tr
tD2
tD4
tf
tD3 tD2
tftD4
1160/62 TD
tD1
9
LT1160/LT1162
11602fb
Power MOSFET Selection
Since the LT1160 (or 1/2 LT1162) inherently protects the
top and bottom MOSFETs from simultaneous conduction,
there are no size or matching constraints. Therefore selec-
tion can be made based on the operating voltage and
R
DS(ON)
requirements. The MOSFET BV
DSS
should be
greater than the HV and should be increased to approxi-
mately (2)(HV) in harsh environments with frequent fault
conditions. For the LT1160 maximum operating HV supply
of 60V, the MOSFET BV
DSS
should be from 60V to 100V.
The MOSFET R
DS(ON)
is specified at T
J
= 25°C and is
generally chosen based on the operating efficiency re-
quired as long as the maximum MOSFET junction tem-
perature is not exceeded. The dissipation while each
MOSFET is on is given by:
P = D(I
DS
)
2
(1+∂)R
DS(ON)
Where D is the duty cycle and ∂ is the increase in R
DS(ON)
at the anticipated MOSFET junction temperature. From this
equation the required R
DS(ON)
can be derived:
RP
DI
DS ON
DS
()
=
()
+
()
2
1∂
For example, if the MOSFET loss is to be limited to 2W
when operating at 5A and a 90% duty cycle, the required
R
DS(ON)
would be 0.089Ω/(1 + ∂). (1 + ∂) is given for each
MOSFET in the form of a normalized R
DS(ON)
vs tempera-
ture curve, but ∂ = 0.007/°C can be used as an approxima-
tion for low voltage MOSFETs. Thus, if T
A
= 85°C and the
available heat sinking has a thermal resistance of 20°C/W,
the MOSFET junction temperature will be 125°C and
∂ = 0.007(125 – 25) = 0.7. This means that the required
R
DS(ON)
of the MOSFET will be 0.089Ω/1.7 = 0.0523Ω,
which can be satisfied by an IRFZ34 manufactured by
International Rectifier.
Transition losses result from the power dissipated in each
MOSFET during the time it is transitioning from off to on,
or from on to off. These losses are proportional to (f)(HV)
2
and vary from insignificant to being a limiting factor on
operating frequency in some high voltage applications.
APPLICATIONS INFORMATION
WUUU
Paralleling MOSFETs
When the above calculations result in a lower R
DS(ON)
than
is economically feasible with a single MOSFET, two or
more MOSFETs can be paralleled. The MOSFETs will
inherently share the currents according to their R
DS(ON)
ratio as long as they are thermally connected (e.g., on a
common heat sink). The LT1160 top and bottom drivers
can each drive five power MOSFETs in parallel with only a
small loss in switching speeds (see Typical Performance
Characteristics). A low value resistor (10Ω to 47Ω) in
series with each individual MOSFET gate may be required
to “decouple” each MOSFET from its neighbors to prevent
high frequency oscillations (consult manufacturer’s rec-
ommendations). If gate decoupling resistors are used the
corresponding gate feedback pin can be connected to any
one of the gates as shown in Figure 1.
Driving multiple MOSFETs in parallel may restrict the
operating frequency to prevent overdissipation in the
LT1160 (see the following Gate Charge and Driver Dissi-
pation).
Gate Charge and Driver Dissipation
A useful indicator of the load presented to the driver by a
power MOSFET is the total gate charge Q
G
, which includes
the additional charge required by the gate-to-drain swing.
Q
G
is usually specified for V
GS
= 10V and V
DS
= 0.8V
DS(MAX)
.
When the supply current is measured in a switching
application, it will be larger than given by the DC electrical
characteristics because of the additional supply current
associated with sourcing the MOSFET gate charge:
II
dQ
dt
dQ
dt
SUPPLY DC G
TOP
G
BOTTOM
=+
⎛
⎝
⎜⎞
⎠
⎟+⎛
⎝
⎜⎞
⎠
⎟
GATE DR
GATE FB
LT1160 R
G
*R
G
*
*OPTIONAL 10Ω
1160 F01
Figure 1. Paralleling MOSFETs
10
LT1160/LT1162
11602fb
APPLICATIONS INFORMATION
WUUU
The actual increase in supply current is slightly higher due
to LT1160 switching losses and the fact that the gates are
being charged to more than 10V. Supply Current vs
Input Frequency is given in the Typical Performance
Characteristics.
The LT1160 junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the LT1160IS is limited to
less than 31mA from a 12V supply:
T
J
= 85°C + (31mA)(12V)(110°C/W)
= 126°C exceeds absolute maximum
In order to prevent the maximum junction temperature
from being exceeded, the LT1160 supply current must be
verified while driving the full complement of the chosen
MOSFET type at the maximum switching frequency.
Ugly Transient Issues
In PWM applications the drain current of the top MOSFET
is a square wave at the input frequency and duty cycle. To
prevent large voltage transients at the top drain, a low ESR
electrolytic capacitor must be used and returned to the
power ground. The capacitor is generally in the range of
25µF to 5000µF and must be physically sized for the RMS
current flowing in the drain to prevent heating and prema-
ture failure. In addition, the LT1160 requires a separate
10µF capacitor connected closely between Pins 1 and 5
(the LT1162 requires two 10µF capacitors connected
between Pins 1 and 5, and Pins 7 and 11).
The LT1160 top source is internally protected against
transients below ground and above supply. However, the
gate drive pins cannot be forced below ground. In most
applications, negative transients coupled from the source
to the gate of the top MOSFET do not cause any problems.
Switching Regulator Applications
The LT1160 (or 1/2 LT1162) is ideal as a synchronous
switch driver to improve the efficiency of step-down
(buck) switching regulators. Most step-down regulators
use a high current Schottky diode to conduct the inductor
current when the switch is off. The fractions of the oscil-
lator period that the switch is on (switch conducting) and
off (diode conducting) are given by:
Switch Total Period
Switch Total Period
ON = V
HV
OFF = HV – V
HV
OUT
OUT
⎛
⎝
⎜⎞
⎠
⎟
()
⎛
⎝
⎜⎞
⎠
⎟
()
Note that for HV
> 2V
OUT
the switch is off longer than it is
on, making the diode losses more significant than the
switch. The worst case for the diode is during a short
circuit, when V
OUT
approaches zero and the diode con-
ducts the short-circuit current almost continuously.
Figure 2 shows the LT1160 used to synchronously drive a
pair of power MOSFETs in a step-down regulator applica-
tion, where the top MOSFET is the switch and the bottom
MOSFET replaces the Schottky diode. Since both conduc-
tion paths have low losses, this approach can result in very
high efficiency (90% to 95%) in most applications. For
regulators under 10A, using low R
DS(ON)
N-channel
MOSFETs eliminates the need for heat sinks. R
GS
holds the
top MOSFET off when HV
is applied before the 12V supply.
One fundamental difference in the operation of a step-
down regulator with synchronous switching is that it never
becomes discontinuous at light loads. The inductor cur-
rent doesn’t stop ramping down when it reaches zero but
actually reverses polarity resulting in a constant ripple
current independent of load. This does not cause a signifi-
cant efficiency loss (as might be expected) since the
negative inductor current is returned to HV when the
switch turns back on. However, I
2
R losses will occur
under these conditions due to the recirculating currents.
The LT1160 performs the synchronous MOSFET drive in a
step-down switching regulator. A reference and PWM are
required to complete the regulator. Any voltage mode or
current mode PWM controller may be used but the LT3526
is particularly well-suited to high power, high efficiency
applications such as the 10A circuit shown in Figure 4. In
higher current regulators a small Schottky diode across the
bottom MOSFET helps to reduce reverse-recovery switching
losses.
11
LT1160/LT1162
11602fb
APPLICATIONS INFORMATION
WUUU
+
IN TOP
IN BOTTOM
BOOST
T GATE DR
T GATE FB
T SOURCE
B GATE DR
B GATE FB
LT1160
HV
VOUT
RGS RSENSE
1160 F02
12V
REF PWM
OUT A
OUT A
SV+
PV+
Figure 2. Adding Synchronous Switching to a Step-Down Switching Regulator
Motor Drive Applications
In applications where rotation is always in the same
direction, a single LT1160 controlling a half-bridge can be
used to drive a DC motor. One end of the motor may be
connected either to supply or to ground as seen on Figure
3. A motor in this configuration is controlled by its inputs
which give three alternatives: run, free running stop (coast-
ing) and fast stop (“plugging” braking, with the motor
shorted by one of the MOSFETs).
To drive a DC motor in both directions the LT1162 can be
used to drive an H-bridge output stage. In this configura-
tion the motor can be made to run clockwise, counter-
clockwise, stop rapidly (“plugging” braking) or free run
(coast) to a stop. A very rapid stop may be achieved by
reversing the current, though this requires more careful
design to stop the motor dead. In practice a closed-loop
control system with tachometric feedback is usually
necessary.
The motor speed in these examples can be controlled by
switching the drivers with pulse width modulated square
waves. This approach is particularly suitable for micro-
computers/DSP control loops.
Figure 3. Driving a Supply Referenced Motor
SV
+
PV
+
BOOST
T GATE DR
T GATE FB
T SOURCE
B GATE DR
B GATE FB
PGND
LT1160
12V
1160 F03
HV
IN TOP
IN BOTTOM
12
LT1160/LT1162
11602fb
Figure 5. 90% Efficiency, 40V to 5V 10A Low Dropout Current Mode Switching Regulator
TYPICAL APPLICATIONS
U
6800pF
100pF
10k
18k
18k
10k
2k
1k
1k
5k
25k
500k
5V
5400µF
LOW ESR
1160/62 F05
0.1µF
10µF
2.2µF
1µF0.1µF330k
12V
1N4148
1N4148
1N4148
4700pF
IRFZ44
IRFZ44
MBR360
* HURRICANE LAB
HL-KM147U
IRFZ44
60V
MAX
2200µF EA
LOW ESR
R
S
**
0.007Ω
L*
47µH
f = 40kHz
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BOOST
T GATE DR
T GATE FB
T SOURCE
PV
+
B GATE DR
B GATE FB
LT1160
SV
+
IN TOP
IN BOTTOM
UV OUT
SGND
PGND
NC
2N2222
LT1846
** DALE TYPE LVR-3
ULTRONIX RCS01
+ +
+
+
2.2nF
27k
0.1µF
1k
1k
5k
2k
5V
5400µF
LOW ESR
1160/62 F04
0.1µF
10µF
1µF
1µF
0.1µF
0.022µF
C1
0.1µF
360Ω
510Ω
4.7k
0.33µF
330k
12V
1N4148
1N4148
1N4148
IRFZ44
IRFZ44 MBR360
* MAGNETICS CORE #55585-A2
30 TURNS 14GA MAGNET WIRE
IRFZ44
60V MAX
2200µF EA
LOW ESR
R
S
**
0.007Ω
L*
70µH
4.7k
f = 25kHz
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
BOOST
T GATE DR
T GATE FB
T SOURCE
PV
+
B GATE DR
B GATE FB
LT1160
SV
+
IN TOP
IN BOTTOM
UV OUT
SGND
PGND
NC
SHUTDOWN
2N2222
LT3526
** DALE TYPE LVR-3
ULTRONIX RCS01
++
+
Figure 4. 90% Efficiency, 40V to 5V 10A Low Dropout Voltage Mode Switching Regulator
13
LT1160/LT1162
11602fb
TYPICAL APPLICATIONS
U
Figure 6. 200W Class D, 10Hz to 1kHz Amplifier
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
5
6
7
8
7
6
5
14
13
12
11
10
9
8
8
7
6
5
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
LT1162
IN TOP A
IN BOTTOM A
UV OUT A
GND A
SV+ A
B GATE FB A
SV+ B
IN TOP B
IN BOTTOM B
UV OUT B
GND B
B GATE FB B
PV+ A
BOOST A
T GATE DR A
T GATE FB A
T SOURCE A
B GATE DR A
BOOST B
T GATE DR B
T GATE FB B
T SOURCE B
PV+ B
B GATE DR B
LT1058
TC4428
1N4148
330k
L*
158µH
L*
158µH
330k
IRFZ44
IRFZ44
IRFZ44
IRFZ44
0.1µF
10µF
1000µF
10µF
150k10k
100k
10k
95k
1160/62 F06
150k
–12V
10k
10k
10k
200k
95k
10k
10k
200k
IN
5V
1k
1k
1k
1k
12V
0.0033µF
0.1µF
0.1µF
1µF
0.0033µF
1k
47µF
47µF
47µF
47µF
0.1µF
100µF
0.1µF
10µF
10µF
0.1µF
1000µF
1N4148
LT1015
LT1016
+
10k
* Kool Mµ
®
CORE #77548-A7
35 TURNS 14GA MAGNET WIRE
fCARRIER = 100kHz
60V MAX
LOAD
+
Kool Mµ is a registered trademark of Magnetics, Inc.
14
LT1160/LT1162
11602fb
OBSOLETE PACKAGE
PACKAGE DESCRIPTION
U
N14 1002
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.018 ± .003
(0.457 ± 0.076)
.005
(0.125)
MIN
.255 ± .015*
(6.477 ± 0.381)
.770*
(19.558)
MAX
31 24567
8910
11
1213
14
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N24 1002
.255 ± .015*
(6.477 ± 0.381)
1.265*
(32.131)
MAX
12345678910
19
11 12
131416 151718
20
21
2223
24
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.018 ± .003
(0.457 ± 0.076)
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N Package
24-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
15
LT1160/LT1162
11602fb
PACKAGE DESCRIPTION
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
N
234
.150 – .157
(3.810 – 3.988)
NOTE 3
14 13
.337 – .344
(8.560 – 8.738)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
567
N/2
8
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)
× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
S14 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S Package
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
16
LT1160/LT1162
11602fb
© LINEAR TECHNOLOGY CORPORATION 1995
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1158 Half-Bridge N-Channel Power MOSFET Driver Single Input, Continuous Current Protection and Internal Charge
Pump for DC Operation
LT1336 Half-Bridge N-Channel Power MOSFET Driver with Onboard Boost Regulator to Supply the High Side Driver
Boost Regulator
LT1910 Protected High Side MOSFET Driver V
IN
= 8V to 48V, Protected from –15V to 60V Transients, Auto
Restart, Fault Indication
LTC1922-1 Synchronous Phase Modulated Full-Bridge Controller Output Power from 50W to Kilowatts, Adaptive Direct Sense Zero
Voltage Switching Compensates for External Component Tolerances
LTC1923 Full-Bridge Controller for Thermoelectric Coolers High Efficiency, Adjustable Slew Rate Reduces EMI
5mm × 5mm QFN and 28-Pin SSOP
PACKAGE DESCRIPTION
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LT 0807 REV B • PRINTED IN USA
S24 (WIDE) 0502
NOTE 3
.598 – .614
(15.190 – 15.600)
NOTE 4
22 21 20 19 18 17 16 15
12345678
.394 – .419
(10.007 – 10.643)
910
1314
11 12
N/2
2324
N
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
123 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SW Package
24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
