In-Circuit Serial ProgrammingTM (ICSPTM) Guide 2000 Microchip Technology Inc. May 2000 DS30277C All rights reserved. Copyright 2000, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." DS30277C - page ii The Microchip name and logo, PIC, PICmicro, PRO MATE, PICSTART, MPLAB, and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. In-Circuit Serial Programming and ICSP are trademarks and SQTP is a service mark of Microchip Technology Inc. All other trademarks mentioned herein are property of their respective companies. 2000 Microchip Technology Inc. Table of Contents PAGE SECTION 1 INTRODUCTION In-Circuit Serial ProgrammingTM (ICSPTM) Guide ............................................................................................. 1-1 SECTION 2 TECHNICAL BRIEFS How to Implement ICSPTM Using PIC12C5XX OTP MCUs ............................................................................. 2-1 How to Implement ICSPTM Using PIC16CXXX OTP MCUs ............................................................................. 2-9 How to Implement ICSPTM Using PIC17CXXX OTP MCUs ........................................................................... 2-15 How to Implement ICSPTM Using PIC16F8X FLASH MCUs .......................................................................... 2-21 SECTION 3 PROGRAMMING SPECIFICATIONS In-Circuit Serial Programming for PIC12C5XX OTP MCUs ............................................................................. 3-1 In-Circuit Serial Programming for PIC12C67X and PIC12CE67X OTP MCUs .............................................. 3-15 In-Circuit Serial Programming for PIC14000 OTP MCUs ............................................................................... 3-27 In-Circuit Serial Programming for PIC16C55X OTP MCUs ............................................................................ 3-39 In-Circuit Serial Programming for PIC16C6XX/7XX/9XX OTP MCUs ............................................................ 3-51 In-Circuit Serial Programming for PIC17C7XX OTP MCUs ........................................................................... 3-71 In-Circuit Serial Programming for PIC18CXXX OTP MCUs ........................................................................... 3-97 In-Circuit Serial Programming for PIC16F62X FLASH MCUs ...................................................................... 3-135 In-Circuit Serial Programming for PIC16F8X FLASH MCUs ........................................................................ 3-149 In-Circuit Serial Programming for PIC16F8XX FLASH MCUs ..................................................................... 3-165 SECTION 4 APPLICATION NOTES In-Circuit Serial ProgrammingTM (ICSPTM) of Calibration Parameters Using a PICmicro(R) Microcontroller ...... 4-1 2000 Microchip Technology Inc. DS30277C-page iii DS30277C-page iv (c) 2000 Microchip Technology Inc. SECTION 1 INTRODUCTION IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) GUIDE ................................................................... 1-1 2000 Microchip Technology Inc. DS30277C-page 1-i DS30277C-page 1-ii 2000 Microchip Technology Inc. INTRODUCTION In-Circuit Serial ProgrammingTM (ICSPTM) Guide WHAT IS IN-CIRCUIT SERIAL PROGRAMMING (ICSP)? WHAT CAN I DO WITH IN-CIRCUIT SERIAL PROGRAMMING? In-System Programming (ISP) is a technique where a programmable device is programmed after the device is placed in a circuit board. ICSP is truly an enabling technology that can be used in a variety of ways including: In-Circuit Serial Programming (ICSP) is an enhanced ISP technique implemented in Microchip's PICmicro(R) One-Time-Programmable (OTP) and FLASH RISC microcontrollers (MCU). Use of only two I/O pins to serially input and output data makes ICSP easy to use and less intrusive on the normal operation of the MCU. The cost of upgrading a system's code can be dramatically reduced using ICSP. With very little effort and planning, a PICmicro OTP- or FLASHbased system can be designed to have code updates in the field. Because they can accommodate rapid code changes in a manufacturing line, PICmicro OTP and FLASH MCUs offer tremendous flexibility, reduce development time and manufacturing cycles, and improve time to market. In-Circuit Serial Programming enhances the flexibility of the PICmicro even further. This In-Circuit Serial Programming Guide is designed to show you how you can use ICSP to get an edge over your competition. Microchip has helped its customers implement ICSP using PICmicro MCUs since 1992. Contact your local Microchip sales representative today for more information on implementing ICSP in your product. PICmicro MCUs MAKE IN-CIRCUIT SERIAL PROGRAMMING A CINCH Unlike many other MCUs, most PICmicro MCUs offer a simple serial programming interface using only two I/O pins (plus power, ground and VPP). Following very simple guidelines, these pins can be fully utilized as I/O pins during normal operation and programming pins during ICSP. ICSP can be activated through a simple 5-pin connector and a standard PICmicro programmer supporting serial programming mode such as Microchip's PRO MATE(R) II. No other MCU has a simpler and less intrusive Serial Programming Mode to facilitate your ICSP needs. * Reduce Cost of Field Upgrades For PICmicro FLASH devices, the entire code memory can be rewritten with new code. In PICmicro OTP devices, new code segments and parameter tables can be easily added in program memory areas left blank for update purpose. Often, only a portion of the code (such as a key algorithm) requires update. * Reduce Time to Market In instances where one product is programmed with different customer codes, generic systems can be built and inventoried ahead of time. Based on actual mix of customer orders, the PICmicro MCU can be programmed using ICSP, then tested and shipped. The lead-time reduction and simplification of finished goods inventory are key benefits. * Calibrate Your System During Manufacturing Many systems require calibration in the final stages of manufacturing and testing. Typically, calibration parameters are stored in Serial EEPROM devices. Using PICmicro MCUs, it is possible to save the additional system cost by programming the calibration parameters directly into the program memory. * Add Unique ID Code to Your System During Manufacturing Many products require a unique ID number or a serial number. An example application would be a remote keyless entry device. Each transmitter has a unique "binary key" that makes it very easy to program in the access code at the very end of the manufacturing process and prior to final test. Serial number, revision code, date code, manufacturer ID and a variety of other useful information can also be added to any product for traceability. Using ICSP, you can eliminate the need for DIP switches or jumpers. In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc. SQTP is a service mark of Microchip Technology Inc. 2000 Microchip Technology Inc. DS30277C-page 1-1 Introduction In fact, this capability is so important to many of our customers that Microchip offers a factory programming service called Serialized Quick Turn Programming (SQTPSM), where each PICmicro MCU device is coded with up to 16 bytes of unique code. * Program Dice When Using Chip-On-Board (COB) If you are using COB, Microchip offers a comprehensive die program. You can get dice that are preprogrammed, or you may want to program the die once the circuit board is assembled. Programming and testing in one single step in the manufacturing process is simpler and more cost effective. * Calibrate Your System in the Field Calibration need not be done only in the factory. During installation of a system, ICSP can be used to further calibrate the system to actual operating environment. In fact, recalibration can be easily done during periodic servicing and maintenance. In OTP parts, newer calibration data can be written to blank memory locations reserved for such use. * Customize and Configure Your System in the Field Like calibration, customization need not done in the factory only. In many situations, customizing a product at installation time is very useful. A good example is home or car security systems where ID code, access code and other such information can be burned in after the actual configuration is determined. Additionally, you can save the cost of DIP switches and jumpers, which are traditionally used. PROGRAMMING TIME CONSIDERATIONS Programming time can be significantly different between OTP and FLASH MCUs. OTP (EPROM) bytes typically program with pulses in the order of several hundred microseconds. FLASH, on the other hand, require several milliseconds or more per byte (or word) to program. Figure 1 and Figure 2 below illustrate the programming time differences between OTP and FLASH MCUs. Figure 1 shows programming time in an ideal programmer or tester, where the only time spent is actually programming the device. This is only important to illustrate the minimum time required to program such devices, where the programmer or the tester is fully optimized. Figure 2 is a more realistic programming time comparison, where the "overhead" time for programmer or a tester is built in. The programmer often requires 3 to 5 times the "theoretically" minimum programming time. FIGURE 1: PROGRAMMING TIME FOR FLASH AND OTP MCUS (THEORETICAL MINIMUM TIMES) 45 Programming Time (Seconds) 40 Typical Typical Flash FLASH MCU MCU 35 30 25 20 15 Microchip Microchip OTP OTPMCU MCU 10 5 0 0 1K 2K 4K 8K 16K Memory Size (in bytes) Note 1: The programming times shown here only include the total programming time for all memory. Typically, a programmer will have quite a bit of overhead over this "theoretical minimum" programming time. 2: In the PIC16CXX MCU (used here for comparison) each word is 14 bits wide. For the sake of simplicity, each word is viewed as "two bytes". DS30277C-page 1-2 2000 Microchip Technology Inc. Introduction FIGURE 2: PROGRAMMING TIME FOR FLASH AND OTP MCUS (TYPICAL PROGRAMMING TIMES ON A PROGRAMMER) 280 260 Programming Time (Seconds) 240 220 200 Typical Typical Flash FLASHMCU MCU 180 160 140 120 100 80 60 Microchip Microchip OTP MCU OTP MCU 40 20 0 0 1K 2K 4K 8K 16K Memory Size (in bytes) Note 1: The programming times shown are actual programming times on vendor supplied programmers. 2: Microchip OTP programming times are based on PRO MATE II programmer. Ramifications Development Tools The programming time differences between FLASH and OTP MCUs are not particular material for prototyping quantities. However, its impact can be significant in large volume production. Microchip offers a comprehensive set of development tools for ICSP that allow system engineers to quickly prototype, make code changes and get designs out the door faster than ever before. MICROCHIP PROVIDES A COMPLETE SOLUTION FOR ICSP PRO MATE II Production Programmer - a production quality programmer designed to support the Serial Programming Mode in MCUs up to midvolume production. PRO MATE II runs under DOS in a Command Line Mode, Microsoft(R) Windows(R) 3.1, Windows(R) 95/98, and Windows NT(R). PRO MATE II is also capable of Serialized Quick Turn ProgrammingSM (SQTPSM), where each device can be programmed with up to 16 bytes of unique code. Products Microchip offers the broadest line of ICSP-capable MCUs: * * * * * * * * * PIC12C5XX OTP, 8-pin Family PIC12C67X OTP, 8-pin Family PIC12CE67X OTP, 8-pin Family PIC16C6XX OTP, Mid-Range Family PIC17C7XX OTP High-End Family PIC18CXXX OTP, High-End Family PIC16F62X FLASH, Mid-Range Family PIC16F8X FLASH, Mid-Range Family PIC6F8XX FLASH, Mid-Range Family All together, Microchip currently offers over 40 MCUs capable of ICSP. 2000 Microchip Technology Inc. Microchip offers an ICSP kit that can be used with the Universal Microchip Device Programmer, PRO MATE II. Together these two tools allow you to implement ICSP with minimal effort and use the ICSP capability of Microchip's PICmicro MCUs. Technical support Microchip has been delivering ICSP capable MCUs since 1992. Many of our customers are using ICSP capability in full production. Our field and factory application engineers can help you implement ICSP in your product. DS30277C-page 1-3 Introduction NOTES: DS30277C-page 1-4 2000 Microchip Technology Inc. SECTION 2 TECHNICAL BRIEFS HOW TO IMPLEMENT ICSPTM USING PIC12C5XX OTP MCUS ........................................................... 2-1 HOW TO IMPLEMENT ICSPTM USING PIC16CXXX OTP MCUS .......................................................... 2-9 HOW TO IMPLEMENT ICSPTM USING PIC17CXXX OTP MCUS ........................................................ 2-15 HOW TO IMPLEMENT ICSPTM USING PIC16F8X FLASH MCUS ....................................................... 2-21 2000 Microchip Technology Inc. DS30277C-page 2-i DS30277C-page 2-ii 2000 Microchip Technology Inc. TB017 How to Implement ICSPTM Using PIC12C5XX OTP MCUs Author: IN-CIRCUIT SERIAL PROGRAMMING Thomas Schmidt Microchip Technology Inc. To implement ICSP into an application, the user needs to consider three main components of an ICSP system: Application Circuit, Programmer and Programming Environment. INTRODUCTION The technical brief describes how to implement in-circuit serial programmingTM (ICSP) using the PIC12C5XX OTP PICmicro(R) MCU. Application Circuit During the initial design phase of the application circuit, certain considerations have to be taken into account. Figure 1 shows and typical circuit that addresses the details to be considered during design. In order to implement ICSP on your application board you have to put the following issues into consideration: ICSP is a simple way to manufacture your board with an unprogrammed PICmicro MCU and program the device just before shipping the product. Programming the PIC12C5XX MCU in-circuit has many advantages for developing and manufacturing your product. 1. * Reduces inventory of products with old firmware. With ICSP, the user can manufacture product without programming the PICmicro MCU. The PICmicro MCU will be programmed just before the product is shipped. * ICSP in production. New software revisions or additional software modules can be programmed during production into the PIC12C5XX MCU. * ICSP in the field. Even after your product has been sold, a service man can update your program with new program modules. * One hardware with different software. ICSP allows the user to have one hardware, whereas the PIC12C5XX MCU can be programmed with different types of software. * Last minute programming. Last minute programming can also facilitate quick turnarounds on custom orders for your products. FIGURE 1: 2. 3. 4. 5. Isolation of the GP3/MCLR/VPP pin from the rest of the circuit. Isolation of pins GP1 and GP0 from the rest of the circuit. Capacitance on each of the VDD, GP3/MCLR/ VPP, GP1, and GP0 pins. Interface to the programmer. Minimum and maximum operating voltage for VDD. TYPICAL APPLICATION CIRCUIT Application PCB PIC12C5XX VDD VDD GP3/MCLR/VPP ICSP Connector VDD VSS GP0 GP1 To application circuit Isolation circuits PICmicro, PRO MATE and PICSTART are registered trademarks of Microchip Technology Inc. In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc. 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-1 TB017 Isolation of the GP3/MCLR/VPP Pin from the Rest of the Circuit Total Capacitance on VDD, GP3/MCLR/VPP, GP1, and GP0 PIC12C5XX devices have two ways of configuring the MCLR pin: The total capacitance on the programming pins affects the rise rates of these signals as they are driven out of the programmer. Typical circuits use several hundred microfarads of capacitance on VDD, which helps to dampen noise and improve electromagnetic interference. However, this capacitance requires a fairly strong driver in the programmer to meet the rise rate timings for VDD. * MCLR can be connected either to an external RC circuit or * MCLR is tied internally to VDD When GP3/MCLR/VPP pin is connected to an external RC circuit, the pull-up resistor is tied to VDD, and a capacitor is tied to ground. This circuit can affect the operation of ICSP depending on the size of the capacitor. Another point of consideration with the GP3/MCLR/VPP pin, is that when the PICmicro MCU is programmed, this pin is driven up to 13V and also to ground. Therefore, the application circuit must be isolated from the voltage coming from the programmer. When MCLR is tied internally to VDD, the user has only to consider that up to 13V are present during programming of the GP3/MCLR/VPP pin. This might affect other components connected to that pin. For more information about configuring the GP3/ MCLR/VPP internally to VDD, please refer to the PIC12C5XX data sheet (DS40139). Isolation of Pins GP1 and GP0 from the Rest of the Circuit Pins GP1 and GP0 are used by the PICmicro MCU for serial programming. GP1 is the clock line and GP0 is the data line. GP1 is driven by the programmer. GP0 is a bidirectional pin that is driven by the programmer when programming and driven by the PICmicro MCU when verifying. These pins must be isolated from the rest of the application circuit so as not to affect the signals during programming. You must take into consideration the output impedance of the programmer when isolating GP1 and GP0 from the rest of the circuit. This isolation circuit must account for GP1 being an input on the PICmicro MCU and for GP0 being bidirectional pin. For example, PRO MATE(R) II has an output impedance of 1 k. If the design permits, these pins should not be used by the application. This is not the case with most designs. As a designer, you must consider what type of circuitry is connected to GP1 and GP0 and then make a decision on how to isolate these pins. DS91017B-page 2-2 Interface to the Programmer Most programmers are designed to simply program the PICmicro MCU itself and don't have strong enough drivers to power the application circuit. One solution is to use a driver board between the programmer and the application circuit. The driver board needs a separate power supply that is capable of driving the VPP, VDD, GP1, and GP0 pins with the correct ramp rates and also should provide enough current to power-up the application circuit. The cable length between the programmer and the circuit is also an important factor for ICSP. If the cable between the programmer and the circuit is too long, signal reflections may occur. These reflections can momentarily cause up to twice the voltage at the end of the cable, that was sent from the programmer. This voltage can cause a latch-up. In this case, a termination resistor has to be used at the end of the signal line. Minimum and Maximum Operating Voltage for VDD The PIC12C5XX programming specification states that the device should be programmed at 5V. Special considerations must be made if your application circuit operates at 3V only. These considerations may include totally isolating the PICmicro MCU during programming. The other point of consideration is that the device must be verified at minimum and maximum operation voltage of the circuit in order to ensure proper programming margin. For example, a battery driven system may operate from three 1.5V cells giving an operating voltage range of 2.7V to 4.5V. The programmer must program the device at 5V and must verify the program memory contents at both 2.7V and 4.5V to ensure that proper programming margins have been achieved. Preliminary 2000 Microchip Technology Inc. TB017 THE PROGRAMMER PIC12C5XX MCUs only use serial programming and, therefore, all programmers supporting these devices will support the ICSP. One issue with the programmer is the drive capability. As discussed before, it must be able to provide the specified rise rates on the ICSP signals and also provide enough current to power the application circuit. It is recommended that you buffer the programming signals. Another point of consideration for the programmer is what VDD levels are used to verify the memory contents of the PICmicro MCU. For instance, the PRO MATE II verifies program memory at the minimum and maximum VDD levels for the specified device and is therefore considered a production quality programmer. On the other hand, the PICSTART(R) Plus only verifies at 5V and is for prototyping use only. The PIC12C5XX programming specifications state that the program memory contents should be verified at both the minimum and maximum VDD levels that the application circuit will be operating. This implies that the application circuit must be able to handle the varying VDD voltages. There are also several third-party programmers that are available. You should select a programmer based on the features it has and how it fits into your programming environment. The Microchip Development Systems Ordering Guide (DS30177) provides detailed information on all our development tools. The Microchip Third Party Guide (DS00104) provides information on all of our third party development tool developers. Please consult these two references when selecting a programmer. Many options exist including serial or parallel PC host connection, stand-alone operation, and single or gang programmers. in the same configuration as the pads on the board. The application circuit is moved into position and the fixture is moved such that the spring loaded test pins come into contact with the board. This method might be more suitable for an automated assembly line. After taking into consideration the issues with the application circuit, the programmer, and the programming environment, anyone can build a high quality, reliable manufacturing line based on ICSP. OTHER BENEFITS ICSP provides several other benefits such as calibration and serialization. If program memory permits, it would be cheaper and more reliable to store calibration constants in program memory instead of using an external serial EEPROM. Field Programming of PICmicro OTP MCUs An OTP device is not normally capable of being reprogrammed, but the PICmicro MCU architecture gives you this flexibility provided the size of your firmware is less than half that of the desired device. This method involves using jump tables for the reset and interrupt vectors. Example 1 shows the location of a main routine and the reset vector for the first time a device with 0.5K-words of program memory is programmed. Example 2 shows the location of a second main routine and its reset vector for the second time the same device is programmed. You will notice that the GOTO Main that was previously at location 0x0002 is replaced with an NOP. An NOP is a program memory location with all the bits programmed as 0s. When the reset vector is executed, it will execute an NOP and then a GOTO Main1 instruction to the new code. PROGRAMMING ENVIRONMENT The programming environment will affect the type of programmer used, the programmer cable length, and the application circuit interface. Some programmers are well suited for a manual assembly line while others are desirable for an automated assembly line. A gang programmer should be chosen for programming multiple MCUs at one time. The physical distance between the programmer and the application circuit affects the load capacitance on each of the programming signals. This will directly affect the drive strength needed to provide the correct signal rise rates and current. Finally, the application circuit interface to the programmer depends on the size constraints of the application circuit itself and the assembly line. A simple header can be used to interface the application circuit to the programmer. This might be more desirable for a manual assembly line where a technician plugs the programmer cable into the board. A different method is the uses spring loaded test pins (often referred as pogo-pins). The application circuit has pads on the board for each of the programming signals. Then there is a movable fixture that has pogo pins 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-3 TB017 EXAMPLE 1: LOCATION OF THE FIRST MAIN ROUTINE AND ITS INTERRUPT VECTOR PROGRAM MEMORY 0X000 MOVWF OSCAL 0X001 GOTO MAIN1 RESET VECTOR UNPROGRAMMED 0X040 MAIN1 MAIN1 ROUTINE 0X080 UNPROGRAMMED 0X1FF MOVLW XX CALIBRATION VALUE LEGEND: XX = CALIBRATION VALUE DS91017B-page 2-4 Preliminary 2000 Microchip Technology Inc. TB017 EXAMPLE 2: LOCATION OF THE SECOND MAIN ROUTINE AND IT INTERRUPT VECTOR (AFTER SECOND PROGRAMMING) PROGRAM MEMORY 0X000 MOVWF OSCAL 0X001 0X002 NOP GOTO MAIN2 RESET VECTOR UNPROGRAMMED 0X040 MAIN1 MAIN1 ROUTINE 0X080 UNPROGRAMMED 0X10E MAIN2 MAIN2 ROUTINE 0X136 0X1FF MOVLW XX CALIBRATION VALUE LEGEND: XX = CALIBRATION VALUE 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-5 TB017 Since the program memory of the PIC12C5XX devices is organized in 256 x 12 word pages, placement of such information as look-up tables and CALL instructions must be taken into account. For further information, please refer to application note AN581, Implementing Long Calls and application note AN556, Implementing a Table Read. DS91017B-page 2-6 CONCLUSION Microchip Technology Inc. is committed to supporting your ICSP needs by providing you with our many years of experience and expertise in developing in-circuit system programming solutions. Anyone can create a reliable in-circuit system programming station by coupling our background with some forethought to the circuit design and programmer selection issues previously mentioned. Your local Microchip representative is available to answer any questions you have about the requirements for ICSP. Preliminary 2000 Microchip Technology Inc. VCC 2000 Microchip Technology Inc. VPP_IN Preliminary FROM PROGRAMMER GND_IN FROM PROGRAMMER GP1_IN FROM PROGRAMMER VDD_IN FROM PROGRAMMER U1B 7 U1D 14 TLE2144A 10k R4 TLE2144A 33k R2 GND_OUT TO CIRCUIT *see text in technical brief. R21 100k 12 13 R12 100k 5 6 EXTERNAL POWER SUPPLY VCC 15V C4 1NF C1 1NF GP1_OUT TO CIRCUIT 100 R19 100 R10 Note: 100 R18 100 R9 R22 5k Q4 2N2222 VCC Q3 2N3906 TO CIRCUIT GP0_OUT R17 100 R13 5k Q2 2N2222 VCC Q1 2N3906 The driver board design MUST be tested in the user's application to determine the effects of the applications circuit on the programming signals timing. Changes may be required if the application places a significant load on VDD, VPP, GP0 or GP1. *see text in technical brief. TLE2144A U1C 8 4 TLE2144A 1 U1A 1 FROM PROGRAMMER GP0_IN D2 6.2V 10 9 D1 12.7V 3 2 R9 100 C6 0.1F 1 R15 C3 0.1F 1 R6 VDD_OUT TO CIRCUIT TO CIRCUIT VPP_OUT TB017 APPENDIX A: SAMPLE DRIVER BOARD SCHEMATIC DS91017B-page 2-7 TB017 NOTES: DS91017B-page 2-8 Preliminary 2000 Microchip Technology Inc. TB013 How to Implement ICSPTM Using PIC16CXXX OTP MCUs Author: Application Circuit Rodger Richey Microchip Technology Inc. The application circuit must be designed to allow all the programming signals to be directly connected to the PICmicro MCU. Figure 1 shows a typical circuit that is a starting point for when designing with ICSP. The application must compensate for the following issues: INTRODUCTION In-Circuit Serial ProgrammingTM (ICSP) is a great way to reduce your inventory overhead and time-to-market for your product. By assembling your product with a blank Microchip microcontroller (MCU), you can stock one design. When an order has been placed, these units can be programmed with the latest revision of firmware, tested, and shipped in a very short time. This method also reduces scrapped inventory due to old firmware revisions. This type of manufacturing system can also facilitate quick turnarounds on custom orders for your product. Most people would think to use ICSP with PICmicro(R) OTP MCUs only on an assembly line where the device is programmed once. However, there is a method by which an OTP device can be programmed several times depending on the size of the firmware. This method, explained later, provides a way to field upgrade your firmware in a way similar to EEPROM- or Flash-based devices. HOW DOES ICSP WORK? Now that ICSP appeals to you, what steps do you take to implement it in your application? There are three main components of an ICSP system: Application Circuit, Programmer and Programming Environment. FIGURE 1: 1. 2. 3. 4. 5. 6. Isolation of the MCLR/VPP pin from the rest of the circuit. Isolation of pins RB6 and RB7 from the rest of the circuit. Capacitance on each of the VDD, MCLR/VPP, RB6, and RB7 pins. Minimum and maximum operating voltage for VDD. PICmicro Oscillator. Interface to the programmer. The MCLR/VPP pin is normally connected to an RC circuit. The pull-up resistor is tied to VDD and a capacitor is tied to ground. This circuit can affect the operation of ICSP depending on the size of the capacitor. It is, therefore, recommended that the circuit in Figure 1 be used when an RC is connected to MCLR/VPP. The diode should be a Schottky-type device. Another issue with MCLR/VPP is that when the PICmicro MCU device is programmed, this pin is driven to approximately 13V and also to ground. Therefore, the application circuit must be isolated from this voltage provided by the programmer. TYPICAL APPLICATION CIRCUIT Application PCB PIC16CXXX Vdd Vdd MCLR/Vpp ICSP Connector Vdd Vss RB7 RB6 To application circuit Isolation circuits 2000 Microchip Technology Inc. Preliminary DS91013B-page 2-9 TB013 Pins RB6 and RB7 are used by the PICmicro MCU for serial programming. RB6 is the clock line and RB7 is the data line. RB6 is driven by the programmer. RB7 is a bidirectional pin that is driven by the programmer when programming, and driven by the PICmicro MCU when verifying. These pins must be isolated from the rest of the application circuit so as not to affect the signals during programming. You must take into consideration the output impedance of the programmer when isolating RB6 and RB7 from the rest of the circuit. This isolation circuit must account for RB6 being an input on the PICmicro MCU, and for RB7 being bidirectional (can be driven by both the PICmicro MCU and the programmer). For instance, PRO MATE(R) II has an output impedance of 1k3/4. If the design permits, these pins should not be used by the application. This is not the case with most applications so it is recommended that the designer evaluate whether these signals need to be buffered. As a designer, you must consider what type of circuitry is connected to RB6 and RB7 and then make a decision on how to isolate these pins. Figure 1 does not show any circuitry to isolate RB6 and RB7 on the application circuit because this is very application dependent. The total capacitance on the programming pins affects the rise rates of these signals as they are driven out of the programmer. Typical circuits use several hundred microfarads of capacitance on VDD which helps to dampen noise and ripple. However, this capacitance requires a fairly strong driver in the programmer to meet the rise rate timings for VDD. Most programmers are designed to simply program the PICmicro MCU itself and don't have strong enough drivers to power the application circuit. One solution is to use a driver board between the programmer and the application circuit. The driver board requires a separate power supply that is capable of driving the VPP and VDD pins with the correct rise rates and should also provide enough current to power the application circuit. RB6 and RB7 are not buffered on this schematic but may require buffering depending upon the application. A sample driver board schematic is shown in Appendix A. Note: The driver board design MUST be tested in the user's application to determine the effects of the application circuit on the programming signals timing. Changes may be required if the application places a significant load on VDD, VPP, RB6 OR RB7. The Microchip programming specification states that the device should be programmed at 5V. Special considerations must be made if your application circuit operates at 3V only. These considerations may include totally isolating the PICmicro MCU during programming. The other issue is that the device must be verified at the minimum and maximum voltages at which the application circuit will be operating. For instance, a battery operated system may operate from three 1.5V cells giving an operating voltage range of 2.7V to 4.5V. DS91013B-page 2-10 The programmer must program the device at 5V and must verify the program memory contents at both 2.7V and 4.5V to ensure that proper programming margins have been achieved. This ensures the PICmicro MCU option over the voltage range of the system. This final issue deals with the oscillator circuit on the application board. The voltage on MCLR/VPP must rise to the specified program mode entry voltage before the device executes any code. The crystal modes available on the PICmicro MCU are not affected by this issue because the Oscillator Start-up Timer waits for 1024 oscillations before any code is executed. However, RC oscillators do not require any startup time and, therefore, the Oscillator Startup Timer is not used. The programmer must drive MCLR/VPP to the program mode entry voltage before the RC oscillator toggles four times. If the RC oscillator toggles four or more times, the program counter will be incremented to some value X. Now when the device enters programming mode, the program counter will not be zero and the programmer will start programming your code at an offset of X. There are several alternatives that can compensate for a slow rise rate on MCLR/VPP. The first method would be to not populate the R, program the device, and then insert the R. The other method would be to have the programming interface drive the OSC1 pin of the PICmicro MCU to ground while programming. This will prevent any oscillations from occurring during programming. Now all that is left is how to connect the application circuit to the programmer. This depends a lot on the programming environment and will be discussed in that section. Programmer The second consideration is the programmer. PIC16CXXX MCUs only use serial programming and therefore all programmers supporting these devices will support ICSP. One issue with the programmer is the drive capability. As discussed before, it must be able to provide the specified rise rates on the ICSP signals and also provide enough current to power the application circuit. Appendix A shows an example driver board. This driver schematic does not show any buffer circuitry for RB6 and RB7. It is recommended that an evaluation be performed to determine if buffering is required. Another issue with the programmer is what VDD levels are used to verify the memory contents of the PICmicro MCU. For instance, the PRO MATE II verifies program memory at the minimum and maximum VDD levels for the specified device and is therefore considered a production quality programmer. On the other hand, the PICSTART(R) Plus only verifies at 5V and is for prototyping use only. The Microchip programming specifications state that the program memory contents should be verified at both the minimum and maximum VDD levels that the application circuit will be operating. This implies that the application circuit must be able to handle the varying VDD voltages. Preliminary 2000 Microchip Technology Inc. TB013 There are also several third party programmers that are available. You should select a programmer based on the features it has and how it fits into your programming environment. The Microchip Development Systems Ordering Guide (DS30177) provides detailed information on all our development tools. The Microchip Third Party Guide (DS00104) provides information on all of our third party tool developers. Please consult these two references when selecting a programmer. Many options exist including serial or parallel PC host connection, stand-alone operation, and single or gang programmers. Some of the third party developers include Advanced Transdata Corporation, BP Microsystems, Data I/O, Emulation Technology and Logical Devices. Programming Environment The programming environment will affect the type of programmer used, the programmer cable length, and the application circuit interface. Some programmers are well suited for a manual assembly line while others are desirable for an automated assembly line. You may want to choose a gang programmer to program multiple systems at a time. The physical distance between the programmer and the application circuit affects the load capacitance on each of the programming signals. This will directly affect the drive strength needed to provide the correct signal rise rates and current. This programming cable must also be as short as possible and properly terminated and shielded, or the programming signals may be corrupted by ringing or noise. Finally, the application circuit interface to the programmer depends on the size constraints of the application circuit itself and the assembly line. A simple header can be used to interface the application circuit to the programmer. This might be more desirable for a manual assembly line where a technician plugs the programmer cable into the board. A different method is the use of spring loaded test pins (commonly referred to as pogo pins). The application circuit has pads on the board for each of the programming signals. Then there is a fixture that has pogo pins in the same configuration as the pads on the board. The application circuit or fixture is moved into position such that the pogo pins come into contact with the board. This method might be more suitable for an automated assembly line. After taking into consideration the issues with the application circuit, the programmer, and the programming environment, anyone can build a high quality, reliable manufacturing line based on ICSP. 2000 Microchip Technology Inc. Other Benefits ICSP provides other benefits, such as calibration and serialization. If program memory permits, it would be cheaper and more reliable to store calibration constants in program memory instead of using an external serial EEPROM. For example, your system has a thermistor which can vary from one system to another. Storing some calibration information in a table format allows the microcontroller to compensate in software for external component tolerances. System cost can be reduced without affecting the required performance of the system by using software calibration techniques. But how does this relate to ICSP? The PICmicro MCU has already been programmed with firmware that performs a calibration cycle. The calibration data is transferred to a calibration fixture. When all calibration data has been transferred, the fixture places the PICmicro MCU in programming mode and programs the PICmicro MCU with the calibration data. Application note AN656, In-Circuit Serial Programming of Calibration Parameters Using a PICmicro Microcontroller, shows exactly how to implement this type of calibration data programming. The other benefit of ICSP is serialization. Each individual system can be programmed with a unique or random serial number. One such application of a unique serial number would be for security systems. A typical system might use DIP switches to set the serial number. Instead, this number can be burned into program memory, thus reducing the overall system cost and lowering the risk of tampering. Field Programming of PICmicro OTP MCUs An OTP device is not normally capable of being reprogrammed, but the PICmicro MCU architecture gives you this flexibility provided the size of your firmware is at least half that of the desired device and the device is not code protected. If your target device does not have enough program memory, Microchip provides a wide spectrum of devices from 0.5K to 8K program memory with the same set of peripheral features that will help meet the criteria. The PIC16CXXX microcontrollers have two vectors, reset and interrupt, at locations 0x0000 and 0x0004. When the PICmicro MCU encounters a reset or interrupt condition, the code located at one of these two locations in program memory is executed. The first listing of Example 1 shows the code that is first programmed into the PICmicro MCU. The second listing of Example 1 shows the code that is programmed into the PICmicro MCU for the second time. Preliminary DS91013B-page 2-11 TB013 EXAMPLE 1: PROGRAMMING CYCLE LISTING FILES First Program Cycle Second Program Cycle _________________________________________________________________________________________ Prog Opcode Assembly |Prog Opcode Assembly Mem Instruction |Mem Instruction ----------------------------------------------------------------------------------------0000 2808 goto Main ;Main loop |0000 0000 nop 0001 3FFF <blank> ;at 0x0008 |0001 2860 goto Main ;Main now 0002 3FFF <blank> |0002 3FFF <blank> ;at 0x0060 0003 3FFF <blank> |0003 3FFF <blank> 0004 2848 goto ISR ;ISR at |0004 0000 nop 0005 3FFF <blank> ;0x0048 |0005 28A8 goto ISR ;ISR now at 0006 3FFF <blank> |0006 3FFF <blank> ;0x00A8 0007 3FFF <blank> |0007 3FFF <blank> 0008 1683 bsf STATUS,RP0 | 0008 1683 bsf STATUS,RP0 0009 3007 movlw 0x07 |0009 3007 movlw 0x07 000A 009F movwf ADCON1 |000A 009F movwf ADCON1 . | . . | . . | . 0048 1C0C btfss PIR1,RBIF | 0048 1C0C btfss PIR1,RBIF 0049 284E goto EndISR |0049 284E goto EndISR 004A 1806 btfsc PORTB,0 |004A 1806 btfsc PORTB,0 . | . . | . . | . 0060 3FFF <blank> |0060 1683 bsf STATUS,RP0 0061 3FFF <blank> |0061 3005 movlw 0x05 0062 3FFF <blank> |0062 009F movwf ADCON1 . | . . | . . | . 00A8 3FFF <blank> |00A8 1C0C btfss PIR1,RBIF 00A9 3FFF <blank> |00A9 28AE goto EndISR 00AA 3FFF <blank> |00AA 1806 btfsc PORTB,0 . | . . | . . | . ----------------------------------------------------------------------------------------- DS91013B-page 2-12 Preliminary 2000 Microchip Technology Inc. TB013 The example shows that to program the PICmicro MCU a second time the memory location 0x0000, originally goto Main (0x2808), is reprogrammed to all 0's which happens to be a nop instruction. This location cannot be reprogrammed to the new opcode (0x2860) because the bits that are 0's cannot be reprogrammed to 1's, only bits that are 1's can be reprogrammed to 0's. The next memory location 0x0001 was originally blank (all 1's) and now becomes a goto Main (0x2860). When a reset condition occurs, the PICmicro MCU executes the instruction at location 0x0000 which is the nop, a completely benign instruction, and then executes the goto Main to start the execution of code. The example also shows that all program memory locations after 0x005A are blank in the original program so that the second time the PICmicro MCU is programmed, the revised code can be programmed at these locations. The same descriptions can be given for the interrupt vector at location 0x0004. CONCLUSION Microchip Technology Inc. is committed to supporting your ICSP needs by providing you with our many years of experience and expertise in developing ICSP solutions. Anyone can create a reliable ICSP programming station by coupling our background with some forethought to the circuit design and programmer selection issues previously mentioned. Your local Microchip representative is available to answer any questions you have about the requirements for ICSP. This method changes slightly for PICmicro MCUs with >2K words of program memory. Each of the goto Main and goto ISR instructions are replaced by the following code segments due to paging on devices with >2K words of program memory. movlw <page> movwf PCLATH goto Main movlw <page> movwf PCLATH goto ISR Now your one time programmable PICmicro MCU is exhibiting more EEPROM- or Flash-like qualities. 2000 Microchip Technology Inc. Preliminary DS91013B-page 2-13 VCC DS91013B-page 2-14 VPP_IN Preliminary FROM PROGRAMMER GND_IN FROM PROGRAMMER RB6_IN FROM PROGRAMMER VDD_IN FROM PROGRAMMER U1D 14 TLE2144A 10k R4 TLE2144A U1B 7 GND_OUT TO CIRCUIT *see text in technical brief. R21 100k 12 13 R12 100k 5 33k R2 C4 1NF C1 1NF RB6_OUT TO CIRCUIT 100 R19 100 R10 Note: 100 R18 100 R9 R22 5k Q4 2N2222 VCC Q3 2N3906 TO CIRCUIT RB7_OUT R17 100 R13 5k Q2 2N2222 VCC Q1 2N3906 The driver board design MUST be tested in the user's application to determine the effects of the application circuit on the programming signals timing. Changes may be required if the application places a significant load on Vdd, Vpp, RB6 or RB7. *see text in technical brief. TLE2144A U1C 8 4 TLE2144A 1 U1A 1 FROM PROGRAMMER RB7_IN D2 6.2V 10 9 D1 12.7V 3 2 R9 100 C6 0.1F 1 R15 C3 0.1F 1 R6 VDD_OUT TO CIRCUIT TO CIRCUIT VPP_OUT APPENDIX A: 6 EXTERNAL POWER SUPPLY VCC 15V TB013 SAMPLE DRIVER BOARD SCHEMATIC 2000 Microchip Technology Inc. TB015 How to Implement ICSPTM Using PIC17CXXX OTP MCUs Author: Implementation Stan D'Souza Microchip Technology Inc. INTRODUCTION PIC17CXXX microcontroller (MCU) devices can be serially programmed using an RS-232 or equivalent serial interface. As shown in Figure 2, using just three pins, the PIC17CXXX can be connected to an external interface and programmed. In-Circuit Serial Programming (ICSPTM) allows for a greater flexibility in an application as well as a faster time to market for the user's product. This technical brief will demonstrate the practical aspects associated with ICSP using the PIC17CXXX. It will also demonstrate some key capabilities of OTP devices when used in conjunction with ICSP. FIGURE 2: The PIC17CXXX devices have special instructions, which enables the user to program and read the PIC17CXXX's program memory. The instructions are TABLWT and TLWT which implement the program memory write operation and TABLRD and TLRD which perform the program memory read operation. For more details, please check the In-Circuit Serial Programming for PIC17CXXX OTP Microcontrollers Specification (DS30273), PIC17C4X data sheet (DS30412) and PIC17C75X data sheet (DS30264). When doing ICSP, the PIC17CXXX runs a boot code, which configures the USART port and receives data serially through the RX line. This data is then programmed at the address specified in the serial data string. A high voltage (about 13V) is required for the EPROM cell to get programmed, and this is usually supplied by the programming header as shown in Figure 2 and Figure 3. The PIC17CXXX's boot code enables and disables the high voltage line using a dedicated I/O line. PIC17CXXX IN-CIRCUIT SERIAL PROGRAMMING USING TABLE WRITE INSTRUCTIONS PIC17CXXX SYSTEM BOARD I/O Data Memory 13V Enable Program Memory VPP 13V Data H:Data L Data L Data H Boot Code TX USART 2000 Microchip Technology Inc. RX Level Converter Preliminary In-Circuit Programming Connector DS91015A-page 2-15 TB015 FIGURE 3: PIC17CXXX IN-CIRCUIT SERIAL PROGRAMMING SCHEMATIC PIC17CXXX +5V Vdd 7805 2N3905 13V MCLR RA2 Programming Header +5V Serial Port RX TX RX MAX232 Serial Port TX Vss ICSP Boot Code The boot code is normally programmed, into the PIC17CXXX device using a PRO MATE(R) or PICSTART(R) Plus or any third party programmer. As depicted in the flowchart in Figure 5, on power-up, or a reset, the program execution always vectors to the boot code. The boot code is normally located at the bottom of the program memory space e.g. 0x700 for a PIC17C42A (Figure 4). Several methods could be used to reset the PIC17CXXX when the ICSP header is connected to the system board. The simplest method, as shown in Figure 3, is to derive the system 5V, from the 13V supplied by the ICSP header. It is quite common in manufacturing lines, to have system boards programmed with only the boot code ready and available for testing, calibration or final programming. The ICSP header would thus supply the 13V to the system and this 13V would then be stepped down to supply the 5V required to power the system. Please note that the 13V supply should have enough drive capability to supply power to the system as well as maintain the programming voltage of 13V. interrupt occurs. This delay ensures that the programming pulse width of 1 ms (max.) is met. Once a location is written, RA2 is driven high to disable further writes and a verify operation is done using the Table read instruction. If the result is good, an acknowledge is sent to the host. This process is repeated till all desired locations are programmed. In normal operation, when the ICSP header is not connected, the boot code would still execute and the PIC17CXXX would send out a request to the host. However it would not get a response from the host, so it would abort the boot code and start normal code execution. FIGURE 4: The first action of the boot code (as shown in flowchart Figure 5) is to configure the USART to a known baud rate and transmit a request sequence to the ICSP host system. The host immediately responds with an acknowledgment of this request. The boot code then gets ready to receive ICSP data. The host starts sending the data and address byte sequences to the PIC17CXXX. On receiving the address and data information, the 16-bit address is loaded into the TBLPTR registers and the 16-bit data is loaded into the TABLAT registers. The RA2 pin is driven low to enable 13V at MCLR. The PIC17CXXX device then executes a table write instruction. This instruction in turn causes a long write operation, which disables further code execution. Code execution is resumed when an internal DS91015A-page 2-16 Preliminary BOOT CODE EXAMPLE FOR PIC17C42A Program Memory Reset Vector 0x700 Boot Code 0x7FF 2000 Microchip Technology Inc. TB015 FIGURE 5: FLOWCHART FOR ICSP BOOT CODE Start Goto Boot Code Configure USART and send request Received Host's ACK? No Time-out complete? Yes Yes Prepare to receive ICSP data No No Start Code Execution Received Address and Data info? Yes Do Table Write operation No Interrupt? Yes Read Program Location Program location verified correctly? No Signal Programming Error Yes END No 2000 Microchip Technology Inc. Last Data/Address sequence? Yes Preliminary DS91015A-page 2-17 TB015 USING THE ICSP FEATURE ON PIC17CXXX OTP DEVICES Saving Field Calibration Information Using ICSP The ICSP feature is a very powerful tool when used in conjunction with OTP devices. Saving Calibration Information Using ICSP One key use of ICSP is to store calibration constants or parameters in program memory. It is quite common to interface a PIC17CXXX device to a sensor. Accurate, pre-calibrated sensors can be used, but they are more expensive and have long lead times. Uncalibrated sensors on the other hand are inexpensive and readily available. The only caveat is that these sensors have to be calibrated in the application. Once the calibration constants have been determined, they would be unique to a given system, so they have to be saved in program memory. These calibration parameters/constants can then be retrieved later during program execution and used to improve the accuracy of low cost un-calibrated sensors. ICSP thus offers a cost reduction path for the end user in the application. Sensors typically tend to drift and lose calibration over time and usage. One expensive solution would be to replace the sensor with a new one. A more cost effective solution however, is to re-calibrated the system and save the new calibration parameter/constants into the PIC17CXXX devices using ICSP. The user program however has to take into account certain issues: 1. 2. Un-programmed or blank locations have to be reserved at each calibration constant location in order to save new calibration parameters/constants. The old calibration parameters/constants are all programmed to 0, so the user program will have to be "intelligent" and differentiate between blank (0xFFFF), zero (0x0000), and programmed locations. Figure 6 shows how this can be achieved. Programming Unique Serial Numbers Using ICSP There are applications where each system needs to have a unique and sometimes random serial number. Example: security devices. One common solution is to have a set of DIP switches which are then set to a unique value during final test. A more cost effective solution however would be to program unique serial numbers into the device using ICSP. The user application can thus eliminate the need for DIP switches and subsequently reduce the cost of the system. FIGURE 6: FIELD CALIBRATION USING ICSP DS91015A-page 2-18 Factory Settings Field Calibrate #1 Field Calibrate #2 Parameter 1.1 0xFFFF 0xFFFF 0xFFFF Parameter 2.1 0xFFFF 0xFFFF 0xFFFF 0x0000 Parameter 1.2 0xFFFF 0xFFFF 0x0000 Parameter 2.2 0xFFFF 0xFFFF 0x0000 0x0000 Parameter 1.3 0xFFFF 0x0000 0x0000 Parameter 2.3 0xFFFF Preliminary 2000 Microchip Technology Inc. TB015 CONCLUSION Code Updates in the Field Using ICSP With fast time to market it is not uncommon to see application programs which need to be updated or corrected for either enhancements or minor errors/bugs. If ROM parts were used, updates would be impossible and the product would either become outdated or recalled from the field. A more cost effective solution is to use OTP devices with ICSP and program them in the field with the new updates. Figure 7 shows an example where the user has allowed for one field update to his program. ICSP is a very powerful feature available on the PIC17CXXX devices. It offers tremendous design flexibility to the end user in terms of saving calibration constants and updating code in final production as well as in the field, thus helping the user design a low-cost and fast time-to-market product. Here are some of the issues which need to be addressed: 1. 2. 3. 4. 5. The user has to reserve sufficient blank memory to fit his updated code. At least one blank location needs to be saved at the reset vector as well as for all the interrupts. Program all the old "goto" locations (located at the reset vector and the interrupts vectors) to 0 so that these instructions execute as NOPs. Program new "goto" locations (at the reset vector and the interrupt vectors) just below the old "goto" locations. Finally, program the new updated code in the blank memory space. FIGURE 7: CODE UPDATES USING ICSP Production Program Goto Boot Goto Main1 0xFFFF 0xFFFF Main Code Update #1 Goto Boot 0x0000 0x0000 0x0000 Goto Main2 0xFFFF Main Main1 Main1 Main2 Boot Boot Goto Main 2000 Microchip Technology Inc. Goto Main Preliminary DS91015A-page 2-19 TB015 NOTES: DS91015A-page 2-20 Preliminary 2000 Microchip Technology Inc. TB016 How to Implement ICSPTM Using PIC16F8X FLASH MCUs Author: Application Circuit Rodger Richey Microchip Technology Inc. The application circuit must be designed to allow all the programming signals to be directly connected to the PICmicro MCUs. Figure 1 shows a typical circuit that is a starting point for when designing with ICSP. The application must compensate for the following issues: INTRODUCTION In-Circuit Serial ProgrammingTM (ICSP) with PICmicro(R) FLASH microcontrollers (MCU) is not only a great way to reduce your inventory overhead and timeto-market for your product, but also to easily provide field upgrades of firmware. By assembling your product with a Microchip FLASH-based MCU, you can stock the shelf with one system. When an order has been placed, these units can be programmed with the latest revision of firmware, tested, and shipped in a very short time. This type of manufacturing system can also facilitate quick turnarounds on custom orders for your product. You don't have to worry about scrapped inventory because of the FLASH-based program memory. This gives you the advantage of upgrading the firmware at any time to fix those "features" that pop up from time to time. 1. 2. 3. 4. 5. 6. The MCLR/VPP pin is normally connected to an RC circuit. The pull-up resistor is tied to VDD and a capacitor is tied to ground. This circuit can affect the operation of ICSP depending on the size of the capacitor. It is, therefore, recommended that the circuit in Figure 1 be used when an RC is connected to MCLR/VPP. The diode should be a Schottky-type device. Another issue with MCLR/VPP is that when the PICmicro MCU device is programmed, this pin is driven to approximately 13V and also to ground. Therefore, the application circuit must be isolated from this voltage provided by the programmer. HOW DOES ICSP WORK? Now that ICSP appeals to you, what steps do you take to implement it in your application? There are three main components of an ICSP system. These are the: Application Circuit, Programmer and Programming Environment. FIGURE 1: Isolation of the MCLR/VPP pin from the rest of the circuit. Isolation of pins RB6 and RB7 from the rest of the circuit. Capacitance on each of the VDD, MCLR/VPP, RB6, and RB7 pins. Minimum and maximum operating voltage for VDD. PICmicro Oscillator. Interface to the programmer. TYPICAL APPLICATION CIRCUIT Application PCB PIC16F8X Vdd Vdd MCLR/VPP ICSP Connector Vdd Vss RB7 RB6 To application circuit Isolation circuits PICmicro, PRO MATE, and PICSTART are registered trademarks of Microchip Technology Inc. In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc. 2000 Microchip Technology Inc. DS91016B-page 2-21 TB016 Pins RB6 and RB7 are used by the PICmicro MCU for serial programming. RB6 is the clock line and RB7 is the data line. RB6 is driven by the programmer. RB7 is a bidirectional pin that is driven by the programmer when programming, and driven by the PICmicro MCU when verifying. These pins must be isolated from the rest of the application circuit so as not to affect the signals during programming. You must take into consideration the output impedance of the programmer when isolating RB6 and RB7 from the rest of the circuit. This isolation circuit must account for RB6 being an input on the PICmicro MCU and for RB7 being bidirectional (can be driven by both the PICmicro MCU and the programmer). For instance, PRO MATE(R) II has an output impedance of 1k3/4. If the design permits, these pins should not be used by the application. This is not the case with most applications so it is recommended that the designer evaluate whether these signals need to be buffered. As a designer, you must consider what type of circuitry is connected to RB6 and RB7 and then make a decision on how to isolate these pins. Figure 1 does not show any circuitry to isolate RB6 and RB7 on the application circuit because this is very application dependent. The total capacitance on the programming pins affects the rise rates of these signals as they are driven out of the programmer. Typical circuits use several hundred microfarads of capacitance on VDD which helps to dampen noise and ripple. However, this capacitance requires a fairly strong driver in the programmer to meet the rise rate timings for VDD. Most programmers are designed to simply program the PICmicro MCU itself and don't have strong enough drivers to power the application circuit. One solution is to use a driver board between the programmer and the application circuit. The driver board requires a separate power supply that is capable of driving the VPP and VDD pins with the correct rise rates and should also provide enough current to power the application circuit. RB6 and RB7 are not buffered on this schematic but may require buffering depending upon the application. A sample driver board schematic is shown in Appendix A. Note: The driver board design MUST be tested in the user's application to determine the effects of the application circuit on the programming signals timing. Changes may be required if the application places a significant load on Vdd, VPP, RB6 or RB7. The Microchip programming specification states that the device should be programmed at 5V. Special considerations must be made if your application circuit operates at 3V only. These considerations may include totally isolating the PICmicro MCU during programming. The other issue is that the device must be verified at the minimum and maximum voltages at which the application circuit will be operating. For instance, a battery operated system may operate from three 1.5V DS91016B-page 2-22 cells giving an operating voltage range of 2.7V to 4.5V. The programmer must program the device at 5V and must verify the program memory contents at both 2.7V and 4.5V to ensure that proper programming margins have been achieved. This ensures the PICmicro MCU option over the voltage range of the system. This final issue deals with the oscillator circuit on the application board. The voltage on MCLR/VPP must rise to the specified program mode entry voltage before the device executes any code. The crystal modes available on the PICmicro MCU are not affected by this issue because the Oscillator Start-up Timer waits for 1024 oscillations before any code is executed. However, RC oscillators do not require any startup time and, therefore, the Oscillator Startup Timer is not used. The programmer must drive MCLR/VPP to the program mode entry voltage before the RC oscillator toggles four times. If the RC oscillator toggles four or more times, the program counter will be incremented to some value X. Now when the device enters programming mode, the program counter will not be zero and the programmer will start programming your code at an offset of X. There are several alternatives that can compensate for a slow rise rate on MCLR/VPP. The first method would be to not populate the R, program the device, and then insert the R. The other method would be to have the programming interface drive the OSC1 pin of the PICmicro MCU to ground while programming. This will prevent any oscillations from occurring during programming. Now all that is left is how to connect the application circuit to the programmer. This depends a lot on the programming environment and will be discussed in that section. Programmer The second consideration is the programmer. PIC16F8X MCUs only use serial programming and therefore all programmers supporting these devices will support ICSP. One issue with the programmer is the drive capability. As discussed before, it must be able to provide the specified rise rates on the ICSP signals and also provide enough current to power the application circuit. Appendix A shows an example driver board. This driver schematic does not show any buffer circuitry for RB6 and RB7. It is recommended that an evaluation be performed to determine if buffering is required. Another issue with the programmer is what VDD levels are used to verify the memory contents of the PICmicro MCU. For instance, the PRO MATE II verifies program memory at the minimum and maximum VDD levels for the specified device and is therefore considered a production quality programmer. On the other hand, the PICSTART(R) Plus only verifies at 5V and is for prototyping use only. The Microchip programming specifications state that the program memory contents should be verified at both the minimum and maximum VDD levels that the application circuit will be operating. This implies that the application circuit must be able to handle the varying VDD voltages. 2000 Microchip Technology Inc. TB016 There are also several third party programmers that are available. You should select a programmer based on the features it has and how it fits into your programming environment. The Microchip Development Systems Ordering Guide (DS30177) provides detailed information on all our development tools. The Microchip Third Party Guide (DS00104) provides information on all of our third party tool developers. Please consult these two references when selecting a programmer. Many options exist including serial or parallel PC host connection, stand-alone operation, and single or gang programmers. Some of the third party developers include Advanced Transdata Corporation, BP Microsystems, Data I/O, Emulation Technology and Logical Devices. Programming Environment The programming environment will affect the type of programmer used, the programmer cable length, and the application circuit interface. Some programmers are well suited for a manual assembly line while others are desirable for an automated assembly line. You may want to choose a gang programmer to program multiple systems at a time. The physical distance between the programmer and the application circuit affects the load capacitance on each of the programming signals. This will directly affect the drive strength needed to provide the correct signal rise rates and current. This programming cable must also be as short as possible and properly terminated and shielded or the programming signals may be corrupted by ringing or noise. Finally, the application circuit interface to the programmer depends on the size constraints of the application circuit itself and the assembly line. A simple header can be used to interface the application circuit to the programmer. This might be more desirable for a manual assembly line where a technician plugs the programmer cable into the board. A different method is the use of spring loaded test pins (commonly referred to as pogo pins). The application circuit has pads on the board for each of the programming signals. Then there is a fixture that has pogo pins in the same configuration as the pads on the board. The application circuit or fixture is moved into position such that the pogo pins come into contact with the board. This method might be more suitable for an automated assembly line. After taking into consideration the issues with the application circuit, the programmer, and the programming environment, anyone can build a high quality, reliable manufacturing line based on ICSP. Other Benefits ICSP provides other benefits, such as calibration and serialization. If program memory permits, it would be cheaper and more reliable to store calibration constants in program memory instead of using an external serial EEPROM. For example, your system has a thermistor which can vary from one system to another. Storing some calibration information in a table format allows the microcontroller to compensate in software for external component tolerances. System cost can be reduced without affecting the required performance of the system by using software calibration techniques. But how does this relate to ICSP? The PICmicro MCU has already been programmed with firmware that performs a calibration cycle. The calibration data is transferred to a calibration fixture. When all calibration data has been transferred, the fixture places the PICmicro MCU in programming mode and programs the PICmicro MCU with the calibration data. Application note AN656, In-Circuit Serial Programming of Calibration Parameters Using a PICmicro Microcontroller, shows exactly how to implement this type of calibration data programming. The other benefit of ICSP is serialization. Each individual system can be programmed with a unique or random serial number. One such application of a unique serial number would be for security systems. A typical system might use DIP switches to set the serial number. Instead, this number can be burned into program memory thus reducing the overall system cost and lowering the risk of tampering. Field Programming of FLASH PICmicro MCUs With the ISP interface circuitry already in place, these FLASH-based PICmicro MCUs can be easily reprogrammed in the field. These FLASH devices allow you to reprogram them even if they are code protected. A portable ISP programming station might consist of a laptop computer and programmer. The technician plugs the ISP interface cable into the application circuit and downloads the new firmware into the PICmicro MCU. The next thing you know the system is up and running without those annoying "bugs". Another instance would be that you want to add an additional feature to your system. All of your current inventory can be converted to the new firmware and field upgrades can be performed to bring your installed base of systems up to the latest revision of firmware. CONCLUSION Microchip Technology Inc. is committed to supporting your ICSP needs by providing you with our many years of experience and expertise in developing ICSP solutions. Anyone can create a reliable ICSP programming station by coupling our background with some forethought to the circuit design and programmer selection issues previously mentioned. Your local Microchip representative is available to answer any questions you have about the requirements for ICSP. 2000 Microchip Technology Inc. DS91016B-page 2-23 Vcc DS91016B-page 2-24 VPP_IN FROM PROGRAMMER GND_IN FROM PROGRAMMER RB6_IN FROM PROGRAMMER Vdd_IN FROM PROGRAMMER U1D 14 TLE2144A 10k R4 TLE2144A U1B 7 GND_OUT TO CIRCUIT *see text in technical brief. R21 100k 12 13 R12 100k 5 33k R2 C4 1NF C1 1NF RB6_OUT TO CIRCUIT 100 R19 100 R10 Note: 100 R18 100 R9 *see text in technical brief. TLE2144A U1C 8 4 TLE2144A 1 U1A 1 R22 5k Q4 2N2222 Vcc Q3 2N3906 To Circuit RB7_OUT R17 100 R13 5k Q2 2N2222 Vcc Q1 2N3906 The driver board design MUST be tested in the user's application to determine the effects of the application circuit on the programming signals timing. Changes may be required if the application places a significant load on Vdd, VPP, RB6 or RB7. from programmer RB7_IN D2 6.2V 10 9 D1 12.7V 3 2 R9 100 C6 0.1mF 1 R15 C3 0.1mF 1 R6 VDD_OUT TO CIRCUIT TO CIRCUIT VPP_OUT APPENDIX A: 6 EXTERNAL POWER SUPPLY Vcc 15V TB016 SAMPLE DRIVER BOARD SCHEMATIC 2000 Microchip Technology Inc. SECTION 3 PROGRAMMING SPECIFICATIONS IN-CIRCUIT SERIAL PROGRAMMING FOR PIC12C5XX OTP MCUs .................................................. 3-1 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC12C67X AND PIC12CE67X OTP MCUs ................. 3-15 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC14000 OTP MCUs ................................................... 3-27 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16C55X OTP MCUs ................................................ 3-39 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16C6XX/7XX/9XX OTP MCUsS .............................. 3-51 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC17C7XX OTP MCUs ................................................ 3-71 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC18CXXX OTP MCUs ................................................ 3-97 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F62X FLASH MCUs ..........................................3-135 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F8X FLASH MCUs ............................................ 3-149 IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F8XX FLASH MCUs ..........................................3-165 2000 Microchip Technology Inc. DS30277C-page 3-i DS30277C-page 3-ii 2000 Microchip Technology Inc. PIC12C5XX In-Circuit Serial Programming for PIC12C5XX OTP MCUs This document includes the programming specifications for the following devices: 1.0 * PIC12C508A * PIC12C509A * PIC12CE518 * PIC12CE519 PROGRAMMING THE PIC12C5XX PDIP, SOIC, JW VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2/CLKOUT 3 GP3/MCLR/Vpp 4 PIC12C5XX PIC12C5XXA PIC12CE5XXA * PIC12C508 * PIC12C509 Pin Diagram 8 VSS 7 GP0 6 GP1 5 GP2/T0CKI The PIC12C5XX can be programmed using a serial method. Due to this serial programming, the PIC12C5XX can be programmed while in the user's system increasing design flexibility. This programming specification applies to PIC12C5XX devices in all packages. 1.1 Hardware Requirements The PIC12C5XX requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC12C5XX allows programming of user program memory, special locations used for ID, and the configuration word for the PIC12C5XX. 2000 Microchip Technology Inc. DS30557E-page 3-1 PIC12C5XX 2.0 PROGRAM MODE ENTRY The program/verify test mode is entered by holding pins DB0 and DB1 low while raising MCLR pin from VIL to VIHH. Once in this test mode the user program memory and the test program memory can be accessed and programmed in a serial fashion. The first selected memory location is the fuses. GP0 and GP1 are Schmitt trigger inputs in this mode. Incrementing the PC once (using the increment address command) selects location 0x000 of the regular program memory. Afterwards all other memory locations from 0x001-01FF (PIC12C508/CE518), 0x00103FF (PIC12C509/CE519) can be addressed by incrementing the PC. If the program counter has reached the last user program location and is incremented again, the on-chip special EPROM area will be addressed. (See Figure 2-2 to determine where the special EPROM area is located for the various PIC12C5XX devices). 2.1 Programming Method The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable power supply for VCC. 2.1.1 PROGRAMMING METHOD DETAILS Essentially, this technique includes the following steps: 1. 2. a) Perform blank check at VDD = VDDmin. Report failure. The device may not be properly erased. Program location with pulses and verify after each pulse at VDD = VDDP: where VDDP = VDD range required during programming (4.5V - 5.5V). Programming condition: VPP = 13.0V to 13.25V VDD = VDDP = 4.5V to 5.5V VPP must be VDD + 7.25V to keep "programming mode" active. b) 5. 6. VDDmin is the minimum operating voltage spec. for the part. VDDmax is the maximum operating voltage spec. for the part. 2.1.2 VPP: VPP can be a fixed 13.0V to 13.25V supply. It must not exceed 14.0V to avoid damage to the pin and should be current limited to approximately 100mA. VDD: 2.0V to 6.5V with 0.25V granularity. Since this method calls for verification at different VDD values, a programmable VDD power supply is needed. Current Requirement: 40mA maximum Microchip may release devices in the future with different VDD ranges which make it necessary to have a programmable VDD. It is important to verify an EPROM at the voltages specified in this method to remain consistent with M i c r o c h i p ' s t e s t s c r e e n i n g . Fo r ex a m p l e , a PIC12C5XX specified for 4.5V to 5.5V should be tested for proper programming from 4.5V to 5.5V. Note: Any programmer not meeting the programmable VDD requirement and the verify at VDDmax and VDDmin requirement may only be classified as "prototype" or "development" programmer but not a production programmer. 2.1.3 SOFTWARE REQUIREMENTS Certain parameters should be programmable (and therefore easily modified) for easy upgrade. a) b) c) Verify condition: Pulse width Maximum number of pulses, present limit 8. Number of over-programming pulses: should be = (A * N) + B, where N = number of pulses required in regular programming. In our current algorithm A = 11, B = 0. VPP VDD + 7.5V but not to exceed 13.25V 2.2 If location fails to program after "N" pulses, (suggested maximum program pulses of 8) then report error as a programming failure. Program Memory Cells: When programming one word of EPROM, a programming pulse width (TPW) of 100s is recommended. Note: 4. SYSTEM REQUIREMENTS Clearly, to implement this technique, the most stringent requirements will be that of the power supplies: VDD = VDDP 3. Verify all locations (using speed verify mode) at VDD = VDDmin Verify all locations at VDD = VDDmax Device must be verified at minimum and maximum specified operating voltages as specified in the data sheet. Once location passes "Step 2", apply 11X over programming, i.e., apply 11 times the number of pulses that were required to program the location. This will guarantee a solid programming margin. The over programming should be made "software programmable" for easy updates. Program all locations. DS30557E-page 3-2 Programming Pulse Width The maximum number of programming attempts should be limited to 8 per word. After the first successful verify, the same location should be over-programmed with 11X over-programming. Configuration Word: The configuration word for oscillator selection, WDT (watchdog timer) disable and code protection, and MCLR enable, requires a programming pulse width (TPWF) of 10ms. A series of 100s pulses is preferred over a single 10ms pulse. 2000 Microchip Technology Inc. PIC12C5XX FIGURE 2-1: PROGRAMMING METHOD FLOWCHART Start Blank Check @ VDD = VDDmin Report Possible Erase Failure Continue Programming at user's option No Pass? Report Programming Failure Yes Yes Program 1 Location @ VPP = 13.0V to 13.25V VDD = VDDP No Pass? No N > 8? N=N+1 (N = # of program pulses) Yes Increment PC to point to next location, N = 0 Apply 11N additional program pulses No All locations done? Yes Verify all locations @ VDD = VDDmin No Pass? Report verify failure @ VDDmin Yes Verify all locations DD VDD @VV DD= = VDDmax. max No Pass? Report verify failure @ VDDmax Yes Now program Configuration Word Verify Configuration Word @ VDDmax & VDDmin Done 2000 Microchip Technology Inc. DS30557E-page 3-3 PIC12C5XX FIGURE 2-2: PIC12C5XX SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE Address 11 (Hex) 000 NNN Bit Number 0 User Program Memory (NNN + 1) x 12 bit TTT 0 0 ID0 TTT + 1 0 0 0 0 ID1 ID2 0 0 ID3 TTT + 2 TTT + 3 For Customer Use (4 x 4 bit usable) For Factory Use TTT + 3F (FFF) Configuration Word 5 bits NNN Highest normal EPROM memory address. NNN = 0x1FF for PIC12C508/CE518. NNN = 0x3FF for PIC12C509/CE519. Note that some versions will have an oscillator calibration value programmed at NNN TTT Start address of special EPROM area and ID locations. DS30557E-page 3-4 2000 Microchip Technology Inc. PIC12C5XX 2.3 Special Memory Locations The highest address of program memory space is reserved for the internal RC oscillator calibration value. This location should not be overwritten except when this location is blank, and it should be verified, when programmed, that it is a MOVLW XX instruction. The ID Locations area is only enabled if the device is in programming/verify mode. Thus, in normal operation mode only the memory location 0x000 to 0xNNN will be accessed and the Program Counter will just roll over from address 0xNNN to 0x000 when incremented. The configuration word can only be accessed immediately after MCLR going from VIL to VHH. The Program Counter will be set to all '1's upon MCLR = VIL. Thus, it has the value "0xFFF" when accessing the configuration EPROM. Incrementing the Program Counter once causes the Program Counter to roll over to all '0's. Incrementing the Program Counter 4K times after reset (MCLR = VIL) does not allow access to the configuration EPROM. 2.3.1 2.4 Program/Verify Mode The program/verify mode is entered by holding pins GP1 and GP0 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial. GP0 and GP1 are Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: The MCLR pin should be raised from VIL to VIHH within 9 ms of VDD rise. This is to ensure that the device does not have the PC incremented while in valid operation range. CUSTOMER ID CODE LOCATIONS Per definition, the first four words (address TTT to TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with '0's. A user may want to store an identification code (ID) in the ID locations and still be able to read this code after the code protection bit was programmed. EXAMPLE 2-1: CUSTOMER CODE 0xD1E2 The Customer ID code "0xD1E2" should be stored in the ID locations 0x200-0x203 like this (PIC12C508/ 508A/CE518): 200: 201: 202: 203: 0000 0000 0000 0000 0000 0000 0000 0000 1101 0001 1110 0010 Reading these four memory locations, even with the code protection bit programmed would still output on GP0 the bit sequence "1101", "0001", "1110", "0010" which is "0xD1E2". Note: All other locations in PICmicro(R) MCU configuration memory are reserved and should not be programmed. 2000 Microchip Technology Inc. DS30557E-page 3-5 PIC12C5XX 2.4.1 PROGRAM/VERIFY OPERATION All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). The GP1 pin is used as a clock input pin, and the GP0 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (GP1) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin GP0 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin GP0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. TABLE 2-1: The commands that are available are listed in Table . COMMAND MAPPING Command Mapping (MSB ... LSB) Data Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: The clock must be disabled during in-circuit programming. DS30557E-page 3-6 2000 Microchip Technology Inc. PIC12C5XX 2.4.1.1 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. Because this is a 12 bit core, the two msb's of the data word are ignored. A timing diagram for the load data command is shown in Figure 5-1. 2.4.1.2 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The GP0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. Because this is a 12bit core, the two MSB's of the data are unused and read as '0'. A timing diagram of this command is shown in Figure 5-2. 2.4.1.3 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.4.1.4 2.5 Programming Algorithm Requires Variable VDD The PIC12C5XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC12C5XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC12C5XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. BEGIN PROGRAMMING A load data command must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.4.1.5 END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 2000 Microchip Technology Inc. DS30557E-page 3-7 PIC12C5XX 3.0 CONFIGURATION WORD The PIC12C5XX family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. FIGURE 3-1: CONFIGURATION WORD BIT MAP Bit Number: PIC12C5XX 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- MCLRE CP WDTE FOSC1 FOSC0 bit 11-5:Reserved, '-' write as '0' for PIC12C5XX bit 4: MCLRE, Master Clear pin Enable Bit 0 = MCLR internally connected to Vdd 1 = MCLR pin enabled bit 3: CP, Code Protect Enable Bit 1 = Code Memory Unprotected 0 = Code Memory Protected bit 2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC<1:0>, Oscillator Selection Bit 11: ExtRC oscillator 10: IntRC oscillator 01: XT oscillator 00: LP oscillator DS30557E-page 3-8 2000 Microchip Technology Inc. PIC12C5XX 4.0 CODE PROTECTION The program code written into the EPROM can be protected by writing to the CP bit of the configuration word. In PIC12C5XX, it is still possible to program and read locations 0x000 through 0x03F, after code protection. Once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected 4.1 segments, including ID locations and configuration word, read normally. These locations can be programmed. Once code protection is enabled, all code protected locations read 0's. All unprotected segments, including the internal oscillator calibration value, ID, and configuration word read as normal. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: CODE PROTECTION PIC12C508 To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled [0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled [0x40:0x1FF] Read Disabled (all 0's), Write Disabled Read Enabled, Write Enabled ID Locations (0x200 : 0x203) Read Enabled, Write Enabled Read Enabled, Write Enabled PIC12C508A To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x1FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled PIC12C509 To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FF] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled 2000 Microchip Technology Inc. DS30557E-page 3-9 PIC12C5XX PIC12C509A To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x3FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled PIC12CE518 To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x1FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled PIC12CE519 To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FF] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled DS30557E-page 3-10 2000 Microchip Technology Inc. PIC12C5XX 4.2 Checksum 4.2.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC12C5XX memory locations and adding up the opcodes up to the maximum user addressable location, (not including the last location which is reserved for the oscillator calibration value) e.g., 0x1FE for the PIC12C508/CE518. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC12C5XX family is shown in Table 4-2. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. The oscillator calibration value location is not used in the above checksums. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. TABLE 4-2: CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x723 at 0 and max address PIC12C508 OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12C508A OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12C509 OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 PIC12C509A OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 PIC12CE518 OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12CE519 OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 Device Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND 2000 Microchip Technology Inc. DS30557E-page 3-11 PIC12C5XX 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic PD1 VDDP Supply voltage during programming PD2 IDDP Supply current (from VDD) during programming Min. Typ. Max. Units 4.75 5.0 5.25 V 20 mA Conditions General PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 13.25 V Note 2 PD5 VIHH2 PD6 IPP Programming supply current (from VPP) PD9 VIH1 (GP1, GP0) input high level 0.8 VDD V Schmitt Trigger input PD8 VIL1 (GP1, GP0) input low level 0.2 VDD V Schmitt Trigger input Voltage on MCLR/VPP during verify VDD + 4.0 13.5 50 mA Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VHH) 8.0 s P2 Tf MCLR Fall time 8.0 s P3 Tset1 Data in setup time before clock 100 ns P4 Thld1 Data in hold time after clock 100 ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 s P6 Tdly2 Delay between clock to clock of next command or data 1.0 s P7 Tdly3 Clock to date out valid (during read data) 200 ns P8 Thld0 Hold time after MCLR 2 s Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. DS30557E-page 3-12 2000 Microchip Technology Inc. PIC12C5XX FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 GP1 (CLOCK) GP0 (DATA) 0 1 2 1ms min. 1 6 4 5 15 0 0 0 P5 P3 P3 1ms min. P4 P4 } } } } 100ns min. 100ns min. Program/Verify Mode Reset FIGURE 5-2: 3 READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 GP1 (CLOCK) GP0 (DATA) 0 0 2 1ms min. 1 6 3 4 5 15 P7 0 P5 P4 1ms min. P3 } } 100ns min. GP0 input GP0 = output Program/Verify Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 1ms min. Next Command 1 2 GP1 (CLOCK) GP0 (DATA) 1 0 0 P5 P3 P4 1ms min. } } 100ns min Program/Verify Mode Reset 2000 Microchip Technology Inc. DS30557E-page 3-13 PIC12C5XX DS30557E-page 3-14 2000 Microchip Technology Inc. PIC12C67X AND PIC12CE67X In-Circuit Serial Programming for PIC12C67X and PIC12CE67X OTP MCUs This document includes the programming specifications for the following devices: PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 1.0 PROGRAMMING THE PIC12C67X AND PIC12CE67X 1.1 VDD 1 GP5/OSC1/CLKIN GP4/OSC2/AN3/ CLKOUT GP3/MCLR/VPP 2 3 4 8 VSS 7 GP0/AN0 6 GP1/AN1/VREF 5 GP2/T0CKI/ AN2/INT PDIP, JW VDD 1 GP5/OSC1/CLKIN GP4/OSC2/AN3/ CLKOUT GP3/MCLR/VPP 2 3 4 PIC12CE67X The PIC12C67X and PIC12CE67X can be programmed using a serial method. In serial mode the PIC12C67X and PIC12CE67X can be programmed while in the users system. This allows for increased design flexibility. PDIP, SOIC, JW PIC12C67X * * * * Pin Diagram: 8 VSS 7 GP0/AN0 6 GP1/AN1/VREF 5 GP2/T0CKI/ AN2/INT Hardware Requirements The PIC12C67X and PIC12CE67X requires two programmable power supplies, one for VDD (2.0V to 6.0V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC12C67X and PIC12CE67X allows programming of user program memory, special locations used for ID, and the configuration word for the PIC12C67X and PIC12CE67X. 2000 Microchip Technology Inc. DS40175B-page 3-15 PIC12C67X and PIC12CE67X 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC12C67X family. TABLE 2-1: IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC12C67X Device Program Memory Size PIC12C671/ PIC12CE673 0x000 - 0x3FF (1K) PIC12C672/ PIC12CE674 0x000 - 0x7FF (2K) When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. The last location of the program memory space holds the factory programmed oscillator calibration value. This location should not be programmed except when blank (a non-blank value should not cause the device to fail a blank check). If blank, the programmer should program it to a RETLW XX statement where "XX" is the calibration value. In the configuration memory space, 0x2000-0x20FF are utilized. When in configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as the PC exceeds 0x2XFF (see Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000: 0x2003]. Note 1: All other locations in PICmicro(R) MCU configuration memory are reserved and should not be programmed. 2: Due to the secure nature of the on-board EEPROM memory in the PIC12CE673/674, it can be accessed only by the user program. DS40175B-page 3-16 2000 Microchip Technology Inc. PIC12C67X and PIC12CE67X FIGURE 2-1: PROGRAM MEMORY MAPPING 0 1FF 3FF 400 7FF 800 2000 ID Location 2001 ID Location 2002 ID Location 2003 ID Location BFF C00 2004 Reserved FFF 1000 2005 Reserved 2006 Reserved 1KW 2KW Implemented Implemented Implemented Reserved Reserved 2007 Configuration Word 1FFF 2000 2008 Reserved Reserved Reserved Reserved 2100 3FFF 2000 Microchip Technology Inc. DS40175B-page 3-17 PIC12C67X and PIC12CE67X 2.2 Program/Verify Mode 2.2.1 PROGRAM/VERIFY OPERATION The GP1 pin is used as a clock input pin, and the GP0 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (GP1) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin GP0 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin GP0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. The program/verify mode is entered by holding pins GP1 and GP0 low while raising MCLR pin from VIL to VIHH (high voltage). VDD is then raised from VIL to VIH.Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. GP1 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note 1:The MCLR pin must be raised from VIL to VIHH before VDD is applied. This is to ensure that the device does not have the PC incremented while in valid operation range. Note 2:Do not power GP2, GP4 or GP5 before VDD is applied. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1s is required between a command and a data word (or another command). The commands that are available are listed in Table . 2.2.1.1 LOAD CONFIGURATION After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). TABLE 1-1: COMMAND MAPPING Command Mapping (MSB ... LSB) Data Load Configuration 0 0 0 0 0 0 0, data(14), 0 Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 DS40175B-page 3-18 2000 Microchip Technology Inc. PIC12C67X and PIC12CE67X FIGURE 2-2: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X PROGRAM MEMORY Start Set VPP = VIHH1 Set VDD = VDDP* N=0 No N > 25 Program Cycle Read Data Command Yes Report Programming Failure N=N+1 N = # of Program Cycles No Increment Address Command Data Correct? Yes Program Cycle Apply 3N Additional Program Cycles No Load Data Command All Locations Done? Begin Programming Command Yes Verify all Locations @ VDD MIN.* VPP = VIHH2 Wait 100 s No Data Correct? Report Verify @ VDD MIN. Error End Programming Command Yes Verify all Locations @ VDD MAX. VPP = VIHH2 No Data Correct? Report Verify @ VDD MAX Error Yes Done * VDDP = VDD range for programming (typically 4.75V - 5.25V). VDD MIN. = Minimum VDD for device operation. VDD MAX. = Maximum VDD for device operation. 2000 Microchip Technology Inc. DS40175B-page 3-19 PIC12C67X and PIC12CE67X FIGURE 2-3: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X CONFIGURATION WORD & ID LOCATIONS Start Set VPP = VIHH1 Load Configuration Command N=0 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1 N = # of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command ID/Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No Done DS40175B-page 3-20 Yes Data Correct? No Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD DDmax max Read Data Command Set VPP = VIHH2 2000 Microchip Technology Inc. PIC12C67X and PIC12CE67X 2.2.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.2.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The GP0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.2.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.2.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 2.3 Programming Algorithm Requires Variable VDD The PIC12C67X and PIC12CE67X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDD max.= maximum operating VDD spec for the part. Programmers must verify the PIC12C67X and PIC12CE67X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC12C67X and PIC12CE67X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 2000 Microchip Technology Inc. DS40175B-page 3-21 PIC12C67X and PIC12CE67X 3.0 CONFIGURATION WORD The PIC12C67X and PIC12CE67X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to FIGURE 3-1: select various device configurations. Figure 3-1 provides an overview of configuration bits. CONFIGURATION WORD Bit Number: 13 12 11 10 9 8 7 6 5 4 CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE 3 2 WDTE FOSC2 1 0 FOSC1 FOSC0 Register: Address CONFIG 2007h bit 13-8, 6-5: CP1:CP0: Code Protection bits (1) (2) 11 = Code protection off 10 = 0400h-07FFh code protected; 01 = 0200h-07FFh code protected; 00 = 0000h-07FFh code protected; bit 7: MCLRE: GP3/MCLR pin function select 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to Vdd bit 4: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 3: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0: FOSC2:FOSC0: Oscillator Selection bits 111 = EXTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin 110 = EXTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin 101 = INTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin 100 = INTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator 3: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 4: 07FFh is always uncode protected on the 12C672 and 03FFh is always uncode protected on the 12C671. This location contains the RETLW xx calibration instruction for the INTRC. DS40175B-page 3-22 2000 Microchip Technology Inc. PIC12C67X and PIC12CE67X 4.0 CODE PROTECTION The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word. For PIC12C67X and PIC12CE67X devices, once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID and configuration word locations, and calibration word location read normally and can be programmed. 4.1 Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 1-2: CONFIGURATION WORD PIC12C671, PIC12CE673 To code protect: * Protect all memory * Protect 0200h-07FFh * No code protection 00 0000 X00X XXXX 01 0101 X01X XXXX 11 1111 X11X XXXX Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Unprotected memory segment Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Protected memory segment Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled INTRC Calibration Word (0X3FF) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC12C672, PIC12CE674 To code protect: * Protect all memory * Protect 0200h-07FFh * Protect 0400h-07FFh * No code protection 00 01 10 11 Program Memory Segment 0000 0101 1010 1111 X00X X01X X10X X11X XXXX XXXX XXXX XXXX R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Unprotected memory segment Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Protected memory segment Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled INTRC Calibration Word (0X7FF) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled 2000 Microchip Technology Inc. DS40175B-page 3-23 PIC12C67X and PIC12CE67X 4.2 Checksum * Masked ID locations (when applicable) 4.2.1 CHECKSUM CALCULATIONS The least significant 16 bits of this sum is the checksum. Checksum is calculated by reading the contents of the PIC12C67X and PIC12CE67X memory locations and adding the opcodes up to the maximum user addressable location, excluding the oscillator calibration location in the last address, e.g., 0x3FE for the PIC12C671/ CE673. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC12C67X and PIC12CE67X devices is shown in Table 4-1. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked TABLE 4-1: The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect Checksum* Blank Value Ox25E6 at 0 and max address PIC12C671 PIC12CE673 OFF 1/2 ALL SUM[0x000:0x3FE] + CFGW & 0x3FFF SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID CFGW & 0x3FFF + SUM_ID 3B3F 4E5E 3B4E 070D 0013 071C PIC12C672 PIC12CE674 OFF 1/2 3/4 ALL SUM[0x000:0x7FE] + CFGW & 0x3FFF SUM[0x000:0x3FF] + CFGW & 0x3FFF + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID CFGW & 0x3FFF + SUM_ID 373F 5D6E 4A5E 374E 030D 0F23 FC13 031C Device Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS40175B-page 3-24 2000 Microchip Technology Inc. PIC12C67X and PIC12CE67X 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 1-3: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (25C is recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic PD1 VDDP Supply voltage during programming PD2 IDDP Supply current (from VDD) during programming Min. Typ. Max. Units 4.75 5.0 5.25 V 20 mA Conditions General PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 13.25 V Note 2 PD5 VIHH2 PD6 IPP Programming supply current (from VPP) PD9 VIH1 (GP0, GP1) input high level 0.8 VDD V Schmitt Trigger input PD8 VIL1 (GP0, GP1) input low level 0.2 VDD V Schmitt Trigger input Voltage on MCLR/VPP during verify VDD + 4.0 13.5 50 mA Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VIHH) for test mode entry 8.0 s 8.0 s P2 Tf MCLR Fall time P3 Tset1 Data in setup time before clock 100 ns P4 Thld1 Data in hold time after clock 100 ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 s P6 Tdly2 Delay between clock to clock of next command or data 1.0 s P7 Tdly3 Clock to data out valid (during read data) 200 ns P8 Thld0 Hold time after VDD 2 s P9 TPPDP Hold time after VPP 5 s Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS40175B-page 3-25 PIC12C67X and PIC12CE67X FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/VPP 100ns P8 1 P6 3 2 4 5 6 GP1 (CLOCK) GP0 (DATA) 0 100ns 0 1 0 0 1 1s min. 2 4 5 15 0 0 0 P5 P3 P4 P3 1s min. P4 } } } } 100ns min. 100ns min. Program/Verify Mode Reset FIGURE 5-2: 3 READ DATA COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/V PP 100ns P8 1 P6 2 3 4 5 6 1s min. GP1 (CLOCK) GP0 (DATA) 0 100ns 1 0 0 0 1 2 3 4 5 15 P7 0 P5 P3 P4 1s min. } } 100ns min. RB7 input RB7 = output Program/Verify Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/VPP P6 1 2 3 4 5 Next Command 1s min. 6 1 2 GP1 (CLOCK) GP0 (DATA) 0 1 1 0 0 0 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Mode Reset DS40175B-page 3-26 2000 Microchip Technology Inc. PIC14000 In-Circuit Serial Programming for PIC14000 OTP MCUs This document includes the programming specifications for the following devices: * PIC14000 PROGRAMMING THE PIC14000 The PIC14000 can be programmed using a serial method. In serial mode the PIC14000 can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC14000 devices in all packages. 1.1 Hardware Requirements PDIP, SOIC, SSOP, Windowed CERDIP RA1/AN1 *1 28 RA2/AN2 RA0/AN0 2 27 RA3/AN3 RD3/REFB 3 26 RD4/AN4 RD2/CMPB 4 25 RD5/AN5 RD1/SDAB 5 24 RD6/AN6 RD0/SCLB 6 23 RD7/AN7 OSC2/CLKOUT 7 22 CDAC OSC1/PBTN 8 21 SUM VDD 9 20 VSS 19 RC0/REFA PIC14000 1.0 PIN DIAGRAM VREG 10 RC7/SDAA 11 18 RC1/CMPA RC6/SCLA 12 17 RC2 RC5 13 16 RC3/T0CKI MCLR/VPP 14 15 RC4 The PIC14000 requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). 1.2 Programming Mode The programming mode for the PIC14000 allows programming of user program memory, configuration word, and calibration memory. 2000 Microchip Technology Inc. DS30555B-page 3-27 PIC14000 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The program and calibration memory space extends from 0x000 to 0xFFF (4096 words). Table 2-1 shows actual implementation of program memory in the PIC14000. TABLE 2-1: IMPLEMENTATION OF PROGRAM AND CALIBRATION MEMORY IN THE PIC14000P Area Memory Space Access to Memory Program Calibration 0x000-0xFBF 0xFC0 -0xFFF PC<12:0> PC<12:0> When the PC reaches address 0xFFF, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x0000, or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. In the configuration memory space, 0x2000-0x20FF are utilized. When in configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as PC exceeds 0x2XFF (Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000: 0x2003]. All other locations are reserved and should not be programmed. The ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.1. DS30555B-page 3-28 2000 Microchip Technology Inc. PIC14000 FIGURE 2-1: PROGRAM MEMORY MAPPING 0 Program 2000 ID Location 0FBF 0FC0 Calibration 2001 ID Location 2002 ID Location 2003 ID Location 2004 Reserved 2005 Reserved 2006 Reserved 2007 Configuration Word 0FFF Reserved 1FFF 2000 Test 20FF Reserved 3FFF 2000 Microchip Technology Inc. DS30555B-page 3-29 PIC14000 2.2 Program/Verify Mode have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RC7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. The program/verify mode is entered by holding pins RC6 and RC7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RC6 and RC7 are both Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: 2.2.1 All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1s is required between a command and a data word (or another command). The MCLR pin should be raised as quickly as possible from VIL to VIHH. This is to ensure that the device does not have the PC incremented while in valid operation range. The commands that are available are listed in Table . 2.2.1.1 After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). PROGRAM/VERIFY OPERATION The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RC6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RC7 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to TABLE 2-1: LOAD CONFIGURATION COMMAND MAPPING Command Load Configuration Mapping (MSB ... LSB) 0 0 0 0 0 Data 0 0, data(14), 0 Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: The CPU clock must be disabled during in-circuit programming (to avoid incrementing the PC). DS30555B-page 3-30 2000 Microchip Technology Inc. PIC14000 FIGURE 2-2: PROGRAM FLOW CHART - PIC14000 PROGRAM MEMORY AND CALIBRATION Start Set VDD = VDDP* N=0 No Program Cycle N > 25 Read Data Command Increment Address Command Data Correct? Yes Report Programming Failure N=N+1 N=# of Program Cycles No Yes Apply 3N Additional Program Cycles Program Cycle No Load Data Command All Locations Done? Yes Begin Programming Command Verify all Locations @ VDD min.* VPP = VIHH2 Data Correct? No Wait 100 s Report Verify @ VDD min. Error Yes End Programming Command Verify all Locations @ VDD max. VPP = VIHH2 Data Correct? No Report Verify @ VDD max. Error Yes * VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for deviceDone operation. VDDmax = Maximum VDD for device operation. 2000 Microchip Technology Inc. DS30555B-page 3-31 PIC14000 FIGURE 2-3: PROGRAM FLOW CHART - PIC14000 CONFIGURATION WORD & ID LOCATIONS Start Load Configuration Command N=0 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1N=# of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command Report ID Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No Done DS30555B-page 3-32 Yes Data Correct? No Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD DDmax max Read Data Command Set VPP = VIHH2 2000 Microchip Technology Inc. PIC14000 2.2.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.2.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RC7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.2.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.2.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 2.3 Programming Algorithm Requires Variable VDD The PIC14000 uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDDmin = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC14000 at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC14000 with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 2000 Microchip Technology Inc. DS30555B-page 3-33 PIC14000 3.0 CONFIGURATION WORD The PIC14000 has several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. FIGURE 3-1: CONFIGURATION WORD BIT MAP Bit Number: 13 PIC14000 CPC 12 11 10 9 8 7 6 5 4 3 2 1 0 CPP1 CPP0 CPP0 CPP1 CPC CPC F CPP1 CPP0 PWRTE WDTE F FOSC CPP<1:0> 11: All Unprotected 10: N/A 01: N/A 00: All Protected bit 1,6: F Internal trim, factory programmed. DO NOT CHANGE! Program as `1'. Note 1. bit 3: PWRTE, Power Up Timer Enable Bit 0 = Power up timer enabled 1 = Power up timer disabled (unprogrammed) bit 2: WDTE, WDT Enable Bit 0 = WDT disabled 1 = WDT enabled (unprogrammed) bit 0: FOSC<1:0>, Oscillator Selection Bit 0: HS oscillator (crystal/resonator) 1: Internal RC oscillator (unprogrammed) Note 1: See Section 4.1.2 for cautions. DS30555B-page 3-34 2000 Microchip Technology Inc. PIC14000 4.0 CODE PROTECTION The memory space in the PIC14000 is divided into two areas: program space (0-0xFBF) and calibration space (0xFC0-0xFFF). For program space or user space, once code protection is enabled, all protected segments read `0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed. 4.1 Calibration Space The calibration space can contain factory-generated and programmed values. For non-JW devices, the CPC bits in the configuration word are set to `0' at the factory, and the calibration data values are write-protected; they may still be read out, but not programmed. JW devices contain the factory values, but DO NOT have the CPC bits set. Microchip does not recommend setting code protect bits in windowed devices to `0'. Once code-protected, the device cannot be reprogrammed. 4.1.1 CALIBRATION SPACE CHECKSUM The data in the calibration space has its own checksum. When properly programmed, the calibration memory will always checksum to 0x0000. When this 4.2 checksum is 0x0000, and the checksum of memory [0x0000:0xFBF] is 0x2FBF, the part is effectively blank, and the programmer should indicate such. If the CPC bits are set to `1', but the checksum of the calibration memory is 0x0000, the programmer should NOT program locations in the calibration memory space, even if requested to do so by the operator. This would be the case for a new JW device. If the CPC bits are set to `1', and the checksum of the calibration memory is NOT 0x0000, the programmer is allowed to program the calibration space as directed by the operator. The calibration space contains specially coded data values used for device parameter calibration. The programmer may wish to read these values and display them for the operator's convenience. For further information on these values and their coding, refer to AN621 (DS00621B). 4.1.2 REPROGRAMMING CALIBRATION SPACE The operator should be allowed to read and store the data in the calibration space, for future reprogramming of the device. This procedure is necessary for reprogramming a windowed device, since the calibration data will be erased along with the rest of the memory. When saving this data, Configuration Word <1,6> must also be saved, and restored when the calibration data is reloaded. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: CODE PROTECT OPTIONS * Protect calibration memory 0XXXX00XXXXXXX Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment Protected calibration memory ID Locations (0x2000 : 0x2003) * Protect program memory X0000XXX00XXXX * No code protection 1111111X11XXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Legend: X = Don't care 2000 Microchip Technology Inc. DS30555B-page 3-35 PIC14000 4.3 Checksum 4.3.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC14000 memory locations and adding up the opcodes up to the maximum user addressable location, 0xFBF. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for the PIC14000 device is shown in Table 4-2: The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. TABLE 4-2: CHECKSUM COMPUTATION The least significant 16 bits of this sum is the checksum. Code Protect OFF OFF OTP ON Checksum* SUM[0000:0FBF] + CFGW & 0x3FBD SUM[0000:0FBF] + CFGW & 0x3FBD CFGW & 0x3FBD + SUM(IDs) Blank Value 0x25E6 at 0 and max address 0x2FFD 0x0E7D 0x300A 0xFBCB 0xDA4B 0xFBD8 Legend: CFGW = Configuration Word SUM[A:B] = [Sum of locations a through b inclusive] SUM(ID) = ID locations masked by 0x7F then made into a 28-bit value with ID0 as the most significant byte *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS30555B-page 3-36 2000 Microchip Technology Inc. PIC14000 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 5-1: AC/DC CHARACTERISTICS AC/DC TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (25C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units Conditions 4.75 5.0 5.25 V - - 20 mA VDDmax V Note 1 13.25 V Note 2 General PD1 VDDP Supply voltage during programming PD2 IDDP PD3 VDDV Supply voltage during verify VDDmin PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 PD5 VIHH2 Voltage on MCLR/VPP during verify PD6 IPP PD9 VIH1 PD8 VIL1 Supply current (from VDD) during programming Programming supply current (from VPP) - VDD + 4.0 13.5 - - 50 mA (RC6, RC7) input high level 0.8 VDD - - V Schmitt Trigger input (RC6, RC7) input low level 0.2 VDD - - V Schmitt Trigger input - - 8.0 s Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VHH) for test mode entry Tf MCLR Fall time - - 8.0 s P3 Tset1 Data in setup time before clock 100 - - ns P2 P4 Thld1 Data in hold time after clock 100 - - ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 - - s P6 Tdly2 Delay between clock to clock of next command or data 1.0 - - s P7 Tdly3 Clock to date out valid (during read data) 200 - - ns P8 Thld0 Hold time after MCLR 2 - - s Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS30555B-page 3-37 PIC14000 FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 RC6 (CLOCK) RC7 (DATA) 0 1 2 1s min. 1 6 4 5 15 0 0 0 P5 P3 P4 P3 1s min. P4 } } } } 100ns min. Program/Verify Test Mode Reset FIGURE 5-2: 3 100ns min. READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 RC6 (CLOCK) RC7 (DATA) 0 0 2 1s min. 1 6 3 4 5 15 P7 0 P5 P3 P4 1s min. } } 100ns min. RC7 input RC7 = output Program/Verify Test Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 Next Command 1s min. 1 2 RC6 (CLOCK) RC7 (DATA) 1 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Test Mode Reset DS30555B-page 3-38 2000 Microchip Technology Inc. 30261C.fm Page 39 Wednesday, May 3, 2000 12:18 PM PIC16C55X In-Circuit Serial Programming for PIC16C55X OTP MCUs This document includes the programming specifications for the following devices: PROGRAMMING THE PIC16C55X The PIC16C55X can be programmed using a serial method. In serial mode the PIC16C55X can be programmed while in the users system. This allows for increased design flexibility. 1.1 Hardware Requirements The PIC16C55X requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 PIC16C55X 1.0 PDIP, SOIC, Windowed CERDIP PIC16C55X * PIC16C554 * PIC16C556 * PIC16C558 PIN Diagrams 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 SSOP RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 The programming mode for the PIC16C55X allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C55X. 2000 Microchip Technology Inc. DS30261C-page 3-39 30261C.fm Page 40 Wednesday, May 3, 2000 12:18 PM PIC16C55X 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC16C55X family. TABLE 2-1: Device IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C55X Program Memory Size Access to Program Memory PIC16C554 0x000 - 0x1FF (0.5K) PC<8:0> PIC16C556 0x000 - 0x3FF (1K) PC<9:0> PIC16C558 0x000 - 0x7FF (2K) PC<10:0> When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. In the configuration memory space, 0x2000-0x20FF are utilized. When in a configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as the PC exceeds 0x2XFF (see Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000: 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where 'bbbb' is ID information. Note: All other locations are reserved and should not be programmed. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.1. DS30261C-page 3-40 2000 Microchip Technology Inc. 30261C.fm Page 41 Wednesday, May 3, 2000 12:18 PM PIC16C55X FIGURE 2-1: PROGRAM MEMORY MAPPING 0.5KW 1KW 2KW Implemented Implemented 0 2000 ID Location 2001 ID Location 2002 ID Location 2003 ID Location 2004 Reserved 2005 Reserved 2006 Reserved 1FF 3FF 400 Implemented Implemented 7FF 800 BFF C00 FFF 1000 Reserved Reserved Reserved Reserved Reserved 2007 Configuration Word 1FFF 2000 2008 Reserved Reserved Reserved Reserved Reserved Reserved 2100 3FFF 2000 Microchip Technology Inc. DS30261C-page 3-41 30261C.fm Page 42 Wednesday, May 3, 2000 12:18 PM PIC16C55X 2.2 Program/Verify Mode setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program and configuration memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: 2.2.1 The commands in Table 2-1. The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. 2.2.1.1 are available are The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum LOAD CONFIGURATION COMMAND MAPPING Command Mapping (MSB ... LSB) Data Load Configuration 0 0 0 0 0 0 0, data(14), 0 Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: listed After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). PROGRAM/VERIFY OPERATION TABLE 2-1: that The CPU clock must be disabled during in-circuit programming. DS30261C-page3-42 2000 Microchip Technology Inc. 30261C.fm Page 43 Wednesday, May 3, 2000 12:18 PM PIC16C55X FIGURE 2-2: PROGRAM FLOW CHART - PIC16C55X PROGRAM MEMORY Start Set VDD = VDDP* N=0 No Program Cycle N > 25 Read Data Command Increment Address Command Data Correct? Yes Report Programming Failure N=N+1 N=# of Program Cycles No Yes Apply 3N Additional Program Cycles Program Cycle No Load Data Command All Locations Done? Yes Begin Programming Command Verify all Locations @ VDD min.* VPP = VIHH2 Data Correct? No Wait 100 s Report Verify @ VDD min. Error Yes End Programming Command Verify all Locations @ VDD max. VPP = VIHH2 Data Correct? No Report Verify @ VDD max. Error Yes Done * VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation. 2000 Microchip Technology Inc. DS30261C-page 3-43 30261C.fm Page 44 Wednesday, May 3, 2000 12:18 PM PIC16C55X FIGURE 2-3: PROGRAM FLOW CHART - PIC16C55X CONFIGURATION WORD & ID LOCATIONS Start Load Configuration Command N=0 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1N=# of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command ID/Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No Done DS30261C-page 3-44 Yes Data Correct? No Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD DDmax max Read Data Command Set VPP = VIHH2 2000 Microchip Technology Inc. 30261C.fm Page 45 Wednesday, May 3, 2000 12:18 PM PIC16C55X 2.2.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.2.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.2.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.2.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 2.3 Programming Algorithm Requires Variable VDD The PIC16C55X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDD max.= maximum operating VDD spec for the part. Programmers must verify the PIC16C55X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C55X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 2000 Microchip Technology Inc. DS30261C-page 3-45 30261C.fm Page 46 Wednesday, May 3, 2000 12:18 PM PIC16C55X 3.0 CONFIGURATION WORD The PIC16C55X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. FIGURE 3-1: CONFIGURATION WORD BIT MAP Bit Number: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIC16C554/556/558 CP1 CP0 CP1 CP0 CP1 CP0 -- 0 CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit 7: Reserved for future use bit 6: Set to 0 bit 5-4: CP1:CP0, Code Protect bit 8-13 Device CP1 CP0 Code Protection PIC16C554 0 0 1 0 1 0 All memory protected Do not use Do not use 1 0 0 1 1 1 0 1 0 1 Code protection off All memory protected Upper 1/2 memory protected Do not use 0 0 0 1 1 1 0 1 PIC16C556 PIC16C558 Code protection off All memory protected Upper 3/4 memory protected Upper 1/2 memory protected Code protection off bit 3: PWRTE, Power Up Timer Enable Bit PIC16C554/556/558: 0 = Power up timer enabled 1 = Power up timer disabled bit 2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0:FOSC<1:0>, Oscillator Selection Bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator DS30261C-page 3-46 2000 Microchip Technology Inc. 30261C.fm Page 47 Wednesday, May 3, 2000 12:18 PM PIC16C55X 4.0 CODE PROTECTION 4.1 The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word. 4.2 Programming Locations 0x0000 to 0x03F after Code Protection For PIC16C55X devices, once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: CONFIGURATION WORD PIC16C554 To code protect: * Protect all memory * No code protection 0000001000XXXX 1111111011XXXX Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Protected memory segment Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC16C556 To code protect: * Protect all memory 0000001000XXXX * Protect upper 1/2 memory 0101011001XXXX * No code protection 1111111011XXXX Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Protected memory segment Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC16C558 To code protect: * Protect all memory * Protect upper 3/4 memory * Protect upper 1/2 memory * No code protection 0000001000XXXX 0101011001XXXX 1010101010XXXX 1111111011XXXX Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Protected memory segment Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled 2000 Microchip Technology Inc. DS30261C-page 3-47 30261C.fm Page 48 Wednesday, May 3, 2000 12:18 PM PIC16C55X 4.3 Checksum 4.3.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC16C55X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16C74. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C55X devices is shown in Table . The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. The least significant 16 bits of this sum is the checksum. TABLE 4-2: CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C554 OFF ALL SUM[0x000:0x1FF] + CFGW & 0x3F3F SUM_ID + CFGW & 0x3F3F 3D3F 3D4E 090D 091C PIC16C556 OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F3F SUM[0x000:0x1FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 3B3F 4E5E 3B4E 070D 0013 071C PIC16C558 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F3F SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 373F 5D6E 4A5E 374E 030D 0F23 FC13 031C Device Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS30261C-page 3-48 2000 Microchip Technology Inc. 30261C.fm Page 49 Wednesday, May 3, 2000 12:18 PM PIC16C55X 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (25C is recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic PD1 VDDP PD2 IDDP Min. Typ. Max. Units Supply voltage during programming 4.75 5.0 5.25 V Supply current (from VDD) during programming - - 20 mA Conditions General PD3 VDDV Supply voltage during verify VDDmin - VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 - 13.25 V Note 2 PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 - 13.5 - PD6 IPP Programming supply current (from VPP) - - 50 mA PD9 VIH1 (RB6, RB7) input high level 0.8 VDD - - V Schmitt Trigger input PD8 VIL1 (RB6, RB7) input low level 0.2 VDD - - V Schmitt Trigger input P1 TR - - 8.0 s Serial Program Verify MCLR/VPP rise time (VSS to VHH) for test mode entry P2 Tf MCLR Fall time - - 8.0 s P3 Tset1 Data in setup time before clock 100 - - ns P4 Thld1 Data in hold time after clock 100 - - ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 - - s P6 Tdly2 Delay between clock to clock of next command or data 1.0 - - s P7 Tdly3 Clock to date out valid (during read data) 200 - - ns P8 Thld0 Hold time after MCLR 2 - - s - Tpw Programming Pulse Width 10 100 1000 s Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS30261C-page 3-49 30261C.fm Page 50 Wednesday, May 3, 2000 12:18 PM PIC16C55X FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 RB6 (CLOCK) RB7 (DATA) 0 1 2 1s min. 1 6 4 5 15 0 0 0 P5 P3 P3 1s min. P4 P4 } } } } 100ns min. Program/Verify Test Mode Reset FIGURE 5-2: 3 100ns min. READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 RB6 (CLOCK) RB7 (DATA) 0 0 2 1s min. 1 6 3 4 5 15 P7 0 P5 P4 1s min. P3 } } 100ns min. RB7 input RB7 = output Program/Verify Test Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 Next Command 1s min. 1 2 RB6 (CLOCK) RB7 (DATA) 1 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Test Mode Reset DS30261C-page 3-50 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX In-Circuit Serial Programming for PIC16C6XX/7XX/9XX OTP MCUs This document includes the programming specifications for the following devices: 1.0 * * * * * * * * * * * * * * * PIC16C72A PIC16C73 PIC16C73A PIC16C73B PIC16C74 PIC16C74A PIC16C74B PIC16C76 PIC16C77 PIC16C620 PIC16C620A PIC16C621 PIC16C621A PIC16C622 PIC16C622A * * * * * * * * * * * * * PIC16CE623 PIC16CE624 PIC16CE625 PIC16C710 PIC16C711 PIC16C712 PIC16C716 PIC16C745 PIC16C765 PIC16C773 PIC16C774 PIC16C923 PIC16C924 PROGRAMMING THE PIC16C6XX/7XX/9XX The PIC16C6XX/7XX/9XX can be programmed using a serial method. In serial mode the PIC16C6XX/7XX/ 9XX can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16C6XX/7XX/ 9XX devices in all packages. 1.1 PDIP, Windowed CERDIP MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5 RE0 RE1 RE2 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PDIP, SOIC, Windowed CERDIP MCLR/VPP *1 RA0 2 RA1 3 RA2 4 RA3 5 RA4/T0CKI 6 RA5 7 VSS 8 OSC1/CLKIN 9 OSC2/CLKOUT 10 RC0 11 RC1 12 RC2 13 RC3 14 PIC16C62/62A/63/66/72/72A PIC16C73/73A/73B/76/745 PIC16C61 PIC16C62 PIC16C62A PIC16C62B PIC16C63 PIC16C63A PIC16C64 PIC16C64A PIC16C65 PIC16C65A PIC16C65B PIC16C66 PIC16C67 PIC16C71 PIC16C72 PIC16C64/64A/65/65A/67 PIC16C74/74A/74B/77/765 * * * * * * * * * * * * * * * Pin Diagrams RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 (300 mil) 28 RB7 27 RB6 26 RB5 25 RB4 24 RB3 23 RB2 22 RB1 21 RB0/INT 20 VDD 19 VSS 18 RC7 17 RC6 16 RC5 15 RC4 Hardware Requirements The PIC16C6XX/7XX/9XX requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC16C6XX/7XX/9XX allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C6XX/7XX/9XX. 2000 Microchip Technology Inc. DS30228J-page 3-51 PIC16C6XX/7XX/9XX Pin Diagrams (Con't) 300 mil. SDIP, SOIC, Windowed CERDIP, SSOP PDIP, SOIC, Windowed CERDIP RA2 *1 RA3 2 RA4/T0CKI 3 MCLR/VPP 4 VSS 5 RB0/INT 6 RB1 7 RB2 RB3 18 RA1 17 RA0 16 OSC1/CLKIN 15 OSC2/CLKOUT 14 RB7 27 RB6 RA1/AN1 3 26 RB5 RA2/AN2/VREF-/VRL 4 25 RB4 VDD RA3/AN3/VREF+/VRH 5 24 RB3/AN9/LVDIN 13 RB7 RA4/T0CKI 6 23 RB2/AN8 12 RB6 8 11 RB5 AVDD AVSS 7 8 22 21 RB1/SS RB0/INT 9 10 RB4 OSC1/CLKIN 9 20 VDD 19 VSS 18 RC7/RX/DT PIC16C773 28 2 PIC16C61/71 PIC16C710/711 PIC16C62X *1 RA0/AN0 MCLR/VPP OSC2/CLKOUT 10 RC0/T1OSO/T1CKI 11 RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 18 pin PDIP, SOIC, Windowed CERDIP 20 pin SSOP 18 2 17 3 16 5 6 7 8 9 15 14 13 12 11 10 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1 *1 20 2 19 3 18 4 5 6 7 8 PIC16C712 PIC16C716 4 PIC16C712 PIC16C716 RA4/T0CKI MCLR/VPP VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1 *1 17 16 15 14 13 9 12 10 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RA2/AN2 RA3/AN3/VREF 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 PIC16C923 PIC16C924 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 AVDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI DS30228J-page 3-52 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC16C6XX/7XX/9XX family. TABLE 2-1: IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C6XX/7XX/9XX Device Program Memory Size PIC16C61 0x000 - 0x3FF (1K) PIC16C620/620A 0x000 - 0x1FF (0.5K) PIC16C621/621A 0x000 - 0x3FF (1K) PIC16C622/622A 0x000 - 0x7FF (2K) PIC16C62/62A/62B 0x000 - 0x7FF (2K) PIC16C63/63A 0x000 - 0xFFF (4K) PIC16C64/64A 0x000 - 0x7FF (2K) PIC16C65/65A/65B 0x000 - 0xFFF (4K) PIC16CE623 0x000 - 0x1FF (0.5K) PIC16CE624 0x000 - 0x3FF (1K) PIC16CE625 0x000 - 0x7FF (2K) PIC16C71 0x000 - 0x3FF (1K) PIC16C710 0x000 - 0x1FF (0.5K) PIC16C711 0x000 - 0x3FF (1K) PIC16C712 0x000 - 0x3FF (1K) PIC16C716 0x000 - 0x7FF (2K) PIC16C72/72A 0x000 - 0x7FF (2K) PIC16C73/73A/73B 0x000 - 0xFFF (4K) PIC16C74/74A/74B 0x000 - 0xFFF (4K) PIC16C66 0x000 - 0x1FFF (8K) PIC16C67 0x000 - 0x1FFF (8K) PIC16C76 0x000 - 0x1FFF (8K) PIC16C77 0x000 - 0x1FFF (8K) PIC16C745 0x000 - 0x1FFF (8K) PIC16C765 0x000 - 0x1FFF (8K) PIC16C773 0x000 - 0xFFF (4K) PIC16C774 0x000 - 0xFFF (4K) PIC16C923/924 0x000 - 0xFFF (4K) 2000 Microchip Technology Inc. When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000: 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1bbb bbbb" where 'bbbb' is ID information. Note: All other locations are reserved and should not be programmed. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 3.1. DS30228J-page 3-53 PIC16C6XX/7XX/9XX FIGURE 2-1: PROGRAM MEMORY MAPPING 0.5K words 2000h ID Location 0h 1FFh 2001h 2002h 2003h ID Location ID Location ID Location 2004h Reserved 2005h Reserved 2006h Reserved Implemented 1K words 2K words 4K words 8K words Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented 3FFh 400h 7FFh 800h Reserved BFFh C00h Reserved FFFh 1000h Reserved Implemented Reserved Implemented Implemented 2007h Configuration Word Implemented 1FFFh 2008h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2100h 3FFFh DS30228J-page 3-54 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 2.2 have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSb first. Therefore, during a read operation the LSb will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSb will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. Program/Verify Mode The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VSS to the appropriate VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VSS). This means that all I/O are in the reset state (High impedance inputs). All commands are transmitted LSb first. Data words are also transmitted LSb first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). Note 1: The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. The commands in Table 2-2. 2.2.1.1 2: Do not power any pin before VDD is applied. 2.2.1 are available The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSb) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to listed LOAD CONFIGURATION TABLE 2-2: COMMAND MAPPING Mapping (MSb... LSb) Data Load Configuration 0 0 0 0 0 0 0, data(14), 0 Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: are After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). PROGRAM/VERIFY OPERATION Command that The clock must be disabled during In-Circuit Serial Programming. 2000 Microchip Technology Inc. DS30228J-page 3-55 PIC16C6XX/7XX/9XX FIGURE 2-2: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX PROGRAM MEMORY Start Set VDD = VDDP* Set VPP = VIHH1 N=1 No Program Cycle N > 25? Read Data Command Increment Address Command Data correct? Yes Report programming failure N=N+1 N=# of Program Cycles No Yes Apply 3N Additional Program Cycles Program Cycle No Load Data Command All locations done? Yes Begin Programming Command Verify all locations @ VDD min.* VPP = VIHH2 Data correct? No Wait 100 s Report verify @ VDD min. Error Yes End Programming Command Verify all locations @ VDD max.* VPP = VIHH2 Data correct? No Report verify @ VDD max. Error Yes Done * VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation. DS30228J-page 3-56 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX FIGURE 2-3: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX CONFIGURATION WORD & ID LOCATIONS Start Set VDD = VDDP* Set VPP = VIHH1 Load Configuration Command N=1 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1N=# of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command Report ID Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No No Done Yes Data Correct? Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD DDmax max Read Data Command Set VPP = VIHH2 VDDP = VDD Range for programming (Typically 4.25V - 5.25V) VDDMIN = minimum VDD for device operation VDDMAX = maximum VDD for device operation 2000 Microchip Technology Inc. DS30228J-page 3-57 PIC16C6XX/7XX/9XX 2.2.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 4-1. 2.2.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 4-2. 2.2.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 4-3. 2.2.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 2.3 Programming Algorithm Requires Variable VDD The PIC16C6XX/7XX/9XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC16C6XX/7XX/9XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C6XX/7XX/9XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. DS30228J-page 3-58 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 3.0 CONFIGURATION WORD The PIC16C6XX/7XX/9XX family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 and Figure 3-2 provides an overview of configuration bits. 2000 Microchip Technology Inc. DS30228J-page 3-59 PIC16C6XX/7XX/9XX FIGURE 3-1: CONFIGURATION WORD BIT MAP Bit 13 Number: PIC16C61/71 -- PIC16C62/64/65/73/74 -- PIC16C62A/62B/63A/CR62/ 63/ 64A/CR64/65A/65B/66/67/ 72/72A/73A/73B/74A/74B/76/ 77/620/620A/621/621A/622/ 622A/ 712/716 CP1 PIC16C9XX/745/765 CP1 12 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- CP1 CP0 CP0 PWRTE PWRTE WDTE WDTE FOSC1 FOSC1 FOSC0 FOSC0 CP0 CP1 CP0 CP1 CP0 -- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 CP0 CP1 CP0 CP1 CP0 -- -- CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Reserved, '-' write as '1' for PIC16C6XX/7XX/9XX CP <1:0>, Code Protect Device PIC16C622/622A PIC16C62/62A/62B PIC16C63/63A PIC16C64/64A/712/716 PIC16C65/65A/65B PIC16C66/67/72/72A PIC16C73/73A/73B PIC16C74/74A/74B/76/77 PIC16C745/765 PIC16C9XX PIC16C61/71 PIC16C710/711 PIC16C620 PIC16C621 bit 6: bit 4: CP1 CP0 Code Protection 0 0 All memory protected 0 1 Upper 3/4 memory protected 1 0 Upper 1/2 memory protected 1 1 Code protection off -- -- 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 All memory protected Off All memory protected Do not use Do not use Code protection off All memory protected Upper 1/2 memory protected Code protection off BODEN, Brown Out Enable Bit 1 = Enabled 2 = Disable PWRTE/PWRTE, Power Up Timer Enable Bit PIC16C61/62/64/65/71/73/74: 1 = Power up timer enabled 0 = Power up timer disabled PIC16C620/620A/621/621A/622/622A/62A/63/63A/65A/65B/66/67/72/72A/73A/73B/74A/74B/76/77/710/ 711/923/924/745/765: 0 = Power up timer enabled 1 = Power up timer disabled bit 3-2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC<1:0>, Oscillator Selection Bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator bit 1-0: FOSC<1:0>, PIC16C745/765 11: E external clock with 4k PLL 10: H HS oscillator with 4k PL enabled 01: EC external clock, clkout on osc2 00: HS Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. DS30228J-page 3-60 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX FIGURE 3-2: CP1 CONFIGURATION WORD FOR PIC16C773/774 DEVICE CP0 BORV1 BORV0 CP1 bit13 12 11 10 CP0 - BODEN CP1 8 7 6 5 9 CP0 PWRTE 4 3 WDTE FOSC1 2 1 FOSC0 Register: Address CONFIG 2007h bit0 CP <1:0> Code Protection bits (2) Device PIC16C773/774 CP1 CP0 Code Protection 0 0 All memory protected 0 1 Upper 3/4 memory protected 1 0 Upper 1/2 memory protected1 1 1 Code protection off bit 11-10: BORV <1:0>: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 7: Unimplemented, Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC <1:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP <1:0> pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. DS30228J-page 3-61 PIC16C6XX/7XX/9XX FIGURE 3-3: CP0 CP0 CONFIGURATION WORD, PIC16C710/711 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 bit13 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-7 CP0: Code protection bits (2) 5-4: 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC <1:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed. DS30228J-page 3-62 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 3.1 Embedding Configuration Word and ID Information in the Hex File. To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is beneficial to the end customer. 2000 Microchip Technology Inc. DS30228J-page 3-63 PIC16C6XX/7XX/9XX 3.2 Checksum 3.2.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC16C6XX/7XX/9XX memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16C74. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C6XX/7XX/9XX devices is shown in Table 3-1. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. The least significant 16 bits of this sum is the checksum. TABLE 3-1: Device CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C61 OFF ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF 0xFC6F 0x07CD 0xFC15 PIC16C620 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C PIC16C620A OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C PIC16C621 OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16C621A OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16C622 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C622A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16CE623 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 3-64 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16CE624 OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16CE625 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C62 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x37AF 0x379F 0x378F 0x038D 0x1D69 0x1D59 0x3735 PIC16C62A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C62B OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C63 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C63A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C64 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x37AF 0x379F 0x378F 0x038D 0x1D69 0x1D59 0x3735 PIC16C64A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C65 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR 2000 Microchip Technology Inc. DS30228J-page 3-65 PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C65A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C65B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C66 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C67 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C710 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3FFF SUM[0x00:0x3F] + CFGW & 0x3FFF + SUM_ID 0x3DFF 0x3E0E 0x09CD 0xEFC3 PIC16C71 OFF ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF 0xFC6F 0x07CD 0xFC15 PIC16C711 OFF ON SUM[0x000:0x03FF] + CFGW & 0x3FFF SUM[0x00:0x3FF] + CFGW & 0x3FFF + SUM_ID 0x3BFF 0x3C0E 0x07CD 0xEDC3 PIC16C712 OFF 1/2 ALL SUM[0x000:0x07FF] + CFGW & 0x3F7F SUM[0x000:0x03FF] + CFGW & 3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x37CE 0x034D 0xF58A 0x039C PIC16C716 OFF 1/2 3/4 ALL SUM[0x000:0x07FF] + CFGW & 0x3F7F SUM[0x000:0x03FF] + CFGW & 0x3F7F + SUM_ID SUM]0x000:0x01FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C72 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C72A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C73 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 PIC16C73A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 3-66 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C73B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C74 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 PIC16C74A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C74B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C76 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C77 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C773 OFF 1/2 3/4 ALL SUM[0x000:0x0FFF] + CFGW & 0x3F7F SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x55EE 0x48DE 0x3BCE 0xFB4D 0x07A3 0xFA93 0x079C PIC16C774 OFF 1/2 3/4 ALL SU:M[0x000:0FFF] + CFGW & 0x3F7F SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0X55EE 0X48DE 0x3BCE 0xFB4D 0x07A3 0xFA93 0X079C PIC16C923 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F3F SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 0x2F3F 0x516E 0x405E 0x2F4E 0xFB0D 0x0323 0xF213 0xFB1C PIC16C924 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F3F SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 0x2F3F 0x516E 0x405E 0x2F4E 0xFB0D 0x0323 0xF213 0xFB1C PIC16C745 OFF 1000:1FFF 800:1FFF ALL 1F3F 396E 2C5E 1F4E EB0D EB23 DE13 EB1C SUM(0000:1FFF) + CFGW & 0x3F3F SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID CFGW * 0x3F3F + SUM_ID Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR 2000 Microchip Technology Inc. DS30228J-page 3-67 PIC16C6XX/7XX/9XX TABLE 3-1: Device PIC16c765 CHECKSUM COMPUTATION (CONTINUED) Code Protect OFF 1000:1FFF 800:1FFF ALL Checksum* Blank Value 0x25E6 at 0 and max address SUM(0000:1FFF) + CFGW & 0x3F3F SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID CFGW * 0x3F3F + SUM_ID 1F3F 396E 2C5E 1F4E EB0D EB23 DE13 EB1C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 3-68 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 4.0 PROGRAM/VERIFY MODE TABLE 4-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units 4.75 5.0 5.25 V - - 20 mA Conditions General PD1 VDDP Supply voltage during programming PD2 IDDP Supply current (from VDD) during programming PD3 VDDV Supply voltage during verify VDDmin - VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 - 13.25 V Note 2 PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.5 - 13.25 - - - 50 mA PD6 IPP Programming supply current (from VPP) PD9 VIH (RB6, RB7) input high level 0.8 VDD - - V Schmitt Trigger input PD8 VIL (RB6, RB7) input low level 0.2 VDD - - V Schmitt Trigger input - - 8.0 s Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VHH) for test mode entry Tf MCLR Fall time - - 8.0 s P3 Tset1 Data in setup time before clock 100 - - ns P4 Thld1 Data in hold time after clock 100 - - ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 - - s P6 Tdly2 Delay between clock to clock of next command or data 1.0 - - s P7 Tdly3 Clock to date out valid (during read data) 200 - - ns P8 Thld0 Hold time after MCLR 2 - - s P2 Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS30228J-page 3-69 PIC16C6XX/7XX/9XX FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 RB6 (CLOCK) RB7 (DATA) 0 1 2 1s min. 1 6 4 5 15 0 0 0 P5 P3 P4 1s min. P3 P4 } } } } 100ns min. Program/Verify Test Mode Reset FIGURE 4-2: 3 100ns min. READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 RB6 (CLOCK) RB7 (DATA) 0 0 2 1s min. 1 6 3 4 5 15 P7 0 P5 P3 P4 1s min. } } 100ns min. RB7 input RB7 = output Program/Verify Test Mode Reset FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 Next Command 1s min. 1 2 RB6 (CLOCK) RB7 (DATA) 1 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Test Mode Reset DS30228J-page 3-70 2000 Microchip Technology Inc. PIC17C7XX In-Circuit Serial Programming for PIC17C7XX OTP MCUs This document includes the programming specifications for the following devices: * * * * * PIC17C752 PIC17C756 PIC17C756A PIC17C762 PIC17C766 1.0 PROGRAMMING THE PIC17C7XX The PIC17C7XX is programmed using the TABLWT instruction. The table pointer points to the internal EPROM location start. Therefore, a user can program an EPROM location while executing code (even from internal EPROM). This programming specification applies to PIC17C7XX devices in all packages. For the convenience of a programmer developer, a "program & verify" routine is provided in the on-chip test program memory space. The program resides in ROM and not EPROM, therefore, it is not erasable. The "program/verify" routine allows the user to load any address, program a location, verify a location or increment to the next location. It allows variable programming pulse width. The PIC17C7XX group of the High End Family has added a feature that allows the serial programming of the device. This is very useful in applications where it is desirable to program the device after it has been manufactured into the users system (In-circuit Serial Programming (ISP)). This allows the product to be shipped with the most current version of the firmware, since the microcontroller can be programmed just before final test as opposed to before board manufacture. Devices may be serialized to make the product unique, "special" variants of the product may be offered, and code updates are possible. This allows for increased design flexibility. 2000 Microchip Technology Inc. 1.1 Hardware Requirements Since the PIC17C7XX under programming is actually executing code from "boot ROM," a clock must be provided to the part. Furthermore, the PIC17C7XX under programming may have any oscillator configuration (EC, XT, LF or RC). Therefore, the external clock driver must be able to overdrive pulldown in RC mode. CMOS drivers are required since the OSC1 input has a Schmitt trigger input with levels (typically) of 0.2 VDD and 0.8 VDD. See the PIC17C7XX data sheet (DS30289) for exact specifications. The PIC17C7XX requires two programmable power supplies, one for VDD (3.0V to 5.5V recommended) and one for VPP (13 0.25V). Both supplies should have a minimum resolution of 0.25V. The PIC17C7XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin." Three times (3X) additional pulses will increase program margin beyond VDDmax and insure safe operation in user system. The actual programming must be done with VDD in the VDDP range (Parameter PD1). VDDP = VDD range required during programming. VDDmin. = minimum operating VDD spec. for the part. VDDmax. = maximum operating VCC spec for the part. Programmers must verify the PIC17C7XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC17C7XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Blank checks should be performed at VDDMIN. Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. DS30274B-page 3-71 PIC17C7XX PIC17C752/756/756A/762/766 LCC RH1 RH0 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 RC0/AD0 VDD NC VSS RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 RJ7 RJ6 FIGURE 1-1: PIC17C762/766 Top View RJ5 RJ4 RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 VSS NC OSC2/CLKOUT OSC1/CLKIN VDD RB7/SDO RB6/SCK RA3/SDI/SDA RA2/SS/SCL RA1/T0CKI RJ3 RJ2 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 RC0/AD0 VDD NC VSS RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 1110 9 8 7 6 5 4 3 2 1 84 83828180 7978777675 12 74 13 73 14 72 15 71 16 70 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 31 55 32 54 3334353637383940414243444546 474849 50 51 52 53 RH6/AN14 RH7/AN15 RF1/AN5 RF0/AN4 AVDD AVSS RG3/AN0/VREF+ RG2/AN1/VREFRG1/AN2 RG0/AN3 NC VSS VDD RG4/CAP3 RG5/PWM3 RG7/TX2/CK2 RG6/RX2/DT2 RA5/TX1/CK1 RA4/RX1/DT1 RJ0 RJ1 RH2 RH3 RD1/AD9 RD0/AD8 RE0/ALE RE1/OE RE2/WR RE3/CAP4 MCLR/VPP TEST NC VSS VDD RF7/AN11 RF6/AN10 RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 RH4/AN12 RH5/AN13 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 RD1/AD9 RD0/AD8 RE0/ALE RE1/OE RE2/WR RE3/CAP4 MCLR/VPP TEST NC VSS VDD RF7/AN11 RF6/AN10 RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 PIC17C752/756/756A Top View 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 VSS NC OSC2/CLKOUT OSC1/CLKIN VDD RB7/SDO RB6/SCK RA3/SDI/SDA RA2/SS/SCL RA1/T0CKI RF1/AN5 RF0/AN4 AVDD AVSS RG3/AN0/VREF+ RG2/AN1/VREFRG1/AN2 RG0/AN3 NC VSS VDD RG4/CAP3 RG5/PWM3 RG7/TX2/CK2 RG6/RX2/DT2 RA5/TX1/CK1 RA4/RX1/DT1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING IN PARALLEL MODE): PIC17C7XX During Programming Pin Name Pin Name Pin Type RA4:RA0 TEST PORTB<7:0> PORTC<7:0> MCLR/VPP VDD VSS RA4:RA0 TEST DAD15:DAD8 DAD7:DAD0 VPP VDD VSS I I I/O I/O P P P Pin Description Necessary in programming mode Must be set to "high" to enter programming mode Address & data: high byte Address & data: low byte Programming Power Power Supply Ground Legend: I = Input, O = Output, P = Power DS30274B-page 3-72 2000 Microchip Technology Inc. PIC17C7XX 2.0 PARALLEL MODE PROGRAM ENTRY 2.1 To execute the programming routine, the user must hold TEST pin high, RA2, RA3 must be low and RA4 must be high (after power-up) while keeping MCLR low and then raise MCLR pin from VIL to VDD or VPP. This will force FFE0h in the program counter and execution will begin at that location (the beginning of the boot code) following reset. Note: The Oscillator must not have 72 OSC clocks while the device MCLR is between VIL and VIHH. Program/Verify Mode The program/verify mode is intended for full-feature programmers. This mode offers the following capabilities: a) b) c) d) e) All unused pins during programming are in hi-impedance state. Load any arbitrary 16-bit address to start program and/or verify at that location. Increment address to program/verify the next location. Allows arbitrary length programming pulse width. Following a "verify" allows option to program the same location or increment and verify the next location. Following a "program" allows options to program the same location again, verify the same location or to increment and verify the next location. PORTB (RB pins) has internal weak pull-ups which are active during the programming mode. When the TEST pin is high, the Power-up timer (PWRT) and Oscillator Start-up Timers (OST) are disabled. FIGURE 2-1: PROGRAMMING/VERIFY STATE DIAGRAM Pulse RA1 Increment Address Reset Jump to Program Routine Pulse RA1 Load Address Pulse RA1 Pulse RA1 (Raise RA1 after RA0) Reset RA0 Raise RA1 before RA0 2000 Microchip Technology Inc. Program Pulse RA0 (RA0 pulse width is programming time) DS30274B-page 3-73 PIC17C7XX 2.1.1 LOADING NEW ADDRESS 2.1.3 The program allows new address to be loaded right out of reset. A 16-bit address is presented on ports B (high byte) and C (low byte) and the RA1 is pulsed (0 1, then 1 0). The address is latched on the rising edge of RA1. See timing diagrams for details. After loading an address, the program automatically goes into a "verify cycle." To load a new address at any time, the PIC17C7XX must be reset and the programming mode re-entered. 2.1.2 VERIFY (OR READ) MODE "Verify mode" can be entered from "Load address" mode, "program mode" or "verify mode." In verify mode pulsing RA1 will turn on PORTB and PORTC output drivers and output the 16-bit value from the current location. Pulsing RA1 again will increment location count and be ready for the next verify cycle. Pulsing RA0 will begin a program cycle. FIGURE 2-2: PROGRAM CYCLE "Program cycle" is entered from "verify cycle" or program cycle" itself. After a verify, pulsing RA0 will begin a program cycle. 16-bit data must be presented on PORTB (high byte) and PORTC (low byte) before RA0 is raised. The data is sampled 3 TCY cycles after the rising edge of RA0. Programming continues for the duration of RA0 pulse. At the end of programming, the user can choose one of three different routes. If RA1 is kept low and RA0 is pulsed again, the same location will be programmed again. This is useful for applying over programming pulses. If RA1 is raised before RA0 falling edge, then a verify cycle is started without address increment. Raising RA1 after RA0 goes low will increment address and begin verify cycle on the next address. PIC17C7XX PROGRAM MEMORY MAP FE00h FOSC0 FE01h FOSC1 FE02h WDTPS0 FE03h WDTPS1 FE04h PM0 FE05h Reserved FE06h PM1 FE07h Reserved FE08h Reserved FE09h Reserved FE0Eh BODEN FE0Fh PM2 PIC17C752 PIC17C756/756A PIC17C762 PIC17C766 On-chip Program EPROM On-chip Program EPROM On-chip Program EPROM On-chip Program EPROM Configuration Word Configuration Word Configuration Word 0000h 1FFFh 3FFFh FE00h Configuration Word FE0Fh FFFFh DS30274B-page 3-74 2000 Microchip Technology Inc. PIC17C7XX 3.0 PARALLEL MODE PROGRAMMING SPECIFICATIONS FIGURE 3-1: PROGRAMMING ROUTINE FLOWCHART RESET NO RA1 = 0 RA2 = 0 RA3 = 0 RA4 = 1 YES NO RA1 = 1 MCLR = 1 Bport = 0xE1 (hold for 10 TCY) YES NO Present address on ports RB, RC hold TCY after RA1 changes to 1 NO RA1 = 0 RA1 = 1 YES B and C ports not driven by part Program 16-bit data YES NO RA1 = 0 Read MSB of data from portB. Read LSB of data from portC Enable RA0 to end program cycle NO If programming is desired force portB = MSB of data force portC = LSB of data (hold 10 Tcy after RA0 is raised) RA0 = 0 YES YES YES Stop driving address on ports YES YES RA1 = 0 RA1 = 0 NO RA0 = 1 NO NO RA0 = 1 NO NO NO RA1 = 1 YES RA1 = 1 YES Increment Address NO RA1 = 1 YES Bport = xxx - B port is forced by the part B port = MSB of Data C port = LSB of Data Bport = xxx - B port tristate, should be forced by user Min RA + high or low = 10 TCY 2000 Microchip Technology Inc. DS30274B-page 3-75 PIC17C7XX FIGURE 3-2: RECOMMENDED PROGRAMMING ALGORITHM FOR USER EPROM Start Load new address Pulse-count = 0 Set VDD = VDDMIN Verify blank Pulse Blank Check? NO Issue "Blank check fail" error message YES Load new data Set VDD = VDDMIN Program error message Issue error message "Fail verify @ VDDMIN/MAX" Set VDD to VDDP Program using 100 s pulse increment pulse-count YES NO Pass? Set VDD = VDDMIN verify location(s) Set VDD = VDDMIN verify location Verify location for correct date YES Pass? Apply (3x Pulse-count) more 100 s programming pulses for margin (Over programming) NO NO PulseCount >25 YES Location fails programming issue error message "Unable to programming location" DS30274B-page 3-76 2000 Microchip Technology Inc. PIC17C7XX FIGURE 3-3: RECOMMENDED PROGRAMMING ALGORITHM FOR CONFIGURATION WORDS Start Load new address Pulse-count = 0 Set VDD = VDDmin Verify blank Pass Blank check? NO Issue "blank check fail" error message YES Load new data Programming error: Issue error message "Fail verify @ VDDmin/max" Set VDD = VDDMIN Set VDD = VDDP YES Program using 100 s pulse increment pulse-count YES Pass? NO Set VDD = VDDmax Verify location(s) Pulse count <100 NO Verify location for correct data SetVVDD==VVDDmin min Set DD DD Verify location YES Pass? NO Location fails programming, issue error message "Unable to program location" 2000 Microchip Technology Inc. DS30274B-page 3-77 PIC17C7XX 4.0 4.1 SERIAL MODE PROGRAM ENTRY 4.2 Hardware Requirements Certain design criteria must be taken into account for ISP. Seven pins are required for the interface. These are shown in Table 4-1. Serial Program Mode Entry To place the device into the serial programming test mode, two pins will need to be placed at VIHH. These are the TEST pin and the MCLR/VPP pins. Also, the following sequence of events must occur: 1. 2. The TEST pin is placed at VIHH. The MCLR/VPP pin is placed at VIHH. There is a setup time between step 1 and step 2 that must be meet (See "Electrical Specifications for Serial Programming Mode" on page 93.) After this sequence the Program Counter is pointing to Program Memory Address 0xFF60. This location is in the Boot ROM. The code initializes the USART/SCI so that it can receive commands. For this the device must be clocked. The device clock source in this mode is the RA1/T0CKI pin. Once the USART/SCI has been initialized, commands may be received. The flow is show in these 3 steps: 1. 2. 3. TABLE 4-1: The device clock source starts. Wait 80 device clocks for Boot ROM code to configure the USART/SCI. Commands may be sent now. ISP Interface Pins During Programming Name Function Type RA4/RX/DT DT I/O Serial Data RA5/TX/CK CK I Serial Clock RA1/T0CKI OSCI I Device Clock Source TEST TEST I Test mode selection control input. Force to VIHH, MCLR/VPP MCLR/VPP P Programming Power VDD VDD P Power Supply VSS VSS P Ground DS30274B-page 3-78 Description 2000 Microchip Technology Inc. PIC17C7XX 4.3 4.3.1 Software Commands This is used to clear the address pointer to the Program Memory. This ensures that the pointer is at a known state as well as pointing to the first location in program memory. This feature is similar to that of the PIC16CXXX midrange family, but the programming commands have been implemented in the device Boot ROM. The Boot ROM is located in the program memory from 0xFF60 to 0xFFFF. The ISP mode is entered when the TEST pin has a VIHH voltage applied. Once in ISP mode, the USART/SCI module is configured as a synchronous slave receiver, and the device waits for a command to be received. The ISP firmware recognizes eight commands. These are shown in Table 4-2. TABLE 4-2: RESET PROGRAM MEMORY POINTER 4.3.2 INCREMENT ADDRESS This is used to increment the address pointer to the Program Memory. This is used after the current location has been programmed (or read). ISP COMMANDS Command Value RESET PROGRAM MEMORY POINTER 0000 0000 LOAD DATA 0000 0010 READ DATA 0000 0100 INCREMENT ADDRSS 0000 0110 BEGIN PROGRAMMING 0000 1000 LOAD ADDRESS 0000 1010 READ ADDRESS 0000 1100 END PROGRAMMING 0000 1110 FIGURE 4-1: RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP (NEXT COMMAND) PS3 PS1 1 2 3 4 5 6 7 8 1 2 RA5 (Clock) PS6 PS4PS5 0 RA4 (Data) 0 0 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 4-2: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 3 4 (NEXT COMMAND) 5 6 7 8 1 2 RA5 (Clock) PS6 PS4PS5 RA4 (Data) 0 1 1 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode 2000 Microchip Technology Inc. DS30274B-page 3-79 PIC17C7XX 4.3.3 LOAD ADDRESS 4.3.4 This is used to load the address pointer to the Program Memory with a specific 16-bit value. This is useful when a specific range of locations are to be accessed. FIGURE 4-3: READ ADDRESS This is used so that the current address in the Program Memory pointer can be determined. This can be used to increase the robustness of the ISP programming (ensure that the Program Memory pointers are still in sync). LOAD ADDRESS COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 (NEXT COMMAND) 2 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS7 PS6 PS4PS5 0 RA4 (Data) 1 0 1 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 4-4: READ ADDRESS COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS8 PS6 PS4PS5 PS9 RA4 (Data) 0 0 1 1 0 0 0 0 RA4 = Input RA4 = Output Reset Program/Verify Test Mode DS30274B-page 3-80 2000 Microchip Technology Inc. PIC17C7XX 4.3.5 LOAD DATA 4.3.6 This is used to load the 16-bit data that is to be programmed into the Program Memory location. The Program Memory address may be modified after the data is loaded. This data will not be programmed until a BEGIN PROGRAMMING command is executed. FIGURE 4-5: READ DATA This is used to read the data in Program Memory that is pointed to by the current address pointer. This is useful for doing a verify of the programming cycle and can be used to determine the number for programming cycles that are required for the 3X overprogramming. LOAD DATA COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP (NEXT COMMAND) PS3 PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS7 SP6 PS4PS5 0 RA4 (Data) 1 0 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 4-6: READ DATA COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS8 PS6 PS4PS5 PS9 RA4 (Data) 0 0 1 0 0 0 0 0 RA4 = Input RA4 = Output Reset Program/Verify Test Mode 2000 Microchip Technology Inc. DS30274B-page 3-81 PIC17C7XX 4.3.7 BEGIN PROGRAMMING 4.3.8 This is used to program the current 16-bit data (last data sent with LOAD DATA Command) into the Program Memory at the address specified by the current address pointer. The programming cycle time is specified by specification P10. After this time has elapsed, any command must be sent, which wakes the processor from the Long Write cycle. This command will be the next executed command. FIGURE 4-7: 3X OVERPROGRAMMING Once a location has been both programmed and verified over a range of voltages, 3X overprogramming should be applied. In other words, apply three times the number of programming pulses that were required to program a location in memory, to ensure a solid programming margin. This means that every location will be programmed a minimum of 4 times (1 + 3X overprogramming). BEGIN PROGRAMMING COMMAND (PROGRAM) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 3 4 (NEXT COMMAND) 5 6 7 8 1 2 7 8 RA5 (Clock) PS10 PS4PS5 RA4 (Data) 0 0 0 1 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode DS30274B-page 3-82 2000 Microchip Technology Inc. PIC17C7XX FIGURE 4-8: RECOMMENDED PROGRAMMING FLOWCHART TEST = MCLR = RA4 = RA5 = Vss START 4.75V < VDD < 5.25V TEST = Vihh MCLR = Vihh Start Device Clock (on RA0), Wait 80 Device Clocks ISP Command RESET ADDRESS ISP Command INCREMENT ADDRESS or LOAD ADDRESS N=1 ISP Command LOAD DATA Yes No ISP Command BEGIN PROGRAMMING N > 25? Report Programming Failure Wait approx 100 ms ISP Command READ DATA No Data Correct? N=N+1 Yes N = 3N ISP Command BEGIN PROGRAMMING Verify all Locations @ Vddmin Wait approx 100 ms No Data Correct? N=N-1 Yes No Yes Programmed all required locations? @ Vddmin Verify all Locations @ Vddmax N = 0? No Report Verify Error Yes Yes No Data Correct? Report Verify Error @ Vddmax DONE 2000 Microchip Technology Inc. DS30274B-page 3-83 PIC17C7XX 5.0 CONFIGURATION WORD 5.1 Configuration bits are mapped into program memory. Each bit is assigned one memory location. In erased condition, a bit will read as `1'. To program a bit, the user needs to write to the memory address. The data is immaterial; the very act of writing will program the bit. The configuration word locations are shown in Table 5-3. The programmer should not program the reserved locations to avoid unpredictable results and to be compatible with future variations of the PIC17C7XX. It is also mandatory that configuration locations are programmed in the strict order starting from the first location (0xFE00) and ending with the last (0xFE0F). Unpredictable results may occur if the sequence is violated. TABLE 5-2: Reading Configuration Word The PIC17C7XX has seven configuration locations (Table 5-1). These locations can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. Reading any configuration location between 0xFE00 and 0xFE07 will place the low byte of the configuration word (Table 5-2) into DAD<7:0> (PORTC). DAD<15:8> (PORTD) will be set to 0xFF. Reading a configuration location between 0xFE08 and 0xFE0F will place the high byte of the configuration word into DAD<7:0> (PORTC). DAD<15:8> (PORTD) will be set to 0xFF. TABLE 5-1: CONFIGURATION BIT PROGRAMMING LOCATIONS Bit Address FOSC0 0xFE00 FOSC1 0xFE01 WDTPS0 0xFE02 WDTPS1 0xFE03 PM0 0xFE04 PM1 0xFE06 BODEN 0xFE0E PM2 0xFE0F READ MAPPING OF CONFIGURATION BITS 15 14 13 12 11 10 9 8 7 6 5 1 1 1 1 1 1 1 1 -- PM1 -- 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 PM2 6 BODEN 4 3 2 1 0 PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 5 4 PM2 PM2 3 PM2 2 PM2 1 PM2 0 PM2 --=Unused PM<2:0>, Processor Mode Select bits 111 = Microprocessor mode 110 = Microcontroller mode 101 = Extended Microcontroller mode 000 = Code protected microcontroller mode BODEN, Brown-out Detect Enable 1 = Brown-out Detect Circuitry enabled 0 = Brown-out Detect Circuitry disabled WDTPS1:WDTPS0, WDT Prescaler Select bits. 11 = WDT enabled, postscaler = 1 10 = WDT enabled, postscaler = 256 01 = WDT enabled, postscaler = 64 00 = WDT disabled, 16-bit overflow timer FOSC1:FOSC0, Oscillator Select bits 11 = EC oscillator 10 = XT oscillator 01 = RC oscillator 00 = LF oscillator DS30274B-page 3-84 2000 Microchip Technology Inc. PIC17C7XX 5.2 Embedding Configuration Word Information in the Hex File To allow portability of code, a PIC17C7XX programmer is required to read the configuration word locations from the hex file when loading the hex file. If the configuration word information was not present in the hex file, then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the hex file, it should be to address FE00h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.3 Reading From and Writing To a Code Protected Device When a device is code-protected, writing to program memory is disabled. If program memory is read, the value returned is the XNOR8 result of the actual program memory word. The XNOR8 result is the upper eight bits of the program memory word XNOR'd with the lower eight bits of the same word. This 8-bit result is then duplicated into both the upper and lower 8-bits of the read value. The configuration word can always be read and written. 2000 Microchip Technology Inc. DS30274B-page 3-85 PIC17C7XX 5.4 CHECKSUM COMPUTATION ulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) Note: The least significant 16 bits of this sum is the checksum. Table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently, depending on the code protect setting, the table describes how to manipulate the actual program memory values to sim- TABLE 5-3: Some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0xC0DE at 0 and max address PIC17C752 MP mode MC mode EMC mode PMC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA05F 0xA04F 0xA01F 0x200F 0x221D 0x220D 0x21DD 0xE3D3 PIC17C756 MP mode MC mode EMC mode PMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x804F 0x801F 0x000F 0x021D 0x020D 0x01DD 0xC3D3 PIC17C756A MP mode MC mode EMC mode PMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x804F 0x801F 0x000F 0x021D 0x020D 0x01DD 0xC3D3 PIC17C762 MP mode MC mode EMC mode PMC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA05F 0xA04F 0xA01F 0x200F 0x221D 0x220D 0x21DD 0xE3D3 PIC17C766 MP mode MC mode EMC mode PMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x804F 0x801F 0x000F 0x021D 0x020D 0x01DD 0xC3D3 Device Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_XNOR8(a:b) = [Sum of 8-bit wide XNOR copied into upper and lower byte, of locations a to b inclusive] *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS30274B-page 3-86 2000 Microchip Technology Inc. PIC17C7XX 5.5 Device ID Register Program memory location FDFFh is preprogrammed during the fabrication process with information on the device and revision information. These bits are accessed by a TABLR0 instruction, and are access when the TEST pin is high. As as a result, the device ID bits can be read when the part is code protected. TABLE 5-4: DEVICE ID REGISTER DECODE Resultant Device Device ID Value Device DEV REV PIC17C766 0000 0001 001 X XXXX PIC17C762 0000 0001 101 X XXXX PIC17C756 0000 0000 001 X XXXX PIC17C756A 0000 0010 001 X XXXX PIC17C752 0000 0010 101 X XXXX 2000 Microchip Technology Inc. DS30274B-page 3-87 PIC17C7XX 6.0 PARALLEL MODE AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: Operating Voltage: +10C TA +70C, unless otherwise stated, (25C is recommended) 4.5V VDD 5.25V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units PD1 VDDP 4.75 5.0 5.25 V PD2 IDDP -- -- 50 mA Freq = 10MHz, VDD = 5.5V PD3 VDDV Supply voltage during programming Supply current during programming Supply voltage during verify VDD min. 12.75 -- VDD max. 13.25 V Note 2 PD4 PD6 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 Note 1: 2: Conditions/Comments Voltage on VPP/MCLR pin -- V Note 1 during programming -- 25 50 mA Programming current on IPP VPP/MCLR pin Osc/clockin frequency dur4 -- 10 MHz FOSCP ing programming TCY Instruction cycle 1 -- 0.4 s TCY = 4/FOSCP TIRV2TSH RA0, RA1, RA2, RA3, RA4 1 -- -- s setup before TEST TEST to MCLR 1 -- -- s TTSH2MCH TBCV2IRH RC7:RC0, RB7:RB0 valid to 0 -- -- s RA1 or RA0:Address/Data input setup time TIRH2BCL RA1 or RA0 to RB7:RB0, 10 TCY -- -- s RC7:RC0 invalid; Address data hold time; -- -- 8TCY T0CKIL2RBCZ RT to RB7:RB0, RC7:RC0 hi-impedance T0CKIH2BCV RA1 to data out valid -- -- 10 TCY TPROG Programming pulse width 100 1000 s TIRH2IRL RA0, RA1 high pulse width 10 TCY -- -- s TIRL2IRH RA0, RA1 low pulse width 10 TCY -- -- s T0CKIV2INL RA1 before INT (to go 0 -- -- s from prog cycle to verify w/o increment) RA1 valid after RA0 (to 10 TCY -- -- s TINL2RTL select increment or no increment going from program to verify cycle VPP setup time before RA0 100 -- -- s Note 1 TVPPS TVPPH VPP hold time after INT 0 -- -- s Note 1 TVDV2TSH VDD stable to TEST 10 -- -- ms TRBV2MCH RB input (E1h) valid to VPP/ 0 -- -- s MCLR TMCH2RBI RB input (E1h) hold after 10TCY -- -- ns VPP/MCLR TVPL2VDL VDD power down after VPP 10 -- -- ms power down VPP/MCLR pin must only be equal to or greater than VDD at times other than programming. Program must be verified at the minimum and maximum VDD limits for the part. VPP DS30274B-page 3-88 2000 Microchip Technology Inc. 2000 Microchip Technology Inc. RC<7:0> RB<7:0> RA0 RA1 P5 E1H P18 P4 Note: Mode Entry Load Address X ADDR_LO ADDR_HI RA2 = 0 RA3 = 0 RA4 = 1 Jump Address Input Programming 5V 13V P9 P7 Verify location X DATA_LO OUT DATA_HI OUT P11 INC ADDR Increment Address to X + 1 by pulsing RA1 P10 Verify location X + 1 DATA_LO OUT DATA_HI OUT P9 P6 by raising RA1 before RA0 Program location X + ! Do not increment PC P5 DATA_LO OUT DDATA_HI OUT P14 P15 Verify location X + 1 DATA_LO OUT DATA_HI OUT FIGURE 6-1: MCLR Test PIC17C7XX PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS I DS30274B-page 3-89 DS30274B-page 3-90 Note: RC<7:0> RB<7:0> RA0 RA1 E1H Jump Address Input RA2 = 0 RA3 = 0 RA4 = 1 Programming mode entry 5V 13V Load address X ADDR_LO ADDR_HI Verify location X DATA_LO OUT DATA_HI OUT P14 DATA_LO_IN DATA_HI_IN P9 Program location X DATA_LO_IN DATA_HI_IN P9 Program location X Move to verify cycle Prevent increment of PC by raising RA1 before RA0 DATA_LO_IN DATA_HI_IN P9 P15 Verify location X DATA_LO OUT DATA_HI OUT FIGURE 6-2: VPP/MCLR Test PIC17C7XX PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS II 2000 Microchip Technology Inc. 2000 Microchip Technology Inc. RC<7:0> RB<7:0> DATA_LO OUT DATA_HIOUT Device in PGM mode Test = +6 VPP/MCLR = VPP RA2 = 0 RA3 = 0 RA4 = 1 Verify location X Note: INC PC Program location X Do not increment PC Raise RA1 before RA0 to do this DATA_LO IN DATA_HI IN P12 Verify location X DATA_LO OUT DATA_HI OUT Program location X Raise RA1 after RA0 to increment location X + 1 DATA_LO IN DATA_HI IN INC PC P13 Verify location X + 1 Pulse RA1 to increment address to X + 2 DATA_LO OUT DATA_HI OUT INC PC Verify location X + 2 DATA_LO IN DATA_HI IN FIGURE 6-3: RA0 RA1 P13 PIC17C7XX PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS III DS30274B-page 3-91 PIC17C7XX FIGURE 6-4: POWER-UP/DOWN SEQUENCE FOR PROGRAMMING VDD P19 P16 VPP/MCLR Test RA4 RA2 RA3 RA0 P3 RB<7:0> P17 E1H DS30274B-page 3-92 P18 2000 Microchip Technology Inc. PIC17C7XX 7.0 ELECTRICAL SPECIFICATIONS FOR SERIAL PROGRAMMING MODE All parameters apply across the specified operating ranges unless otherwise noted. Parameter No. PS1 Vcc = 2.5V to 5.5V Commercial (C): Tamb = Industrial (I): Tamb = 0 to +70C -40C to +85C Sym Characteristic Min Typ Max Units VIHH Programming Voltage on VPP/ MCLR pin and TEST pin. 12.75 -- 13.75 V IPP Programming current on MCLR pin -- 25 50 mA FOSC Input OSC frequency on RA1 -- -- 8 MHz TCY Instruction Cycle Time -- 4/FOSC -- TVH2VH Setup time between TEST = VIHH and MCLR = VIHH 1 -- -- s PS2 TSER Serial setup time 20 -- -- TCY PS3 TSCLK Serial Clock period 1 -- -- TCY PS4 TSET1 Input Data Setup Time to serial clock 15 -- -- ns PS5 THLD1 Input Data Hold Time from serial clock 15 -- -- ns PS6 TDLY1 Delay between last clock to first clock of next command 20 -- -- TCY PS7 TDLY2 Delay between last clock of command byte to first clock of read of data word 20 -- -- TCY PS8 TDLY3 Delay between last clock of command byte to first clock of write of data word 30 -- -- TCY PS9 TDLY4 Data input not driven to next clock input 1 -- -- TCY PS10 TDLY5 Delay between last begin programming clock to last clock of next command (minimum programming time) 100 -- -- s * Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. DS30274B-page 3-93 PIC17C7XX FIGURE 7-1: RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP (NEXT COMMAND) PS3 PS1 1 2 3 4 5 6 7 8 1 2 RA5 (Clock) PS6 PS4PS5 0 RA4 (Data) 0 0 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 7-2: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 3 4 (NEXT COMMAND) 5 6 7 8 1 2 RA5 (Clock) PS6 PS4PS5 RA4 (Data) 0 1 1 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode DS30274B-page 3-94 2000 Microchip Technology Inc. PIC17C7XX FIGURE 7-3: LOAD ADDRESS COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 (NEXT COMMAND) 2 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS7 PS6 PS4PS5 0 RA4 (Data) 1 0 1 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 7-4: READ ADDRESS COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS8 PS6 PS4PS5 PS9 RA4 (Data) 0 0 1 1 0 0 0 0 RA4 = Input RA4 = Output Reset Program/Verify Test Mode 2000 Microchip Technology Inc. DS30274B-page 3-95 PIC17C7XX FIGURE 7-5: LOAD DATA COMMAND RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP (NEXT COMMAND) PS3 PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS7 PS6 PS4PS5 0 RA4 (Data) 1 0 0 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode FIGURE 7-6: READ DATA COMMAND RA1T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1 RA5 (Clock) PS8 PS6 PS4PS5 PS9 0 RA4 (Data) 0 1 0 0 0 0 0 RA4 = Input RA4 = Output Reset Program/Verify Test Mode FIGURE 7-7: BEGIN PROGRAMMING COMMAND (PROGRAM) RA1/T0CKI VIHH Test PS2 VIHH MCLR/VPP PS3 PS1 1 2 3 4 (NEXT COMMAND) 5 6 7 8 1 2 7 8 RA5 (Clock) PS10 PS4PS RA4 (Data) 0 0 0 1 0 0 0 0 RA4 = Input Reset Program/Verify Test Mode DS30274B-page 3-96 2000 Microchip Technology Inc. PIC18CXXX In-Circuit Serial Programming for PIC18CXXX OTP MCUs This document includes the programming specifications for the following devices: * PIC18C452 * PIC18C252 1.0 Pin Diagram PDIP, Windowed CERDIP * PIC18C242 * PIC18C442 PROGRAMMING THE PIC18CXXX The PIC18CXXX can be programmed using a serial method. while in the users system. This allows for increased design flexibility. This programming specification applies to PIC18CXXX devices in all package types. 1.1 Hardware Requirements (300 mil) *1 28 RB7 2 27 RB6 RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 RA4/T0CKI 6 23 RB2 RA5 7 22 RB1 VSS 8 21 RB0/INT OSC1/CLKIN 9 20 VDD 19 VSS PIC18C2XX The programming mode for the PIC18CXXX allows programming of user program memory, special locations used for ID, and the configuration word for the PIC18CXXX. RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 RA0 MCLR/VPP Programming Mode TABLE 1-1: 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PDIP, SOIC, Windowed CERDIP The PIC18CXXX requires two programmable power supplies, one for VDD (2.0V to 5.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18C4XX MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5 RE0 RE1 RE2 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RD0 RD1 OSC2/CLKOUT 10 RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18C242/252/442/452 During Programming Pin Name Pin Name Pin Type Pin Description MCLR/VPP VPP P Programming Power VDD VDD P Power Supply Vss VSS P Ground RB6 RB6 I Serial Clock RB7 RB7 I/O Serial Data Legend: I = Input, O = Output, P = Power 2000 Microchip Technology Inc. DS39028A-page 3-97 PIC18CXXX 2.0 2.1 IN-CIRCUIT SERIAL PROGRAMMING MODE (ICSP) Introduction Serial programming mode is entered by asserting MCLR/VPP = VIHH and RB6, RB7 = 0. Instructions are fed into the CPU serially on RB7, and are shifted in on the rising edge of the serial clock presented on RB6. Programming and verification are performed by executing TBLRD and TBLWT instructions. The address pointer to the program memory is simply the table pointer. The address pointer can be incremented and decremented by executing table reads and writes with auto-decrement and auto-increment. 2.2 ICSP OPERATION In ICSP mode, instruction execution takes place through a serial interface using RB6 and RB7. RB7 is used to shift in instructions and shift out data from the TABLAT register. RB6 is used as the serial shift clock and the CPU execution clock. Instructions and data are shifted in LSb first. In this mode all instructions are shifted serially, then loaded into the instruction register, and executed. No program fetching occurs from internal or external program memory. 8-bit data bytes are read from the TABLAT register via the same serial interface. 2.2.1 4-BIT SERIAL INSTRUCTIONS A set of 4-bit instructions are provided for ICSP mode, so that the most common instructions used for ICSP can be fetched quickly, and thus reduce the amount of time required to program a device. The 4-bit opcode is shifted in while the previous instruction fetched executes. The 4-bit instruction contains the lower 4-bits of an instruction opcode. The upper 12-bits default as all 0's. Instructions with all 0's in the upper byte of the instruction word, are by default considered special instructions. The serial instructions are decoded as shown in Table 2-1: TABLE 2-1: SPECIAL INSTRUCTIONS FOR SERIAL INSTRUCTION EXECUTION AND ICSP Mnemonic, Operands Description Cycles 4-Bit Opcode Status Affected NOP No Operation (Shift in16-bit instruction) 1 0000 None TBLRD * Table Read (no change to TBLPTR) 2 1000 None TBLRD *+ Table Read (post-increment TBLPTR) 2 1001 None TBLRD *- Table Read (post-decrement TBLPTR) 2 1010 None TBLRD +* Table Read (pre-increment TBLPTR) 2 1011 None TBLWT * Table Write (no change to TBLPTR) 2 1100 None TBLWT *+ Table Write (post-increment TBLPTR) 2 1101 None TBLWT *- Table Write (post-decrement TBLPTR) 2 1110 None TBLWT +* Table Write (pre-increment TBLPTR) 2 1111 None Legend: Refer to the PIC18CXXX Data Sheet (DS39026) for opcode field descriptions. Note: All special instructions not included in this table are decoded as NOP's In-Circuit Serial ProgrammingTM (ICSP) is a trademark of Microchip Technology Inc. DS39028A-page 3-98 2000 Microchip Technology Inc. PIC18CXXX 2.2.2 INITIAL SERIAL INSTRUCTION OPERATION Following the FNOP instruction execution and the next shifting in of the next instruction, the serial state machine will do one of three things depending upon the 4-bit instruction that was fetched: Upon ICSP mode entry, the CPU is idle. The execution of the CPU is governed by a state machine. The CPU clock source comes from RB6 which also acts as the serial shift clock. The first clock transition on RB6 is absorbed after RESET. While the first instruction is being clocked in, a forced NOP is executed. 1. 2. 3. If the instruction fetched was a NOP, the state machine will suspend the CPU awaiting a 16-bit wide instruction to be shifted in. If the instruction is a TBLWT, the state machine suspends the CPU from execution while sixteen bits of data are shifted in as data for the TBLWT instruction. If the instruction is a TBLRD, then execution of the TBLRD instruction begins immediately for eight clock cycles, followed by eight clock cycles where the contents of the TABLAT register is shifted out onto RB7. Once sixteen clock cycles have elapsed, the next 4-bit instruction is fetched while the current instruction is executed. Each instruction type is described in later sections. FIGURE 2-1: Q Cycles SERIAL INSTRUCTION TIMING AFTER RESET Q1 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 P1 VIHH P2 MCLR/VPP 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 RB6 (Clock) P9 P5 P5 P3P4 RB7 (Data) 1 1 0 1 1 Execute FNOP Fetch 4-bit Instruction (TBLWT **) Reset 16-bit Instruction Load or 16-bit data Fetch or Perform TABLRD followed by shift data out 1 0 1 Execute Instruction, Fetch Next 4-bit Instruction RB7 = Input or Output depending upon instruction ICSP Mode 2000 Microchip Technology Inc. DS39028A-page 3-99 PIC18CXXX 2.2.3 NOP SERIAL INSTRUCTION EXECUTION 2.2.4 The NOP serial instruction is used to allow execution of all other instructions not included in Table 2-1. When the NOP instruction is fetched, the serial execution state machine suspends the CPU for 16 clock cycles. During these 16 clock cycles, all 16-bits of an instruction are fed into the CPU and the NOP instruction is discarded. Once all 16 bits have been shifted in the state machine will allow the instruction to be executed for the next 4 clock cycles. Note: ONE CYCLE 16-BIT INSTRUCTIONS If the instruction fetched is a one cycle instruction, then the instruction operation will be completed in the 4 clock cycles following the instruction fetched. During instruction execution, the next 4-bit serial instruction is fetched (See Figure 2-2). 16-bit TBLWT and TBLRD instructions are not permitted. They will cause timing problems with the serial state machine. If the user wishes to perform a TBLWT or TBLRD instruction, it must be performed as a 4-bit instruction. FIGURE 2-2: SERIAL INSTRUCTION TIMING FOR 1 CYCLE 16-BIT INSTRUCTIONS Q Cycles Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 MCLR/VPP = VIHH P2 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 RB6 (Clock) P5 P5 P3P4 RB7 (Data) 0 0 0 1 0 Execute PC-2, Fetch NOP to enable 16-bit Instruction fetch 16-bit Instruction Fetch 1 0 1 Execute 16-bit Instruction, Fetch Next Serial 4-bit Instruction RB7 = Input ICSP Mode DS39028A-page 3-100 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-3: 16-BIT 1 CYCLE SERIAL INSTRUCTION FLOW AFTER RESET Start Execute 16-bit Instruction, and shift in next 4-bit instruction, Num_Clk = 1, MCLR = VSS, RB6, RB7 = 0 MCLR = VIHH Clock Transition RB6? Shift in 1st 4-bit instruction, Num_Clk = 1, No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Clock Transition RB6? No End Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 16-bit instruction, Num_Clk = 1 Clock Transition RB6? No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Num_Clk = 16? No Yes 2000 Microchip Technology Inc. DS39028A-page 3-101 PIC18CXXX FIGURE 2-4: 16-BIT 1 CYCLE SERIAL INSTRUCTION FLOW Start execute (PC - 2), and shift in next 4-bit instruction, Num_Clk = 1, Clock Transition RB6? execute 16-bit Instruction, and shift in next 4-bit instruction, Num_Clk = 1, No Clock Transition RB6? Yes No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Shift(R) RB7 Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 16-bit instruction, Num_Clk = 1 End Clock Transition RB6? No Yes Shift(R) RB7 into ROMLAT<15>, Num_Clk = Num_Clk + 1 Num_Clk = 16? No Yes DS39028A-page 3-102 2000 Microchip Technology Inc. PIC18CXXX 2.3 Serial Instruction Execution For Two Cycle, One Word Instructions When a NOP instruction is fetched, the serial execution state machine suspends the CPU for 16 clock cycles. During these 16 clock cycles, all 16-bits of an instruction are fed in and the NOP instruction is discarded. If the instruction fetched is a two cycle, one word instruction, then the instruction operation will require a second "dummy fetch" to be performed before the instruction execution can be completed. The first cycle of the instruction will be executed in the 4 clock cycles following the instruction fetched. During the first cycle of instruction execution, the next 4-bit serial instruction is fetched. In order to perform the second half of the two cycle instruction, this 4-bit instruction loaded in must be a NOP, so that state machine will remain idle for the second half of the instruction. Following the fetch of the second NOP, the state machine will shift 16-bits of data that will be discarded. After the 16-bits of data is shifted in, the state machine will release the CPU, and allow it to perform the second half of the two cycle instruction. During the second half of the two cycle instruction execution, the next 4-bit instruction is loaded (See Figure 2-5). FIGURE 2-5: Q Cycles 2 CYCLE 1 WORD 16-BIT INSTRUCTION SEQUENCE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 MCLR/VPP Q1 Q2 Q3 Q4 P2 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 0 1 RB6 (Clock) P5 P5 P5 P5 P3P4 RB7 (Data) 0 0 0 1 0 Execute PC-2 Fetch 4-bit NOP Fetch 16-bit Instruction Fetch 4-bit NOP, Execute 1st Cycle of 16-bit Instruction 1 Fetch 2nd 16-bit Execute 2nd Cycle, Operand Word (discarded) Fetch Next 4-bit Instruction RB7 = Input ICSP Mode 2000 Microchip Technology Inc. DS39028A-page 3-103 PIC18CXXX 2.4 Serial Instruction Execution For Two Word, Two Cycle Instructions After a NOP instruction is fetched, the serial execution state machine suspends the CPU in the Q4 state for 16 clock cycles. During these 16 clock cycles, all 16bits of an instruction are fed in and the NOP instruction is discarded. If the 16-bit instruction fetched is a two cycle, two word instruction, then the instruction operation will require a second operand fetch to be performed before the instruction execution can be completed. The first cycle of the instruction will be executed in the 4 clock cycles following the 16-bit instruction fetch. During the first cycle of instruction execution, the next 4-bit serial instruction is fetched. In order to perform the second half of the two cycle instruction, this 4-bit instruction loaded in must also be a NOP, so that the state machine will remain idle for the second half of the instruction. Following the fetch of the second NOP, the state machine will shift 16-bits of data that will be used as an operand for the two cycle instruction. After the 16-bits of data are shifted in, the state machine will release the CPU, and allow it to execute the second half of the two cycle instruction. During the second half of the two cycle instruction execution, the next 4-bit instruction is loaded (see Figure 2-6). FIGURE 2-6: 16-BIT 2 CYCLE 2 WORD INSTRUCTION SEQUENCE Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 MCLR/VPP = VIHH Q1 Q2 Q3 Q4 P2 1 2 3 4 1 2 3 15 16 1 2 3 4 1 2 15 16 1 2 3 4 RB6 (Clock) P5 P5 P5 P5 P3P4 RB7 (Data) 0 0 0 0 0 Execute PC-2, Fetch 4-bit NOP Fetch 1st word 0 0 1 0 Execute 1st Cycle, Fetch 4-bit NOP Fetch 2nd word 1 0 1 Execute 2nd Cycle, Fetch next 4-bit Instruction RB7 = Input ICSP Mode DS39028A-page 3-104 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-7: 16-BIT 2 CYCLE 2 WORD SERIAL INSTRUCTION FLOW AFTER RESET Start MCLR = VPP, RB6, RB7 = 0 Clock Transition RB6? MCLR = VIHH Yes execute FNOP and shift in 1st 4-bit instruction, Num_Clk = 1, Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 16-bit instruction, Num_Clk = 1 Shift(R) RB7, Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 2nd 16-bit operand, Num_Clk = 1 Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 Num_Clk = 16? No Yes Enable CPU, execute 1st cycle of 16-bit instruction, and shift in next 4-bit instruction, Num_Clk = 1, 2000 Microchip Technology Inc. No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 Num_Clk = 16? Clock Transition RB6? No No Yes execute 2nd cycle of 16-bit instruction, and shift in next 4-bit instruction Num_Clk = 1 Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 End DS39028A-page 3-105 PIC18CXXX FIGURE 2-8: 16-BIT 2 CYCLE 2 WORD SERIAL INSTRUCTION FLOW Clock Transition RB6? Start Yes execute (PC-2)and shift in 4-bit instruction, Num_Clk = 1, Clock Transition RB6? No No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 16-bit instruction, Num_Clk = 1 Shift(R) RB7, Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 2nd 16-bit operand, Num_Clk = 1 Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 Num_Clk = 16? Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 Num_Clk = 16? No Yes execute 1st cycle of 16-bit instruction, and shift in next 4-bit instruction, Num_Clk = 1, DS39028A-page 3-106 No Yes execute 2nd cycle of 16-bit instruction, and shift in next 4-bit instruction Num_Clk = 1 Clock Transition RB6? No Yes Shift(R) RB7, Num_Clk = Num_Clk + 1 End 2000 Microchip Technology Inc. PIC18CXXX 2.5 The TBLWT instruction is used in ICSP mode to program the EPROM array. When writing a 16-bit value to the EPROM, ID locations, or configuration locations, the device, RB6, must be held high for the appropriate programming time during the TBLWT instruction as specified by parameter P9. TBLWT Instruction The TBLWT instruction is a unique two cycle instruction. All forms of TBLWT instructions (post/pre-increment, post decrement, etc.) are encoded as 4-bit special instructions. This is useful as TBLWT instructions are used repeatedly in ICSP mode. A 4-bit instruction will minimize the total number of clock cycles required to perform programming algorithms. When RB6 is asserted low the device will cease programming the specified location. After RB6 is asserted low, RB6 is held low for the time specified by parameter P10, to allow high voltage discharge of the program memory array. The TBLWT instruction sequence operates as follows: 1. 2. 3. 4. The 4-bit TBLWT instruction is read in by the state machine on RB7 during the 4 clock cycle execution of the instruction fetched previous to the TBLWT (which is an FNOP if the TBLWT is executed following a reset). Once the state machine recognizes that the instruction fetched is a TBLWT, the state machine proceeds to fetch in the 16-bits of data that will be written into the program memory location pointed to by the TBLPTR. The serial state machine releases the CPU to execute the first cycle of the TBLWT instruction while the first 4 bits of the 16-bit data word are shifted in. After the first cycle of TBLWT instruction has completed the state machine shifts in the remaining 12 of the sixteen bits of data. The data word will not be used until the second cycle of the instruction. After all 16-bits of data are shifted in and the first cycle of the TBLWT is performed, the CPU is allowed to execute the second cycle of the TBLWT operation, programming the current memory location with the 16-bit value. The next instruction following the TBLWT instruction is shifted in during the execution of the second cycle (See Figure 2-9). FIGURE 2-9: TBLWT INSTRUCTION SEQUENCE Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 MCLR/VPP = VIHH Q1 Q2 Q3 Q4 P2 1 2 3 4 1 2 3 4 P10 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 RB6 (Clock) P9 P5 P5 P3P4 RB7 (Data) 1 1 0 0 0 Execute PC-2 Fetch TBLWT 0 0 0 Execute 1st Cycle TBLWT 1 1 0 1 Execute 2nd Cycle TBLWT and fetch next 4-bit instruction Load TBLWT Data RB7 = Input ICSP Mode 2000 Microchip Technology Inc. DS39028A-page 3-107 PIC18CXXX FIGURE 2-10: TBLWT SERIAL INSTRUCTION FLOW AFTER RESET Start Clock Transition RB6? MCLR = VSS, RB6, RB7 = 0 No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 MCLR = VIHH Execute FNOP, and shift in 4-bit TBLWT instruction, Num_Clk = 1, Num_Clk = 12? No Yes Clock Transition RB6? No Execute 2nd cycle of TBLWT instruction and shift in next 4-bit instruction, Num_Clk = 1, Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 4-bit instruction = TBLWT, Execute 1st cycle of TBLWT, Begin Shifting in TBLWT data, Num_Clk = 1 Clock Transition RB6? No Clock Transition RB6? No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 End Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Num_Clk = 4? No Yes shift in last 12 bits of TBLWT data, Num_Clk = 1, DS39028A-page 3-108 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-11: TBLWT SERIAL INSTRUCTION FLOW Clock Transition RB6? No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Start Execute (PC-2), and shift in 4-bit TBLWT instruction, Num_Clk = 1, Num_Clk = 12? No Yes Clock Transition RB6? No Execute 2nd cycle of TBLWT instruction and shift in next 4-bit instruction, Num_Clk = 1, Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 4-bit instruction = TBLWT, Execute 1st cycle of TBLWT, Begin Shifting in TBLWT data, Num_Clk = 1 Clock Transition RB6? No Clock Transition RB6? No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 End Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Num_Clk = 4? No Yes Shift in last 12 bits of TBLWT data, Num_Clk = 1, 2000 Microchip Technology Inc. DS39028A-page 3-109 PIC18CXXX 2.6 TBLRD Instruction The TBLRD instruction sequence operates as follows: 1. The TBLRD instruction is another unique two cycle instruction. All forms of TBLRD instructions (post/pre-increment, post decrement, etc.) are encoded as 4-bit special instructions. This is useful as TBLRD instructions are used repeatedly in ICSP mode. A 4-bit instruction will minimize the total number of clock cycles required to perform programming algorithms. 2. 3. 4. The 4-bit TBLRD instruction is read in by the state machine on RB7 during the 4 clock cycle execution of the instruction fetched previous to the TBLRD (which is an FNOP if the TBLRD is executed following a reset). Once the state machine recognizes that the instruction fetched is a TBLRD, the state machine releases the CPU and allows execution of the first and second cycles of the TBLRD instruction for eight clock cycles. When the TBLRD is performed, the contents of the program memory byte pointed to by the TBLPTR is loaded into the TABLAT register. After eight clock cycles have transitioned on RB6, and the TBLRD instruction has completed, the state machine will suspend the CPU for eight clock cycles. During these eight clock cycles, the state machine configures RB7 as an output, and will shift out the contents of the TABLAT register onto RB7 LSb first. When the state machine has shifted out all eight bits of data, the state machine suspends the CPU to allow an instruction pre-fetch. Four (4) clock cycles are required on RB6 to shift in the next 4-bit instruction. FIGURE 2-12: TBLRD INSTRUCTION SEQUENCE Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 MCLR/VPP = VIHH 1 2 3 4 1 2 3 4 1 2 3 1 4 2 3 4 5 6 7 8 1 2 3 4 RB6 (Clock) P5 RB7 (Data) 1 0 0 Execute PC-2 Fetch TBLRD P5 P6 LSb 1 Execute Cycle 1 TBLRD RB7 = Input Execute Cycle 2 TBLRD 1 2 3 4 5 6 MSb Shift Data Out From TABLAT RB7 = Output 1 0 0 1 No Execution takes place, Fetch Next 4-bit instruction RB7 = Input ICSP Mode DS39028A-page 3-110 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-13: TBLRD SERIAL INSTRUCTION FLOW AFTER RESET Start Clock Transition RB6? MCLR = VSS, RB6, RB7 = 0 No Yes MCLR = VIHH Shift(R) TABLAT<0> out onto RB7 Num_Clk = Num_Clk + 1 Execute FNOP, and shift in 4-bit TBLRD instruction, Num_Clk = 1, Num_Clk = 8? No Yes Clock Transition RB6? No Shift in next 4-bit instruction Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Enable CPU, execute 1st and 2nd cycle TBLRD instruction Clock Transition RB6? No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Clock Transition RB6? No Num_Clk = 4? No Yes Yes TBLRD instruction execution takes place here Num_Clk = Num_Clk + 1 Num_Clk = 8? End No Yes Shift out 8-bits of data to RB7 2000 Microchip Technology Inc. DS39028A-page 3-111 PIC18CXXX FIGURE 2-14: TBLRD SERIAL INSTRUCTION FLOW Start Execute (PC-2), and shift in 4-bit TBLRD instruction, Num_Clk = 1, Clock Transition RB6? No Yes Shift(R) TABLAT<0> out onto RB7 Num_Clk = Num_Clk + 1 Clock Transition RB6? No Num_Clk = 8? No Yes Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Shift in next 4-bit instruction Execute 1st and 2nd cycle TBLRD instruction Clock Transition RB6? Clock Transition RB6? No No Yes Shift(R) RB7 Num_Clk = Num_Clk + 1 Yes TBLRD instruction execution takes place here Num_Clk = Num_Clk + 1 Num_Clk = 4? Num_Clk = 8? Yes No No Yes End Shift out 8-bits of data to RB7 DS39028A-page 3-112 2000 Microchip Technology Inc. PIC18CXXX 2.6.1 SOFTWARE COMMANDS ICSP commands of the PICmicro(R) MCU are supported in the PIC18CXXX family by simply combining CPU instructions. Once in In-Circuit Serial Programming (ICSP) mode, the instructions are loaded into a shift register, and the device waits for a command to be received. The ICSP commands for the PIC16CXXX family are now "pseudo-commands" and are shown in Table 2-2. The following sections are a description of how the pseudo-commands can be implemented using CPU instructions. TABLE 2-2: ICSP PSEUDO COMMAND MAPPING ICSP Command Golden Gate Instructions Load Configuration MOVLW #Address1 Load Data Not needed. Data encoded in 4-bit TBLWT instruction sequence. Read Data TBLRD instruction Increment Address Not needed. Use TBLWT with increment/decrement (TBLWT *+/*-). Load Address MOVLW #Addr_low MOVWF TBLPTRL MOVLW #Addr_high MOVWF TBLPTRH Reset Address MOVLW #Data MOVWF TBLPTRH MOVWF TBLPTRL MOVWF TBLPTRU MOVWF TBLPTRL MOVLW #Address2 MOVWF TBLPTRH MOVLW #Address3 MOVLW #Addr_upper MOVWF TBLPTRU MOVWF TBLPTRU Begin programming TBLWT End Programming Not needed. Programming will cease at the end of TBLWT execution. 2000 Microchip Technology Inc. DS39028A-page 3-113 PIC18CXXX 2.6.2 RESET ADDRESS A reset of the program memory pointer is a write to the upper, high, and low bytes of the TBLPTR. To reset the program memory pointer, the following instruction sequence is used. NOP MOVLW NOP MOVWF NOP MOVWF NOP MOVWF ;(4-BIT INSTRUCTION) 00h ;(4-BIT INSTRUCTION) TBLPTRU, 0 ;(4-BIT INSTRUCTION) TBLPTRH, 0 ;(4-BIT INSTRUCTION) TBLPTRL, 0 DS39028A-page 3-114 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-15: RESET ADDRESS SERIAL INSTRUCTION SEQUENCE Start execute (PC - 2), shift in next 4-bit instruction, Num_Clk = 1, (NOP) On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 4-bit instruction = NOP, Shift in 16-bit MOVWF instruction, Num_Clk = 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 MOVWF TBLPTRM,0 (NOP) No Num_Clk = 4? Num_Clk = 16? No Yes Yes 4-bit instruction = NOP, Shift in 16-bit MOVLW instruction, Num-Clk = 1 (NOP) On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 execute MOVWF Instruction, shift in 4-bit NOP instruction, Num_Clk = 1, On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 MOVLW 00h Num_Clk = 16? (NOP) No Num_Clk = 4? Yes No Yes Execute MOVLW Instruction, shift in 4-bit NOP instruction, Num_Clk = 1, (NOP) 4-bit instruction = NOP, Shift in 16-bit MOVWF instruction, Num_Clk = 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 (NOP) Num_Clk = 4? No Num_Clk = 16? MOVWF TBLPTRM,0 No Yes Yes Execute MOVWF Instruction, shift in next 4-bit instruction, Num_Clk = 1, End 2000 Microchip Technology Inc. DS39028A-page 3-115 PIC18CXXX 2.6.3 LOAD ADDRESS This is used to load the address pointer to the Program Memory with a specific 22-bit value. This is useful when a specific range of locations are to be accessed. To load the address into the table pointer, the following commands must be used: NOP MOVLW NOP MOVWF NOP MOVLW NOP MOVWF NOP MOVLW NOP MOVWF ; 4-bit instruction Low_Address ; 4-bit instruction TBLPTRL, 0 ; 4-bit instruction High_Address ; 4-bit instruction TBLPTRH, 0 ; 4-bit instruction Upper_Address ; 4-bit instruction TBLPTRU, 0 DS39028A-page 3-116 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-16: LOAD ADDRESS SERIAL INSTRUCTION SEQUENCE Start execute (PC - 2), shift in next 4-bit instruction, Num_Clk = 1, 4-bit instruction = NOP, Shift in 16-bit MOVWF instruction, Num_Clk = 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 MOVWF TBLPTRL,0 (NOP) No Num_Clk = 4? Num_Clk = 16? Yes Yes 4-bit instruction = NOP, Shift in 16-bit MOVLW instruction, Num_Clk = 1 execute MOVWF Instruction, shift in 4-bit NOP instruction, Num_Clk = 1, On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 MOVLW LOW_Address Num_Clk = 16? No On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 (NOP) No Num_Clk = 4? Yes No Yes execute MOVLW Instruction, shift in 4-bit NOP instruction, Num_Clk = 1, 4-bit instruction = NOP, Shift in 16-bit MOVWF instruction, Num_Clk = 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<3>, Num_Clk = Num_Clk + 1 On rising edge RB6 Shift(R) RB7 into Shift Reg<15>, Num_Clk = Num_Clk + 1 (NOP) Num_Clk = 4? No Num_Clk = 16? MOVLW HIGH_Address No Yes Yes execute MOVWF Instruction, shift in next 4-bit instruction, Num_Clk = 1, End 2000 Microchip Technology Inc. DS39028A-page 3-117 PIC18CXXX 2.6.4 ICSP BEGIN PROGRAMMING Programming is performed by executing a TBLWT instruction. In ICSP mode the TBLWT instruction sequence will include 16-bits of data that are shifted into a data buffer, and then written to the word location that is addressed by the TBLPTR. Although the TBLPTR addresses the program memory on a byte wide boundary, all 16-bits of data that are shifted in during the TBLWT sequence are written at once. The 16-bits are shifted into the TABLAT and buffer registers. The TBLPTR points to the word that will be programmed; it can point to either the high or the low byte. (See Figure 2-17). The sequence for programming a location could occur as follows: 1. 2. 3. 4. 5. 6. 7. 8. Setup the TLBPTR with the first ok address to be programmed (even or odd byte). Shift in a 4 bit TBLWT instruction. 16-bits of data are then shifted in for programming both high and low byte of the first programmed location. Execute TBLWT instruction to program location. Verify high byte (odd address) by executing TLBRD *- (post-decrement). (If TBLPTR pointing at odd address.) Verify low byte (even address) by executing TLBRD *+ (post-increment). TBLPTR is pointing to odd address again. If location doesn't verify, go back to step 4. If location does verify, begin 3x overprogramming. The TBLWT instruction offers flexibility with multiple addressing modes: pre-increment, post-increment, post decrement, and no change of the TBLPTR. These modes eliminate the need for the increment address command sequence. FIGURE 2-17: DATA BUFFERING SCHEME FOR ICSP Program Memory bank 0 (Even Address) Program Memory bank 1 (Odd Address) TBLWT TBLWT Odd or Even address Odd or Even address Buffer Register TABLAT Register RB7 TBLRD TBLRD DS39028A-page 3-118 Odd Data shifted into TABLAT and Buffer registers Even 2000 Microchip Technology Inc. PIC18CXXX 2.6.5 PROGRAMMING INSTRUCTION SEQUENCE The series of instructions needed to execute a programming sequence is as follows. Many of the instruction sequences used in the following example are also shown in previous sections. NOP MOVLW NOP MOVWF NOP MOVLW NOP MOVWF NOP MOVLW NOP MOVWF Low_Byte_Address ; ; ; ; ; 4-bit instruction Set up low byte of program address = 00 4-bit instruction TBLPTRL, 0 ; ; ; ; High_Byte_Address ; ; TBLPTRH, 0 ; ; ; ; Upper_Byte_Address; ; TBLPTRU, 0 ; ; ; ; TBLWT+* 4-bit instruction Set up high byte of program address = 00 4-bit instruction 4-bit instruction Set up upper byte of program address = 00 4-bit instruction Program data byte included in TBLWT instruction sequence ; TBLPTR = 000000h 2.6.6 VERIFY SEQUENCE The table pointer = 000001h in the last example. A TBLRD will then read the odd address byte of the current program word address location first. The verify sequence will be as follows: ; Read/verify high byte first TBLRD*; TBLPTR = 0000 post-dec ; Read/verify low byte TBLRD* The first TBLRD decrements the table pointer to point to the even address byte of the current program word. After the first and second cycle of the TBLRD are performed, all 8-bits of data are shifted out on RB7. The fetch of the second TBLRD occurs on the next 4 clock cycles. The second TBLRD does not modify the table pointer address. This allows another programming cycle (TBLWT+*) to take place if the verify doesn't match the program data without having to update the table pointer. If the contents of the verify do not match the intended program data word, then the TBLWT instruction must be repeated with the correct contents of the current program word. Therefore, only one instruction needs to be performed to repeat the programming cycle: TBLWT+* 2.6.7 3X OVER PROGRAMMING A write of a program memory location with an odd or an even address causes a long write cycle in ICSP mode. The 16-bit data is encoded in the TBLWT sequence and is loaded into the temporary buffer register for word wide writes. Once a location has been both programmed and verified over a range of voltages, 3x over programming should be applied. In other words, apply three times the number of programming pulses that were required to program a location in memory, to ensure a solid programming margin. The user must wait 100 s for the long write to complete before the next instruction is executed. This means that every location will be programmed a minimum of 4 times (1 + 3x over programming). 2000 Microchip Technology Inc. DS39028A-page 3-119 PIC18CXXX FIGURE 2-18: DETAILED PROGRAMMING FLOW CHART - PROGRAM MEMORY Execute 1st cycle TBLWT +*, and shift in first 4-bits of data for 4 clock cycles Start MCLR = VPP, RB6, RB7 = 0 B Shift in last 12-bits of data for 12 clock cycles N=0 Execute 2nd cycle TBLWT +* for 4 clock cycles Shift in TBLRD *for 4 clock cycles Execute FNOP for four clock cycles shift in 4-bit NOP Hold RB6 Clock high 4-bit instruction = NOP, Shift in 16-bit MOVLW Low_Addr instruction for 16 clock cycles Wait 100 sec to ensure programming Execute MOVLW for 4 clock cycles and shift in 4-bit NOP Clock Low for Discharge Hold RB6 Clock high (P10) 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRL instruction for 16 clock cycles Execute MOVWF for 4 clock cycles and shift in 4-bit NOP Execute MOVWF for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVLW Upper_Addr instruction for 16 clock cycles 4-bit instruction = NOP, Shift in 16-bit MOVLW High_Addr instruction for 16 clock cycles Execute MOVLW for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRH instruction for 16 clock cycles Execute MOVLW for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRU instruction for 16 clock cycles Execute 1st and 2nd cycle TBLRD *- for 8 clock cycles Shift Data Out for 8 clock cycles Hold CPU, Shift in TBLRD * for 4 clock cycles Execute 1st and 2nd cycle TBLRD * for 8 clock cycles Shift Data Out for 8 clock cycles Verify? Execute current instruction for 4 clock cycles, and shift in 4-bit TBLWT+* Yes A No N=N+1 N > 25? No DS39028A-page 3-120 Yes Report Programming Failure 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-19: DETAILED PROGRAMMING FLOW CHART - PROGRAM MEMORY (CONTINUED) A N=3*N Execute current instruction, Shift in TBLWT *+ for 4 clock cycles Execute 1st cycle TBLWT *+ or *, and shift in first 4-bits of data for 4 clock cycles Shift in last 12-bits of data for 12 clock cycles N = 1? No Yes Execute 2nd cycle TBLWT * for 4 clock cycles Shift in TBLWT *+ for 4 clock cycles Shift in last 12-bits of data for 12 clock cycles Execute 2nd cycle TBLWT * for 4 clock cycles Shift in TBLWT * for 4 clock cycles Hold RB6 high Wait 100 S Clock Low for Discharge Execute current instruction for 4 clock cycles, and shift in 4-bit TBLRD+* N=N-1 Hold RB6 high Verify all Locations @ VDDMIN Wait 100 sec to ensure programming No Data Correct? All locations programmed? No To B Yes Yes Report Verify Error @ VDDMIN Verify all Locations @ VDDMAX Yes Data Correct? No Report Verify Error @ VDDMAX End 2000 Microchip Technology Inc. DS39028A-page 3-121 PIC18CXXX 2.6.8 LOAD CONFIGURATION 2.6.9 END PROGRAMMING The Configuration registers are located in ok memory, and are only addressable when the high address bit of the TBLPTR (bit 21) is set. Test program memory contains test memory, configuration registers, calibration registers, and ID locations. The desired address must be loaded into all three bytes of the table pointer to program specific ID locations or the configuration bits. To program the configuration registers, the following sequence must be followed: When programming occurs, 16 bits of data are programmed into memory. The 16-bits of data are shifted in during the TBLWT sequence. After the programming command (TBLWT) has been executed, the user must wait for 100 s until programming is complete, before another command can be executed by the CPU. There is no command to end programming. NOP After the falling edge occurs on RB6, RB6 must be held low for a period of time so that a high voltage discharge can be performed to ensure that the program array isn't stressed at high voltage during execution of the next instruction. The high voltage discharge will occur while RB6 is low following the programming time. ; 4-bit instruction ; shift in 16-bit ; MOVLW instruction MOVLW NOP 03h MOVWF NOP TBLPTRU, 0 MOVLW NOP MOVWF NOP MOVLW NOP MOVWF NOP TBLWT ; ; ; ; 4-bit instruction shift in 16-bit MOVWF instruction Enable Test memory RB6 must remain high for as long as programming is desired. When RB6 is lowered programming will cease. ; 4-bit instruction ; shift in 16-bit ; MOVLW instruction Low_Config_Address ; 4-bit instruction ; shift in 16-bit ; MOVWF instruction TBLPTRL, 0 ; 4-bit instruction ; shift in 16-bit ; MOVLW instruction ; High_Config_Address ; 4-bit instruction ; shift in 16-bit ; MOVWF instruction TBLPTRH, 0 ; 4-bit instruction ; shift in 16-bit ; MOVLW instruction *+ ; 16-bits of data are ; shifted in for write ; of config1L and ; config1H TBLWT is a ; 4-bit special ; instruction Wait ; 100 sec for programming DS39028A-page 3-122 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-20: SYMBOLIC PROGRAMMING FLOW CHART - CONFIG WORD / ID LOCATION START MCLR = VSS 4.75V < VDD < 5.25V MCLR = VIHH ICSP Command LOAD CONFIGURATION Address = 300000h N=0 No ICSP Command LOAD DATA Yes Program ID Loc? ICSP Command BEGIN PROGRAMMING ICSP Command LOAD ADDRESS Address = 300000h Wait approx 100 s ICSP Command READ DATA ICSP Command LOAD DATA Data Correct? Yes Yes Report Programming Failure ICSP Command BEGIN PROGRAMMING Wait approx 100 s N = 3N ICSP Command BEGIN PROGRAMMING N=0 N=N-1 No No N > 25? N = 100 Wait approx 100 s Address = 300000h? N=N-1 ICSP Command INCREMENT ADDRESS N = 0? Yes No ICSP Command READ DATA Yes No Data Correct? Yes N = 0? Report Programming Failure Verify all Locations @ VDDMIN Report Verify Error @ VDDMIN Data Correct? Verify all Locations @ VDDMAX Data Correct? No Report Verify Error @ VDDMAX DONE 2000 Microchip Technology Inc. DS39028A-page 3-123 PIC18CXXX FIGURE 2-21: DETAILED PROGRAMMING FLOW CHART - CONFIG WORD START Execute MOVLW for 4 clock cycles and shift in 4-bit NOP MCLR = VSS 4.75V < VDD < 5.25V MCLR = VIHH Execute FNOP for four clock cycles shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVWF TBPLTRL instruction for 16 clock cycles TBPLTR = 0x300000h CONFIG1L and CONFIG1H B N = 99 4-bit instruction = NOP, Shift in 16-bit MOVLW 30 instruction for 16 clock cycles Execute MOVLW for 4 clock cycles and shift in 4-bit NOP Execute last fetched inst. for 4 clock cycles and shift in 4-bit TBLWT+* Execute 1st cycle TBLWT, and shift in first 4-bits of config. reg. for 4 clock cycles 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRU instruction for 16 clock cycles Shift in last 12-bits of data for 12 clock cycles Execute MOVWF for 4 clock cycles and shift in 4-bit NOP N = 1? 4-bit instruction = NOP, Shift in 16-bit MOVLW 00 instruction for 16 clock cycles Execute 2nd cycle TBLWT for 4 clock cycles Shift in TBLWT * for 4 clock cycles Execute MOVLW for 4 clock cycles and shift in 4-bit NOP RB6 High Yes No 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRH instruction for 16 clock cycles Wait 100 sec to ensure programming Clock Low for Discharge N=N-1 Execute MOVWF for 4 clock cycles and shift in 4-bit NOP Execute 2nd cycle TBLWT* for 4 clock cycles Shift in TBLWT *for 4 clock cycles 4-bit instruction = NOP, Shift in 16-bit MOVLW 00 instruction for 16 clock cycles Wait 100 sec to ensure programming DS39028A-page 3-124 A 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-22: DETAILED PROGRAMMING FLOW CHART - CONFIG WORD A Execute 1st cycle TBLWT*-, and shift in first 4-bits of config. reg. for 4 clock cycles Verify? Shift in last 12-bits of data for 12 clock cycles Execute 2nd cycle TBLWT *- for 4 clock cycles Shift in TBLRD*+ for 4 clock cycles Wait 100 sec to ensure programming Report Verify Error Yes All locations programmed? No B Yes Verify all ID_Locations @ VDDMIN Execute 1st and 2nd cycle TBLRD*+ for 8 clock cycles Data Correct? Shift Data Out for 8 clock cycles No No Report Verify Error @ VDDMIN Yes Verify all Locations @ VDDMAX Shift in TBLRD*+ for 4 clock cycles No Execute 1st and 2nd cycle TBLRD*+ for 8 clock cycles Data Correct? Report Verify Error @ VDDMAX Yes Shift Data Out for 8 clock cycles 2000 Microchip Technology Inc. DONE DS39028A-page 3-125 PIC18CXXX FIGURE 2-23: DETAILED PROGRAMMING FLOW CHART - ID LOCATION Start MCLR = VPP, RB6, RB7 = 0 Execute 1st cycle TBLWT +*, and shift in first 4-bits of data for 4 clock cycles N=0 B Shift in last 12-bits of data for 12 clock cycles Execute FNOP for four clock cycles shift in 4-bit NOP Execute 2nd cycle TBLWT +* for 4 clock cycles Shift in TBLRD *for 4 clock cycles 4-bit instruction = NOP, Shift in 16-bit MOVLW Low_Addr instruction for 16 clock cycles Wait 100 sec to ensure programming Execute MOVLW for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRL instruction for 16 clock cycles Execute MOVWF for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVLW High_Addr instruction for 16 clock cycles Execute 1st and 2nd cycle TBLRD *- for 8 clock cycles Shift Data Out for 8 clock cycles Execute MOVWF for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVLW Upper_Addr instruction for 16 clock cycles Execute 1st and 2nd cycle TBLRD * for 8 clock cycles Shift Data Out for 8 clock cycles Execute MOVLW for 4 clock cycles and shift in 4-bit NOP Verify? Execute MOVLW for 4 clock cycles and shift in 4-bit NOP 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRU instruction for 16 clock cycles 4-bit instruction = NOP, Shift in 16-bit MOVWF TBLPTRH instruction for 16 clock cycles Shift in TBLRD * for 4 clock cycles Execute current instruction for 4 clock cycles, and shift in 4-bit TBLWT+* A No N=N+1 N > 25? No DS39028A-page 3-126 Yes Yes Report Programming Failure 2000 Microchip Technology Inc. PIC18CXXX FIGURE 2-24: DETAILED PROGRAMMING FLOW CHART - ID LOCATIONS (CONTINUED) A N=3*N Execute current instruction, Shift in TBLWT *+ for 4 clock cycles Execute 1st cycle TBLWT *+ or *, and shift in first 4-bits of data for 4 clock cycles Shift in last 12-bits of data for 12 clock cycles N = 1? No Yes Execute 2nd cycle TBLWT * for 4 clock cycles Shift in TBLWT *+ for 4 clock cycles Execute 1st cycle TBLWT *+, and shift in first 4-bits of data for 4 clock cycles Wait 100 sec to ensure programming Execute 2nd cycle TBLWT * for 4 clock cycles Shift in TBLWT * for 4 clock cycles N=N-1 Shift in last 12-bits of data for 12 clock cycles Execute 2nd cycle TBLWT *+ for 4 clock cycles, and shift in 4-bit TBLWT +* Verify all Locations @ VDDMIN Wait 100 sec to ensure programming No Data Correct? Yes All locations programmed? Yes Verify all Locations @ VDDMAX Yes No B 2000 Microchip Technology Inc. Report Verify Error @ VDDMIN Data Correct? No Report Verify Error @ VDDMAX End DS39028A-page 3-127 PIC18CXXX 3.0 CONFIGURATION WORD The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh). TABLE 3-1: CONFIGURATION BITS AND DEVICE IDS Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default / unprogrammed value 300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111 300001h CONFIG1H RES1 RES1 OSCSEN -- -- FOSC2 FOSC1 FOSC0 111- -111 300002h CONFIG2L -- -- -- -- BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H -- -- -- -- WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300005h CONFIG3H -- -- -- -- -- -- -- CCP2MX ---- ---1 300006h CONFIG4L -- -- -- -- -- -- RES1 STVREN ---- --11 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 ---- ---- 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 ---- ---- Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, grayed cells are unimplemented read as 0 Note 1: Resvered - Read as 1. DS39028A-page 3-128 2000 Microchip Technology Inc. PIC18CXXX Register 3-1: Configuration Register 1 High (CONFIG1H: Byte Address 300001h) R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 Reserved Reserved OSCSEN -- -- FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Reserved: Read as '1' bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 =Oscillator system clock switch option is disabled (OSCA is source) 0 =Oscillator system clock switch option is enabled (OSCA OSCB, OSCB OSCA switching is enabled) bit 4-3 Reserved: Read as '0' bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS oscillator with PLL enabled/CLock frequency = (4 x Fosc1) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide by 4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state Register 3-2: Configuration Register 1 Low (CONFIG1L: Byte Address 300000h) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP CP CP CP CP CP CP bit 7 R/P-1 CP bit 0 CP: Code Protection bits (apply when in Code Protected Microcontroller Mode) 1 = Program memory code protection off 0 = All of program memory code protected Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2000 Microchip Technology Inc. U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39028A-page 3-129 PIC18CXXX Register 3-3: Configuration Register 2 High (CONFIG2H: Byte Address 300003h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- -- WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Reserved: Read as '0' bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTE bit) Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state Register 3-4: Configuration Register 2 Low (CONFIG2L: Byte Address 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- -- BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Reserved: Read as '0' bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. bit 0 PWRTEN: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39028A-page 3-130 U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2000 Microchip Technology Inc. PIC18CXXX Register 3-5: Configuration Register 3 High (CONFIG3H: Byte Address 300005h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 -- -- -- -- -- -- -- CCP2MX bit 7 bit 0 bit 7-1 Reserved: Read as '0' bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state Register 3-6: Configuration Register 4 Low (CONFIG3H: Byte Address 300006h) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 -- -- -- -- -- -- Reserved STVREN bit 7 bit 0 bit 7-2 Reserved: Read as '0' bit 1 Reserved: Maintain this bit set. bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause reset 0 = Stack Full/Underflow will not cause reset Legend R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 3.1 U = Unimplemented bit, read as `0' u = Unchanged from programmed state ID Locations A user may store identification information (ID) in 8 ID locations. The ID locations are mapped in [0x200000:0x200007]. It is recommended that the user use only the 4 least significant bits of each ID location. The ID locations do not read out in a scrambled fashion after code protection is enabled. For all devices it is recommended that all ID locations are written as `1111 bbbb' where bbbb is the ID information. When the upper four bits of an ID location is written as `1111', the resulting opcode when executed is read as a NOP. This allows Reset testing of test program memory after ID locations have been programmed. 2000 Microchip Technology Inc. DS39028A-page 3-131 PIC18CXXX 3.2 Embedding Configuration Word Information in the Hex File To allow portability of code, a PIC18C4X programmer is required to read the configuration word locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the hex file, it should be to address FE00h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 3.3 ently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. CHECKSUM COMPUTATION The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differ- TABLE 3-2: Device PIC18C452 PIC18C442 PIC18C252 PIC18C242 Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0xAA at 0 and max address Disable SUM[0C000:0x7FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 0x8148 0x809E Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0xF + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 + SUM_ID 0x005E 0x0068 Disable SUM[0x000:0x3FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 0xC148 0xC09E Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 + SUM_ID 0x0062 0x006C Disable SUM[0x000:0x7FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 0x8148 0x809E Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 + SUM_ID 0x005E 0x0068 Disable SUM[0x000:0x3FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 0xC148 0xC09E Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 & 0x00 + SUM_ID 0x0062 0x006C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = Byte-wise sum of lower four bits of all ID locations + = Addition & = Bitwise AND DS39028A-page 3-132 2000 Microchip Technology Inc. PIC18CXXX 4.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10C TA +70C, unless otherwise stated, (25C is recommended) Operating Voltage: Parameter No. Sym VIHH IPP * 4.5V VDD 5.25V, unless otherwise stated. Characteristic Programming Voltage on VPP/ MCLR pin and TEST pin. Min Typ Max Units VDD + 4.0 -- 13.25 V 25 50 mA Programming current on MCLR pin P1 TSER Serial setup time 20 -- -- ns P2 TSCLK Serial Clock period 100 -- -- ns P3 TSET1 Input Data Setup Time to serial clock 15 -- -- ns P4 THLD1 Input Data Hold Time from serial clock 15 -- -- ns P5 TDLY1 Delay between last clock to first clock of next command 20 -- -- ns P6 TDLY2 Delay between last clock of command byte to first clock of read of data word 20 -- -- ns P8 TDLY4 Data input not driven to next clock input 1 -- -- ns P9 TDLY5 RB6 high time (minimum programming time) 100 -- -- s P10 TDLY6 RB6 low time after programming (high voltage discharge time) 100 -- -- ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25xC unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. DS39028A-page 3-133 PIC18CXXX NOTES: DS39028A-page 3-134 2000 Microchip Technology Inc. PIC16F62X In-Circuit Serial Programming for PIC16F62X FLASH MCUs This document includes the programming specifications for the following devices: 1.0 PDIP, SOIC PIC16F627 PIC16F628 PIC16LF627 PIC16LF628 RA2/AN2/VREF *1 18 RA1/AN1 RA3/AN3/CMP1 2 17 RA0/AN0 RA4/T0CKI/CMP2 3 16 RA7/OSC1/CLKIN RA5/MCLR/THV 4 15 RA6/OSC2/CLKOUT VSS 5 RB0/INT 6 RB1/RX/DT RB2/TX/CK RB3/CCP1 PROGRAMMING THE PIC16F62X The PIC16F62X is programmed using a serial method. The serial mode will allow the PIC16F62X to be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16F62X devices in all packages. PIC16F62X devices may be programmed using a single +5 volt supply (low voltage programming mode). VDD 13 RB7/T1OSI 7 12 RB6/T1OSO/T1CKI 8 11 RB5 9 10 RB4/PGM *1 20 RA1/AN1 RA3/AN3/CMP1 2 19 RA0/AN0 RA4/T0CKI/CMP2 3 18 RA7/OSC1/CLKIN RA5/MCLR/THV 4 17 RA6/OSC2/CLKOUT VSS 5 16 VDD VSS 6 RB0/INT 7 14 RB7/T1OSI RB1/RX/DT 8 13 RB6/T1OSO/T1CKI RB2/TX/CK 9 12 RB5 RB3/CCP1 10 11 RB4/PGM Hardware Requirements The PIC16F62X requires one programmable power supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V or VPP of (4.5V to 5.5V) when using low voltage. Both supplies should have a minimum resolution of 0.25V. 1.2 14 Programming Mode PIC16F62X 1.1 RA2/AN2/VREF PIC16F62X * * * * PIN Diagram VDD 15 The programming mode for the PIC16F62X allows programming of user program memory, data memory, special locations used for ID, and the configuration word. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F62X During Programming Pin Name Function Pin Type Pin Description RB4 PGM I Low voltage programming input if configuration bit equals 1 RB6 CLOCK I Clock input RB7 DATA I/O Data input/output MCLR VTEST MODE P* Program Mode Select VDD VDD P Power Supply VSS VSS P Ground Legend: I = Input, O = Output, P = Power *In the PIC16F62X, the programming high voltage is internally generated. To activate the programming mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current. 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-135 PIC16F62X 2.0 PROGRAM MODE ENTRY 2.2 2.1 User Program Memory Map A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in an unscrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where `bbbb' is ID information. The user memory space extends from 0x0000 to 0x7FFF. In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x7FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x7FFF and wrap to 0x000, 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a `1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode as described in Section 2.3. ID Locations In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 3-1. In the configuration memory space, 0x2000-0x200F are physically implemented. However, only locations 0x2000 through 0x2007 are available. Other locations are reserved. Locations beyond 0x200F will physically access user memory. (See Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAPPING 1 KW 2 KW 0x1FF 2000 ID Location 2001 2002 2003 2004 2005 2006 ID Location Implemented Implemented Implemented 1FFF 2000 2008 ID Location ID Location Reserved Not Implemented Reserved Reserved 2007 Configuration Word DS30034A-page 3-136 Implemented 3FFF Preliminary 2000 Microchip Technology Inc. PIC16F62X 2.3 2.3.2 Program/Verify Mode The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage) or by applying VDD to MCLR and raising RB3 from VIL to VDD. Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 and RB7 are Schmitt Trigger Inputs in this mode. Note: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). The normal sequence for programming is to use the load data command to set a value to be written at the selected address. Issue the begin programming command followed by read data command to verify, and then increment the address. SERIAL PROGRAM/VERIFY OPERATION The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specifications) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. A device reset will clear the PC and set the address to 0. The "increment address" command will increment the PC. The "load configuration" command will se the PC to 0x2000. The available commands are shown in Table 2-1. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). 2.3.1 The commands that are available are: LOW-VOLTAGE PROGRAMMING MODE When LVP bit is set to `1', the low-voltage programming entry is enabled. Since the LVP configuration bit allows low voltage programming entry in its erased state, an erased device will have the LVP bit enabled at the factory. While LVP is `1', RB4 is dedicated to low voltage programming. Bring MCLR to VDD and then RB4 to VDD to enter programming mode. All other specifications for high-voltage ICSPTM apply. To disable low voltage mode, the LVP bit must be programmed to `0'. This must be done while entered with high voltage entry mode (LVP bit= 1). RB4 is now a general purpose I/O pin. 2000 Microchip Technology Inc. 2.3.2.1 LOAD CONFIGURATION After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits in a "data word," as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). Preliminary DS30034A-page 3-137 PIC16F62X 2.3.2.2 LOAD DATA FOR PROGRAM MEMORY After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. TABLE 2-1: COMMAND MAPPING FOR PIC16F627/PIC16F628 Command Mapping (MSB ... LSB) Data Load Configuration X X 0 0 0 0 0, data (14), 0 Load Data for Program Memory X X 0 0 1 0 0, data (14), 0 0, data (14), 0 Read Data from Program Memory X X 0 1 0 0 Increment Address X X 0 1 1 0 Begin Erase Programming Cycle 0 0 1 0 0 0 Begin Programming Only Cycle 0 1 1 0 0 0 Load Data for Data Memory X X 0 0 1 1 0, data (14), 0 Read Data from Data Memory X X 0 1 0 1 0, data (14), 0 Bulk Erase Program Memory X X 1 0 0 1 Bulk Erase Data Memory X X 1 0 1 1 DS30034A-page 3-138 Preliminary 2000 Microchip Technology Inc. PIC16F62X FIGURE 2-2: PROGRAM FLOW CHART - PIC16F62X PROGRAM MEMORY Start Set VDD = VDDP Program Cycle PROGRAM CYCLE Read Data Command Data Correct? Increment Address Command No Load Data Command No Report Programming Failure All Locations Done? Begin Programming Command Wait 2 ms Verify all Locations @ VDDMIN Report Verify Error @ VDDMIN No Data Correct? Verify all Locations @ VDDMAX Report Verify Error @ VDDMAX No Data Correct? Done 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-139 PIC16F62X FIGURE 2-3: PROGRAM FLOW CHART - PIC16F62X CONFIGURATION MEMORY Start Load Configuration Data No Program ID Location? Yes Read Data Command Program Cycle Report Programming Failure Increment Address Command No Data Correct? Yes No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command Report Program Configuration Word Error No Program Cycle (Config. Word) Set VDD = VDDMAX Data Correct? Read Data Command Yes Set VDD = VDDMAX No Yes Done DS30034A-page 3-140 Data Correct? Preliminary Read Data Command 2000 Microchip Technology Inc. PIC16F62X 2.3.2.3 LOAD DATA FOR DATA MEMORY 2.3.2.8 After receiving this command, the chip will load in a 14bit "data word" when 16 cycles are applied. However, the data memory is only 8-bits wide, and thus only the first 8-bits of data after the start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly. The data memory contains 64 words. Only the lower 8-bits of the PC are decoded by the data memory, and therefore if the PC is greater than 0x3F, it will wrap around and address a location within the physically implemented memory. If the device is code protected, the data is read as all zeros. 2.3.2.4 READ DATA FROM PROGRAM MEMORY 2.3.2.5 A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes a write. The user must allow for program cycle time for programming to complete. No "end programming" command is required. This command is similar to the ERASE/PROGRAM CYCLE command, except that a word erase is not done. It is recommended that a bulk erase be performed before starting a series of programming only cycles. 2.3.2.9 After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. READ DATA FROM DATA MEMORY After receiving this command, the chip will transmit data bits out of the data memory starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8bits wide, and therefore, only the first 8-bits that are output are actual data. To perform a bulk erase of the program memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase User Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. If the address is pointing to the test program memory (0x2000 - 0x200F), then both the user memory and the test memory will be erased. The configuration word will not be erased, even if the address is pointing to location 0x2007. Note: If the device is code-protected, the BULK ERASE command will not work. BULK ERASE DATA MEMORY INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.2.7 BULK ERASE PROGRAM MEMORY After this command is performed, the next program command will erase the entire program memory. 2.3.2.10 2.3.2.6 BEGIN PROGRAMMING BEGIN ERASE/PROGRAM CYCLE A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes an erase before write. The user must allow for both erase and programming cycle times for programming to complete. No "end programming" command is required. 2000 Microchip Technology Inc. To perform a bulk erase of the data memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase Data Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. Note: Preliminary All BULK ERASE operations must take place at 4.5 to 5.5 VDD range. DS30034A-page 3-141 PIC16F62X 2.4 Programming Algorithm Requires Variable VDD The PIC16F62X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin. as well as VDDmax. Verification at VDDmin. guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (See Table 5-1). VDDP = VCC range required during programming. VDDmin. = minimum operating VDD spec for the part. VDDmax.= maximum operating VDD spec for the part. Programmers must verify the PIC16F62X at its specified VDD max. and VDDmin levels. Since Microchip may introduce future versions of the PIC16F62X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. DS30034A-page 3-142 Preliminary 2000 Microchip Technology Inc. PIC16F62X 3.0 CONFIGURATION WORD TABLE 3-1: The PIC16F62X has several configuration bits. These bits can be set (reads `0') or left unchanged (reads `1') to select various device configurations. 3.1 Device ID Value Device PIC16F627 PIC16F628 Device ID Word Dev Rev 00 0111 111 00 0111 001 x xxxx x xxxx The device ID word for the PIC16F62X is located at 2006h. FIGURE 3-1: CP1 CONFIGURATION WORD FOR PIC16F877/876/873 CP0 CP1 CP0 - CPD LVP BODEN MCLRE FOSC2 PWRTE WDTE bit13 F0SC1 F0SC0 bit0 Register: Address CONFIG 2007h bit 13-10: CP1:CP0: Code Protection bits (2) Code protection for 2K program memory 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFhcode protected Code protection for 1K program memory 11 = Program memory code protection off 10 = Program memory code protection off 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected bit 8: CPD: Data Code Protection bit(3) 1 = Data memory code protection off 0 = Data memory code protected bit 7: LVP: Low Voltage Programming Enable 1 = RB4/PGM pin has PGM function, low voltage programming enabled 0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming bit 6: BODEN: Brown-out Detect Reset Enable bit (1) 1 = BOD reset enabled 0 = BOD reset disabled bit 5: MCLRE: RA5/MCLR pin function select 1 = RA5/MCLR pin function is MCLR 0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 4,1-0: FOSC2:FOSC0: Oscillator Selection bits(4) 111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN 110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN 101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 = EXTCLK: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. The entire program EEPROM will be erased if the code protection is reduced. 3: The entire data EEPROM will be erased when the code protection is turned off. The calibration space in the test memory is not erased. 4: When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled. 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-143 PIC16F62X 4.0 CODE PROTECTION Procedure to disable code protect: For PIC16F62X devices, once code protection is enabled, all program memory locations read all 0's. The ID locations and the configuration word read out in an unscrambled fashion. Further programming is disabled for the entire program memory as well as data memory. It is possible to program the ID locations and the configuration word. 4.1 Disabling Code-Protection It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (code protect bit = 1) using this procedure; however, all data within the program memory and the data memory will be erased when this procedure is executed, and thus, the security of the data or code is not compromised. 4.2 a) b) c) d) e) f) g) h) Execute load configuration (with a `1' in bit 4, code protect). Increment to configuration word location (0x2007) Execute command (000001) Execute command (000111) Execute `Begin Programming' (001000) Wait 10 ms Execute command (000001) Execute command (000111) Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F62X, the EEPROM data memory should also be embedded in the hex file (see Section 5.1). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. DS30034A-page 3-144 Preliminary 2000 Microchip Technology Inc. PIC16F62X 4.3 CHECKSUM COMPUTATION 4.3.1 CHECKSUM The least significant 16 bits of this sum is the checksum. Checksum is calculated by reading the contents of the PIC16F62X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16F62X. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F62X devices is shown in Table 4-1. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) TABLE 4-1: Device PIC16F627 The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect OFF 0x200 : 0x3FF Checksum* OFF 0x25E6 at 0 and max address SUM[0x0000:0x3FFF] + CFGW & 0x3DFF 0x39FF 0x05CD SUM[0x0000:0x01FF] + CFGW & 0x3DFF + SUM_ID 0x4DFE 0xFFB3 0x3BFE 0x07CC 0x35FF 0x01CD ALL PIC16F628 Blank Value SUM[0x0000:0x07FF] + CFGW & 0x3DFF 0x400 : 0xFFF SUM[0x0000:0x03FF] + CFGW & 0x3DFF +SUM_ID 0x5BFE 0x0DB3 0x200 : 0x7FF SUM[0x0000:0x01FF] + CFGW & 0x3DFF + SUM_ID 0x49FE 0xFBB3 CFGW & 0x3DFF + SUM_ID 0x37FE 0x03CC ALL Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234 *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-145 PIC16F62X 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS 5.1 Embedding Data EEPROM Contents in Hex File The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write data EEPROM contents to a hex file along with program memory information and fuse information. The 64 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage is one data byte per address location, LSB aligned. TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature: Operating Voltage: 0C TA +70C 4.5V VDD 5.5V Characteristics Sym Min VDD level for word operations, program memory VDD VDD level for word operations, data memory VDD level for bulk erase/write operations, program and data memory Typ Max Units 2.0 5.5 V VDD 2.0 5.5 V VDD 4.5 5.5 V VIHH VDD + 3.5 13.5 V 1.0 s Conditions/Comments General High voltage on MCLR and RA4/T0CKI for test-mode entry MCLR rise time (VSS to VHH) for test mode entry tVHHR (RB6, RB7) input high level VIH1 0.8VDD V Schmitt Trigger input (RB6, RB7) input low level VIL1 0.2VDD V Schmitt Trigger input RB<7:4> setup time before MCLR (test mode selection pattern setup time) tset0 100 ns RB<7:4> hold time after MCLR (test mode selection pattern setup time) thld0 5 s Data in setup time before clock tset1 100 ns Data in hold time after clock thld1 100 ns Data input not driven to next clock input (delay required between command/data or command/command) tdly1 1.0 s Delay between clock to clock of next command or data tdly2 1.0 s Clock to data out valid (during read data) tdly3 80 ns Data in setup time before clock tset0 1.0 s Data in hold time after clock thld0 1.0 s RB6 and RB7 setup time before clock tset1 1.0 s RB6 and RB7 hold time after clock thld1 1.0 s RA4/T0CKI (clock) to (clock) tdly4 2.0 s RB7 (data/command select input) setup before RA4/T0CKI (clock) tset2 1.0 s RB7 (data/command select input) hold time after RA4/T0CKI (clock) thld2 1.0 s RA4/T0CKI (clock) to data out valid tdly5 1.0 s RB6 (hi/lo select) valid to data out valid tdly6 1.0 Erase cycle time tera Programming cycle time tprog Serial Program/Verify Parallel Program/Verify Time delay from program to compare (HV discharge time) DS30034A-page 3-146 tdis s 2 5 ms 2 5 ms 0.5 Preliminary s 2000 Microchip Technology Inc. PIC16F62X FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR 1s min. tset0 RB6 (CLOCK) 1 2 3 4 5 6 1 tdly2 2 3 4 5 15 16 thld0 RB7 (DATA) 1 0 0 0 X tset1 strt_bit X stp_bit tset1 tdly1 1s min. thld1 } } } } thld1 100ns min. 100ns min. Program/Verify Test Mode Reset FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR tset0 tdly2 thld0 1s min. 1 2 3 4 5 1 0 1 6 2 3 RB6 (CLOCK) 4 5 15 16 tdly3 RB7 (DATA) 0 1 X X stp_bit strt_bit tdly1 tset1 thld1 1s min. } } 100ns min. RB7 = input RB7 = output RB7 input Program/Verify Test Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR tdly2 Next Command 1s min. 1 2 3 4 5 1 6 2 RB6 (CLOCK) RB7 (DATA) 0 1 1 0 X tset1 X X 0 tdly1 thld1 } } 1s min. 100ns min. Reset 2000 Microchip Technology Inc. Program/Verify Test Mode Preliminary DS30034A-page 3-147 PIC16F62X NOTES: DS30034A-page 3-148 Preliminary 2000 Microchip Technology Inc. PIC16F8X In-Circuit Serial Programming for PIC16F8X FLASH MCUs This document includes the programming specifications for the following devices: 1.0 PDIP, SOIC PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 PIC16F84A PIC16F877 RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3 PROGRAMMING THE PIC16F8X The PIC16F8X is programmed using a serial method. The serial mode will allow the PIC16F8X to be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16F8X devices in all packages. 1.1 MCLR/VPP RA0/AN0 39 38 4 37 RA3/AN3/VREF 5 36 RA4/T0CKI 6 7 35 34 RB2 33 RB0/INT VDD RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD Programming Mode 9 10 11 32 31 RB7 RB6 RB5 RB4 RB3 RB1 VSS 30 RD7/PSP7 29 28 14 27 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2 16 17 25 24 RC6/TX/CK 18 23 19 20 22 21 RC4/SDI/SDA RD3/PSP3 OSC1/CLKIN OSC2/CLKOUT The programming mode for the PIC16F8X allows programming of user program memory, data memory, special locations used for ID, and the configuration word. 8 PIC16F877 40 VSS 1.2 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 2 3 RA5/AN4/SS The PIC16F8X requires one programmable power supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V. Both supplies should have a minimum resolution of 0.25V. 18 17 16 15 14 13 12 11 10 1 RA1/AN1 RA2/AN2/VREF Hardware Requirements *1 2 3 4 5 6 7 8 9 PIC16F8X * * * * * * Pin Diagram RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 12 13 RC5/SDO RD2/PSP2 PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F8X During Programming Pin Name Function Pin Type Pin Description RB6 CLOCK I RB7 DATA I/O MCLR VTEST MODE P* Program Mode Select VDD VDD P Power Supply VSS VSS P Ground Clock input Data input/output Legend: I = Input, O = Output, P = Power *In the PIC16F8X, the programming high voltage is internally generated. To activate the programming mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current. 2000 Microchip Technology Inc. DS30262C-page 3-149 PIC16F8X 2.0 PROGRAM MODE ENTRY 2.2 2.1 User Program Memory Map A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in an unscrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where `bbbb' is ID information. The user memory space extends from 0x0000 to 0x1FFF (8K), of which 1K (0x0000 - 0x03FF) is physically implemented. In actual implementation the onchip user program memory is accessed by the lower 10-bits of the PC, with the upper 3-bits of the PC ignored. Therefore if the PC is greater than 0x3FF, it will wrap around and address a location within the physically implemented memory. (See Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a `1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode as described in Section 2.3. ID Locations In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-2. To understand the scrambling mechanism after code protection, refer to Section 4.0. In the configuration memory space, 0x2000-0x200F are physically implemented. However, only locations 0x2000 through 0x2007 are available. Other locations are reserved. Locations beyond 0x200F will physically access user memory. (See Figure 2-1). DS30262C-page 3-150 2000 Microchip Technology Inc. PIC16F8X FIGURE 2-1: PROGRAM MEMORY MAPPING 0.5 KW 0 1FF 3FF 400 Implemented 1 KW 8 KW Implemented Not Implemented Not Implemented Implemented Implemented Implemented Implemented Not Implemented Not Implemented 1FFF 2000 2000 ID Location 2001 ID Location 2002 ID Location 2003 ID Location 2004 Reserved 2005 Reserved 2006 Reserved 2007 Configuration Word 2000 Microchip Technology Inc. 2008 Not Implemented 3FFF DS30262C-page 3-151 PIC16F8X 2.3 Program/Verify Mode The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 and RB7 are Schmitt Trigger Inputs in this mode. Note: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). The normal sequence for programming is to use the load data command to set a value to be written at the selected address. Issue the begin programming command followed by read data command to verify, and then increment the address. 2.3.1 SERIAL PROGRAM/VERIFY OPERATION The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specifications) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. DS30262C-page 3-152 Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). The commands that are available are: 2.3.1.1 LOAD CONFIGURATION After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits in a "data word," as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). 2000 Microchip Technology Inc. PIC16F8X 2.3.1.2 LOAD DATA FOR PROGRAM MEMORY After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. TABLE 2-1: COMMAND MAPPING FOR PIC16F83/CR83/F84/CR84 Command Mapping (MSB ... LSB) Data Load Configuration 0 0 0 0 0 0 0, data (14), 0 Load Data for Program Memory 0 0 0 0 1 0 0, data (14), 0 0, data (14), 0 Read Data from Program Memory 0 0 0 1 0 0 Increment Address 0 0 0 1 1 0 Begin Programming 0 0 1 0 0 0 Load Data for Data Memory 0 0 0 0 1 1 0, data (14), 0 Read Data from Data Memory 0 0 0 1 0 1 0, data (14), 0 Bulk Erase Program Memory 0 0 1 0 0 1 Bulk Erase Data Memory 0 0 1 0 1 1 TABLE 2-2: COMMAND MAPPING FOR PIC16F84A/PIC16F877 Command Mapping (MSB ... LSB) Data Load Configuration X X 0 0 0 0 0, data (14), 0 Load Data for Program Memory X X 0 0 1 0 0, data (14), 0 Read Data from Program Memory X X 0 1 0 0 0, data (14), 0 Increment Address X X 0 1 1 0 Begin Erase Programming Cycle 0 0 1 0 0 0 Begin Programming Only Cycle 0 1 1 0 0 0 Load Data for Data Memory X X 0 0 1 1 0, data (14), 0 Read Data from Data Memory X X 0 1 0 1 0, data (14), 0 Bulk Erase Program Memory X X 1 0 0 1 Bulk Erase Data Memory X X 1 0 1 1 2000 Microchip Technology Inc. DS30262C-page 3-153 PIC16F8X FIGURE 2-2: PROGRAM FLOW CHART - PIC16F8X PROGRAM MEMORY Start Set VDD = VDDP Program Cycle PROGRAM CYCLE Read Data Command Data Correct? Increment Address Command No All Locations Done? Load Data Command No Report Programming Failure Begin Programming Command Wait 10 ms Verify all Locations @ VDDMIN Report Verify Error @ VDDMIN No Data Correct? Verify all Locations @ VDDMAX Report Verify Error @ VDDMAX No Data Correct? Done DS30262C-page 3-154 2000 Microchip Technology Inc. PIC16F8X FIGURE 2-3: PROGRAM FLOW CHART - PIC16F8X CONFIGURATION MEMORY Start Load Configuration Data No Program ID Location? Yes Read Data Command Program Cycle Report Programming Failure Increment Address Command No Data Correct? Yes No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command Report Program Configuration Word Error No Program Cycle (Config. Word) Set VDD = VDDMAX Data Correct? Read Data Command Yes Set VDD = VDDMAX No Yes Done 2000 Microchip Technology Inc. Data Correct? Read Data Command DS30262C-page 3-155 PIC16F8X 2.3.1.3 LOAD DATA FOR DATA MEMORY After receiving this command, the chip will load in a 14bit "data word" when 16 cycles are applied. However, the data memory is only 8-bits wide, and thus only the first 8-bits of data after the start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly. The data memory contains 64 words. Only the lower 8-bits of the PC are decoded by the data memory, and therefore if the PC is greater than 0x3F, it will wrap around and address a location within the physically implemented memory. 2.3.1.4 READ DATA FROM PROGRAM MEMORY After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.3.1.5 READ DATA FROM DATA MEMORY After receiving this command, the chip will transmit data bits out of the data memory starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8bits wide, and therefore, only the first 8-bits that are output are actual data. 2.3.1.6 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.1.7 BEGIN ERASE/PROGRAM CYCLE A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes an erase before write. The user must allow for both erase and programming cycle times for programming to complete. No "end programming" command is required. DS30262C-page 3-156 2.3.1.8 BEGIN PROGRAMMING A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes a write. The user must allow for program cycle time for programming to complete. No "end programming" command is required. This command is similar to the ERASE/PROGRAM CYCLE command, except that a word erase is not done. It is recommended that a bulk erase be performed before starting a series of programming only cycles. 2.3.1.9 BULK ERASE PROGRAM MEMORY After this command is performed, the next program command will erase the entire program memory. To perform a bulk erase of the program memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase User Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. If the address is pointing to the test program memory (0x2000 - 0x200F), then both the user memory and the test memory will be erased. The configuration word will not be erased, even if the address is pointing to location 0x2007 For PIC16F84 perform the following commands: 1. 2. 3. 4. 5. 6. 7. 8. Issue Command 2 (write program memory). Send out 3FFFH data. Issue Command 1 (toggle select even rows). Issue Command 7 (toggle select even rows). Issue Command 8 (begin programming) Delay 10 ms Issue Command 1 (toggle select even rows). Issue Command 7 (toggle select even rows). Note: If the device is code-protected (PIC16F84A), the BULK ERASE command will not work. 2000 Microchip Technology Inc. PIC16F8X 2.3.1.10 BULK ERASE DATA MEMORY To perform a bulk erase of the data memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase Data Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. For PIC16F84 perform the data memory). 5. 6. 7. 8. 9. 10. Send out 3FFFH data. Issue Command 1 (toggle select even rows). Issue Command 7 (toggle select even rows). Issue Command 8 (begin data) Delay 10 ms Issue Command 1 (toggle select even rows). Issue Command 7 (toggle select even rows). Note: All BULK ERASE operations must take place at 4.5 to 5.5 VDD range. 2000 Microchip Technology Inc. 2.4 Programming Algorithm Requires Variable VDD The PIC16F8X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin. as well as VDDmax. Verification at VDDmin. guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (See Table 5-1). VDDP = VCC range required during programming. VDDmin. = minimum operating VDD spec for the part. VDDmax.= maximum operating VDD spec for the part. Programmers must verify the PIC16F8X at its specified VDD max. and VDDmin levels. Since Microchip may introduce future versions of the PIC16F8X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. DS30262C-page 3-157 PIC16F8X 3.0 CONFIGURATION WORD 3.1 The PIC16F8X has five configuration bits. These bits can be set (reads `0') or left unchanged (reads `1') to select various device configurations. Device ID Word The device ID word for the PIC16F8XX is located at 2006h. TABLE 3-1: Device ID Value Device Dev FIGURE 3-1: Rev PIC16F84A 00 0101 010 0 0000 PIC16F877 00 1001 101 0 0000 CONFIGURATION WORD BIT MAP FOR PIC16F83/CR83/F84/CR84/F84A Bit Number: PIC16F83/ F84/F84A 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP CP CP CP CP CP CP CP CP CP PWRTE WDTE FOSC1 FOSC0 PIC16CR83/ CR84 CP CP CP CP CP CP DP CP CP CP PWRTE WDTE FOSC1 FOSC0 bit 4-13: CP, Code Protection Configuration Bits 1 = code protection off 0 = code protection on bit 7: PIC16CR83/CR84 only DP, Data Memory Code Protection Bit 1 = code protection off 0 = data memory is code protected bit 3: PWRTE, Power Up Timer Enable Configuration Bit 1 = Power up timer disabled 0 = Power up timer enabled bit 2: WDTE, WDT Enable Configuration Bits 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC<1:0>, Oscillator Selection Configuration Bits 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator DS30262C-page 3-158 2000 Microchip Technology Inc. PIC16F8X FIGURE 3-2: CP1 CONFIGURATION WORD FOR PIC16F877 CP0 BKBUG - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 Register: Address CONFIG 2007h bit 13-12: bit 11: BKBUG: Background Debugger Mode (This bit documented as reserved in data sheet) 1 = Background debugger functions not enabled 0 = Background debugger functional. bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2) 11 = Code protection off 10 = 1F00h to 1FFFh code protected 01 = 1000h to 1FFFh code protected 00 = 0000h to 1FFFh code protected bit 11: Reserved: Set to `1' for normal operation bit 10: Unimplemented: Read as `1' bit 9: WRT: Flash Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control bit 8: CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EE memory code protected bit 7: LVP: Low voltage programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. DS30262C-page 3-159 PIC16F8X 4.0 CODE PROTECTION Procedure to disable code protect: For PIC16F8X devices, once code protection is enabled, all program memory locations read all 0's. The ID locations and the configuration word read out in an unscrambled fashion. Further programming is disabled for the entire program memory as well as data memory. It is possible to program the ID locations and the configuration word. 4.1 Disabling Code-Protection It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (code protect bit = 1) using this procedure; however, all data within the program memory and the data memory will be erased when this procedure is executed, and thus, the security of the data or code is not compromised. 4.2 a) b) c) d) e) f) g) h) Execute load configuration (with a `1' in bit 4, code protect). Increment to configuration word location (0x2007) Execute command (000001) Execute command (000111) Execute `Begin Programming' (001000) Wait 10 ms Execute command (000001) Execute command (000111) Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F8X, the EEPROM data memory should also be embedded in the hex file (see Section 5.1). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: CONFIGURATION WORD PIC16F83 To code protect: 0000000000XXXX Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled All memory Read All 0's, Write Disabled Read Unscrambled, Write Enabled ID Locations [0x2000 : 0x2003] Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC16CR83 To code protect: 0000000000XXXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] DS30262C-page 3-160 R/W in Protected Mode Read Unscrambled Read All 0's for Program Memory, Read All 1's for Data Memory Write Disabled Read Unscrambled R/W in Unprotected Mode Read Unscrambled Read Unscrambled, Data Memory Write Enabled Read Unscrambled 2000 Microchip Technology Inc. PIC16F8X PIC16CR84 To code protect: 0000000000XXXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] R/W in Protected Mode Read Unscrambled Read All 0's for Program Memory, Read All 1's for Data Memory Write Disabled Read Unscrambled R/W in Unprotected Mode Read Unscrambled Read Unscrambled, Data Memory Write Enabled Read Unscrambled PIC16F84 To code protect: 0000000000XXXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC16F84A To code protect: 0000000000XXXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC16F8XX To code protect: 00X1XXXX00XXXX Program Memory Segment Configuration Word (0x2007) All memory ID Locations [0x2000 : 0x2003] R/W in Protected Mode Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Legend: X = Don't care 2000 Microchip Technology Inc. DS30262C-page 3-161 PIC16F8X 4.3 CHECKSUM COMPUTATION 4.3.1 CHECKSUM The least significant 16 bits of this sum is the checksum. Checksum is calculated by reading the contents of the PIC16F8X memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16F8X. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F8X devices is shown in Table 4-2. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) TABLE 4-2: Device The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16F83 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID 0x3DFF 0x3E0E 0x09CD 0x09DC PIC16CR83 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID 0x3DFF 0x3E0E 0x09CD 0x09DC PIC16F84 OFF ON SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID 0x3BFF 0x3C0E 0x07CD 0x07DC PIC16CR84 OFF ON SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID 0x3BFF 0x3C0E 0x07CD 0x07DC PIC16F84A OFF ON SUM[0x000:0x3FF] + CFGW & 0x3FFF CFGW & 0x3FFF + SUM_ID 0x3BFF 0x3C0E 0x07CD 0x07DC OFF PIC16F877 SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD 0X1F00 SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID - 0X1FFF 0x28EE 0xDAA3 0x1000 - 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993 CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C ALL Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234 *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS30262C-page 3-162 2000 Microchip Technology Inc. PIC16F8X 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS 5.1 Embedding Data EEPROM Contents in Hex File The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write data EEPROM contents to a hex file along with program memory information and fuse information. The 64 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage is one data byte per address location, LSB aligned. TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: Operating Voltage: Paramet er No. +10C TA +40C, unless otherwise stated, (25C is recommended) 4.5V VDD 5.5V, unless otherwise stated. Sym. Characteristic VDDP Supply voltage during programming VDDV Supply voltage during verify VIHH High voltage on MCLR for test mode entry IDDP Supply current (from VDD) during program/verify Conditions/ Comments Min. Typ. Max. Units 4.5 5.0 5.5 V VDDmin VDDmax V Note 1 12 14.0 V Note 2 50 mA 200 A IHH Supply current from VIHH (on MCLR) VIH1 (RB6, RB7) input high level 0.8 VDD V Schmitt Trigger input VIL1 (RB6, RB7) input low level MCLR (test mode selection) 0.2 VDD V Schmitt Trigger input 8.0 s P1 TvHHR MCLR rise time (VSS to VHH) for test mode entry P2 Tset0 RB6, RB7 setup time (before pattern setup time) 100 ns P3 Tset1 Data in setup time before clock 100 ns P4 Thld1 Data in hold time after clock 100 ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 s P6 Tdly2 Delay between clock to clock of next command or data 1.0 s P7 Tdly3 Clock to data out valid (during read data) 80 ns P8 Thld0 RB <7:6> hold time after MCLR 100 - - Erase cycle time - - 10 ms - - Program cycle time - - 10 ms ns Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS30262C-page 3-163 PIC16F8X FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR 100ns P2 1 P6 2 P8 RB6 (CLOCK) RB7 (DATA) 0 1 3 4 5 100ns 0 0 0 2 1s min. 1 6 4 5 15 0 0 0 P5 P3 P3 1s min. P4 P4 } } } } 100ns min. Program/Verify Test Mode Reset FIGURE 5-2: 3 100ns min. READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR 100ns P2 1 RB6 (CLOCK) P6 2 3 4 5 100ns 1 0 0 P8 RB7 (DATA) 0 0 2 1s min. 1 6 3 4 5 15 P7 0 P5 P3 P4 1s min. } } 100ns min. RB7 input RB7 = output Program/Verify Test Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR P6 1 2 0 1 3 4 5 6 0 0 0 Next Command 1s min. 1 2 RB6 (CLOCK) RB7 (DATA) 1 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Test Mode Reset DS30262C-page 3-164 2000 Microchip Technology Inc. PIC16F8XX In-Circuit Serial Programming for PIC16F8XX FLASH MCUs This document includes the programming specifications for the following devices: * PIC16F874 * PIC16F871 * PIC16F876 * PIC16F872 * PIC16F877 PDIP, SOIC MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL * PIC16F873 1.0 PROGRAMMING THE PIC16F8XX The PIC16F8XX is programmed using a serial method. The serial mode will allow the PIC16F8XX to be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16F8XX devices in all packages. PIC16F8XX devices may be programmed using a single +5 volt supply (low voltage programming mode). Hardware Requirements 1.2 40 39 RB7 RB6 RA1/AN1 RA2/AN2/VREF 3 38 RB5 4 37 RA3/AN3/VREF RA4/T0CKI 5 6 36 35 RB4 RB3 RB2 RA5/AN4/SS 7 8 34 33 RB1 RB0/INT 32 31 VDD 30 29 28 RD7/PSP7 RD6/PSP6 RD5/PSP5 27 RD4/PSP4 26 25 RC7/RX/DT RC6/TX/CK 24 23 RC5/SDO RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN Programming Mode 9 10 11 12 13 OSC2/CLKOUT 14 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 15 16 RC2/CCP1 17 18 RC3/SCK/SCL RD0/PSP0 The programming mode for the PIC16F8XX allows programming of user program memory, data memory, special locations used for ID, and the configuration word. RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 1 2 RE0/RD/AN5 The PIC16F8XX requires one programmable power supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V or VPP of (4.5V to 5.5V) when using low voltage In-Circuit Serial ProgrammingTM (ICSPTM). Both supplies should have a minimum resolution of 0.25V. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP RA0/AN0 RD1/PSP1 19 20 PIC16F877/874/871 1.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16F876/873/872/870 * PIC16F870 Pin Diagram 22 21 VSS RC4/SDI/SDA RD3/PSP3 RD2/PSP2 PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F8XX During Programming Pin Name Function Pin Type Pin Description RB3 PGM I Low voltage ICSP programming input if configuration bit equals 1 RB6 CLOCK I Clock input RB7 DATA I/O MCLR VTEST MODE P* Program Mode Select VDD VDD P Power Supply VSS VSS P Ground Data input/output Legend: I = Input, O = Output, P = Power *In the PIC16F8XX, the programming high voltage is internally generated. To activate the programming mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current. In-circuit Serial Programming (ICSP) is a trademark of Microchip Technology Inc. 2000 Microchip Technology Inc. DS39025D-page 3-165 PIC16F8XX 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000, 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a `1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode as described in Section 2.3. In the configuration memory space, 0x2000-0x200F are physically implemented. However, only locations 0x2000 through 0x2007 are available. Other locations are reserved. Locations beyond 0x200F will physically access user memory. (See Figure 2-1). 2.2 ID Locations A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in an unscrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb" where `bbbb' is ID information. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.0. DS39025D-page 3-166 2000 Microchip Technology Inc. PIC16F8XX FIGURE 2-1: 2000h PROGRAM MEMORY MAPPING ID Location 2002h 2003h 2004h ID Location ID Location ID Location Reserved Reserved 2006h Device ID 8K words Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented 3FFh 400h 7FFh 800h BFFh C00h FFFh 1000h 2005h 4K words 0h 1FFh 2001h 2K words Reserved Implemented Reserved Implemented Implemented 2007h Configuration Word Implemented 1FFFh 2008h Reserved Reserved Reserved Reserved Reserved Reserved 2100h 3FFFh 2000 Microchip Technology Inc. DS39025D-page 3-167 PIC16F8XX 2.3 Program/Verify Mode The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VIL to VIHH (high voltage). In this mode, the state of the RB3 pin does not effect programming. Low-voltage ICSP programming mode is entered by applying VDD to MCLR and raising RB3 from VIL to VDD. Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 and RB7 are Schmitt Trigger Inputs in this mode. Note: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). The normal sequence for programming is to use the load data command to set a value to be written at the selected address. Issue the begin programming command followed by read data command to verify, and then increment the address. A device reset will clear the PC and set the address to 0. The "increment address" command will increment the PC. The "load configuration" command will se the PC to 0x2000. The available commands are shown in Table 2-1. 2.3.1 LOW-VOLTAGE ICSP PROGRAMMING MODE When LVP bit is set to `1', the low-voltage ICSP programming entry is enabled. Since the LVP configuration bit allows low voltage ICSP programming entry in its erased state, an erased device will have the LVP bit enabled at the factory. While LVP is `1', RB3 is dedicated to low voltage ICSP programming. Bring MCLR to VDD and then RB3 to VDD to enter programming mode. All other specifications for high-voltage ICSPTM apply. 2.3.2 SERIAL PROGRAM/VERIFY OPERATION The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specifications) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay, the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). The commands that are available are: 2.3.2.1 LOAD CONFIGURATION After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits in a "data word," as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). To disable low voltage ICSP mode, the LVP bit must be programmed to `0'. This must be done while entered with high voltage entry mode (LVP bit= 1). RB3 is now a general purpose I/O pin. DS39025D-page 3-168 2000 Microchip Technology Inc. PIC16F8XX 2.3.2.2 LOAD DATA FOR PROGRAM MEMORY After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. TABLE 2-1: COMMAND MAPPING FOR PIC16F84A/PIC16F877 Command Mapping (MSB ... LSB) Data Load Configuration X X 0 0 0 0 0, data (14), 0 Load Data for Program Memory X X 0 0 1 0 0, data (14), 0 0, data (14), 0 Read Data from Program Memory X X 0 1 0 0 Increment Address X X 0 1 1 0 Begin Erase Programming Cycle 0 0 1 0 0 0 Begin Programming Only Cycle 0 1 1 0 0 0 Load Data for Data Memory X X 0 0 1 1 0, data (14), 0 Read Data from Data Memory X X 0 1 0 1 0, data (14), 0 Bulk Erase Program Memory X X 1 0 0 1 Bulk Erase Data Memory X X 1 0 1 1 2000 Microchip Technology Inc. DS39025D-page 3-169 PIC16F8XX FIGURE 2-2: PROGRAM FLOW CHART - PIC16F8XX PROGRAM MEMORY Start Set VDD = VDDP Program Cycle PROGRAM CYCLE Read Data Command Data Correct? Increment Address Command No All Locations Done? Load Data Command No Report Programming Failure Begin Programming Command Wait tprog Verify all Locations @ VDDMIN Report Verify Error @ VDDMIN No Data Correct? Verify all Locations @ VDDMAX Report Verify Error @ VDDMAX No Data Correct? Done DS39025D-page 3-170 2000 Microchip Technology Inc. PIC16F8XX FIGURE 2-3: PROGRAM FLOW CHART - PIC16F8XX CONFIGURATION MEMORY Start Load Configuration Data No Program ID Location? Yes Read Data Command Program Cycle Report Programming Failure Increment Address Command No Data Correct? Yes No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command Report Program Configutation Word Error No Program Cycle (Config. Word) Set VDD = VDDMAX Data Correct? Read Data Command Yes Set VDD = VDDMAX No Yes Done 2000 Microchip Technology Inc. Data Correct? Read Data Command DS39025D-page 3-171 PIC16F8XX 2.3.2.3 LOAD DATA FOR DATA MEMORY After receiving this command, the chip will load in a 14bit "data word" when 16 cycles are applied. However, the data memory is only 8-bits wide, and thus only the first 8-bits of data after the start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly. The data memory contains 64 words. Only the lower 8-bits of the PC are decoded by the data memory, and therefore if the PC is greater than 0x3F, it will wrap around and address a location within the physically implemented memory. If the device is code protected, the data is read as all zeros. 2.3.2.4 READ DATA FROM PROGRAM MEMORY After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.3.2.5 READ DATA FROM DATA MEMORY After receiving this command, the chip will transmit data bits out of the data memory starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8bits wide, and therefore, only the first 8-bits that are output are actual data. 2.3.2.8 A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes a write. The user must allow for program cycle time for programming to complete. No "end programming" command is required. This command is similar to the ERASE/PROGRAM CYCLE command, except that a word erase is not done. It is recommended that a bulk erase be performed before starting a series of programming only cycles. 2.3.2.9 To perform a bulk erase of the program memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase Program Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. If the address is pointing to the test program memory (0x2000 - 0x200F), then both the user memory and the test memory will be erased. The configuration word will not be erased, even if the address is pointing to location 0x2007. Note: If the device is code-protected, the BULK ERASE command will not work. BULK ERASE DATA MEMORY INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.3.2.7 BULK ERASE PROGRAM MEMORY After this command is performed, the next program command will erase the entire program memory. 2.3.2.10 2.3.2.6 BEGIN PROGRAMMING BEGIN ERASE/PROGRAM CYCLE A load command must be given before every begin programming command. Programming of the appropriate memory (test program memory, user program memory or data memory) will begin after this command is received and decoded. An internal timing mechanism executes an erase before write. The user must allow for both erase and programming cycle times for programming to complete. No "end programming" command is required. DS39025D-page 3-172 To perform a bulk erase of the data memory, the following sequence must be performed. 1. 2. 3. 4. Do a "Load Data All 1's" command. Do a "Bulk Erase Data Memory" command. Do a "Begin Programming" command. Wait 10 ms to complete bulk erase. Note: All BULK ERASE operations must take place at 4.5 to 5.5 VDD range. 2000 Microchip Technology Inc. PIC16F8XX 2.4 Programming Algorithm Requires Variable VDD The PIC16F8XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin. as well as VDDmax. Verification at VDDmin. guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (See Table 5-1). VDDP = VCC range required during programming. VDDmin. = minimum operating VDD spec for the part. VDDmax.= maximum operating VDD spec for the part. Programmers must verify the PIC16F8XX at its specified VDD max. and VDDmin levels. Since Microchip may introduce future versions of the PIC16F8XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. 2000 Microchip Technology Inc. DS39025D-page 3-173 PIC16F8XX 3.0 CONFIGURATION WORD TABLE 3-1: The PIC16F8XX has several configuration bits. These bits can be set (reads `0') or left unchanged (reads `1') to select various device configurations. 3.1 Device ID Value Device Device ID Word The device ID word for the PIC16F8XX is located at 2006h. FIGURE 3-1: CP1 CP0 DEVICE ID VALUE Dev Rev PIC16F870 00 1101 000 x xxxx PIC16F871 00 1101 001 x xxxx PIC16F872 00 1000 111 x xxxx PIC16F873 00 1001 011 x xxxx PIC16F874 00 1001 001 x xxxx PIC16F876 00 1001 111 x xxxx PIC16F877 00 1001 101 x xxxx CONFIGURATION WORD FOR PIC16F873/874/876/877 RESV - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 Register: Address CONFIG 2007h bit 13-12: bit 11: Reserved: Set to `1' for normal operation bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2) 4K Devices: 11 = Code protection off 10 = not supported 01 = not supported 00 = 0000h to 0FFFh code protected 8K Devices: 11 = Code protection off bit 11: bit 10: bit 9: bit 8: 10 = 1F00h to 1FFFh code protected 01 = 1000h to 1FFFh code protected 00 = 0000h to 1FFFh code protected Reserved: Set to `1' for normal operation Unimplemented: Read as `1' WRT: Flash Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EE memory code protected bit 7: LVP: Low voltage programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS39025D-page 3-174 2000 Microchip Technology Inc. PIC16F8XX FIGURE 3-2: CP1 CP0 CONFIGURATION WORD FOR PIC16F870/871/872 RESV - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 Register: Address CONFIG 2007h bit 13-12: bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2) 11 = Code protection off 10 = not supported 01 = not supported 00 = 0000h to 07FFh code protected bit 11: Reserved: Set to `1' for normal operation bit 10: Unimplemented: Read as `1' bit 9: WRT: Flash Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control bit 8: CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EE memory code protected bit 7: LVP: Low voltage programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. DS39025D-page 3-175 PIC16F8XX 4.0 CODE PROTECTION For PIC16F8XX devices, once code protection is enabled, all program memory locations read all 0's. The ID locations and the configuration word read out in an unscrambled fashion. Further programming is disabled for the entire program memory as well as data memory. It is possible to program the ID locations and the configuration word. 4.1 Disabling Code-Protection It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (code protect bit = 1) using this procedure; however, all data within the program memory and the data memory will be erased when this procedure is executed, and thus, the security of the data or code is not compromised. 4.2 Procedure to disable code protect: a) b) c) d) e) f) g) h) Execute load configuration (with a `1' in bit 13-4, code protect). Increment to configuration word location (0x2007) Execute command (000001) Execute command (000111) Execute `Begin Programming' (001000) Wait 12 ms Execute command (000001) Execute command (000111) Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F8XX, the EEPROM data memory should also be embedded in the hex file (see Section 5.1). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. DS39025D-page 3-176 2000 Microchip Technology Inc. PIC16F8XX 4.3 CHECKSUM COMPUTATION 4.3.1 CHECKSUM Checksum is calculated by reading the contents of the PIC16F8XX memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16F8XX. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F8XX devices is shown in Table 4-1. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. 2000 Microchip Technology Inc. DS39025D-page 3-177 PIC16F8XX TABLE 4-1: CHECKSUM COMPUTATION Blank"V alue 0x25E6 at 0 and max address Device Code Protect PIC16F870 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C PIC16F871 PIC16F872 PIC16F873 Checksum* OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD 0x0F00 : 0xFFF OFF SUM[0x0000:0x0EFF] + CFGW & 0x3BFF +SUM_ID 0x48EE 0xFAA3 0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193 CFGW & 0x3BFF + SUM_ID 0x37CE 0x039C ALL PIC16F874 SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD 0x0F00 : 0xFFF OFF SUM[0x0000:0x0EFF] + CFGW & 0x3BFF +SUM_ID 0x48EE 0xFAA3 0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193 CFGW & 0x3BFF + SUM_ID 0x37CE 0x039C ALL PIC16F876 SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD 0x1F00 : 0x1FFF OFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3 0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993 CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C ALL PIC16F877 SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD 0x1F00 : 0x1FFF OFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3 0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993 CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C ALL Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234 *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS39025D-page 3-178 2000 Microchip Technology Inc. PIC16F8XX 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS 5.1 Embedding Data EEPROM Contents in Hex File The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write data EEPROM contents to a hex file along with program memory information and fuse information. The 256 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage is one data byte per address location, LSB aligned. TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature: Operating Voltage: 0C TA +70C 4.5V VDD 5.5V Characteristics Sym Min VDD level for word operations, program memory VDD VDD level for word operations, data memory VDD level for bulk erase/write operations, program and data memory High voltage on MCLR for high-voltage programming entry Typ Max Units 2.0 5.5 V VDD 2.0 5.5 V VDD 4.5 5.5 V VIHH VDD + 3.5 13.5 V VIH 4.5 5.5 V 1.0 s Conditions/Comments General Voltage on MCLR for low-voltage programming entry MCLR rise time (VSS to VHH) for test mode entry tVHHR (RB6, RB7) input high level VIH1 0.8VDD V Schmitt Trigger input (RB6, RB7) input low level VIL1 0.2VDD V Schmitt Trigger input RB<7:4> setup time before MCLR (test mode selection pattern setup time) tset0 100 ns RB<7:4> hold time after MCLR (test mode selection pattern setup time) thld0 5 s Data in setup time before clock tset1 100 ns Data in hold time after clock thld1 100 ns Data input not driven to next clock input (delay required between command/data or command/command) tdly1 1.0 s Delay between clock to clock of next command or data tdly2 1.0 s Clock to data out valid (during read data) tdly3 80 Erase cycle time tera 2 5 ms Programming cycle time tprog 2 5 ms Serial Program/Verify 2000 Microchip Technology Inc. ns DS39025D-page 3-179 PIC16F8XX FIGURE 5-1: LOAD DATA COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY) VIHH MCLR 1s min. tset0 RB6 (CLOCK) 1 2 3 4 5 6 1 tdly2 2 3 4 5 15 16 thld0 RB7 (DATA) 1 0 0 0 X tset1 strt_bit X stp_bit tset1 tdly1 1s min. thld1 } } } } thld1 100ns min. 100ns min. Program/Verify Test Mode Reset FIGURE 5-2: READ DATA COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY) VIHH MCLR tset0 tdly2 thld0 1s min. 1 2 3 4 5 1 0 1 6 2 3 RB6 (CLOCK) 4 5 15 16 tdly3 RB7 (DATA) 0 0 X X stp_bit strt_bit tdly1 tset1 thld1 1s min. } } 100ns min. RB7 = input RB7 = output RB7 input Program/Verify Test Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY) VIHH MCLR tdly2 Next Command 1s min. 1 2 3 4 5 1 6 2 RB6 (CLOCK) RB7 (DATA) 0 1 1 0 X tset1 X X 0 tdly1 thld1 } } 1s min. 100ns min. Reset DS39025D-page 3-180 Program/Verify Test Mode 2000 Microchip Technology Inc. PIC16F8XX FIGURE 5-4: LOAD DATA COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY) VIH MCLR 1s min. tset0 RB6 (CLOCK) 1 2 3 4 5 6 1 tdly2 2 3 4 5 15 16 thld0 RB7 (DATA) 1 0 0 0 X tset1 strt_bit X stp_bit tset1 tdly1 1s min. thld1 } } } } thld1 100ns min. 100ns min. RB3 Program/Verify Test Mode Reset FIGURE 5-5: READ DATA COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY) VIH MCLR tset0 tdly2 thld0 1s min. 1 2 3 4 5 1 0 1 6 2 3 RB6 (CLOCK) 4 5 15 16 tdly3 RB7 (DATA) 0 0 X X stp_bit strt_bit tdly1 tset1 thld1 1s min. } } 100ns min. RB7 = input RB7 = output RB7 input RB3 Program/Verify Test Mode Reset FIGURE 5-6: INCREMENT ADDRESS COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY) VIH MCLR tdly2 Next Command 1s min. 1 2 3 4 5 1 6 2 RB6 (CLOCK) RB7 (DATA) 0 1 1 0 X tset1 } } Reset 2000 Microchip Technology Inc. X 0 tdly1 thld1 RB3 X 1s min. 100ns min. Program/Verify Test Mode DS39025D-page 3-181 PIC16F8XX NOTES: DS39025D-page 3-182 2000 Microchip Technology Inc. SECTION 4 APPLICATION NOTES IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) OF CALIBRATION PARAMETERS USING A PICmicro(R) MICROCONTROLLER ......................................................................................... 4-1 2000 Microchip Technology Inc. DS30277C-page 4-i DS30277C-page 4-ii 2000 Microchip Technology Inc. AN656 In-Circuit Serial ProgrammingTM (ICSPTM) of Calibration Parameters Using a PICmicro(R) Microcontroller PROGRAMMING FIXTURE Author: John Day Microchip Technology Inc. A programming fixture is needed to assist with the self programming operation. This is typically a small reusable module that plugs into the application PCB being calibrated. Only five pin connections are needed and this programming fixture can draw its power from the application PCB to simplify the connections. INTRODUCTION Many embedded control applications, where sensor offsets, slopes and configuration information are measured and stored, require a calibration step. Traditionally, potentiometers or Serial EEPROM devices are used to set up and store this calibration information. This application note will show how to construct a programming jig that will receive calibration parameters from the application mid-range PICmicro(R) microcontrollers (MCU) and program this information into the application baseline PICmicro MCU using the In-Circuit Serial Programming (ICSP) protocol. This method uses the PIC16CXXX In-Circuit Serial Programming algorithm of the 14-bit core microcontrollers. FIGURE 1: Customer Application PCB Calibration Programming Jig +5V +5V Sensor(s) PIC16CXXX RAX MCLR/VPP VDD VSS Application I/O RB7 RBX RB6 +5V +13V VPP Generator 10k VPP VDD GND_ON VPP_ON MCLR VSS VDD 1k VSS RB7 RB6 PIC16C58 To Application Input(s) 2000 Microchip Technology Inc. RB7 RB6 RB5 RB4 RC osc RB3 RB1 Wait RB2 Done Optional PC Connection DS00656B-page 4-1 AN656 Electrical Interface Programming Issues There are a total of five electrical connections needed between the application PIC16CXXX microcontroller and the programming jig: The PIC16CXXX programming specification suggests verification of program memory at both Maximum and Minimum VDD for each device. This is done to ensure proper programming margins and to detect (and reject) any improperly programmed devices. All production quality programmers vary VDD from VDDmin to VDDmax after programming and verify the device under each of these conditions. * MCLR/VPP - High voltage pin used to place application PIC16CXXX into programming mode * VDD - +5 volt power supply connection to the application PIC16CXXX * VSS - Ground power supply connection to the application PIC16CXXX * RB6 - PORTB, bit6 connection to application PIC16CXXX used to clock programming data * RB7 - PORTB, bit7 connection to application PIC16CXXX used to send programming data This programming jig is intended to grab power from the application power supply through the VDD connection. The programming jig will require 100 mA of peak current during programming. The application will need to set RB6 and RB7 as inputs, which means external devices cannot drive these lines. The calibration data will be sent to the programming jig by the application PIC16CXXX through RB6 and RB7. The programming jig will later use these lines to clock the calibration data into the application PIC16CXXX. Since both the application voltage and it's tolerances are known, it is not necessary to verify the PIC16CXXX calibration parameters at the device VDDmax and VDDmin. It is only necessary to verify at the application power supply Max and Min voltages. This application note shows the nominal (+5V) verification routine and hardware. If the power supply is a regulated +5V, this is adequate and no additional hardware or software is needed. If the application power supply is not regulated (such as a battery powered or poorly regulated system) it is important to complete a VDDmin and VDDmax verification cycle following the +5V verification cycle. See programming specifications for more details on VDD verification procedures. * PIC16C5X Programming Specifications DS30190 * PIC16C55X Programming Specifications DS30261 * PIC16C6X/7X/9XX Programming Specifications DS30228 * PIC16C84 Programming Specifications DS30189 Note: The designer must consider environmental conditions, voltage ranges, and aging issues when determining VDD min/max verification levels. Please refer to the programming specification for the application device. The calibration programming and initial verification MUST occur at +5V. If the application is intended to run at lower (or higher voltages), a second verification pass must be added where those voltages are applied to VDD and the device is verified. DS00656B-page 4-2 2000 Microchip Technology Inc. AN656 is accomplished through the RB6 and RB7 lines. The format is a simple synchronous clock and data format as shown in Figure 2. Communication Format (Application Microcontroller to Programming Jig) Unused program memory, in the application PIC16CXXX, is left unprogrammed as all 1s; therefore the unprogrammed program memory for the calibration look-up table would contain 3FFF (hex). This is interpreted as an "ADDLW FF". The application microcontroller simply needs one "RETLW FF" instruction at the end of the space allocated in program memory for the calibration parameter look-up table. When the application microcontroller is powered up, it will receive a "FFh" for each calibration parameter that is looked up; therefore, it can detect that it is uncalibrated and jump to the calibration code. A pull-down on the clock line is used to hold it low. The application microcontroller needs to send the high and low bytes of the target start address of the calibration constants to the calibration jig. Next, the data bytes are sent followed by a checksum of the entire data transfer as shown in Figure 1. Once the data transfer is complete, the checksum is verified by the programming jig and the data printed at 9600 baud, 8-bits, no parity, 1 stop bit through RB3. A connection to this pin is optional. Next the programming jig applies +13V, programs and verifies the application PIC16CXXX calibration parameters. Once the calibration constants are calculated by the application PICmicro MCU, they need to be communicated to the (PIC16C58A based) programming jig. This FIGURE 2: RB6 RB7 CALbit7 CALbit6 CALbit5 CALbit4 CALbit3 CALbit2 CALbit1 CALbit0 FIGURE 1: AddrH AddrL 2000 Microchip Technology Inc. Data 0 Data 1 Data N CKSUM DS00656B-page 4-3 AN656 LED Operation When the programming jig is waiting for communication from the application PICmicro MCU, both LEDs are OFF. Once a valid data stream is received (with at least one calibration byte and a correct checksum) the WORK LED is lit while the calibration parameters are printed through the optional RB3 port. Next, the DONE LED is lit to indicate that these parameters are being programmed and verified by the programming jig. Once the programming is finished, the WORK LED is extinguished and the DONE LED remains lit. If any parameters fail programming, the DONE LED is extinguished; therefore both LEDs would remain off. FIGURE 3: ISP CALIBRATION JIG PROGRAMMER SCHEMATIC VCC VCC VCC VCC VCC T0CKI VSS VDD VCC VPP VCC VIN VCC VREF VPP DS00656B-page 4-4 2000 Microchip Technology Inc. AN656 the application PIC16CXXX, places it into programming mode and programs/verifies each calibration word. Code Protection Selection of the code protection configuration bits on PIC16CXXX microcontrollers prevents further programming of the program memory array. This would prevent writing self calibration parameters if the device is code protected prior to calibration. There are two ways to address this issue: 1. 2. CONCLUSION Typically, calibration information about a system is stored in EEPROM. For calibration data that does not change over time, the In-circuit Serial Programming capability of the PIC16CXXX devices provide a simple, cost effective solution to an external EEPROM. This method not only decreases the cost of a design, but also reduces the complexity and possible failure points of the application. Do not code protect the device when programming it with the programmer. Add additional code (See the PIC16C6X/7X programming Spec) to the ISPPRGM.ASM to program the code protection bit after complete verification of the calibration parameters Only code protect 1/2 or 3/4 of the program memory with the programmer. Place the calibration constants into the unprotected part of program memory. Software Routines There are two source code files needed for this application note: 1. ISPTEST.ASM (Appendix A) Contains the source code for the application PIC16CXXX, sets up the calibration look-up table and implements the communication protocol to the programming jig. 2. ISPPRGM.ASM (Appendix B) Source code for a PIC16C58A to implement the programming jig. This waits for and receives the calibration parameters from TABLE 1: PARTS LIST FOR PIC16CXXX ISP CALIBRATION JIG Bill of Material Item Quantity 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2 1 1 2 2 1 1 1 1 2 2 5 4 2 1 1 1 1 1 2000 Microchip Technology Inc. Reference C1,C2 C3 C4 C5,C6 D1,D2 E1 E2 J1 L1 Q1,Q2 Q3,Q4 R1,R2,R3,R4,R15 R5,R6,R12,R14 R7,R8 R9 R10 R11 R13 Y1 Part 15 pF 620 pF 0.1 mF 220 mF LED PIC16C58 LM78S40 CON5 270 mH 2N2222 2N2907 1k 10k 270 180 23.7k 2.49k 2.2k 4.0 MHz DS00656B-page 4-5 AN656 APPENDIX A: MPASM 01.40.01 Intermediate LOC OBJECT CODE VALUE 0FFF 0FF9 00000006 00000007 00000005 00000004 00000003 00000002 00000001 ISPPRGM.ASM 3-31-1997 10:57:03 PAGE 1 LINE SOURCE TEXT 00001 ; Filename: ISPPRGM.ASM 00002 ; ********************************************** 00003 ; * Author: John Day * 00004 ; * Sr. Field Applications Engineer * 00005 ; * Microchip Technology * 00006 ; * Revision: 1.0 * 00007 ; * Date August 25, 1995 * 00008 ; * Part: PIC16C58 * 00009 ; * Compiled using MPASM V1.40 * 00010 ; ********************************************** 00011 ; * Include files: * 00012 ; * P16C5X.ASM * 00013 ; ********************************************** 00014 ; * Fuses: OSC: XT (4.0 Mhz xtal) * 00015 ; * WDT: OFF * 00016 ; * CP: OFF * 00017 ;********************************************************************************* 00018 ; This program is intended to be used as a self programmer 00019 ; to store calibration constants into a lookup table 00020 ; within the main system processor. A 4 Mhz crystal 00021 ; is needed and an optional 9600 baud seiral port will 00022 ; display the parameters to be programmed. 00023 ; ;********************************************************************************* 00024 ; * Program Memory: * 00025 ; * Words - communication with test jig * 00026 ; * 17 Words - calibration look-up table (16 bytes of data) * 00027 ; * 13 Words - Test Code to generate Calibration Constants * 00028 ; * RAM memory: * 00029 ; * 64 Bytes - Store up to 64 bytes of calibration constant * 00030 ; * 9 Bytes - Store 9 bytes of temp variables (reused) * 00031 ; ;**************************************************************************** 00032 00033 list p=16C58A 00034 include <p16C5x.inc> 00001 LIST 00002 ; P16C5X.INC Standard Hdr File, Version 3.30 Microchip Technology, Inc. 00224 LIST 00035 __CONFIG _CP_OFF&_WDT_OFF&_XT_OSC 00036 00037 ; ************************************ 00038 ; * Port A (RA0-RA4) bit definitions * 00039 ; ************************************ 00040 ; No PORT A pins are used in this design 00041 00042 ; ************************************ 00043 ; * Port B (RB0-RB7) bit definitions * 00044 ; ************************************ 00045 ISPCLOCK EQU 6 ; Clock line for ISP and parameter comm 00046 ISPDATA EQU 7 ; Data line for ISP and parameter comm 00047 VPPON EQU 5 ; Apply +13V VPP voltage to MCLR (test mode) 00048 GNDON EQU 4 ; Apply +0V (gnd) voltage to MCLR (reset) 00049 SEROUT EQU 3 ; Optional RS-232 TX output (needs 12V driver) 00050 DONELED EQU 2 ; Turns on LED when done sucessfully program 00051 WORKLED EQU 1 ; On during programming, off when done 00052 ; RB0 is not used in this design 00053 DS00656B-page 4-6 2000 Microchip Technology Inc. AN656 00000007 00000008 00000007 00000008 00000009 0000000A 0000000B 0000000C 0000000D 00000007 00000008 00000009 0000000A 0000000B 0000000C 0000000E 0000000F 00000001 00000081 00000006 00000010 00000007 00000006 00000008 0000000E 00000002 00000004 00000034 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 ; ************************************************* ; * RAM register definition: * ; * 07h - 0Fh - used for internal counters, vars * ; * 10h - 7Fh - 64 bytes for cal param storage * ; ************************************************* ; *** ; *** The following VARS are used during ISP programming: ; *** HIADDR EQU 07h ; High address of CAL params to be stored LOADDR EQU 08h ; Low address of CAL params to be stored HIDATA EQU 07h ; High byte of data to be sent via ISP LODATA EQU 08h ; Low byte of data to be sent via ISP HIBYTE EQU 09h ; High byte of data received via ISP LOBYTE EQU 0Ah ; Low byte of data received via ISP PULSECNT EQU 0Bh ; Number of times PIC has been pulse programmed TEMPCOUNT EQU 0Ch ; TEMP var used in counters TEMP EQU 0Dh ; TEMP var used throughout program ; *** ; *** The following VARS are used to receive and store CAL params: ; *** COUNT EQU 07h ; Counter var used to receive cal params TEMP1 EQU 08h ; TEMP var used for RS-232 comm DATAREG EQU 09h ; Data register used for RS-232 comm CSUMTOTAL EQU 0Ah ; Running total of checksum (addr + data) TIMEHIGH EQU 0Bh ; Count how long CLOCK line is high TIMELOW EQU 0Ch ; Count how long CLOCK line is low ADDRPTR EQU 0Eh ; Pointer to next byte of CAL storage BYTECOUNT EQU 0Fh ; Number of CAL bytes received ; ************************************* ; * Various constants used in program * ; ************************************* DATISPOUT EQU b'00000001' ; tris settings for ISP data out DATISPIN EQU b'10000001' ; tris settings for ISP data in CMDISPCNT EQU 6 ; Number of bits for ISP command STARTCALBYTE EQU 10h ; Address in RAM where CAL byte data stored VFYYES EQU PA2 ; Flag bit enables verification (STATUS) CMDISPINCRADDR EQU b'00000110' ; ISP Pattern to increment address CMDISPPGMSTART EQU b'00001000' ; ISP Pattern to start programming CMDISPPGMEND EQU b'00001110' ; ISP Pattern to end programming CMDISPLOAD EQU b'00000010' ; ISP Pattern to load data for program CMDISPREAD EQU b'00000100' ; ISP Pattern to read data for verify UPPER6BITS EQU 034h ; Upper 6 bits for retlw instruction ; ************************************* ; * delaybit macro * ; * Delays for 104 uS (at 4 Mhz clock)* ; * for 9600 baud communications * ; * RAM used: COUNT * ; ************************************* delaybit macro local dlylabels ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz movlw .31 ; place 31 decimal literal into count movwf COUNT ; Initialize COUNT with loop count nop ; Add one cycle delay dlylabels decfsz COUNT,F ; Decrement count until done goto dlylabels ; Not done delaying - go back! ENDM ; Done with Macro ; ; ; ; ************************************************ * addrtofsr macro * * Converts logical, continuous address 10h-4Fh * * to FSR address as follows for access to (4) * 2000 Microchip Technology Inc. DS00656B-page 4-7 AN656 00120 ; * banks of file registers in PIC16C58: * 00121 ; * Logical Address FSR Value * 00122 ; * 10h-1Fh 10h-1Fh * 00123 ; * 20h-2Fh 30h-3Fh * 00124 ; * 30h-3Fh 50h-5Fh * 00125 ; * 40h-4Fh 70h-7Fh * 00126 ; * Variable Passed: Logical Address * 00127 ; * RAM used: FSR * 00128 ; * W * 00129 ; ************************************************ 00130 addrtofsr macro TESTADDR 00131 movlw STARTCALBYTE ; Place base address into W 00132 subwf TESTADDR,w ; Offset by STARTCALBYTE 00133 movwf FSR ; Place into FSR 00134 btfsc FSR,5 ; Shift bits 4,5 to 5,6 00135 bsf FSR,6 00136 bcf FSR,5 00137 btfsc FSR,4 00138 bsf FSR,5 00139 bsf FSR,4 00140 endm 00141 00142 00143 ; ************************************** 00144 ; * The PC starts at the END of memory * 00145 ; ************************************** 07FF 00146 ORG 7FFh Message[306]: Crossing page boundary -- ensure page bits are set. 07FF 0A00 00147 goto start 00148 00149 ; ************************************** 00150 ; * Start of CAL param read routine * 00151 ; ************************************** 0000 00152 ORG 0h 0000 00153 start 0000 0C0A 00154 movlw b'00001010' ; Serial OFF, LEDS OFF, VPP OFF 0001 0026 00155 movwf PORTB ; Place "0" into port b latch register 0002 0CC1 00156 movlw b'11000001' ; RB7;:RB6, RB0 set to inputs 0003 0006 00157 tris PORTB ; Move to tris registers 0004 0040 00158 clrw ; Place 0 into W 0005 0065 00159 clrf PORTA ; Place all ZERO into latch 0006 0005 00160 tris PORTA ; Make all pins outputs to be safe.. 0007 0586 00161 bsf PORTB,GNDON ; TEST ONLY-RESET PIC-NOT NEEDED IN REAL DESIGN! 0008 00162 clearram 0008 0C10 00163 movlw 010h ; Place start of buffer into W 0009 0027 00164 movwf COUNT ; Use count for RAM pointer 000A 00165 loopclrram 00166 addrtofsr COUNT ; Set up FSR 000A 0C10 M movlw STARTCALBYTE ; Place base address into W 000B 0087 M subwf COUNT,w ; Offset by STARTCALBYTE 000C 0024 M movwf FSR ; Place into FSR 000D 06A4 M btfsc FSR,5 ; Shift bits 4,5 to 5,6 000E 05C4 M bsf FSR,6 000F 04A4 M bcf FSR,5 0010 0684 M btfsc FSR,4 0011 05A4 M bsf FSR,5 0012 0584 M bsf FSR,4 0013 0060 00167 clrf INDF ; Clear buffer value 0014 02A7 00168 incf COUNT,F ; Move to next reg 0015 0C50 00169 movlw 050h ; Move end of buffer addr to W 0016 0087 00170 subwf COUNT,W ; Check if at last MEM 0017 0743 00171 btfss STATUS,Z ; Skip when at end of counter 0018 0A0A 00172 goto loopclrram ; go back to next location 0019 0486 00173 bcf PORTB,GNDON ; TEST ONLY-LET IT GO-NOT NEEDED IN REAL DESIGN! 001A 00174 calget 001A 006A 00175 clrf CSUMTOTAL ; Clear checksum total byte DS00656B-page 4-8 2000 Microchip Technology Inc. AN656 001B 001C 001D 001E 001E 001F 0020 0020 0021 0022 0022 0023 0024 0024 0025 0026 0027 0028 0029 0029 002A 002B 002C 002D 002E 002E 002F 0030 0031 0032 0033 0034 0034 0035 0036 0037 0038 0039 0069 0C10 002E 003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047 0047 0048 0049 004A 004B 004C 004D 004E 004F 004F 0050 0051 0052 0C10 008E 0024 06A4 05C4 04A4 0684 05A4 0584 0209 0020 02AE 0A20 07C6 0A1E 0C08 0027 006B 006C 06C6 0A29 02EB 0A24 0A47 07C6 0A2E 02EC 0A29 0A47 0C08 0087 0743 0A34 0209 01EA 0503 07E6 0403 0369 02E7 0A22 0C14 008E 0703 0A93 0200 00AA 0743 0A9F 0426 0C10 008E 002F 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 M M M M M M M M M 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 clrf DATAREG ; Clear out data receive register movlw STARTCALBYTE ; Place RAM start address of first cal byte movwf ADDRPTR ; Place this into ADDRPTR waitclockpulse btfss PORTB,ISPCLOCK ; Wait for CLOCK high pulse - skip when high goto waitclockpulse ; CLOCK is low - go back and wait! loopcal movlw .8 ; Place 8 into W (8 bits/byte) movwf COUNT ; set up counter register to count bits loopsendcal clrf TIMEHIGH ; Clear timeout counter for high pulse clrf TIMELOW ; Clear timeout counter for low pulse waitclkhi btfsc PORTB,ISPCLOCK ; Wait for CLOCK high - skip if it is low goto waitclklo ; Jump to wait for CLOCK low state decfsz TIMEHIGH,F ; Decrement counter - skip if timeout goto waitclkhi ; Jump back and wait for CLOCK high again goto timeout ; Timed out waiting for high - check data! waitclklo btfss PORTB,ISPCLOCK ; Wait for CLOCK low - skip if it is high goto clockok ; Got a high to low pulse - jump to clockok decfsz TIMELOW,F ; Decrement counter - skip if timeout goto waitclklo ; Jump back and wait for CLOCK low again goto timeout ; Timed out waiting for low - check data! clockok movlw .8 ; Place initial count value into W subwf COUNT,W ; Subtract from count, place into W btfss STATUS,Z ; Skip if we are at count 8 (first value) goto skipcsumadd ; Skip checksum add if any other count value movf DATAREG,W ; Place last byte received into W addwf CSUMTOTAL,F ; Add to checksum skipcsumadd bsf STATUS,C ; Assume data bit is high btfss PORTB,ISPDATA ; Skip if the data bit was high bcf STATUS,C ; Set data bit to low rlf DATAREG,F ; Rotate next bit into DATAREG decfsz COUNT,F ; Skip after 8 bits goto loopsendcal ; Jump back and send next bit addrtofsr ADDRPTR ; Convert pointer address to FSR movlw STARTCALBYTE ; Place base address into W subwf ADDRPTR,w ; Offset by STARTCALBYTE movwf FSR ; Place into FSR btfsc FSR,5 ; Shift bits 4,5 to 5,6 bsf FSR,6 bcf FSR,5 btfsc FSR,4 bsf FSR,5 bsf FSR,4 movf DATAREG,W ; Place received byte into W movwf INDF ; Move recv'd byte into CAL buffer location incf ADDRPTR,F ; Move to the next cal byte goto loopcal ; Go back for next byte timeout movlw STARTCALBYTE+4 ; check if we received (4) params subwf ADDRPTR,W ; Move current address pointer to W btfss STATUS,C ; Skip if we have at least (4) goto sendnoise ; not enough params - print and RESET! movf INDF,W ; Move received checksum into W subwf CSUMTOTAL,F ; Subtract received Checksum from calc'd checksum btfss STATUS,Z ; Skip if CSUM OK goto sendcsumbad ; Checksum bad - print and RESET! csumok bcf PORTB,WORKLED ; Turn on WORK LED movlw STARTCALBYTE ; Place start pointer into W subwf ADDRPTR,W ; Subtract from current address movwf BYTECOUNT ; Place into number of bytes into BYTECOUNT 2000 Microchip Technology Inc. DS00656B-page 4-9 AN656 0053 002B 0054 0C10 0055 002E 0056 0C7C 09AE 028E 0E0F 00233 00234 00235 00236 00237 M M M M M M M M M 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 008B 0643 00288 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0066 0067 0068 0069 006A 006B 006C 006D 006D 006E 006F 0070 0071 0072 0073 0073 0074 0075 0076 0077 0078 0079 007A 007A 007B 007C 007D 007E 007F 0080 0081 0081 0082 0083 0084 0085 0086 0087 0087 0088 0089 008A 0C10 008E 0024 06A4 05C4 04A4 0684 05A4 0584 0380 0E0F 002D 0C0A 00AD 0603 0A6D 0380 0E0F 002D 0C30 01CD 09AE 0A73 0380 0E0F 002D 0C37 01CD 09AE 0200 0E0F 002D 0C0A 00AD 0603 0A81 0200 0E0F 002D 0C30 01CD 09AE 0A87 0200 0E0F 002D 0C37 01CD 09AE DS00656B-page 4-10 movwf TIMEHIGH movlw STARTCALBYTE movwf ADDRPTR loopprintnums addrtofsr ADDRPTR movlw STARTCALBYTE subwf ADDRPTR,w movwf FSR btfsc FSR,5 bsf FSR,6 bcf FSR,5 btfsc FSR,4 bsf FSR,5 bsf FSR,4 swapf INDF,W andlw 0Fh movwf TEMP movlw .10 subwf TEMP,F btfsc STATUS,C goto printhiletter printhinumber swapf INDF,W andlw 0Fh movwf TEMP movlw `0' addwf TEMP,w call putchar goto printlo printhiletter swapf INDF,W andlw 0Fh movwf TEMP movlw `A'-.10 addwf TEMP,w call putchar printlo movf INDF,W andlw 0Fh movwf TEMP movlw .10 subwf TEMP,F btfsc STATUS,C goto printloletter printlonumber movf INDF,W andlw 0Fh movwf TEMP movlw `0' addwf TEMP,w call putchar goto printnext printloletter movf INDF,W andlw 0Fh movwf TEMP movlw `A'-.10 addwf TEMP,w call putchar printnext movlw `|' call putchar incf ADDRPTR,W andlw 0Fh btfsc STATUS,Z ; TEMP store into timehigh reg ; Place start address into W ; Set up address pointer ; ; ; ; ; Set up FSR Place base address into W Offset by STARTCALBYTE Place into FSR Shift bits 4,5 to 5,6 ; ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place .10 into W Subtract 10 from TEMP Skip if TEMP is less than 9 Greater than 9 - print letter instead ; ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place ASCII `0' into W Add to TEMP, place into W Send out char Jump to print next char ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place ASCII `A' into W Add to TEMP, place into W send out char ; ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place .10 into W Subtract 10 from TEMP Skip if TEMP is less than 9 Greater than 9 - print letter instead ; ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place ASCII `0' into W Add to TEMP, place into W send out char jump to print next char ; ; ; ; ; ; Place received char into W Strip off upper digits Place into TEMP Place ASCII `A' into W Add to TEMP, place into W send out char ; ; ; ; Place ASCII `|' into W Send out character Go to next buffer value And with F ; Skip if this is NOT multiple of 16 2000 Microchip Technology Inc. AN656 008C 09A9 00289 call printcrlf ; Print CR and LF every 16 chars 008D 02AE 00290 incf ADDRPTR,F ; go to next address 008E 02EF 00291 decfsz BYTECOUNT,F ; Skip after last byte 008F 0A56 00292 goto loopprintnums ; Go back and print next char 0090 09A9 00293 call printcrlf ; Print CR and LF 0091 05A3 00294 bsf STATUS,PA0 ; Set page bit to page 1 Message[306]: Crossing page boundary -- ensure page bits are set. 0092 0A6B 00295 goto programpartisp ; Go to program part through ISP 0093 00296 sendnoise 0093 0C4E 00297 movlw `N' ; Place `N' into W 0094 09AE 00298 call putchar ; Send char in W to terminal 0095 0C4F 00299 movlw `O' ; Place `O' into W 0096 09AE 00300 call putchar ; Send char in W to terminal 0097 0C49 00301 movlw `I' ; Place `I' into W 0098 09AE 00302 call putchar ; Send char in W to terminal 0099 0C53 00303 movlw `S' ; Place `S' into W 009A 09AE 00304 call putchar ; Send char in W to terminal 009B 0C45 00305 movlw `E' ; Place `E' into W 009C 09AE 00306 call putchar ; Send char in W to terminal 009D 09A9 00307 call printcrlf ; Print CR and LF 009E 0A1A 00308 goto calget ; RESET! 009F 00309 sendcsumbad 009F 0C43 00310 movlw `C' ; Place `C' into W 00A0 09AE 00311 call putchar ; Send char in W to terminal 00A1 0C53 00312 movlw `S' ; Place `S' into W 00A2 09AE 00313 call putchar ; Send char in W to terminal 00A3 0C55 00314 movlw `U' ; Place `U' into W 00A4 09AE 00315 call putchar ; Send char in W to terminal 00A5 0C4D 00316 movlw `M' ; Place `M' into W 00A6 09AE 00317 call putchar ; Send char in W to terminal 00A7 09A9 00318 call printcrlf ; Print CR and LF 00A8 0A1A 00319 goto calget ; RESET! 00320 00321 ; ****************************************** 00322 ; * printcrlf * 00323 ; * Sends char .13 (Carrage Return) and * 00324 ; * char .10 (Line Feed) to RS-232 port * 00325 ; * by calling putchar. * 00326 ; * RAM used: W * 00327 ; ****************************************** 00A9 00328 printcrlf 00A9 0C0D 00329 movlw .13 ; Value for CR placed into W 00AA 09AE 00330 call putchar ; Send char in W to terminal 00AB 0C0A 00331 movlw .10 ; Value for LF placed into W 00AC 09AE 00332 call putchar ; Send char in W to terminal 00AD 0800 00333 retlw 0 ; Done - return! 00334 00335 ; ****************************************** 00336 ; * putchar * 00337 ; * Print out the character stored in W * 00338 ; * by toggling the data to the RS-232 * 00339 ; * output pin in software. * 00340 ; * RAM used: W,DATAREG,TEMP1 * 00341 ; ****************************************** 00AE 00342 putchar 00AE 0029 00343 movwf DATAREG ; Place character into DATAREG 00AF 0C09 00344 movlw 09h ; Place total number of bits into W 00B0 0028 00345 movwf TEMP1 ; Init TEMP1 for bit counter 00B1 0403 00346 bcf STATUS,C ; Set carry to send start bit 00B2 0AB4 00347 goto putloop1 ; Send out start bit 00B3 00348 putloop 00B3 0329 00349 rrf DATAREG,F ; Place next bit into carry 00B4 00350 putloop1 00B4 0703 00351 btfss STATUS,C ; Skip if carry was set 00B5 0466 00352 bcf PORTB,SEROUT ; Clear RS-232 serial output bit 00B6 0603 00353 btfsc STATUS,C ; Skip if carry was clear 2000 Microchip Technology Inc. DS00656B-page 4-11 AN656 00B7 0566 0000 00B8 00B9 00BA 00BB 00BB 00BC 00BD 00BE 00BF 0C1F 0027 0000 02E7 0ABB 02E8 0AB3 0566 0000 00C0 00C1 00C2 00C3 00C3 00C4 00C5 0C1F 0027 0000 02E7 0AC3 0800 0200 0200 0200 0201 0202 0203 0204 0205 0206 0207 0207 0208 0209 020A 020B 020C 020D 020E 020F 0210 0211 0212 04A6 0586 0CC1 0006 0486 0526 0800 0C08 0026 04A6 0586 0C01 0006 0206 002D 048D 05AD 020D 0026 00354 00355 M M M M M M M M M 00356 00357 00358 00359 M M M M M M M M M 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 DS00656B-page 4-12 bsf PORTB,SEROUT ; Set RS-232 serial output bit delaybit ; Delay for one bit time local dlylabels ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz movlw .31 ; place 31 decimal literal into count movwf COUNT ; Initialize COUNT with loop count nop ; Add one cycle delay dlylabels decfsz COUNT,F ; Decrement count until done goto dlylabels ; Not done delaying - go back! decfsz TEMP1,F ; Decrement bit counter, skip when done! goto putloop ; Jump back and send next bit bsf PORTB,SEROUT ; Send out stop bit delaybit ; delay for stop bit local dlylabels ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz movlw .31 ; place 31 decimal literal into count movwf COUNT ; Initialize COUNT with loop count nop ; Add one cycle delay dlylabels decfsz COUNT,F ; Decrement count until done goto dlylabels ; Not done delaying - go back! retlw 0 ; Done - RETURN ; ; ; ; ; ******************************************************************* * ISP routines from PICSTART-16C * * Converted from PIC17C42 to PIC16C5X code by John Day * * Originially written by Jim Pepping * ******************************************************************* ORG 200 ; ISP routines stored on page 1 ; ******************************************************************* ; * poweroffisp * ; * Power off application PIC - turn off VPP and reset device after * ; * programming pass is complete * ; ******************************************************************* poweroffisp bcf PORTB,VPPON ; Turn off VPP 13 volts bsf PORTB,GNDON ; Apply 0 V to MCLR to reset PIC movlw b'11000001' ; RB6,7 set to inputs tris PORTB ; Move to tris registers bcf PORTB,GNDON ; Allow MCLR to go back to 5 volts, deassert reset bsf PORTB,WORKLED ; Turn off WORK LED retlw 0 ; Done so return! ; ******************************************************************* ; * testmodeisp * ; * Apply VPP voltage to place application PIC into test mode. * ; * this enables ISP programming to proceed * ; * RAM used: TEMP * ; ******************************************************************* testmodeisp movlw b'00001000' ; Serial OFF, LEDS OFF, VPP OFF movwf PORTB ; Place "0" into port b latch register bcf PORTB,VPPON ; Turn off VPP just in case! bsf PORTB,GNDON ; Apply 0 volts to MCLR movlw b'00000001' ; RB6,7 set to outputs tris PORTB ; Move to tris registers movf PORTB,W ; Place PORT B state into W movwf TEMP ; Move state to TEMP bcf TEMP,4 ; Turn off MCLR GND bsf TEMP,5 ; Turn on VPP voltage movf TEMP,W ; Place TEMP into W movwf PORTB ; Turn OFF GND and ON VPP 2000 Microchip Technology Inc. AN656 0213 0546 0214 0800 0215 0215 0216 0217 0218 0219 021A 021B 021C 021D 021E 021E 021F 0220 0221 0222 0223 0224 0225 0226 0227 0228 0229 022A 022B 022C 022C 022D 022E 022F 0230 0231 0232 0233 0234 0235 0236 0237 0237 0238 0239 023A 023B 023C 023D 023E 023F 0240 0C0E 002D 04C6 04E6 0C01 0006 04E6 05C6 04C6 0403 04E6 0329 032A 0603 05E6 05C6 04C6 02ED 0A1E 04E6 05C6 04C6 0800 0C0E 002D 0069 006A 0403 04C6 04E6 0C81 0006 05C6 04C6 05C6 0000 0403 06E6 0503 0329 032A 04C6 0000 0000 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 bsf PORTB,DONELED retlw 0 ; Turn ON GREEN LED ; Done so return! ; ******************************************************************* ; * p16cispout * ; * Send 14-bit data word to application PIC for writing this data * ; * to it's program memory. The data to be sent is stored in both * ; * HIBYTE (6 MSBs only) and LOBYTE. * ; * RAM used: TEMP, W, HIBYTE (inputs), LOBYTE (inputs) * ; ******************************************************************* P16cispout movlw .14 ; Place 14 into W for bit counter movwf TEMP ; Use TEMP as bit counter bcf PORTB,ISPCLOCK ; Clear CLOCK line bcf PORTB,ISPDATA ; Clear DATA line movlw DATISPOUT ; Place tris value for data output tris PORTB ; Set tris latch as data output bcf PORTB,ISPDATA ; Send a start bit (0) bsf PORTB,ISPCLOCK ; Set CLOCK output bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock start bit) P16cispoutloop bcf STATUS,C ; Clear carry bit to start clean bcf PORTB,ISPDATA ; Clear DATA bit to start (assume 0) rrf HIBYTE,F ; Rotate HIBYTE output rrf LOBYTE,F ; Rotate LOBYTE output btfsc STATUS,C ; Skip if data bit is zero bsf PORTB,ISPDATA ; Set DATA line to send a one bsf PORTB,ISPCLOCK ; Set CLOCK output bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock bit) decfsz TEMP,F ; Decrement bit counter, skip when done goto P16cispoutloop ; Jump back and send next bit bcf PORTB,ISPDATA ; Send a stop bit (0) bsf PORTB,ISPCLOCK ; Set CLOCK output bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock stop bit) retlw 0 ; Done so return! ; ******************************************************************* ; * p16cispin * ; * Receive 14-bit data word from application PIC for reading this * ; * data from it's program memory. The data received is stored in * ; * both HIBYTE (6 MSBs only) and LOBYTE. * ; * RAM used: TEMP, W, HIBYTE (output), LOBYTE (output) * ; ******************************************************************* P16cispin movlw .14 ; Place 14 data bit count value into W movwf TEMP ; Init TEMP and use for bit counter clrf HIBYTE ; Clear recieved HIBYTE register clrf LOBYTE ; Clear recieved LOBYTE register bcf STATUS,C ; Clear carry bit to start clean bcf PORTB,ISPCLOCK ; Clear CLOCK output bcf PORTB,ISPDATA ; Clear DATA output movlw DATISPIN ; Place tris value for data input into W tris PORTB ; Set up tris latch for data input bsf PORTB,ISPCLOCK ; Send a single clock to start things going bcf PORTB,ISPCLOCK ; Clear CLOCK to start receive P16cispinloop bsf PORTB,ISPCLOCK ; Set CLOCK bit nop ; Wait one cycle bcf STATUS,C ; Clear carry bit, assume 0 read btfsc PORTB,ISPDATA ; Check the data, skip if it was zero bsf STATUS,C ; Set carry bit if data was one rrf HIBYTE,F ; Move recevied bit into HIBYTE rrf LOBYTE,F ; Update LOBYTE bcf PORTB,ISPCLOCK ; Clear CLOCK line nop ; Wait one cycle nop ; Wait one cycle 2000 Microchip Technology Inc. DS00656B-page 4-13 AN656 0241 0242 0243 0244 0245 0246 0247 0248 0249 024A 024B 024C 024D 024E 024F 0250 0251 0252 0252 0253 0254 0255 0256 0257 0258 0259 0259 025A 025B 025C 025D 025E 025F 0260 0261 0262 0263 0264 0265 0266 0267 0268 0269 026A 026B 026B 026C 026D 026E 026F 0270 02ED 0A37 05C6 0000 04C6 0000 0403 0329 032A 0403 0329 032A 04C6 04E6 0C01 0006 0800 002A 0C06 002D 04E6 04C6 0C01 0006 0403 04E6 032A 0603 05E6 05C6 0000 04C6 02ED 0A59 0000 04E6 04C6 0C81 0006 0000 0000 0800 0907 0064 0210 0027 0211 0028 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 00513 00514 00515 00516 00517 00518 00519 00520 00521 00522 00523 00524 00525 00526 00527 00528 00529 00530 00531 00532 00533 DS00656B-page 4-14 decfsz goto bsf nop bcf nop bcf rrf rrf bcf rrf rrf bcf bcf movlw tris retlw 0 TEMP,F P16cispinloop PORTB,ISPCLOCK PORTB,ISPCLOCK STATUS,C HIBYTE,F LOBYTE,F STATUS,C HIBYTE,F LOBYTE,F PORTB,ISPCLOCK PORTB,ISPDATA DATISPOUT PORTB ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Decrement bit counter, skip when zero Jump back and receive next bit Clock a stop bit (0) Wait one cycle Clear CLOCK to send bit Wait one cycle Clear carry bit Update HIBYTE with the data Update LOBYTE Clear carry bit Update HIBYTE with the data Update LOBYTE with the data Clear CLOCK line Clear DATA line Place tris value for data output into W Set tris to data output Done so RETURN! ; ******************************************************************* ; * commandisp * ; * Send 6-bit ISP command to application PIC. The command is sent * ; * in the W register and later stored in LOBYTE for shifting. * ; * RAM used: LOBYTE, W, TEMP * ; ******************************************************************* commandisp movwf LOBYTE ; Place command into LOBYTE movlw CMDISPCNT ; Place number of command bits into W movwf TEMP ; Use TEMP as command bit counter bcf PORTB,ISPDATA ; Clear DATA line bcf PORTB,ISPCLOCK ; Clear CLOCK line movlw DATISPOUT ; Place tris value for data output into W tris PORTB ; Set tris to data output P16cispcmmdoutloop bcf STATUS,C ; Clear carry bit to start clean bcf PORTB,ISPDATA ; Clear the DATA line to start rrf LOBYTE,F ; Update carry with next CMD bit to send btfsc STATUS,C ; Skip if bit is supposed to be 0 bsf PORTB,ISPDATA ; Command bit was a one - set DATA to one bsf PORTB,ISPCLOCK ; Set CLOCK line to clock the data nop ; Wait one cycle bcf PORTB,ISPCLOCK ; Clear CLOCK line to clock data decfsz TEMP,F ; Decement bit counter TEMP, skip when done goto P16cispcmmdoutloop ; Jump back and send next cmd bit nop ; Wait one cycle bcf PORTB,ISPDATA ; Clear DATA line bcf PORTB,ISPCLOCK ; Clear CLOCK line movlw DATISPIN ; Place tris value for data input into W tris PORTB ; set as input to avoid any contention nop ; Wait one cycle nop ; Wait one cycle retlw 0 ; Done - return! ; ******************************************************************** ; * programpartisp * ; * Main ISP programming loop. Reads data starting at STARTCALBYTE * ; * and calls programming subroutines to program and verify this * ; * data into the application PIC. * ; * RAM used: LOADDR, HIADDR, LODATA, HIDATA, FSR, LOBYTE, HIBYTE* ; ******************************************************************** programpartisp call testmodeisp ; Place PIC into test/program mode clrf FSR ; Point to bank 0 movf STARTCALBYTE,W ; Upper order address of data to be stored into W movwf HIADDR ; place into counter movf STARTCALBYTE+1,W ; Lower order address byte of data to be stored movwf LOADDR ; place into counter 2000 Microchip Technology Inc. AN656 0271 0272 0273 0273 0274 0275 0276 0277 0278 0279 027A 027B 027C 027D 027E 027E 027F 00E8 02A7 0280 0281 0282 0283 0284 0285 0286 0287 0288 0289 028A 028B 028C 028D 028E 028F 0290 0290 0291 0292 0293 0294 0295 0296 0297 0298 0299 029A 029B 029C 029D 029E 029F 02A0 02A1 02A2 02A3 02A4 02A4 02A5 02A6 02A7 02A8 02A9 02A9 02AA 02AA 02AB 0C10 008E 0024 06A4 05C4 04A4 0684 05A4 0584 0200 0028 0208 002A 0207 0029 006B 0C06 0952 02E8 0A73 02E7 0A73 0C03 008B 002F 0C12 002E 0C34 0027 05E3 09B1 02AB 0C19 008B 0643 0AA9 0209 0087 0743 0A90 020A 0088 0743 0A90 0040 01CB 01CB 01CB 002B 04E3 09B1 02EB 0AA4 0AAA 0446 0C06 0952 00534 00535 00536 00537 00538 00539 00540 00541 00542 00543 00544 00545 00546 00547 00548 00549 00550 00551 M M M M M M M M M 00552 00553 00554 00555 00556 00557 00558 00559 00560 00561 00562 00563 00564 00565 00566 00567 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 00580 00581 00582 00583 00584 00585 00586 00587 00588 00589 00590 decf LOADDR,F incf HIADDR,F programsetptr movlw CMDISPINCRADDR call commandisp decfsz LOADDR,F goto programsetptr decfsz HIADDR,F goto programsetptr movlw .3 subwf TIMEHIGH,W movwf BYTECOUNT movlw STARTCALBYTE+2 movwf ADDRPTR programisploop movlw UPPER6BITS movwf HIDATA addrtofsr ADDRPTR movlw STARTCALBYTE subwf ADDRPTR,w movwf FSR btfsc FSR,5 bsf FSR,6 bcf FSR,5 btfsc FSR,4 bsf FSR,5 bsf FSR,4 movf INDF,W movwf LODATA movf LODATA,W movwf LOBYTE movf HIDATA,W movwf HIBYTE clrf PULSECNT pgmispcntloop bsf STATUS,VFYYES call pgmvfyisp incf PULSECNT,F movlw .25 subwf PULSECNT,w btfsc STATUS,Z goto pgmispfail movf HIBYTE,w subwf HIDATA,w btfss STATUS,Z goto pgmispcntloop movf LOBYTE,w subwf LODATA,w btfss STATUS,Z goto pgmispcntloop clrw addwf PULSECNT,W addwf PULSECNT,W addwf PULSECNT,W movwf PULSECNT pgmisp3X bcf STATUS,VFYYES call pgmvfyisp decfsz PULSECNT,F goto pgmisp3X goto prgnextbyte pgmispfail bcf PORTB,DONELED prgnextbyte movlw CMDISPINCRADDR call commandisp 2000 Microchip Technology Inc. ; Subtract one from loop constant ; Add one for loop constant ; ; ; ; ; ; ; ; ; ; ; Increment address command load into W Send command to PIC Decrement lower address Go back again Decrement high address Go back again Place start pointer into W, offset address Restore byte count into W Place into byte counter Place start of REAL DATA address into W Update pointer ; ; ; ; ; ; ; retlw instruction opcode placed into W Set up upper bits of program word Set up FSR to point to next value Place base address into W Offset by STARTCALBYTE Place into FSR Shift bits 4,5 to 5,6 ; ; ; ; ; ; ; Place next cal param into W Move it out to LODATA Place LODATA into LOBYTE ; ; ; ; ; ; ; ; Set verify flag Program and verify this byte Increment pulse counter Place 25 count into W Subtract pulse count from 25 Skip if NOT 25 pulse counts Jump to program failed - only try 25 times Subtract programmed and read data Place HIDATA into HIBYTE Clear pulse counter ; Skip if programmed is OK ; Miscompare - program it again! ; Subtract programmed and read data ; ; ; ; Skip if programmed is OK Miscompare - program it again! Clear W reg now do 3 times overprogramming pulses ; Add 3X pulsecount to pulsecount ; ; ; ; ; Clear verify flag Program this byte Decrement pulse counter, skip when done Loop back and program again! Done - jump to program next byte! ; Failure - clear green LED! ; Increiment address command load into W ; Send command to PIC DS00656B-page 4-15 AN656 02AC 02AD 02AE 02AF 02B0 02B0 02B1 02B1 02B1 02B2 02B3 02B4 02B5 02B6 02B7 02B8 02B9 02BA 02BB 02BC 02BD 02BD 02BE 02BF 02C0 02C0 02C1 02C2 02C3 02C4 02C5 02C6 02C7 02C7 02C8 02C9 02CA 02AE 02EF 0A7E 0900 0AB0 0C02 0952 0000 0000 0000 0208 002A 0207 0029 0915 0C08 0952 0C20 0000 002D 02ED 0AC0 0C0E 0952 07E3 0800 0000 0C04 0952 092C 0800 00591 00592 00593 00594 00595 00596 00597 00598 00599 00600 00601 00602 00603 00604 00605 00606 00607 00608 00609 00610 00611 00612 00613 00614 00615 00616 00617 00618 00619 00620 00621 00622 00623 00624 00625 00626 00627 00628 00629 00630 00631 00632 00633 00634 00635 00636 00637 00638 DS00656B-page 4-16 incf decfsz goto call ADDRPTR,F BYTECOUNT,F programisploop poweroffisp ; ; ; ; Increment pointer to next address See if we sent last byte Jump back and send next byte Done - power off PIC and reset it! goto self ; Done with programming - wait here! self ; ******************************************************************* ; * pgmvfyisp * ; * Program and/or Veryify a word in program memory on the * ; * application PIC. The data to be programmed is in HIDATA and * ; * LODATA. * ; * RAM used: HIBYTE, LOBYTE, HIDATA, LODATA, TEMP * ; ******************************************************************* pgmvfyisp loadcisp movlw CMDISPLOAD ; Place load data command into W call commandisp ; Send load data command to PIC nop ; Wait one cycle nop ; Wait one cycle nop ; Wait one cycle movf LODATA,w ; Place LODATA byte into W movwf LOBYTE ; Move it to LOBYTE reg movf HIDATA,w ; Place HIDATA byte into W movwf HIBYTE ; Move it to HIBYTE reg call P16cispout ; Send data to PIC movlw CMDISPPGMSTART ; Place start programming command into W call commandisp ; Send start programming command to PIC delay100us movlw .32 ; Place 32 into W nop ; Wait one cycle movwf TEMP ; Move it to TEMP for delay counter loopprgm decfsz TEMP,F ; Decrement TEMP, skip when delay done goto loopprgm ; Jump back and loop delay movlw CMDISPPGMEND ; Place stop programming command into W call commandisp ; Send end programming command to PIC btfss STATUS,VFYYES ; Skip if we are supposed to verify this time retlw 0 ; Done - return! nop ; Wait one cycle readcisp movlw CMDISPREAD ; Place read data command into W call commandisp ; Send read data command to PIC call P16cispin ; Read programmed data retlw 0 ; Done - return! END 2000 Microchip Technology Inc. AN656 MEMORY USAGE MAP (`X' = Used, 0000 0040 0080 00C0 0200 0240 0280 02C0 07C0 0FC0 : : : : : : : : : : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXX---------XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXX----------------------------------- `-' = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------------------------------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------------------------------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ------------------------------X ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 2 reported, 2000 Microchip Technology Inc. 402 1646 0 suppressed 0 suppressed DS00656B-page 4-17 AN656 APPENDIX B: MPASM 01.40.01 Intermediate LOC OBJECT CODE VALUE 3-31-1997 10:55:57 PAGE 1 LINE SOURCE TEXT 00001 ; 00002 ; 00003 ; 00004 ; 00005 ; 00006 ; 00007 ; 00008 ; 00009 ; 00010 ; 00011 ; 00012 ; 00013 ; 00014 ; 00015 ; 00016 ; 00017 ; 00018 ; 00019 ; 00020 ; 00021 ; 00022 ; 00023 ; 00024 ; 00025 ; 00026 ; 00027 ; 00028 ; 00029 ; 00030 ; 00031 ; 00032 ; 00033 ; 00034 ; 00035 ; 00036 ; 00037 ; 00038 ; 00039 ; 00040 ; 00041 ; 00042 ; 00043 ; 00044 Warning[217]: Hex file 00045 00046 00001 00002 ; 00142 2007 3FF1 00047 00048 00049 ; 00050 ; 00051 ; 00052 ; 00053 00054 ; DS00656B-page 4-18 ISPTEST.ASM Filename: ISPTEST.ASM ********************************************** * Author: John Day * * Sr. Field Applications Engineer * * Microchip Technology * * Revision: 1.0 * * Date August 25, 1995 * * Part: PIC16CXX * * Compiled using MPASM V1.40 * ********************************************** * Include files: * * P16CXX.ASM * ********************************************** * Fuses: OSC: XT (4.0 Mhz xtal) * * WDT: OFF * * CP: OFF * * PWRTE: OFF * ************************************************************************** * This program is intended to be used as a code example to * * show how to comunicate with a manufacturing test jig that * * allows this PIC16CXX device to self program. The RB6 and RB7 * * lines of this PIC16CXX device are used to clock the data from * * this device to the test jig (running ISPPRGM.ASM). Once the * * PIC16C58 running ISPPRGM in the test jig receives the data, * * it places this device in test mode and programs these parameters. * * The code with comments "TEST -" is used to create some fakecalibration * * parameters that are first written to addresses STARTCALBYTE through * * ENDCALBYTE and later used to call the self-programming algorithm. * * Replace this code with your parameter calculation procedure, * * placing each parameter into the STARTCALBYTE to ENDCALBYTE * * file register addresses (16 are used in this example). The address * * "lookuptable" is used by the main code later on for the final lookup * * table of calibration constants. 16 words are reserved for this lookup * * table. * ************************************************************************** * Program Memory: * * 49 Words - communication with test jig * * 17 Words - calibration look-up table (16 bytes of data) * * 13 Words - Test Code to generate Calibration Constants * * RAM Memory: * * 16 Bytes -Temporary- Store 16 bytes of calibration constant* * 4 Bytes -Temporary- Store 4 bytes of temp variables * ************************************************************************** format specified on command line. list p=16C71,f=inhx8m include <p16C71.inc> LIST P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc. LIST __CONFIG _CP_OFF&_WDT_OFF&_XT_OSC&_PWRTE_OFF ************************************ * Port A (RA0-RA4) bit definitions * ************************************ Port A is not used in this test program ************************************ 2000 Microchip Technology Inc. AN656 0000000C 0000000D 0000000E 0000000F 00000010 0000002F 00000020 0000 0000 0000 0001 0002 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000E 3010 0084 0804 0080 0A84 0804 3C30 1D03 2802 0103 200F 3CFF 1903 2830 280E 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 ; * Port B (RB0-RB7) bit definitions * ; ************************************ #define CLOCK 6 ; clock line for ISP #define DATA 7 ; data line for ISP ; Port pins RB0-5 are not used in this test program ; ************************************ ; * RAM register usage definition * ; ************************************ CSUMTOTAL EQU 0Ch ; Address for checksum var COUNT EQU 0Dh ; Address for COUNT var DATAREG EQU 0Eh ; Address for Data output register var COUNTDLY EQU 0Fh ; Address for clock delay counter ; ; ; ; ; These two symbols are used for the start and end address in RAM where the calibration bytes are stored. There are 16 bytes to be stored in this example; however, you can increase or decrease the number of bytes by changing the STARTCALBYTE or ENDCALBYTE address values. STARTCALBYTE ENDCALBYTE EQU 10h EQU 2Fh ; Address pointer for start CAL byte ; Address pointer for end CAL byte ; Table length of lookup table (number of CAL parameters to be stored) CALTABLELENGTH EQU ENDCALBYTE - STARTCALBYTE + 1 ORG 0 ; ****************************************************************** ; * testcode routine * ; * TEST code - sets up RAM register with register address as data * ; * Uses file register STARTCALBYTE through ENDCALBYTE to store the* ; * calibration values that are to be programmed into the lookup * ; * table by the test jig running ISPPRGM. * ; * Customer would place calibration code here and make sure that * ; * calibration constants start at address STARTCALBYTE * ; ****************************************************************** testcode movlw STARTCALBYTE ; TEST movwf FSR ; TEST - Init FSR with start of RAM addres looptestram movf FSR,W ; TEST - Place address into W movwf INDF ; TEST - Place address into RAM data byte incf FSR,F ; TEST - Move to next address movf FSR,W ; TEST - Place current address into W sublw ENDCALBYTE+1 ; TEST - Subtract from end of RAM btfss STATUS,Z ; TEST - Skip if at END of ram goto looptestram ; TEST - Jump back and init next RAM byte clrw ; TEST - Clear W call lookuptable ; TEST - Get first CAL value from lookup table sublw 0FFh ; TEST - Check if lookup CAL table is blank btfsc STATUS,Z ; TEST - Skip if table is NOT blank goto calsend ; TEST - Table blank - send out cal parameters mainloop goto mainloop ; TEST - Jump back to self since CAL is done ; ; ; ; ; ; ; ; ****************************************************************** * lookuptable * * Calibration constants look-up table. This is where the CAL * * Constants will be stored via ISP protocol later. Note it is * * blank, since these values will be pogrammed by the test jig * * running ISPPRGM later. * * Input Variable: W stores index for table lookup * * Output Variable: W returns with the calibration constant * 2000 Microchip Technology Inc. DS00656B-page 4-19 AN656 00119 ; * NOTE: Blank table when programmed reads "FF" for all locations * 00120 ; ****************************************************************** 000F 00121 lookuptable 000F 0782 00122 addwf PCL,F ; Place the calibration constant table here! 00123 002F 00124 ORG lookuptable + CALTABLELENGTH 002F 34FF 00125 retlw 0FFh ; Return FF at last location for a blank table 00126 00127 ; ****************************************************************** 00128 ; * calsend subroutine * 00129 ; * Send the calibration data stored in locations STARTCALBYTE * 00130 ; * through ENDCALBYTE in RAM to the programming jig using a serial* 00131 ; * clock and data protocol * 00132 ; * Input Variables: STARTCALBYTE through ENDCALBYTE * 00133 ; ****************************************************************** 0030 00134 calsend 0030 018C 00135 clrf CSUMTOTAL ; Clear CSUMTOTAL reg for delay counter 0031 018D 00136 clrf COUNT ; Clear COUNT reg to delay counter 0032 00137 delayloop ; Delay for 100 mS to wait for prog jig wakeup 0032 0B8D 00138 decfsz COUNT,F ; Decrement COUNT and skip when zero 0033 2832 00139 goto delayloop ; Go back and delay again 0034 0B8C 00140 decfsz CSUMTOTAL,F ; Decrement CSUMTOTAL and skip when zero 0035 2832 00141 goto delayloop ; Go back and delay again 0036 0186 00142 clrf PORTB ; Place "0" into port b latch register 0037 1683 00143 bsf STATUS,RP0 ; Switch to bank 1 0038 303F 00144 movlw b'00111111' ; RB6,7 set to outputs Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct. 0039 0086 00145 movwf TRISB ; Move to TRIS registers 003A 1283 00146 bcf STATUS,RP0 ; Switch to bank 0 003B 018C 00147 clrf CSUMTOTAL ; Clear checksum total byte 003C 3001 00148 movlw high lookuptable+1 ; place MSB of first addr of cal table into W 003D 204D 00149 call sendcalbyte ; Send the high address out 003E 3010 00150 movlw low lookuptable+1 ; place LSB of first addr of cal table into W 003F 204D 00151 call sendcalbyte ; Send low address out 0040 3010 00152 movlw STARTCALBYTE ; Place RAM start address of first cal byte 0041 0084 00153 movwf FSR ; Place this into FSR 0042 00154 loopcal 0042 0800 00155 movf INDF,W ; Place data into W 0043 204D 00156 call sendcalbyte ; Send the byte out 0044 0A84 00157 incf FSR,F ; Move to the next cal byte 0045 0804 00158 movf FSR,W ; Place byte address into W 0046 3C30 00159 sublw ENDCALBYTE+1 ; Set Z bit if we are at the end of CAL data 0047 1D03 00160 btfss STATUS,Z ; Skip if we are done 0048 2842 00161 goto loopcal ; Go back for next byte 0049 080C 00162 movf CSUMTOTAL,W ; place checksum total into W 004A 204D 00163 call sendcalbyte ; Send the checksum out 004B 0186 00164 clrf PORTB ; clear out port pins 004C 00165 calsenddone 004C 284C 00166 goto calsenddone ; We are done - go home! 00167 00168 ; ****************************************************************** 00169 ; * sendcalbyte subroutine * 00170 ; * Send one byte of calibration data to the programming jig * 00171 ; * Input Variable: W contains the byte to be sent * 00172 ; ****************************************************************** 004D 00173 sendcalbyte 004D 008E 00174 movwf DATAREG ; Place send byte into data register 004E 078C 00175 addwf CSUMTOTAL,F ; Update checksum total 004F 3008 00176 movlw .8 ; Place 8 into W 0050 008D 00177 movwf COUNT ; set up counter register 0051 00178 loopsendcal 0051 1706 00179 bsf PORTB,CLOCK ; Set clock line high 0052 205C 00180 call delaysend ; Wait for test jig to synch up 0053 0D8E 00181 rlf DATAREG,F ; Rotate to next bit 0054 1786 00182 bsf PORTB,DATA ; Assume data bit is high 0055 1C03 00183 btfss STATUS,C ; Skip if the data bit was high DS00656B-page 4-20 2000 Microchip Technology Inc. AN656 0056 0057 0058 0059 005A 005B 005C 005C 005D 005E 005E 005F 0060 1386 1306 205C 0B8D 2851 0008 3010 008F 0B8F 285E 0008 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 bcf bcf call decfsz goto return PORTB,DATA PORTB,CLOCK delaysend COUNT,F loopsendcal ; ; ; ; ; ; Set data bit to low Clear clock bit to clock data out Wait for test jig to synch up Skip after 8 bits Jump back and send next bit We are done with this byte so return! ; ****************************************************************** ; * delaysend subroutine * ; * Delay for 50 ms to wait for the programming jig to synch up * ; ****************************************************************** delaysend movlw 10h ; Delay for 16 loops movwf COUNTDLY ; Use COUNTDLY as delay count variable loopdelaysend decfsz COUNTDLY,F ; Decrement COUNTDLY and skip when done goto loopdelaysend ; Jump back for more delay return END MEMORY USAGE MAP (`X' = Used, `-' = Unused) 0000 : XXXXXXXXXXXXXXXX ---------------- ---------------X XXXXXXXXXXXXXXXX 0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX X--------------- ---------------2000 : -------X-------- ---------------- ---------------- ---------------All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 1 reported, 1 reported, 2000 Microchip Technology Inc. 66 958 0 suppressed 0 suppressed DS00656B-page 4-21 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing, 100027, P.R.C. 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(c) 2000 Microchip Technology Incorporated. Printed in the USA. 5/00 Italy United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 03/23/00 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30277C-page 4-22 2000 Microchip Technology Inc.